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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
41 | #include <linux/sched.h> | |
42 | #include <rdma/ib_user_verbs.h> | |
3f89a643 | 43 | #include <rdma/ib_addr.h> |
2811ba51 | 44 | #include <rdma/ib_cache.h> |
1b5daf11 | 45 | #include <linux/mlx5/vport.h> |
e126ba97 EC |
46 | #include <rdma/ib_smi.h> |
47 | #include <rdma/ib_umem.h> | |
038d2ef8 MG |
48 | #include <linux/in.h> |
49 | #include <linux/etherdevice.h> | |
50 | #include <linux/mlx5/fs.h> | |
e126ba97 EC |
51 | #include "user.h" |
52 | #include "mlx5_ib.h" | |
53 | ||
54 | #define DRIVER_NAME "mlx5_ib" | |
169a1d85 AV |
55 | #define DRIVER_VERSION "2.2-1" |
56 | #define DRIVER_RELDATE "Feb 2014" | |
e126ba97 EC |
57 | |
58 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); | |
59 | MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); | |
60 | MODULE_LICENSE("Dual BSD/GPL"); | |
61 | MODULE_VERSION(DRIVER_VERSION); | |
62 | ||
9603b61d JM |
63 | static int deprecated_prof_sel = 2; |
64 | module_param_named(prof_sel, deprecated_prof_sel, int, 0444); | |
65 | MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core"); | |
e126ba97 EC |
66 | |
67 | static char mlx5_version[] = | |
68 | DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v" | |
69 | DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; | |
70 | ||
da7525d2 EBE |
71 | enum { |
72 | MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, | |
73 | }; | |
74 | ||
1b5daf11 | 75 | static enum rdma_link_layer |
ebd61f68 | 76 | mlx5_port_type_cap_to_rdma_ll(int port_type_cap) |
1b5daf11 | 77 | { |
ebd61f68 | 78 | switch (port_type_cap) { |
1b5daf11 MD |
79 | case MLX5_CAP_PORT_TYPE_IB: |
80 | return IB_LINK_LAYER_INFINIBAND; | |
81 | case MLX5_CAP_PORT_TYPE_ETH: | |
82 | return IB_LINK_LAYER_ETHERNET; | |
83 | default: | |
84 | return IB_LINK_LAYER_UNSPECIFIED; | |
85 | } | |
86 | } | |
87 | ||
ebd61f68 AS |
88 | static enum rdma_link_layer |
89 | mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) | |
90 | { | |
91 | struct mlx5_ib_dev *dev = to_mdev(device); | |
92 | int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); | |
93 | ||
94 | return mlx5_port_type_cap_to_rdma_ll(port_type_cap); | |
95 | } | |
96 | ||
fc24fc5e AS |
97 | static int mlx5_netdev_event(struct notifier_block *this, |
98 | unsigned long event, void *ptr) | |
99 | { | |
100 | struct net_device *ndev = netdev_notifier_info_to_dev(ptr); | |
101 | struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, | |
102 | roce.nb); | |
103 | ||
104 | if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER)) | |
105 | return NOTIFY_DONE; | |
106 | ||
107 | write_lock(&ibdev->roce.netdev_lock); | |
108 | if (ndev->dev.parent == &ibdev->mdev->pdev->dev) | |
109 | ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev; | |
110 | write_unlock(&ibdev->roce.netdev_lock); | |
111 | ||
112 | return NOTIFY_DONE; | |
113 | } | |
114 | ||
115 | static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, | |
116 | u8 port_num) | |
117 | { | |
118 | struct mlx5_ib_dev *ibdev = to_mdev(device); | |
119 | struct net_device *ndev; | |
120 | ||
121 | /* Ensure ndev does not disappear before we invoke dev_hold() | |
122 | */ | |
123 | read_lock(&ibdev->roce.netdev_lock); | |
124 | ndev = ibdev->roce.netdev; | |
125 | if (ndev) | |
126 | dev_hold(ndev); | |
127 | read_unlock(&ibdev->roce.netdev_lock); | |
128 | ||
129 | return ndev; | |
130 | } | |
131 | ||
3f89a643 AS |
132 | static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, |
133 | struct ib_port_attr *props) | |
134 | { | |
135 | struct mlx5_ib_dev *dev = to_mdev(device); | |
136 | struct net_device *ndev; | |
137 | enum ib_mtu ndev_ib_mtu; | |
c876a1b7 | 138 | u16 qkey_viol_cntr; |
3f89a643 AS |
139 | |
140 | memset(props, 0, sizeof(*props)); | |
141 | ||
142 | props->port_cap_flags |= IB_PORT_CM_SUP; | |
143 | props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; | |
144 | ||
145 | props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, | |
146 | roce_address_table_size); | |
147 | props->max_mtu = IB_MTU_4096; | |
148 | props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); | |
149 | props->pkey_tbl_len = 1; | |
150 | props->state = IB_PORT_DOWN; | |
151 | props->phys_state = 3; | |
152 | ||
c876a1b7 LR |
153 | mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); |
154 | props->qkey_viol_cntr = qkey_viol_cntr; | |
3f89a643 AS |
155 | |
156 | ndev = mlx5_ib_get_netdev(device, port_num); | |
157 | if (!ndev) | |
158 | return 0; | |
159 | ||
160 | if (netif_running(ndev) && netif_carrier_ok(ndev)) { | |
161 | props->state = IB_PORT_ACTIVE; | |
162 | props->phys_state = 5; | |
163 | } | |
164 | ||
165 | ndev_ib_mtu = iboe_get_mtu(ndev->mtu); | |
166 | ||
167 | dev_put(ndev); | |
168 | ||
169 | props->active_mtu = min(props->max_mtu, ndev_ib_mtu); | |
170 | ||
171 | props->active_width = IB_WIDTH_4X; /* TODO */ | |
172 | props->active_speed = IB_SPEED_QDR; /* TODO */ | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
3cca2606 AS |
177 | static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, |
178 | const struct ib_gid_attr *attr, | |
179 | void *mlx5_addr) | |
180 | { | |
181 | #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) | |
182 | char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, | |
183 | source_l3_address); | |
184 | void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, | |
185 | source_mac_47_32); | |
186 | ||
187 | if (!gid) | |
188 | return; | |
189 | ||
190 | ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr); | |
191 | ||
192 | if (is_vlan_dev(attr->ndev)) { | |
193 | MLX5_SET_RA(mlx5_addr, vlan_valid, 1); | |
194 | MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev)); | |
195 | } | |
196 | ||
197 | switch (attr->gid_type) { | |
198 | case IB_GID_TYPE_IB: | |
199 | MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); | |
200 | break; | |
201 | case IB_GID_TYPE_ROCE_UDP_ENCAP: | |
202 | MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); | |
203 | break; | |
204 | ||
205 | default: | |
206 | WARN_ON(true); | |
207 | } | |
208 | ||
209 | if (attr->gid_type != IB_GID_TYPE_IB) { | |
210 | if (ipv6_addr_v4mapped((void *)gid)) | |
211 | MLX5_SET_RA(mlx5_addr, roce_l3_type, | |
212 | MLX5_ROCE_L3_TYPE_IPV4); | |
213 | else | |
214 | MLX5_SET_RA(mlx5_addr, roce_l3_type, | |
215 | MLX5_ROCE_L3_TYPE_IPV6); | |
216 | } | |
217 | ||
218 | if ((attr->gid_type == IB_GID_TYPE_IB) || | |
219 | !ipv6_addr_v4mapped((void *)gid)) | |
220 | memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); | |
221 | else | |
222 | memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); | |
223 | } | |
224 | ||
225 | static int set_roce_addr(struct ib_device *device, u8 port_num, | |
226 | unsigned int index, | |
227 | const union ib_gid *gid, | |
228 | const struct ib_gid_attr *attr) | |
229 | { | |
230 | struct mlx5_ib_dev *dev = to_mdev(device); | |
231 | u32 in[MLX5_ST_SZ_DW(set_roce_address_in)]; | |
232 | u32 out[MLX5_ST_SZ_DW(set_roce_address_out)]; | |
233 | void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); | |
234 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); | |
235 | ||
236 | if (ll != IB_LINK_LAYER_ETHERNET) | |
237 | return -EINVAL; | |
238 | ||
239 | memset(in, 0, sizeof(in)); | |
240 | ||
241 | ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); | |
242 | ||
243 | MLX5_SET(set_roce_address_in, in, roce_address_index, index); | |
244 | MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); | |
245 | ||
246 | memset(out, 0, sizeof(out)); | |
247 | return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); | |
248 | } | |
249 | ||
250 | static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, | |
251 | unsigned int index, const union ib_gid *gid, | |
252 | const struct ib_gid_attr *attr, | |
253 | __always_unused void **context) | |
254 | { | |
255 | return set_roce_addr(device, port_num, index, gid, attr); | |
256 | } | |
257 | ||
258 | static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, | |
259 | unsigned int index, __always_unused void **context) | |
260 | { | |
261 | return set_roce_addr(device, port_num, index, NULL, NULL); | |
262 | } | |
263 | ||
2811ba51 AS |
264 | __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, |
265 | int index) | |
266 | { | |
267 | struct ib_gid_attr attr; | |
268 | union ib_gid gid; | |
269 | ||
270 | if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) | |
271 | return 0; | |
272 | ||
273 | if (!attr.ndev) | |
274 | return 0; | |
275 | ||
276 | dev_put(attr.ndev); | |
277 | ||
278 | if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) | |
279 | return 0; | |
280 | ||
281 | return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); | |
282 | } | |
283 | ||
1b5daf11 MD |
284 | static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) |
285 | { | |
286 | return !dev->mdev->issi; | |
287 | } | |
288 | ||
289 | enum { | |
290 | MLX5_VPORT_ACCESS_METHOD_MAD, | |
291 | MLX5_VPORT_ACCESS_METHOD_HCA, | |
292 | MLX5_VPORT_ACCESS_METHOD_NIC, | |
293 | }; | |
294 | ||
295 | static int mlx5_get_vport_access_method(struct ib_device *ibdev) | |
296 | { | |
297 | if (mlx5_use_mad_ifc(to_mdev(ibdev))) | |
298 | return MLX5_VPORT_ACCESS_METHOD_MAD; | |
299 | ||
ebd61f68 | 300 | if (mlx5_ib_port_link_layer(ibdev, 1) == |
1b5daf11 MD |
301 | IB_LINK_LAYER_ETHERNET) |
302 | return MLX5_VPORT_ACCESS_METHOD_NIC; | |
303 | ||
304 | return MLX5_VPORT_ACCESS_METHOD_HCA; | |
305 | } | |
306 | ||
da7525d2 EBE |
307 | static void get_atomic_caps(struct mlx5_ib_dev *dev, |
308 | struct ib_device_attr *props) | |
309 | { | |
310 | u8 tmp; | |
311 | u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); | |
312 | u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); | |
313 | u8 atomic_req_8B_endianness_mode = | |
314 | MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); | |
315 | ||
316 | /* Check if HW supports 8 bytes standard atomic operations and capable | |
317 | * of host endianness respond | |
318 | */ | |
319 | tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; | |
320 | if (((atomic_operations & tmp) == tmp) && | |
321 | (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && | |
322 | (atomic_req_8B_endianness_mode)) { | |
323 | props->atomic_cap = IB_ATOMIC_HCA; | |
324 | } else { | |
325 | props->atomic_cap = IB_ATOMIC_NONE; | |
326 | } | |
327 | } | |
328 | ||
1b5daf11 MD |
329 | static int mlx5_query_system_image_guid(struct ib_device *ibdev, |
330 | __be64 *sys_image_guid) | |
331 | { | |
332 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
333 | struct mlx5_core_dev *mdev = dev->mdev; | |
334 | u64 tmp; | |
335 | int err; | |
336 | ||
337 | switch (mlx5_get_vport_access_method(ibdev)) { | |
338 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
339 | return mlx5_query_mad_ifc_system_image_guid(ibdev, | |
340 | sys_image_guid); | |
341 | ||
342 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
343 | err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); | |
3f89a643 AS |
344 | break; |
345 | ||
346 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
347 | err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); | |
348 | break; | |
1b5daf11 MD |
349 | |
350 | default: | |
351 | return -EINVAL; | |
352 | } | |
3f89a643 AS |
353 | |
354 | if (!err) | |
355 | *sys_image_guid = cpu_to_be64(tmp); | |
356 | ||
357 | return err; | |
358 | ||
1b5daf11 MD |
359 | } |
360 | ||
361 | static int mlx5_query_max_pkeys(struct ib_device *ibdev, | |
362 | u16 *max_pkeys) | |
363 | { | |
364 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
365 | struct mlx5_core_dev *mdev = dev->mdev; | |
366 | ||
367 | switch (mlx5_get_vport_access_method(ibdev)) { | |
368 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
369 | return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); | |
370 | ||
371 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
372 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
373 | *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, | |
374 | pkey_table_size)); | |
375 | return 0; | |
376 | ||
377 | default: | |
378 | return -EINVAL; | |
379 | } | |
380 | } | |
381 | ||
382 | static int mlx5_query_vendor_id(struct ib_device *ibdev, | |
383 | u32 *vendor_id) | |
384 | { | |
385 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
386 | ||
387 | switch (mlx5_get_vport_access_method(ibdev)) { | |
388 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
389 | return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); | |
390 | ||
391 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
392 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
393 | return mlx5_core_query_vendor_id(dev->mdev, vendor_id); | |
394 | ||
395 | default: | |
396 | return -EINVAL; | |
397 | } | |
398 | } | |
399 | ||
400 | static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, | |
401 | __be64 *node_guid) | |
402 | { | |
403 | u64 tmp; | |
404 | int err; | |
405 | ||
406 | switch (mlx5_get_vport_access_method(&dev->ib_dev)) { | |
407 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
408 | return mlx5_query_mad_ifc_node_guid(dev, node_guid); | |
409 | ||
410 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
411 | err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); | |
3f89a643 AS |
412 | break; |
413 | ||
414 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
415 | err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); | |
416 | break; | |
1b5daf11 MD |
417 | |
418 | default: | |
419 | return -EINVAL; | |
420 | } | |
3f89a643 AS |
421 | |
422 | if (!err) | |
423 | *node_guid = cpu_to_be64(tmp); | |
424 | ||
425 | return err; | |
1b5daf11 MD |
426 | } |
427 | ||
428 | struct mlx5_reg_node_desc { | |
429 | u8 desc[64]; | |
430 | }; | |
431 | ||
432 | static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) | |
433 | { | |
434 | struct mlx5_reg_node_desc in; | |
435 | ||
436 | if (mlx5_use_mad_ifc(dev)) | |
437 | return mlx5_query_mad_ifc_node_desc(dev, node_desc); | |
438 | ||
439 | memset(&in, 0, sizeof(in)); | |
440 | ||
441 | return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, | |
442 | sizeof(struct mlx5_reg_node_desc), | |
443 | MLX5_REG_NODE_DESC, 0, 0); | |
444 | } | |
445 | ||
e126ba97 | 446 | static int mlx5_ib_query_device(struct ib_device *ibdev, |
2528e33e MB |
447 | struct ib_device_attr *props, |
448 | struct ib_udata *uhw) | |
e126ba97 EC |
449 | { |
450 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
938fe83c | 451 | struct mlx5_core_dev *mdev = dev->mdev; |
e126ba97 EC |
452 | int err = -ENOMEM; |
453 | int max_rq_sg; | |
454 | int max_sq_sg; | |
e0238a6a | 455 | u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); |
e126ba97 | 456 | |
2528e33e MB |
457 | if (uhw->inlen || uhw->outlen) |
458 | return -EINVAL; | |
459 | ||
1b5daf11 MD |
460 | memset(props, 0, sizeof(*props)); |
461 | err = mlx5_query_system_image_guid(ibdev, | |
462 | &props->sys_image_guid); | |
463 | if (err) | |
464 | return err; | |
e126ba97 | 465 | |
1b5daf11 | 466 | err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); |
e126ba97 | 467 | if (err) |
1b5daf11 | 468 | return err; |
e126ba97 | 469 | |
1b5daf11 MD |
470 | err = mlx5_query_vendor_id(ibdev, &props->vendor_id); |
471 | if (err) | |
472 | return err; | |
e126ba97 | 473 | |
9603b61d JM |
474 | props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | |
475 | (fw_rev_min(dev->mdev) << 16) | | |
476 | fw_rev_sub(dev->mdev); | |
e126ba97 EC |
477 | props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | |
478 | IB_DEVICE_PORT_ACTIVE_EVENT | | |
479 | IB_DEVICE_SYS_IMAGE_GUID | | |
1a4c3a3d | 480 | IB_DEVICE_RC_RNR_NAK_GEN; |
938fe83c SM |
481 | |
482 | if (MLX5_CAP_GEN(mdev, pkv)) | |
e126ba97 | 483 | props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; |
938fe83c | 484 | if (MLX5_CAP_GEN(mdev, qkv)) |
e126ba97 | 485 | props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; |
938fe83c | 486 | if (MLX5_CAP_GEN(mdev, apm)) |
e126ba97 | 487 | props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; |
938fe83c | 488 | if (MLX5_CAP_GEN(mdev, xrc)) |
e126ba97 EC |
489 | props->device_cap_flags |= IB_DEVICE_XRC; |
490 | props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; | |
938fe83c | 491 | if (MLX5_CAP_GEN(mdev, sho)) { |
2dea9094 SG |
492 | props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; |
493 | /* At this stage no support for signature handover */ | |
494 | props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | | |
495 | IB_PROT_T10DIF_TYPE_2 | | |
496 | IB_PROT_T10DIF_TYPE_3; | |
497 | props->sig_guard_cap = IB_GUARD_T10DIF_CRC | | |
498 | IB_GUARD_T10DIF_CSUM; | |
499 | } | |
938fe83c | 500 | if (MLX5_CAP_GEN(mdev, block_lb_mc)) |
f360d88a | 501 | props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; |
e126ba97 | 502 | |
88115fe7 BW |
503 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && |
504 | (MLX5_CAP_ETH(dev->mdev, csum_cap))) | |
505 | props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; | |
506 | ||
1b5daf11 MD |
507 | props->vendor_part_id = mdev->pdev->device; |
508 | props->hw_ver = mdev->pdev->revision; | |
e126ba97 EC |
509 | |
510 | props->max_mr_size = ~0ull; | |
e0238a6a | 511 | props->page_size_cap = ~(min_page_size - 1); |
938fe83c SM |
512 | props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); |
513 | props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); | |
514 | max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / | |
515 | sizeof(struct mlx5_wqe_data_seg); | |
516 | max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - | |
517 | sizeof(struct mlx5_wqe_ctrl_seg)) / | |
518 | sizeof(struct mlx5_wqe_data_seg); | |
e126ba97 | 519 | props->max_sge = min(max_rq_sg, max_sq_sg); |
18ebd407 | 520 | props->max_sge_rd = props->max_sge; |
938fe83c | 521 | props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); |
9f177686 | 522 | props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; |
938fe83c SM |
523 | props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); |
524 | props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); | |
525 | props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); | |
526 | props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); | |
527 | props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); | |
528 | props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; | |
529 | props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); | |
e126ba97 | 530 | props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; |
e126ba97 EC |
531 | props->max_srq_sge = max_rq_sg - 1; |
532 | props->max_fast_reg_page_list_len = (unsigned int)-1; | |
da7525d2 | 533 | get_atomic_caps(dev, props); |
81bea28f | 534 | props->masked_atomic_cap = IB_ATOMIC_NONE; |
938fe83c SM |
535 | props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); |
536 | props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); | |
e126ba97 EC |
537 | props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * |
538 | props->max_mcast_grp; | |
539 | props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ | |
7c60bcbb MB |
540 | props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); |
541 | props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; | |
e126ba97 | 542 | |
8cdd312c | 543 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
938fe83c | 544 | if (MLX5_CAP_GEN(mdev, pg)) |
8cdd312c HE |
545 | props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; |
546 | props->odp_caps = dev->odp_caps; | |
547 | #endif | |
548 | ||
051f2630 LR |
549 | if (MLX5_CAP_GEN(mdev, cd)) |
550 | props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; | |
551 | ||
1b5daf11 | 552 | return 0; |
e126ba97 EC |
553 | } |
554 | ||
1b5daf11 MD |
555 | enum mlx5_ib_width { |
556 | MLX5_IB_WIDTH_1X = 1 << 0, | |
557 | MLX5_IB_WIDTH_2X = 1 << 1, | |
558 | MLX5_IB_WIDTH_4X = 1 << 2, | |
559 | MLX5_IB_WIDTH_8X = 1 << 3, | |
560 | MLX5_IB_WIDTH_12X = 1 << 4 | |
561 | }; | |
562 | ||
563 | static int translate_active_width(struct ib_device *ibdev, u8 active_width, | |
564 | u8 *ib_width) | |
e126ba97 EC |
565 | { |
566 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
1b5daf11 MD |
567 | int err = 0; |
568 | ||
569 | if (active_width & MLX5_IB_WIDTH_1X) { | |
570 | *ib_width = IB_WIDTH_1X; | |
571 | } else if (active_width & MLX5_IB_WIDTH_2X) { | |
572 | mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", | |
573 | (int)active_width); | |
574 | err = -EINVAL; | |
575 | } else if (active_width & MLX5_IB_WIDTH_4X) { | |
576 | *ib_width = IB_WIDTH_4X; | |
577 | } else if (active_width & MLX5_IB_WIDTH_8X) { | |
578 | *ib_width = IB_WIDTH_8X; | |
579 | } else if (active_width & MLX5_IB_WIDTH_12X) { | |
580 | *ib_width = IB_WIDTH_12X; | |
581 | } else { | |
582 | mlx5_ib_dbg(dev, "Invalid active_width %d\n", | |
583 | (int)active_width); | |
584 | err = -EINVAL; | |
e126ba97 EC |
585 | } |
586 | ||
1b5daf11 MD |
587 | return err; |
588 | } | |
e126ba97 | 589 | |
1b5daf11 MD |
590 | static int mlx5_mtu_to_ib_mtu(int mtu) |
591 | { | |
592 | switch (mtu) { | |
593 | case 256: return 1; | |
594 | case 512: return 2; | |
595 | case 1024: return 3; | |
596 | case 2048: return 4; | |
597 | case 4096: return 5; | |
598 | default: | |
599 | pr_warn("invalid mtu\n"); | |
600 | return -1; | |
e126ba97 | 601 | } |
1b5daf11 | 602 | } |
e126ba97 | 603 | |
1b5daf11 MD |
604 | enum ib_max_vl_num { |
605 | __IB_MAX_VL_0 = 1, | |
606 | __IB_MAX_VL_0_1 = 2, | |
607 | __IB_MAX_VL_0_3 = 3, | |
608 | __IB_MAX_VL_0_7 = 4, | |
609 | __IB_MAX_VL_0_14 = 5, | |
610 | }; | |
e126ba97 | 611 | |
1b5daf11 MD |
612 | enum mlx5_vl_hw_cap { |
613 | MLX5_VL_HW_0 = 1, | |
614 | MLX5_VL_HW_0_1 = 2, | |
615 | MLX5_VL_HW_0_2 = 3, | |
616 | MLX5_VL_HW_0_3 = 4, | |
617 | MLX5_VL_HW_0_4 = 5, | |
618 | MLX5_VL_HW_0_5 = 6, | |
619 | MLX5_VL_HW_0_6 = 7, | |
620 | MLX5_VL_HW_0_7 = 8, | |
621 | MLX5_VL_HW_0_14 = 15 | |
622 | }; | |
e126ba97 | 623 | |
1b5daf11 MD |
624 | static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, |
625 | u8 *max_vl_num) | |
626 | { | |
627 | switch (vl_hw_cap) { | |
628 | case MLX5_VL_HW_0: | |
629 | *max_vl_num = __IB_MAX_VL_0; | |
630 | break; | |
631 | case MLX5_VL_HW_0_1: | |
632 | *max_vl_num = __IB_MAX_VL_0_1; | |
633 | break; | |
634 | case MLX5_VL_HW_0_3: | |
635 | *max_vl_num = __IB_MAX_VL_0_3; | |
636 | break; | |
637 | case MLX5_VL_HW_0_7: | |
638 | *max_vl_num = __IB_MAX_VL_0_7; | |
639 | break; | |
640 | case MLX5_VL_HW_0_14: | |
641 | *max_vl_num = __IB_MAX_VL_0_14; | |
642 | break; | |
e126ba97 | 643 | |
1b5daf11 MD |
644 | default: |
645 | return -EINVAL; | |
e126ba97 | 646 | } |
e126ba97 | 647 | |
1b5daf11 | 648 | return 0; |
e126ba97 EC |
649 | } |
650 | ||
1b5daf11 MD |
651 | static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, |
652 | struct ib_port_attr *props) | |
e126ba97 | 653 | { |
1b5daf11 MD |
654 | struct mlx5_ib_dev *dev = to_mdev(ibdev); |
655 | struct mlx5_core_dev *mdev = dev->mdev; | |
656 | struct mlx5_hca_vport_context *rep; | |
657 | int max_mtu; | |
658 | int oper_mtu; | |
659 | int err; | |
660 | u8 ib_link_width_oper; | |
661 | u8 vl_hw_cap; | |
e126ba97 | 662 | |
1b5daf11 MD |
663 | rep = kzalloc(sizeof(*rep), GFP_KERNEL); |
664 | if (!rep) { | |
665 | err = -ENOMEM; | |
e126ba97 | 666 | goto out; |
e126ba97 | 667 | } |
e126ba97 | 668 | |
1b5daf11 | 669 | memset(props, 0, sizeof(*props)); |
e126ba97 | 670 | |
1b5daf11 | 671 | err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); |
e126ba97 EC |
672 | if (err) |
673 | goto out; | |
674 | ||
1b5daf11 MD |
675 | props->lid = rep->lid; |
676 | props->lmc = rep->lmc; | |
677 | props->sm_lid = rep->sm_lid; | |
678 | props->sm_sl = rep->sm_sl; | |
679 | props->state = rep->vport_state; | |
680 | props->phys_state = rep->port_physical_state; | |
681 | props->port_cap_flags = rep->cap_mask1; | |
682 | props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); | |
683 | props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); | |
684 | props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); | |
685 | props->bad_pkey_cntr = rep->pkey_violation_counter; | |
686 | props->qkey_viol_cntr = rep->qkey_violation_counter; | |
687 | props->subnet_timeout = rep->subnet_timeout; | |
688 | props->init_type_reply = rep->init_type_reply; | |
e126ba97 | 689 | |
1b5daf11 MD |
690 | err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port); |
691 | if (err) | |
e126ba97 | 692 | goto out; |
e126ba97 | 693 | |
1b5daf11 MD |
694 | err = translate_active_width(ibdev, ib_link_width_oper, |
695 | &props->active_width); | |
696 | if (err) | |
697 | goto out; | |
698 | err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB, | |
699 | port); | |
e126ba97 EC |
700 | if (err) |
701 | goto out; | |
702 | ||
facc9699 | 703 | mlx5_query_port_max_mtu(mdev, &max_mtu, port); |
e126ba97 | 704 | |
1b5daf11 | 705 | props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); |
e126ba97 | 706 | |
facc9699 | 707 | mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); |
e126ba97 | 708 | |
1b5daf11 | 709 | props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); |
e126ba97 | 710 | |
1b5daf11 MD |
711 | err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); |
712 | if (err) | |
713 | goto out; | |
e126ba97 | 714 | |
1b5daf11 MD |
715 | err = translate_max_vl_num(ibdev, vl_hw_cap, |
716 | &props->max_vl_num); | |
e126ba97 | 717 | out: |
1b5daf11 | 718 | kfree(rep); |
e126ba97 EC |
719 | return err; |
720 | } | |
721 | ||
1b5daf11 MD |
722 | int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, |
723 | struct ib_port_attr *props) | |
e126ba97 | 724 | { |
1b5daf11 MD |
725 | switch (mlx5_get_vport_access_method(ibdev)) { |
726 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
727 | return mlx5_query_mad_ifc_port(ibdev, port, props); | |
e126ba97 | 728 | |
1b5daf11 MD |
729 | case MLX5_VPORT_ACCESS_METHOD_HCA: |
730 | return mlx5_query_hca_port(ibdev, port, props); | |
e126ba97 | 731 | |
3f89a643 AS |
732 | case MLX5_VPORT_ACCESS_METHOD_NIC: |
733 | return mlx5_query_port_roce(ibdev, port, props); | |
734 | ||
1b5daf11 MD |
735 | default: |
736 | return -EINVAL; | |
737 | } | |
738 | } | |
e126ba97 | 739 | |
1b5daf11 MD |
740 | static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, |
741 | union ib_gid *gid) | |
742 | { | |
743 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
744 | struct mlx5_core_dev *mdev = dev->mdev; | |
e126ba97 | 745 | |
1b5daf11 MD |
746 | switch (mlx5_get_vport_access_method(ibdev)) { |
747 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
748 | return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); | |
e126ba97 | 749 | |
1b5daf11 MD |
750 | case MLX5_VPORT_ACCESS_METHOD_HCA: |
751 | return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); | |
752 | ||
753 | default: | |
754 | return -EINVAL; | |
755 | } | |
e126ba97 | 756 | |
e126ba97 EC |
757 | } |
758 | ||
1b5daf11 MD |
759 | static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, |
760 | u16 *pkey) | |
761 | { | |
762 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
763 | struct mlx5_core_dev *mdev = dev->mdev; | |
764 | ||
765 | switch (mlx5_get_vport_access_method(ibdev)) { | |
766 | case MLX5_VPORT_ACCESS_METHOD_MAD: | |
767 | return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); | |
768 | ||
769 | case MLX5_VPORT_ACCESS_METHOD_HCA: | |
770 | case MLX5_VPORT_ACCESS_METHOD_NIC: | |
771 | return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, | |
772 | pkey); | |
773 | default: | |
774 | return -EINVAL; | |
775 | } | |
776 | } | |
e126ba97 EC |
777 | |
778 | static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, | |
779 | struct ib_device_modify *props) | |
780 | { | |
781 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
782 | struct mlx5_reg_node_desc in; | |
783 | struct mlx5_reg_node_desc out; | |
784 | int err; | |
785 | ||
786 | if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) | |
787 | return -EOPNOTSUPP; | |
788 | ||
789 | if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) | |
790 | return 0; | |
791 | ||
792 | /* | |
793 | * If possible, pass node desc to FW, so it can generate | |
794 | * a 144 trap. If cmd fails, just ignore. | |
795 | */ | |
796 | memcpy(&in, props->node_desc, 64); | |
9603b61d | 797 | err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, |
e126ba97 EC |
798 | sizeof(out), MLX5_REG_NODE_DESC, 0, 1); |
799 | if (err) | |
800 | return err; | |
801 | ||
802 | memcpy(ibdev->node_desc, props->node_desc, 64); | |
803 | ||
804 | return err; | |
805 | } | |
806 | ||
807 | static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, | |
808 | struct ib_port_modify *props) | |
809 | { | |
810 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
811 | struct ib_port_attr attr; | |
812 | u32 tmp; | |
813 | int err; | |
814 | ||
815 | mutex_lock(&dev->cap_mask_mutex); | |
816 | ||
817 | err = mlx5_ib_query_port(ibdev, port, &attr); | |
818 | if (err) | |
819 | goto out; | |
820 | ||
821 | tmp = (attr.port_cap_flags | props->set_port_cap_mask) & | |
822 | ~props->clr_port_cap_mask; | |
823 | ||
9603b61d | 824 | err = mlx5_set_port_caps(dev->mdev, port, tmp); |
e126ba97 EC |
825 | |
826 | out: | |
827 | mutex_unlock(&dev->cap_mask_mutex); | |
828 | return err; | |
829 | } | |
830 | ||
831 | static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, | |
832 | struct ib_udata *udata) | |
833 | { | |
834 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
b368d7cb MB |
835 | struct mlx5_ib_alloc_ucontext_req_v2 req = {}; |
836 | struct mlx5_ib_alloc_ucontext_resp resp = {}; | |
e126ba97 EC |
837 | struct mlx5_ib_ucontext *context; |
838 | struct mlx5_uuar_info *uuari; | |
839 | struct mlx5_uar *uars; | |
c1be5232 | 840 | int gross_uuars; |
e126ba97 | 841 | int num_uars; |
78c0f98c | 842 | int ver; |
e126ba97 EC |
843 | int uuarn; |
844 | int err; | |
845 | int i; | |
f241e749 | 846 | size_t reqlen; |
a168a41c MD |
847 | size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, |
848 | max_cqe_version); | |
e126ba97 EC |
849 | |
850 | if (!dev->ib_active) | |
851 | return ERR_PTR(-EAGAIN); | |
852 | ||
dfbee859 HA |
853 | if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) |
854 | return ERR_PTR(-EINVAL); | |
855 | ||
78c0f98c EC |
856 | reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); |
857 | if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) | |
858 | ver = 0; | |
a168a41c | 859 | else if (reqlen >= min_req_v2) |
78c0f98c EC |
860 | ver = 2; |
861 | else | |
862 | return ERR_PTR(-EINVAL); | |
863 | ||
b368d7cb | 864 | err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); |
e126ba97 EC |
865 | if (err) |
866 | return ERR_PTR(err); | |
867 | ||
b368d7cb | 868 | if (req.flags) |
78c0f98c EC |
869 | return ERR_PTR(-EINVAL); |
870 | ||
e126ba97 EC |
871 | if (req.total_num_uuars > MLX5_MAX_UUARS) |
872 | return ERR_PTR(-ENOMEM); | |
873 | ||
874 | if (req.total_num_uuars == 0) | |
875 | return ERR_PTR(-EINVAL); | |
876 | ||
f72300c5 | 877 | if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) |
b368d7cb MB |
878 | return ERR_PTR(-EOPNOTSUPP); |
879 | ||
880 | if (reqlen > sizeof(req) && | |
881 | !ib_is_udata_cleared(udata, sizeof(req), | |
dfbee859 | 882 | reqlen - sizeof(req))) |
b368d7cb MB |
883 | return ERR_PTR(-EOPNOTSUPP); |
884 | ||
c1be5232 EC |
885 | req.total_num_uuars = ALIGN(req.total_num_uuars, |
886 | MLX5_NON_FP_BF_REGS_PER_PAGE); | |
e126ba97 EC |
887 | if (req.num_low_latency_uuars > req.total_num_uuars - 1) |
888 | return ERR_PTR(-EINVAL); | |
889 | ||
c1be5232 EC |
890 | num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; |
891 | gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; | |
938fe83c SM |
892 | resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); |
893 | resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); | |
894 | resp.cache_line_size = L1_CACHE_BYTES; | |
895 | resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); | |
896 | resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); | |
897 | resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); | |
898 | resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); | |
899 | resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); | |
f72300c5 HA |
900 | resp.cqe_version = min_t(__u8, |
901 | (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), | |
902 | req.max_cqe_version); | |
b368d7cb MB |
903 | resp.response_length = min(offsetof(typeof(resp), response_length) + |
904 | sizeof(resp.response_length), udata->outlen); | |
e126ba97 EC |
905 | |
906 | context = kzalloc(sizeof(*context), GFP_KERNEL); | |
907 | if (!context) | |
908 | return ERR_PTR(-ENOMEM); | |
909 | ||
910 | uuari = &context->uuari; | |
911 | mutex_init(&uuari->lock); | |
912 | uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); | |
913 | if (!uars) { | |
914 | err = -ENOMEM; | |
915 | goto out_ctx; | |
916 | } | |
917 | ||
c1be5232 | 918 | uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), |
e126ba97 EC |
919 | sizeof(*uuari->bitmap), |
920 | GFP_KERNEL); | |
921 | if (!uuari->bitmap) { | |
922 | err = -ENOMEM; | |
923 | goto out_uar_ctx; | |
924 | } | |
925 | /* | |
926 | * clear all fast path uuars | |
927 | */ | |
c1be5232 | 928 | for (i = 0; i < gross_uuars; i++) { |
e126ba97 EC |
929 | uuarn = i & 3; |
930 | if (uuarn == 2 || uuarn == 3) | |
931 | set_bit(i, uuari->bitmap); | |
932 | } | |
933 | ||
c1be5232 | 934 | uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); |
e126ba97 EC |
935 | if (!uuari->count) { |
936 | err = -ENOMEM; | |
937 | goto out_bitmap; | |
938 | } | |
939 | ||
940 | for (i = 0; i < num_uars; i++) { | |
9603b61d | 941 | err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); |
e126ba97 EC |
942 | if (err) |
943 | goto out_count; | |
944 | } | |
945 | ||
b4cfe447 HE |
946 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
947 | context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; | |
948 | #endif | |
949 | ||
146d2f1a | 950 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { |
951 | err = mlx5_core_alloc_transport_domain(dev->mdev, | |
952 | &context->tdn); | |
953 | if (err) | |
954 | goto out_uars; | |
955 | } | |
956 | ||
e126ba97 EC |
957 | INIT_LIST_HEAD(&context->db_page_list); |
958 | mutex_init(&context->db_page_mutex); | |
959 | ||
960 | resp.tot_uuars = req.total_num_uuars; | |
938fe83c | 961 | resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); |
b368d7cb | 962 | |
f72300c5 HA |
963 | if (field_avail(typeof(resp), cqe_version, udata->outlen)) |
964 | resp.response_length += sizeof(resp.cqe_version); | |
b368d7cb MB |
965 | |
966 | if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { | |
967 | resp.comp_mask |= | |
968 | MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; | |
969 | resp.hca_core_clock_offset = | |
970 | offsetof(struct mlx5_init_seg, internal_timer_h) % | |
971 | PAGE_SIZE; | |
f72300c5 HA |
972 | resp.response_length += sizeof(resp.hca_core_clock_offset) + |
973 | sizeof(resp.reserved2) + | |
974 | sizeof(resp.reserved3); | |
b368d7cb MB |
975 | } |
976 | ||
977 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
e126ba97 | 978 | if (err) |
146d2f1a | 979 | goto out_td; |
e126ba97 | 980 | |
78c0f98c | 981 | uuari->ver = ver; |
e126ba97 EC |
982 | uuari->num_low_latency_uuars = req.num_low_latency_uuars; |
983 | uuari->uars = uars; | |
984 | uuari->num_uars = num_uars; | |
f72300c5 HA |
985 | context->cqe_version = resp.cqe_version; |
986 | ||
e126ba97 EC |
987 | return &context->ibucontext; |
988 | ||
146d2f1a | 989 | out_td: |
990 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) | |
991 | mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); | |
992 | ||
e126ba97 EC |
993 | out_uars: |
994 | for (i--; i >= 0; i--) | |
9603b61d | 995 | mlx5_cmd_free_uar(dev->mdev, uars[i].index); |
e126ba97 EC |
996 | out_count: |
997 | kfree(uuari->count); | |
998 | ||
999 | out_bitmap: | |
1000 | kfree(uuari->bitmap); | |
1001 | ||
1002 | out_uar_ctx: | |
1003 | kfree(uars); | |
1004 | ||
1005 | out_ctx: | |
1006 | kfree(context); | |
1007 | return ERR_PTR(err); | |
1008 | } | |
1009 | ||
1010 | static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) | |
1011 | { | |
1012 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1013 | struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); | |
1014 | struct mlx5_uuar_info *uuari = &context->uuari; | |
1015 | int i; | |
1016 | ||
146d2f1a | 1017 | if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) |
1018 | mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn); | |
1019 | ||
e126ba97 | 1020 | for (i = 0; i < uuari->num_uars; i++) { |
9603b61d | 1021 | if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) |
e126ba97 EC |
1022 | mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); |
1023 | } | |
1024 | ||
1025 | kfree(uuari->count); | |
1026 | kfree(uuari->bitmap); | |
1027 | kfree(uuari->uars); | |
1028 | kfree(context); | |
1029 | ||
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) | |
1034 | { | |
9603b61d | 1035 | return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; |
e126ba97 EC |
1036 | } |
1037 | ||
1038 | static int get_command(unsigned long offset) | |
1039 | { | |
1040 | return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; | |
1041 | } | |
1042 | ||
1043 | static int get_arg(unsigned long offset) | |
1044 | { | |
1045 | return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); | |
1046 | } | |
1047 | ||
1048 | static int get_index(unsigned long offset) | |
1049 | { | |
1050 | return get_arg(offset); | |
1051 | } | |
1052 | ||
1053 | static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) | |
1054 | { | |
1055 | struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); | |
1056 | struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); | |
1057 | struct mlx5_uuar_info *uuari = &context->uuari; | |
1058 | unsigned long command; | |
1059 | unsigned long idx; | |
1060 | phys_addr_t pfn; | |
1061 | ||
1062 | command = get_command(vma->vm_pgoff); | |
1063 | switch (command) { | |
1064 | case MLX5_IB_MMAP_REGULAR_PAGE: | |
1065 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) | |
1066 | return -EINVAL; | |
1067 | ||
1068 | idx = get_index(vma->vm_pgoff); | |
1c3ce90d EC |
1069 | if (idx >= uuari->num_uars) |
1070 | return -EINVAL; | |
1071 | ||
e126ba97 EC |
1072 | pfn = uar_index2pfn(dev, uuari->uars[idx].index); |
1073 | mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx, | |
1074 | (unsigned long long)pfn); | |
1075 | ||
e126ba97 EC |
1076 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); |
1077 | if (io_remap_pfn_range(vma, vma->vm_start, pfn, | |
1078 | PAGE_SIZE, vma->vm_page_prot)) | |
1079 | return -EAGAIN; | |
1080 | ||
1081 | mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n", | |
1082 | vma->vm_start, | |
1083 | (unsigned long long)pfn << PAGE_SHIFT); | |
1084 | break; | |
1085 | ||
1086 | case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: | |
1087 | return -ENOSYS; | |
1088 | ||
d69e3bcf | 1089 | case MLX5_IB_MMAP_CORE_CLOCK: |
d69e3bcf MB |
1090 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) |
1091 | return -EINVAL; | |
1092 | ||
1093 | if (vma->vm_flags & (VM_WRITE | VM_EXEC)) | |
1094 | return -EPERM; | |
1095 | ||
1096 | /* Don't expose to user-space information it shouldn't have */ | |
1097 | if (PAGE_SIZE > 4096) | |
1098 | return -EOPNOTSUPP; | |
1099 | ||
1100 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
1101 | pfn = (dev->mdev->iseg_base + | |
1102 | offsetof(struct mlx5_init_seg, internal_timer_h)) >> | |
1103 | PAGE_SHIFT; | |
1104 | if (io_remap_pfn_range(vma, vma->vm_start, pfn, | |
1105 | PAGE_SIZE, vma->vm_page_prot)) | |
1106 | return -EAGAIN; | |
1107 | ||
1108 | mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n", | |
1109 | vma->vm_start, | |
1110 | (unsigned long long)pfn << PAGE_SHIFT); | |
1111 | break; | |
d69e3bcf | 1112 | |
e126ba97 EC |
1113 | default: |
1114 | return -EINVAL; | |
1115 | } | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
e126ba97 EC |
1120 | static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, |
1121 | struct ib_ucontext *context, | |
1122 | struct ib_udata *udata) | |
1123 | { | |
1124 | struct mlx5_ib_alloc_pd_resp resp; | |
1125 | struct mlx5_ib_pd *pd; | |
1126 | int err; | |
1127 | ||
1128 | pd = kmalloc(sizeof(*pd), GFP_KERNEL); | |
1129 | if (!pd) | |
1130 | return ERR_PTR(-ENOMEM); | |
1131 | ||
9603b61d | 1132 | err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); |
e126ba97 EC |
1133 | if (err) { |
1134 | kfree(pd); | |
1135 | return ERR_PTR(err); | |
1136 | } | |
1137 | ||
1138 | if (context) { | |
1139 | resp.pdn = pd->pdn; | |
1140 | if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { | |
9603b61d | 1141 | mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); |
e126ba97 EC |
1142 | kfree(pd); |
1143 | return ERR_PTR(-EFAULT); | |
1144 | } | |
e126ba97 EC |
1145 | } |
1146 | ||
1147 | return &pd->ibpd; | |
1148 | } | |
1149 | ||
1150 | static int mlx5_ib_dealloc_pd(struct ib_pd *pd) | |
1151 | { | |
1152 | struct mlx5_ib_dev *mdev = to_mdev(pd->device); | |
1153 | struct mlx5_ib_pd *mpd = to_mpd(pd); | |
1154 | ||
9603b61d | 1155 | mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); |
e126ba97 EC |
1156 | kfree(mpd); |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
038d2ef8 MG |
1161 | static bool outer_header_zero(u32 *match_criteria) |
1162 | { | |
1163 | int size = MLX5_ST_SZ_BYTES(fte_match_param); | |
1164 | char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria, | |
1165 | outer_headers); | |
1166 | ||
1167 | return outer_headers_c[0] == 0 && !memcmp(outer_headers_c, | |
1168 | outer_headers_c + 1, | |
1169 | size - 1); | |
1170 | } | |
1171 | ||
1172 | static int parse_flow_attr(u32 *match_c, u32 *match_v, | |
1173 | union ib_flow_spec *ib_spec) | |
1174 | { | |
1175 | void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, | |
1176 | outer_headers); | |
1177 | void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, | |
1178 | outer_headers); | |
1179 | switch (ib_spec->type) { | |
1180 | case IB_FLOW_SPEC_ETH: | |
1181 | if (ib_spec->size != sizeof(ib_spec->eth)) | |
1182 | return -EINVAL; | |
1183 | ||
1184 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1185 | dmac_47_16), | |
1186 | ib_spec->eth.mask.dst_mac); | |
1187 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1188 | dmac_47_16), | |
1189 | ib_spec->eth.val.dst_mac); | |
1190 | ||
1191 | if (ib_spec->eth.mask.vlan_tag) { | |
1192 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1193 | vlan_tag, 1); | |
1194 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1195 | vlan_tag, 1); | |
1196 | ||
1197 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1198 | first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); | |
1199 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1200 | first_vid, ntohs(ib_spec->eth.val.vlan_tag)); | |
1201 | ||
1202 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1203 | first_cfi, | |
1204 | ntohs(ib_spec->eth.mask.vlan_tag) >> 12); | |
1205 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1206 | first_cfi, | |
1207 | ntohs(ib_spec->eth.val.vlan_tag) >> 12); | |
1208 | ||
1209 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1210 | first_prio, | |
1211 | ntohs(ib_spec->eth.mask.vlan_tag) >> 13); | |
1212 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1213 | first_prio, | |
1214 | ntohs(ib_spec->eth.val.vlan_tag) >> 13); | |
1215 | } | |
1216 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1217 | ethertype, ntohs(ib_spec->eth.mask.ether_type)); | |
1218 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1219 | ethertype, ntohs(ib_spec->eth.val.ether_type)); | |
1220 | break; | |
1221 | case IB_FLOW_SPEC_IPV4: | |
1222 | if (ib_spec->size != sizeof(ib_spec->ipv4)) | |
1223 | return -EINVAL; | |
1224 | ||
1225 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, | |
1226 | ethertype, 0xffff); | |
1227 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, | |
1228 | ethertype, ETH_P_IP); | |
1229 | ||
1230 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1231 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
1232 | &ib_spec->ipv4.mask.src_ip, | |
1233 | sizeof(ib_spec->ipv4.mask.src_ip)); | |
1234 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1235 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
1236 | &ib_spec->ipv4.val.src_ip, | |
1237 | sizeof(ib_spec->ipv4.val.src_ip)); | |
1238 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, | |
1239 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
1240 | &ib_spec->ipv4.mask.dst_ip, | |
1241 | sizeof(ib_spec->ipv4.mask.dst_ip)); | |
1242 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, | |
1243 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
1244 | &ib_spec->ipv4.val.dst_ip, | |
1245 | sizeof(ib_spec->ipv4.val.dst_ip)); | |
1246 | break; | |
1247 | case IB_FLOW_SPEC_TCP: | |
1248 | if (ib_spec->size != sizeof(ib_spec->tcp_udp)) | |
1249 | return -EINVAL; | |
1250 | ||
1251 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, | |
1252 | 0xff); | |
1253 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, | |
1254 | IPPROTO_TCP); | |
1255 | ||
1256 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, | |
1257 | ntohs(ib_spec->tcp_udp.mask.src_port)); | |
1258 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, | |
1259 | ntohs(ib_spec->tcp_udp.val.src_port)); | |
1260 | ||
1261 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, | |
1262 | ntohs(ib_spec->tcp_udp.mask.dst_port)); | |
1263 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, | |
1264 | ntohs(ib_spec->tcp_udp.val.dst_port)); | |
1265 | break; | |
1266 | case IB_FLOW_SPEC_UDP: | |
1267 | if (ib_spec->size != sizeof(ib_spec->tcp_udp)) | |
1268 | return -EINVAL; | |
1269 | ||
1270 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, | |
1271 | 0xff); | |
1272 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, | |
1273 | IPPROTO_UDP); | |
1274 | ||
1275 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, | |
1276 | ntohs(ib_spec->tcp_udp.mask.src_port)); | |
1277 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, | |
1278 | ntohs(ib_spec->tcp_udp.val.src_port)); | |
1279 | ||
1280 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, | |
1281 | ntohs(ib_spec->tcp_udp.mask.dst_port)); | |
1282 | MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, | |
1283 | ntohs(ib_spec->tcp_udp.val.dst_port)); | |
1284 | break; | |
1285 | default: | |
1286 | return -EINVAL; | |
1287 | } | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | /* If a flow could catch both multicast and unicast packets, | |
1293 | * it won't fall into the multicast flow steering table and this rule | |
1294 | * could steal other multicast packets. | |
1295 | */ | |
1296 | static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) | |
1297 | { | |
1298 | struct ib_flow_spec_eth *eth_spec; | |
1299 | ||
1300 | if (ib_attr->type != IB_FLOW_ATTR_NORMAL || | |
1301 | ib_attr->size < sizeof(struct ib_flow_attr) + | |
1302 | sizeof(struct ib_flow_spec_eth) || | |
1303 | ib_attr->num_of_specs < 1) | |
1304 | return false; | |
1305 | ||
1306 | eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); | |
1307 | if (eth_spec->type != IB_FLOW_SPEC_ETH || | |
1308 | eth_spec->size != sizeof(*eth_spec)) | |
1309 | return false; | |
1310 | ||
1311 | return is_multicast_ether_addr(eth_spec->mask.dst_mac) && | |
1312 | is_multicast_ether_addr(eth_spec->val.dst_mac); | |
1313 | } | |
1314 | ||
1315 | static bool is_valid_attr(struct ib_flow_attr *flow_attr) | |
1316 | { | |
1317 | union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); | |
1318 | bool has_ipv4_spec = false; | |
1319 | bool eth_type_ipv4 = true; | |
1320 | unsigned int spec_index; | |
1321 | ||
1322 | /* Validate that ethertype is correct */ | |
1323 | for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
1324 | if (ib_spec->type == IB_FLOW_SPEC_ETH && | |
1325 | ib_spec->eth.mask.ether_type) { | |
1326 | if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && | |
1327 | ib_spec->eth.val.ether_type == htons(ETH_P_IP))) | |
1328 | eth_type_ipv4 = false; | |
1329 | } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { | |
1330 | has_ipv4_spec = true; | |
1331 | } | |
1332 | ib_spec = (void *)ib_spec + ib_spec->size; | |
1333 | } | |
1334 | return !has_ipv4_spec || eth_type_ipv4; | |
1335 | } | |
1336 | ||
1337 | static void put_flow_table(struct mlx5_ib_dev *dev, | |
1338 | struct mlx5_ib_flow_prio *prio, bool ft_added) | |
1339 | { | |
1340 | prio->refcount -= !!ft_added; | |
1341 | if (!prio->refcount) { | |
1342 | mlx5_destroy_flow_table(prio->flow_table); | |
1343 | prio->flow_table = NULL; | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) | |
1348 | { | |
1349 | struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); | |
1350 | struct mlx5_ib_flow_handler *handler = container_of(flow_id, | |
1351 | struct mlx5_ib_flow_handler, | |
1352 | ibflow); | |
1353 | struct mlx5_ib_flow_handler *iter, *tmp; | |
1354 | ||
1355 | mutex_lock(&dev->flow_db.lock); | |
1356 | ||
1357 | list_for_each_entry_safe(iter, tmp, &handler->list, list) { | |
1358 | mlx5_del_flow_rule(iter->rule); | |
1359 | list_del(&iter->list); | |
1360 | kfree(iter); | |
1361 | } | |
1362 | ||
1363 | mlx5_del_flow_rule(handler->rule); | |
1364 | put_flow_table(dev, &dev->flow_db.prios[handler->prio], true); | |
1365 | mutex_unlock(&dev->flow_db.lock); | |
1366 | ||
1367 | kfree(handler); | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | #define MLX5_FS_MAX_TYPES 10 | |
1373 | #define MLX5_FS_MAX_ENTRIES 32000UL | |
1374 | static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, | |
1375 | struct ib_flow_attr *flow_attr) | |
1376 | { | |
1377 | struct mlx5_flow_namespace *ns = NULL; | |
1378 | struct mlx5_ib_flow_prio *prio; | |
1379 | struct mlx5_flow_table *ft; | |
1380 | int num_entries; | |
1381 | int num_groups; | |
1382 | int priority; | |
1383 | int err = 0; | |
1384 | ||
1385 | if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { | |
1386 | if (flow_is_multicast_only(flow_attr)) | |
1387 | priority = MLX5_IB_FLOW_MCAST_PRIO; | |
1388 | else | |
1389 | priority = flow_attr->priority; | |
1390 | ns = mlx5_get_flow_namespace(dev->mdev, | |
1391 | MLX5_FLOW_NAMESPACE_BYPASS); | |
1392 | num_entries = MLX5_FS_MAX_ENTRIES; | |
1393 | num_groups = MLX5_FS_MAX_TYPES; | |
1394 | prio = &dev->flow_db.prios[priority]; | |
1395 | } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || | |
1396 | flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
1397 | ns = mlx5_get_flow_namespace(dev->mdev, | |
1398 | MLX5_FLOW_NAMESPACE_LEFTOVERS); | |
1399 | build_leftovers_ft_param(&priority, | |
1400 | &num_entries, | |
1401 | &num_groups); | |
1402 | prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; | |
1403 | } | |
1404 | ||
1405 | if (!ns) | |
1406 | return ERR_PTR(-ENOTSUPP); | |
1407 | ||
1408 | ft = prio->flow_table; | |
1409 | if (!ft) { | |
1410 | ft = mlx5_create_auto_grouped_flow_table(ns, priority, | |
1411 | num_entries, | |
1412 | num_groups); | |
1413 | ||
1414 | if (!IS_ERR(ft)) { | |
1415 | prio->refcount = 0; | |
1416 | prio->flow_table = ft; | |
1417 | } else { | |
1418 | err = PTR_ERR(ft); | |
1419 | } | |
1420 | } | |
1421 | ||
1422 | return err ? ERR_PTR(err) : prio; | |
1423 | } | |
1424 | ||
1425 | static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, | |
1426 | struct mlx5_ib_flow_prio *ft_prio, | |
1427 | struct ib_flow_attr *flow_attr, | |
1428 | struct mlx5_flow_destination *dst) | |
1429 | { | |
1430 | struct mlx5_flow_table *ft = ft_prio->flow_table; | |
1431 | struct mlx5_ib_flow_handler *handler; | |
1432 | void *ib_flow = flow_attr + 1; | |
1433 | u8 match_criteria_enable = 0; | |
1434 | unsigned int spec_index; | |
1435 | u32 *match_c; | |
1436 | u32 *match_v; | |
1437 | int err = 0; | |
1438 | ||
1439 | if (!is_valid_attr(flow_attr)) | |
1440 | return ERR_PTR(-EINVAL); | |
1441 | ||
1442 | match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
1443 | match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL); | |
1444 | handler = kzalloc(sizeof(*handler), GFP_KERNEL); | |
1445 | if (!handler || !match_c || !match_v) { | |
1446 | err = -ENOMEM; | |
1447 | goto free; | |
1448 | } | |
1449 | ||
1450 | INIT_LIST_HEAD(&handler->list); | |
1451 | ||
1452 | for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { | |
1453 | err = parse_flow_attr(match_c, match_v, ib_flow); | |
1454 | if (err < 0) | |
1455 | goto free; | |
1456 | ||
1457 | ib_flow += ((union ib_flow_spec *)ib_flow)->size; | |
1458 | } | |
1459 | ||
1460 | /* Outer header support only */ | |
1461 | match_criteria_enable = (!outer_header_zero(match_c)) << 0; | |
1462 | handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable, | |
1463 | match_c, match_v, | |
1464 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST, | |
1465 | MLX5_FS_DEFAULT_FLOW_TAG, | |
1466 | dst); | |
1467 | ||
1468 | if (IS_ERR(handler->rule)) { | |
1469 | err = PTR_ERR(handler->rule); | |
1470 | goto free; | |
1471 | } | |
1472 | ||
1473 | handler->prio = ft_prio - dev->flow_db.prios; | |
1474 | ||
1475 | ft_prio->flow_table = ft; | |
1476 | free: | |
1477 | if (err) | |
1478 | kfree(handler); | |
1479 | kfree(match_c); | |
1480 | kfree(match_v); | |
1481 | return err ? ERR_PTR(err) : handler; | |
1482 | } | |
1483 | ||
1484 | enum { | |
1485 | LEFTOVERS_MC, | |
1486 | LEFTOVERS_UC, | |
1487 | }; | |
1488 | ||
1489 | static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, | |
1490 | struct mlx5_ib_flow_prio *ft_prio, | |
1491 | struct ib_flow_attr *flow_attr, | |
1492 | struct mlx5_flow_destination *dst) | |
1493 | { | |
1494 | struct mlx5_ib_flow_handler *handler_ucast = NULL; | |
1495 | struct mlx5_ib_flow_handler *handler = NULL; | |
1496 | ||
1497 | static struct { | |
1498 | struct ib_flow_attr flow_attr; | |
1499 | struct ib_flow_spec_eth eth_flow; | |
1500 | } leftovers_specs[] = { | |
1501 | [LEFTOVERS_MC] = { | |
1502 | .flow_attr = { | |
1503 | .num_of_specs = 1, | |
1504 | .size = sizeof(leftovers_specs[0]) | |
1505 | }, | |
1506 | .eth_flow = { | |
1507 | .type = IB_FLOW_SPEC_ETH, | |
1508 | .size = sizeof(struct ib_flow_spec_eth), | |
1509 | .mask = {.dst_mac = {0x1} }, | |
1510 | .val = {.dst_mac = {0x1} } | |
1511 | } | |
1512 | }, | |
1513 | [LEFTOVERS_UC] = { | |
1514 | .flow_attr = { | |
1515 | .num_of_specs = 1, | |
1516 | .size = sizeof(leftovers_specs[0]) | |
1517 | }, | |
1518 | .eth_flow = { | |
1519 | .type = IB_FLOW_SPEC_ETH, | |
1520 | .size = sizeof(struct ib_flow_spec_eth), | |
1521 | .mask = {.dst_mac = {0x1} }, | |
1522 | .val = {.dst_mac = {} } | |
1523 | } | |
1524 | } | |
1525 | }; | |
1526 | ||
1527 | handler = create_flow_rule(dev, ft_prio, | |
1528 | &leftovers_specs[LEFTOVERS_MC].flow_attr, | |
1529 | dst); | |
1530 | if (!IS_ERR(handler) && | |
1531 | flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { | |
1532 | handler_ucast = create_flow_rule(dev, ft_prio, | |
1533 | &leftovers_specs[LEFTOVERS_UC].flow_attr, | |
1534 | dst); | |
1535 | if (IS_ERR(handler_ucast)) { | |
1536 | kfree(handler); | |
1537 | handler = handler_ucast; | |
1538 | } else { | |
1539 | list_add(&handler_ucast->list, &handler->list); | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | return handler; | |
1544 | } | |
1545 | ||
1546 | static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, | |
1547 | struct ib_flow_attr *flow_attr, | |
1548 | int domain) | |
1549 | { | |
1550 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
1551 | struct mlx5_ib_flow_handler *handler = NULL; | |
1552 | struct mlx5_flow_destination *dst = NULL; | |
1553 | struct mlx5_ib_flow_prio *ft_prio; | |
1554 | int err; | |
1555 | ||
1556 | if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) | |
1557 | return ERR_PTR(-ENOSPC); | |
1558 | ||
1559 | if (domain != IB_FLOW_DOMAIN_USER || | |
1560 | flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || | |
1561 | flow_attr->flags) | |
1562 | return ERR_PTR(-EINVAL); | |
1563 | ||
1564 | dst = kzalloc(sizeof(*dst), GFP_KERNEL); | |
1565 | if (!dst) | |
1566 | return ERR_PTR(-ENOMEM); | |
1567 | ||
1568 | mutex_lock(&dev->flow_db.lock); | |
1569 | ||
1570 | ft_prio = get_flow_table(dev, flow_attr); | |
1571 | if (IS_ERR(ft_prio)) { | |
1572 | err = PTR_ERR(ft_prio); | |
1573 | goto unlock; | |
1574 | } | |
1575 | ||
1576 | dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; | |
1577 | dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn; | |
1578 | ||
1579 | if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { | |
1580 | handler = create_flow_rule(dev, ft_prio, flow_attr, | |
1581 | dst); | |
1582 | } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || | |
1583 | flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { | |
1584 | handler = create_leftovers_rule(dev, ft_prio, flow_attr, | |
1585 | dst); | |
1586 | } else { | |
1587 | err = -EINVAL; | |
1588 | goto destroy_ft; | |
1589 | } | |
1590 | ||
1591 | if (IS_ERR(handler)) { | |
1592 | err = PTR_ERR(handler); | |
1593 | handler = NULL; | |
1594 | goto destroy_ft; | |
1595 | } | |
1596 | ||
1597 | ft_prio->refcount++; | |
1598 | mutex_unlock(&dev->flow_db.lock); | |
1599 | kfree(dst); | |
1600 | ||
1601 | return &handler->ibflow; | |
1602 | ||
1603 | destroy_ft: | |
1604 | put_flow_table(dev, ft_prio, false); | |
1605 | unlock: | |
1606 | mutex_unlock(&dev->flow_db.lock); | |
1607 | kfree(dst); | |
1608 | kfree(handler); | |
1609 | return ERR_PTR(err); | |
1610 | } | |
1611 | ||
e126ba97 EC |
1612 | static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) |
1613 | { | |
1614 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
1615 | int err; | |
1616 | ||
9603b61d | 1617 | err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); |
e126ba97 EC |
1618 | if (err) |
1619 | mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", | |
1620 | ibqp->qp_num, gid->raw); | |
1621 | ||
1622 | return err; | |
1623 | } | |
1624 | ||
1625 | static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) | |
1626 | { | |
1627 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
1628 | int err; | |
1629 | ||
9603b61d | 1630 | err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); |
e126ba97 EC |
1631 | if (err) |
1632 | mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", | |
1633 | ibqp->qp_num, gid->raw); | |
1634 | ||
1635 | return err; | |
1636 | } | |
1637 | ||
1638 | static int init_node_data(struct mlx5_ib_dev *dev) | |
1639 | { | |
1b5daf11 | 1640 | int err; |
e126ba97 | 1641 | |
1b5daf11 | 1642 | err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); |
e126ba97 | 1643 | if (err) |
1b5daf11 | 1644 | return err; |
e126ba97 | 1645 | |
1b5daf11 | 1646 | dev->mdev->rev_id = dev->mdev->pdev->revision; |
e126ba97 | 1647 | |
1b5daf11 | 1648 | return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); |
e126ba97 EC |
1649 | } |
1650 | ||
1651 | static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, | |
1652 | char *buf) | |
1653 | { | |
1654 | struct mlx5_ib_dev *dev = | |
1655 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
1656 | ||
9603b61d | 1657 | return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages); |
e126ba97 EC |
1658 | } |
1659 | ||
1660 | static ssize_t show_reg_pages(struct device *device, | |
1661 | struct device_attribute *attr, char *buf) | |
1662 | { | |
1663 | struct mlx5_ib_dev *dev = | |
1664 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
1665 | ||
6aec21f6 | 1666 | return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); |
e126ba97 EC |
1667 | } |
1668 | ||
1669 | static ssize_t show_hca(struct device *device, struct device_attribute *attr, | |
1670 | char *buf) | |
1671 | { | |
1672 | struct mlx5_ib_dev *dev = | |
1673 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
9603b61d | 1674 | return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); |
e126ba97 EC |
1675 | } |
1676 | ||
1677 | static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr, | |
1678 | char *buf) | |
1679 | { | |
1680 | struct mlx5_ib_dev *dev = | |
1681 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
9603b61d JM |
1682 | return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev), |
1683 | fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); | |
e126ba97 EC |
1684 | } |
1685 | ||
1686 | static ssize_t show_rev(struct device *device, struct device_attribute *attr, | |
1687 | char *buf) | |
1688 | { | |
1689 | struct mlx5_ib_dev *dev = | |
1690 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
9603b61d | 1691 | return sprintf(buf, "%x\n", dev->mdev->rev_id); |
e126ba97 EC |
1692 | } |
1693 | ||
1694 | static ssize_t show_board(struct device *device, struct device_attribute *attr, | |
1695 | char *buf) | |
1696 | { | |
1697 | struct mlx5_ib_dev *dev = | |
1698 | container_of(device, struct mlx5_ib_dev, ib_dev.dev); | |
1699 | return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, | |
9603b61d | 1700 | dev->mdev->board_id); |
e126ba97 EC |
1701 | } |
1702 | ||
1703 | static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); | |
1704 | static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); | |
1705 | static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); | |
1706 | static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); | |
1707 | static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); | |
1708 | static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); | |
1709 | ||
1710 | static struct device_attribute *mlx5_class_attributes[] = { | |
1711 | &dev_attr_hw_rev, | |
1712 | &dev_attr_fw_ver, | |
1713 | &dev_attr_hca_type, | |
1714 | &dev_attr_board_id, | |
1715 | &dev_attr_fw_pages, | |
1716 | &dev_attr_reg_pages, | |
1717 | }; | |
1718 | ||
9603b61d | 1719 | static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, |
4d2f9bbb | 1720 | enum mlx5_dev_event event, unsigned long param) |
e126ba97 | 1721 | { |
9603b61d | 1722 | struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; |
e126ba97 | 1723 | struct ib_event ibev; |
9603b61d | 1724 | |
e126ba97 EC |
1725 | u8 port = 0; |
1726 | ||
1727 | switch (event) { | |
1728 | case MLX5_DEV_EVENT_SYS_ERROR: | |
1729 | ibdev->ib_active = false; | |
1730 | ibev.event = IB_EVENT_DEVICE_FATAL; | |
1731 | break; | |
1732 | ||
1733 | case MLX5_DEV_EVENT_PORT_UP: | |
1734 | ibev.event = IB_EVENT_PORT_ACTIVE; | |
4d2f9bbb | 1735 | port = (u8)param; |
e126ba97 EC |
1736 | break; |
1737 | ||
1738 | case MLX5_DEV_EVENT_PORT_DOWN: | |
1739 | ibev.event = IB_EVENT_PORT_ERR; | |
4d2f9bbb | 1740 | port = (u8)param; |
e126ba97 EC |
1741 | break; |
1742 | ||
1743 | case MLX5_DEV_EVENT_PORT_INITIALIZED: | |
1744 | /* not used by ULPs */ | |
1745 | return; | |
1746 | ||
1747 | case MLX5_DEV_EVENT_LID_CHANGE: | |
1748 | ibev.event = IB_EVENT_LID_CHANGE; | |
4d2f9bbb | 1749 | port = (u8)param; |
e126ba97 EC |
1750 | break; |
1751 | ||
1752 | case MLX5_DEV_EVENT_PKEY_CHANGE: | |
1753 | ibev.event = IB_EVENT_PKEY_CHANGE; | |
4d2f9bbb | 1754 | port = (u8)param; |
e126ba97 EC |
1755 | break; |
1756 | ||
1757 | case MLX5_DEV_EVENT_GUID_CHANGE: | |
1758 | ibev.event = IB_EVENT_GID_CHANGE; | |
4d2f9bbb | 1759 | port = (u8)param; |
e126ba97 EC |
1760 | break; |
1761 | ||
1762 | case MLX5_DEV_EVENT_CLIENT_REREG: | |
1763 | ibev.event = IB_EVENT_CLIENT_REREGISTER; | |
4d2f9bbb | 1764 | port = (u8)param; |
e126ba97 EC |
1765 | break; |
1766 | } | |
1767 | ||
1768 | ibev.device = &ibdev->ib_dev; | |
1769 | ibev.element.port_num = port; | |
1770 | ||
a0c84c32 EC |
1771 | if (port < 1 || port > ibdev->num_ports) { |
1772 | mlx5_ib_warn(ibdev, "warning: event on port %d\n", port); | |
1773 | return; | |
1774 | } | |
1775 | ||
e126ba97 EC |
1776 | if (ibdev->ib_active) |
1777 | ib_dispatch_event(&ibev); | |
1778 | } | |
1779 | ||
1780 | static void get_ext_port_caps(struct mlx5_ib_dev *dev) | |
1781 | { | |
1782 | int port; | |
1783 | ||
938fe83c | 1784 | for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) |
e126ba97 EC |
1785 | mlx5_query_ext_port_caps(dev, port); |
1786 | } | |
1787 | ||
1788 | static int get_port_caps(struct mlx5_ib_dev *dev) | |
1789 | { | |
1790 | struct ib_device_attr *dprops = NULL; | |
1791 | struct ib_port_attr *pprops = NULL; | |
f614fc15 | 1792 | int err = -ENOMEM; |
e126ba97 | 1793 | int port; |
2528e33e | 1794 | struct ib_udata uhw = {.inlen = 0, .outlen = 0}; |
e126ba97 EC |
1795 | |
1796 | pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); | |
1797 | if (!pprops) | |
1798 | goto out; | |
1799 | ||
1800 | dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); | |
1801 | if (!dprops) | |
1802 | goto out; | |
1803 | ||
2528e33e | 1804 | err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); |
e126ba97 EC |
1805 | if (err) { |
1806 | mlx5_ib_warn(dev, "query_device failed %d\n", err); | |
1807 | goto out; | |
1808 | } | |
1809 | ||
938fe83c | 1810 | for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { |
e126ba97 EC |
1811 | err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); |
1812 | if (err) { | |
938fe83c SM |
1813 | mlx5_ib_warn(dev, "query_port %d failed %d\n", |
1814 | port, err); | |
e126ba97 EC |
1815 | break; |
1816 | } | |
938fe83c SM |
1817 | dev->mdev->port_caps[port - 1].pkey_table_len = |
1818 | dprops->max_pkeys; | |
1819 | dev->mdev->port_caps[port - 1].gid_table_len = | |
1820 | pprops->gid_tbl_len; | |
e126ba97 EC |
1821 | mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", |
1822 | dprops->max_pkeys, pprops->gid_tbl_len); | |
1823 | } | |
1824 | ||
1825 | out: | |
1826 | kfree(pprops); | |
1827 | kfree(dprops); | |
1828 | ||
1829 | return err; | |
1830 | } | |
1831 | ||
1832 | static void destroy_umrc_res(struct mlx5_ib_dev *dev) | |
1833 | { | |
1834 | int err; | |
1835 | ||
1836 | err = mlx5_mr_cache_cleanup(dev); | |
1837 | if (err) | |
1838 | mlx5_ib_warn(dev, "mr cache cleanup failed\n"); | |
1839 | ||
1840 | mlx5_ib_destroy_qp(dev->umrc.qp); | |
1841 | ib_destroy_cq(dev->umrc.cq); | |
e126ba97 EC |
1842 | ib_dealloc_pd(dev->umrc.pd); |
1843 | } | |
1844 | ||
1845 | enum { | |
1846 | MAX_UMR_WR = 128, | |
1847 | }; | |
1848 | ||
1849 | static int create_umr_res(struct mlx5_ib_dev *dev) | |
1850 | { | |
1851 | struct ib_qp_init_attr *init_attr = NULL; | |
1852 | struct ib_qp_attr *attr = NULL; | |
1853 | struct ib_pd *pd; | |
1854 | struct ib_cq *cq; | |
1855 | struct ib_qp *qp; | |
8e37210b | 1856 | struct ib_cq_init_attr cq_attr = {}; |
e126ba97 EC |
1857 | int ret; |
1858 | ||
1859 | attr = kzalloc(sizeof(*attr), GFP_KERNEL); | |
1860 | init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); | |
1861 | if (!attr || !init_attr) { | |
1862 | ret = -ENOMEM; | |
1863 | goto error_0; | |
1864 | } | |
1865 | ||
1866 | pd = ib_alloc_pd(&dev->ib_dev); | |
1867 | if (IS_ERR(pd)) { | |
1868 | mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); | |
1869 | ret = PTR_ERR(pd); | |
1870 | goto error_0; | |
1871 | } | |
1872 | ||
8e37210b MB |
1873 | cq_attr.cqe = 128; |
1874 | cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, | |
1875 | &cq_attr); | |
e126ba97 EC |
1876 | if (IS_ERR(cq)) { |
1877 | mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); | |
1878 | ret = PTR_ERR(cq); | |
1879 | goto error_2; | |
1880 | } | |
1881 | ib_req_notify_cq(cq, IB_CQ_NEXT_COMP); | |
1882 | ||
1883 | init_attr->send_cq = cq; | |
1884 | init_attr->recv_cq = cq; | |
1885 | init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; | |
1886 | init_attr->cap.max_send_wr = MAX_UMR_WR; | |
1887 | init_attr->cap.max_send_sge = 1; | |
1888 | init_attr->qp_type = MLX5_IB_QPT_REG_UMR; | |
1889 | init_attr->port_num = 1; | |
1890 | qp = mlx5_ib_create_qp(pd, init_attr, NULL); | |
1891 | if (IS_ERR(qp)) { | |
1892 | mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); | |
1893 | ret = PTR_ERR(qp); | |
1894 | goto error_3; | |
1895 | } | |
1896 | qp->device = &dev->ib_dev; | |
1897 | qp->real_qp = qp; | |
1898 | qp->uobject = NULL; | |
1899 | qp->qp_type = MLX5_IB_QPT_REG_UMR; | |
1900 | ||
1901 | attr->qp_state = IB_QPS_INIT; | |
1902 | attr->port_num = 1; | |
1903 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | | |
1904 | IB_QP_PORT, NULL); | |
1905 | if (ret) { | |
1906 | mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); | |
1907 | goto error_4; | |
1908 | } | |
1909 | ||
1910 | memset(attr, 0, sizeof(*attr)); | |
1911 | attr->qp_state = IB_QPS_RTR; | |
1912 | attr->path_mtu = IB_MTU_256; | |
1913 | ||
1914 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); | |
1915 | if (ret) { | |
1916 | mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); | |
1917 | goto error_4; | |
1918 | } | |
1919 | ||
1920 | memset(attr, 0, sizeof(*attr)); | |
1921 | attr->qp_state = IB_QPS_RTS; | |
1922 | ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); | |
1923 | if (ret) { | |
1924 | mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); | |
1925 | goto error_4; | |
1926 | } | |
1927 | ||
1928 | dev->umrc.qp = qp; | |
1929 | dev->umrc.cq = cq; | |
e126ba97 EC |
1930 | dev->umrc.pd = pd; |
1931 | ||
1932 | sema_init(&dev->umrc.sem, MAX_UMR_WR); | |
1933 | ret = mlx5_mr_cache_init(dev); | |
1934 | if (ret) { | |
1935 | mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); | |
1936 | goto error_4; | |
1937 | } | |
1938 | ||
1939 | kfree(attr); | |
1940 | kfree(init_attr); | |
1941 | ||
1942 | return 0; | |
1943 | ||
1944 | error_4: | |
1945 | mlx5_ib_destroy_qp(qp); | |
1946 | ||
1947 | error_3: | |
1948 | ib_destroy_cq(cq); | |
1949 | ||
1950 | error_2: | |
e126ba97 EC |
1951 | ib_dealloc_pd(pd); |
1952 | ||
1953 | error_0: | |
1954 | kfree(attr); | |
1955 | kfree(init_attr); | |
1956 | return ret; | |
1957 | } | |
1958 | ||
1959 | static int create_dev_resources(struct mlx5_ib_resources *devr) | |
1960 | { | |
1961 | struct ib_srq_init_attr attr; | |
1962 | struct mlx5_ib_dev *dev; | |
bcf4c1ea | 1963 | struct ib_cq_init_attr cq_attr = {.cqe = 1}; |
e126ba97 EC |
1964 | int ret = 0; |
1965 | ||
1966 | dev = container_of(devr, struct mlx5_ib_dev, devr); | |
1967 | ||
1968 | devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); | |
1969 | if (IS_ERR(devr->p0)) { | |
1970 | ret = PTR_ERR(devr->p0); | |
1971 | goto error0; | |
1972 | } | |
1973 | devr->p0->device = &dev->ib_dev; | |
1974 | devr->p0->uobject = NULL; | |
1975 | atomic_set(&devr->p0->usecnt, 0); | |
1976 | ||
bcf4c1ea | 1977 | devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); |
e126ba97 EC |
1978 | if (IS_ERR(devr->c0)) { |
1979 | ret = PTR_ERR(devr->c0); | |
1980 | goto error1; | |
1981 | } | |
1982 | devr->c0->device = &dev->ib_dev; | |
1983 | devr->c0->uobject = NULL; | |
1984 | devr->c0->comp_handler = NULL; | |
1985 | devr->c0->event_handler = NULL; | |
1986 | devr->c0->cq_context = NULL; | |
1987 | atomic_set(&devr->c0->usecnt, 0); | |
1988 | ||
1989 | devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); | |
1990 | if (IS_ERR(devr->x0)) { | |
1991 | ret = PTR_ERR(devr->x0); | |
1992 | goto error2; | |
1993 | } | |
1994 | devr->x0->device = &dev->ib_dev; | |
1995 | devr->x0->inode = NULL; | |
1996 | atomic_set(&devr->x0->usecnt, 0); | |
1997 | mutex_init(&devr->x0->tgt_qp_mutex); | |
1998 | INIT_LIST_HEAD(&devr->x0->tgt_qp_list); | |
1999 | ||
2000 | devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); | |
2001 | if (IS_ERR(devr->x1)) { | |
2002 | ret = PTR_ERR(devr->x1); | |
2003 | goto error3; | |
2004 | } | |
2005 | devr->x1->device = &dev->ib_dev; | |
2006 | devr->x1->inode = NULL; | |
2007 | atomic_set(&devr->x1->usecnt, 0); | |
2008 | mutex_init(&devr->x1->tgt_qp_mutex); | |
2009 | INIT_LIST_HEAD(&devr->x1->tgt_qp_list); | |
2010 | ||
2011 | memset(&attr, 0, sizeof(attr)); | |
2012 | attr.attr.max_sge = 1; | |
2013 | attr.attr.max_wr = 1; | |
2014 | attr.srq_type = IB_SRQT_XRC; | |
2015 | attr.ext.xrc.cq = devr->c0; | |
2016 | attr.ext.xrc.xrcd = devr->x0; | |
2017 | ||
2018 | devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); | |
2019 | if (IS_ERR(devr->s0)) { | |
2020 | ret = PTR_ERR(devr->s0); | |
2021 | goto error4; | |
2022 | } | |
2023 | devr->s0->device = &dev->ib_dev; | |
2024 | devr->s0->pd = devr->p0; | |
2025 | devr->s0->uobject = NULL; | |
2026 | devr->s0->event_handler = NULL; | |
2027 | devr->s0->srq_context = NULL; | |
2028 | devr->s0->srq_type = IB_SRQT_XRC; | |
2029 | devr->s0->ext.xrc.xrcd = devr->x0; | |
2030 | devr->s0->ext.xrc.cq = devr->c0; | |
2031 | atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); | |
2032 | atomic_inc(&devr->s0->ext.xrc.cq->usecnt); | |
2033 | atomic_inc(&devr->p0->usecnt); | |
2034 | atomic_set(&devr->s0->usecnt, 0); | |
2035 | ||
4aa17b28 HA |
2036 | memset(&attr, 0, sizeof(attr)); |
2037 | attr.attr.max_sge = 1; | |
2038 | attr.attr.max_wr = 1; | |
2039 | attr.srq_type = IB_SRQT_BASIC; | |
2040 | devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); | |
2041 | if (IS_ERR(devr->s1)) { | |
2042 | ret = PTR_ERR(devr->s1); | |
2043 | goto error5; | |
2044 | } | |
2045 | devr->s1->device = &dev->ib_dev; | |
2046 | devr->s1->pd = devr->p0; | |
2047 | devr->s1->uobject = NULL; | |
2048 | devr->s1->event_handler = NULL; | |
2049 | devr->s1->srq_context = NULL; | |
2050 | devr->s1->srq_type = IB_SRQT_BASIC; | |
2051 | devr->s1->ext.xrc.cq = devr->c0; | |
2052 | atomic_inc(&devr->p0->usecnt); | |
2053 | atomic_set(&devr->s0->usecnt, 0); | |
2054 | ||
e126ba97 EC |
2055 | return 0; |
2056 | ||
4aa17b28 HA |
2057 | error5: |
2058 | mlx5_ib_destroy_srq(devr->s0); | |
e126ba97 EC |
2059 | error4: |
2060 | mlx5_ib_dealloc_xrcd(devr->x1); | |
2061 | error3: | |
2062 | mlx5_ib_dealloc_xrcd(devr->x0); | |
2063 | error2: | |
2064 | mlx5_ib_destroy_cq(devr->c0); | |
2065 | error1: | |
2066 | mlx5_ib_dealloc_pd(devr->p0); | |
2067 | error0: | |
2068 | return ret; | |
2069 | } | |
2070 | ||
2071 | static void destroy_dev_resources(struct mlx5_ib_resources *devr) | |
2072 | { | |
4aa17b28 | 2073 | mlx5_ib_destroy_srq(devr->s1); |
e126ba97 EC |
2074 | mlx5_ib_destroy_srq(devr->s0); |
2075 | mlx5_ib_dealloc_xrcd(devr->x0); | |
2076 | mlx5_ib_dealloc_xrcd(devr->x1); | |
2077 | mlx5_ib_destroy_cq(devr->c0); | |
2078 | mlx5_ib_dealloc_pd(devr->p0); | |
2079 | } | |
2080 | ||
e53505a8 AS |
2081 | static u32 get_core_cap_flags(struct ib_device *ibdev) |
2082 | { | |
2083 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
2084 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); | |
2085 | u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); | |
2086 | u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); | |
2087 | u32 ret = 0; | |
2088 | ||
2089 | if (ll == IB_LINK_LAYER_INFINIBAND) | |
2090 | return RDMA_CORE_PORT_IBA_IB; | |
2091 | ||
2092 | if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) | |
2093 | return 0; | |
2094 | ||
2095 | if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) | |
2096 | return 0; | |
2097 | ||
2098 | if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) | |
2099 | ret |= RDMA_CORE_PORT_IBA_ROCE; | |
2100 | ||
2101 | if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) | |
2102 | ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; | |
2103 | ||
2104 | return ret; | |
2105 | } | |
2106 | ||
7738613e IW |
2107 | static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, |
2108 | struct ib_port_immutable *immutable) | |
2109 | { | |
2110 | struct ib_port_attr attr; | |
2111 | int err; | |
2112 | ||
2113 | err = mlx5_ib_query_port(ibdev, port_num, &attr); | |
2114 | if (err) | |
2115 | return err; | |
2116 | ||
2117 | immutable->pkey_tbl_len = attr.pkey_tbl_len; | |
2118 | immutable->gid_tbl_len = attr.gid_tbl_len; | |
e53505a8 | 2119 | immutable->core_cap_flags = get_core_cap_flags(ibdev); |
337877a4 | 2120 | immutable->max_mad_size = IB_MGMT_MAD_SIZE; |
7738613e IW |
2121 | |
2122 | return 0; | |
2123 | } | |
2124 | ||
fc24fc5e AS |
2125 | static int mlx5_enable_roce(struct mlx5_ib_dev *dev) |
2126 | { | |
e53505a8 AS |
2127 | int err; |
2128 | ||
fc24fc5e | 2129 | dev->roce.nb.notifier_call = mlx5_netdev_event; |
e53505a8 AS |
2130 | err = register_netdevice_notifier(&dev->roce.nb); |
2131 | if (err) | |
2132 | return err; | |
2133 | ||
2134 | err = mlx5_nic_vport_enable_roce(dev->mdev); | |
2135 | if (err) | |
2136 | goto err_unregister_netdevice_notifier; | |
2137 | ||
2138 | return 0; | |
2139 | ||
2140 | err_unregister_netdevice_notifier: | |
2141 | unregister_netdevice_notifier(&dev->roce.nb); | |
2142 | return err; | |
fc24fc5e AS |
2143 | } |
2144 | ||
2145 | static void mlx5_disable_roce(struct mlx5_ib_dev *dev) | |
2146 | { | |
e53505a8 | 2147 | mlx5_nic_vport_disable_roce(dev->mdev); |
fc24fc5e AS |
2148 | unregister_netdevice_notifier(&dev->roce.nb); |
2149 | } | |
2150 | ||
9603b61d | 2151 | static void *mlx5_ib_add(struct mlx5_core_dev *mdev) |
e126ba97 | 2152 | { |
e126ba97 | 2153 | struct mlx5_ib_dev *dev; |
ebd61f68 AS |
2154 | enum rdma_link_layer ll; |
2155 | int port_type_cap; | |
e126ba97 EC |
2156 | int err; |
2157 | int i; | |
2158 | ||
ebd61f68 AS |
2159 | port_type_cap = MLX5_CAP_GEN(mdev, port_type); |
2160 | ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); | |
2161 | ||
e53505a8 | 2162 | if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) |
647241ea MD |
2163 | return NULL; |
2164 | ||
e126ba97 EC |
2165 | printk_once(KERN_INFO "%s", mlx5_version); |
2166 | ||
2167 | dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); | |
2168 | if (!dev) | |
9603b61d | 2169 | return NULL; |
e126ba97 | 2170 | |
9603b61d | 2171 | dev->mdev = mdev; |
e126ba97 | 2172 | |
fc24fc5e | 2173 | rwlock_init(&dev->roce.netdev_lock); |
e126ba97 EC |
2174 | err = get_port_caps(dev); |
2175 | if (err) | |
9603b61d | 2176 | goto err_dealloc; |
e126ba97 | 2177 | |
1b5daf11 MD |
2178 | if (mlx5_use_mad_ifc(dev)) |
2179 | get_ext_port_caps(dev); | |
e126ba97 | 2180 | |
e126ba97 EC |
2181 | MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); |
2182 | ||
2183 | strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX); | |
2184 | dev->ib_dev.owner = THIS_MODULE; | |
2185 | dev->ib_dev.node_type = RDMA_NODE_IB_CA; | |
c6790aa9 | 2186 | dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; |
938fe83c | 2187 | dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); |
e126ba97 | 2188 | dev->ib_dev.phys_port_cnt = dev->num_ports; |
233d05d2 SM |
2189 | dev->ib_dev.num_comp_vectors = |
2190 | dev->mdev->priv.eq_table.num_comp_vectors; | |
e126ba97 EC |
2191 | dev->ib_dev.dma_device = &mdev->pdev->dev; |
2192 | ||
2193 | dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; | |
2194 | dev->ib_dev.uverbs_cmd_mask = | |
2195 | (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | | |
2196 | (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | | |
2197 | (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | | |
2198 | (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | | |
2199 | (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | | |
2200 | (1ull << IB_USER_VERBS_CMD_REG_MR) | | |
2201 | (1ull << IB_USER_VERBS_CMD_DEREG_MR) | | |
2202 | (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | | |
2203 | (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | | |
2204 | (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | | |
2205 | (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | | |
2206 | (1ull << IB_USER_VERBS_CMD_CREATE_QP) | | |
2207 | (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | | |
2208 | (1ull << IB_USER_VERBS_CMD_QUERY_QP) | | |
2209 | (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | | |
2210 | (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | | |
2211 | (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | | |
2212 | (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | | |
2213 | (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | | |
2214 | (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | | |
2215 | (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | | |
2216 | (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | | |
2217 | (1ull << IB_USER_VERBS_CMD_OPEN_QP); | |
1707cb4a | 2218 | dev->ib_dev.uverbs_ex_cmd_mask = |
d4584ddf MB |
2219 | (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | |
2220 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | | |
2221 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); | |
e126ba97 EC |
2222 | |
2223 | dev->ib_dev.query_device = mlx5_ib_query_device; | |
2224 | dev->ib_dev.query_port = mlx5_ib_query_port; | |
ebd61f68 | 2225 | dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; |
fc24fc5e AS |
2226 | if (ll == IB_LINK_LAYER_ETHERNET) |
2227 | dev->ib_dev.get_netdev = mlx5_ib_get_netdev; | |
e126ba97 | 2228 | dev->ib_dev.query_gid = mlx5_ib_query_gid; |
3cca2606 AS |
2229 | dev->ib_dev.add_gid = mlx5_ib_add_gid; |
2230 | dev->ib_dev.del_gid = mlx5_ib_del_gid; | |
e126ba97 EC |
2231 | dev->ib_dev.query_pkey = mlx5_ib_query_pkey; |
2232 | dev->ib_dev.modify_device = mlx5_ib_modify_device; | |
2233 | dev->ib_dev.modify_port = mlx5_ib_modify_port; | |
2234 | dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; | |
2235 | dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; | |
2236 | dev->ib_dev.mmap = mlx5_ib_mmap; | |
2237 | dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; | |
2238 | dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; | |
2239 | dev->ib_dev.create_ah = mlx5_ib_create_ah; | |
2240 | dev->ib_dev.query_ah = mlx5_ib_query_ah; | |
2241 | dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; | |
2242 | dev->ib_dev.create_srq = mlx5_ib_create_srq; | |
2243 | dev->ib_dev.modify_srq = mlx5_ib_modify_srq; | |
2244 | dev->ib_dev.query_srq = mlx5_ib_query_srq; | |
2245 | dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; | |
2246 | dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; | |
2247 | dev->ib_dev.create_qp = mlx5_ib_create_qp; | |
2248 | dev->ib_dev.modify_qp = mlx5_ib_modify_qp; | |
2249 | dev->ib_dev.query_qp = mlx5_ib_query_qp; | |
2250 | dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; | |
2251 | dev->ib_dev.post_send = mlx5_ib_post_send; | |
2252 | dev->ib_dev.post_recv = mlx5_ib_post_recv; | |
2253 | dev->ib_dev.create_cq = mlx5_ib_create_cq; | |
2254 | dev->ib_dev.modify_cq = mlx5_ib_modify_cq; | |
2255 | dev->ib_dev.resize_cq = mlx5_ib_resize_cq; | |
2256 | dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; | |
2257 | dev->ib_dev.poll_cq = mlx5_ib_poll_cq; | |
2258 | dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; | |
2259 | dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; | |
2260 | dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; | |
2261 | dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; | |
2262 | dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; | |
2263 | dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; | |
2264 | dev->ib_dev.process_mad = mlx5_ib_process_mad; | |
9bee178b | 2265 | dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; |
8a187ee5 | 2266 | dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; |
d5436ba0 | 2267 | dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; |
7738613e | 2268 | dev->ib_dev.get_port_immutable = mlx5_port_immutable; |
e126ba97 | 2269 | |
938fe83c | 2270 | mlx5_ib_internal_fill_odp_caps(dev); |
8cdd312c | 2271 | |
938fe83c | 2272 | if (MLX5_CAP_GEN(mdev, xrc)) { |
e126ba97 EC |
2273 | dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; |
2274 | dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; | |
2275 | dev->ib_dev.uverbs_cmd_mask |= | |
2276 | (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | | |
2277 | (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); | |
2278 | } | |
2279 | ||
048ccca8 | 2280 | if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == |
038d2ef8 MG |
2281 | IB_LINK_LAYER_ETHERNET) { |
2282 | dev->ib_dev.create_flow = mlx5_ib_create_flow; | |
2283 | dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; | |
2284 | dev->ib_dev.uverbs_ex_cmd_mask |= | |
2285 | (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | | |
2286 | (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW); | |
2287 | } | |
e126ba97 EC |
2288 | err = init_node_data(dev); |
2289 | if (err) | |
233d05d2 | 2290 | goto err_dealloc; |
e126ba97 | 2291 | |
038d2ef8 | 2292 | mutex_init(&dev->flow_db.lock); |
e126ba97 | 2293 | mutex_init(&dev->cap_mask_mutex); |
e126ba97 | 2294 | |
fc24fc5e AS |
2295 | if (ll == IB_LINK_LAYER_ETHERNET) { |
2296 | err = mlx5_enable_roce(dev); | |
2297 | if (err) | |
2298 | goto err_dealloc; | |
2299 | } | |
2300 | ||
e126ba97 EC |
2301 | err = create_dev_resources(&dev->devr); |
2302 | if (err) | |
fc24fc5e | 2303 | goto err_disable_roce; |
e126ba97 | 2304 | |
6aec21f6 | 2305 | err = mlx5_ib_odp_init_one(dev); |
281d1a92 | 2306 | if (err) |
e126ba97 EC |
2307 | goto err_rsrc; |
2308 | ||
6aec21f6 HE |
2309 | err = ib_register_device(&dev->ib_dev, NULL); |
2310 | if (err) | |
2311 | goto err_odp; | |
2312 | ||
e126ba97 EC |
2313 | err = create_umr_res(dev); |
2314 | if (err) | |
2315 | goto err_dev; | |
2316 | ||
2317 | for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { | |
281d1a92 WY |
2318 | err = device_create_file(&dev->ib_dev.dev, |
2319 | mlx5_class_attributes[i]); | |
2320 | if (err) | |
e126ba97 EC |
2321 | goto err_umrc; |
2322 | } | |
2323 | ||
2324 | dev->ib_active = true; | |
2325 | ||
9603b61d | 2326 | return dev; |
e126ba97 EC |
2327 | |
2328 | err_umrc: | |
2329 | destroy_umrc_res(dev); | |
2330 | ||
2331 | err_dev: | |
2332 | ib_unregister_device(&dev->ib_dev); | |
2333 | ||
6aec21f6 HE |
2334 | err_odp: |
2335 | mlx5_ib_odp_remove_one(dev); | |
2336 | ||
e126ba97 EC |
2337 | err_rsrc: |
2338 | destroy_dev_resources(&dev->devr); | |
2339 | ||
fc24fc5e AS |
2340 | err_disable_roce: |
2341 | if (ll == IB_LINK_LAYER_ETHERNET) | |
2342 | mlx5_disable_roce(dev); | |
2343 | ||
9603b61d | 2344 | err_dealloc: |
e126ba97 EC |
2345 | ib_dealloc_device((struct ib_device *)dev); |
2346 | ||
9603b61d | 2347 | return NULL; |
e126ba97 EC |
2348 | } |
2349 | ||
9603b61d | 2350 | static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) |
e126ba97 | 2351 | { |
9603b61d | 2352 | struct mlx5_ib_dev *dev = context; |
fc24fc5e | 2353 | enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); |
6aec21f6 | 2354 | |
e126ba97 | 2355 | ib_unregister_device(&dev->ib_dev); |
eefd56e5 | 2356 | destroy_umrc_res(dev); |
6aec21f6 | 2357 | mlx5_ib_odp_remove_one(dev); |
e126ba97 | 2358 | destroy_dev_resources(&dev->devr); |
fc24fc5e AS |
2359 | if (ll == IB_LINK_LAYER_ETHERNET) |
2360 | mlx5_disable_roce(dev); | |
e126ba97 EC |
2361 | ib_dealloc_device(&dev->ib_dev); |
2362 | } | |
2363 | ||
9603b61d JM |
2364 | static struct mlx5_interface mlx5_ib_interface = { |
2365 | .add = mlx5_ib_add, | |
2366 | .remove = mlx5_ib_remove, | |
2367 | .event = mlx5_ib_event, | |
64613d94 | 2368 | .protocol = MLX5_INTERFACE_PROTOCOL_IB, |
e126ba97 EC |
2369 | }; |
2370 | ||
2371 | static int __init mlx5_ib_init(void) | |
2372 | { | |
6aec21f6 HE |
2373 | int err; |
2374 | ||
9603b61d JM |
2375 | if (deprecated_prof_sel != 2) |
2376 | pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n"); | |
2377 | ||
6aec21f6 HE |
2378 | err = mlx5_ib_odp_init(); |
2379 | if (err) | |
2380 | return err; | |
2381 | ||
2382 | err = mlx5_register_interface(&mlx5_ib_interface); | |
2383 | if (err) | |
2384 | goto clean_odp; | |
2385 | ||
2386 | return err; | |
2387 | ||
2388 | clean_odp: | |
2389 | mlx5_ib_odp_cleanup(); | |
2390 | return err; | |
e126ba97 EC |
2391 | } |
2392 | ||
2393 | static void __exit mlx5_ib_cleanup(void) | |
2394 | { | |
9603b61d | 2395 | mlx5_unregister_interface(&mlx5_ib_interface); |
6aec21f6 | 2396 | mlx5_ib_odp_cleanup(); |
e126ba97 EC |
2397 | } |
2398 | ||
2399 | module_init(mlx5_ib_init); | |
2400 | module_exit(mlx5_ib_cleanup); |