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IB/mlx5: Implements disassociate_ucontext API
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
7c2344c3 45#include <linux/delay.h>
e126ba97 46#include <rdma/ib_user_verbs.h>
3f89a643 47#include <rdma/ib_addr.h>
2811ba51 48#include <rdma/ib_cache.h>
ada68c31 49#include <linux/mlx5/port.h>
1b5daf11 50#include <linux/mlx5/vport.h>
7c2344c3 51#include <linux/list.h>
e126ba97
EC		 52#include <rdma/ib_smi.h>
53#include <rdma/ib_umem.h>
038d2ef8
MG		 54#include <linux/in.h>
55#include <linux/etherdevice.h>
56#include <linux/mlx5/fs.h>
e126ba97
EC		 57#include "user.h"
58#include "mlx5_ib.h"
59
60#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 61#define DRIVER_VERSION "2.2-1"
62#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 63
64MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRIVER_VERSION);
68
9603b61d
JM		 69static int deprecated_prof_sel = 2;
70module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
71MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 72
73static char mlx5_version[] =
74 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
75 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
76
da7525d2
EBE		 77enum {
78 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
79};
80
1b5daf11 81static enum rdma_link_layer
ebd61f68 82mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 83{
ebd61f68 84 switch (port_type_cap) {
1b5daf11
MD		 85 case MLX5_CAP_PORT_TYPE_IB:
86 return IB_LINK_LAYER_INFINIBAND;
87 case MLX5_CAP_PORT_TYPE_ETH:
88 return IB_LINK_LAYER_ETHERNET;
89 default:
90 return IB_LINK_LAYER_UNSPECIFIED;
91 }
92}
93
ebd61f68
AS		 94static enum rdma_link_layer
95mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
96{
97 struct mlx5_ib_dev *dev = to_mdev(device);
98 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
99
100 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
101}
102
fc24fc5e
AS		 103static int mlx5_netdev_event(struct notifier_block *this,
104 unsigned long event, void *ptr)
105{
106 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
107 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
108 roce.nb);
109
110 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
111 return NOTIFY_DONE;
112
113 write_lock(&ibdev->roce.netdev_lock);
114 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
115 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
116 write_unlock(&ibdev->roce.netdev_lock);
117
118 return NOTIFY_DONE;
119}
120
121static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
122 u8 port_num)
123{
124 struct mlx5_ib_dev *ibdev = to_mdev(device);
125 struct net_device *ndev;
126
127 /* Ensure ndev does not disappear before we invoke dev_hold()
128 */
129 read_lock(&ibdev->roce.netdev_lock);
130 ndev = ibdev->roce.netdev;
131 if (ndev)
132 dev_hold(ndev);
133 read_unlock(&ibdev->roce.netdev_lock);
134
135 return ndev;
136}
137
3f89a643
AS		 138static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
139 struct ib_port_attr *props)
140{
141 struct mlx5_ib_dev *dev = to_mdev(device);
142 struct net_device *ndev;
143 enum ib_mtu ndev_ib_mtu;
c876a1b7 144 u16 qkey_viol_cntr;
3f89a643
AS		 145
146 memset(props, 0, sizeof(*props));
147
148 props->port_cap_flags |= IB_PORT_CM_SUP;
149 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
150
151 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
152 roce_address_table_size);
153 props->max_mtu = IB_MTU_4096;
154 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
155 props->pkey_tbl_len = 1;
156 props->state = IB_PORT_DOWN;
157 props->phys_state = 3;
158
c876a1b7
LR		 159 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
160 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 161
162 ndev = mlx5_ib_get_netdev(device, port_num);
163 if (!ndev)
164 return 0;
165
166 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
167 props->state = IB_PORT_ACTIVE;
168 props->phys_state = 5;
169 }
170
171 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
172
173 dev_put(ndev);
174
175 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
176
177 props->active_width = IB_WIDTH_4X; /* TODO */
178 props->active_speed = IB_SPEED_QDR; /* TODO */
179
180 return 0;
181}
182
3cca2606
AS		 183static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
184 const struct ib_gid_attr *attr,
185 void *mlx5_addr)
186{
187#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
188 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
189 source_l3_address);
190 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
191 source_mac_47_32);
192
193 if (!gid)
194 return;
195
196 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
197
198 if (is_vlan_dev(attr->ndev)) {
199 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
200 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
201 }
202
203 switch (attr->gid_type) {
204 case IB_GID_TYPE_IB:
205 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
206 break;
207 case IB_GID_TYPE_ROCE_UDP_ENCAP:
208 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
209 break;
210
211 default:
212 WARN_ON(true);
213 }
214
215 if (attr->gid_type != IB_GID_TYPE_IB) {
216 if (ipv6_addr_v4mapped((void *)gid))
217 MLX5_SET_RA(mlx5_addr, roce_l3_type,
218 MLX5_ROCE_L3_TYPE_IPV4);
219 else
220 MLX5_SET_RA(mlx5_addr, roce_l3_type,
221 MLX5_ROCE_L3_TYPE_IPV6);
222 }
223
224 if ((attr->gid_type == IB_GID_TYPE_IB) ||
225 !ipv6_addr_v4mapped((void *)gid))
226 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
227 else
228 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
229}
230
231static int set_roce_addr(struct ib_device *device, u8 port_num,
232 unsigned int index,
233 const union ib_gid *gid,
234 const struct ib_gid_attr *attr)
235{
236 struct mlx5_ib_dev *dev = to_mdev(device);
237 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
238 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
239 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
240 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
241
242 if (ll != IB_LINK_LAYER_ETHERNET)
243 return -EINVAL;
244
245 memset(in, 0, sizeof(in));
246
247 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
248
249 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
250 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
251
252 memset(out, 0, sizeof(out));
253 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
254}
255
256static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
257 unsigned int index, const union ib_gid *gid,
258 const struct ib_gid_attr *attr,
259 __always_unused void **context)
260{
261 return set_roce_addr(device, port_num, index, gid, attr);
262}
263
264static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
265 unsigned int index, __always_unused void **context)
266{
267 return set_roce_addr(device, port_num, index, NULL, NULL);
268}
269
2811ba51
AS		 270__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
271 int index)
272{
273 struct ib_gid_attr attr;
274 union ib_gid gid;
275
276 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
277 return 0;
278
279 if (!attr.ndev)
280 return 0;
281
282 dev_put(attr.ndev);
283
284 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
285 return 0;
286
287 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
288}
289
1b5daf11
MD		 290static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
291{
d603c809 292 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
1b5daf11
MD		 293}
294
295enum {
296 MLX5_VPORT_ACCESS_METHOD_MAD,
297 MLX5_VPORT_ACCESS_METHOD_HCA,
298 MLX5_VPORT_ACCESS_METHOD_NIC,
299};
300
301static int mlx5_get_vport_access_method(struct ib_device *ibdev)
302{
303 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
304 return MLX5_VPORT_ACCESS_METHOD_MAD;
305
ebd61f68 306 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 307 IB_LINK_LAYER_ETHERNET)
308 return MLX5_VPORT_ACCESS_METHOD_NIC;
309
310 return MLX5_VPORT_ACCESS_METHOD_HCA;
311}
312
da7525d2
EBE		 313static void get_atomic_caps(struct mlx5_ib_dev *dev,
314 struct ib_device_attr *props)
315{
316 u8 tmp;
317 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
318 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
319 u8 atomic_req_8B_endianness_mode =
320 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
321
322 /* Check if HW supports 8 bytes standard atomic operations and capable
323 * of host endianness respond
324 */
325 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
326 if (((atomic_operations & tmp) == tmp) &&
327 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
328 (atomic_req_8B_endianness_mode)) {
329 props->atomic_cap = IB_ATOMIC_HCA;
330 } else {
331 props->atomic_cap = IB_ATOMIC_NONE;
332 }
333}
334
1b5daf11
MD		 335static int mlx5_query_system_image_guid(struct ib_device *ibdev,
336 __be64 *sys_image_guid)
337{
338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
339 struct mlx5_core_dev *mdev = dev->mdev;
340 u64 tmp;
341 int err;
342
343 switch (mlx5_get_vport_access_method(ibdev)) {
344 case MLX5_VPORT_ACCESS_METHOD_MAD:
345 return mlx5_query_mad_ifc_system_image_guid(ibdev,
346 sys_image_guid);
347
348 case MLX5_VPORT_ACCESS_METHOD_HCA:
349 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 350 break;
351
352 case MLX5_VPORT_ACCESS_METHOD_NIC:
353 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
354 break;
1b5daf11
MD		 355
356 default:
357 return -EINVAL;
358 }
3f89a643
AS		 359
360 if (!err)
361 *sys_image_guid = cpu_to_be64(tmp);
362
363 return err;
364
1b5daf11
MD		 365}
366
367static int mlx5_query_max_pkeys(struct ib_device *ibdev,
368 u16 *max_pkeys)
369{
370 struct mlx5_ib_dev *dev = to_mdev(ibdev);
371 struct mlx5_core_dev *mdev = dev->mdev;
372
373 switch (mlx5_get_vport_access_method(ibdev)) {
374 case MLX5_VPORT_ACCESS_METHOD_MAD:
375 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
376
377 case MLX5_VPORT_ACCESS_METHOD_HCA:
378 case MLX5_VPORT_ACCESS_METHOD_NIC:
379 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
380 pkey_table_size));
381 return 0;
382
383 default:
384 return -EINVAL;
385 }
386}
387
388static int mlx5_query_vendor_id(struct ib_device *ibdev,
389 u32 *vendor_id)
390{
391 struct mlx5_ib_dev *dev = to_mdev(ibdev);
392
393 switch (mlx5_get_vport_access_method(ibdev)) {
394 case MLX5_VPORT_ACCESS_METHOD_MAD:
395 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
396
397 case MLX5_VPORT_ACCESS_METHOD_HCA:
398 case MLX5_VPORT_ACCESS_METHOD_NIC:
399 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
400
401 default:
402 return -EINVAL;
403 }
404}
405
406static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
407 __be64 *node_guid)
408{
409 u64 tmp;
410 int err;
411
412 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
413 case MLX5_VPORT_ACCESS_METHOD_MAD:
414 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
415
416 case MLX5_VPORT_ACCESS_METHOD_HCA:
417 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 418 break;
419
420 case MLX5_VPORT_ACCESS_METHOD_NIC:
421 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
422 break;
1b5daf11
MD		 423
424 default:
425 return -EINVAL;
426 }
3f89a643
AS		 427
428 if (!err)
429 *node_guid = cpu_to_be64(tmp);
430
431 return err;
1b5daf11
MD		 432}
433
434struct mlx5_reg_node_desc {
435 u8 desc[64];
436};
437
438static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
439{
440 struct mlx5_reg_node_desc in;
441
442 if (mlx5_use_mad_ifc(dev))
443 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
444
445 memset(&in, 0, sizeof(in));
446
447 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
448 sizeof(struct mlx5_reg_node_desc),
449 MLX5_REG_NODE_DESC, 0, 0);
450}
451
e126ba97 452static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 453 struct ib_device_attr *props,
454 struct ib_udata *uhw)
e126ba97
EC		 455{
456 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 457 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 458 int err = -ENOMEM;
459 int max_rq_sg;
460 int max_sq_sg;
e0238a6a 461 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 462
2528e33e
MB		 463 if (uhw->inlen || uhw->outlen)
464 return -EINVAL;
465
1b5daf11
MD		 466 memset(props, 0, sizeof(*props));
467 err = mlx5_query_system_image_guid(ibdev,
468 &props->sys_image_guid);
469 if (err)
470 return err;
e126ba97 471
1b5daf11 472 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 473 if (err)
1b5daf11 474 return err;
e126ba97 475
1b5daf11
MD		 476 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
477 if (err)
478 return err;
e126ba97 479
9603b61d
JM		 480 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
481 (fw_rev_min(dev->mdev) << 16) |
482 fw_rev_sub(dev->mdev);
e126ba97
EC		 483 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
484 IB_DEVICE_PORT_ACTIVE_EVENT |
485 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 486 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 487
488 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 489 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 490 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 491 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 492 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 493 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 494 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 495 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 496 if (MLX5_CAP_GEN(mdev, imaicl)) {
497 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
498 IB_DEVICE_MEM_WINDOW_TYPE_2B;
499 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 500 /* We support 'Gappy' memory registration too */
501 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 502 }
e126ba97 503 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 504 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 505 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
506 /* At this stage no support for signature handover */
507 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
508 IB_PROT_T10DIF_TYPE_2 |
509 IB_PROT_T10DIF_TYPE_3;
510 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
511 IB_GUARD_T10DIF_CSUM;
512 }
938fe83c 513 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 514 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 515
88115fe7
BW		 516 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
517 (MLX5_CAP_ETH(dev->mdev, csum_cap)))
518 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
519
f0313965
ES		 520 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
521 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
522 props->device_cap_flags |= IB_DEVICE_UD_TSO;
523 }
524
cff5a0f3
MD		 525 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
526 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
527 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
528
da6d6ba3
MG		 529 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
530 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
531
1b5daf11
MD		 532 props->vendor_part_id = mdev->pdev->device;
533 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 534
535 props->max_mr_size = ~0ull;
e0238a6a 536 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 537 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
538 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
539 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
540 sizeof(struct mlx5_wqe_data_seg);
541 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
542 sizeof(struct mlx5_wqe_ctrl_seg)) /
543 sizeof(struct mlx5_wqe_data_seg);
e126ba97 544 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 545 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 546 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 547 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 548 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
549 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
550 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
551 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
552 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
553 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
554 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 555 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 556 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 557 props->max_fast_reg_page_list_len =
558 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 559 get_atomic_caps(dev, props);
81bea28f 560 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 561 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
562 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 563 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
564 props->max_mcast_grp;
565 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 566 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
567 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 568
8cdd312c 569#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 570 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 571 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
572 props->odp_caps = dev->odp_caps;
573#endif
574
051f2630
LR		 575 if (MLX5_CAP_GEN(mdev, cd))
576 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
577
eff901d3
EC		 578 if (!mlx5_core_is_pf(mdev))
579 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
580
1b5daf11 581 return 0;
e126ba97
EC		 582}
583
1b5daf11
MD		 584enum mlx5_ib_width {
585 MLX5_IB_WIDTH_1X = 1 << 0,
586 MLX5_IB_WIDTH_2X = 1 << 1,
587 MLX5_IB_WIDTH_4X = 1 << 2,
588 MLX5_IB_WIDTH_8X = 1 << 3,
589 MLX5_IB_WIDTH_12X = 1 << 4
590};
591
592static int translate_active_width(struct ib_device *ibdev, u8 active_width,
593 u8 *ib_width)
e126ba97
EC		 594{
595 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 596 int err = 0;
597
598 if (active_width & MLX5_IB_WIDTH_1X) {
599 *ib_width = IB_WIDTH_1X;
600 } else if (active_width & MLX5_IB_WIDTH_2X) {
601 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
602 (int)active_width);
603 err = -EINVAL;
604 } else if (active_width & MLX5_IB_WIDTH_4X) {
605 *ib_width = IB_WIDTH_4X;
606 } else if (active_width & MLX5_IB_WIDTH_8X) {
607 *ib_width = IB_WIDTH_8X;
608 } else if (active_width & MLX5_IB_WIDTH_12X) {
609 *ib_width = IB_WIDTH_12X;
610 } else {
611 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
612 (int)active_width);
613 err = -EINVAL;
e126ba97
EC		 614 }
615
1b5daf11
MD		 616 return err;
617}
e126ba97 618
1b5daf11
MD		 619static int mlx5_mtu_to_ib_mtu(int mtu)
620{
621 switch (mtu) {
622 case 256: return 1;
623 case 512: return 2;
624 case 1024: return 3;
625 case 2048: return 4;
626 case 4096: return 5;
627 default:
628 pr_warn("invalid mtu\n");
629 return -1;
e126ba97 630 }
1b5daf11 631}
e126ba97 632
1b5daf11
MD		 633enum ib_max_vl_num {
634 __IB_MAX_VL_0 = 1,
635 __IB_MAX_VL_0_1 = 2,
636 __IB_MAX_VL_0_3 = 3,
637 __IB_MAX_VL_0_7 = 4,
638 __IB_MAX_VL_0_14 = 5,
639};
e126ba97 640
1b5daf11
MD		 641enum mlx5_vl_hw_cap {
642 MLX5_VL_HW_0 = 1,
643 MLX5_VL_HW_0_1 = 2,
644 MLX5_VL_HW_0_2 = 3,
645 MLX5_VL_HW_0_3 = 4,
646 MLX5_VL_HW_0_4 = 5,
647 MLX5_VL_HW_0_5 = 6,
648 MLX5_VL_HW_0_6 = 7,
649 MLX5_VL_HW_0_7 = 8,
650 MLX5_VL_HW_0_14 = 15
651};
e126ba97 652
1b5daf11
MD		 653static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
654 u8 *max_vl_num)
655{
656 switch (vl_hw_cap) {
657 case MLX5_VL_HW_0:
658 *max_vl_num = __IB_MAX_VL_0;
659 break;
660 case MLX5_VL_HW_0_1:
661 *max_vl_num = __IB_MAX_VL_0_1;
662 break;
663 case MLX5_VL_HW_0_3:
664 *max_vl_num = __IB_MAX_VL_0_3;
665 break;
666 case MLX5_VL_HW_0_7:
667 *max_vl_num = __IB_MAX_VL_0_7;
668 break;
669 case MLX5_VL_HW_0_14:
670 *max_vl_num = __IB_MAX_VL_0_14;
671 break;
e126ba97 672
1b5daf11
MD		 673 default:
674 return -EINVAL;
e126ba97 675 }
e126ba97 676
1b5daf11 677 return 0;
e126ba97
EC		 678}
679
1b5daf11
MD		 680static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
681 struct ib_port_attr *props)
e126ba97 682{
1b5daf11
MD		 683 struct mlx5_ib_dev *dev = to_mdev(ibdev);
684 struct mlx5_core_dev *mdev = dev->mdev;
685 struct mlx5_hca_vport_context *rep;
046339ea
SM		 686 u16 max_mtu;
687 u16 oper_mtu;
1b5daf11
MD		 688 int err;
689 u8 ib_link_width_oper;
690 u8 vl_hw_cap;
e126ba97 691
1b5daf11
MD		 692 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
693 if (!rep) {
694 err = -ENOMEM;
e126ba97 695 goto out;
e126ba97 696 }
e126ba97 697
1b5daf11 698 memset(props, 0, sizeof(*props));
e126ba97 699
1b5daf11 700 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 701 if (err)
702 goto out;
703
1b5daf11
MD		 704 props->lid = rep->lid;
705 props->lmc = rep->lmc;
706 props->sm_lid = rep->sm_lid;
707 props->sm_sl = rep->sm_sl;
708 props->state = rep->vport_state;
709 props->phys_state = rep->port_physical_state;
710 props->port_cap_flags = rep->cap_mask1;
711 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
712 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
713 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
714 props->bad_pkey_cntr = rep->pkey_violation_counter;
715 props->qkey_viol_cntr = rep->qkey_violation_counter;
716 props->subnet_timeout = rep->subnet_timeout;
717 props->init_type_reply = rep->init_type_reply;
eff901d3 718 props->grh_required = rep->grh_required;
e126ba97 719
1b5daf11
MD		 720 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
721 if (err)
e126ba97 722 goto out;
e126ba97 723
1b5daf11
MD		 724 err = translate_active_width(ibdev, ib_link_width_oper,
725 &props->active_width);
726 if (err)
727 goto out;
728 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
729 port);
e126ba97
EC		 730 if (err)
731 goto out;
732
facc9699 733 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 734
1b5daf11 735 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 736
facc9699 737 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 738
1b5daf11 739 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 740
1b5daf11
MD		 741 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
742 if (err)
743 goto out;
e126ba97 744
1b5daf11
MD		 745 err = translate_max_vl_num(ibdev, vl_hw_cap,
746 &props->max_vl_num);
e126ba97 747out:
1b5daf11 748 kfree(rep);
e126ba97
EC		 749 return err;
750}
751
1b5daf11
MD		 752int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
753 struct ib_port_attr *props)
e126ba97 754{
1b5daf11
MD		 755 switch (mlx5_get_vport_access_method(ibdev)) {
756 case MLX5_VPORT_ACCESS_METHOD_MAD:
757 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 758
1b5daf11
MD		 759 case MLX5_VPORT_ACCESS_METHOD_HCA:
760 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 761
3f89a643
AS		 762 case MLX5_VPORT_ACCESS_METHOD_NIC:
763 return mlx5_query_port_roce(ibdev, port, props);
764
1b5daf11
MD		 765 default:
766 return -EINVAL;
767 }
768}
e126ba97 769
1b5daf11
MD		 770static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
771 union ib_gid *gid)
772{
773 struct mlx5_ib_dev *dev = to_mdev(ibdev);
774 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 775
1b5daf11
MD		 776 switch (mlx5_get_vport_access_method(ibdev)) {
777 case MLX5_VPORT_ACCESS_METHOD_MAD:
778 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 779
1b5daf11
MD		 780 case MLX5_VPORT_ACCESS_METHOD_HCA:
781 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
782
783 default:
784 return -EINVAL;
785 }
e126ba97 786
e126ba97
EC		 787}
788
1b5daf11
MD		 789static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
790 u16 *pkey)
791{
792 struct mlx5_ib_dev *dev = to_mdev(ibdev);
793 struct mlx5_core_dev *mdev = dev->mdev;
794
795 switch (mlx5_get_vport_access_method(ibdev)) {
796 case MLX5_VPORT_ACCESS_METHOD_MAD:
797 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
798
799 case MLX5_VPORT_ACCESS_METHOD_HCA:
800 case MLX5_VPORT_ACCESS_METHOD_NIC:
801 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
802 pkey);
803 default:
804 return -EINVAL;
805 }
806}
e126ba97
EC		 807
808static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
809 struct ib_device_modify *props)
810{
811 struct mlx5_ib_dev *dev = to_mdev(ibdev);
812 struct mlx5_reg_node_desc in;
813 struct mlx5_reg_node_desc out;
814 int err;
815
816 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
817 return -EOPNOTSUPP;
818
819 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
820 return 0;
821
822 /*
823 * If possible, pass node desc to FW, so it can generate
824 * a 144 trap. If cmd fails, just ignore.
825 */
826 memcpy(&in, props->node_desc, 64);
9603b61d 827 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 828 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
829 if (err)
830 return err;
831
832 memcpy(ibdev->node_desc, props->node_desc, 64);
833
834 return err;
835}
836
837static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
838 struct ib_port_modify *props)
839{
840 struct mlx5_ib_dev *dev = to_mdev(ibdev);
841 struct ib_port_attr attr;
842 u32 tmp;
843 int err;
844
845 mutex_lock(&dev->cap_mask_mutex);
846
847 err = mlx5_ib_query_port(ibdev, port, &attr);
848 if (err)
849 goto out;
850
851 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
852 ~props->clr_port_cap_mask;
853
9603b61d 854 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 855
856out:
857 mutex_unlock(&dev->cap_mask_mutex);
858 return err;
859}
860
861static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
862 struct ib_udata *udata)
863{
864 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 865 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
866 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 867 struct mlx5_ib_ucontext *context;
868 struct mlx5_uuar_info *uuari;
869 struct mlx5_uar *uars;
c1be5232 870 int gross_uuars;
e126ba97 871 int num_uars;
78c0f98c 872 int ver;
e126ba97
EC		 873 int uuarn;
874 int err;
875 int i;
f241e749 876 size_t reqlen;
a168a41c
MD		 877 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
878 max_cqe_version);
e126ba97
EC		 879
880 if (!dev->ib_active)
881 return ERR_PTR(-EAGAIN);
882
dfbee859
HA		 883 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
884 return ERR_PTR(-EINVAL);
885
78c0f98c
EC		 886 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
887 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
888 ver = 0;
a168a41c 889 else if (reqlen >= min_req_v2)
78c0f98c
EC		 890 ver = 2;
891 else
892 return ERR_PTR(-EINVAL);
893
b368d7cb 894 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 895 if (err)
896 return ERR_PTR(err);
897
b368d7cb 898 if (req.flags)
78c0f98c
EC		 899 return ERR_PTR(-EINVAL);
900
e126ba97
EC		 901 if (req.total_num_uuars > MLX5_MAX_UUARS)
902 return ERR_PTR(-ENOMEM);
903
904 if (req.total_num_uuars == 0)
905 return ERR_PTR(-EINVAL);
906
f72300c5 907 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 908 return ERR_PTR(-EOPNOTSUPP);
909
910 if (reqlen > sizeof(req) &&
911 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 912 reqlen - sizeof(req)))
b368d7cb
MB		 913 return ERR_PTR(-EOPNOTSUPP);
914
c1be5232
EC		 915 req.total_num_uuars = ALIGN(req.total_num_uuars,
916 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 917 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
918 return ERR_PTR(-EINVAL);
919
c1be5232
EC		 920 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
921 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c 922 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 923 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
924 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
938fe83c
SM		 925 resp.cache_line_size = L1_CACHE_BYTES;
926 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
927 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
928 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
929 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
930 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 931 resp.cqe_version = min_t(__u8,
932 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
933 req.max_cqe_version);
b368d7cb
MB		 934 resp.response_length = min(offsetof(typeof(resp), response_length) +
935 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 936
937 context = kzalloc(sizeof(*context), GFP_KERNEL);
938 if (!context)
939 return ERR_PTR(-ENOMEM);
940
941 uuari = &context->uuari;
942 mutex_init(&uuari->lock);
943 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
944 if (!uars) {
945 err = -ENOMEM;
946 goto out_ctx;
947 }
948
c1be5232 949 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 950 sizeof(*uuari->bitmap),
951 GFP_KERNEL);
952 if (!uuari->bitmap) {
953 err = -ENOMEM;
954 goto out_uar_ctx;
955 }
956 /*
957 * clear all fast path uuars
958 */
c1be5232 959 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 960 uuarn = i & 3;
961 if (uuarn == 2 || uuarn == 3)
962 set_bit(i, uuari->bitmap);
963 }
964
c1be5232 965 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 966 if (!uuari->count) {
967 err = -ENOMEM;
968 goto out_bitmap;
969 }
970
971 for (i = 0; i < num_uars; i++) {
9603b61d 972 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 973 if (err)
974 goto out_count;
975 }
976
b4cfe447
HE		 977#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
978 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
979#endif
980
146d2f1a 981 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
982 err = mlx5_core_alloc_transport_domain(dev->mdev,
983 &context->tdn);
984 if (err)
985 goto out_uars;
986 }
987
7c2344c3 988 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 989 INIT_LIST_HEAD(&context->db_page_list);
990 mutex_init(&context->db_page_mutex);
991
992 resp.tot_uuars = req.total_num_uuars;
938fe83c 993 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 994
f72300c5
HA		 995 if (field_avail(typeof(resp), cqe_version, udata->outlen))
996 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 997
bc5c6eed
NO		 998 /*
999 * We don't want to expose information from the PCI bar that is located
1000 * after 4096 bytes, so if the arch only supports larger pages, let's
1001 * pretend we don't support reading the HCA's core clock. This is also
1002 * forced by mmap function.
1003 */
1004 if (PAGE_SIZE <= 4096 &&
1005 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
b368d7cb
MB		 1006 resp.comp_mask |=
1007 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1008 resp.hca_core_clock_offset =
1009 offsetof(struct mlx5_init_seg, internal_timer_h) %
1010 PAGE_SIZE;
f72300c5
HA		 1011 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1012 sizeof(resp.reserved2) +
1013 sizeof(resp.reserved3);
b368d7cb
MB		 1014 }
1015
1016 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1017 if (err)
146d2f1a 1018 goto out_td;
e126ba97 1019
78c0f98c 1020 uuari->ver = ver;
e126ba97
EC		 1021 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1022 uuari->uars = uars;
1023 uuari->num_uars = num_uars;
f72300c5
HA		 1024 context->cqe_version = resp.cqe_version;
1025
e126ba97
EC		 1026 return &context->ibucontext;
1027
146d2f1a 1028out_td:
1029 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1030 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1031
e126ba97
EC		 1032out_uars:
1033 for (i--; i >= 0; i--)
9603b61d 1034 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1035out_count:
1036 kfree(uuari->count);
1037
1038out_bitmap:
1039 kfree(uuari->bitmap);
1040
1041out_uar_ctx:
1042 kfree(uars);
1043
1044out_ctx:
1045 kfree(context);
1046 return ERR_PTR(err);
1047}
1048
1049static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1050{
1051 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1052 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1053 struct mlx5_uuar_info *uuari = &context->uuari;
1054 int i;
1055
146d2f1a 1056 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1057 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1058
e126ba97 1059 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1060 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1061 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1062 }
1063
1064 kfree(uuari->count);
1065 kfree(uuari->bitmap);
1066 kfree(uuari->uars);
1067 kfree(context);
1068
1069 return 0;
1070}
1071
1072static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1073{
9603b61d 1074 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1075}
1076
1077static int get_command(unsigned long offset)
1078{
1079 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1080}
1081
1082static int get_arg(unsigned long offset)
1083{
1084 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1085}
1086
1087static int get_index(unsigned long offset)
1088{
1089 return get_arg(offset);
1090}
1091
7c2344c3
MG		 1092static void mlx5_ib_vma_open(struct vm_area_struct *area)
1093{
1094 /* vma_open is called when a new VMA is created on top of our VMA. This
1095 * is done through either mremap flow or split_vma (usually due to
1096 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1097 * as this VMA is strongly hardware related. Therefore we set the
1098 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1099 * calling us again and trying to do incorrect actions. We assume that
1100 * the original VMA size is exactly a single page, and therefore all
1101 * "splitting" operation will not happen to it.
1102 */
1103 area->vm_ops = NULL;
1104}
1105
1106static void mlx5_ib_vma_close(struct vm_area_struct *area)
1107{
1108 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1109
1110 /* It's guaranteed that all VMAs opened on a FD are closed before the
1111 * file itself is closed, therefore no sync is needed with the regular
1112 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1113 * However need a sync with accessing the vma as part of
1114 * mlx5_ib_disassociate_ucontext.
1115 * The close operation is usually called under mm->mmap_sem except when
1116 * process is exiting.
1117 * The exiting case is handled explicitly as part of
1118 * mlx5_ib_disassociate_ucontext.
1119 */
1120 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1121
1122 /* setting the vma context pointer to null in the mlx5_ib driver's
1123 * private data, to protect a race condition in
1124 * mlx5_ib_disassociate_ucontext().
1125 */
1126 mlx5_ib_vma_priv_data->vma = NULL;
1127 list_del(&mlx5_ib_vma_priv_data->list);
1128 kfree(mlx5_ib_vma_priv_data);
1129}
1130
1131static const struct vm_operations_struct mlx5_ib_vm_ops = {
1132 .open = mlx5_ib_vma_open,
1133 .close = mlx5_ib_vma_close
1134};
1135
1136static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1137 struct mlx5_ib_ucontext *ctx)
1138{
1139 struct mlx5_ib_vma_private_data *vma_prv;
1140 struct list_head *vma_head = &ctx->vma_private_list;
1141
1142 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1143 if (!vma_prv)
1144 return -ENOMEM;
1145
1146 vma_prv->vma = vma;
1147 vma->vm_private_data = vma_prv;
1148 vma->vm_ops = &mlx5_ib_vm_ops;
1149
1150 list_add(&vma_prv->list, vma_head);
1151
1152 return 0;
1153}
1154
1155static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1156{
1157 int ret;
1158 struct vm_area_struct *vma;
1159 struct mlx5_ib_vma_private_data *vma_private, *n;
1160 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1161 struct task_struct *owning_process = NULL;
1162 struct mm_struct *owning_mm = NULL;
1163
1164 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1165 if (!owning_process)
1166 return;
1167
1168 owning_mm = get_task_mm(owning_process);
1169 if (!owning_mm) {
1170 pr_info("no mm, disassociate ucontext is pending task termination\n");
1171 while (1) {
1172 put_task_struct(owning_process);
1173 usleep_range(1000, 2000);
1174 owning_process = get_pid_task(ibcontext->tgid,
1175 PIDTYPE_PID);
1176 if (!owning_process ||
1177 owning_process->state == TASK_DEAD) {
1178 pr_info("disassociate ucontext done, task was terminated\n");
1179 /* in case task was dead need to release the
1180 * task struct.
1181 */
1182 if (owning_process)
1183 put_task_struct(owning_process);
1184 return;
1185 }
1186 }
1187 }
1188
1189 /* need to protect from a race on closing the vma as part of
1190 * mlx5_ib_vma_close.
1191 */
1192 down_read(&owning_mm->mmap_sem);
1193 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1194 list) {
1195 vma = vma_private->vma;
1196 ret = zap_vma_ptes(vma, vma->vm_start,
1197 PAGE_SIZE);
1198 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1199 /* context going to be destroyed, should
1200 * not access ops any more.
1201 */
1202 vma->vm_ops = NULL;
1203 list_del(&vma_private->list);
1204 kfree(vma_private);
1205 }
1206 up_read(&owning_mm->mmap_sem);
1207 mmput(owning_mm);
1208 put_task_struct(owning_process);
1209}
1210
37aa5c36
GL		 1211static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1212{
1213 switch (cmd) {
1214 case MLX5_IB_MMAP_WC_PAGE:
1215 return "WC";
1216 case MLX5_IB_MMAP_REGULAR_PAGE:
1217 return "best effort WC";
1218 case MLX5_IB_MMAP_NC_PAGE:
1219 return "NC";
1220 default:
1221 return NULL;
1222 }
1223}
1224
1225static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1226 struct vm_area_struct *vma,
1227 struct mlx5_ib_ucontext *context)
37aa5c36 1228{
7c2344c3 1229 struct mlx5_uuar_info *uuari = &context->uuari;
37aa5c36
GL		 1230 int err;
1231 unsigned long idx;
1232 phys_addr_t pfn, pa;
1233 pgprot_t prot;
1234
1235 switch (cmd) {
1236 case MLX5_IB_MMAP_WC_PAGE:
1237/* Some architectures don't support WC memory */
1238#if defined(CONFIG_X86)
1239 if (!pat_enabled())
1240 return -EPERM;
1241#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1242 return -EPERM;
1243#endif
1244 /* fall through */
1245 case MLX5_IB_MMAP_REGULAR_PAGE:
1246 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1247 prot = pgprot_writecombine(vma->vm_page_prot);
1248 break;
1249 case MLX5_IB_MMAP_NC_PAGE:
1250 prot = pgprot_noncached(vma->vm_page_prot);
1251 break;
1252 default:
1253 return -EINVAL;
1254 }
1255
1256 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1257 return -EINVAL;
1258
1259 idx = get_index(vma->vm_pgoff);
1260 if (idx >= uuari->num_uars)
1261 return -EINVAL;
1262
1263 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1264 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1265
1266 vma->vm_page_prot = prot;
1267 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1268 PAGE_SIZE, vma->vm_page_prot);
1269 if (err) {
1270 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1271 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1272 return -EAGAIN;
1273 }
1274
1275 pa = pfn << PAGE_SHIFT;
1276 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1277 vma->vm_start, &pa);
1278
7c2344c3 1279 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1280}
1281
e126ba97
EC		 1282static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1283{
1284 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1285 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1286 unsigned long command;
e126ba97
EC		 1287 phys_addr_t pfn;
1288
1289 command = get_command(vma->vm_pgoff);
1290 switch (command) {
37aa5c36
GL		 1291 case MLX5_IB_MMAP_WC_PAGE:
1292 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1293 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1294 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1295
1296 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1297 return -ENOSYS;
1298
d69e3bcf 1299 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1300 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1301 return -EINVAL;
1302
6cbac1e4 1303 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1304 return -EPERM;
1305
1306 /* Don't expose to user-space information it shouldn't have */
1307 if (PAGE_SIZE > 4096)
1308 return -EOPNOTSUPP;
1309
1310 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1311 pfn = (dev->mdev->iseg_base +
1312 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1313 PAGE_SHIFT;
1314 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1315 PAGE_SIZE, vma->vm_page_prot))
1316 return -EAGAIN;
1317
1318 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1319 vma->vm_start,
1320 (unsigned long long)pfn << PAGE_SHIFT);
1321 break;
d69e3bcf 1322
e126ba97
EC		 1323 default:
1324 return -EINVAL;
1325 }
1326
1327 return 0;
1328}
1329
e126ba97
EC		 1330static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1331 struct ib_ucontext *context,
1332 struct ib_udata *udata)
1333{
1334 struct mlx5_ib_alloc_pd_resp resp;
1335 struct mlx5_ib_pd *pd;
1336 int err;
1337
1338 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1339 if (!pd)
1340 return ERR_PTR(-ENOMEM);
1341
9603b61d 1342 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1343 if (err) {
1344 kfree(pd);
1345 return ERR_PTR(err);
1346 }
1347
1348 if (context) {
1349 resp.pdn = pd->pdn;
1350 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1351 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1352 kfree(pd);
1353 return ERR_PTR(-EFAULT);
1354 }
e126ba97
EC		 1355 }
1356
1357 return &pd->ibpd;
1358}
1359
1360static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1361{
1362 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1363 struct mlx5_ib_pd *mpd = to_mpd(pd);
1364
9603b61d 1365 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1366 kfree(mpd);
1367
1368 return 0;
1369}
1370
038d2ef8
MG		 1371static bool outer_header_zero(u32 *match_criteria)
1372{
1373 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1374 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1375 outer_headers);
1376
1377 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1378 outer_headers_c + 1,
1379 size - 1);
1380}
1381
1382static int parse_flow_attr(u32 *match_c, u32 *match_v,
1383 union ib_flow_spec *ib_spec)
1384{
1385 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1386 outer_headers);
1387 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1388 outer_headers);
1389 switch (ib_spec->type) {
1390 case IB_FLOW_SPEC_ETH:
1391 if (ib_spec->size != sizeof(ib_spec->eth))
1392 return -EINVAL;
1393
1394 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1395 dmac_47_16),
1396 ib_spec->eth.mask.dst_mac);
1397 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1398 dmac_47_16),
1399 ib_spec->eth.val.dst_mac);
1400
1401 if (ib_spec->eth.mask.vlan_tag) {
1402 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1403 vlan_tag, 1);
1404 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1405 vlan_tag, 1);
1406
1407 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1408 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1409 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1410 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1411
1412 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1413 first_cfi,
1414 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1415 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1416 first_cfi,
1417 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1418
1419 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1420 first_prio,
1421 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1422 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1423 first_prio,
1424 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1425 }
1426 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1427 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1428 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1429 ethertype, ntohs(ib_spec->eth.val.ether_type));
1430 break;
1431 case IB_FLOW_SPEC_IPV4:
1432 if (ib_spec->size != sizeof(ib_spec->ipv4))
1433 return -EINVAL;
1434
1435 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1436 ethertype, 0xffff);
1437 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1438 ethertype, ETH_P_IP);
1439
1440 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1441 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1442 &ib_spec->ipv4.mask.src_ip,
1443 sizeof(ib_spec->ipv4.mask.src_ip));
1444 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1445 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1446 &ib_spec->ipv4.val.src_ip,
1447 sizeof(ib_spec->ipv4.val.src_ip));
1448 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1449 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1450 &ib_spec->ipv4.mask.dst_ip,
1451 sizeof(ib_spec->ipv4.mask.dst_ip));
1452 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1453 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1454 &ib_spec->ipv4.val.dst_ip,
1455 sizeof(ib_spec->ipv4.val.dst_ip));
1456 break;
1457 case IB_FLOW_SPEC_TCP:
1458 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1459 return -EINVAL;
1460
1461 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1462 0xff);
1463 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1464 IPPROTO_TCP);
1465
1466 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1467 ntohs(ib_spec->tcp_udp.mask.src_port));
1468 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1469 ntohs(ib_spec->tcp_udp.val.src_port));
1470
1471 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1472 ntohs(ib_spec->tcp_udp.mask.dst_port));
1473 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1474 ntohs(ib_spec->tcp_udp.val.dst_port));
1475 break;
1476 case IB_FLOW_SPEC_UDP:
1477 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1478 return -EINVAL;
1479
1480 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1481 0xff);
1482 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1483 IPPROTO_UDP);
1484
1485 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1486 ntohs(ib_spec->tcp_udp.mask.src_port));
1487 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1488 ntohs(ib_spec->tcp_udp.val.src_port));
1489
1490 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1491 ntohs(ib_spec->tcp_udp.mask.dst_port));
1492 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1493 ntohs(ib_spec->tcp_udp.val.dst_port));
1494 break;
1495 default:
1496 return -EINVAL;
1497 }
1498
1499 return 0;
1500}
1501
1502/* If a flow could catch both multicast and unicast packets,
1503 * it won't fall into the multicast flow steering table and this rule
1504 * could steal other multicast packets.
1505 */
1506static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1507{
1508 struct ib_flow_spec_eth *eth_spec;
1509
1510 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1511 ib_attr->size < sizeof(struct ib_flow_attr) +
1512 sizeof(struct ib_flow_spec_eth) ||
1513 ib_attr->num_of_specs < 1)
1514 return false;
1515
1516 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1517 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1518 eth_spec->size != sizeof(*eth_spec))
1519 return false;
1520
1521 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1522 is_multicast_ether_addr(eth_spec->val.dst_mac);
1523}
1524
1525static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1526{
1527 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1528 bool has_ipv4_spec = false;
1529 bool eth_type_ipv4 = true;
1530 unsigned int spec_index;
1531
1532 /* Validate that ethertype is correct */
1533 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1534 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1535 ib_spec->eth.mask.ether_type) {
1536 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1537 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1538 eth_type_ipv4 = false;
1539 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1540 has_ipv4_spec = true;
1541 }
1542 ib_spec = (void *)ib_spec + ib_spec->size;
1543 }
1544 return !has_ipv4_spec || eth_type_ipv4;
1545}
1546
1547static void put_flow_table(struct mlx5_ib_dev *dev,
1548 struct mlx5_ib_flow_prio *prio, bool ft_added)
1549{
1550 prio->refcount -= !!ft_added;
1551 if (!prio->refcount) {
1552 mlx5_destroy_flow_table(prio->flow_table);
1553 prio->flow_table = NULL;
1554 }
1555}
1556
1557static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1558{
1559 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1560 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1561 struct mlx5_ib_flow_handler,
1562 ibflow);
1563 struct mlx5_ib_flow_handler *iter, *tmp;
1564
1565 mutex_lock(&dev->flow_db.lock);
1566
1567 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1568 mlx5_del_flow_rule(iter->rule);
1569 list_del(&iter->list);
1570 kfree(iter);
1571 }
1572
1573 mlx5_del_flow_rule(handler->rule);
1574 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1575 mutex_unlock(&dev->flow_db.lock);
1576
1577 kfree(handler);
1578
1579 return 0;
1580}
1581
35d19011
MG		 1582static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1583{
1584 priority *= 2;
1585 if (!dont_trap)
1586 priority++;
1587 return priority;
1588}
1589
038d2ef8
MG		 1590#define MLX5_FS_MAX_TYPES 10
1591#define MLX5_FS_MAX_ENTRIES 32000UL
1592static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1593 struct ib_flow_attr *flow_attr)
1594{
35d19011 1595 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1596 struct mlx5_flow_namespace *ns = NULL;
1597 struct mlx5_ib_flow_prio *prio;
1598 struct mlx5_flow_table *ft;
1599 int num_entries;
1600 int num_groups;
1601 int priority;
1602 int err = 0;
1603
1604 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1605 if (flow_is_multicast_only(flow_attr) &&
1606 !dont_trap)
038d2ef8
MG		 1607 priority = MLX5_IB_FLOW_MCAST_PRIO;
1608 else
35d19011
MG		 1609 priority = ib_prio_to_core_prio(flow_attr->priority,
1610 dont_trap);
038d2ef8
MG		 1611 ns = mlx5_get_flow_namespace(dev->mdev,
1612 MLX5_FLOW_NAMESPACE_BYPASS);
1613 num_entries = MLX5_FS_MAX_ENTRIES;
1614 num_groups = MLX5_FS_MAX_TYPES;
1615 prio = &dev->flow_db.prios[priority];
1616 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1617 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1618 ns = mlx5_get_flow_namespace(dev->mdev,
1619 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1620 build_leftovers_ft_param(&priority,
1621 &num_entries,
1622 &num_groups);
1623 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1624 }
1625
1626 if (!ns)
1627 return ERR_PTR(-ENOTSUPP);
1628
1629 ft = prio->flow_table;
1630 if (!ft) {
1631 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1632 num_entries,
d63cd286
MG		 1633 num_groups,
1634 0);
038d2ef8
MG		 1635
1636 if (!IS_ERR(ft)) {
1637 prio->refcount = 0;
1638 prio->flow_table = ft;
1639 } else {
1640 err = PTR_ERR(ft);
1641 }
1642 }
1643
1644 return err ? ERR_PTR(err) : prio;
1645}
1646
1647static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1648 struct mlx5_ib_flow_prio *ft_prio,
1649 struct ib_flow_attr *flow_attr,
1650 struct mlx5_flow_destination *dst)
1651{
1652 struct mlx5_flow_table *ft = ft_prio->flow_table;
1653 struct mlx5_ib_flow_handler *handler;
1654 void *ib_flow = flow_attr + 1;
1655 u8 match_criteria_enable = 0;
1656 unsigned int spec_index;
1657 u32 *match_c;
1658 u32 *match_v;
35d19011 1659 u32 action;
038d2ef8
MG		 1660 int err = 0;
1661
1662 if (!is_valid_attr(flow_attr))
1663 return ERR_PTR(-EINVAL);
1664
1665 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1666 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1667 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1668 if (!handler || !match_c || !match_v) {
1669 err = -ENOMEM;
1670 goto free;
1671 }
1672
1673 INIT_LIST_HEAD(&handler->list);
1674
1675 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1676 err = parse_flow_attr(match_c, match_v, ib_flow);
1677 if (err < 0)
1678 goto free;
1679
1680 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1681 }
1682
1683 /* Outer header support only */
1684 match_criteria_enable = (!outer_header_zero(match_c)) << 0;
35d19011
MG		 1685 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1686 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
038d2ef8
MG		 1687 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable,
1688 match_c, match_v,
35d19011 1689 action,
038d2ef8
MG		 1690 MLX5_FS_DEFAULT_FLOW_TAG,
1691 dst);
1692
1693 if (IS_ERR(handler->rule)) {
1694 err = PTR_ERR(handler->rule);
1695 goto free;
1696 }
1697
1698 handler->prio = ft_prio - dev->flow_db.prios;
1699
1700 ft_prio->flow_table = ft;
1701free:
1702 if (err)
1703 kfree(handler);
1704 kfree(match_c);
1705 kfree(match_v);
1706 return err ? ERR_PTR(err) : handler;
1707}
1708
35d19011
MG		 1709static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1710 struct mlx5_ib_flow_prio *ft_prio,
1711 struct ib_flow_attr *flow_attr,
1712 struct mlx5_flow_destination *dst)
1713{
1714 struct mlx5_ib_flow_handler *handler_dst = NULL;
1715 struct mlx5_ib_flow_handler *handler = NULL;
1716
1717 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1718 if (!IS_ERR(handler)) {
1719 handler_dst = create_flow_rule(dev, ft_prio,
1720 flow_attr, dst);
1721 if (IS_ERR(handler_dst)) {
1722 mlx5_del_flow_rule(handler->rule);
1723 kfree(handler);
1724 handler = handler_dst;
1725 } else {
1726 list_add(&handler_dst->list, &handler->list);
1727 }
1728 }
1729
1730 return handler;
1731}
038d2ef8
MG		 1732enum {
1733 LEFTOVERS_MC,
1734 LEFTOVERS_UC,
1735};
1736
1737static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1738 struct mlx5_ib_flow_prio *ft_prio,
1739 struct ib_flow_attr *flow_attr,
1740 struct mlx5_flow_destination *dst)
1741{
1742 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1743 struct mlx5_ib_flow_handler *handler = NULL;
1744
1745 static struct {
1746 struct ib_flow_attr flow_attr;
1747 struct ib_flow_spec_eth eth_flow;
1748 } leftovers_specs[] = {
1749 [LEFTOVERS_MC] = {
1750 .flow_attr = {
1751 .num_of_specs = 1,
1752 .size = sizeof(leftovers_specs[0])
1753 },
1754 .eth_flow = {
1755 .type = IB_FLOW_SPEC_ETH,
1756 .size = sizeof(struct ib_flow_spec_eth),
1757 .mask = {.dst_mac = {0x1} },
1758 .val = {.dst_mac = {0x1} }
1759 }
1760 },
1761 [LEFTOVERS_UC] = {
1762 .flow_attr = {
1763 .num_of_specs = 1,
1764 .size = sizeof(leftovers_specs[0])
1765 },
1766 .eth_flow = {
1767 .type = IB_FLOW_SPEC_ETH,
1768 .size = sizeof(struct ib_flow_spec_eth),
1769 .mask = {.dst_mac = {0x1} },
1770 .val = {.dst_mac = {} }
1771 }
1772 }
1773 };
1774
1775 handler = create_flow_rule(dev, ft_prio,
1776 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1777 dst);
1778 if (!IS_ERR(handler) &&
1779 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1780 handler_ucast = create_flow_rule(dev, ft_prio,
1781 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1782 dst);
1783 if (IS_ERR(handler_ucast)) {
1784 kfree(handler);
1785 handler = handler_ucast;
1786 } else {
1787 list_add(&handler_ucast->list, &handler->list);
1788 }
1789 }
1790
1791 return handler;
1792}
1793
1794static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1795 struct ib_flow_attr *flow_attr,
1796 int domain)
1797{
1798 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1799 struct mlx5_ib_flow_handler *handler = NULL;
1800 struct mlx5_flow_destination *dst = NULL;
1801 struct mlx5_ib_flow_prio *ft_prio;
1802 int err;
1803
1804 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1805 return ERR_PTR(-ENOSPC);
1806
1807 if (domain != IB_FLOW_DOMAIN_USER ||
1808 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 1809 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 1810 return ERR_PTR(-EINVAL);
1811
1812 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1813 if (!dst)
1814 return ERR_PTR(-ENOMEM);
1815
1816 mutex_lock(&dev->flow_db.lock);
1817
1818 ft_prio = get_flow_table(dev, flow_attr);
1819 if (IS_ERR(ft_prio)) {
1820 err = PTR_ERR(ft_prio);
1821 goto unlock;
1822 }
1823
1824 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1825 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1826
1827 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1828 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
1829 handler = create_dont_trap_rule(dev, ft_prio,
1830 flow_attr, dst);
1831 } else {
1832 handler = create_flow_rule(dev, ft_prio, flow_attr,
1833 dst);
1834 }
038d2ef8
MG		 1835 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1836 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1837 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1838 dst);
1839 } else {
1840 err = -EINVAL;
1841 goto destroy_ft;
1842 }
1843
1844 if (IS_ERR(handler)) {
1845 err = PTR_ERR(handler);
1846 handler = NULL;
1847 goto destroy_ft;
1848 }
1849
1850 ft_prio->refcount++;
1851 mutex_unlock(&dev->flow_db.lock);
1852 kfree(dst);
1853
1854 return &handler->ibflow;
1855
1856destroy_ft:
1857 put_flow_table(dev, ft_prio, false);
1858unlock:
1859 mutex_unlock(&dev->flow_db.lock);
1860 kfree(dst);
1861 kfree(handler);
1862 return ERR_PTR(err);
1863}
1864
e126ba97
EC		 1865static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1866{
1867 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1868 int err;
1869
9603b61d 1870 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1871 if (err)
1872 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1873 ibqp->qp_num, gid->raw);
1874
1875 return err;
1876}
1877
1878static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1879{
1880 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1881 int err;
1882
9603b61d 1883 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1884 if (err)
1885 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1886 ibqp->qp_num, gid->raw);
1887
1888 return err;
1889}
1890
1891static int init_node_data(struct mlx5_ib_dev *dev)
1892{
1b5daf11 1893 int err;
e126ba97 1894
1b5daf11 1895 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1896 if (err)
1b5daf11 1897 return err;
e126ba97 1898
1b5daf11 1899 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1900
1b5daf11 1901 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1902}
1903
1904static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1905 char *buf)
1906{
1907 struct mlx5_ib_dev *dev =
1908 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1909
9603b61d 1910 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1911}
1912
1913static ssize_t show_reg_pages(struct device *device,
1914 struct device_attribute *attr, char *buf)
1915{
1916 struct mlx5_ib_dev *dev =
1917 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1918
6aec21f6 1919 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1920}
1921
1922static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1923 char *buf)
1924{
1925 struct mlx5_ib_dev *dev =
1926 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1927 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1928}
1929
1930static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1931 char *buf)
1932{
1933 struct mlx5_ib_dev *dev =
1934 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
c0fcebf5 1935 return sprintf(buf, "%d.%d.%04d\n", fw_rev_maj(dev->mdev),
9603b61d 1936 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1937}
1938
1939static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1940 char *buf)
1941{
1942 struct mlx5_ib_dev *dev =
1943 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1944 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1945}
1946
1947static ssize_t show_board(struct device *device, struct device_attribute *attr,
1948 char *buf)
1949{
1950 struct mlx5_ib_dev *dev =
1951 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1952 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1953 dev->mdev->board_id);
e126ba97
EC		 1954}
1955
1956static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1957static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1958static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1959static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1960static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1961static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1962
1963static struct device_attribute *mlx5_class_attributes[] = {
1964 &dev_attr_hw_rev,
1965 &dev_attr_fw_ver,
1966 &dev_attr_hca_type,
1967 &dev_attr_board_id,
1968 &dev_attr_fw_pages,
1969 &dev_attr_reg_pages,
1970};
1971
7722f47e
HE		 1972static void pkey_change_handler(struct work_struct *work)
1973{
1974 struct mlx5_ib_port_resources *ports =
1975 container_of(work, struct mlx5_ib_port_resources,
1976 pkey_change_work);
1977
1978 mutex_lock(&ports->devr->mutex);
1979 mlx5_ib_gsi_pkey_change(ports->gsi);
1980 mutex_unlock(&ports->devr->mutex);
1981}
1982
9603b61d 1983static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1984 enum mlx5_dev_event event, unsigned long param)
e126ba97 1985{
9603b61d 1986 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1987 struct ib_event ibev;
9603b61d 1988
e126ba97
EC		 1989 u8 port = 0;
1990
1991 switch (event) {
1992 case MLX5_DEV_EVENT_SYS_ERROR:
1993 ibdev->ib_active = false;
1994 ibev.event = IB_EVENT_DEVICE_FATAL;
1995 break;
1996
1997 case MLX5_DEV_EVENT_PORT_UP:
1998 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1999 port = (u8)param;
e126ba97
EC		 2000 break;
2001
2002 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2003 case MLX5_DEV_EVENT_PORT_INITIALIZED:
e126ba97 2004 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 2005 port = (u8)param;
e126ba97
EC		 2006 break;
2007
e126ba97
EC		 2008 case MLX5_DEV_EVENT_LID_CHANGE:
2009 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2010 port = (u8)param;
e126ba97
EC		 2011 break;
2012
2013 case MLX5_DEV_EVENT_PKEY_CHANGE:
2014 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2015 port = (u8)param;
7722f47e
HE		 2016
2017 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2018 break;
2019
2020 case MLX5_DEV_EVENT_GUID_CHANGE:
2021 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2022 port = (u8)param;
e126ba97
EC		 2023 break;
2024
2025 case MLX5_DEV_EVENT_CLIENT_REREG:
2026 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2027 port = (u8)param;
e126ba97
EC		 2028 break;
2029 }
2030
2031 ibev.device = &ibdev->ib_dev;
2032 ibev.element.port_num = port;
2033
a0c84c32
EC		 2034 if (port < 1 || port > ibdev->num_ports) {
2035 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2036 return;
2037 }
2038
e126ba97
EC		 2039 if (ibdev->ib_active)
2040 ib_dispatch_event(&ibev);
2041}
2042
2043static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2044{
2045 int port;
2046
938fe83c 2047 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2048 mlx5_query_ext_port_caps(dev, port);
2049}
2050
2051static int get_port_caps(struct mlx5_ib_dev *dev)
2052{
2053 struct ib_device_attr *dprops = NULL;
2054 struct ib_port_attr *pprops = NULL;
f614fc15 2055 int err = -ENOMEM;
e126ba97 2056 int port;
2528e33e 2057 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2058
2059 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2060 if (!pprops)
2061 goto out;
2062
2063 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2064 if (!dprops)
2065 goto out;
2066
2528e33e 2067 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2068 if (err) {
2069 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2070 goto out;
2071 }
2072
938fe83c 2073 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 2074 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2075 if (err) {
938fe83c
SM		 2076 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2077 port, err);
e126ba97
EC		 2078 break;
2079 }
938fe83c
SM		 2080 dev->mdev->port_caps[port - 1].pkey_table_len =
2081 dprops->max_pkeys;
2082 dev->mdev->port_caps[port - 1].gid_table_len =
2083 pprops->gid_tbl_len;
e126ba97
EC		 2084 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2085 dprops->max_pkeys, pprops->gid_tbl_len);
2086 }
2087
2088out:
2089 kfree(pprops);
2090 kfree(dprops);
2091
2092 return err;
2093}
2094
2095static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2096{
2097 int err;
2098
2099 err = mlx5_mr_cache_cleanup(dev);
2100 if (err)
2101 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2102
2103 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2104 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2105 ib_dealloc_pd(dev->umrc.pd);
2106}
2107
2108enum {
2109 MAX_UMR_WR = 128,
2110};
2111
2112static int create_umr_res(struct mlx5_ib_dev *dev)
2113{
2114 struct ib_qp_init_attr *init_attr = NULL;
2115 struct ib_qp_attr *attr = NULL;
2116 struct ib_pd *pd;
2117 struct ib_cq *cq;
2118 struct ib_qp *qp;
e126ba97
EC		 2119 int ret;
2120
2121 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2122 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2123 if (!attr || !init_attr) {
2124 ret = -ENOMEM;
2125 goto error_0;
2126 }
2127
2128 pd = ib_alloc_pd(&dev->ib_dev);
2129 if (IS_ERR(pd)) {
2130 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2131 ret = PTR_ERR(pd);
2132 goto error_0;
2133 }
2134
add08d76 2135 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2136 if (IS_ERR(cq)) {
2137 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2138 ret = PTR_ERR(cq);
2139 goto error_2;
2140 }
e126ba97
EC		 2141
2142 init_attr->send_cq = cq;
2143 init_attr->recv_cq = cq;
2144 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2145 init_attr->cap.max_send_wr = MAX_UMR_WR;
2146 init_attr->cap.max_send_sge = 1;
2147 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2148 init_attr->port_num = 1;
2149 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2150 if (IS_ERR(qp)) {
2151 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2152 ret = PTR_ERR(qp);
2153 goto error_3;
2154 }
2155 qp->device = &dev->ib_dev;
2156 qp->real_qp = qp;
2157 qp->uobject = NULL;
2158 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2159
2160 attr->qp_state = IB_QPS_INIT;
2161 attr->port_num = 1;
2162 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2163 IB_QP_PORT, NULL);
2164 if (ret) {
2165 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2166 goto error_4;
2167 }
2168
2169 memset(attr, 0, sizeof(*attr));
2170 attr->qp_state = IB_QPS_RTR;
2171 attr->path_mtu = IB_MTU_256;
2172
2173 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2174 if (ret) {
2175 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2176 goto error_4;
2177 }
2178
2179 memset(attr, 0, sizeof(*attr));
2180 attr->qp_state = IB_QPS_RTS;
2181 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2182 if (ret) {
2183 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2184 goto error_4;
2185 }
2186
2187 dev->umrc.qp = qp;
2188 dev->umrc.cq = cq;
e126ba97
EC		 2189 dev->umrc.pd = pd;
2190
2191 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2192 ret = mlx5_mr_cache_init(dev);
2193 if (ret) {
2194 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2195 goto error_4;
2196 }
2197
2198 kfree(attr);
2199 kfree(init_attr);
2200
2201 return 0;
2202
2203error_4:
2204 mlx5_ib_destroy_qp(qp);
2205
2206error_3:
add08d76 2207 ib_free_cq(cq);
e126ba97
EC		 2208
2209error_2:
e126ba97
EC		 2210 ib_dealloc_pd(pd);
2211
2212error_0:
2213 kfree(attr);
2214 kfree(init_attr);
2215 return ret;
2216}
2217
2218static int create_dev_resources(struct mlx5_ib_resources *devr)
2219{
2220 struct ib_srq_init_attr attr;
2221 struct mlx5_ib_dev *dev;
bcf4c1ea 2222 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2223 int port;
e126ba97
EC		 2224 int ret = 0;
2225
2226 dev = container_of(devr, struct mlx5_ib_dev, devr);
2227
d16e91da
HE		 2228 mutex_init(&devr->mutex);
2229
e126ba97
EC		 2230 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2231 if (IS_ERR(devr->p0)) {
2232 ret = PTR_ERR(devr->p0);
2233 goto error0;
2234 }
2235 devr->p0->device = &dev->ib_dev;
2236 devr->p0->uobject = NULL;
2237 atomic_set(&devr->p0->usecnt, 0);
2238
bcf4c1ea 2239 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2240 if (IS_ERR(devr->c0)) {
2241 ret = PTR_ERR(devr->c0);
2242 goto error1;
2243 }
2244 devr->c0->device = &dev->ib_dev;
2245 devr->c0->uobject = NULL;
2246 devr->c0->comp_handler = NULL;
2247 devr->c0->event_handler = NULL;
2248 devr->c0->cq_context = NULL;
2249 atomic_set(&devr->c0->usecnt, 0);
2250
2251 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2252 if (IS_ERR(devr->x0)) {
2253 ret = PTR_ERR(devr->x0);
2254 goto error2;
2255 }
2256 devr->x0->device = &dev->ib_dev;
2257 devr->x0->inode = NULL;
2258 atomic_set(&devr->x0->usecnt, 0);
2259 mutex_init(&devr->x0->tgt_qp_mutex);
2260 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2261
2262 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2263 if (IS_ERR(devr->x1)) {
2264 ret = PTR_ERR(devr->x1);
2265 goto error3;
2266 }
2267 devr->x1->device = &dev->ib_dev;
2268 devr->x1->inode = NULL;
2269 atomic_set(&devr->x1->usecnt, 0);
2270 mutex_init(&devr->x1->tgt_qp_mutex);
2271 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2272
2273 memset(&attr, 0, sizeof(attr));
2274 attr.attr.max_sge = 1;
2275 attr.attr.max_wr = 1;
2276 attr.srq_type = IB_SRQT_XRC;
2277 attr.ext.xrc.cq = devr->c0;
2278 attr.ext.xrc.xrcd = devr->x0;
2279
2280 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2281 if (IS_ERR(devr->s0)) {
2282 ret = PTR_ERR(devr->s0);
2283 goto error4;
2284 }
2285 devr->s0->device = &dev->ib_dev;
2286 devr->s0->pd = devr->p0;
2287 devr->s0->uobject = NULL;
2288 devr->s0->event_handler = NULL;
2289 devr->s0->srq_context = NULL;
2290 devr->s0->srq_type = IB_SRQT_XRC;
2291 devr->s0->ext.xrc.xrcd = devr->x0;
2292 devr->s0->ext.xrc.cq = devr->c0;
2293 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2294 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2295 atomic_inc(&devr->p0->usecnt);
2296 atomic_set(&devr->s0->usecnt, 0);
2297
4aa17b28
HA		 2298 memset(&attr, 0, sizeof(attr));
2299 attr.attr.max_sge = 1;
2300 attr.attr.max_wr = 1;
2301 attr.srq_type = IB_SRQT_BASIC;
2302 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2303 if (IS_ERR(devr->s1)) {
2304 ret = PTR_ERR(devr->s1);
2305 goto error5;
2306 }
2307 devr->s1->device = &dev->ib_dev;
2308 devr->s1->pd = devr->p0;
2309 devr->s1->uobject = NULL;
2310 devr->s1->event_handler = NULL;
2311 devr->s1->srq_context = NULL;
2312 devr->s1->srq_type = IB_SRQT_BASIC;
2313 devr->s1->ext.xrc.cq = devr->c0;
2314 atomic_inc(&devr->p0->usecnt);
2315 atomic_set(&devr->s0->usecnt, 0);
2316
7722f47e
HE		 2317 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2318 INIT_WORK(&devr->ports[port].pkey_change_work,
2319 pkey_change_handler);
2320 devr->ports[port].devr = devr;
2321 }
2322
e126ba97
EC		 2323 return 0;
2324
4aa17b28
HA		 2325error5:
2326 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2327error4:
2328 mlx5_ib_dealloc_xrcd(devr->x1);
2329error3:
2330 mlx5_ib_dealloc_xrcd(devr->x0);
2331error2:
2332 mlx5_ib_destroy_cq(devr->c0);
2333error1:
2334 mlx5_ib_dealloc_pd(devr->p0);
2335error0:
2336 return ret;
2337}
2338
2339static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2340{
7722f47e
HE		 2341 struct mlx5_ib_dev *dev =
2342 container_of(devr, struct mlx5_ib_dev, devr);
2343 int port;
2344
4aa17b28 2345 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2346 mlx5_ib_destroy_srq(devr->s0);
2347 mlx5_ib_dealloc_xrcd(devr->x0);
2348 mlx5_ib_dealloc_xrcd(devr->x1);
2349 mlx5_ib_destroy_cq(devr->c0);
2350 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2351
2352 /* Make sure no change P_Key work items are still executing */
2353 for (port = 0; port < dev->num_ports; ++port)
2354 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2355}
2356
e53505a8
AS		 2357static u32 get_core_cap_flags(struct ib_device *ibdev)
2358{
2359 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2360 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2361 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2362 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2363 u32 ret = 0;
2364
2365 if (ll == IB_LINK_LAYER_INFINIBAND)
2366 return RDMA_CORE_PORT_IBA_IB;
2367
2368 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2369 return 0;
2370
2371 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2372 return 0;
2373
2374 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2375 ret |= RDMA_CORE_PORT_IBA_ROCE;
2376
2377 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2378 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2379
2380 return ret;
2381}
2382
7738613e
IW		 2383static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2384 struct ib_port_immutable *immutable)
2385{
2386 struct ib_port_attr attr;
2387 int err;
2388
2389 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2390 if (err)
2391 return err;
2392
2393 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2394 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2395 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2396 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2397
2398 return 0;
2399}
2400
fc24fc5e
AS		 2401static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2402{
e53505a8
AS		 2403 int err;
2404
fc24fc5e 2405 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8
AS		 2406 err = register_netdevice_notifier(&dev->roce.nb);
2407 if (err)
2408 return err;
2409
2410 err = mlx5_nic_vport_enable_roce(dev->mdev);
2411 if (err)
2412 goto err_unregister_netdevice_notifier;
2413
2414 return 0;
2415
2416err_unregister_netdevice_notifier:
2417 unregister_netdevice_notifier(&dev->roce.nb);
2418 return err;
fc24fc5e
AS		 2419}
2420
2421static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2422{
e53505a8 2423 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2424 unregister_netdevice_notifier(&dev->roce.nb);
2425}
2426
9603b61d 2427static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2428{
e126ba97 2429 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2430 enum rdma_link_layer ll;
2431 int port_type_cap;
e126ba97
EC		 2432 int err;
2433 int i;
2434
ebd61f68
AS		 2435 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2436 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2437
e53505a8 2438 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2439 return NULL;
2440
e126ba97
EC		 2441 printk_once(KERN_INFO "%s", mlx5_version);
2442
2443 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2444 if (!dev)
9603b61d 2445 return NULL;
e126ba97 2446
9603b61d 2447 dev->mdev = mdev;
e126ba97 2448
fc24fc5e 2449 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2450 err = get_port_caps(dev);
2451 if (err)
9603b61d 2452 goto err_dealloc;
e126ba97 2453
1b5daf11
MD		 2454 if (mlx5_use_mad_ifc(dev))
2455 get_ext_port_caps(dev);
e126ba97 2456
e126ba97
EC		 2457 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2458
2459 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2460 dev->ib_dev.owner = THIS_MODULE;
2461 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2462 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2463 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2464 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2465 dev->ib_dev.num_comp_vectors =
2466 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2467 dev->ib_dev.dma_device = &mdev->pdev->dev;
2468
2469 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2470 dev->ib_dev.uverbs_cmd_mask =
2471 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2472 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2473 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2474 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2475 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2476 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2477 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2478 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2479 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2480 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2481 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2482 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2483 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2484 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2485 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2486 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2487 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2488 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2489 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2490 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2491 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2492 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2493 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2494 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 2495 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 2496 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2497 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2498 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 2499
2500 dev->ib_dev.query_device = mlx5_ib_query_device;
2501 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 2502 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 2503 if (ll == IB_LINK_LAYER_ETHERNET)
2504 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 2505 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 2506 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2507 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 2508 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2509 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2510 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2511 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2512 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2513 dev->ib_dev.mmap = mlx5_ib_mmap;
2514 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2515 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2516 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2517 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2518 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2519 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2520 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2521 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2522 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2523 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2524 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2525 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2526 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2527 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2528 dev->ib_dev.post_send = mlx5_ib_post_send;
2529 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2530 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2531 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2532 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2533 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2534 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2535 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2536 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2537 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 2538 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 2539 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2540 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2541 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2542 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 2543 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 2544 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 2545 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 2546 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
eff901d3
EC		 2547 if (mlx5_core_is_pf(mdev)) {
2548 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
2549 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
2550 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
2551 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
2552 }
e126ba97 2553
7c2344c3
MG		 2554 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
2555
938fe83c 2556 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 2557
d2370e0a
MB		 2558 if (MLX5_CAP_GEN(mdev, imaicl)) {
2559 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2560 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2561 dev->ib_dev.uverbs_cmd_mask |=
2562 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2563 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2564 }
2565
938fe83c 2566 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 2567 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2568 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2569 dev->ib_dev.uverbs_cmd_mask |=
2570 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2571 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2572 }
2573
048ccca8 2574 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 2575 IB_LINK_LAYER_ETHERNET) {
2576 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2577 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 2578 dev->ib_dev.create_wq = mlx5_ib_create_wq;
2579 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
2580 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 2581 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
2582 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 2583 dev->ib_dev.uverbs_ex_cmd_mask |=
2584 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 2585 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
2586 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2587 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 2588 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2589 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2590 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 2591 }
e126ba97
EC		 2592 err = init_node_data(dev);
2593 if (err)
233d05d2 2594 goto err_dealloc;
e126ba97 2595
038d2ef8 2596 mutex_init(&dev->flow_db.lock);
e126ba97 2597 mutex_init(&dev->cap_mask_mutex);
e126ba97 2598
fc24fc5e
AS		 2599 if (ll == IB_LINK_LAYER_ETHERNET) {
2600 err = mlx5_enable_roce(dev);
2601 if (err)
2602 goto err_dealloc;
2603 }
2604
e126ba97
EC		 2605 err = create_dev_resources(&dev->devr);
2606 if (err)
fc24fc5e 2607 goto err_disable_roce;
e126ba97 2608
6aec21f6 2609 err = mlx5_ib_odp_init_one(dev);
281d1a92 2610 if (err)
e126ba97
EC		 2611 goto err_rsrc;
2612
6aec21f6
HE		 2613 err = ib_register_device(&dev->ib_dev, NULL);
2614 if (err)
2615 goto err_odp;
2616
e126ba97
EC		 2617 err = create_umr_res(dev);
2618 if (err)
2619 goto err_dev;
2620
2621 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 2622 err = device_create_file(&dev->ib_dev.dev,
2623 mlx5_class_attributes[i]);
2624 if (err)
e126ba97
EC		 2625 goto err_umrc;
2626 }
2627
2628 dev->ib_active = true;
2629
9603b61d 2630 return dev;
e126ba97
EC		 2631
2632err_umrc:
2633 destroy_umrc_res(dev);
2634
2635err_dev:
2636 ib_unregister_device(&dev->ib_dev);
2637
6aec21f6
HE		 2638err_odp:
2639 mlx5_ib_odp_remove_one(dev);
2640
e126ba97
EC		 2641err_rsrc:
2642 destroy_dev_resources(&dev->devr);
2643
fc24fc5e
AS		 2644err_disable_roce:
2645 if (ll == IB_LINK_LAYER_ETHERNET)
2646 mlx5_disable_roce(dev);
2647
9603b61d 2648err_dealloc:
e126ba97
EC		 2649 ib_dealloc_device((struct ib_device *)dev);
2650
9603b61d 2651 return NULL;
e126ba97
EC		 2652}
2653
9603b61d 2654static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 2655{
9603b61d 2656 struct mlx5_ib_dev *dev = context;
fc24fc5e 2657 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 2658
e126ba97 2659 ib_unregister_device(&dev->ib_dev);
eefd56e5 2660 destroy_umrc_res(dev);
6aec21f6 2661 mlx5_ib_odp_remove_one(dev);
e126ba97 2662 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 2663 if (ll == IB_LINK_LAYER_ETHERNET)
2664 mlx5_disable_roce(dev);
e126ba97
EC		 2665 ib_dealloc_device(&dev->ib_dev);
2666}
2667
9603b61d
JM		 2668static struct mlx5_interface mlx5_ib_interface = {
2669 .add = mlx5_ib_add,
2670 .remove = mlx5_ib_remove,
2671 .event = mlx5_ib_event,
64613d94 2672 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 2673};
2674
2675static int __init mlx5_ib_init(void)
2676{
6aec21f6
HE		 2677 int err;
2678
9603b61d
JM		 2679 if (deprecated_prof_sel != 2)
2680 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2681
6aec21f6
HE		 2682 err = mlx5_ib_odp_init();
2683 if (err)
2684 return err;
2685
2686 err = mlx5_register_interface(&mlx5_ib_interface);
2687 if (err)
2688 goto clean_odp;
2689
2690 return err;
2691
2692clean_odp:
2693 mlx5_ib_odp_cleanup();
2694 return err;
e126ba97
EC		 2695}
2696
2697static void __exit mlx5_ib_cleanup(void)
2698{
9603b61d 2699 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 2700 mlx5_ib_odp_cleanup();
e126ba97
EC		 2701}
2702
2703module_init(mlx5_ib_init);
2704module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)