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net/mlx5: Add multi dest support
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
37aa5c36
GL		 40#if defined(CONFIG_X86)
41#include <asm/pat.h>
42#endif
e126ba97 43#include <linux/sched.h>
7c2344c3 44#include <linux/delay.h>
e126ba97 45#include <rdma/ib_user_verbs.h>
3f89a643 46#include <rdma/ib_addr.h>
2811ba51 47#include <rdma/ib_cache.h>
ada68c31 48#include <linux/mlx5/port.h>
1b5daf11 49#include <linux/mlx5/vport.h>
7c2344c3 50#include <linux/list.h>
e126ba97
EC		 51#include <rdma/ib_smi.h>
52#include <rdma/ib_umem.h>
038d2ef8
MG		 53#include <linux/in.h>
54#include <linux/etherdevice.h>
55#include <linux/mlx5/fs.h>
e126ba97
EC		 56#include "mlx5_ib.h"
57
58#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 59#define DRIVER_VERSION "2.2-1"
60#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 61
62MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64MODULE_LICENSE("Dual BSD/GPL");
65MODULE_VERSION(DRIVER_VERSION);
66
9603b61d
JM		 67static int deprecated_prof_sel = 2;
68module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
69MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 70
71static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
74
da7525d2
EBE		 75enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77};
78
1b5daf11 79static enum rdma_link_layer
ebd61f68 80mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 81{
ebd61f68 82 switch (port_type_cap) {
1b5daf11
MD		 83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90}
91
ebd61f68
AS		 92static enum rdma_link_layer
93mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94{
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99}
100
fc24fc5e
AS		 101static int mlx5_netdev_event(struct notifier_block *this,
102 unsigned long event, void *ptr)
103{
104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
106 roce.nb);
107
5ec8c83e
AH		 108 switch (event) {
109 case NETDEV_REGISTER:
110 case NETDEV_UNREGISTER:
111 write_lock(&ibdev->roce.netdev_lock);
112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
114 NULL : ndev;
115 write_unlock(&ibdev->roce.netdev_lock);
116 break;
fc24fc5e 117
5ec8c83e 118 case NETDEV_UP:
88621dfe
AH		 119 case NETDEV_DOWN: {
120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
121 struct net_device *upper = NULL;
122
123 if (lag_ndev) {
124 upper = netdev_master_upper_dev_get(lag_ndev);
125 dev_put(lag_ndev);
126 }
127
128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129 && ibdev->ib_active) {
5ec8c83e
AH		 130 struct ib_event ibev = {0};
131
132 ibev.device = &ibdev->ib_dev;
133 ibev.event = (event == NETDEV_UP) ?
134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
135 ibev.element.port_num = 1;
136 ib_dispatch_event(&ibev);
137 }
138 break;
88621dfe 139 }
fc24fc5e 140
5ec8c83e
AH		 141 default:
142 break;
143 }
fc24fc5e
AS		 144
145 return NOTIFY_DONE;
146}
147
148static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
149 u8 port_num)
150{
151 struct mlx5_ib_dev *ibdev = to_mdev(device);
152 struct net_device *ndev;
153
88621dfe
AH		 154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
155 if (ndev)
156 return ndev;
157
fc24fc5e
AS		 158 /* Ensure ndev does not disappear before we invoke dev_hold()
159 */
160 read_lock(&ibdev->roce.netdev_lock);
161 ndev = ibdev->roce.netdev;
162 if (ndev)
163 dev_hold(ndev);
164 read_unlock(&ibdev->roce.netdev_lock);
165
166 return ndev;
167}
168
3f89a643
AS		 169static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
170 struct ib_port_attr *props)
171{
172 struct mlx5_ib_dev *dev = to_mdev(device);
88621dfe 173 struct net_device *ndev, *upper;
3f89a643 174 enum ib_mtu ndev_ib_mtu;
c876a1b7 175 u16 qkey_viol_cntr;
3f89a643
AS		 176
177 memset(props, 0, sizeof(*props));
178
179 props->port_cap_flags |= IB_PORT_CM_SUP;
180 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
181
182 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
183 roce_address_table_size);
184 props->max_mtu = IB_MTU_4096;
185 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
186 props->pkey_tbl_len = 1;
187 props->state = IB_PORT_DOWN;
188 props->phys_state = 3;
189
c876a1b7
LR		 190 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
191 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 192
193 ndev = mlx5_ib_get_netdev(device, port_num);
194 if (!ndev)
195 return 0;
196
88621dfe
AH		 197 if (mlx5_lag_is_active(dev->mdev)) {
198 rcu_read_lock();
199 upper = netdev_master_upper_dev_get_rcu(ndev);
200 if (upper) {
201 dev_put(ndev);
202 ndev = upper;
203 dev_hold(ndev);
204 }
205 rcu_read_unlock();
206 }
207
3f89a643
AS		 208 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
209 props->state = IB_PORT_ACTIVE;
210 props->phys_state = 5;
211 }
212
213 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
214
215 dev_put(ndev);
216
217 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
218
219 props->active_width = IB_WIDTH_4X; /* TODO */
220 props->active_speed = IB_SPEED_QDR; /* TODO */
221
222 return 0;
223}
224
3cca2606
AS		 225static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
226 const struct ib_gid_attr *attr,
227 void *mlx5_addr)
228{
229#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
231 source_l3_address);
232 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
233 source_mac_47_32);
234
235 if (!gid)
236 return;
237
238 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
239
240 if (is_vlan_dev(attr->ndev)) {
241 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
242 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
243 }
244
245 switch (attr->gid_type) {
246 case IB_GID_TYPE_IB:
247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
248 break;
249 case IB_GID_TYPE_ROCE_UDP_ENCAP:
250 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
251 break;
252
253 default:
254 WARN_ON(true);
255 }
256
257 if (attr->gid_type != IB_GID_TYPE_IB) {
258 if (ipv6_addr_v4mapped((void *)gid))
259 MLX5_SET_RA(mlx5_addr, roce_l3_type,
260 MLX5_ROCE_L3_TYPE_IPV4);
261 else
262 MLX5_SET_RA(mlx5_addr, roce_l3_type,
263 MLX5_ROCE_L3_TYPE_IPV6);
264 }
265
266 if ((attr->gid_type == IB_GID_TYPE_IB) ||
267 !ipv6_addr_v4mapped((void *)gid))
268 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
269 else
270 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
271}
272
273static int set_roce_addr(struct ib_device *device, u8 port_num,
274 unsigned int index,
275 const union ib_gid *gid,
276 const struct ib_gid_attr *attr)
277{
c4f287c4
SM		 278 struct mlx5_ib_dev *dev = to_mdev(device);
279 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
280 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
3cca2606
AS		 281 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
282 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
283
284 if (ll != IB_LINK_LAYER_ETHERNET)
285 return -EINVAL;
286
3cca2606
AS		 287 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
288
289 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
290 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
3cca2606
AS		 291 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
292}
293
294static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
295 unsigned int index, const union ib_gid *gid,
296 const struct ib_gid_attr *attr,
297 __always_unused void **context)
298{
299 return set_roce_addr(device, port_num, index, gid, attr);
300}
301
302static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
303 unsigned int index, __always_unused void **context)
304{
305 return set_roce_addr(device, port_num, index, NULL, NULL);
306}
307
2811ba51
AS		 308__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
309 int index)
310{
311 struct ib_gid_attr attr;
312 union ib_gid gid;
313
314 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
315 return 0;
316
317 if (!attr.ndev)
318 return 0;
319
320 dev_put(attr.ndev);
321
322 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
323 return 0;
324
325 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
326}
327
1b5daf11
MD		 328static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
329{
7fae6655
NO		 330 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
331 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
332 return 0;
1b5daf11
MD		 333}
334
335enum {
336 MLX5_VPORT_ACCESS_METHOD_MAD,
337 MLX5_VPORT_ACCESS_METHOD_HCA,
338 MLX5_VPORT_ACCESS_METHOD_NIC,
339};
340
341static int mlx5_get_vport_access_method(struct ib_device *ibdev)
342{
343 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
344 return MLX5_VPORT_ACCESS_METHOD_MAD;
345
ebd61f68 346 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 347 IB_LINK_LAYER_ETHERNET)
348 return MLX5_VPORT_ACCESS_METHOD_NIC;
349
350 return MLX5_VPORT_ACCESS_METHOD_HCA;
351}
352
da7525d2
EBE		 353static void get_atomic_caps(struct mlx5_ib_dev *dev,
354 struct ib_device_attr *props)
355{
356 u8 tmp;
357 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
358 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
359 u8 atomic_req_8B_endianness_mode =
360 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
361
362 /* Check if HW supports 8 bytes standard atomic operations and capable
363 * of host endianness respond
364 */
365 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
366 if (((atomic_operations & tmp) == tmp) &&
367 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
368 (atomic_req_8B_endianness_mode)) {
369 props->atomic_cap = IB_ATOMIC_HCA;
370 } else {
371 props->atomic_cap = IB_ATOMIC_NONE;
372 }
373}
374
1b5daf11
MD		 375static int mlx5_query_system_image_guid(struct ib_device *ibdev,
376 __be64 *sys_image_guid)
377{
378 struct mlx5_ib_dev *dev = to_mdev(ibdev);
379 struct mlx5_core_dev *mdev = dev->mdev;
380 u64 tmp;
381 int err;
382
383 switch (mlx5_get_vport_access_method(ibdev)) {
384 case MLX5_VPORT_ACCESS_METHOD_MAD:
385 return mlx5_query_mad_ifc_system_image_guid(ibdev,
386 sys_image_guid);
387
388 case MLX5_VPORT_ACCESS_METHOD_HCA:
389 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 390 break;
391
392 case MLX5_VPORT_ACCESS_METHOD_NIC:
393 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
394 break;
1b5daf11
MD		 395
396 default:
397 return -EINVAL;
398 }
3f89a643
AS		 399
400 if (!err)
401 *sys_image_guid = cpu_to_be64(tmp);
402
403 return err;
404
1b5daf11
MD		 405}
406
407static int mlx5_query_max_pkeys(struct ib_device *ibdev,
408 u16 *max_pkeys)
409{
410 struct mlx5_ib_dev *dev = to_mdev(ibdev);
411 struct mlx5_core_dev *mdev = dev->mdev;
412
413 switch (mlx5_get_vport_access_method(ibdev)) {
414 case MLX5_VPORT_ACCESS_METHOD_MAD:
415 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
416
417 case MLX5_VPORT_ACCESS_METHOD_HCA:
418 case MLX5_VPORT_ACCESS_METHOD_NIC:
419 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
420 pkey_table_size));
421 return 0;
422
423 default:
424 return -EINVAL;
425 }
426}
427
428static int mlx5_query_vendor_id(struct ib_device *ibdev,
429 u32 *vendor_id)
430{
431 struct mlx5_ib_dev *dev = to_mdev(ibdev);
432
433 switch (mlx5_get_vport_access_method(ibdev)) {
434 case MLX5_VPORT_ACCESS_METHOD_MAD:
435 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
436
437 case MLX5_VPORT_ACCESS_METHOD_HCA:
438 case MLX5_VPORT_ACCESS_METHOD_NIC:
439 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
440
441 default:
442 return -EINVAL;
443 }
444}
445
446static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
447 __be64 *node_guid)
448{
449 u64 tmp;
450 int err;
451
452 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
453 case MLX5_VPORT_ACCESS_METHOD_MAD:
454 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
455
456 case MLX5_VPORT_ACCESS_METHOD_HCA:
457 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 458 break;
459
460 case MLX5_VPORT_ACCESS_METHOD_NIC:
461 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
462 break;
1b5daf11
MD		 463
464 default:
465 return -EINVAL;
466 }
3f89a643
AS		 467
468 if (!err)
469 *node_guid = cpu_to_be64(tmp);
470
471 return err;
1b5daf11
MD		 472}
473
474struct mlx5_reg_node_desc {
bd99fdea 475 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 476};
477
478static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
479{
480 struct mlx5_reg_node_desc in;
481
482 if (mlx5_use_mad_ifc(dev))
483 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
484
485 memset(&in, 0, sizeof(in));
486
487 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
488 sizeof(struct mlx5_reg_node_desc),
489 MLX5_REG_NODE_DESC, 0, 0);
490}
491
e126ba97 492static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 493 struct ib_device_attr *props,
494 struct ib_udata *uhw)
e126ba97
EC		 495{
496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 497 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 498 int err = -ENOMEM;
499 int max_rq_sg;
500 int max_sq_sg;
e0238a6a 501 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 502 struct mlx5_ib_query_device_resp resp = {};
503 size_t resp_len;
504 u64 max_tso;
e126ba97 505
402ca536
BW		 506 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
507 if (uhw->outlen && uhw->outlen < resp_len)
508 return -EINVAL;
509 else
510 resp.response_length = resp_len;
511
512 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 513 return -EINVAL;
514
1b5daf11
MD		 515 memset(props, 0, sizeof(*props));
516 err = mlx5_query_system_image_guid(ibdev,
517 &props->sys_image_guid);
518 if (err)
519 return err;
e126ba97 520
1b5daf11 521 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 522 if (err)
1b5daf11 523 return err;
e126ba97 524
1b5daf11
MD		 525 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
526 if (err)
527 return err;
e126ba97 528
9603b61d
JM		 529 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
530 (fw_rev_min(dev->mdev) << 16) |
531 fw_rev_sub(dev->mdev);
e126ba97
EC		 532 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
533 IB_DEVICE_PORT_ACTIVE_EVENT |
534 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 535 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 536
537 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 538 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 539 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 540 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 541 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 542 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 543 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 544 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 545 if (MLX5_CAP_GEN(mdev, imaicl)) {
546 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
547 IB_DEVICE_MEM_WINDOW_TYPE_2B;
548 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 549 /* We support 'Gappy' memory registration too */
550 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 551 }
e126ba97 552 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 553 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 554 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
555 /* At this stage no support for signature handover */
556 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
557 IB_PROT_T10DIF_TYPE_2 |
558 IB_PROT_T10DIF_TYPE_3;
559 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
560 IB_GUARD_T10DIF_CSUM;
561 }
938fe83c 562 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 563 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 564
402ca536
BW		 565 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
566 if (MLX5_CAP_ETH(mdev, csum_cap))
88115fe7
BW		 567 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
568
402ca536
BW		 569 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
570 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
571 if (max_tso) {
572 resp.tso_caps.max_tso = 1 << max_tso;
573 resp.tso_caps.supported_qpts |=
574 1 << IB_QPT_RAW_PACKET;
575 resp.response_length += sizeof(resp.tso_caps);
576 }
577 }
31f69a82
YH		 578
579 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
580 resp.rss_caps.rx_hash_function =
581 MLX5_RX_HASH_FUNC_TOEPLITZ;
582 resp.rss_caps.rx_hash_fields_mask =
583 MLX5_RX_HASH_SRC_IPV4 |
584 MLX5_RX_HASH_DST_IPV4 |
585 MLX5_RX_HASH_SRC_IPV6 |
586 MLX5_RX_HASH_DST_IPV6 |
587 MLX5_RX_HASH_SRC_PORT_TCP |
588 MLX5_RX_HASH_DST_PORT_TCP |
589 MLX5_RX_HASH_SRC_PORT_UDP |
590 MLX5_RX_HASH_DST_PORT_UDP;
591 resp.response_length += sizeof(resp.rss_caps);
592 }
593 } else {
594 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
595 resp.response_length += sizeof(resp.tso_caps);
596 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
597 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 598 }
599
f0313965
ES		 600 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
601 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
602 props->device_cap_flags |= IB_DEVICE_UD_TSO;
603 }
604
cff5a0f3
MD		 605 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
606 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
607 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
608
da6d6ba3
MG		 609 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
610 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
611
1b5daf11
MD		 612 props->vendor_part_id = mdev->pdev->device;
613 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 614
615 props->max_mr_size = ~0ull;
e0238a6a 616 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 617 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
618 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
619 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
620 sizeof(struct mlx5_wqe_data_seg);
621 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
622 sizeof(struct mlx5_wqe_ctrl_seg)) /
623 sizeof(struct mlx5_wqe_data_seg);
e126ba97 624 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 625 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 626 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 627 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 628 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
629 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
630 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
631 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
632 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
633 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
634 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 635 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 636 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 637 props->max_fast_reg_page_list_len =
638 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
da7525d2 639 get_atomic_caps(dev, props);
81bea28f 640 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 641 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
642 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 643 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
644 props->max_mcast_grp;
645 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
7c60bcbb
MB		 646 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
647 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 648
8cdd312c 649#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 650 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 651 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
652 props->odp_caps = dev->odp_caps;
653#endif
654
051f2630
LR		 655 if (MLX5_CAP_GEN(mdev, cd))
656 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
657
eff901d3
EC		 658 if (!mlx5_core_is_pf(mdev))
659 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
660
31f69a82
YH		 661 if (mlx5_ib_port_link_layer(ibdev, 1) ==
662 IB_LINK_LAYER_ETHERNET) {
663 props->rss_caps.max_rwq_indirection_tables =
664 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
665 props->rss_caps.max_rwq_indirection_table_size =
666 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
667 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
668 props->max_wq_type_rq =
669 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
670 }
671
402ca536
BW		 672 if (uhw->outlen) {
673 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
674
675 if (err)
676 return err;
677 }
678
1b5daf11 679 return 0;
e126ba97
EC		 680}
681
1b5daf11
MD		 682enum mlx5_ib_width {
683 MLX5_IB_WIDTH_1X = 1 << 0,
684 MLX5_IB_WIDTH_2X = 1 << 1,
685 MLX5_IB_WIDTH_4X = 1 << 2,
686 MLX5_IB_WIDTH_8X = 1 << 3,
687 MLX5_IB_WIDTH_12X = 1 << 4
688};
689
690static int translate_active_width(struct ib_device *ibdev, u8 active_width,
691 u8 *ib_width)
e126ba97
EC		 692{
693 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 694 int err = 0;
695
696 if (active_width & MLX5_IB_WIDTH_1X) {
697 *ib_width = IB_WIDTH_1X;
698 } else if (active_width & MLX5_IB_WIDTH_2X) {
699 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
700 (int)active_width);
701 err = -EINVAL;
702 } else if (active_width & MLX5_IB_WIDTH_4X) {
703 *ib_width = IB_WIDTH_4X;
704 } else if (active_width & MLX5_IB_WIDTH_8X) {
705 *ib_width = IB_WIDTH_8X;
706 } else if (active_width & MLX5_IB_WIDTH_12X) {
707 *ib_width = IB_WIDTH_12X;
708 } else {
709 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
710 (int)active_width);
711 err = -EINVAL;
e126ba97
EC		 712 }
713
1b5daf11
MD		 714 return err;
715}
e126ba97 716
1b5daf11
MD		 717static int mlx5_mtu_to_ib_mtu(int mtu)
718{
719 switch (mtu) {
720 case 256: return 1;
721 case 512: return 2;
722 case 1024: return 3;
723 case 2048: return 4;
724 case 4096: return 5;
725 default:
726 pr_warn("invalid mtu\n");
727 return -1;
e126ba97 728 }
1b5daf11 729}
e126ba97 730
1b5daf11
MD		 731enum ib_max_vl_num {
732 __IB_MAX_VL_0 = 1,
733 __IB_MAX_VL_0_1 = 2,
734 __IB_MAX_VL_0_3 = 3,
735 __IB_MAX_VL_0_7 = 4,
736 __IB_MAX_VL_0_14 = 5,
737};
e126ba97 738
1b5daf11
MD		 739enum mlx5_vl_hw_cap {
740 MLX5_VL_HW_0 = 1,
741 MLX5_VL_HW_0_1 = 2,
742 MLX5_VL_HW_0_2 = 3,
743 MLX5_VL_HW_0_3 = 4,
744 MLX5_VL_HW_0_4 = 5,
745 MLX5_VL_HW_0_5 = 6,
746 MLX5_VL_HW_0_6 = 7,
747 MLX5_VL_HW_0_7 = 8,
748 MLX5_VL_HW_0_14 = 15
749};
e126ba97 750
1b5daf11
MD		 751static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
752 u8 *max_vl_num)
753{
754 switch (vl_hw_cap) {
755 case MLX5_VL_HW_0:
756 *max_vl_num = __IB_MAX_VL_0;
757 break;
758 case MLX5_VL_HW_0_1:
759 *max_vl_num = __IB_MAX_VL_0_1;
760 break;
761 case MLX5_VL_HW_0_3:
762 *max_vl_num = __IB_MAX_VL_0_3;
763 break;
764 case MLX5_VL_HW_0_7:
765 *max_vl_num = __IB_MAX_VL_0_7;
766 break;
767 case MLX5_VL_HW_0_14:
768 *max_vl_num = __IB_MAX_VL_0_14;
769 break;
e126ba97 770
1b5daf11
MD		 771 default:
772 return -EINVAL;
e126ba97 773 }
e126ba97 774
1b5daf11 775 return 0;
e126ba97
EC		 776}
777
1b5daf11
MD		 778static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
779 struct ib_port_attr *props)
e126ba97 780{
1b5daf11
MD		 781 struct mlx5_ib_dev *dev = to_mdev(ibdev);
782 struct mlx5_core_dev *mdev = dev->mdev;
783 struct mlx5_hca_vport_context *rep;
046339ea
SM		 784 u16 max_mtu;
785 u16 oper_mtu;
1b5daf11
MD		 786 int err;
787 u8 ib_link_width_oper;
788 u8 vl_hw_cap;
e126ba97 789
1b5daf11
MD		 790 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
791 if (!rep) {
792 err = -ENOMEM;
e126ba97 793 goto out;
e126ba97 794 }
e126ba97 795
1b5daf11 796 memset(props, 0, sizeof(*props));
e126ba97 797
1b5daf11 798 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 799 if (err)
800 goto out;
801
1b5daf11
MD		 802 props->lid = rep->lid;
803 props->lmc = rep->lmc;
804 props->sm_lid = rep->sm_lid;
805 props->sm_sl = rep->sm_sl;
806 props->state = rep->vport_state;
807 props->phys_state = rep->port_physical_state;
808 props->port_cap_flags = rep->cap_mask1;
809 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
810 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
811 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
812 props->bad_pkey_cntr = rep->pkey_violation_counter;
813 props->qkey_viol_cntr = rep->qkey_violation_counter;
814 props->subnet_timeout = rep->subnet_timeout;
815 props->init_type_reply = rep->init_type_reply;
eff901d3 816 props->grh_required = rep->grh_required;
e126ba97 817
1b5daf11
MD		 818 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
819 if (err)
e126ba97 820 goto out;
e126ba97 821
1b5daf11
MD		 822 err = translate_active_width(ibdev, ib_link_width_oper,
823 &props->active_width);
824 if (err)
825 goto out;
d5beb7f2 826 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 827 if (err)
828 goto out;
829
facc9699 830 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 831
1b5daf11 832 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 833
facc9699 834 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 835
1b5daf11 836 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 837
1b5daf11
MD		 838 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
839 if (err)
840 goto out;
e126ba97 841
1b5daf11
MD		 842 err = translate_max_vl_num(ibdev, vl_hw_cap,
843 &props->max_vl_num);
e126ba97 844out:
1b5daf11 845 kfree(rep);
e126ba97
EC		 846 return err;
847}
848
1b5daf11
MD		 849int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
850 struct ib_port_attr *props)
e126ba97 851{
1b5daf11
MD		 852 switch (mlx5_get_vport_access_method(ibdev)) {
853 case MLX5_VPORT_ACCESS_METHOD_MAD:
854 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 855
1b5daf11
MD		 856 case MLX5_VPORT_ACCESS_METHOD_HCA:
857 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 858
3f89a643
AS		 859 case MLX5_VPORT_ACCESS_METHOD_NIC:
860 return mlx5_query_port_roce(ibdev, port, props);
861
1b5daf11
MD		 862 default:
863 return -EINVAL;
864 }
865}
e126ba97 866
1b5daf11
MD		 867static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
868 union ib_gid *gid)
869{
870 struct mlx5_ib_dev *dev = to_mdev(ibdev);
871 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 872
1b5daf11
MD		 873 switch (mlx5_get_vport_access_method(ibdev)) {
874 case MLX5_VPORT_ACCESS_METHOD_MAD:
875 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 876
1b5daf11
MD		 877 case MLX5_VPORT_ACCESS_METHOD_HCA:
878 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
879
880 default:
881 return -EINVAL;
882 }
e126ba97 883
e126ba97
EC		 884}
885
1b5daf11
MD		 886static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
887 u16 *pkey)
888{
889 struct mlx5_ib_dev *dev = to_mdev(ibdev);
890 struct mlx5_core_dev *mdev = dev->mdev;
891
892 switch (mlx5_get_vport_access_method(ibdev)) {
893 case MLX5_VPORT_ACCESS_METHOD_MAD:
894 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
895
896 case MLX5_VPORT_ACCESS_METHOD_HCA:
897 case MLX5_VPORT_ACCESS_METHOD_NIC:
898 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
899 pkey);
900 default:
901 return -EINVAL;
902 }
903}
e126ba97
EC		 904
905static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
906 struct ib_device_modify *props)
907{
908 struct mlx5_ib_dev *dev = to_mdev(ibdev);
909 struct mlx5_reg_node_desc in;
910 struct mlx5_reg_node_desc out;
911 int err;
912
913 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
914 return -EOPNOTSUPP;
915
916 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
917 return 0;
918
919 /*
920 * If possible, pass node desc to FW, so it can generate
921 * a 144 trap. If cmd fails, just ignore.
922 */
bd99fdea 923 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 924 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 925 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
926 if (err)
927 return err;
928
bd99fdea 929 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 930
931 return err;
932}
933
934static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
935 struct ib_port_modify *props)
936{
937 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938 struct ib_port_attr attr;
939 u32 tmp;
940 int err;
941
942 mutex_lock(&dev->cap_mask_mutex);
943
944 err = mlx5_ib_query_port(ibdev, port, &attr);
945 if (err)
946 goto out;
947
948 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
949 ~props->clr_port_cap_mask;
950
9603b61d 951 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 952
953out:
954 mutex_unlock(&dev->cap_mask_mutex);
955 return err;
956}
957
958static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
959 struct ib_udata *udata)
960{
961 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 962 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
963 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97
EC		 964 struct mlx5_ib_ucontext *context;
965 struct mlx5_uuar_info *uuari;
966 struct mlx5_uar *uars;
c1be5232 967 int gross_uuars;
e126ba97 968 int num_uars;
78c0f98c 969 int ver;
e126ba97
EC		 970 int uuarn;
971 int err;
972 int i;
f241e749 973 size_t reqlen;
a168a41c
MD		 974 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
975 max_cqe_version);
e126ba97
EC		 976
977 if (!dev->ib_active)
978 return ERR_PTR(-EAGAIN);
979
dfbee859
HA		 980 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
981 return ERR_PTR(-EINVAL);
982
78c0f98c
EC		 983 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
984 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
985 ver = 0;
a168a41c 986 else if (reqlen >= min_req_v2)
78c0f98c
EC		 987 ver = 2;
988 else
989 return ERR_PTR(-EINVAL);
990
b368d7cb 991 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
e126ba97
EC		 992 if (err)
993 return ERR_PTR(err);
994
b368d7cb 995 if (req.flags)
78c0f98c
EC		 996 return ERR_PTR(-EINVAL);
997
e126ba97
EC		 998 if (req.total_num_uuars > MLX5_MAX_UUARS)
999 return ERR_PTR(-ENOMEM);
1000
1001 if (req.total_num_uuars == 0)
1002 return ERR_PTR(-EINVAL);
1003
f72300c5 1004 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1005 return ERR_PTR(-EOPNOTSUPP);
1006
1007 if (reqlen > sizeof(req) &&
1008 !ib_is_udata_cleared(udata, sizeof(req),
dfbee859 1009 reqlen - sizeof(req)))
b368d7cb
MB		 1010 return ERR_PTR(-EOPNOTSUPP);
1011
c1be5232
EC		 1012 req.total_num_uuars = ALIGN(req.total_num_uuars,
1013 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 1014 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1015 return ERR_PTR(-EINVAL);
1016
c1be5232
EC		 1017 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1018 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c 1019 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1020 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1021 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
938fe83c
SM		 1022 resp.cache_line_size = L1_CACHE_BYTES;
1023 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1024 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1025 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1026 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1027 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1028 resp.cqe_version = min_t(__u8,
1029 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1030 req.max_cqe_version);
b368d7cb
MB		 1031 resp.response_length = min(offsetof(typeof(resp), response_length) +
1032 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1033
1034 context = kzalloc(sizeof(*context), GFP_KERNEL);
1035 if (!context)
1036 return ERR_PTR(-ENOMEM);
1037
1038 uuari = &context->uuari;
1039 mutex_init(&uuari->lock);
1040 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1041 if (!uars) {
1042 err = -ENOMEM;
1043 goto out_ctx;
1044 }
1045
c1be5232 1046 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 1047 sizeof(*uuari->bitmap),
1048 GFP_KERNEL);
1049 if (!uuari->bitmap) {
1050 err = -ENOMEM;
1051 goto out_uar_ctx;
1052 }
1053 /*
1054 * clear all fast path uuars
1055 */
c1be5232 1056 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 1057 uuarn = i & 3;
1058 if (uuarn == 2 || uuarn == 3)
1059 set_bit(i, uuari->bitmap);
1060 }
1061
c1be5232 1062 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 1063 if (!uuari->count) {
1064 err = -ENOMEM;
1065 goto out_bitmap;
1066 }
1067
1068 for (i = 0; i < num_uars; i++) {
9603b61d 1069 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 1070 if (err)
1071 goto out_count;
1072 }
1073
b4cfe447
HE		 1074#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1075 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1076#endif
1077
146d2f1a 1078 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1079 err = mlx5_core_alloc_transport_domain(dev->mdev,
1080 &context->tdn);
1081 if (err)
1082 goto out_uars;
1083 }
1084
7c2344c3 1085 INIT_LIST_HEAD(&context->vma_private_list);
e126ba97
EC		 1086 INIT_LIST_HEAD(&context->db_page_list);
1087 mutex_init(&context->db_page_mutex);
1088
1089 resp.tot_uuars = req.total_num_uuars;
938fe83c 1090 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
b368d7cb 1091
f72300c5
HA		 1092 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1093 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1094
402ca536
BW		 1095 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1096 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1097 resp.response_length += sizeof(resp.cmds_supp_uhw);
1098 }
1099
bc5c6eed
NO		 1100 /*
1101 * We don't want to expose information from the PCI bar that is located
1102 * after 4096 bytes, so if the arch only supports larger pages, let's
1103 * pretend we don't support reading the HCA's core clock. This is also
1104 * forced by mmap function.
1105 */
1106 if (PAGE_SIZE <= 4096 &&
1107 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
b368d7cb
MB		 1108 resp.comp_mask |=
1109 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1110 resp.hca_core_clock_offset =
1111 offsetof(struct mlx5_init_seg, internal_timer_h) %
1112 PAGE_SIZE;
f72300c5 1113 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1114 sizeof(resp.reserved2);
b368d7cb
MB		 1115 }
1116
1117 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1118 if (err)
146d2f1a 1119 goto out_td;
e126ba97 1120
78c0f98c 1121 uuari->ver = ver;
e126ba97
EC		 1122 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1123 uuari->uars = uars;
1124 uuari->num_uars = num_uars;
f72300c5
HA		 1125 context->cqe_version = resp.cqe_version;
1126
e126ba97
EC		 1127 return &context->ibucontext;
1128
146d2f1a 1129out_td:
1130 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1131 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1132
e126ba97
EC		 1133out_uars:
1134 for (i--; i >= 0; i--)
9603b61d 1135 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 1136out_count:
1137 kfree(uuari->count);
1138
1139out_bitmap:
1140 kfree(uuari->bitmap);
1141
1142out_uar_ctx:
1143 kfree(uars);
1144
1145out_ctx:
1146 kfree(context);
1147 return ERR_PTR(err);
1148}
1149
1150static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1151{
1152 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1153 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1154 struct mlx5_uuar_info *uuari = &context->uuari;
1155 int i;
1156
146d2f1a 1157 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1158 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1159
e126ba97 1160 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 1161 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 1162 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1163 }
1164
1165 kfree(uuari->count);
1166 kfree(uuari->bitmap);
1167 kfree(uuari->uars);
1168 kfree(context);
1169
1170 return 0;
1171}
1172
1173static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1174{
9603b61d 1175 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 1176}
1177
1178static int get_command(unsigned long offset)
1179{
1180 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1181}
1182
1183static int get_arg(unsigned long offset)
1184{
1185 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1186}
1187
1188static int get_index(unsigned long offset)
1189{
1190 return get_arg(offset);
1191}
1192
7c2344c3
MG		 1193static void mlx5_ib_vma_open(struct vm_area_struct *area)
1194{
1195 /* vma_open is called when a new VMA is created on top of our VMA. This
1196 * is done through either mremap flow or split_vma (usually due to
1197 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1198 * as this VMA is strongly hardware related. Therefore we set the
1199 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1200 * calling us again and trying to do incorrect actions. We assume that
1201 * the original VMA size is exactly a single page, and therefore all
1202 * "splitting" operation will not happen to it.
1203 */
1204 area->vm_ops = NULL;
1205}
1206
1207static void mlx5_ib_vma_close(struct vm_area_struct *area)
1208{
1209 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1210
1211 /* It's guaranteed that all VMAs opened on a FD are closed before the
1212 * file itself is closed, therefore no sync is needed with the regular
1213 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1214 * However need a sync with accessing the vma as part of
1215 * mlx5_ib_disassociate_ucontext.
1216 * The close operation is usually called under mm->mmap_sem except when
1217 * process is exiting.
1218 * The exiting case is handled explicitly as part of
1219 * mlx5_ib_disassociate_ucontext.
1220 */
1221 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1222
1223 /* setting the vma context pointer to null in the mlx5_ib driver's
1224 * private data, to protect a race condition in
1225 * mlx5_ib_disassociate_ucontext().
1226 */
1227 mlx5_ib_vma_priv_data->vma = NULL;
1228 list_del(&mlx5_ib_vma_priv_data->list);
1229 kfree(mlx5_ib_vma_priv_data);
1230}
1231
1232static const struct vm_operations_struct mlx5_ib_vm_ops = {
1233 .open = mlx5_ib_vma_open,
1234 .close = mlx5_ib_vma_close
1235};
1236
1237static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1238 struct mlx5_ib_ucontext *ctx)
1239{
1240 struct mlx5_ib_vma_private_data *vma_prv;
1241 struct list_head *vma_head = &ctx->vma_private_list;
1242
1243 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1244 if (!vma_prv)
1245 return -ENOMEM;
1246
1247 vma_prv->vma = vma;
1248 vma->vm_private_data = vma_prv;
1249 vma->vm_ops = &mlx5_ib_vm_ops;
1250
1251 list_add(&vma_prv->list, vma_head);
1252
1253 return 0;
1254}
1255
1256static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1257{
1258 int ret;
1259 struct vm_area_struct *vma;
1260 struct mlx5_ib_vma_private_data *vma_private, *n;
1261 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1262 struct task_struct *owning_process = NULL;
1263 struct mm_struct *owning_mm = NULL;
1264
1265 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1266 if (!owning_process)
1267 return;
1268
1269 owning_mm = get_task_mm(owning_process);
1270 if (!owning_mm) {
1271 pr_info("no mm, disassociate ucontext is pending task termination\n");
1272 while (1) {
1273 put_task_struct(owning_process);
1274 usleep_range(1000, 2000);
1275 owning_process = get_pid_task(ibcontext->tgid,
1276 PIDTYPE_PID);
1277 if (!owning_process ||
1278 owning_process->state == TASK_DEAD) {
1279 pr_info("disassociate ucontext done, task was terminated\n");
1280 /* in case task was dead need to release the
1281 * task struct.
1282 */
1283 if (owning_process)
1284 put_task_struct(owning_process);
1285 return;
1286 }
1287 }
1288 }
1289
1290 /* need to protect from a race on closing the vma as part of
1291 * mlx5_ib_vma_close.
1292 */
1293 down_read(&owning_mm->mmap_sem);
1294 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1295 list) {
1296 vma = vma_private->vma;
1297 ret = zap_vma_ptes(vma, vma->vm_start,
1298 PAGE_SIZE);
1299 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1300 /* context going to be destroyed, should
1301 * not access ops any more.
1302 */
1303 vma->vm_ops = NULL;
1304 list_del(&vma_private->list);
1305 kfree(vma_private);
1306 }
1307 up_read(&owning_mm->mmap_sem);
1308 mmput(owning_mm);
1309 put_task_struct(owning_process);
1310}
1311
37aa5c36
GL		 1312static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1313{
1314 switch (cmd) {
1315 case MLX5_IB_MMAP_WC_PAGE:
1316 return "WC";
1317 case MLX5_IB_MMAP_REGULAR_PAGE:
1318 return "best effort WC";
1319 case MLX5_IB_MMAP_NC_PAGE:
1320 return "NC";
1321 default:
1322 return NULL;
1323 }
1324}
1325
1326static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1327 struct vm_area_struct *vma,
1328 struct mlx5_ib_ucontext *context)
37aa5c36 1329{
7c2344c3 1330 struct mlx5_uuar_info *uuari = &context->uuari;
37aa5c36
GL		 1331 int err;
1332 unsigned long idx;
1333 phys_addr_t pfn, pa;
1334 pgprot_t prot;
1335
1336 switch (cmd) {
1337 case MLX5_IB_MMAP_WC_PAGE:
1338/* Some architectures don't support WC memory */
1339#if defined(CONFIG_X86)
1340 if (!pat_enabled())
1341 return -EPERM;
1342#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1343 return -EPERM;
1344#endif
1345 /* fall through */
1346 case MLX5_IB_MMAP_REGULAR_PAGE:
1347 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1348 prot = pgprot_writecombine(vma->vm_page_prot);
1349 break;
1350 case MLX5_IB_MMAP_NC_PAGE:
1351 prot = pgprot_noncached(vma->vm_page_prot);
1352 break;
1353 default:
1354 return -EINVAL;
1355 }
1356
1357 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1358 return -EINVAL;
1359
1360 idx = get_index(vma->vm_pgoff);
1361 if (idx >= uuari->num_uars)
1362 return -EINVAL;
1363
1364 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1365 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1366
1367 vma->vm_page_prot = prot;
1368 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1369 PAGE_SIZE, vma->vm_page_prot);
1370 if (err) {
1371 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1372 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1373 return -EAGAIN;
1374 }
1375
1376 pa = pfn << PAGE_SHIFT;
1377 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1378 vma->vm_start, &pa);
1379
7c2344c3 1380 return mlx5_ib_set_vma_data(vma, context);
37aa5c36
GL		 1381}
1382
e126ba97
EC		 1383static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1384{
1385 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1386 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 1387 unsigned long command;
e126ba97
EC		 1388 phys_addr_t pfn;
1389
1390 command = get_command(vma->vm_pgoff);
1391 switch (command) {
37aa5c36
GL		 1392 case MLX5_IB_MMAP_WC_PAGE:
1393 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 1394 case MLX5_IB_MMAP_REGULAR_PAGE:
7c2344c3 1395 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 1396
1397 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1398 return -ENOSYS;
1399
d69e3bcf 1400 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 1401 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1402 return -EINVAL;
1403
6cbac1e4 1404 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 1405 return -EPERM;
1406
1407 /* Don't expose to user-space information it shouldn't have */
1408 if (PAGE_SIZE > 4096)
1409 return -EOPNOTSUPP;
1410
1411 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1412 pfn = (dev->mdev->iseg_base +
1413 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1414 PAGE_SHIFT;
1415 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1416 PAGE_SIZE, vma->vm_page_prot))
1417 return -EAGAIN;
1418
1419 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1420 vma->vm_start,
1421 (unsigned long long)pfn << PAGE_SHIFT);
1422 break;
d69e3bcf 1423
e126ba97
EC		 1424 default:
1425 return -EINVAL;
1426 }
1427
1428 return 0;
1429}
1430
e126ba97
EC		 1431static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1432 struct ib_ucontext *context,
1433 struct ib_udata *udata)
1434{
1435 struct mlx5_ib_alloc_pd_resp resp;
1436 struct mlx5_ib_pd *pd;
1437 int err;
1438
1439 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1440 if (!pd)
1441 return ERR_PTR(-ENOMEM);
1442
9603b61d 1443 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1444 if (err) {
1445 kfree(pd);
1446 return ERR_PTR(err);
1447 }
1448
1449 if (context) {
1450 resp.pdn = pd->pdn;
1451 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1452 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1453 kfree(pd);
1454 return ERR_PTR(-EFAULT);
1455 }
e126ba97
EC		 1456 }
1457
1458 return &pd->ibpd;
1459}
1460
1461static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1462{
1463 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1464 struct mlx5_ib_pd *mpd = to_mpd(pd);
1465
9603b61d 1466 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1467 kfree(mpd);
1468
1469 return 0;
1470}
1471
466fa6d2
MG		 1472enum {
1473 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1474 MATCH_CRITERIA_ENABLE_MISC_BIT,
1475 MATCH_CRITERIA_ENABLE_INNER_BIT
1476};
1477
1478#define HEADER_IS_ZERO(match_criteria, headers) \
1479 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1480 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 1481
466fa6d2 1482static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 1483{
466fa6d2 1484 u8 match_criteria_enable;
038d2ef8 1485
466fa6d2
MG		 1486 match_criteria_enable =
1487 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1488 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1489 match_criteria_enable |=
1490 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1491 MATCH_CRITERIA_ENABLE_MISC_BIT;
1492 match_criteria_enable |=
1493 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1494 MATCH_CRITERIA_ENABLE_INNER_BIT;
1495
1496 return match_criteria_enable;
038d2ef8
MG		 1497}
1498
ca0d4753
MG		 1499static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1500{
1501 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1502 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 1503}
1504
ca0d4753
MG		 1505static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1506{
1507 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1508 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1509 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1510 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1511}
1512
c47ac6ae
MG		 1513#define LAST_ETH_FIELD vlan_tag
1514#define LAST_IB_FIELD sl
ca0d4753 1515#define LAST_IPV4_FIELD tos
466fa6d2 1516#define LAST_IPV6_FIELD traffic_class
c47ac6ae
MG		 1517#define LAST_TCP_UDP_FIELD src_port
1518
1519/* Field is the last supported field */
1520#define FIELDS_NOT_SUPPORTED(filter, field)\
1521 memchr_inv((void *)&filter.field +\
1522 sizeof(filter.field), 0,\
1523 sizeof(filter) -\
1524 offsetof(typeof(filter), field) -\
1525 sizeof(filter.field))
1526
038d2ef8 1527static int parse_flow_attr(u32 *match_c, u32 *match_v,
dd063d0e 1528 const union ib_flow_spec *ib_spec)
038d2ef8
MG		 1529{
1530 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1531 outer_headers);
1532 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1533 outer_headers);
466fa6d2
MG		 1534 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1535 misc_parameters);
1536 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1537 misc_parameters);
1538
038d2ef8
MG		 1539 switch (ib_spec->type) {
1540 case IB_FLOW_SPEC_ETH:
c47ac6ae
MG		 1541 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1542 return -ENOTSUPP;
038d2ef8
MG		 1543
1544 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1545 dmac_47_16),
1546 ib_spec->eth.mask.dst_mac);
1547 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1548 dmac_47_16),
1549 ib_spec->eth.val.dst_mac);
1550
ee3da804
MG		 1551 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1552 smac_47_16),
1553 ib_spec->eth.mask.src_mac);
1554 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1555 smac_47_16),
1556 ib_spec->eth.val.src_mac);
1557
038d2ef8
MG		 1558 if (ib_spec->eth.mask.vlan_tag) {
1559 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1560 vlan_tag, 1);
1561 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1562 vlan_tag, 1);
1563
1564 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1565 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1566 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1567 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1568
1569 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1570 first_cfi,
1571 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1572 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1573 first_cfi,
1574 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1575
1576 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1577 first_prio,
1578 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1579 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1580 first_prio,
1581 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1582 }
1583 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1584 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1585 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1586 ethertype, ntohs(ib_spec->eth.val.ether_type));
1587 break;
1588 case IB_FLOW_SPEC_IPV4:
c47ac6ae
MG		 1589 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1590 return -ENOTSUPP;
038d2ef8
MG		 1591
1592 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1593 ethertype, 0xffff);
1594 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1595 ethertype, ETH_P_IP);
1596
1597 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1598 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1599 &ib_spec->ipv4.mask.src_ip,
1600 sizeof(ib_spec->ipv4.mask.src_ip));
1601 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1602 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1603 &ib_spec->ipv4.val.src_ip,
1604 sizeof(ib_spec->ipv4.val.src_ip));
1605 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1606 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1607 &ib_spec->ipv4.mask.dst_ip,
1608 sizeof(ib_spec->ipv4.mask.dst_ip));
1609 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1610 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1611 &ib_spec->ipv4.val.dst_ip,
1612 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753
MG		 1613
1614 set_tos(outer_headers_c, outer_headers_v,
1615 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1616
1617 set_proto(outer_headers_c, outer_headers_v,
1618 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 1619 break;
026bae0c 1620 case IB_FLOW_SPEC_IPV6:
c47ac6ae
MG		 1621 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1622 return -ENOTSUPP;
026bae0c
MG		 1623
1624 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1625 ethertype, 0xffff);
1626 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1627 ethertype, ETH_P_IPV6);
1628
1629 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1630 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1631 &ib_spec->ipv6.mask.src_ip,
1632 sizeof(ib_spec->ipv6.mask.src_ip));
1633 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1634 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1635 &ib_spec->ipv6.val.src_ip,
1636 sizeof(ib_spec->ipv6.val.src_ip));
1637 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1638 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1639 &ib_spec->ipv6.mask.dst_ip,
1640 sizeof(ib_spec->ipv6.mask.dst_ip));
1641 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1642 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1643 &ib_spec->ipv6.val.dst_ip,
1644 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2
MG		 1645
1646 set_tos(outer_headers_c, outer_headers_v,
1647 ib_spec->ipv6.mask.traffic_class,
1648 ib_spec->ipv6.val.traffic_class);
1649
1650 set_proto(outer_headers_c, outer_headers_v,
1651 ib_spec->ipv6.mask.next_hdr,
1652 ib_spec->ipv6.val.next_hdr);
1653
1654 MLX5_SET(fte_match_set_misc, misc_params_c,
1655 outer_ipv6_flow_label,
1656 ntohl(ib_spec->ipv6.mask.flow_label));
1657 MLX5_SET(fte_match_set_misc, misc_params_v,
1658 outer_ipv6_flow_label,
1659 ntohl(ib_spec->ipv6.val.flow_label));
026bae0c 1660 break;
038d2ef8 1661 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 1662 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1663 LAST_TCP_UDP_FIELD))
1664 return -ENOTSUPP;
038d2ef8
MG		 1665
1666 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1667 0xff);
1668 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1669 IPPROTO_TCP);
1670
1671 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1672 ntohs(ib_spec->tcp_udp.mask.src_port));
1673 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1674 ntohs(ib_spec->tcp_udp.val.src_port));
1675
1676 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1677 ntohs(ib_spec->tcp_udp.mask.dst_port));
1678 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1679 ntohs(ib_spec->tcp_udp.val.dst_port));
1680 break;
1681 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 1682 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1683 LAST_TCP_UDP_FIELD))
1684 return -ENOTSUPP;
038d2ef8
MG		 1685
1686 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1687 0xff);
1688 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1689 IPPROTO_UDP);
1690
1691 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1692 ntohs(ib_spec->tcp_udp.mask.src_port));
1693 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1694 ntohs(ib_spec->tcp_udp.val.src_port));
1695
1696 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1697 ntohs(ib_spec->tcp_udp.mask.dst_port));
1698 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1699 ntohs(ib_spec->tcp_udp.val.dst_port));
1700 break;
1701 default:
1702 return -EINVAL;
1703 }
1704
1705 return 0;
1706}
1707
1708/* If a flow could catch both multicast and unicast packets,
1709 * it won't fall into the multicast flow steering table and this rule
1710 * could steal other multicast packets.
1711 */
1712static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1713{
1714 struct ib_flow_spec_eth *eth_spec;
1715
1716 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1717 ib_attr->size < sizeof(struct ib_flow_attr) +
1718 sizeof(struct ib_flow_spec_eth) ||
1719 ib_attr->num_of_specs < 1)
1720 return false;
1721
1722 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1723 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1724 eth_spec->size != sizeof(*eth_spec))
1725 return false;
1726
1727 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1728 is_multicast_ether_addr(eth_spec->val.dst_mac);
1729}
1730
dd063d0e 1731static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
038d2ef8
MG		 1732{
1733 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1734 bool has_ipv4_spec = false;
1735 bool eth_type_ipv4 = true;
1736 unsigned int spec_index;
1737
1738 /* Validate that ethertype is correct */
1739 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1740 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1741 ib_spec->eth.mask.ether_type) {
1742 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1743 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1744 eth_type_ipv4 = false;
1745 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1746 has_ipv4_spec = true;
1747 }
1748 ib_spec = (void *)ib_spec + ib_spec->size;
1749 }
1750 return !has_ipv4_spec || eth_type_ipv4;
1751}
1752
1753static void put_flow_table(struct mlx5_ib_dev *dev,
1754 struct mlx5_ib_flow_prio *prio, bool ft_added)
1755{
1756 prio->refcount -= !!ft_added;
1757 if (!prio->refcount) {
1758 mlx5_destroy_flow_table(prio->flow_table);
1759 prio->flow_table = NULL;
1760 }
1761}
1762
1763static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1764{
1765 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1766 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1767 struct mlx5_ib_flow_handler,
1768 ibflow);
1769 struct mlx5_ib_flow_handler *iter, *tmp;
1770
1771 mutex_lock(&dev->flow_db.lock);
1772
1773 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 1774 mlx5_del_flow_rules(iter->rule);
cc0e5d42 1775 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 1776 list_del(&iter->list);
1777 kfree(iter);
1778 }
1779
74491de9 1780 mlx5_del_flow_rules(handler->rule);
5497adc6 1781 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 1782 mutex_unlock(&dev->flow_db.lock);
1783
1784 kfree(handler);
1785
1786 return 0;
1787}
1788
35d19011
MG		 1789static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1790{
1791 priority *= 2;
1792 if (!dont_trap)
1793 priority++;
1794 return priority;
1795}
1796
cc0e5d42
MG		 1797enum flow_table_type {
1798 MLX5_IB_FT_RX,
1799 MLX5_IB_FT_TX
1800};
1801
038d2ef8
MG		 1802#define MLX5_FS_MAX_TYPES 10
1803#define MLX5_FS_MAX_ENTRIES 32000UL
1804static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 1805 struct ib_flow_attr *flow_attr,
1806 enum flow_table_type ft_type)
038d2ef8 1807{
35d19011 1808 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 1809 struct mlx5_flow_namespace *ns = NULL;
1810 struct mlx5_ib_flow_prio *prio;
1811 struct mlx5_flow_table *ft;
1812 int num_entries;
1813 int num_groups;
1814 int priority;
1815 int err = 0;
1816
1817 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 1818 if (flow_is_multicast_only(flow_attr) &&
1819 !dont_trap)
038d2ef8
MG		 1820 priority = MLX5_IB_FLOW_MCAST_PRIO;
1821 else
35d19011
MG		 1822 priority = ib_prio_to_core_prio(flow_attr->priority,
1823 dont_trap);
038d2ef8
MG		 1824 ns = mlx5_get_flow_namespace(dev->mdev,
1825 MLX5_FLOW_NAMESPACE_BYPASS);
1826 num_entries = MLX5_FS_MAX_ENTRIES;
1827 num_groups = MLX5_FS_MAX_TYPES;
1828 prio = &dev->flow_db.prios[priority];
1829 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1830 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1831 ns = mlx5_get_flow_namespace(dev->mdev,
1832 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1833 build_leftovers_ft_param(&priority,
1834 &num_entries,
1835 &num_groups);
1836 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 1837 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1838 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1839 allow_sniffer_and_nic_rx_shared_tir))
1840 return ERR_PTR(-ENOTSUPP);
1841
1842 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1843 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1844 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1845
1846 prio = &dev->flow_db.sniffer[ft_type];
1847 priority = 0;
1848 num_entries = 1;
1849 num_groups = 1;
038d2ef8
MG		 1850 }
1851
1852 if (!ns)
1853 return ERR_PTR(-ENOTSUPP);
1854
1855 ft = prio->flow_table;
1856 if (!ft) {
1857 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1858 num_entries,
d63cd286
MG		 1859 num_groups,
1860 0);
038d2ef8
MG		 1861
1862 if (!IS_ERR(ft)) {
1863 prio->refcount = 0;
1864 prio->flow_table = ft;
1865 } else {
1866 err = PTR_ERR(ft);
1867 }
1868 }
1869
1870 return err ? ERR_PTR(err) : prio;
1871}
1872
1873static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1874 struct mlx5_ib_flow_prio *ft_prio,
dd063d0e 1875 const struct ib_flow_attr *flow_attr,
038d2ef8
MG		 1876 struct mlx5_flow_destination *dst)
1877{
1878 struct mlx5_flow_table *ft = ft_prio->flow_table;
1879 struct mlx5_ib_flow_handler *handler;
c5bb1730 1880 struct mlx5_flow_spec *spec;
dd063d0e 1881 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 1882 unsigned int spec_index;
35d19011 1883 u32 action;
038d2ef8
MG		 1884 int err = 0;
1885
1886 if (!is_valid_attr(flow_attr))
1887 return ERR_PTR(-EINVAL);
1888
c5bb1730 1889 spec = mlx5_vzalloc(sizeof(*spec));
038d2ef8 1890 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 1891 if (!handler || !spec) {
038d2ef8
MG		 1892 err = -ENOMEM;
1893 goto free;
1894 }
1895
1896 INIT_LIST_HEAD(&handler->list);
1897
1898 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
c5bb1730
MG		 1899 err = parse_flow_attr(spec->match_criteria,
1900 spec->match_value, ib_flow);
038d2ef8
MG		 1901 if (err < 0)
1902 goto free;
1903
1904 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1905 }
1906
466fa6d2 1907 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
35d19011
MG		 1908 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1909 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
74491de9 1910 handler->rule = mlx5_add_flow_rules(ft, spec,
35d19011 1911 action,
038d2ef8 1912 MLX5_FS_DEFAULT_FLOW_TAG,
74491de9 1913 dst, 1);
038d2ef8
MG		 1914
1915 if (IS_ERR(handler->rule)) {
1916 err = PTR_ERR(handler->rule);
1917 goto free;
1918 }
1919
d9d4980a 1920 ft_prio->refcount++;
5497adc6 1921 handler->prio = ft_prio;
038d2ef8
MG		 1922
1923 ft_prio->flow_table = ft;
1924free:
1925 if (err)
1926 kfree(handler);
c5bb1730 1927 kvfree(spec);
038d2ef8
MG		 1928 return err ? ERR_PTR(err) : handler;
1929}
1930
35d19011
MG		 1931static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1932 struct mlx5_ib_flow_prio *ft_prio,
1933 struct ib_flow_attr *flow_attr,
1934 struct mlx5_flow_destination *dst)
1935{
1936 struct mlx5_ib_flow_handler *handler_dst = NULL;
1937 struct mlx5_ib_flow_handler *handler = NULL;
1938
1939 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1940 if (!IS_ERR(handler)) {
1941 handler_dst = create_flow_rule(dev, ft_prio,
1942 flow_attr, dst);
1943 if (IS_ERR(handler_dst)) {
74491de9 1944 mlx5_del_flow_rules(handler->rule);
d9d4980a 1945 ft_prio->refcount--;
35d19011
MG		 1946 kfree(handler);
1947 handler = handler_dst;
1948 } else {
1949 list_add(&handler_dst->list, &handler->list);
1950 }
1951 }
1952
1953 return handler;
1954}
038d2ef8
MG		 1955enum {
1956 LEFTOVERS_MC,
1957 LEFTOVERS_UC,
1958};
1959
1960static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1961 struct mlx5_ib_flow_prio *ft_prio,
1962 struct ib_flow_attr *flow_attr,
1963 struct mlx5_flow_destination *dst)
1964{
1965 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1966 struct mlx5_ib_flow_handler *handler = NULL;
1967
1968 static struct {
1969 struct ib_flow_attr flow_attr;
1970 struct ib_flow_spec_eth eth_flow;
1971 } leftovers_specs[] = {
1972 [LEFTOVERS_MC] = {
1973 .flow_attr = {
1974 .num_of_specs = 1,
1975 .size = sizeof(leftovers_specs[0])
1976 },
1977 .eth_flow = {
1978 .type = IB_FLOW_SPEC_ETH,
1979 .size = sizeof(struct ib_flow_spec_eth),
1980 .mask = {.dst_mac = {0x1} },
1981 .val = {.dst_mac = {0x1} }
1982 }
1983 },
1984 [LEFTOVERS_UC] = {
1985 .flow_attr = {
1986 .num_of_specs = 1,
1987 .size = sizeof(leftovers_specs[0])
1988 },
1989 .eth_flow = {
1990 .type = IB_FLOW_SPEC_ETH,
1991 .size = sizeof(struct ib_flow_spec_eth),
1992 .mask = {.dst_mac = {0x1} },
1993 .val = {.dst_mac = {} }
1994 }
1995 }
1996 };
1997
1998 handler = create_flow_rule(dev, ft_prio,
1999 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2000 dst);
2001 if (!IS_ERR(handler) &&
2002 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2003 handler_ucast = create_flow_rule(dev, ft_prio,
2004 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2005 dst);
2006 if (IS_ERR(handler_ucast)) {
74491de9 2007 mlx5_del_flow_rules(handler->rule);
d9d4980a 2008 ft_prio->refcount--;
038d2ef8
MG		 2009 kfree(handler);
2010 handler = handler_ucast;
2011 } else {
2012 list_add(&handler_ucast->list, &handler->list);
2013 }
2014 }
2015
2016 return handler;
2017}
2018
cc0e5d42
MG		 2019static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2020 struct mlx5_ib_flow_prio *ft_rx,
2021 struct mlx5_ib_flow_prio *ft_tx,
2022 struct mlx5_flow_destination *dst)
2023{
2024 struct mlx5_ib_flow_handler *handler_rx;
2025 struct mlx5_ib_flow_handler *handler_tx;
2026 int err;
2027 static const struct ib_flow_attr flow_attr = {
2028 .num_of_specs = 0,
2029 .size = sizeof(flow_attr)
2030 };
2031
2032 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2033 if (IS_ERR(handler_rx)) {
2034 err = PTR_ERR(handler_rx);
2035 goto err;
2036 }
2037
2038 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2039 if (IS_ERR(handler_tx)) {
2040 err = PTR_ERR(handler_tx);
2041 goto err_tx;
2042 }
2043
2044 list_add(&handler_tx->list, &handler_rx->list);
2045
2046 return handler_rx;
2047
2048err_tx:
74491de9 2049 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2050 ft_rx->refcount--;
2051 kfree(handler_rx);
2052err:
2053 return ERR_PTR(err);
2054}
2055
038d2ef8
MG		 2056static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2057 struct ib_flow_attr *flow_attr,
2058 int domain)
2059{
2060 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2061 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2062 struct mlx5_ib_flow_handler *handler = NULL;
2063 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2064 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2065 struct mlx5_ib_flow_prio *ft_prio;
2066 int err;
2067
2068 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2069 return ERR_PTR(-ENOSPC);
2070
2071 if (domain != IB_FLOW_DOMAIN_USER ||
2072 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
35d19011 2073 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2074 return ERR_PTR(-EINVAL);
2075
2076 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2077 if (!dst)
2078 return ERR_PTR(-ENOMEM);
2079
2080 mutex_lock(&dev->flow_db.lock);
2081
cc0e5d42 2082 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2083 if (IS_ERR(ft_prio)) {
2084 err = PTR_ERR(ft_prio);
2085 goto unlock;
2086 }
cc0e5d42
MG		 2087 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2088 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2089 if (IS_ERR(ft_prio_tx)) {
2090 err = PTR_ERR(ft_prio_tx);
2091 ft_prio_tx = NULL;
2092 goto destroy_ft;
2093 }
2094 }
038d2ef8
MG		 2095
2096 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2097 if (mqp->flags & MLX5_IB_QP_RSS)
2098 dst->tir_num = mqp->rss_qp.tirn;
2099 else
2100 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2101
2102 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2103 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2104 handler = create_dont_trap_rule(dev, ft_prio,
2105 flow_attr, dst);
2106 } else {
2107 handler = create_flow_rule(dev, ft_prio, flow_attr,
2108 dst);
2109 }
038d2ef8
MG		 2110 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2111 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2112 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2113 dst);
cc0e5d42
MG		 2114 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2115 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2116 } else {
2117 err = -EINVAL;
2118 goto destroy_ft;
2119 }
2120
2121 if (IS_ERR(handler)) {
2122 err = PTR_ERR(handler);
2123 handler = NULL;
2124 goto destroy_ft;
2125 }
2126
038d2ef8
MG		 2127 mutex_unlock(&dev->flow_db.lock);
2128 kfree(dst);
2129
2130 return &handler->ibflow;
2131
2132destroy_ft:
2133 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2134 if (ft_prio_tx)
2135 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2136unlock:
2137 mutex_unlock(&dev->flow_db.lock);
2138 kfree(dst);
2139 kfree(handler);
2140 return ERR_PTR(err);
2141}
2142
e126ba97
EC		 2143static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2144{
2145 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2146 int err;
2147
9603b61d 2148 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2149 if (err)
2150 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2151 ibqp->qp_num, gid->raw);
2152
2153 return err;
2154}
2155
2156static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2157{
2158 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2159 int err;
2160
9603b61d 2161 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2162 if (err)
2163 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2164 ibqp->qp_num, gid->raw);
2165
2166 return err;
2167}
2168
2169static int init_node_data(struct mlx5_ib_dev *dev)
2170{
1b5daf11 2171 int err;
e126ba97 2172
1b5daf11 2173 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2174 if (err)
1b5daf11 2175 return err;
e126ba97 2176
1b5daf11 2177 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2178
1b5daf11 2179 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2180}
2181
2182static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2183 char *buf)
2184{
2185 struct mlx5_ib_dev *dev =
2186 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2187
9603b61d 2188 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2189}
2190
2191static ssize_t show_reg_pages(struct device *device,
2192 struct device_attribute *attr, char *buf)
2193{
2194 struct mlx5_ib_dev *dev =
2195 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2196
6aec21f6 2197 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 2198}
2199
2200static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2201 char *buf)
2202{
2203 struct mlx5_ib_dev *dev =
2204 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2205 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 2206}
2207
e126ba97
EC		 2208static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2209 char *buf)
2210{
2211 struct mlx5_ib_dev *dev =
2212 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 2213 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 2214}
2215
2216static ssize_t show_board(struct device *device, struct device_attribute *attr,
2217 char *buf)
2218{
2219 struct mlx5_ib_dev *dev =
2220 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2221 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 2222 dev->mdev->board_id);
e126ba97
EC		 2223}
2224
2225static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 2226static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2227static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2228static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2229static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2230
2231static struct device_attribute *mlx5_class_attributes[] = {
2232 &dev_attr_hw_rev,
e126ba97
EC		 2233 &dev_attr_hca_type,
2234 &dev_attr_board_id,
2235 &dev_attr_fw_pages,
2236 &dev_attr_reg_pages,
2237};
2238
7722f47e
HE		 2239static void pkey_change_handler(struct work_struct *work)
2240{
2241 struct mlx5_ib_port_resources *ports =
2242 container_of(work, struct mlx5_ib_port_resources,
2243 pkey_change_work);
2244
2245 mutex_lock(&ports->devr->mutex);
2246 mlx5_ib_gsi_pkey_change(ports->gsi);
2247 mutex_unlock(&ports->devr->mutex);
2248}
2249
89ea94a7
MG		 2250static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2251{
2252 struct mlx5_ib_qp *mqp;
2253 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2254 struct mlx5_core_cq *mcq;
2255 struct list_head cq_armed_list;
2256 unsigned long flags_qp;
2257 unsigned long flags_cq;
2258 unsigned long flags;
2259
2260 INIT_LIST_HEAD(&cq_armed_list);
2261
2262 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2263 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2264 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2265 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2266 if (mqp->sq.tail != mqp->sq.head) {
2267 send_mcq = to_mcq(mqp->ibqp.send_cq);
2268 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2269 if (send_mcq->mcq.comp &&
2270 mqp->ibqp.send_cq->comp_handler) {
2271 if (!send_mcq->mcq.reset_notify_added) {
2272 send_mcq->mcq.reset_notify_added = 1;
2273 list_add_tail(&send_mcq->mcq.reset_notify,
2274 &cq_armed_list);
2275 }
2276 }
2277 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2278 }
2279 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2280 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2281 /* no handling is needed for SRQ */
2282 if (!mqp->ibqp.srq) {
2283 if (mqp->rq.tail != mqp->rq.head) {
2284 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2285 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2286 if (recv_mcq->mcq.comp &&
2287 mqp->ibqp.recv_cq->comp_handler) {
2288 if (!recv_mcq->mcq.reset_notify_added) {
2289 recv_mcq->mcq.reset_notify_added = 1;
2290 list_add_tail(&recv_mcq->mcq.reset_notify,
2291 &cq_armed_list);
2292 }
2293 }
2294 spin_unlock_irqrestore(&recv_mcq->lock,
2295 flags_cq);
2296 }
2297 }
2298 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2299 }
2300 /*At that point all inflight post send were put to be executed as of we
2301 * lock/unlock above locks Now need to arm all involved CQs.
2302 */
2303 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2304 mcq->comp(mcq);
2305 }
2306 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2307}
2308
9603b61d 2309static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 2310 enum mlx5_dev_event event, unsigned long param)
e126ba97 2311{
9603b61d 2312 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 2313 struct ib_event ibev;
9603b61d 2314
e126ba97
EC		 2315 u8 port = 0;
2316
2317 switch (event) {
2318 case MLX5_DEV_EVENT_SYS_ERROR:
2319 ibdev->ib_active = false;
2320 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 2321 mlx5_ib_handle_internal_error(ibdev);
e126ba97
EC		 2322 break;
2323
2324 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 2325 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 2326 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 2327 port = (u8)param;
5ec8c83e
AH		 2328
2329 /* In RoCE, port up/down events are handled in
2330 * mlx5_netdev_event().
2331 */
2332 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2333 IB_LINK_LAYER_ETHERNET)
2334 return;
2335
2336 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2337 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 2338 break;
2339
e126ba97
EC		 2340 case MLX5_DEV_EVENT_LID_CHANGE:
2341 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 2342 port = (u8)param;
e126ba97
EC		 2343 break;
2344
2345 case MLX5_DEV_EVENT_PKEY_CHANGE:
2346 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 2347 port = (u8)param;
7722f47e
HE		 2348
2349 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 2350 break;
2351
2352 case MLX5_DEV_EVENT_GUID_CHANGE:
2353 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 2354 port = (u8)param;
e126ba97
EC		 2355 break;
2356
2357 case MLX5_DEV_EVENT_CLIENT_REREG:
2358 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 2359 port = (u8)param;
e126ba97 2360 break;
bdc37924
SM		 2361 default:
2362 return;
e126ba97
EC		 2363 }
2364
2365 ibev.device = &ibdev->ib_dev;
2366 ibev.element.port_num = port;
2367
a0c84c32
EC		 2368 if (port < 1 || port > ibdev->num_ports) {
2369 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2370 return;
2371 }
2372
e126ba97
EC		 2373 if (ibdev->ib_active)
2374 ib_dispatch_event(&ibev);
2375}
2376
2377static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2378{
2379 int port;
2380
938fe83c 2381 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 2382 mlx5_query_ext_port_caps(dev, port);
2383}
2384
2385static int get_port_caps(struct mlx5_ib_dev *dev)
2386{
2387 struct ib_device_attr *dprops = NULL;
2388 struct ib_port_attr *pprops = NULL;
f614fc15 2389 int err = -ENOMEM;
e126ba97 2390 int port;
2528e33e 2391 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 2392
2393 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2394 if (!pprops)
2395 goto out;
2396
2397 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2398 if (!dprops)
2399 goto out;
2400
2528e33e 2401 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 2402 if (err) {
2403 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2404 goto out;
2405 }
2406
938fe83c 2407 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 2408 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2409 if (err) {
938fe83c
SM		 2410 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2411 port, err);
e126ba97
EC		 2412 break;
2413 }
938fe83c
SM		 2414 dev->mdev->port_caps[port - 1].pkey_table_len =
2415 dprops->max_pkeys;
2416 dev->mdev->port_caps[port - 1].gid_table_len =
2417 pprops->gid_tbl_len;
e126ba97
EC		 2418 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2419 dprops->max_pkeys, pprops->gid_tbl_len);
2420 }
2421
2422out:
2423 kfree(pprops);
2424 kfree(dprops);
2425
2426 return err;
2427}
2428
2429static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2430{
2431 int err;
2432
2433 err = mlx5_mr_cache_cleanup(dev);
2434 if (err)
2435 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2436
2437 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 2438 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 2439 ib_dealloc_pd(dev->umrc.pd);
2440}
2441
2442enum {
2443 MAX_UMR_WR = 128,
2444};
2445
2446static int create_umr_res(struct mlx5_ib_dev *dev)
2447{
2448 struct ib_qp_init_attr *init_attr = NULL;
2449 struct ib_qp_attr *attr = NULL;
2450 struct ib_pd *pd;
2451 struct ib_cq *cq;
2452 struct ib_qp *qp;
e126ba97
EC		 2453 int ret;
2454
2455 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2456 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2457 if (!attr || !init_attr) {
2458 ret = -ENOMEM;
2459 goto error_0;
2460 }
2461
ed082d36 2462 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 2463 if (IS_ERR(pd)) {
2464 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2465 ret = PTR_ERR(pd);
2466 goto error_0;
2467 }
2468
add08d76 2469 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 2470 if (IS_ERR(cq)) {
2471 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2472 ret = PTR_ERR(cq);
2473 goto error_2;
2474 }
e126ba97
EC		 2475
2476 init_attr->send_cq = cq;
2477 init_attr->recv_cq = cq;
2478 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2479 init_attr->cap.max_send_wr = MAX_UMR_WR;
2480 init_attr->cap.max_send_sge = 1;
2481 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2482 init_attr->port_num = 1;
2483 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2484 if (IS_ERR(qp)) {
2485 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2486 ret = PTR_ERR(qp);
2487 goto error_3;
2488 }
2489 qp->device = &dev->ib_dev;
2490 qp->real_qp = qp;
2491 qp->uobject = NULL;
2492 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2493
2494 attr->qp_state = IB_QPS_INIT;
2495 attr->port_num = 1;
2496 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2497 IB_QP_PORT, NULL);
2498 if (ret) {
2499 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2500 goto error_4;
2501 }
2502
2503 memset(attr, 0, sizeof(*attr));
2504 attr->qp_state = IB_QPS_RTR;
2505 attr->path_mtu = IB_MTU_256;
2506
2507 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2508 if (ret) {
2509 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2510 goto error_4;
2511 }
2512
2513 memset(attr, 0, sizeof(*attr));
2514 attr->qp_state = IB_QPS_RTS;
2515 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2516 if (ret) {
2517 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2518 goto error_4;
2519 }
2520
2521 dev->umrc.qp = qp;
2522 dev->umrc.cq = cq;
e126ba97
EC		 2523 dev->umrc.pd = pd;
2524
2525 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2526 ret = mlx5_mr_cache_init(dev);
2527 if (ret) {
2528 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2529 goto error_4;
2530 }
2531
2532 kfree(attr);
2533 kfree(init_attr);
2534
2535 return 0;
2536
2537error_4:
2538 mlx5_ib_destroy_qp(qp);
2539
2540error_3:
add08d76 2541 ib_free_cq(cq);
e126ba97
EC		 2542
2543error_2:
e126ba97
EC		 2544 ib_dealloc_pd(pd);
2545
2546error_0:
2547 kfree(attr);
2548 kfree(init_attr);
2549 return ret;
2550}
2551
2552static int create_dev_resources(struct mlx5_ib_resources *devr)
2553{
2554 struct ib_srq_init_attr attr;
2555 struct mlx5_ib_dev *dev;
bcf4c1ea 2556 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 2557 int port;
e126ba97
EC		 2558 int ret = 0;
2559
2560 dev = container_of(devr, struct mlx5_ib_dev, devr);
2561
d16e91da
HE		 2562 mutex_init(&devr->mutex);
2563
e126ba97
EC		 2564 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2565 if (IS_ERR(devr->p0)) {
2566 ret = PTR_ERR(devr->p0);
2567 goto error0;
2568 }
2569 devr->p0->device = &dev->ib_dev;
2570 devr->p0->uobject = NULL;
2571 atomic_set(&devr->p0->usecnt, 0);
2572
bcf4c1ea 2573 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 2574 if (IS_ERR(devr->c0)) {
2575 ret = PTR_ERR(devr->c0);
2576 goto error1;
2577 }
2578 devr->c0->device = &dev->ib_dev;
2579 devr->c0->uobject = NULL;
2580 devr->c0->comp_handler = NULL;
2581 devr->c0->event_handler = NULL;
2582 devr->c0->cq_context = NULL;
2583 atomic_set(&devr->c0->usecnt, 0);
2584
2585 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2586 if (IS_ERR(devr->x0)) {
2587 ret = PTR_ERR(devr->x0);
2588 goto error2;
2589 }
2590 devr->x0->device = &dev->ib_dev;
2591 devr->x0->inode = NULL;
2592 atomic_set(&devr->x0->usecnt, 0);
2593 mutex_init(&devr->x0->tgt_qp_mutex);
2594 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2595
2596 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2597 if (IS_ERR(devr->x1)) {
2598 ret = PTR_ERR(devr->x1);
2599 goto error3;
2600 }
2601 devr->x1->device = &dev->ib_dev;
2602 devr->x1->inode = NULL;
2603 atomic_set(&devr->x1->usecnt, 0);
2604 mutex_init(&devr->x1->tgt_qp_mutex);
2605 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2606
2607 memset(&attr, 0, sizeof(attr));
2608 attr.attr.max_sge = 1;
2609 attr.attr.max_wr = 1;
2610 attr.srq_type = IB_SRQT_XRC;
2611 attr.ext.xrc.cq = devr->c0;
2612 attr.ext.xrc.xrcd = devr->x0;
2613
2614 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2615 if (IS_ERR(devr->s0)) {
2616 ret = PTR_ERR(devr->s0);
2617 goto error4;
2618 }
2619 devr->s0->device = &dev->ib_dev;
2620 devr->s0->pd = devr->p0;
2621 devr->s0->uobject = NULL;
2622 devr->s0->event_handler = NULL;
2623 devr->s0->srq_context = NULL;
2624 devr->s0->srq_type = IB_SRQT_XRC;
2625 devr->s0->ext.xrc.xrcd = devr->x0;
2626 devr->s0->ext.xrc.cq = devr->c0;
2627 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2628 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2629 atomic_inc(&devr->p0->usecnt);
2630 atomic_set(&devr->s0->usecnt, 0);
2631
4aa17b28
HA		 2632 memset(&attr, 0, sizeof(attr));
2633 attr.attr.max_sge = 1;
2634 attr.attr.max_wr = 1;
2635 attr.srq_type = IB_SRQT_BASIC;
2636 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2637 if (IS_ERR(devr->s1)) {
2638 ret = PTR_ERR(devr->s1);
2639 goto error5;
2640 }
2641 devr->s1->device = &dev->ib_dev;
2642 devr->s1->pd = devr->p0;
2643 devr->s1->uobject = NULL;
2644 devr->s1->event_handler = NULL;
2645 devr->s1->srq_context = NULL;
2646 devr->s1->srq_type = IB_SRQT_BASIC;
2647 devr->s1->ext.xrc.cq = devr->c0;
2648 atomic_inc(&devr->p0->usecnt);
2649 atomic_set(&devr->s0->usecnt, 0);
2650
7722f47e
HE		 2651 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2652 INIT_WORK(&devr->ports[port].pkey_change_work,
2653 pkey_change_handler);
2654 devr->ports[port].devr = devr;
2655 }
2656
e126ba97
EC		 2657 return 0;
2658
4aa17b28
HA		 2659error5:
2660 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 2661error4:
2662 mlx5_ib_dealloc_xrcd(devr->x1);
2663error3:
2664 mlx5_ib_dealloc_xrcd(devr->x0);
2665error2:
2666 mlx5_ib_destroy_cq(devr->c0);
2667error1:
2668 mlx5_ib_dealloc_pd(devr->p0);
2669error0:
2670 return ret;
2671}
2672
2673static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2674{
7722f47e
HE		 2675 struct mlx5_ib_dev *dev =
2676 container_of(devr, struct mlx5_ib_dev, devr);
2677 int port;
2678
4aa17b28 2679 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 2680 mlx5_ib_destroy_srq(devr->s0);
2681 mlx5_ib_dealloc_xrcd(devr->x0);
2682 mlx5_ib_dealloc_xrcd(devr->x1);
2683 mlx5_ib_destroy_cq(devr->c0);
2684 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 2685
2686 /* Make sure no change P_Key work items are still executing */
2687 for (port = 0; port < dev->num_ports; ++port)
2688 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 2689}
2690
e53505a8
AS		 2691static u32 get_core_cap_flags(struct ib_device *ibdev)
2692{
2693 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2694 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2695 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2696 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2697 u32 ret = 0;
2698
2699 if (ll == IB_LINK_LAYER_INFINIBAND)
2700 return RDMA_CORE_PORT_IBA_IB;
2701
2702 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2703 return 0;
2704
2705 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2706 return 0;
2707
2708 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2709 ret |= RDMA_CORE_PORT_IBA_ROCE;
2710
2711 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2712 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2713
2714 return ret;
2715}
2716
7738613e
IW		 2717static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2718 struct ib_port_immutable *immutable)
2719{
2720 struct ib_port_attr attr;
2721 int err;
2722
2723 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2724 if (err)
2725 return err;
2726
2727 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2728 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 2729 immutable->core_cap_flags = get_core_cap_flags(ibdev);
337877a4 2730 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 2731
2732 return 0;
2733}
2734
c7342823
IW		 2735static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2736 size_t str_len)
2737{
2738 struct mlx5_ib_dev *dev =
2739 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2740 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2741 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2742}
2743
9ef9c640
AH		 2744static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2745{
2746 struct mlx5_core_dev *mdev = dev->mdev;
2747 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2748 MLX5_FLOW_NAMESPACE_LAG);
2749 struct mlx5_flow_table *ft;
2750 int err;
2751
2752 if (!ns || !mlx5_lag_is_active(mdev))
2753 return 0;
2754
2755 err = mlx5_cmd_create_vport_lag(mdev);
2756 if (err)
2757 return err;
2758
2759 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2760 if (IS_ERR(ft)) {
2761 err = PTR_ERR(ft);
2762 goto err_destroy_vport_lag;
2763 }
2764
2765 dev->flow_db.lag_demux_ft = ft;
2766 return 0;
2767
2768err_destroy_vport_lag:
2769 mlx5_cmd_destroy_vport_lag(mdev);
2770 return err;
2771}
2772
2773static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2774{
2775 struct mlx5_core_dev *mdev = dev->mdev;
2776
2777 if (dev->flow_db.lag_demux_ft) {
2778 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2779 dev->flow_db.lag_demux_ft = NULL;
2780
2781 mlx5_cmd_destroy_vport_lag(mdev);
2782 }
2783}
2784
5ec8c83e
AH		 2785static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2786{
2787 if (dev->roce.nb.notifier_call) {
2788 unregister_netdevice_notifier(&dev->roce.nb);
2789 dev->roce.nb.notifier_call = NULL;
2790 }
2791}
2792
fc24fc5e
AS		 2793static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2794{
e53505a8
AS		 2795 int err;
2796
fc24fc5e 2797 dev->roce.nb.notifier_call = mlx5_netdev_event;
e53505a8 2798 err = register_netdevice_notifier(&dev->roce.nb);
5ec8c83e
AH		 2799 if (err) {
2800 dev->roce.nb.notifier_call = NULL;
e53505a8 2801 return err;
5ec8c83e 2802 }
e53505a8
AS		 2803
2804 err = mlx5_nic_vport_enable_roce(dev->mdev);
2805 if (err)
2806 goto err_unregister_netdevice_notifier;
2807
9ef9c640
AH		 2808 err = mlx5_roce_lag_init(dev);
2809 if (err)
2810 goto err_disable_roce;
2811
e53505a8
AS		 2812 return 0;
2813
9ef9c640
AH		 2814err_disable_roce:
2815 mlx5_nic_vport_disable_roce(dev->mdev);
2816
e53505a8 2817err_unregister_netdevice_notifier:
5ec8c83e 2818 mlx5_remove_roce_notifier(dev);
e53505a8 2819 return err;
fc24fc5e
AS		 2820}
2821
2822static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2823{
9ef9c640 2824 mlx5_roce_lag_cleanup(dev);
e53505a8 2825 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 2826}
2827
0837e86a
MB		 2828static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2829{
2830 unsigned int i;
2831
2832 for (i = 0; i < dev->num_ports; i++)
2833 mlx5_core_dealloc_q_counter(dev->mdev,
2834 dev->port[i].q_cnt_id);
2835}
2836
2837static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2838{
2839 int i;
2840 int ret;
2841
2842 for (i = 0; i < dev->num_ports; i++) {
2843 ret = mlx5_core_alloc_q_counter(dev->mdev,
2844 &dev->port[i].q_cnt_id);
2845 if (ret) {
2846 mlx5_ib_warn(dev,
2847 "couldn't allocate queue counter for port %d, err %d\n",
2848 i + 1, ret);
2849 goto dealloc_counters;
2850 }
2851 }
2852
2853 return 0;
2854
2855dealloc_counters:
2856 while (--i >= 0)
2857 mlx5_core_dealloc_q_counter(dev->mdev,
2858 dev->port[i].q_cnt_id);
2859
2860 return ret;
2861}
2862
61961500 2863static const char * const names[] = {
0ad17a8f
MB		 2864 "rx_write_requests",
2865 "rx_read_requests",
2866 "rx_atomic_requests",
2867 "out_of_buffer",
2868 "out_of_sequence",
2869 "duplicate_request",
2870 "rnr_nak_retry_err",
2871 "packet_seq_err",
2872 "implied_nak_seq_err",
2873 "local_ack_timeout_err",
2874};
2875
2876static const size_t stats_offsets[] = {
2877 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2878 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2879 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2880 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2881 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2882 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2883 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2884 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2885 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2886 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2887};
2888
2889static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2890 u8 port_num)
2891{
2892 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2893
2894 /* We support only per port stats */
2895 if (port_num == 0)
2896 return NULL;
2897
2898 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2899 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2900}
2901
2902static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2903 struct rdma_hw_stats *stats,
2904 u8 port, int index)
2905{
2906 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2907 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2908 void *out;
2909 __be32 val;
2910 int ret;
2911 int i;
2912
2913 if (!port || !stats)
2914 return -ENOSYS;
2915
2916 out = mlx5_vzalloc(outlen);
2917 if (!out)
2918 return -ENOMEM;
2919
2920 ret = mlx5_core_query_q_counter(dev->mdev,
2921 dev->port[port - 1].q_cnt_id, 0,
2922 out, outlen);
2923 if (ret)
2924 goto free;
2925
2926 for (i = 0; i < ARRAY_SIZE(names); i++) {
2927 val = *(__be32 *)(out + stats_offsets[i]);
2928 stats->value[i] = (u64)be32_to_cpu(val);
2929 }
2930free:
2931 kvfree(out);
2932 return ARRAY_SIZE(names);
2933}
2934
9603b61d 2935static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 2936{
e126ba97 2937 struct mlx5_ib_dev *dev;
ebd61f68
AS		 2938 enum rdma_link_layer ll;
2939 int port_type_cap;
4babcf97 2940 const char *name;
e126ba97
EC		 2941 int err;
2942 int i;
2943
ebd61f68
AS		 2944 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2945 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2946
e53505a8 2947 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
647241ea
MD		 2948 return NULL;
2949
e126ba97
EC		 2950 printk_once(KERN_INFO "%s", mlx5_version);
2951
2952 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2953 if (!dev)
9603b61d 2954 return NULL;
e126ba97 2955
9603b61d 2956 dev->mdev = mdev;
e126ba97 2957
0837e86a
MB		 2958 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2959 GFP_KERNEL);
2960 if (!dev->port)
2961 goto err_dealloc;
2962
fc24fc5e 2963 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 2964 err = get_port_caps(dev);
2965 if (err)
0837e86a 2966 goto err_free_port;
e126ba97 2967
1b5daf11
MD		 2968 if (mlx5_use_mad_ifc(dev))
2969 get_ext_port_caps(dev);
e126ba97 2970
e126ba97
EC		 2971 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2972
4babcf97
AH		 2973 if (!mlx5_lag_is_active(mdev))
2974 name = "mlx5_%d";
2975 else
2976 name = "mlx5_bond_%d";
2977
2978 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 2979 dev->ib_dev.owner = THIS_MODULE;
2980 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 2981 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 2982 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 2983 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 2984 dev->ib_dev.num_comp_vectors =
2985 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 2986 dev->ib_dev.dma_device = &mdev->pdev->dev;
2987
2988 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2989 dev->ib_dev.uverbs_cmd_mask =
2990 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2991 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2992 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2993 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2994 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2995 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 2996 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 2997 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2998 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2999 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3000 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3001 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3002 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3003 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3004 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3005 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3006 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3007 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3008 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3009 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3010 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3011 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3012 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3013 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 3014 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 3015 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3016 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3017 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
e126ba97
EC		 3018
3019 dev->ib_dev.query_device = mlx5_ib_query_device;
3020 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 3021 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 3022 if (ll == IB_LINK_LAYER_ETHERNET)
3023 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 3024 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 3025 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3026 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 3027 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3028 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3029 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3030 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3031 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3032 dev->ib_dev.mmap = mlx5_ib_mmap;
3033 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3034 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3035 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3036 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3037 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3038 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3039 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3040 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3041 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3042 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3043 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3044 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3045 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3046 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3047 dev->ib_dev.post_send = mlx5_ib_post_send;
3048 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3049 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3050 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3051 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3052 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3053 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3054 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3055 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3056 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 3057 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 3058 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3059 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3060 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3061 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 3062 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 3063 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 3064 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 3065 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 3066 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
eff901d3
EC		 3067 if (mlx5_core_is_pf(mdev)) {
3068 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3069 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3070 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3071 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3072 }
e126ba97 3073
7c2344c3
MG		 3074 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3075
938fe83c 3076 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 3077
d2370e0a
MB		 3078 if (MLX5_CAP_GEN(mdev, imaicl)) {
3079 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3080 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3081 dev->ib_dev.uverbs_cmd_mask |=
3082 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3083 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3084 }
3085
0ad17a8f
MB		 3086 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3087 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3088 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3089 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3090 }
3091
938fe83c 3092 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 3093 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3094 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3095 dev->ib_dev.uverbs_cmd_mask |=
3096 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3097 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3098 }
3099
048ccca8 3100 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
038d2ef8
MG		 3101 IB_LINK_LAYER_ETHERNET) {
3102 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3103 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
79b20a6c
YH		 3104 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3105 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3106 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
c5f90929
YH		 3107 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3108 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
038d2ef8
MG		 3109 dev->ib_dev.uverbs_ex_cmd_mask |=
3110 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
79b20a6c
YH		 3111 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3112 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3113 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
c5f90929
YH		 3114 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3115 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3116 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
038d2ef8 3117 }
e126ba97
EC		 3118 err = init_node_data(dev);
3119 if (err)
233d05d2 3120 goto err_dealloc;
e126ba97 3121
038d2ef8 3122 mutex_init(&dev->flow_db.lock);
e126ba97 3123 mutex_init(&dev->cap_mask_mutex);
89ea94a7
MG		 3124 INIT_LIST_HEAD(&dev->qp_list);
3125 spin_lock_init(&dev->reset_flow_resource_lock);
e126ba97 3126
fc24fc5e
AS		 3127 if (ll == IB_LINK_LAYER_ETHERNET) {
3128 err = mlx5_enable_roce(dev);
3129 if (err)
3130 goto err_dealloc;
3131 }
3132
e126ba97
EC		 3133 err = create_dev_resources(&dev->devr);
3134 if (err)
fc24fc5e 3135 goto err_disable_roce;
e126ba97 3136
6aec21f6 3137 err = mlx5_ib_odp_init_one(dev);
281d1a92 3138 if (err)
e126ba97
EC		 3139 goto err_rsrc;
3140
0837e86a 3141 err = mlx5_ib_alloc_q_counters(dev);
6aec21f6
HE		 3142 if (err)
3143 goto err_odp;
3144
0837e86a
MB		 3145 err = ib_register_device(&dev->ib_dev, NULL);
3146 if (err)
3147 goto err_q_cnt;
3148
e126ba97
EC		 3149 err = create_umr_res(dev);
3150 if (err)
3151 goto err_dev;
3152
3153 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 3154 err = device_create_file(&dev->ib_dev.dev,
3155 mlx5_class_attributes[i]);
3156 if (err)
e126ba97
EC		 3157 goto err_umrc;
3158 }
3159
3160 dev->ib_active = true;
3161
9603b61d 3162 return dev;
e126ba97
EC		 3163
3164err_umrc:
3165 destroy_umrc_res(dev);
3166
3167err_dev:
3168 ib_unregister_device(&dev->ib_dev);
3169
0837e86a
MB		 3170err_q_cnt:
3171 mlx5_ib_dealloc_q_counters(dev);
3172
6aec21f6
HE		 3173err_odp:
3174 mlx5_ib_odp_remove_one(dev);
3175
e126ba97
EC		 3176err_rsrc:
3177 destroy_dev_resources(&dev->devr);
3178
fc24fc5e 3179err_disable_roce:
5ec8c83e 3180 if (ll == IB_LINK_LAYER_ETHERNET) {
fc24fc5e 3181 mlx5_disable_roce(dev);
5ec8c83e
AH		 3182 mlx5_remove_roce_notifier(dev);
3183 }
fc24fc5e 3184
0837e86a
MB		 3185err_free_port:
3186 kfree(dev->port);
3187
9603b61d 3188err_dealloc:
e126ba97
EC		 3189 ib_dealloc_device((struct ib_device *)dev);
3190
9603b61d 3191 return NULL;
e126ba97
EC		 3192}
3193
9603b61d 3194static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 3195{
9603b61d 3196 struct mlx5_ib_dev *dev = context;
fc24fc5e 3197 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 3198
5ec8c83e 3199 mlx5_remove_roce_notifier(dev);
e126ba97 3200 ib_unregister_device(&dev->ib_dev);
0837e86a 3201 mlx5_ib_dealloc_q_counters(dev);
eefd56e5 3202 destroy_umrc_res(dev);
6aec21f6 3203 mlx5_ib_odp_remove_one(dev);
e126ba97 3204 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 3205 if (ll == IB_LINK_LAYER_ETHERNET)
3206 mlx5_disable_roce(dev);
0837e86a 3207 kfree(dev->port);
e126ba97
EC		 3208 ib_dealloc_device(&dev->ib_dev);
3209}
3210
9603b61d
JM		 3211static struct mlx5_interface mlx5_ib_interface = {
3212 .add = mlx5_ib_add,
3213 .remove = mlx5_ib_remove,
3214 .event = mlx5_ib_event,
64613d94 3215 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 3216};
3217
3218static int __init mlx5_ib_init(void)
3219{
6aec21f6
HE		 3220 int err;
3221
9603b61d
JM		 3222 if (deprecated_prof_sel != 2)
3223 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3224
6aec21f6
HE		 3225 err = mlx5_ib_odp_init();
3226 if (err)
3227 return err;
3228
3229 err = mlx5_register_interface(&mlx5_ib_interface);
3230 if (err)
3231 goto clean_odp;
3232
3233 return err;
3234
3235clean_odp:
3236 mlx5_ib_odp_cleanup();
3237 return err;
e126ba97
EC		 3238}
3239
3240static void __exit mlx5_ib_cleanup(void)
3241{
9603b61d 3242 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 3243 mlx5_ib_odp_cleanup();
e126ba97
EC		 3244}
3245
3246module_init(mlx5_ib_init);
3247module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)