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net/mlx5: Fix mlx5_get_vector_affinity function
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
24da0016 41#include <linux/bitmap.h>
37aa5c36
GL		 42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
e126ba97 45#include <linux/sched.h>
6e84f315 46#include <linux/sched/mm.h>
0881e7bd 47#include <linux/sched/task.h>
7c2344c3 48#include <linux/delay.h>
e126ba97 49#include <rdma/ib_user_verbs.h>
3f89a643 50#include <rdma/ib_addr.h>
2811ba51 51#include <rdma/ib_cache.h>
ada68c31 52#include <linux/mlx5/port.h>
1b5daf11 53#include <linux/mlx5/vport.h>
72c7fe90 54#include <linux/mlx5/fs.h>
802c2125 55#include <linux/mlx5/fs_helpers.h>
7c2344c3 56#include <linux/list.h>
e126ba97
EC		 57#include <rdma/ib_smi.h>
58#include <rdma/ib_umem.h>
038d2ef8
MG		 59#include <linux/in.h>
60#include <linux/etherdevice.h>
e126ba97 61#include "mlx5_ib.h"
fc385b7a 62#include "ib_rep.h"
e1f24a79 63#include "cmd.h"
3346c487 64#include <linux/mlx5/fs_helpers.h>
c6475a0b 65#include <linux/mlx5/accel.h>
8c84660b 66#include <rdma/uverbs_std_types.h>
c6475a0b
AY		 67#include <rdma/mlx5_user_ioctl_verbs.h>
68#include <rdma/mlx5_user_ioctl_cmds.h>
8c84660b
MB		 69
70#define UVERBS_MODULE_NAME mlx5_ib
71#include <rdma/uverbs_named_ioctl.h>
e126ba97
EC		 72
73#define DRIVER_NAME "mlx5_ib"
b359911d 74#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 75
76MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
77MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
78MODULE_LICENSE("Dual BSD/GPL");
e126ba97 79
e126ba97
EC		 80static char mlx5_version[] =
81 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 82 DRIVER_VERSION "\n";
e126ba97 83
d69a24e0
DJ		 84struct mlx5_ib_event_work {
85 struct work_struct work;
86 struct mlx5_core_dev *dev;
87 void *context;
88 enum mlx5_dev_event event;
89 unsigned long param;
90};
91
da7525d2
EBE		 92enum {
93 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
94};
95
d69a24e0 96static struct workqueue_struct *mlx5_ib_event_wq;
32f69e4b
DJ		 97static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
98static LIST_HEAD(mlx5_ib_dev_list);
99/*
100 * This mutex should be held when accessing either of the above lists
101 */
102static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
103
c44ef998
IL		 104/* We can't use an array for xlt_emergency_page because dma_map_single
105 * doesn't work on kernel modules memory
106 */
107static unsigned long xlt_emergency_page;
108static struct mutex xlt_emergency_page_mutex;
109
32f69e4b
DJ		 110struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
111{
112 struct mlx5_ib_dev *dev;
113
114 mutex_lock(&mlx5_ib_multiport_mutex);
115 dev = mpi->ibdev;
116 mutex_unlock(&mlx5_ib_multiport_mutex);
117 return dev;
118}
119
1b5daf11 120static enum rdma_link_layer
ebd61f68 121mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 122{
ebd61f68 123 switch (port_type_cap) {
1b5daf11
MD		 124 case MLX5_CAP_PORT_TYPE_IB:
125 return IB_LINK_LAYER_INFINIBAND;
126 case MLX5_CAP_PORT_TYPE_ETH:
127 return IB_LINK_LAYER_ETHERNET;
128 default:
129 return IB_LINK_LAYER_UNSPECIFIED;
130 }
131}
132
ebd61f68
AS		 133static enum rdma_link_layer
134mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
135{
136 struct mlx5_ib_dev *dev = to_mdev(device);
137 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
138
139 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
140}
141
fd65f1b8
MS		 142static int get_port_state(struct ib_device *ibdev,
143 u8 port_num,
144 enum ib_port_state *state)
145{
146 struct ib_port_attr attr;
147 int ret;
148
149 memset(&attr, 0, sizeof(attr));
8e6efa3a 150 ret = ibdev->query_port(ibdev, port_num, &attr);
fd65f1b8
MS		 151 if (!ret)
152 *state = attr.state;
153 return ret;
154}
155
fc24fc5e
AS		 156static int mlx5_netdev_event(struct notifier_block *this,
157 unsigned long event, void *ptr)
158{
7fd8aefb 159 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 160 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 161 u8 port_num = roce->native_port_num;
162 struct mlx5_core_dev *mdev;
163 struct mlx5_ib_dev *ibdev;
164
165 ibdev = roce->dev;
32f69e4b
DJ		 166 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
167 if (!mdev)
168 return NOTIFY_DONE;
fc24fc5e 169
5ec8c83e
AH		 170 switch (event) {
171 case NETDEV_REGISTER:
172 case NETDEV_UNREGISTER:
7fd8aefb 173 write_lock(&roce->netdev_lock);
bcf87f1d
MB		 174 if (ibdev->rep) {
175 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
176 struct net_device *rep_ndev;
177
178 rep_ndev = mlx5_ib_get_rep_netdev(esw,
179 ibdev->rep->vport);
180 if (rep_ndev == ndev)
181 roce->netdev = (event == NETDEV_UNREGISTER) ?
7fd8aefb 182 NULL : ndev;
bcf87f1d
MB		 183 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) {
184 roce->netdev = (event == NETDEV_UNREGISTER) ?
185 NULL : ndev;
186 }
7fd8aefb 187 write_unlock(&roce->netdev_lock);
5ec8c83e 188 break;
fc24fc5e 189
fd65f1b8 190 case NETDEV_CHANGE:
5ec8c83e 191 case NETDEV_UP:
88621dfe 192 case NETDEV_DOWN: {
7fd8aefb 193 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 194 struct net_device *upper = NULL;
195
196 if (lag_ndev) {
197 upper = netdev_master_upper_dev_get(lag_ndev);
198 dev_put(lag_ndev);
199 }
200
7fd8aefb 201 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 202 && ibdev->ib_active) {
626bc02d 203 struct ib_event ibev = { };
fd65f1b8 204 enum ib_port_state port_state;
5ec8c83e 205
7fd8aefb
DJ		 206 if (get_port_state(&ibdev->ib_dev, port_num,
207 &port_state))
208 goto done;
fd65f1b8 209
7fd8aefb
DJ		 210 if (roce->last_port_state == port_state)
211 goto done;
fd65f1b8 212
7fd8aefb 213 roce->last_port_state = port_state;
5ec8c83e 214 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 215 if (port_state == IB_PORT_DOWN)
216 ibev.event = IB_EVENT_PORT_ERR;
217 else if (port_state == IB_PORT_ACTIVE)
218 ibev.event = IB_EVENT_PORT_ACTIVE;
219 else
7fd8aefb 220 goto done;
fd65f1b8 221
7fd8aefb 222 ibev.element.port_num = port_num;
5ec8c83e
AH		 223 ib_dispatch_event(&ibev);
224 }
225 break;
88621dfe 226 }
fc24fc5e 227
5ec8c83e
AH		 228 default:
229 break;
230 }
7fd8aefb 231done:
32f69e4b 232 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 233 return NOTIFY_DONE;
234}
235
236static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
237 u8 port_num)
238{
239 struct mlx5_ib_dev *ibdev = to_mdev(device);
240 struct net_device *ndev;
32f69e4b
DJ		 241 struct mlx5_core_dev *mdev;
242
243 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
244 if (!mdev)
245 return NULL;
fc24fc5e 246
32f69e4b 247 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 248 if (ndev)
32f69e4b 249 goto out;
88621dfe 250
fc24fc5e
AS		 251 /* Ensure ndev does not disappear before we invoke dev_hold()
252 */
7fd8aefb
DJ		 253 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
254 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 255 if (ndev)
256 dev_hold(ndev);
7fd8aefb 257 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 258
32f69e4b
DJ		 259out:
260 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 261 return ndev;
262}
263
32f69e4b
DJ		 264struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
265 u8 ib_port_num,
266 u8 *native_port_num)
267{
268 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
269 ib_port_num);
270 struct mlx5_core_dev *mdev = NULL;
271 struct mlx5_ib_multiport_info *mpi;
272 struct mlx5_ib_port *port;
273
210b1f78
MB		 274 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
275 ll != IB_LINK_LAYER_ETHERNET) {
276 if (native_port_num)
277 *native_port_num = ib_port_num;
278 return ibdev->mdev;
279 }
280
32f69e4b
DJ		 281 if (native_port_num)
282 *native_port_num = 1;
283
32f69e4b
DJ		 284 port = &ibdev->port[ib_port_num - 1];
285 if (!port)
286 return NULL;
287
288 spin_lock(&port->mp.mpi_lock);
289 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
290 if (mpi && !mpi->unaffiliate) {
291 mdev = mpi->mdev;
292 /* If it's the master no need to refcount, it'll exist
293 * as long as the ib_dev exists.
294 */
295 if (!mpi->is_master)
296 mpi->mdev_refcnt++;
297 }
298 spin_unlock(&port->mp.mpi_lock);
299
300 return mdev;
301}
302
303void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
304{
305 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
306 port_num);
307 struct mlx5_ib_multiport_info *mpi;
308 struct mlx5_ib_port *port;
309
310 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
311 return;
312
313 port = &ibdev->port[port_num - 1];
314
315 spin_lock(&port->mp.mpi_lock);
316 mpi = ibdev->port[port_num - 1].mp.mpi;
317 if (mpi->is_master)
318 goto out;
319
320 mpi->mdev_refcnt--;
321 if (mpi->unaffiliate)
322 complete(&mpi->unref_comp);
323out:
324 spin_unlock(&port->mp.mpi_lock);
325}
326
f1b65df5
NO		 327static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
328 u8 *active_width)
329{
330 switch (eth_proto_oper) {
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
332 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
333 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
334 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
335 *active_width = IB_WIDTH_1X;
336 *active_speed = IB_SPEED_SDR;
337 break;
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
344 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
345 *active_width = IB_WIDTH_1X;
346 *active_speed = IB_SPEED_QDR;
347 break;
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
350 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
351 *active_width = IB_WIDTH_1X;
352 *active_speed = IB_SPEED_EDR;
353 break;
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
357 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
358 *active_width = IB_WIDTH_4X;
359 *active_speed = IB_SPEED_QDR;
360 break;
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
363 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
364 *active_width = IB_WIDTH_1X;
365 *active_speed = IB_SPEED_HDR;
366 break;
367 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
368 *active_width = IB_WIDTH_4X;
369 *active_speed = IB_SPEED_FDR;
370 break;
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
374 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
375 *active_width = IB_WIDTH_4X;
376 *active_speed = IB_SPEED_EDR;
377 break;
378 default:
379 return -EINVAL;
380 }
381
382 return 0;
383}
384
095b0927
IT		 385static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
386 struct ib_port_attr *props)
3f89a643
AS		 387{
388 struct mlx5_ib_dev *dev = to_mdev(device);
da005f9f 389 struct mlx5_core_dev *mdev;
88621dfe 390 struct net_device *ndev, *upper;
3f89a643 391 enum ib_mtu ndev_ib_mtu;
b3cbd6f0 392 bool put_mdev = true;
c876a1b7 393 u16 qkey_viol_cntr;
f1b65df5 394 u32 eth_prot_oper;
b3cbd6f0 395 u8 mdev_port_num;
095b0927 396 int err;
3f89a643 397
b3cbd6f0
DJ		 398 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
399 if (!mdev) {
400 /* This means the port isn't affiliated yet. Get the
401 * info for the master port instead.
402 */
403 put_mdev = false;
404 mdev = dev->mdev;
405 mdev_port_num = 1;
406 port_num = 1;
407 }
408
f1b65df5
NO		 409 /* Possible bad flows are checked before filling out props so in case
410 * of an error it will still be zeroed out.
50f22fd8 411 */
b3cbd6f0
DJ		 412 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
413 mdev_port_num);
095b0927 414 if (err)
b3cbd6f0 415 goto out;
f1b65df5 416
7672ed33
HL		 417 props->active_width = IB_WIDTH_4X;
418 props->active_speed = IB_SPEED_QDR;
419
f1b65df5
NO		 420 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
421 &props->active_width);
3f89a643
AS		 422
423 props->port_cap_flags |= IB_PORT_CM_SUP;
424 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
425
426 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
427 roce_address_table_size);
428 props->max_mtu = IB_MTU_4096;
429 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
430 props->pkey_tbl_len = 1;
431 props->state = IB_PORT_DOWN;
432 props->phys_state = 3;
433
b3cbd6f0 434 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
c876a1b7 435 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643 436
b3cbd6f0
DJ		 437 /* If this is a stub query for an unaffiliated port stop here */
438 if (!put_mdev)
439 goto out;
440
3f89a643
AS		 441 ndev = mlx5_ib_get_netdev(device, port_num);
442 if (!ndev)
b3cbd6f0 443 goto out;
3f89a643 444
88621dfe
AH		 445 if (mlx5_lag_is_active(dev->mdev)) {
446 rcu_read_lock();
447 upper = netdev_master_upper_dev_get_rcu(ndev);
448 if (upper) {
449 dev_put(ndev);
450 ndev = upper;
451 dev_hold(ndev);
452 }
453 rcu_read_unlock();
454 }
455
3f89a643
AS		 456 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
457 props->state = IB_PORT_ACTIVE;
458 props->phys_state = 5;
459 }
460
461 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
462
463 dev_put(ndev);
464
465 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
b3cbd6f0
DJ		 466out:
467 if (put_mdev)
468 mlx5_ib_put_native_port_mdev(dev, port_num);
469 return err;
3f89a643
AS		 470}
471
095b0927
IT		 472static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
473 unsigned int index, const union ib_gid *gid,
474 const struct ib_gid_attr *attr)
3cca2606 475{
095b0927
IT		 476 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
477 u8 roce_version = 0;
478 u8 roce_l3_type = 0;
479 bool vlan = false;
480 u8 mac[ETH_ALEN];
481 u16 vlan_id = 0;
482
483 if (gid) {
484 gid_type = attr->gid_type;
485 ether_addr_copy(mac, attr->ndev->dev_addr);
486
487 if (is_vlan_dev(attr->ndev)) {
488 vlan = true;
489 vlan_id = vlan_dev_vlan_id(attr->ndev);
490 }
3cca2606
AS		 491 }
492
095b0927 493 switch (gid_type) {
3cca2606 494 case IB_GID_TYPE_IB:
095b0927 495 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 496 break;
497 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 498 roce_version = MLX5_ROCE_VERSION_2;
499 if (ipv6_addr_v4mapped((void *)gid))
500 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
501 else
502 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 503 break;
504
505 default:
095b0927 506 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 507 }
508
095b0927
IT		 509 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
510 roce_l3_type, gid->raw, mac, vlan,
cfe4e37f 511 vlan_id, port_num);
3cca2606
AS		 512}
513
414448d2 514static int mlx5_ib_add_gid(const union ib_gid *gid,
3cca2606
AS		 515 const struct ib_gid_attr *attr,
516 __always_unused void **context)
517{
414448d2
PP		 518 return set_roce_addr(to_mdev(attr->device), attr->port_num,
519 attr->index, gid, attr);
3cca2606
AS		 520}
521
414448d2
PP		 522static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
523 __always_unused void **context)
3cca2606 524{
414448d2
PP		 525 return set_roce_addr(to_mdev(attr->device), attr->port_num,
526 attr->index, NULL, NULL);
3cca2606
AS		 527}
528
2811ba51
AS		 529__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
530 int index)
531{
532 struct ib_gid_attr attr;
533 union ib_gid gid;
534
535 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
536 return 0;
537
2811ba51
AS		 538 dev_put(attr.ndev);
539
540 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
541 return 0;
542
543 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
544}
545
ed88451e
MD		 546int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
547 int index, enum ib_gid_type *gid_type)
548{
549 struct ib_gid_attr attr;
550 union ib_gid gid;
551 int ret;
552
553 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
554 if (ret)
555 return ret;
556
ed88451e
MD		 557 dev_put(attr.ndev);
558
559 *gid_type = attr.gid_type;
560
561 return 0;
562}
563
1b5daf11
MD		 564static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
565{
7fae6655
NO		 566 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
567 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
568 return 0;
1b5daf11
MD		 569}
570
571enum {
572 MLX5_VPORT_ACCESS_METHOD_MAD,
573 MLX5_VPORT_ACCESS_METHOD_HCA,
574 MLX5_VPORT_ACCESS_METHOD_NIC,
575};
576
577static int mlx5_get_vport_access_method(struct ib_device *ibdev)
578{
579 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
580 return MLX5_VPORT_ACCESS_METHOD_MAD;
581
ebd61f68 582 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 583 IB_LINK_LAYER_ETHERNET)
584 return MLX5_VPORT_ACCESS_METHOD_NIC;
585
586 return MLX5_VPORT_ACCESS_METHOD_HCA;
587}
588
da7525d2 589static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 590 u8 atomic_size_qp,
da7525d2
EBE		 591 struct ib_device_attr *props)
592{
593 u8 tmp;
594 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 595 u8 atomic_req_8B_endianness_mode =
bd10838a 596 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 597
598 /* Check if HW supports 8 bytes standard atomic operations and capable
599 * of host endianness respond
600 */
601 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
602 if (((atomic_operations & tmp) == tmp) &&
603 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
604 (atomic_req_8B_endianness_mode)) {
605 props->atomic_cap = IB_ATOMIC_HCA;
606 } else {
607 props->atomic_cap = IB_ATOMIC_NONE;
608 }
609}
610
776a3906
MS		 611static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
612 struct ib_device_attr *props)
613{
614 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
615
616 get_atomic_caps(dev, atomic_size_qp, props);
617}
618
619static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
620 struct ib_device_attr *props)
621{
622 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
623
624 get_atomic_caps(dev, atomic_size_qp, props);
625}
626
627bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
628{
629 struct ib_device_attr props = {};
630
631 get_atomic_caps_dc(dev, &props);
632 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
633}
1b5daf11
MD		 634static int mlx5_query_system_image_guid(struct ib_device *ibdev,
635 __be64 *sys_image_guid)
636{
637 struct mlx5_ib_dev *dev = to_mdev(ibdev);
638 struct mlx5_core_dev *mdev = dev->mdev;
639 u64 tmp;
640 int err;
641
642 switch (mlx5_get_vport_access_method(ibdev)) {
643 case MLX5_VPORT_ACCESS_METHOD_MAD:
644 return mlx5_query_mad_ifc_system_image_guid(ibdev,
645 sys_image_guid);
646
647 case MLX5_VPORT_ACCESS_METHOD_HCA:
648 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 649 break;
650
651 case MLX5_VPORT_ACCESS_METHOD_NIC:
652 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
653 break;
1b5daf11
MD		 654
655 default:
656 return -EINVAL;
657 }
3f89a643
AS		 658
659 if (!err)
660 *sys_image_guid = cpu_to_be64(tmp);
661
662 return err;
663
1b5daf11
MD		 664}
665
666static int mlx5_query_max_pkeys(struct ib_device *ibdev,
667 u16 *max_pkeys)
668{
669 struct mlx5_ib_dev *dev = to_mdev(ibdev);
670 struct mlx5_core_dev *mdev = dev->mdev;
671
672 switch (mlx5_get_vport_access_method(ibdev)) {
673 case MLX5_VPORT_ACCESS_METHOD_MAD:
674 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
675
676 case MLX5_VPORT_ACCESS_METHOD_HCA:
677 case MLX5_VPORT_ACCESS_METHOD_NIC:
678 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
679 pkey_table_size));
680 return 0;
681
682 default:
683 return -EINVAL;
684 }
685}
686
687static int mlx5_query_vendor_id(struct ib_device *ibdev,
688 u32 *vendor_id)
689{
690 struct mlx5_ib_dev *dev = to_mdev(ibdev);
691
692 switch (mlx5_get_vport_access_method(ibdev)) {
693 case MLX5_VPORT_ACCESS_METHOD_MAD:
694 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
695
696 case MLX5_VPORT_ACCESS_METHOD_HCA:
697 case MLX5_VPORT_ACCESS_METHOD_NIC:
698 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
699
700 default:
701 return -EINVAL;
702 }
703}
704
705static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
706 __be64 *node_guid)
707{
708 u64 tmp;
709 int err;
710
711 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
712 case MLX5_VPORT_ACCESS_METHOD_MAD:
713 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
714
715 case MLX5_VPORT_ACCESS_METHOD_HCA:
716 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 717 break;
718
719 case MLX5_VPORT_ACCESS_METHOD_NIC:
720 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
721 break;
1b5daf11
MD		 722
723 default:
724 return -EINVAL;
725 }
3f89a643
AS		 726
727 if (!err)
728 *node_guid = cpu_to_be64(tmp);
729
730 return err;
1b5daf11
MD		 731}
732
733struct mlx5_reg_node_desc {
bd99fdea 734 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 735};
736
737static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
738{
739 struct mlx5_reg_node_desc in;
740
741 if (mlx5_use_mad_ifc(dev))
742 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
743
744 memset(&in, 0, sizeof(in));
745
746 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
747 sizeof(struct mlx5_reg_node_desc),
748 MLX5_REG_NODE_DESC, 0, 0);
749}
750
e126ba97 751static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 752 struct ib_device_attr *props,
753 struct ib_udata *uhw)
e126ba97
EC		 754{
755 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 756 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 757 int err = -ENOMEM;
288c01b7 758 int max_sq_desc;
e126ba97
EC		 759 int max_rq_sg;
760 int max_sq_sg;
e0238a6a 761 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
85c7c014 762 bool raw_support = !mlx5_core_mp_enabled(mdev);
402ca536
BW		 763 struct mlx5_ib_query_device_resp resp = {};
764 size_t resp_len;
765 u64 max_tso;
e126ba97 766
402ca536
BW		 767 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
768 if (uhw->outlen && uhw->outlen < resp_len)
769 return -EINVAL;
770 else
771 resp.response_length = resp_len;
772
773 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 774 return -EINVAL;
775
1b5daf11
MD		 776 memset(props, 0, sizeof(*props));
777 err = mlx5_query_system_image_guid(ibdev,
778 &props->sys_image_guid);
779 if (err)
780 return err;
e126ba97 781
1b5daf11 782 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 783 if (err)
1b5daf11 784 return err;
e126ba97 785
1b5daf11
MD		 786 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
787 if (err)
788 return err;
e126ba97 789
9603b61d
JM		 790 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
791 (fw_rev_min(dev->mdev) << 16) |
792 fw_rev_sub(dev->mdev);
e126ba97
EC		 793 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
794 IB_DEVICE_PORT_ACTIVE_EVENT |
795 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 796 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 797
798 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 799 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 800 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 801 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 802 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 803 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 804 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 805 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 806 if (MLX5_CAP_GEN(mdev, imaicl)) {
807 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
808 IB_DEVICE_MEM_WINDOW_TYPE_2B;
809 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 810 /* We support 'Gappy' memory registration too */
811 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 812 }
e126ba97 813 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 814 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 815 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
816 /* At this stage no support for signature handover */
817 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
818 IB_PROT_T10DIF_TYPE_2 |
819 IB_PROT_T10DIF_TYPE_3;
820 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
821 IB_GUARD_T10DIF_CSUM;
822 }
938fe83c 823 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 824 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 825
85c7c014 826 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
e8161334
NO		 827 if (MLX5_CAP_ETH(mdev, csum_cap)) {
828 /* Legacy bit to support old userspace libraries */
88115fe7 829 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 830 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
831 }
832
833 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
834 props->raw_packet_caps |=
835 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 836
402ca536
BW		 837 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
838 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
839 if (max_tso) {
840 resp.tso_caps.max_tso = 1 << max_tso;
841 resp.tso_caps.supported_qpts |=
842 1 << IB_QPT_RAW_PACKET;
843 resp.response_length += sizeof(resp.tso_caps);
844 }
845 }
31f69a82
YH		 846
847 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
848 resp.rss_caps.rx_hash_function =
849 MLX5_RX_HASH_FUNC_TOEPLITZ;
850 resp.rss_caps.rx_hash_fields_mask =
851 MLX5_RX_HASH_SRC_IPV4 |
852 MLX5_RX_HASH_DST_IPV4 |
853 MLX5_RX_HASH_SRC_IPV6 |
854 MLX5_RX_HASH_DST_IPV6 |
855 MLX5_RX_HASH_SRC_PORT_TCP |
856 MLX5_RX_HASH_DST_PORT_TCP |
857 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 858 MLX5_RX_HASH_DST_PORT_UDP |
859 MLX5_RX_HASH_INNER;
2d93fc85
MB		 860 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
861 MLX5_ACCEL_IPSEC_CAP_DEVICE)
862 resp.rss_caps.rx_hash_fields_mask |=
863 MLX5_RX_HASH_IPSEC_SPI;
31f69a82
YH		 864 resp.response_length += sizeof(resp.rss_caps);
865 }
866 } else {
867 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
868 resp.response_length += sizeof(resp.tso_caps);
869 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
870 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 871 }
872
f0313965
ES		 873 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
874 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
875 props->device_cap_flags |= IB_DEVICE_UD_TSO;
876 }
877
03404e8a 878 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
85c7c014
DJ		 879 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
880 raw_support)
03404e8a
MG		 881 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
882
1d54f890
YH		 883 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
884 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
885 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
886
cff5a0f3 887 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
85c7c014
DJ		 888 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
889 raw_support) {
e8161334 890 /* Legacy bit to support old userspace libraries */
cff5a0f3 891 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 892 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
893 }
cff5a0f3 894
24da0016
AL		 895 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
896 props->max_dm_size =
897 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
898 }
899
da6d6ba3
MG		 900 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
901 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
902
b1383aa6
NO		 903 if (MLX5_CAP_GEN(mdev, end_pad))
904 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
905
1b5daf11
MD		 906 props->vendor_part_id = mdev->pdev->device;
907 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 908
909 props->max_mr_size = ~0ull;
e0238a6a 910 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 911 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
912 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
913 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
914 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 915 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
916 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
917 sizeof(struct mlx5_wqe_raddr_seg)) /
918 sizeof(struct mlx5_wqe_data_seg);
e126ba97 919 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 920 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 921 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 922 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 923 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
924 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
925 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
926 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
927 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
928 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
929 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 930 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 931 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 932 props->max_fast_reg_page_list_len =
933 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 934 get_atomic_caps_qp(dev, props);
81bea28f 935 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 936 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
937 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 938 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
939 props->max_mcast_grp;
940 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 941 props->max_ah = INT_MAX;
7c60bcbb
MB		 942 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
943 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 944
8cdd312c 945#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 946 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 947 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
948 props->odp_caps = dev->odp_caps;
949#endif
950
051f2630
LR		 951 if (MLX5_CAP_GEN(mdev, cd))
952 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
953
eff901d3
EC		 954 if (!mlx5_core_is_pf(mdev))
955 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
956
31f69a82 957 if (mlx5_ib_port_link_layer(ibdev, 1) ==
85c7c014 958 IB_LINK_LAYER_ETHERNET && raw_support) {
31f69a82
YH		 959 props->rss_caps.max_rwq_indirection_tables =
960 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
961 props->rss_caps.max_rwq_indirection_table_size =
962 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
963 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
964 props->max_wq_type_rq =
965 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
966 }
967
eb761894 968 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 969 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
970 props->tm_caps.max_num_tags =
eb761894 971 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 972 props->tm_caps.flags = IB_TM_CAP_RC;
973 props->tm_caps.max_ops =
eb761894 974 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 975 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 976 }
977
87ab3f52
YC		 978 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
979 props->cq_caps.max_cq_moderation_count =
980 MLX5_MAX_CQ_COUNT;
981 props->cq_caps.max_cq_moderation_period =
982 MLX5_MAX_CQ_PERIOD;
983 }
984
7e43a2a5
BW		 985 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
986 resp.cqe_comp_caps.max_num =
987 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
988 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
989 resp.cqe_comp_caps.supported_format =
990 MLX5_IB_CQE_RES_FORMAT_HASH |
991 MLX5_IB_CQE_RES_FORMAT_CSUM;
992 resp.response_length += sizeof(resp.cqe_comp_caps);
993 }
994
85c7c014
DJ		 995 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
996 raw_support) {
d949167d
BW		 997 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
998 MLX5_CAP_GEN(mdev, qos)) {
999 resp.packet_pacing_caps.qp_rate_limit_max =
1000 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1001 resp.packet_pacing_caps.qp_rate_limit_min =
1002 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1003 resp.packet_pacing_caps.supported_qpts |=
1004 1 << IB_QPT_RAW_PACKET;
61147f39
BW		 1005 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1006 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1007 resp.packet_pacing_caps.cap_flags |=
1008 MLX5_IB_PP_SUPPORT_BURST;
d949167d
BW		 1009 }
1010 resp.response_length += sizeof(resp.packet_pacing_caps);
1011 }
1012
9f885201
LR		 1013 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1014 uhw->outlen)) {
795b609c
BW		 1015 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1016 resp.mlx5_ib_support_multi_pkt_send_wqes =
1017 MLX5_IB_ALLOW_MPW;
050da902
BW		 1018
1019 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1020 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1021 MLX5_IB_SUPPORT_EMPW;
1022
9f885201
LR		 1023 resp.response_length +=
1024 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1025 }
1026
de57f2ad
GL		 1027 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1028 resp.response_length += sizeof(resp.flags);
7a0c8f42 1029
de57f2ad
GL		 1030 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1031 resp.flags |=
1032 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 1033
1034 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1035 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 1036 }
9f885201 1037
96dc3fc5
NO		 1038 if (field_avail(typeof(resp), sw_parsing_caps,
1039 uhw->outlen)) {
1040 resp.response_length += sizeof(resp.sw_parsing_caps);
1041 if (MLX5_CAP_ETH(mdev, swp)) {
1042 resp.sw_parsing_caps.sw_parsing_offloads |=
1043 MLX5_IB_SW_PARSING;
1044
1045 if (MLX5_CAP_ETH(mdev, swp_csum))
1046 resp.sw_parsing_caps.sw_parsing_offloads |=
1047 MLX5_IB_SW_PARSING_CSUM;
1048
1049 if (MLX5_CAP_ETH(mdev, swp_lso))
1050 resp.sw_parsing_caps.sw_parsing_offloads |=
1051 MLX5_IB_SW_PARSING_LSO;
1052
1053 if (resp.sw_parsing_caps.sw_parsing_offloads)
1054 resp.sw_parsing_caps.supported_qpts =
1055 BIT(IB_QPT_RAW_PACKET);
1056 }
1057 }
1058
85c7c014
DJ		 1059 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1060 raw_support) {
b4f34597
NO		 1061 resp.response_length += sizeof(resp.striding_rq_caps);
1062 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1063 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1064 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1065 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1066 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1067 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1068 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1069 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1070 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1071 resp.striding_rq_caps.supported_qpts =
1072 BIT(IB_QPT_RAW_PACKET);
1073 }
1074 }
1075
f95ef6cb
MG		 1076 if (field_avail(typeof(resp), tunnel_offloads_caps,
1077 uhw->outlen)) {
1078 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1079 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1080 resp.tunnel_offloads_caps |=
1081 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1082 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1083 resp.tunnel_offloads_caps |=
1084 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1085 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1086 resp.tunnel_offloads_caps |=
1087 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1088 }
1089
402ca536
BW		 1090 if (uhw->outlen) {
1091 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1092
1093 if (err)
1094 return err;
1095 }
1096
1b5daf11 1097 return 0;
e126ba97
EC		 1098}
1099
1b5daf11
MD		 1100enum mlx5_ib_width {
1101 MLX5_IB_WIDTH_1X = 1 << 0,
1102 MLX5_IB_WIDTH_2X = 1 << 1,
1103 MLX5_IB_WIDTH_4X = 1 << 2,
1104 MLX5_IB_WIDTH_8X = 1 << 3,
1105 MLX5_IB_WIDTH_12X = 1 << 4
1106};
1107
1108static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1109 u8 *ib_width)
e126ba97
EC		 1110{
1111 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1112 int err = 0;
1113
1114 if (active_width & MLX5_IB_WIDTH_1X) {
1115 *ib_width = IB_WIDTH_1X;
1116 } else if (active_width & MLX5_IB_WIDTH_2X) {
1117 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1118 (int)active_width);
1119 err = -EINVAL;
1120 } else if (active_width & MLX5_IB_WIDTH_4X) {
1121 *ib_width = IB_WIDTH_4X;
1122 } else if (active_width & MLX5_IB_WIDTH_8X) {
1123 *ib_width = IB_WIDTH_8X;
1124 } else if (active_width & MLX5_IB_WIDTH_12X) {
1125 *ib_width = IB_WIDTH_12X;
1126 } else {
1127 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1128 (int)active_width);
1129 err = -EINVAL;
e126ba97
EC		 1130 }
1131
1b5daf11
MD		 1132 return err;
1133}
e126ba97 1134
1b5daf11
MD		 1135static int mlx5_mtu_to_ib_mtu(int mtu)
1136{
1137 switch (mtu) {
1138 case 256: return 1;
1139 case 512: return 2;
1140 case 1024: return 3;
1141 case 2048: return 4;
1142 case 4096: return 5;
1143 default:
1144 pr_warn("invalid mtu\n");
1145 return -1;
e126ba97 1146 }
1b5daf11 1147}
e126ba97 1148
1b5daf11
MD		 1149enum ib_max_vl_num {
1150 __IB_MAX_VL_0 = 1,
1151 __IB_MAX_VL_0_1 = 2,
1152 __IB_MAX_VL_0_3 = 3,
1153 __IB_MAX_VL_0_7 = 4,
1154 __IB_MAX_VL_0_14 = 5,
1155};
e126ba97 1156
1b5daf11
MD		 1157enum mlx5_vl_hw_cap {
1158 MLX5_VL_HW_0 = 1,
1159 MLX5_VL_HW_0_1 = 2,
1160 MLX5_VL_HW_0_2 = 3,
1161 MLX5_VL_HW_0_3 = 4,
1162 MLX5_VL_HW_0_4 = 5,
1163 MLX5_VL_HW_0_5 = 6,
1164 MLX5_VL_HW_0_6 = 7,
1165 MLX5_VL_HW_0_7 = 8,
1166 MLX5_VL_HW_0_14 = 15
1167};
e126ba97 1168
1b5daf11
MD		 1169static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1170 u8 *max_vl_num)
1171{
1172 switch (vl_hw_cap) {
1173 case MLX5_VL_HW_0:
1174 *max_vl_num = __IB_MAX_VL_0;
1175 break;
1176 case MLX5_VL_HW_0_1:
1177 *max_vl_num = __IB_MAX_VL_0_1;
1178 break;
1179 case MLX5_VL_HW_0_3:
1180 *max_vl_num = __IB_MAX_VL_0_3;
1181 break;
1182 case MLX5_VL_HW_0_7:
1183 *max_vl_num = __IB_MAX_VL_0_7;
1184 break;
1185 case MLX5_VL_HW_0_14:
1186 *max_vl_num = __IB_MAX_VL_0_14;
1187 break;
e126ba97 1188
1b5daf11
MD		 1189 default:
1190 return -EINVAL;
e126ba97 1191 }
e126ba97 1192
1b5daf11 1193 return 0;
e126ba97
EC		 1194}
1195
1b5daf11
MD		 1196static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1197 struct ib_port_attr *props)
e126ba97 1198{
1b5daf11
MD		 1199 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1200 struct mlx5_core_dev *mdev = dev->mdev;
1201 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1202 u16 max_mtu;
1203 u16 oper_mtu;
1b5daf11
MD		 1204 int err;
1205 u8 ib_link_width_oper;
1206 u8 vl_hw_cap;
e126ba97 1207
1b5daf11
MD		 1208 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1209 if (!rep) {
1210 err = -ENOMEM;
e126ba97 1211 goto out;
e126ba97 1212 }
e126ba97 1213
c4550c63 1214 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1215
1b5daf11 1216 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1217 if (err)
1218 goto out;
1219
1b5daf11
MD		 1220 props->lid = rep->lid;
1221 props->lmc = rep->lmc;
1222 props->sm_lid = rep->sm_lid;
1223 props->sm_sl = rep->sm_sl;
1224 props->state = rep->vport_state;
1225 props->phys_state = rep->port_physical_state;
1226 props->port_cap_flags = rep->cap_mask1;
1227 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1228 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1229 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1230 props->bad_pkey_cntr = rep->pkey_violation_counter;
1231 props->qkey_viol_cntr = rep->qkey_violation_counter;
1232 props->subnet_timeout = rep->subnet_timeout;
1233 props->init_type_reply = rep->init_type_reply;
eff901d3 1234 props->grh_required = rep->grh_required;
e126ba97 1235
1b5daf11
MD		 1236 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1237 if (err)
e126ba97 1238 goto out;
e126ba97 1239
1b5daf11
MD		 1240 err = translate_active_width(ibdev, ib_link_width_oper,
1241 &props->active_width);
1242 if (err)
1243 goto out;
d5beb7f2 1244 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1245 if (err)
1246 goto out;
1247
facc9699 1248 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1249
1b5daf11 1250 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1251
facc9699 1252 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1253
1b5daf11 1254 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1255
1b5daf11
MD		 1256 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1257 if (err)
1258 goto out;
e126ba97 1259
1b5daf11
MD		 1260 err = translate_max_vl_num(ibdev, vl_hw_cap,
1261 &props->max_vl_num);
e126ba97 1262out:
1b5daf11 1263 kfree(rep);
e126ba97
EC		 1264 return err;
1265}
1266
1b5daf11
MD		 1267int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1268 struct ib_port_attr *props)
e126ba97 1269{
095b0927
IT		 1270 unsigned int count;
1271 int ret;
1272
1b5daf11
MD		 1273 switch (mlx5_get_vport_access_method(ibdev)) {
1274 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1275 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1276 break;
e126ba97 1277
1b5daf11 1278 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1279 ret = mlx5_query_hca_port(ibdev, port, props);
1280 break;
e126ba97 1281
3f89a643 1282 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1283 ret = mlx5_query_port_roce(ibdev, port, props);
1284 break;
3f89a643 1285
1b5daf11 1286 default:
095b0927
IT		 1287 ret = -EINVAL;
1288 }
1289
1290 if (!ret && props) {
b3cbd6f0
DJ		 1291 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1292 struct mlx5_core_dev *mdev;
1293 bool put_mdev = true;
1294
1295 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1296 if (!mdev) {
1297 /* If the port isn't affiliated yet query the master.
1298 * The master and slave will have the same values.
1299 */
1300 mdev = dev->mdev;
1301 port = 1;
1302 put_mdev = false;
1303 }
1304 count = mlx5_core_reserved_gids_count(mdev);
1305 if (put_mdev)
1306 mlx5_ib_put_native_port_mdev(dev, port);
095b0927 1307 props->gid_tbl_len -= count;
1b5daf11 1308 }
095b0927 1309 return ret;
1b5daf11 1310}
e126ba97 1311
8e6efa3a
MB		 1312static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1313 struct ib_port_attr *props)
1314{
1315 int ret;
1316
1317 /* Only link layer == ethernet is valid for representors */
1318 ret = mlx5_query_port_roce(ibdev, port, props);
1319 if (ret || !props)
1320 return ret;
1321
1322 /* We don't support GIDS */
1323 props->gid_tbl_len = 0;
1324
1325 return ret;
1326}
1327
1b5daf11
MD		 1328static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1329 union ib_gid *gid)
1330{
1331 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1332 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1333
1b5daf11
MD		 1334 switch (mlx5_get_vport_access_method(ibdev)) {
1335 case MLX5_VPORT_ACCESS_METHOD_MAD:
1336 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1337
1b5daf11
MD		 1338 case MLX5_VPORT_ACCESS_METHOD_HCA:
1339 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1340
1341 default:
1342 return -EINVAL;
1343 }
e126ba97 1344
e126ba97
EC		 1345}
1346
b3cbd6f0
DJ		 1347static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1348 u16 index, u16 *pkey)
1b5daf11
MD		 1349{
1350 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b3cbd6f0
DJ		 1351 struct mlx5_core_dev *mdev;
1352 bool put_mdev = true;
1353 u8 mdev_port_num;
1354 int err;
1b5daf11 1355
b3cbd6f0
DJ		 1356 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1357 if (!mdev) {
1358 /* The port isn't affiliated yet, get the PKey from the master
1359 * port. For RoCE the PKey tables will be the same.
1360 */
1361 put_mdev = false;
1362 mdev = dev->mdev;
1363 mdev_port_num = 1;
1364 }
1365
1366 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1367 index, pkey);
1368 if (put_mdev)
1369 mlx5_ib_put_native_port_mdev(dev, port);
1370
1371 return err;
1372}
1373
1374static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1375 u16 *pkey)
1376{
1b5daf11
MD		 1377 switch (mlx5_get_vport_access_method(ibdev)) {
1378 case MLX5_VPORT_ACCESS_METHOD_MAD:
1379 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1380
1381 case MLX5_VPORT_ACCESS_METHOD_HCA:
1382 case MLX5_VPORT_ACCESS_METHOD_NIC:
b3cbd6f0 1383 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1b5daf11
MD		 1384 default:
1385 return -EINVAL;
1386 }
1387}
e126ba97
EC		 1388
1389static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1390 struct ib_device_modify *props)
1391{
1392 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1393 struct mlx5_reg_node_desc in;
1394 struct mlx5_reg_node_desc out;
1395 int err;
1396
1397 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1398 return -EOPNOTSUPP;
1399
1400 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1401 return 0;
1402
1403 /*
1404 * If possible, pass node desc to FW, so it can generate
1405 * a 144 trap. If cmd fails, just ignore.
1406 */
bd99fdea 1407 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1408 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1409 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1410 if (err)
1411 return err;
1412
bd99fdea 1413 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1414
1415 return err;
1416}
1417
cdbe33d0
EC		 1418static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1419 u32 value)
1420{
1421 struct mlx5_hca_vport_context ctx = {};
b3cbd6f0
DJ		 1422 struct mlx5_core_dev *mdev;
1423 u8 mdev_port_num;
cdbe33d0
EC		 1424 int err;
1425
b3cbd6f0
DJ		 1426 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1427 if (!mdev)
1428 return -ENODEV;
1429
1430 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
cdbe33d0 1431 if (err)
b3cbd6f0 1432 goto out;
cdbe33d0
EC		 1433
1434 if (~ctx.cap_mask1_perm & mask) {
1435 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1436 mask, ctx.cap_mask1_perm);
b3cbd6f0
DJ		 1437 err = -EINVAL;
1438 goto out;
cdbe33d0
EC		 1439 }
1440
1441 ctx.cap_mask1 = value;
1442 ctx.cap_mask1_perm = mask;
b3cbd6f0
DJ		 1443 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1444 0, &ctx);
1445
1446out:
1447 mlx5_ib_put_native_port_mdev(dev, port_num);
cdbe33d0
EC		 1448
1449 return err;
1450}
1451
e126ba97
EC		 1452static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1453 struct ib_port_modify *props)
1454{
1455 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1456 struct ib_port_attr attr;
1457 u32 tmp;
1458 int err;
cdbe33d0
EC		 1459 u32 change_mask;
1460 u32 value;
1461 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1462 IB_LINK_LAYER_INFINIBAND);
1463
ec255879
MD		 1464 /* CM layer calls ib_modify_port() regardless of the link layer. For
1465 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1466 */
1467 if (!is_ib)
1468 return 0;
1469
cdbe33d0
EC		 1470 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1471 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1472 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1473 return set_port_caps_atomic(dev, port, change_mask, value);
1474 }
e126ba97
EC		 1475
1476 mutex_lock(&dev->cap_mask_mutex);
1477
c4550c63 1478 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1479 if (err)
1480 goto out;
1481
1482 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1483 ~props->clr_port_cap_mask;
1484
9603b61d 1485 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1486
1487out:
1488 mutex_unlock(&dev->cap_mask_mutex);
1489 return err;
1490}
1491
30aa60b3
EC		 1492static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1493{
1494 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1495 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1496}
1497
31a78a5a
YH		 1498static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1499{
1500 /* Large page with non 4k uar support might limit the dynamic size */
1501 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1502 return MLX5_MIN_DYN_BFREGS;
1503
1504 return MLX5_MAX_DYN_BFREGS;
1505}
1506
b037c29a
EC		 1507static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1508 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1509 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1510{
1511 int uars_per_sys_page;
1512 int bfregs_per_sys_page;
1513 int ref_bfregs = req->total_num_bfregs;
1514
1515 if (req->total_num_bfregs == 0)
1516 return -EINVAL;
1517
1518 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1519 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1520
1521 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1522 return -ENOMEM;
1523
1524 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1525 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1526 /* This holds the required static allocation asked by the user */
b037c29a 1527 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1528 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1529 return -EINVAL;
1530
31a78a5a
YH		 1531 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1532 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1533 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1534 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1535
1536 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1537 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1538 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1539 req->total_num_bfregs, bfregi->total_num_bfregs,
1540 bfregi->num_sys_pages);
b037c29a
EC		 1541
1542 return 0;
1543}
1544
1545static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1546{
1547 struct mlx5_bfreg_info *bfregi;
1548 int err;
1549 int i;
1550
1551 bfregi = &context->bfregi;
31a78a5a 1552 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1553 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1554 if (err)
1555 goto error;
1556
1557 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1558 }
4ed131d0
YH		 1559
1560 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1561 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1562
b037c29a
EC		 1563 return 0;
1564
1565error:
1566 for (--i; i >= 0; i--)
1567 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1568 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1569
1570 return err;
1571}
1572
1573static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1574{
1575 struct mlx5_bfreg_info *bfregi;
1576 int err;
1577 int i;
1578
1579 bfregi = &context->bfregi;
4ed131d0
YH		 1580 for (i = 0; i < bfregi->num_sys_pages; i++) {
1581 if (i < bfregi->num_static_sys_pages ||
1582 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1583 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1584 if (err) {
1585 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1586 return err;
1587 }
b037c29a
EC		 1588 }
1589 }
4ed131d0 1590
b037c29a
EC		 1591 return 0;
1592}
1593
c85023e1
HN		 1594static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1595{
1596 int err;
1597
1598 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1599 if (err)
1600 return err;
1601
1602 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1603 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1604 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1605 return err;
1606
1607 mutex_lock(&dev->lb_mutex);
1608 dev->user_td++;
1609
1610 if (dev->user_td == 2)
1611 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1612
1613 mutex_unlock(&dev->lb_mutex);
1614 return err;
1615}
1616
1617static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1618{
1619 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1620
1621 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
8978cc92
EBE		 1622 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1623 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c85023e1
HN		 1624 return;
1625
1626 mutex_lock(&dev->lb_mutex);
1627 dev->user_td--;
1628
1629 if (dev->user_td < 2)
1630 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1631
1632 mutex_unlock(&dev->lb_mutex);
1633}
1634
e126ba97
EC		 1635static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1636 struct ib_udata *udata)
1637{
1638 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1639 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1640 struct mlx5_ib_alloc_ucontext_resp resp = {};
5c99eaec 1641 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1642 struct mlx5_ib_ucontext *context;
2f5ff264 1643 struct mlx5_bfreg_info *bfregi;
78c0f98c 1644 int ver;
e126ba97 1645 int err;
a168a41c
MD		 1646 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1647 max_cqe_version);
b037c29a 1648 bool lib_uar_4k;
e126ba97
EC		 1649
1650 if (!dev->ib_active)
1651 return ERR_PTR(-EAGAIN);
1652
e093111d 1653 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1654 ver = 0;
e093111d 1655 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1656 ver = 2;
1657 else
1658 return ERR_PTR(-EINVAL);
1659
e093111d 1660 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1661 if (err)
1662 return ERR_PTR(err);
1663
b368d7cb 1664 if (req.flags)
78c0f98c
EC		 1665 return ERR_PTR(-EINVAL);
1666
f72300c5 1667 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1668 return ERR_PTR(-EOPNOTSUPP);
1669
2f5ff264
EC		 1670 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1671 MLX5_NON_FP_BFREGS_PER_UAR);
1672 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1673 return ERR_PTR(-EINVAL);
1674
938fe83c 1675 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1676 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1677 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1678 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1679 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1680 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1681 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1682 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1683 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1684 resp.cqe_version = min_t(__u8,
1685 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1686 req.max_cqe_version);
30aa60b3
EC		 1687 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1688 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1689 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1690 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1691 resp.response_length = min(offsetof(typeof(resp), response_length) +
1692 sizeof(resp.response_length), udata->outlen);
e126ba97 1693
c03faa56
MB		 1694 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1695 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1696 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1697 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1698 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1699 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1700 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1701 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1702 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1703 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1704 }
1705
e126ba97
EC		 1706 context = kzalloc(sizeof(*context), GFP_KERNEL);
1707 if (!context)
1708 return ERR_PTR(-ENOMEM);
1709
30aa60b3 1710 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1711 bfregi = &context->bfregi;
b037c29a
EC		 1712
1713 /* updates req->total_num_bfregs */
31a78a5a 1714 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1715 if (err)
e126ba97 1716 goto out_ctx;
e126ba97 1717
b037c29a
EC		 1718 mutex_init(&bfregi->lock);
1719 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1720 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1721 GFP_KERNEL);
b037c29a 1722 if (!bfregi->count) {
e126ba97 1723 err = -ENOMEM;
b037c29a 1724 goto out_ctx;
e126ba97
EC		 1725 }
1726
b037c29a
EC		 1727 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1728 sizeof(*bfregi->sys_pages),
1729 GFP_KERNEL);
1730 if (!bfregi->sys_pages) {
e126ba97 1731 err = -ENOMEM;
b037c29a 1732 goto out_count;
e126ba97
EC		 1733 }
1734
b037c29a
EC		 1735 err = allocate_uars(dev, context);
1736 if (err)
1737 goto out_sys_pages;
e126ba97 1738
b4cfe447
HE		 1739#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1740 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1741#endif
1742
146d2f1a 1743 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1744 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1745 if (err)
c44ef998 1746 goto out_uars;
146d2f1a 1747 }
1748
7c2344c3 1749 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1750 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1751 INIT_LIST_HEAD(&context->db_page_list);
1752 mutex_init(&context->db_page_mutex);
1753
2f5ff264 1754 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1755 resp.num_ports = dev->num_ports;
b368d7cb 1756
f72300c5
HA		 1757 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1758 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1759
402ca536 1760 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1761 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1762 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1763 resp.response_length += sizeof(resp.cmds_supp_uhw);
1764 }
1765
78984898
OG		 1766 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1767 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1768 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1769 resp.eth_min_inline++;
1770 }
1771 resp.response_length += sizeof(resp.eth_min_inline);
1772 }
1773
5c99eaec
FD		 1774 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1775 if (mdev->clock_info)
1776 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1777 resp.response_length += sizeof(resp.clock_info_versions);
1778 }
1779
bc5c6eed
NO		 1780 /*
1781 * We don't want to expose information from the PCI bar that is located
1782 * after 4096 bytes, so if the arch only supports larger pages, let's
1783 * pretend we don't support reading the HCA's core clock. This is also
1784 * forced by mmap function.
1785 */
de8d6e02
EC		 1786 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1787 if (PAGE_SIZE <= 4096) {
1788 resp.comp_mask |=
1789 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1790 resp.hca_core_clock_offset =
1791 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1792 }
5c99eaec 1793 resp.response_length += sizeof(resp.hca_core_clock_offset);
b368d7cb
MB		 1794 }
1795
30aa60b3
EC		 1796 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1797 resp.response_length += sizeof(resp.log_uar_size);
1798
1799 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1800 resp.response_length += sizeof(resp.num_uars_per_page);
1801
31a78a5a
YH		 1802 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1803 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1804 resp.response_length += sizeof(resp.num_dyn_bfregs);
1805 }
1806
b368d7cb 1807 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1808 if (err)
146d2f1a 1809 goto out_td;
e126ba97 1810
2f5ff264
EC		 1811 bfregi->ver = ver;
1812 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1813 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1814 context->lib_caps = req.lib_caps;
1815 print_lib_caps(dev, context->lib_caps);
f72300c5 1816
e126ba97
EC		 1817 return &context->ibucontext;
1818
146d2f1a 1819out_td:
1820 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1821 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1822
e126ba97 1823out_uars:
b037c29a 1824 deallocate_uars(dev, context);
e126ba97 1825
b037c29a
EC		 1826out_sys_pages:
1827 kfree(bfregi->sys_pages);
e126ba97 1828
b037c29a
EC		 1829out_count:
1830 kfree(bfregi->count);
e126ba97
EC		 1831
1832out_ctx:
1833 kfree(context);
b037c29a 1834
e126ba97
EC		 1835 return ERR_PTR(err);
1836}
1837
1838static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1839{
1840 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1841 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1842 struct mlx5_bfreg_info *bfregi;
e126ba97 1843
b037c29a 1844 bfregi = &context->bfregi;
146d2f1a 1845 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1846 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1847
b037c29a
EC		 1848 deallocate_uars(dev, context);
1849 kfree(bfregi->sys_pages);
2f5ff264 1850 kfree(bfregi->count);
e126ba97
EC		 1851 kfree(context);
1852
1853 return 0;
1854}
1855
b037c29a 1856static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1857 int uar_idx)
e126ba97 1858{
b037c29a
EC		 1859 int fw_uars_per_page;
1860
1861 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1862
4ed131d0 1863 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1864}
1865
1866static int get_command(unsigned long offset)
1867{
1868 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1869}
1870
1871static int get_arg(unsigned long offset)
1872{
1873 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1874}
1875
1876static int get_index(unsigned long offset)
1877{
1878 return get_arg(offset);
1879}
1880
4ed131d0
YH		 1881/* Index resides in an extra byte to enable larger values than 255 */
1882static int get_extended_index(unsigned long offset)
1883{
1884 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1885}
1886
7c2344c3
MG		 1887static void mlx5_ib_vma_open(struct vm_area_struct *area)
1888{
1889 /* vma_open is called when a new VMA is created on top of our VMA. This
1890 * is done through either mremap flow or split_vma (usually due to
1891 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1892 * as this VMA is strongly hardware related. Therefore we set the
1893 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1894 * calling us again and trying to do incorrect actions. We assume that
1895 * the original VMA size is exactly a single page, and therefore all
1896 * "splitting" operation will not happen to it.
1897 */
1898 area->vm_ops = NULL;
1899}
1900
1901static void mlx5_ib_vma_close(struct vm_area_struct *area)
1902{
1903 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1904
1905 /* It's guaranteed that all VMAs opened on a FD are closed before the
1906 * file itself is closed, therefore no sync is needed with the regular
1907 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1908 * However need a sync with accessing the vma as part of
1909 * mlx5_ib_disassociate_ucontext.
1910 * The close operation is usually called under mm->mmap_sem except when
1911 * process is exiting.
1912 * The exiting case is handled explicitly as part of
1913 * mlx5_ib_disassociate_ucontext.
1914 */
1915 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1916
1917 /* setting the vma context pointer to null in the mlx5_ib driver's
1918 * private data, to protect a race condition in
1919 * mlx5_ib_disassociate_ucontext().
1920 */
1921 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1922 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1923 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1924 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1925 kfree(mlx5_ib_vma_priv_data);
1926}
1927
1928static const struct vm_operations_struct mlx5_ib_vm_ops = {
1929 .open = mlx5_ib_vma_open,
1930 .close = mlx5_ib_vma_close
1931};
1932
1933static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1934 struct mlx5_ib_ucontext *ctx)
1935{
1936 struct mlx5_ib_vma_private_data *vma_prv;
1937 struct list_head *vma_head = &ctx->vma_private_list;
1938
1939 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1940 if (!vma_prv)
1941 return -ENOMEM;
1942
1943 vma_prv->vma = vma;
ad9a3668 1944 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1945 vma->vm_private_data = vma_prv;
1946 vma->vm_ops = &mlx5_ib_vm_ops;
1947
ad9a3668 1948 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1949 list_add(&vma_prv->list, vma_head);
ad9a3668 1950 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1951
1952 return 0;
1953}
1954
1955static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1956{
1957 int ret;
1958 struct vm_area_struct *vma;
1959 struct mlx5_ib_vma_private_data *vma_private, *n;
1960 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1961 struct task_struct *owning_process = NULL;
1962 struct mm_struct *owning_mm = NULL;
1963
1964 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1965 if (!owning_process)
1966 return;
1967
1968 owning_mm = get_task_mm(owning_process);
1969 if (!owning_mm) {
1970 pr_info("no mm, disassociate ucontext is pending task termination\n");
1971 while (1) {
1972 put_task_struct(owning_process);
1973 usleep_range(1000, 2000);
1974 owning_process = get_pid_task(ibcontext->tgid,
1975 PIDTYPE_PID);
1976 if (!owning_process ||
1977 owning_process->state == TASK_DEAD) {
1978 pr_info("disassociate ucontext done, task was terminated\n");
1979 /* in case task was dead need to release the
1980 * task struct.
1981 */
1982 if (owning_process)
1983 put_task_struct(owning_process);
1984 return;
1985 }
1986 }
1987 }
1988
1989 /* need to protect from a race on closing the vma as part of
1990 * mlx5_ib_vma_close.
1991 */
ecc7d83b 1992 down_write(&owning_mm->mmap_sem);
ad9a3668 1993 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1994 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1995 list) {
1996 vma = vma_private->vma;
1997 ret = zap_vma_ptes(vma, vma->vm_start,
1998 PAGE_SIZE);
1999 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
2000 /* context going to be destroyed, should
2001 * not access ops any more.
2002 */
13776612 2003 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 2004 vma->vm_ops = NULL;
2005 list_del(&vma_private->list);
2006 kfree(vma_private);
2007 }
ad9a3668 2008 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 2009 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 2010 mmput(owning_mm);
2011 put_task_struct(owning_process);
2012}
2013
37aa5c36
GL		 2014static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2015{
2016 switch (cmd) {
2017 case MLX5_IB_MMAP_WC_PAGE:
2018 return "WC";
2019 case MLX5_IB_MMAP_REGULAR_PAGE:
2020 return "best effort WC";
2021 case MLX5_IB_MMAP_NC_PAGE:
2022 return "NC";
24da0016
AL		 2023 case MLX5_IB_MMAP_DEVICE_MEM:
2024 return "Device Memory";
37aa5c36
GL		 2025 default:
2026 return NULL;
2027 }
2028}
2029
5c99eaec
FD		 2030static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2031 struct vm_area_struct *vma,
2032 struct mlx5_ib_ucontext *context)
2033{
2034 phys_addr_t pfn;
2035 int err;
2036
2037 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2038 return -EINVAL;
2039
2040 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2041 return -EOPNOTSUPP;
2042
2043 if (vma->vm_flags & VM_WRITE)
2044 return -EPERM;
2045
2046 if (!dev->mdev->clock_info_page)
2047 return -EOPNOTSUPP;
2048
2049 pfn = page_to_pfn(dev->mdev->clock_info_page);
2050 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2051 vma->vm_page_prot);
2052 if (err)
2053 return err;
2054
2055 mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2056 vma->vm_start,
2057 (unsigned long long)pfn << PAGE_SHIFT);
2058
2059 return mlx5_ib_set_vma_data(vma, context);
2060}
2061
37aa5c36 2062static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 2063 struct vm_area_struct *vma,
2064 struct mlx5_ib_ucontext *context)
37aa5c36 2065{
2f5ff264 2066 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 2067 int err;
2068 unsigned long idx;
2069 phys_addr_t pfn, pa;
2070 pgprot_t prot;
4ed131d0
YH		 2071 u32 bfreg_dyn_idx = 0;
2072 u32 uar_index;
2073 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2074 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2075 bfregi->num_static_sys_pages;
b037c29a
EC		 2076
2077 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2078 return -EINVAL;
2079
4ed131d0
YH		 2080 if (dyn_uar)
2081 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2082 else
2083 idx = get_index(vma->vm_pgoff);
2084
2085 if (idx >= max_valid_idx) {
2086 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2087 idx, max_valid_idx);
b037c29a
EC		 2088 return -EINVAL;
2089 }
37aa5c36
GL		 2090
2091 switch (cmd) {
2092 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 2093 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 2094/* Some architectures don't support WC memory */
2095#if defined(CONFIG_X86)
2096 if (!pat_enabled())
2097 return -EPERM;
2098#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2099 return -EPERM;
2100#endif
2101 /* fall through */
2102 case MLX5_IB_MMAP_REGULAR_PAGE:
2103 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2104 prot = pgprot_writecombine(vma->vm_page_prot);
2105 break;
2106 case MLX5_IB_MMAP_NC_PAGE:
2107 prot = pgprot_noncached(vma->vm_page_prot);
2108 break;
2109 default:
2110 return -EINVAL;
2111 }
2112
4ed131d0
YH		 2113 if (dyn_uar) {
2114 int uars_per_page;
2115
2116 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2117 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2118 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2119 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2120 bfreg_dyn_idx, bfregi->total_num_bfregs);
2121 return -EINVAL;
2122 }
2123
2124 mutex_lock(&bfregi->lock);
2125 /* Fail if uar already allocated, first bfreg index of each
2126 * page holds its count.
2127 */
2128 if (bfregi->count[bfreg_dyn_idx]) {
2129 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2130 mutex_unlock(&bfregi->lock);
2131 return -EINVAL;
2132 }
2133
2134 bfregi->count[bfreg_dyn_idx]++;
2135 mutex_unlock(&bfregi->lock);
2136
2137 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2138 if (err) {
2139 mlx5_ib_warn(dev, "UAR alloc failed\n");
2140 goto free_bfreg;
2141 }
2142 } else {
2143 uar_index = bfregi->sys_pages[idx];
2144 }
2145
2146 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 2147 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2148
2149 vma->vm_page_prot = prot;
2150 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2151 PAGE_SIZE, vma->vm_page_prot);
2152 if (err) {
2153 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2154 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
4ed131d0
YH		 2155 err = -EAGAIN;
2156 goto err;
37aa5c36
GL		 2157 }
2158
2159 pa = pfn << PAGE_SHIFT;
2160 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2161 vma->vm_start, &pa);
2162
4ed131d0
YH		 2163 err = mlx5_ib_set_vma_data(vma, context);
2164 if (err)
2165 goto err;
2166
2167 if (dyn_uar)
2168 bfregi->sys_pages[idx] = uar_index;
2169 return 0;
2170
2171err:
2172 if (!dyn_uar)
2173 return err;
2174
2175 mlx5_cmd_free_uar(dev->mdev, idx);
2176
2177free_bfreg:
2178 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2179
2180 return err;
37aa5c36
GL		 2181}
2182
24da0016
AL		 2183static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2184{
2185 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2186 struct mlx5_ib_dev *dev = to_mdev(context->device);
2187 u16 page_idx = get_extended_index(vma->vm_pgoff);
2188 size_t map_size = vma->vm_end - vma->vm_start;
2189 u32 npages = map_size >> PAGE_SHIFT;
2190 phys_addr_t pfn;
2191 pgprot_t prot;
2192
2193 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2194 page_idx + npages)
2195 return -EINVAL;
2196
2197 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2198 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2199 PAGE_SHIFT) +
2200 page_idx;
2201 prot = pgprot_writecombine(vma->vm_page_prot);
2202 vma->vm_page_prot = prot;
2203
2204 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2205 vma->vm_page_prot))
2206 return -EAGAIN;
2207
2208 return mlx5_ib_set_vma_data(vma, mctx);
2209}
2210
e126ba97
EC		 2211static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2212{
2213 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2214 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2215 unsigned long command;
e126ba97
EC		 2216 phys_addr_t pfn;
2217
2218 command = get_command(vma->vm_pgoff);
2219 switch (command) {
37aa5c36
GL		 2220 case MLX5_IB_MMAP_WC_PAGE:
2221 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2222 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2223 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2224 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2225
2226 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2227 return -ENOSYS;
2228
d69e3bcf 2229 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2230 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2231 return -EINVAL;
2232
6cbac1e4 2233 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2234 return -EPERM;
2235
2236 /* Don't expose to user-space information it shouldn't have */
2237 if (PAGE_SIZE > 4096)
2238 return -EOPNOTSUPP;
2239
2240 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2241 pfn = (dev->mdev->iseg_base +
2242 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2243 PAGE_SHIFT;
2244 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2245 PAGE_SIZE, vma->vm_page_prot))
2246 return -EAGAIN;
2247
2248 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2249 vma->vm_start,
2250 (unsigned long long)pfn << PAGE_SHIFT);
2251 break;
5c99eaec
FD		 2252 case MLX5_IB_MMAP_CLOCK_INFO:
2253 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
d69e3bcf 2254
24da0016
AL		 2255 case MLX5_IB_MMAP_DEVICE_MEM:
2256 return dm_mmap(ibcontext, vma);
2257
e126ba97
EC		 2258 default:
2259 return -EINVAL;
2260 }
2261
2262 return 0;
2263}
2264
24da0016
AL		 2265struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2266 struct ib_ucontext *context,
2267 struct ib_dm_alloc_attr *attr,
2268 struct uverbs_attr_bundle *attrs)
2269{
2270 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2271 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2272 phys_addr_t memic_addr;
2273 struct mlx5_ib_dm *dm;
2274 u64 start_offset;
2275 u32 page_idx;
2276 int err;
2277
2278 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2279 if (!dm)
2280 return ERR_PTR(-ENOMEM);
2281
2282 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2283 attr->length, act_size, attr->alignment);
2284
2285 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2286 act_size, attr->alignment);
2287 if (err)
2288 goto err_free;
2289
2290 start_offset = memic_addr & ~PAGE_MASK;
2291 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2292 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2293 PAGE_SHIFT;
2294
2295 err = uverbs_copy_to(attrs,
2296 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2297 &start_offset, sizeof(start_offset));
2298 if (err)
2299 goto err_dealloc;
2300
2301 err = uverbs_copy_to(attrs,
2302 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2303 &page_idx, sizeof(page_idx));
2304 if (err)
2305 goto err_dealloc;
2306
2307 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2308 DIV_ROUND_UP(act_size, PAGE_SIZE));
2309
2310 dm->dev_addr = memic_addr;
2311
2312 return &dm->ibdm;
2313
2314err_dealloc:
2315 mlx5_cmd_dealloc_memic(memic, memic_addr,
2316 act_size);
2317err_free:
2318 kfree(dm);
2319 return ERR_PTR(err);
2320}
2321
2322int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2323{
2324 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2325 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2326 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2327 u32 page_idx;
2328 int ret;
2329
2330 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2331 if (ret)
2332 return ret;
2333
2334 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2335 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2336 PAGE_SHIFT;
2337 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2338 page_idx,
2339 DIV_ROUND_UP(act_size, PAGE_SIZE));
2340
2341 kfree(dm);
2342
2343 return 0;
2344}
2345
e126ba97
EC		 2346static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2347 struct ib_ucontext *context,
2348 struct ib_udata *udata)
2349{
2350 struct mlx5_ib_alloc_pd_resp resp;
2351 struct mlx5_ib_pd *pd;
2352 int err;
2353
2354 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2355 if (!pd)
2356 return ERR_PTR(-ENOMEM);
2357
9603b61d 2358 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2359 if (err) {
2360 kfree(pd);
2361 return ERR_PTR(err);
2362 }
2363
2364 if (context) {
2365 resp.pdn = pd->pdn;
2366 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2367 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2368 kfree(pd);
2369 return ERR_PTR(-EFAULT);
2370 }
e126ba97
EC		 2371 }
2372
2373 return &pd->ibpd;
2374}
2375
2376static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2377{
2378 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2379 struct mlx5_ib_pd *mpd = to_mpd(pd);
2380
9603b61d 2381 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2382 kfree(mpd);
2383
2384 return 0;
2385}
2386
466fa6d2
MG		 2387enum {
2388 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2389 MATCH_CRITERIA_ENABLE_MISC_BIT,
2390 MATCH_CRITERIA_ENABLE_INNER_BIT
2391};
2392
2393#define HEADER_IS_ZERO(match_criteria, headers) \
2394 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2395 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2396
466fa6d2 2397static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2398{
466fa6d2 2399 u8 match_criteria_enable;
038d2ef8 2400
466fa6d2
MG		 2401 match_criteria_enable =
2402 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2403 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2404 match_criteria_enable |=
2405 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2406 MATCH_CRITERIA_ENABLE_MISC_BIT;
2407 match_criteria_enable |=
2408 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2409 MATCH_CRITERIA_ENABLE_INNER_BIT;
2410
2411 return match_criteria_enable;
038d2ef8
MG		 2412}
2413
ca0d4753
MG		 2414static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2415{
2416 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2417 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2418}
2419
2d1e697e
MR		 2420static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2421 bool inner)
2422{
2423 if (inner) {
2424 MLX5_SET(fte_match_set_misc,
2425 misc_c, inner_ipv6_flow_label, mask);
2426 MLX5_SET(fte_match_set_misc,
2427 misc_v, inner_ipv6_flow_label, val);
2428 } else {
2429 MLX5_SET(fte_match_set_misc,
2430 misc_c, outer_ipv6_flow_label, mask);
2431 MLX5_SET(fte_match_set_misc,
2432 misc_v, outer_ipv6_flow_label, val);
2433 }
2434}
2435
ca0d4753
MG		 2436static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2437{
2438 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2439 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2440 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2441 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2442}
2443
c47ac6ae
MG		 2444#define LAST_ETH_FIELD vlan_tag
2445#define LAST_IB_FIELD sl
ca0d4753 2446#define LAST_IPV4_FIELD tos
466fa6d2 2447#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2448#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2449#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2450#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2451#define LAST_DROP_FIELD size
c47ac6ae
MG		 2452
2453/* Field is the last supported field */
2454#define FIELDS_NOT_SUPPORTED(filter, field)\
2455 memchr_inv((void *)&filter.field +\
2456 sizeof(filter.field), 0,\
2457 sizeof(filter) -\
2458 offsetof(typeof(filter), field) -\
2459 sizeof(filter.field))
2460
802c2125
AY		 2461static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2462 const struct ib_flow_attr *flow_attr,
2463 struct mlx5_flow_act *action)
2464{
2465 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2466
2467 switch (maction->ib_action.type) {
2468 case IB_FLOW_ACTION_ESP:
2469 /* Currently only AES_GCM keymat is supported by the driver */
2470 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2471 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2472 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2473 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2474 return 0;
2475 default:
2476 return -EOPNOTSUPP;
2477 }
2478}
2479
19cc7524
AL		 2480static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2481 u32 *match_v, const union ib_flow_spec *ib_spec,
802c2125 2482 const struct ib_flow_attr *flow_attr,
075572d4 2483 struct mlx5_flow_act *action)
038d2ef8 2484{
466fa6d2
MG		 2485 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2486 misc_parameters);
2487 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2488 misc_parameters);
2d1e697e
MR		 2489 void *headers_c;
2490 void *headers_v;
19cc7524 2491 int match_ipv;
802c2125 2492 int ret;
2d1e697e
MR		 2493
2494 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2495 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2496 inner_headers);
2497 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2498 inner_headers);
19cc7524
AL		 2499 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2500 ft_field_support.inner_ip_version);
2d1e697e
MR		 2501 } else {
2502 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2503 outer_headers);
2504 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2505 outer_headers);
19cc7524
AL		 2506 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2507 ft_field_support.outer_ip_version);
2d1e697e 2508 }
466fa6d2 2509
2d1e697e 2510 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2511 case IB_FLOW_SPEC_ETH:
c47ac6ae 2512 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2513 return -EOPNOTSUPP;
038d2ef8 2514
2d1e697e 2515 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2516 dmac_47_16),
2517 ib_spec->eth.mask.dst_mac);
2d1e697e 2518 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2519 dmac_47_16),
2520 ib_spec->eth.val.dst_mac);
2521
2d1e697e 2522 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2523 smac_47_16),
2524 ib_spec->eth.mask.src_mac);
2d1e697e 2525 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2526 smac_47_16),
2527 ib_spec->eth.val.src_mac);
2528
038d2ef8 2529 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2530 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2531 cvlan_tag, 1);
2d1e697e 2532 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2533 cvlan_tag, 1);
038d2ef8 2534
2d1e697e 2535 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2536 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2537 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2538 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2539
2d1e697e 2540 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2541 first_cfi,
2542 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2543 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2544 first_cfi,
2545 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2546
2d1e697e 2547 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2548 first_prio,
2549 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2550 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2551 first_prio,
2552 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2553 }
2d1e697e 2554 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2555 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2556 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2557 ethertype, ntohs(ib_spec->eth.val.ether_type));
2558 break;
2559 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2560 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2561 return -EOPNOTSUPP;
038d2ef8 2562
19cc7524
AL		 2563 if (match_ipv) {
2564 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2565 ip_version, 0xf);
2566 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2567 ip_version, MLX5_FS_IPV4_VERSION);
19cc7524
AL		 2568 } else {
2569 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2570 ethertype, 0xffff);
2571 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2572 ethertype, ETH_P_IP);
2573 }
038d2ef8 2574
2d1e697e 2575 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2576 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2577 &ib_spec->ipv4.mask.src_ip,
2578 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2579 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2580 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2581 &ib_spec->ipv4.val.src_ip,
2582 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2583 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2584 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2585 &ib_spec->ipv4.mask.dst_ip,
2586 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2587 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2588 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2589 &ib_spec->ipv4.val.dst_ip,
2590 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2591
2d1e697e 2592 set_tos(headers_c, headers_v,
ca0d4753
MG		 2593 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2594
2d1e697e 2595 set_proto(headers_c, headers_v,
ca0d4753 2596 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2597 break;
026bae0c 2598 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2599 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2600 return -EOPNOTSUPP;
026bae0c 2601
19cc7524
AL		 2602 if (match_ipv) {
2603 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2604 ip_version, 0xf);
2605 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3346c487 2606 ip_version, MLX5_FS_IPV6_VERSION);
19cc7524
AL		 2607 } else {
2608 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2609 ethertype, 0xffff);
2610 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2611 ethertype, ETH_P_IPV6);
2612 }
026bae0c 2613
2d1e697e 2614 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2615 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2616 &ib_spec->ipv6.mask.src_ip,
2617 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2618 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2619 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2620 &ib_spec->ipv6.val.src_ip,
2621 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2622 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2623 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2624 &ib_spec->ipv6.mask.dst_ip,
2625 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2626 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2627 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2628 &ib_spec->ipv6.val.dst_ip,
2629 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2630
2d1e697e 2631 set_tos(headers_c, headers_v,
466fa6d2
MG		 2632 ib_spec->ipv6.mask.traffic_class,
2633 ib_spec->ipv6.val.traffic_class);
2634
2d1e697e 2635 set_proto(headers_c, headers_v,
466fa6d2
MG		 2636 ib_spec->ipv6.mask.next_hdr,
2637 ib_spec->ipv6.val.next_hdr);
2638
2d1e697e
MR		 2639 set_flow_label(misc_params_c, misc_params_v,
2640 ntohl(ib_spec->ipv6.mask.flow_label),
2641 ntohl(ib_spec->ipv6.val.flow_label),
2642 ib_spec->type & IB_FLOW_SPEC_INNER);
802c2125
AY		 2643 break;
2644 case IB_FLOW_SPEC_ESP:
2645 if (ib_spec->esp.mask.seq)
2646 return -EOPNOTSUPP;
2d1e697e 2647
802c2125
AY		 2648 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2649 ntohl(ib_spec->esp.mask.spi));
2650 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2651 ntohl(ib_spec->esp.val.spi));
026bae0c 2652 break;
038d2ef8 2653 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2654 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2655 LAST_TCP_UDP_FIELD))
1ffd3a26 2656 return -EOPNOTSUPP;
038d2ef8 2657
2d1e697e 2658 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2659 0xff);
2d1e697e 2660 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2661 IPPROTO_TCP);
2662
2d1e697e 2663 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2664 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2666 ntohs(ib_spec->tcp_udp.val.src_port));
2667
2d1e697e 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2669 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2671 ntohs(ib_spec->tcp_udp.val.dst_port));
2672 break;
2673 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2674 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2675 LAST_TCP_UDP_FIELD))
1ffd3a26 2676 return -EOPNOTSUPP;
038d2ef8 2677
2d1e697e 2678 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2679 0xff);
2d1e697e 2680 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2681 IPPROTO_UDP);
2682
2d1e697e 2683 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2684 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2685 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2686 ntohs(ib_spec->tcp_udp.val.src_port));
2687
2d1e697e 2688 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2689 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2691 ntohs(ib_spec->tcp_udp.val.dst_port));
2692 break;
ffb30d8f
MR		 2693 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2694 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2695 LAST_TUNNEL_FIELD))
1ffd3a26 2696 return -EOPNOTSUPP;
ffb30d8f
MR		 2697
2698 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2699 ntohl(ib_spec->tunnel.mask.tunnel_id));
2700 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2701 ntohl(ib_spec->tunnel.val.tunnel_id));
2702 break;
2ac693f9
MR		 2703 case IB_FLOW_SPEC_ACTION_TAG:
2704 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2705 LAST_FLOW_TAG_FIELD))
2706 return -EOPNOTSUPP;
2707 if (ib_spec->flow_tag.tag_id >= BIT(24))
2708 return -EINVAL;
2709
075572d4 2710 action->flow_tag = ib_spec->flow_tag.tag_id;
a9db0ecf 2711 action->has_flow_tag = true;
2ac693f9 2712 break;
a22ed86c
SS		 2713 case IB_FLOW_SPEC_ACTION_DROP:
2714 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2715 LAST_DROP_FIELD))
2716 return -EOPNOTSUPP;
075572d4 2717 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
a22ed86c 2718 break;
802c2125
AY		 2719 case IB_FLOW_SPEC_ACTION_HANDLE:
2720 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2721 if (ret)
2722 return ret;
2723 break;
038d2ef8
MG		 2724 default:
2725 return -EINVAL;
2726 }
2727
2728 return 0;
2729}
2730
2731/* If a flow could catch both multicast and unicast packets,
2732 * it won't fall into the multicast flow steering table and this rule
2733 * could steal other multicast packets.
2734 */
a550ddfc 2735static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2736{
81e30880 2737 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2738
2739 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2740 ib_attr->num_of_specs < 1)
2741 return false;
2742
81e30880
YH		 2743 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2744 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2745 struct ib_flow_spec_ipv4 *ipv4_spec;
2746
2747 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2748 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2749 return true;
2750
038d2ef8 2751 return false;
81e30880
YH		 2752 }
2753
2754 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2755 struct ib_flow_spec_eth *eth_spec;
2756
2757 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2758 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2759 is_multicast_ether_addr(eth_spec->val.dst_mac);
2760 }
038d2ef8 2761
81e30880 2762 return false;
038d2ef8
MG		 2763}
2764
802c2125
AY		 2765enum valid_spec {
2766 VALID_SPEC_INVALID,
2767 VALID_SPEC_VALID,
2768 VALID_SPEC_NA,
2769};
2770
2771static enum valid_spec
2772is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2773 const struct mlx5_flow_spec *spec,
2774 const struct mlx5_flow_act *flow_act,
2775 bool egress)
2776{
2777 const u32 *match_c = spec->match_criteria;
2778 bool is_crypto =
2779 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2780 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2781 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2782 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2783
2784 /*
2785 * Currently only crypto is supported in egress, when regular egress
2786 * rules would be supported, always return VALID_SPEC_NA.
2787 */
2788 if (!is_crypto)
2789 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2790
2791 return is_crypto && is_ipsec &&
2792 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2793 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2794}
2795
2796static bool is_valid_spec(struct mlx5_core_dev *mdev,
2797 const struct mlx5_flow_spec *spec,
2798 const struct mlx5_flow_act *flow_act,
2799 bool egress)
2800{
2801 /* We curretly only support ipsec egress flow */
2802 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2803}
2804
19cc7524
AL		 2805static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2806 const struct ib_flow_attr *flow_attr,
0f750966 2807 bool check_inner)
038d2ef8
MG		 2808{
2809 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2810 int match_ipv = check_inner ?
2811 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2812 ft_field_support.inner_ip_version) :
2813 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2814 ft_field_support.outer_ip_version);
0f750966
AL		 2815 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2816 bool ipv4_spec_valid, ipv6_spec_valid;
2817 unsigned int ip_spec_type = 0;
2818 bool has_ethertype = false;
038d2ef8 2819 unsigned int spec_index;
0f750966
AL		 2820 bool mask_valid = true;
2821 u16 eth_type = 0;
2822 bool type_valid;
038d2ef8
MG		 2823
2824 /* Validate that ethertype is correct */
2825 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2826 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2827 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2828 mask_valid = (ib_spec->eth.mask.ether_type ==
2829 htons(0xffff));
2830 has_ethertype = true;
2831 eth_type = ntohs(ib_spec->eth.val.ether_type);
2832 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2833 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2834 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2835 }
2836 ib_spec = (void *)ib_spec + ib_spec->size;
2837 }
0f750966
AL		 2838
2839 type_valid = (!has_ethertype) || (!ip_spec_type);
2840 if (!type_valid && mask_valid) {
2841 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2842 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2843 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2844 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2845
2846 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2847 (((eth_type == ETH_P_MPLS_UC) ||
2848 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2849 }
2850
2851 return type_valid;
2852}
2853
19cc7524
AL		 2854static bool is_valid_attr(struct mlx5_core_dev *mdev,
2855 const struct ib_flow_attr *flow_attr)
0f750966 2856{
19cc7524
AL		 2857 return is_valid_ethertype(mdev, flow_attr, false) &&
2858 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2859}
2860
2861static void put_flow_table(struct mlx5_ib_dev *dev,
2862 struct mlx5_ib_flow_prio *prio, bool ft_added)
2863{
2864 prio->refcount -= !!ft_added;
2865 if (!prio->refcount) {
2866 mlx5_destroy_flow_table(prio->flow_table);
2867 prio->flow_table = NULL;
2868 }
2869}
2870
2871static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2872{
2873 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2874 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2875 struct mlx5_ib_flow_handler,
2876 ibflow);
2877 struct mlx5_ib_flow_handler *iter, *tmp;
2878
9a4ca38d 2879 mutex_lock(&dev->flow_db->lock);
038d2ef8
MG		 2880
2881 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2882 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2883 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2884 list_del(&iter->list);
2885 kfree(iter);
2886 }
2887
74491de9 2888 mlx5_del_flow_rules(handler->rule);
5497adc6 2889 put_flow_table(dev, handler->prio, true);
9a4ca38d 2890 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 2891
2892 kfree(handler);
2893
2894 return 0;
2895}
2896
35d19011
MG		 2897static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2898{
2899 priority *= 2;
2900 if (!dont_trap)
2901 priority++;
2902 return priority;
2903}
2904
cc0e5d42
MG		 2905enum flow_table_type {
2906 MLX5_IB_FT_RX,
2907 MLX5_IB_FT_TX
2908};
2909
00b7c2ab
MG		 2910#define MLX5_FS_MAX_TYPES 6
2911#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2912static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2913 struct ib_flow_attr *flow_attr,
2914 enum flow_table_type ft_type)
038d2ef8 2915{
35d19011 2916 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2917 struct mlx5_flow_namespace *ns = NULL;
2918 struct mlx5_ib_flow_prio *prio;
2919 struct mlx5_flow_table *ft;
dac388ef 2920 int max_table_size;
038d2ef8
MG		 2921 int num_entries;
2922 int num_groups;
2923 int priority;
2924 int err = 0;
2925
dac388ef
MG		 2926 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2927 log_max_ft_size));
038d2ef8 2928 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
802c2125
AY		 2929 if (ft_type == MLX5_IB_FT_TX)
2930 priority = 0;
2931 else if (flow_is_multicast_only(flow_attr) &&
2932 !dont_trap)
038d2ef8
MG		 2933 priority = MLX5_IB_FLOW_MCAST_PRIO;
2934 else
35d19011
MG		 2935 priority = ib_prio_to_core_prio(flow_attr->priority,
2936 dont_trap);
038d2ef8 2937 ns = mlx5_get_flow_namespace(dev->mdev,
802c2125
AY		 2938 ft_type == MLX5_IB_FT_TX ?
2939 MLX5_FLOW_NAMESPACE_EGRESS :
038d2ef8
MG		 2940 MLX5_FLOW_NAMESPACE_BYPASS);
2941 num_entries = MLX5_FS_MAX_ENTRIES;
2942 num_groups = MLX5_FS_MAX_TYPES;
9a4ca38d 2943 prio = &dev->flow_db->prios[priority];
038d2ef8
MG		 2944 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2945 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2946 ns = mlx5_get_flow_namespace(dev->mdev,
2947 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2948 build_leftovers_ft_param(&priority,
2949 &num_entries,
2950 &num_groups);
9a4ca38d 2951 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2952 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2953 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2954 allow_sniffer_and_nic_rx_shared_tir))
2955 return ERR_PTR(-ENOTSUPP);
2956
2957 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2958 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2959 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2960
9a4ca38d 2961 prio = &dev->flow_db->sniffer[ft_type];
cc0e5d42
MG		 2962 priority = 0;
2963 num_entries = 1;
2964 num_groups = 1;
038d2ef8
MG		 2965 }
2966
2967 if (!ns)
2968 return ERR_PTR(-ENOTSUPP);
2969
dac388ef
MG		 2970 if (num_entries > max_table_size)
2971 return ERR_PTR(-ENOMEM);
2972
038d2ef8
MG		 2973 ft = prio->flow_table;
2974 if (!ft) {
2975 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2976 num_entries,
d63cd286 2977 num_groups,
c9f1b073 2978 0, 0);
038d2ef8
MG		 2979
2980 if (!IS_ERR(ft)) {
2981 prio->refcount = 0;
2982 prio->flow_table = ft;
2983 } else {
2984 err = PTR_ERR(ft);
2985 }
2986 }
2987
2988 return err ? ERR_PTR(err) : prio;
2989}
2990
a550ddfc
YH		 2991static void set_underlay_qp(struct mlx5_ib_dev *dev,
2992 struct mlx5_flow_spec *spec,
2993 u32 underlay_qpn)
2994{
2995 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2996 spec->match_criteria,
2997 misc_parameters);
2998 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2999 misc_parameters);
3000
3001 if (underlay_qpn &&
3002 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3003 ft_field_support.bth_dst_qp)) {
3004 MLX5_SET(fte_match_set_misc,
3005 misc_params_v, bth_dst_qp, underlay_qpn);
3006 MLX5_SET(fte_match_set_misc,
3007 misc_params_c, bth_dst_qp, 0xffffff);
3008 }
3009}
3010
3011static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3012 struct mlx5_ib_flow_prio *ft_prio,
3013 const struct ib_flow_attr *flow_attr,
3014 struct mlx5_flow_destination *dst,
3015 u32 underlay_qpn)
038d2ef8
MG		 3016{
3017 struct mlx5_flow_table *ft = ft_prio->flow_table;
3018 struct mlx5_ib_flow_handler *handler;
075572d4 3019 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
c5bb1730 3020 struct mlx5_flow_spec *spec;
a22ed86c 3021 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 3022 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 3023 unsigned int spec_index;
038d2ef8 3024 int err = 0;
a22ed86c 3025 int dest_num = 1;
802c2125 3026 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3027
19cc7524 3028 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 3029 return ERR_PTR(-EINVAL);
3030
1b9a07ee 3031 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 3032 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 3033 if (!handler || !spec) {
038d2ef8
MG		 3034 err = -ENOMEM;
3035 goto free;
3036 }
3037
3038 INIT_LIST_HEAD(&handler->list);
3039
3040 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 3041 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c 3042 spec->match_value,
802c2125 3043 ib_flow, flow_attr, &flow_act);
038d2ef8
MG		 3044 if (err < 0)
3045 goto free;
3046
3047 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3048 }
3049
a550ddfc
YH		 3050 if (!flow_is_multicast_only(flow_attr))
3051 set_underlay_qp(dev, spec, underlay_qpn);
3052
018a94ee
MB		 3053 if (dev->rep) {
3054 void *misc;
3055
3056 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3057 misc_parameters);
3058 MLX5_SET(fte_match_set_misc, misc, source_port,
3059 dev->rep->vport);
3060 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3061 misc_parameters);
3062 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3063 }
3064
466fa6d2 3065 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
802c2125
AY		 3066
3067 if (is_egress &&
3068 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3069 err = -EINVAL;
3070 goto free;
3071 }
3072
075572d4 3073 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
a22ed86c
SS		 3074 rule_dst = NULL;
3075 dest_num = 0;
3076 } else {
802c2125
AY		 3077 if (is_egress)
3078 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3079 else
3080 flow_act.action |=
3081 dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3082 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
a22ed86c 3083 }
2ac693f9 3084
a9db0ecf 3085 if (flow_act.has_flow_tag &&
2ac693f9
MR		 3086 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3087 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3088 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
075572d4 3089 flow_act.flow_tag, flow_attr->type);
2ac693f9
MR		 3090 err = -EINVAL;
3091 goto free;
3092 }
74491de9 3093 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 3094 &flow_act,
a22ed86c 3095 rule_dst, dest_num);
038d2ef8
MG		 3096
3097 if (IS_ERR(handler->rule)) {
3098 err = PTR_ERR(handler->rule);
3099 goto free;
3100 }
3101
d9d4980a 3102 ft_prio->refcount++;
5497adc6 3103 handler->prio = ft_prio;
038d2ef8
MG		 3104
3105 ft_prio->flow_table = ft;
3106free:
3107 if (err)
3108 kfree(handler);
c5bb1730 3109 kvfree(spec);
038d2ef8
MG		 3110 return err ? ERR_PTR(err) : handler;
3111}
3112
a550ddfc
YH		 3113static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3114 struct mlx5_ib_flow_prio *ft_prio,
3115 const struct ib_flow_attr *flow_attr,
3116 struct mlx5_flow_destination *dst)
3117{
3118 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
3119}
3120
35d19011
MG		 3121static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3122 struct mlx5_ib_flow_prio *ft_prio,
3123 struct ib_flow_attr *flow_attr,
3124 struct mlx5_flow_destination *dst)
3125{
3126 struct mlx5_ib_flow_handler *handler_dst = NULL;
3127 struct mlx5_ib_flow_handler *handler = NULL;
3128
3129 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3130 if (!IS_ERR(handler)) {
3131 handler_dst = create_flow_rule(dev, ft_prio,
3132 flow_attr, dst);
3133 if (IS_ERR(handler_dst)) {
74491de9 3134 mlx5_del_flow_rules(handler->rule);
d9d4980a 3135 ft_prio->refcount--;
35d19011
MG		 3136 kfree(handler);
3137 handler = handler_dst;
3138 } else {
3139 list_add(&handler_dst->list, &handler->list);
3140 }
3141 }
3142
3143 return handler;
3144}
038d2ef8
MG		 3145enum {
3146 LEFTOVERS_MC,
3147 LEFTOVERS_UC,
3148};
3149
3150static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3151 struct mlx5_ib_flow_prio *ft_prio,
3152 struct ib_flow_attr *flow_attr,
3153 struct mlx5_flow_destination *dst)
3154{
3155 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3156 struct mlx5_ib_flow_handler *handler = NULL;
3157
3158 static struct {
3159 struct ib_flow_attr flow_attr;
3160 struct ib_flow_spec_eth eth_flow;
3161 } leftovers_specs[] = {
3162 [LEFTOVERS_MC] = {
3163 .flow_attr = {
3164 .num_of_specs = 1,
3165 .size = sizeof(leftovers_specs[0])
3166 },
3167 .eth_flow = {
3168 .type = IB_FLOW_SPEC_ETH,
3169 .size = sizeof(struct ib_flow_spec_eth),
3170 .mask = {.dst_mac = {0x1} },
3171 .val = {.dst_mac = {0x1} }
3172 }
3173 },
3174 [LEFTOVERS_UC] = {
3175 .flow_attr = {
3176 .num_of_specs = 1,
3177 .size = sizeof(leftovers_specs[0])
3178 },
3179 .eth_flow = {
3180 .type = IB_FLOW_SPEC_ETH,
3181 .size = sizeof(struct ib_flow_spec_eth),
3182 .mask = {.dst_mac = {0x1} },
3183 .val = {.dst_mac = {} }
3184 }
3185 }
3186 };
3187
3188 handler = create_flow_rule(dev, ft_prio,
3189 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3190 dst);
3191 if (!IS_ERR(handler) &&
3192 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3193 handler_ucast = create_flow_rule(dev, ft_prio,
3194 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3195 dst);
3196 if (IS_ERR(handler_ucast)) {
74491de9 3197 mlx5_del_flow_rules(handler->rule);
d9d4980a 3198 ft_prio->refcount--;
038d2ef8
MG		 3199 kfree(handler);
3200 handler = handler_ucast;
3201 } else {
3202 list_add(&handler_ucast->list, &handler->list);
3203 }
3204 }
3205
3206 return handler;
3207}
3208
cc0e5d42
MG		 3209static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3210 struct mlx5_ib_flow_prio *ft_rx,
3211 struct mlx5_ib_flow_prio *ft_tx,
3212 struct mlx5_flow_destination *dst)
3213{
3214 struct mlx5_ib_flow_handler *handler_rx;
3215 struct mlx5_ib_flow_handler *handler_tx;
3216 int err;
3217 static const struct ib_flow_attr flow_attr = {
3218 .num_of_specs = 0,
3219 .size = sizeof(flow_attr)
3220 };
3221
3222 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3223 if (IS_ERR(handler_rx)) {
3224 err = PTR_ERR(handler_rx);
3225 goto err;
3226 }
3227
3228 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3229 if (IS_ERR(handler_tx)) {
3230 err = PTR_ERR(handler_tx);
3231 goto err_tx;
3232 }
3233
3234 list_add(&handler_tx->list, &handler_rx->list);
3235
3236 return handler_rx;
3237
3238err_tx:
74491de9 3239 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 3240 ft_rx->refcount--;
3241 kfree(handler_rx);
3242err:
3243 return ERR_PTR(err);
3244}
3245
038d2ef8
MG		 3246static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3247 struct ib_flow_attr *flow_attr,
3248 int domain)
3249{
3250 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 3251 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 3252 struct mlx5_ib_flow_handler *handler = NULL;
3253 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 3254 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8 3255 struct mlx5_ib_flow_prio *ft_prio;
802c2125 3256 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
038d2ef8 3257 int err;
a550ddfc 3258 int underlay_qpn;
038d2ef8
MG		 3259
3260 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 3261 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 3262
3263 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 3264 flow_attr->port > dev->num_ports ||
802c2125
AY		 3265 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3266 IB_FLOW_ATTR_FLAGS_EGRESS)))
3267 return ERR_PTR(-EINVAL);
3268
3269 if (is_egress &&
3270 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3271 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
038d2ef8
MG		 3272 return ERR_PTR(-EINVAL);
3273
3274 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3275 if (!dst)
3276 return ERR_PTR(-ENOMEM);
3277
9a4ca38d 3278 mutex_lock(&dev->flow_db->lock);
038d2ef8 3279
802c2125
AY		 3280 ft_prio = get_flow_table(dev, flow_attr,
3281 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
038d2ef8
MG		 3282 if (IS_ERR(ft_prio)) {
3283 err = PTR_ERR(ft_prio);
3284 goto unlock;
3285 }
cc0e5d42
MG		 3286 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3287 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3288 if (IS_ERR(ft_prio_tx)) {
3289 err = PTR_ERR(ft_prio_tx);
3290 ft_prio_tx = NULL;
3291 goto destroy_ft;
3292 }
3293 }
038d2ef8 3294
802c2125
AY		 3295 if (is_egress) {
3296 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3297 } else {
3298 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3299 if (mqp->flags & MLX5_IB_QP_RSS)
3300 dst->tir_num = mqp->rss_qp.tirn;
3301 else
3302 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3303 }
038d2ef8
MG		 3304
3305 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 3306 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3307 handler = create_dont_trap_rule(dev, ft_prio,
3308 flow_attr, dst);
3309 } else {
a550ddfc
YH		 3310 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3311 mqp->underlay_qpn : 0;
3312 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3313 dst, underlay_qpn);
35d19011 3314 }
038d2ef8
MG		 3315 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3316 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3317 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3318 dst);
cc0e5d42
MG		 3319 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3320 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 3321 } else {
3322 err = -EINVAL;
3323 goto destroy_ft;
3324 }
3325
3326 if (IS_ERR(handler)) {
3327 err = PTR_ERR(handler);
3328 handler = NULL;
3329 goto destroy_ft;
3330 }
3331
9a4ca38d 3332 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3333 kfree(dst);
3334
3335 return &handler->ibflow;
3336
3337destroy_ft:
3338 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 3339 if (ft_prio_tx)
3340 put_flow_table(dev, ft_prio_tx, false);
038d2ef8 3341unlock:
9a4ca38d 3342 mutex_unlock(&dev->flow_db->lock);
038d2ef8
MG		 3343 kfree(dst);
3344 kfree(handler);
3345 return ERR_PTR(err);
3346}
3347
c6475a0b
AY		 3348static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3349{
3350 u32 flags = 0;
3351
3352 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3353 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3354
3355 return flags;
3356}
3357
3358#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3359static struct ib_flow_action *
3360mlx5_ib_create_flow_action_esp(struct ib_device *device,
3361 const struct ib_flow_action_attrs_esp *attr,
3362 struct uverbs_attr_bundle *attrs)
3363{
3364 struct mlx5_ib_dev *mdev = to_mdev(device);
3365 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3366 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3367 struct mlx5_ib_flow_action *action;
3368 u64 action_flags;
3369 u64 flags;
3370 int err = 0;
3371
3372 if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3373 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3374 return ERR_PTR(-EFAULT);
3375
3376 if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3377 return ERR_PTR(-EOPNOTSUPP);
3378
3379 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3380
3381 /* We current only support a subset of the standard features. Only a
3382 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3383 * (with overlap). Full offload mode isn't supported.
3384 */
3385 if (!attr->keymat || attr->replay || attr->encap ||
3386 attr->spi || attr->seq || attr->tfc_pad ||
3387 attr->hard_limit_pkts ||
3388 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3389 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3390 return ERR_PTR(-EOPNOTSUPP);
3391
3392 if (attr->keymat->protocol !=
3393 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3394 return ERR_PTR(-EOPNOTSUPP);
3395
3396 aes_gcm = &attr->keymat->keymat.aes_gcm;
3397
3398 if (aes_gcm->icv_len != 16 ||
3399 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3400 return ERR_PTR(-EOPNOTSUPP);
3401
3402 action = kmalloc(sizeof(*action), GFP_KERNEL);
3403 if (!action)
3404 return ERR_PTR(-ENOMEM);
3405
3406 action->esp_aes_gcm.ib_flags = attr->flags;
3407 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3408 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3409 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3410 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3411 sizeof(accel_attrs.keymat.aes_gcm.salt));
3412 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3413 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3414 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3415 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3416 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3417
3418 accel_attrs.esn = attr->esn;
3419 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3420 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3421 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3422 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3423
3424 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3425 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3426
3427 action->esp_aes_gcm.ctx =
3428 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3429 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3430 err = PTR_ERR(action->esp_aes_gcm.ctx);
3431 goto err_parse;
3432 }
3433
3434 action->esp_aes_gcm.ib_flags = attr->flags;
3435
3436 return &action->ib_action;
3437
3438err_parse:
3439 kfree(action);
3440 return ERR_PTR(err);
3441}
3442
349705c1
MB		 3443static int
3444mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3445 const struct ib_flow_action_attrs_esp *attr,
3446 struct uverbs_attr_bundle *attrs)
3447{
3448 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3449 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3450 int err = 0;
3451
3452 if (attr->keymat || attr->replay || attr->encap ||
3453 attr->spi || attr->seq || attr->tfc_pad ||
3454 attr->hard_limit_pkts ||
3455 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3456 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3457 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3458 return -EOPNOTSUPP;
3459
3460 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3461 * be modified.
3462 */
3463 if (!(maction->esp_aes_gcm.ib_flags &
3464 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3465 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3466 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3467 return -EINVAL;
3468
3469 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3470 sizeof(accel_attrs));
3471
3472 accel_attrs.esn = attr->esn;
3473 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3474 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3475 else
3476 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3477
3478 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3479 &accel_attrs);
3480 if (err)
3481 return err;
3482
3483 maction->esp_aes_gcm.ib_flags &=
3484 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3485 maction->esp_aes_gcm.ib_flags |=
3486 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3487
3488 return 0;
3489}
3490
c6475a0b
AY		 3491static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3492{
3493 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3494
3495 switch (action->type) {
3496 case IB_FLOW_ACTION_ESP:
3497 /*
3498 * We only support aes_gcm by now, so we implicitly know this is
3499 * the underline crypto.
3500 */
3501 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3502 break;
3503 default:
3504 WARN_ON(true);
3505 break;
3506 }
3507
3508 kfree(maction);
3509 return 0;
3510}
3511
e126ba97
EC		 3512static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3513{
3514 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 3515 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 3516 int err;
3517
81e30880
YH		 3518 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3519 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3520 return -EOPNOTSUPP;
3521 }
3522
9603b61d 3523 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3524 if (err)
3525 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3526 ibqp->qp_num, gid->raw);
3527
3528 return err;
3529}
3530
3531static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3532{
3533 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3534 int err;
3535
9603b61d 3536 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 3537 if (err)
3538 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3539 ibqp->qp_num, gid->raw);
3540
3541 return err;
3542}
3543
3544static int init_node_data(struct mlx5_ib_dev *dev)
3545{
1b5daf11 3546 int err;
e126ba97 3547
1b5daf11 3548 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 3549 if (err)
1b5daf11 3550 return err;
e126ba97 3551
1b5daf11 3552 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 3553
1b5daf11 3554 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 3555}
3556
3557static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3558 char *buf)
3559{
3560 struct mlx5_ib_dev *dev =
3561 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3562
9603b61d 3563 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 3564}
3565
3566static ssize_t show_reg_pages(struct device *device,
3567 struct device_attribute *attr, char *buf)
3568{
3569 struct mlx5_ib_dev *dev =
3570 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3571
6aec21f6 3572 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3573}
3574
3575static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3576 char *buf)
3577{
3578 struct mlx5_ib_dev *dev =
3579 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3580 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3581}
3582
e126ba97
EC		 3583static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3584 char *buf)
3585{
3586 struct mlx5_ib_dev *dev =
3587 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3588 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3589}
3590
3591static ssize_t show_board(struct device *device, struct device_attribute *attr,
3592 char *buf)
3593{
3594 struct mlx5_ib_dev *dev =
3595 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3596 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3597 dev->mdev->board_id);
e126ba97
EC		 3598}
3599
3600static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3601static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3602static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3603static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3604static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3605
3606static struct device_attribute *mlx5_class_attributes[] = {
3607 &dev_attr_hw_rev,
e126ba97
EC		 3608 &dev_attr_hca_type,
3609 &dev_attr_board_id,
3610 &dev_attr_fw_pages,
3611 &dev_attr_reg_pages,
3612};
3613
7722f47e
HE		 3614static void pkey_change_handler(struct work_struct *work)
3615{
3616 struct mlx5_ib_port_resources *ports =
3617 container_of(work, struct mlx5_ib_port_resources,
3618 pkey_change_work);
3619
3620 mutex_lock(&ports->devr->mutex);
3621 mlx5_ib_gsi_pkey_change(ports->gsi);
3622 mutex_unlock(&ports->devr->mutex);
3623}
3624
89ea94a7
MG		 3625static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3626{
3627 struct mlx5_ib_qp *mqp;
3628 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3629 struct mlx5_core_cq *mcq;
3630 struct list_head cq_armed_list;
3631 unsigned long flags_qp;
3632 unsigned long flags_cq;
3633 unsigned long flags;
3634
3635 INIT_LIST_HEAD(&cq_armed_list);
3636
3637 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3638 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3639 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3640 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3641 if (mqp->sq.tail != mqp->sq.head) {
3642 send_mcq = to_mcq(mqp->ibqp.send_cq);
3643 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3644 if (send_mcq->mcq.comp &&
3645 mqp->ibqp.send_cq->comp_handler) {
3646 if (!send_mcq->mcq.reset_notify_added) {
3647 send_mcq->mcq.reset_notify_added = 1;
3648 list_add_tail(&send_mcq->mcq.reset_notify,
3649 &cq_armed_list);
3650 }
3651 }
3652 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3653 }
3654 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3655 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3656 /* no handling is needed for SRQ */
3657 if (!mqp->ibqp.srq) {
3658 if (mqp->rq.tail != mqp->rq.head) {
3659 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3660 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3661 if (recv_mcq->mcq.comp &&
3662 mqp->ibqp.recv_cq->comp_handler) {
3663 if (!recv_mcq->mcq.reset_notify_added) {
3664 recv_mcq->mcq.reset_notify_added = 1;
3665 list_add_tail(&recv_mcq->mcq.reset_notify,
3666 &cq_armed_list);
3667 }
3668 }
3669 spin_unlock_irqrestore(&recv_mcq->lock,
3670 flags_cq);
3671 }
3672 }
3673 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3674 }
3675 /*At that point all inflight post send were put to be executed as of we
3676 * lock/unlock above locks Now need to arm all involved CQs.
3677 */
3678 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3679 mcq->comp(mcq);
3680 }
3681 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3682}
3683
03404e8a
MG		 3684static void delay_drop_handler(struct work_struct *work)
3685{
3686 int err;
3687 struct mlx5_ib_delay_drop *delay_drop =
3688 container_of(work, struct mlx5_ib_delay_drop,
3689 delay_drop_work);
3690
fe248c3a
MG		 3691 atomic_inc(&delay_drop->events_cnt);
3692
03404e8a
MG		 3693 mutex_lock(&delay_drop->lock);
3694 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3695 delay_drop->timeout);
3696 if (err) {
3697 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3698 delay_drop->timeout);
3699 delay_drop->activate = false;
3700 }
3701 mutex_unlock(&delay_drop->lock);
3702}
3703
d69a24e0 3704static void mlx5_ib_handle_event(struct work_struct *_work)
e126ba97 3705{
d69a24e0
DJ		 3706 struct mlx5_ib_event_work *work =
3707 container_of(_work, struct mlx5_ib_event_work, work);
3708 struct mlx5_ib_dev *ibdev;
e126ba97 3709 struct ib_event ibev;
dbaaff2a 3710 bool fatal = false;
aba46213 3711 u8 port = (u8)work->param;
e126ba97 3712
d69a24e0
DJ		 3713 if (mlx5_core_is_mp_slave(work->dev)) {
3714 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3715 if (!ibdev)
3716 goto out;
3717 } else {
3718 ibdev = work->context;
3719 }
3720
3721 switch (work->event) {
e126ba97 3722 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 3723 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 3724 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 3725 fatal = true;
e126ba97
EC		 3726 break;
3727
3728 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 3729 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 3730 case MLX5_DEV_EVENT_PORT_INITIALIZED:
5ec8c83e
AH		 3731 /* In RoCE, port up/down events are handled in
3732 * mlx5_netdev_event().
3733 */
3734 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3735 IB_LINK_LAYER_ETHERNET)
d69a24e0 3736 goto out;
5ec8c83e 3737
d69a24e0 3738 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
5ec8c83e 3739 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 3740 break;
3741
e126ba97
EC		 3742 case MLX5_DEV_EVENT_LID_CHANGE:
3743 ibev.event = IB_EVENT_LID_CHANGE;
e126ba97
EC		 3744 break;
3745
3746 case MLX5_DEV_EVENT_PKEY_CHANGE:
3747 ibev.event = IB_EVENT_PKEY_CHANGE;
7722f47e 3748 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 3749 break;
3750
3751 case MLX5_DEV_EVENT_GUID_CHANGE:
3752 ibev.event = IB_EVENT_GID_CHANGE;
e126ba97
EC		 3753 break;
3754
3755 case MLX5_DEV_EVENT_CLIENT_REREG:
3756 ibev.event = IB_EVENT_CLIENT_REREGISTER;
e126ba97 3757 break;
03404e8a
MG		 3758 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3759 schedule_work(&ibdev->delay_drop.delay_drop_work);
3760 goto out;
bdc37924 3761 default:
03404e8a 3762 goto out;
e126ba97
EC		 3763 }
3764
3765 ibev.device = &ibdev->ib_dev;
3766 ibev.element.port_num = port;
3767
aba46213 3768 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
a0c84c32 3769 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 3770 goto out;
a0c84c32
EC		 3771 }
3772
e126ba97
EC		 3773 if (ibdev->ib_active)
3774 ib_dispatch_event(&ibev);
dbaaff2a
EC		 3775
3776 if (fatal)
3777 ibdev->ib_active = false;
03404e8a 3778out:
d69a24e0
DJ		 3779 kfree(work);
3780}
3781
3782static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3783 enum mlx5_dev_event event, unsigned long param)
3784{
3785 struct mlx5_ib_event_work *work;
3786
3787 work = kmalloc(sizeof(*work), GFP_ATOMIC);
10bea9c8 3788 if (!work)
d69a24e0 3789 return;
d69a24e0 3790
10bea9c8
LR		 3791 INIT_WORK(&work->work, mlx5_ib_handle_event);
3792 work->dev = dev;
3793 work->param = param;
3794 work->context = context;
3795 work->event = event;
3796
3797 queue_work(mlx5_ib_event_wq, &work->work);
e126ba97
EC		 3798}
3799
c43f1112
MG		 3800static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3801{
3802 struct mlx5_hca_vport_context vport_ctx;
3803 int err;
3804 int port;
3805
508562d6 3806 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 3807 dev->mdev->port_caps[port - 1].has_smi = false;
3808 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3809 MLX5_CAP_PORT_TYPE_IB) {
3810 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3811 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3812 port, 0,
3813 &vport_ctx);
3814 if (err) {
3815 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3816 port, err);
3817 return err;
3818 }
3819 dev->mdev->port_caps[port - 1].has_smi =
3820 vport_ctx.has_smi;
3821 } else {
3822 dev->mdev->port_caps[port - 1].has_smi = true;
3823 }
3824 }
3825 }
3826 return 0;
3827}
3828
e126ba97
EC		 3829static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3830{
3831 int port;
3832
508562d6 3833 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 3834 mlx5_query_ext_port_caps(dev, port);
3835}
3836
32f69e4b 3837static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 3838{
3839 struct ib_device_attr *dprops = NULL;
3840 struct ib_port_attr *pprops = NULL;
f614fc15 3841 int err = -ENOMEM;
2528e33e 3842 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3843
3844 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3845 if (!pprops)
3846 goto out;
3847
3848 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3849 if (!dprops)
3850 goto out;
3851
c43f1112
MG		 3852 err = set_has_smi_cap(dev);
3853 if (err)
3854 goto out;
3855
2528e33e 3856 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3857 if (err) {
3858 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3859 goto out;
3860 }
3861
32f69e4b
DJ		 3862 memset(pprops, 0, sizeof(*pprops));
3863 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3864 if (err) {
3865 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3866 port, err);
3867 goto out;
e126ba97
EC		 3868 }
3869
32f69e4b
DJ		 3870 dev->mdev->port_caps[port - 1].pkey_table_len =
3871 dprops->max_pkeys;
3872 dev->mdev->port_caps[port - 1].gid_table_len =
3873 pprops->gid_tbl_len;
3874 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3875 port, dprops->max_pkeys, pprops->gid_tbl_len);
3876
e126ba97
EC		 3877out:
3878 kfree(pprops);
3879 kfree(dprops);
3880
3881 return err;
3882}
3883
3884static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3885{
3886 int err;
3887
3888 err = mlx5_mr_cache_cleanup(dev);
3889 if (err)
3890 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3891
32927e28
MB		 3892 if (dev->umrc.qp)
3893 mlx5_ib_destroy_qp(dev->umrc.qp);
3894 if (dev->umrc.cq)
3895 ib_free_cq(dev->umrc.cq);
3896 if (dev->umrc.pd)
3897 ib_dealloc_pd(dev->umrc.pd);
e126ba97
EC		 3898}
3899
3900enum {
3901 MAX_UMR_WR = 128,
3902};
3903
3904static int create_umr_res(struct mlx5_ib_dev *dev)
3905{
3906 struct ib_qp_init_attr *init_attr = NULL;
3907 struct ib_qp_attr *attr = NULL;
3908 struct ib_pd *pd;
3909 struct ib_cq *cq;
3910 struct ib_qp *qp;
e126ba97
EC		 3911 int ret;
3912
3913 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3914 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3915 if (!attr || !init_attr) {
3916 ret = -ENOMEM;
3917 goto error_0;
3918 }
3919
ed082d36 3920 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3921 if (IS_ERR(pd)) {
3922 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3923 ret = PTR_ERR(pd);
3924 goto error_0;
3925 }
3926
add08d76 3927 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3928 if (IS_ERR(cq)) {
3929 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3930 ret = PTR_ERR(cq);
3931 goto error_2;
3932 }
e126ba97
EC		 3933
3934 init_attr->send_cq = cq;
3935 init_attr->recv_cq = cq;
3936 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3937 init_attr->cap.max_send_wr = MAX_UMR_WR;
3938 init_attr->cap.max_send_sge = 1;
3939 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3940 init_attr->port_num = 1;
3941 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3942 if (IS_ERR(qp)) {
3943 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3944 ret = PTR_ERR(qp);
3945 goto error_3;
3946 }
3947 qp->device = &dev->ib_dev;
3948 qp->real_qp = qp;
3949 qp->uobject = NULL;
3950 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3951 qp->send_cq = init_attr->send_cq;
3952 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3953
3954 attr->qp_state = IB_QPS_INIT;
3955 attr->port_num = 1;
3956 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3957 IB_QP_PORT, NULL);
3958 if (ret) {
3959 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3960 goto error_4;
3961 }
3962
3963 memset(attr, 0, sizeof(*attr));
3964 attr->qp_state = IB_QPS_RTR;
3965 attr->path_mtu = IB_MTU_256;
3966
3967 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3968 if (ret) {
3969 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3970 goto error_4;
3971 }
3972
3973 memset(attr, 0, sizeof(*attr));
3974 attr->qp_state = IB_QPS_RTS;
3975 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3976 if (ret) {
3977 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3978 goto error_4;
3979 }
3980
3981 dev->umrc.qp = qp;
3982 dev->umrc.cq = cq;
e126ba97
EC		 3983 dev->umrc.pd = pd;
3984
3985 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3986 ret = mlx5_mr_cache_init(dev);
3987 if (ret) {
3988 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3989 goto error_4;
3990 }
3991
3992 kfree(attr);
3993 kfree(init_attr);
3994
3995 return 0;
3996
3997error_4:
3998 mlx5_ib_destroy_qp(qp);
32927e28 3999 dev->umrc.qp = NULL;
e126ba97
EC		 4000
4001error_3:
add08d76 4002 ib_free_cq(cq);
32927e28 4003 dev->umrc.cq = NULL;
e126ba97
EC		 4004
4005error_2:
e126ba97 4006 ib_dealloc_pd(pd);
32927e28 4007 dev->umrc.pd = NULL;
e126ba97
EC		 4008
4009error_0:
4010 kfree(attr);
4011 kfree(init_attr);
4012 return ret;
4013}
4014
6e8484c5
MG		 4015static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4016{
4017 switch (umr_fence_cap) {
4018 case MLX5_CAP_UMR_FENCE_NONE:
4019 return MLX5_FENCE_MODE_NONE;
4020 case MLX5_CAP_UMR_FENCE_SMALL:
4021 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4022 default:
4023 return MLX5_FENCE_MODE_STRONG_ORDERING;
4024 }
4025}
4026
e126ba97
EC		 4027static int create_dev_resources(struct mlx5_ib_resources *devr)
4028{
4029 struct ib_srq_init_attr attr;
4030 struct mlx5_ib_dev *dev;
bcf4c1ea 4031 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 4032 int port;
e126ba97
EC		 4033 int ret = 0;
4034
4035 dev = container_of(devr, struct mlx5_ib_dev, devr);
4036
d16e91da
HE		 4037 mutex_init(&devr->mutex);
4038
e126ba97
EC		 4039 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4040 if (IS_ERR(devr->p0)) {
4041 ret = PTR_ERR(devr->p0);
4042 goto error0;
4043 }
4044 devr->p0->device = &dev->ib_dev;
4045 devr->p0->uobject = NULL;
4046 atomic_set(&devr->p0->usecnt, 0);
4047
bcf4c1ea 4048 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 4049 if (IS_ERR(devr->c0)) {
4050 ret = PTR_ERR(devr->c0);
4051 goto error1;
4052 }
4053 devr->c0->device = &dev->ib_dev;
4054 devr->c0->uobject = NULL;
4055 devr->c0->comp_handler = NULL;
4056 devr->c0->event_handler = NULL;
4057 devr->c0->cq_context = NULL;
4058 atomic_set(&devr->c0->usecnt, 0);
4059
4060 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4061 if (IS_ERR(devr->x0)) {
4062 ret = PTR_ERR(devr->x0);
4063 goto error2;
4064 }
4065 devr->x0->device = &dev->ib_dev;
4066 devr->x0->inode = NULL;
4067 atomic_set(&devr->x0->usecnt, 0);
4068 mutex_init(&devr->x0->tgt_qp_mutex);
4069 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4070
4071 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4072 if (IS_ERR(devr->x1)) {
4073 ret = PTR_ERR(devr->x1);
4074 goto error3;
4075 }
4076 devr->x1->device = &dev->ib_dev;
4077 devr->x1->inode = NULL;
4078 atomic_set(&devr->x1->usecnt, 0);
4079 mutex_init(&devr->x1->tgt_qp_mutex);
4080 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4081
4082 memset(&attr, 0, sizeof(attr));
4083 attr.attr.max_sge = 1;
4084 attr.attr.max_wr = 1;
4085 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 4086 attr.ext.cq = devr->c0;
e126ba97
EC		 4087 attr.ext.xrc.xrcd = devr->x0;
4088
4089 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4090 if (IS_ERR(devr->s0)) {
4091 ret = PTR_ERR(devr->s0);
4092 goto error4;
4093 }
4094 devr->s0->device = &dev->ib_dev;
4095 devr->s0->pd = devr->p0;
4096 devr->s0->uobject = NULL;
4097 devr->s0->event_handler = NULL;
4098 devr->s0->srq_context = NULL;
4099 devr->s0->srq_type = IB_SRQT_XRC;
4100 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 4101 devr->s0->ext.cq = devr->c0;
e126ba97 4102 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 4103 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 4104 atomic_inc(&devr->p0->usecnt);
4105 atomic_set(&devr->s0->usecnt, 0);
4106
4aa17b28
HA		 4107 memset(&attr, 0, sizeof(attr));
4108 attr.attr.max_sge = 1;
4109 attr.attr.max_wr = 1;
4110 attr.srq_type = IB_SRQT_BASIC;
4111 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4112 if (IS_ERR(devr->s1)) {
4113 ret = PTR_ERR(devr->s1);
4114 goto error5;
4115 }
4116 devr->s1->device = &dev->ib_dev;
4117 devr->s1->pd = devr->p0;
4118 devr->s1->uobject = NULL;
4119 devr->s1->event_handler = NULL;
4120 devr->s1->srq_context = NULL;
4121 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 4122 devr->s1->ext.cq = devr->c0;
4aa17b28 4123 atomic_inc(&devr->p0->usecnt);
1a56ff6d 4124 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 4125
7722f47e
HE		 4126 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4127 INIT_WORK(&devr->ports[port].pkey_change_work,
4128 pkey_change_handler);
4129 devr->ports[port].devr = devr;
4130 }
4131
e126ba97
EC		 4132 return 0;
4133
4aa17b28
HA		 4134error5:
4135 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 4136error4:
4137 mlx5_ib_dealloc_xrcd(devr->x1);
4138error3:
4139 mlx5_ib_dealloc_xrcd(devr->x0);
4140error2:
4141 mlx5_ib_destroy_cq(devr->c0);
4142error1:
4143 mlx5_ib_dealloc_pd(devr->p0);
4144error0:
4145 return ret;
4146}
4147
4148static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4149{
7722f47e
HE		 4150 struct mlx5_ib_dev *dev =
4151 container_of(devr, struct mlx5_ib_dev, devr);
4152 int port;
4153
4aa17b28 4154 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 4155 mlx5_ib_destroy_srq(devr->s0);
4156 mlx5_ib_dealloc_xrcd(devr->x0);
4157 mlx5_ib_dealloc_xrcd(devr->x1);
4158 mlx5_ib_destroy_cq(devr->c0);
4159 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 4160
4161 /* Make sure no change P_Key work items are still executing */
4162 for (port = 0; port < dev->num_ports; ++port)
4163 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 4164}
4165
e53505a8
AS		 4166static u32 get_core_cap_flags(struct ib_device *ibdev)
4167{
4168 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4169 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4170 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4171 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
85c7c014 4172 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
e53505a8
AS		 4173 u32 ret = 0;
4174
4175 if (ll == IB_LINK_LAYER_INFINIBAND)
4176 return RDMA_CORE_PORT_IBA_IB;
4177
85c7c014
DJ		 4178 if (raw_support)
4179 ret = RDMA_CORE_PORT_RAW_PACKET;
72cd5717 4180
e53505a8 4181 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 4182 return ret;
e53505a8
AS		 4183
4184 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 4185 return ret;
e53505a8
AS		 4186
4187 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4188 ret |= RDMA_CORE_PORT_IBA_ROCE;
4189
4190 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4191 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4192
4193 return ret;
4194}
4195
7738613e
IW		 4196static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4197 struct ib_port_immutable *immutable)
4198{
4199 struct ib_port_attr attr;
ca5b91d6
OG		 4200 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4201 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 4202 int err;
4203
c4550c63
OG		 4204 immutable->core_cap_flags = get_core_cap_flags(ibdev);
4205
4206 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 4207 if (err)
4208 return err;
4209
4210 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4211 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 4212 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 4213 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4214 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 4215
4216 return 0;
4217}
4218
8e6efa3a
MB		 4219static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4220 struct ib_port_immutable *immutable)
4221{
4222 struct ib_port_attr attr;
4223 int err;
4224
4225 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4226
4227 err = ib_query_port(ibdev, port_num, &attr);
4228 if (err)
4229 return err;
4230
4231 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4232 immutable->gid_tbl_len = attr.gid_tbl_len;
4233 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4234
4235 return 0;
4236}
4237
9abb0d1b 4238static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 4239{
4240 struct mlx5_ib_dev *dev =
4241 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 4242 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4243 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4244 fw_rev_sub(dev->mdev));
c7342823
IW		 4245}
4246
45f95acd 4247static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4248{
4249 struct mlx5_core_dev *mdev = dev->mdev;
4250 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4251 MLX5_FLOW_NAMESPACE_LAG);
4252 struct mlx5_flow_table *ft;
4253 int err;
4254
4255 if (!ns || !mlx5_lag_is_active(mdev))
4256 return 0;
4257
4258 err = mlx5_cmd_create_vport_lag(mdev);
4259 if (err)
4260 return err;
4261
4262 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4263 if (IS_ERR(ft)) {
4264 err = PTR_ERR(ft);
4265 goto err_destroy_vport_lag;
4266 }
4267
9a4ca38d 4268 dev->flow_db->lag_demux_ft = ft;
9ef9c640
AH		 4269 return 0;
4270
4271err_destroy_vport_lag:
4272 mlx5_cmd_destroy_vport_lag(mdev);
4273 return err;
4274}
4275
45f95acd 4276static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 4277{
4278 struct mlx5_core_dev *mdev = dev->mdev;
4279
9a4ca38d
MB		 4280 if (dev->flow_db->lag_demux_ft) {
4281 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4282 dev->flow_db->lag_demux_ft = NULL;
9ef9c640
AH		 4283
4284 mlx5_cmd_destroy_vport_lag(mdev);
4285 }
4286}
4287
7fd8aefb 4288static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 4289{
4290 int err;
4291
7fd8aefb
DJ		 4292 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4293 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 4294 if (err) {
7fd8aefb 4295 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 4296 return err;
4297 }
4298
4299 return 0;
4300}
4301
7fd8aefb 4302static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 4303{
7fd8aefb
DJ		 4304 if (dev->roce[port_num].nb.notifier_call) {
4305 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4306 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 4307 }
4308}
4309
7fd8aefb 4310static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
fc24fc5e 4311{
e53505a8
AS		 4312 int err;
4313
ca5b91d6
OG		 4314 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4315 err = mlx5_nic_vport_enable_roce(dev->mdev);
4316 if (err)
8e6efa3a 4317 return err;
ca5b91d6 4318 }
e53505a8 4319
45f95acd 4320 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 4321 if (err)
4322 goto err_disable_roce;
4323
e53505a8
AS		 4324 return 0;
4325
9ef9c640 4326err_disable_roce:
ca5b91d6
OG		 4327 if (MLX5_CAP_GEN(dev->mdev, roce))
4328 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 4329
e53505a8 4330 return err;
fc24fc5e
AS		 4331}
4332
45f95acd 4333static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 4334{
45f95acd 4335 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 4336 if (MLX5_CAP_GEN(dev->mdev, roce))
4337 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 4338}
4339
e1f24a79 4340struct mlx5_ib_counter {
7c16f477
KH		 4341 const char *name;
4342 size_t offset;
4343};
4344
4345#define INIT_Q_COUNTER(_name) \
4346 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4347
e1f24a79 4348static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 4349 INIT_Q_COUNTER(rx_write_requests),
4350 INIT_Q_COUNTER(rx_read_requests),
4351 INIT_Q_COUNTER(rx_atomic_requests),
4352 INIT_Q_COUNTER(out_of_buffer),
4353};
4354
e1f24a79 4355static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 4356 INIT_Q_COUNTER(out_of_sequence),
4357};
4358
e1f24a79 4359static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 4360 INIT_Q_COUNTER(duplicate_request),
4361 INIT_Q_COUNTER(rnr_nak_retry_err),
4362 INIT_Q_COUNTER(packet_seq_err),
4363 INIT_Q_COUNTER(implied_nak_seq_err),
4364 INIT_Q_COUNTER(local_ack_timeout_err),
4365};
4366
e1f24a79
PP		 4367#define INIT_CONG_COUNTER(_name) \
4368 { .name = #_name, .offset = \
4369 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4370
4371static const struct mlx5_ib_counter cong_cnts[] = {
4372 INIT_CONG_COUNTER(rp_cnp_ignored),
4373 INIT_CONG_COUNTER(rp_cnp_handled),
4374 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4375 INIT_CONG_COUNTER(np_cnp_sent),
4376};
4377
58dcb60a
PP		 4378static const struct mlx5_ib_counter extended_err_cnts[] = {
4379 INIT_Q_COUNTER(resp_local_length_error),
4380 INIT_Q_COUNTER(resp_cqe_error),
4381 INIT_Q_COUNTER(req_cqe_error),
4382 INIT_Q_COUNTER(req_remote_invalid_request),
4383 INIT_Q_COUNTER(req_remote_access_errors),
4384 INIT_Q_COUNTER(resp_remote_access_errors),
4385 INIT_Q_COUNTER(resp_cqe_flush_error),
4386 INIT_Q_COUNTER(req_cqe_flush_error),
4387};
4388
e1f24a79 4389static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4390{
aac4492e 4391 int i;
0837e86a 4392
7c16f477 4393 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4394 if (dev->port[i].cnts.set_id)
4395 mlx5_core_dealloc_q_counter(dev->mdev,
4396 dev->port[i].cnts.set_id);
e1f24a79
PP		 4397 kfree(dev->port[i].cnts.names);
4398 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 4399 }
4400}
4401
e1f24a79
PP		 4402static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4403 struct mlx5_ib_counters *cnts)
7c16f477
KH		 4404{
4405 u32 num_counters;
4406
4407 num_counters = ARRAY_SIZE(basic_q_cnts);
4408
4409 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4410 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4411
4412 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4413 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 4414
4415 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4416 num_counters += ARRAY_SIZE(extended_err_cnts);
4417
e1f24a79 4418 cnts->num_q_counters = num_counters;
7c16f477 4419
e1f24a79
PP		 4420 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4421 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4422 num_counters += ARRAY_SIZE(cong_cnts);
4423 }
4424
4425 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4426 if (!cnts->names)
7c16f477
KH		 4427 return -ENOMEM;
4428
e1f24a79
PP		 4429 cnts->offsets = kcalloc(num_counters,
4430 sizeof(cnts->offsets), GFP_KERNEL);
4431 if (!cnts->offsets)
7c16f477
KH		 4432 goto err_names;
4433
7c16f477
KH		 4434 return 0;
4435
4436err_names:
e1f24a79 4437 kfree(cnts->names);
aac4492e 4438 cnts->names = NULL;
7c16f477
KH		 4439 return -ENOMEM;
4440}
4441
e1f24a79
PP		 4442static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4443 const char **names,
4444 size_t *offsets)
7c16f477
KH		 4445{
4446 int i;
4447 int j = 0;
4448
4449 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4450 names[j] = basic_q_cnts[i].name;
4451 offsets[j] = basic_q_cnts[i].offset;
4452 }
4453
4454 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4455 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4456 names[j] = out_of_seq_q_cnts[i].name;
4457 offsets[j] = out_of_seq_q_cnts[i].offset;
4458 }
4459 }
4460
4461 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4462 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4463 names[j] = retrans_q_cnts[i].name;
4464 offsets[j] = retrans_q_cnts[i].offset;
4465 }
4466 }
e1f24a79 4467
58dcb60a
PP		 4468 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4469 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4470 names[j] = extended_err_cnts[i].name;
4471 offsets[j] = extended_err_cnts[i].offset;
4472 }
4473 }
4474
e1f24a79
PP		 4475 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4476 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4477 names[j] = cong_cnts[i].name;
4478 offsets[j] = cong_cnts[i].offset;
4479 }
4480 }
0837e86a
MB		 4481}
4482
e1f24a79 4483static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a 4484{
aac4492e 4485 int err = 0;
0837e86a 4486 int i;
0837e86a
MB		 4487
4488 for (i = 0; i < dev->num_ports; i++) {
aac4492e
DJ		 4489 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4490 if (err)
4491 goto err_alloc;
4492
4493 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4494 dev->port[i].cnts.offsets);
7c16f477 4495
aac4492e
DJ		 4496 err = mlx5_core_alloc_q_counter(dev->mdev,
4497 &dev->port[i].cnts.set_id);
4498 if (err) {
0837e86a
MB		 4499 mlx5_ib_warn(dev,
4500 "couldn't allocate queue counter for port %d, err %d\n",
aac4492e
DJ		 4501 i + 1, err);
4502 goto err_alloc;
0837e86a 4503 }
aac4492e 4504 dev->port[i].cnts.set_id_valid = true;
0837e86a
MB		 4505 }
4506
4507 return 0;
4508
aac4492e
DJ		 4509err_alloc:
4510 mlx5_ib_dealloc_counters(dev);
4511 return err;
0837e86a
MB		 4512}
4513
0ad17a8f
MB		 4514static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4515 u8 port_num)
4516{
7c16f477
KH		 4517 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4518 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 4519
4520 /* We support only per port stats */
4521 if (port_num == 0)
4522 return NULL;
4523
e1f24a79
PP		 4524 return rdma_alloc_hw_stats_struct(port->cnts.names,
4525 port->cnts.num_q_counters +
4526 port->cnts.num_cong_counters,
0ad17a8f
MB		 4527 RDMA_HW_STATS_DEFAULT_LIFESPAN);
4528}
4529
aac4492e 4530static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
e1f24a79
PP		 4531 struct mlx5_ib_port *port,
4532 struct rdma_hw_stats *stats)
0ad17a8f 4533{
0ad17a8f
MB		 4534 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4535 void *out;
4536 __be32 val;
e1f24a79 4537 int ret, i;
0ad17a8f 4538
1b9a07ee 4539 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 4540 if (!out)
4541 return -ENOMEM;
4542
aac4492e 4543 ret = mlx5_core_query_q_counter(mdev,
e1f24a79 4544 port->cnts.set_id, 0,
0ad17a8f
MB		 4545 out, outlen);
4546 if (ret)
4547 goto free;
4548
e1f24a79
PP		 4549 for (i = 0; i < port->cnts.num_q_counters; i++) {
4550 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 4551 stats->value[i] = (u64)be32_to_cpu(val);
4552 }
7c16f477 4553
0ad17a8f
MB		 4554free:
4555 kvfree(out);
e1f24a79
PP		 4556 return ret;
4557}
4558
e1f24a79
PP		 4559static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4560 struct rdma_hw_stats *stats,
4561 u8 port_num, int index)
4562{
4563 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4564 struct mlx5_ib_port *port = &dev->port[port_num - 1];
aac4492e 4565 struct mlx5_core_dev *mdev;
e1f24a79 4566 int ret, num_counters;
aac4492e 4567 u8 mdev_port_num;
e1f24a79
PP		 4568
4569 if (!stats)
4570 return -EINVAL;
4571
aac4492e
DJ		 4572 num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4573
4574 /* q_counters are per IB device, query the master mdev */
4575 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
e1f24a79
PP		 4576 if (ret)
4577 return ret;
e1f24a79
PP		 4578
4579 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
aac4492e
DJ		 4580 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4581 &mdev_port_num);
4582 if (!mdev) {
4583 /* If port is not affiliated yet, its in down state
4584 * which doesn't have any counters yet, so it would be
4585 * zero. So no need to read from the HCA.
4586 */
4587 goto done;
4588 }
71a0ff65
MD		 4589 ret = mlx5_lag_query_cong_counters(dev->mdev,
4590 stats->value +
4591 port->cnts.num_q_counters,
4592 port->cnts.num_cong_counters,
4593 port->cnts.offsets +
4594 port->cnts.num_q_counters);
aac4492e
DJ		 4595
4596 mlx5_ib_put_native_port_mdev(dev, port_num);
e1f24a79
PP		 4597 if (ret)
4598 return ret;
e1f24a79
PP		 4599 }
4600
aac4492e 4601done:
e1f24a79 4602 return num_counters;
0ad17a8f
MB		 4603}
4604
8e959601
NV		 4605static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4606{
4607 return mlx5_rdma_netdev_free(netdev);
4608}
4609
693dfd5a
ES		 4610static struct net_device*
4611mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4612 u8 port_num,
4613 enum rdma_netdev_t type,
4614 const char *name,
4615 unsigned char name_assign_type,
4616 void (*setup)(struct net_device *))
4617{
8e959601
NV		 4618 struct net_device *netdev;
4619 struct rdma_netdev *rn;
4620
693dfd5a
ES		 4621 if (type != RDMA_NETDEV_IPOIB)
4622 return ERR_PTR(-EOPNOTSUPP);
4623
8e959601
NV		 4624 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4625 name, setup);
4626 if (likely(!IS_ERR_OR_NULL(netdev))) {
4627 rn = netdev_priv(netdev);
4628 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4629 }
4630 return netdev;
693dfd5a
ES		 4631}
4632
fe248c3a
MG		 4633static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4634{
4635 if (!dev->delay_drop.dbg)
4636 return;
4637 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4638 kfree(dev->delay_drop.dbg);
4639 dev->delay_drop.dbg = NULL;
4640}
4641
03404e8a
MG		 4642static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4643{
4644 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4645 return;
4646
4647 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 4648 delay_drop_debugfs_cleanup(dev);
4649}
4650
4651static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4652 size_t count, loff_t *pos)
4653{
4654 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4655 char lbuf[20];
4656 int len;
4657
4658 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4659 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4660}
4661
4662static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4663 size_t count, loff_t *pos)
4664{
4665 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4666 u32 timeout;
4667 u32 var;
4668
4669 if (kstrtouint_from_user(buf, count, 0, &var))
4670 return -EFAULT;
4671
4672 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4673 1000);
4674 if (timeout != var)
4675 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4676 timeout);
4677
4678 delay_drop->timeout = timeout;
4679
4680 return count;
4681}
4682
4683static const struct file_operations fops_delay_drop_timeout = {
4684 .owner = THIS_MODULE,
4685 .open = simple_open,
4686 .write = delay_drop_timeout_write,
4687 .read = delay_drop_timeout_read,
4688};
4689
4690static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4691{
4692 struct mlx5_ib_dbg_delay_drop *dbg;
4693
4694 if (!mlx5_debugfs_root)
4695 return 0;
4696
4697 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4698 if (!dbg)
4699 return -ENOMEM;
4700
cbafad87
SM		 4701 dev->delay_drop.dbg = dbg;
4702
fe248c3a
MG		 4703 dbg->dir_debugfs =
4704 debugfs_create_dir("delay_drop",
4705 dev->mdev->priv.dbg_root);
4706 if (!dbg->dir_debugfs)
cbafad87 4707 goto out_debugfs;
fe248c3a
MG		 4708
4709 dbg->events_cnt_debugfs =
4710 debugfs_create_atomic_t("num_timeout_events", 0400,
4711 dbg->dir_debugfs,
4712 &dev->delay_drop.events_cnt);
4713 if (!dbg->events_cnt_debugfs)
4714 goto out_debugfs;
4715
4716 dbg->rqs_cnt_debugfs =
4717 debugfs_create_atomic_t("num_rqs", 0400,
4718 dbg->dir_debugfs,
4719 &dev->delay_drop.rqs_cnt);
4720 if (!dbg->rqs_cnt_debugfs)
4721 goto out_debugfs;
4722
4723 dbg->timeout_debugfs =
4724 debugfs_create_file("timeout", 0600,
4725 dbg->dir_debugfs,
4726 &dev->delay_drop,
4727 &fops_delay_drop_timeout);
4728 if (!dbg->timeout_debugfs)
4729 goto out_debugfs;
4730
4731 return 0;
4732
4733out_debugfs:
4734 delay_drop_debugfs_cleanup(dev);
4735 return -ENOMEM;
03404e8a
MG		 4736}
4737
4738static void init_delay_drop(struct mlx5_ib_dev *dev)
4739{
4740 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4741 return;
4742
4743 mutex_init(&dev->delay_drop.lock);
4744 dev->delay_drop.dev = dev;
4745 dev->delay_drop.activate = false;
4746 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4747 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 4748 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4749 atomic_set(&dev->delay_drop.events_cnt, 0);
4750
4751 if (delay_drop_debugfs_init(dev))
4752 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 4753}
4754
84305d71
LR		 4755static const struct cpumask *
4756mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 4757{
4758 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4759
6082d9c9 4760 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
40b24403
SG		 4761}
4762
32f69e4b
DJ		 4763/* The mlx5_ib_multiport_mutex should be held when calling this function */
4764static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4765 struct mlx5_ib_multiport_info *mpi)
4766{
4767 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4768 struct mlx5_ib_port *port = &ibdev->port[port_num];
4769 int comps;
4770 int err;
4771 int i;
4772
a9e546e7
PP		 4773 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4774
32f69e4b
DJ		 4775 spin_lock(&port->mp.mpi_lock);
4776 if (!mpi->ibdev) {
4777 spin_unlock(&port->mp.mpi_lock);
4778 return;
4779 }
4780 mpi->ibdev = NULL;
4781
4782 spin_unlock(&port->mp.mpi_lock);
4783 mlx5_remove_netdev_notifier(ibdev, port_num);
4784 spin_lock(&port->mp.mpi_lock);
4785
4786 comps = mpi->mdev_refcnt;
4787 if (comps) {
4788 mpi->unaffiliate = true;
4789 init_completion(&mpi->unref_comp);
4790 spin_unlock(&port->mp.mpi_lock);
4791
4792 for (i = 0; i < comps; i++)
4793 wait_for_completion(&mpi->unref_comp);
4794
4795 spin_lock(&port->mp.mpi_lock);
4796 mpi->unaffiliate = false;
4797 }
4798
4799 port->mp.mpi = NULL;
4800
4801 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4802
4803 spin_unlock(&port->mp.mpi_lock);
4804
4805 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4806
4807 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4808 /* Log an error, still needed to cleanup the pointers and add
4809 * it back to the list.
4810 */
4811 if (err)
4812 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4813 port_num + 1);
4814
4815 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4816}
4817
4818/* The mlx5_ib_multiport_mutex should be held when calling this function */
4819static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4820 struct mlx5_ib_multiport_info *mpi)
4821{
4822 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4823 int err;
4824
4825 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4826 if (ibdev->port[port_num].mp.mpi) {
4827 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4828 port_num + 1);
4829 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4830 return false;
4831 }
4832
4833 ibdev->port[port_num].mp.mpi = mpi;
4834 mpi->ibdev = ibdev;
4835 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4836
4837 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4838 if (err)
4839 goto unbind;
4840
4841 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4842 if (err)
4843 goto unbind;
4844
4845 err = mlx5_add_netdev_notifier(ibdev, port_num);
4846 if (err) {
4847 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4848 port_num + 1);
4849 goto unbind;
4850 }
4851
a9e546e7
PP		 4852 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4853 if (err)
4854 goto unbind;
4855
32f69e4b
DJ		 4856 return true;
4857
4858unbind:
4859 mlx5_ib_unbind_slave_port(ibdev, mpi);
4860 return false;
4861}
4862
4863static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4864{
4865 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4866 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4867 port_num + 1);
4868 struct mlx5_ib_multiport_info *mpi;
4869 int err;
4870 int i;
4871
4872 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4873 return 0;
4874
4875 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4876 &dev->sys_image_guid);
4877 if (err)
4878 return err;
4879
4880 err = mlx5_nic_vport_enable_roce(dev->mdev);
4881 if (err)
4882 return err;
4883
4884 mutex_lock(&mlx5_ib_multiport_mutex);
4885 for (i = 0; i < dev->num_ports; i++) {
4886 bool bound = false;
4887
4888 /* build a stub multiport info struct for the native port. */
4889 if (i == port_num) {
4890 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4891 if (!mpi) {
4892 mutex_unlock(&mlx5_ib_multiport_mutex);
4893 mlx5_nic_vport_disable_roce(dev->mdev);
4894 return -ENOMEM;
4895 }
4896
4897 mpi->is_master = true;
4898 mpi->mdev = dev->mdev;
4899 mpi->sys_image_guid = dev->sys_image_guid;
4900 dev->port[i].mp.mpi = mpi;
4901 mpi->ibdev = dev;
4902 mpi = NULL;
4903 continue;
4904 }
4905
4906 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4907 list) {
4908 if (dev->sys_image_guid == mpi->sys_image_guid &&
4909 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4910 bound = mlx5_ib_bind_slave_port(dev, mpi);
4911 }
4912
4913 if (bound) {
4914 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4915 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4916 list_del(&mpi->list);
4917 break;
4918 }
4919 }
4920 if (!bound) {
4921 get_port_caps(dev, i + 1);
4922 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4923 i + 1);
4924 }
4925 }
4926
4927 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4928 mutex_unlock(&mlx5_ib_multiport_mutex);
4929 return err;
4930}
4931
4932static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4933{
4934 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4935 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4936 port_num + 1);
4937 int i;
4938
4939 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4940 return;
4941
4942 mutex_lock(&mlx5_ib_multiport_mutex);
4943 for (i = 0; i < dev->num_ports; i++) {
4944 if (dev->port[i].mp.mpi) {
4945 /* Destroy the native port stub */
4946 if (i == port_num) {
4947 kfree(dev->port[i].mp.mpi);
4948 dev->port[i].mp.mpi = NULL;
4949 } else {
4950 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4951 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4952 }
4953 }
4954 }
4955
4956 mlx5_ib_dbg(dev, "removing from devlist\n");
4957 list_del(&dev->ib_dev_list);
4958 mutex_unlock(&mlx5_ib_multiport_mutex);
4959
4960 mlx5_nic_vport_disable_roce(dev->mdev);
4961}
4962
24da0016
AL		 4963ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
4964 UVERBS_METHOD_DM_ALLOC,
4965 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
4966 UVERBS_ATTR_TYPE(u64),
4967 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
4968 &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
4969 UVERBS_ATTR_TYPE(u16),
4970 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4971
c6475a0b
AY		 4972ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
4973 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
4974 &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4975 UVERBS_ATTR_TYPE(u64),
4976 UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4977
24da0016 4978#define NUM_TREES 2
8c84660b
MB		 4979static int populate_specs_root(struct mlx5_ib_dev *dev)
4980{
4981 const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
4982 uverbs_default_get_objects()};
4983 size_t num_trees = 1;
4984
c6475a0b
AY		 4985 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
4986 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4987 default_root[num_trees++] = &mlx5_ib_flow_action;
4988
24da0016
AL		 4989 if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
4990 !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4991 default_root[num_trees++] = &mlx5_ib_dm;
4992
8c84660b
MB		 4993 dev->ib_dev.specs_root =
4994 uverbs_alloc_spec_tree(num_trees, default_root);
4995
4996 return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
4997}
4998
4999static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5000{
5001 uverbs_free_spec_tree(dev->ib_dev.specs_root);
5002}
5003
b5ca15ad 5004void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 5005{
32f69e4b 5006 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 5007#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5008 cleanup_srcu_struct(&dev->mr_srcu);
5009#endif
16c1975f
MB		 5010 kfree(dev->port);
5011}
5012
b5ca15ad 5013int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5014{
5015 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 5016 const char *name;
e126ba97 5017 int err;
32f69e4b 5018 int i;
e126ba97 5019
508562d6 5020 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 5021 GFP_KERNEL);
5022 if (!dev->port)
16c1975f 5023 return -ENOMEM;
0837e86a 5024
32f69e4b
DJ		 5025 for (i = 0; i < dev->num_ports; i++) {
5026 spin_lock_init(&dev->port[i].mp.mpi_lock);
5027 rwlock_init(&dev->roce[i].netdev_lock);
5028 }
5029
5030 err = mlx5_ib_init_multiport_master(dev);
e126ba97 5031 if (err)
0837e86a 5032 goto err_free_port;
e126ba97 5033
32f69e4b 5034 if (!mlx5_core_mp_enabled(mdev)) {
32f69e4b
DJ		 5035 for (i = 1; i <= dev->num_ports; i++) {
5036 err = get_port_caps(dev, i);
5037 if (err)
5038 break;
5039 }
5040 } else {
5041 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5042 }
5043 if (err)
5044 goto err_mp;
5045
1b5daf11
MD		 5046 if (mlx5_use_mad_ifc(dev))
5047 get_ext_port_caps(dev);
e126ba97 5048
4babcf97
AH		 5049 if (!mlx5_lag_is_active(mdev))
5050 name = "mlx5_%d";
5051 else
5052 name = "mlx5_bond_%d";
5053
5054 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 5055 dev->ib_dev.owner = THIS_MODULE;
5056 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 5057 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 5058 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 5059 dev->ib_dev.num_comp_vectors =
5060 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 5061 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 5062
3cc297db
MB		 5063 mutex_init(&dev->cap_mask_mutex);
5064 INIT_LIST_HEAD(&dev->qp_list);
5065 spin_lock_init(&dev->reset_flow_resource_lock);
5066
24da0016
AL		 5067 spin_lock_init(&dev->memic.memic_lock);
5068 dev->memic.dev = mdev;
5069
3cc297db
MB		 5070#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5071 err = init_srcu_struct(&dev->mr_srcu);
5072 if (err)
5073 goto err_free_port;
5074#endif
5075
16c1975f 5076 return 0;
32f69e4b
DJ		 5077err_mp:
5078 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 5079
5080err_free_port:
5081 kfree(dev->port);
5082
5083 return -ENOMEM;
5084}
5085
9a4ca38d
MB		 5086static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5087{
5088 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5089
5090 if (!dev->flow_db)
5091 return -ENOMEM;
5092
5093 mutex_init(&dev->flow_db->lock);
5094
5095 return 0;
5096}
5097
b5ca15ad
MB		 5098int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5099{
5100 struct mlx5_ib_dev *nic_dev;
5101
5102 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5103
5104 if (!nic_dev)
5105 return -EINVAL;
5106
5107 dev->flow_db = nic_dev->flow_db;
5108
5109 return 0;
5110}
5111
9a4ca38d
MB		 5112static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5113{
5114 kfree(dev->flow_db);
5115}
5116
b5ca15ad 5117int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5118{
5119 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 5120 int err;
5121
e126ba97
EC		 5122 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5123 dev->ib_dev.uverbs_cmd_mask =
5124 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5125 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5126 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5127 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5128 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 5129 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5130 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 5131 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 5132 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 5133 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5134 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5135 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5136 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5137 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5138 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5139 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5140 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5141 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5142 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5143 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5144 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5145 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5146 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5147 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5148 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5149 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 5150 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 5151 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5152 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 5153 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 5154 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5155 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 5156
5157 dev->ib_dev.query_device = mlx5_ib_query_device;
ebd61f68 5158 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 5159 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 5160 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5161 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 5162 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5163 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5164 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5165 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5166 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5167 dev->ib_dev.mmap = mlx5_ib_mmap;
5168 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5169 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5170 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5171 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5172 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5173 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5174 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5175 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5176 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5177 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5178 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5179 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5180 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5181 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5182 dev->ib_dev.post_send = mlx5_ib_post_send;
5183 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5184 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5185 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5186 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5187 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5188 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5189 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5190 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5191 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 5192 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 5193 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5194 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5195 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5196 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 5197 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 5198 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 5199 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
c7342823 5200 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 5201 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 5202 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 5203 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 5204
eff901d3
EC		 5205 if (mlx5_core_is_pf(mdev)) {
5206 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5207 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5208 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5209 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5210 }
e126ba97 5211
7c2344c3
MG		 5212 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5213
6e8484c5
MG		 5214 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5215
d2370e0a
MB		 5216 if (MLX5_CAP_GEN(mdev, imaicl)) {
5217 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5218 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5219 dev->ib_dev.uverbs_cmd_mask |=
5220 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5221 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5222 }
5223
938fe83c 5224 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 5225 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5226 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5227 dev->ib_dev.uverbs_cmd_mask |=
5228 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5229 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5230 }
5231
24da0016
AL		 5232 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5233 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5234 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
6c29f57e 5235 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
24da0016
AL		 5236 }
5237
81e30880
YH		 5238 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5239 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5240 dev->ib_dev.uverbs_ex_cmd_mask |=
5241 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5242 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
c6475a0b
AY		 5243 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5244 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
349705c1 5245 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
0ede73bc 5246 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
81e30880 5247
e126ba97
EC		 5248 err = init_node_data(dev);
5249 if (err)
16c1975f 5250 return err;
e126ba97 5251
c8b89924 5252 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
e7996a9a
JG		 5253 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5254 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
c8b89924
MB		 5255 mutex_init(&dev->lb_mutex);
5256
16c1975f
MB		 5257 return 0;
5258}
5259
8e6efa3a
MB		 5260static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5261{
5262 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5263 dev->ib_dev.query_port = mlx5_ib_query_port;
5264
5265 return 0;
5266}
5267
b5ca15ad 5268int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
8e6efa3a
MB		 5269{
5270 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5271 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5272
5273 return 0;
5274}
5275
5276static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5277 u8 port_num)
5278{
5279 int i;
5280
5281 for (i = 0; i < dev->num_ports; i++) {
5282 dev->roce[i].dev = dev;
5283 dev->roce[i].native_port_num = i + 1;
5284 dev->roce[i].last_port_state = IB_PORT_DOWN;
5285 }
5286
5287 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5288 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5289 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5290 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5291 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5292 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5293
5294 dev->ib_dev.uverbs_ex_cmd_mask |=
5295 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5296 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5297 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5298 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5299 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5300
5301 return mlx5_add_netdev_notifier(dev, port_num);
5302}
5303
5304static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5305{
5306 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5307
5308 mlx5_remove_netdev_notifier(dev, port_num);
5309}
5310
5311int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5312{
5313 struct mlx5_core_dev *mdev = dev->mdev;
5314 enum rdma_link_layer ll;
5315 int port_type_cap;
5316 int err = 0;
5317 u8 port_num;
5318
5319 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5320 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5321 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5322
5323 if (ll == IB_LINK_LAYER_ETHERNET)
5324 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5325
5326 return err;
5327}
5328
5329void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5330{
5331 mlx5_ib_stage_common_roce_cleanup(dev);
5332}
5333
16c1975f
MB		 5334static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5335{
5336 struct mlx5_core_dev *mdev = dev->mdev;
5337 enum rdma_link_layer ll;
5338 int port_type_cap;
32f69e4b 5339 u8 port_num;
16c1975f
MB		 5340 int err;
5341
32f69e4b 5342 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 5343 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5344 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5345
fc24fc5e 5346 if (ll == IB_LINK_LAYER_ETHERNET) {
8e6efa3a
MB		 5347 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5348 if (err)
5349 return err;
7fd8aefb 5350
7fd8aefb 5351 err = mlx5_enable_eth(dev, port_num);
fc24fc5e 5352 if (err)
8e6efa3a 5353 goto cleanup;
fc24fc5e
AS		 5354 }
5355
16c1975f 5356 return 0;
8e6efa3a
MB		 5357cleanup:
5358 mlx5_ib_stage_common_roce_cleanup(dev);
5359
5360 return err;
16c1975f 5361}
e126ba97 5362
16c1975f
MB		 5363static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5364{
5365 struct mlx5_core_dev *mdev = dev->mdev;
5366 enum rdma_link_layer ll;
5367 int port_type_cap;
32f69e4b 5368 u8 port_num;
e126ba97 5369
32f69e4b 5370 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 5371 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5372 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5373
5374 if (ll == IB_LINK_LAYER_ETHERNET) {
5375 mlx5_disable_eth(dev);
8e6efa3a 5376 mlx5_ib_stage_common_roce_cleanup(dev);
45bded2c 5377 }
16c1975f 5378}
6aec21f6 5379
b5ca15ad 5380int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5381{
5382 return create_dev_resources(&dev->devr);
5383}
5384
b5ca15ad 5385void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5386{
5387 destroy_dev_resources(&dev->devr);
5388}
5389
5390static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5391{
07321b3c
MB		 5392 mlx5_ib_internal_fill_odp_caps(dev);
5393
16c1975f
MB		 5394 return mlx5_ib_odp_init_one(dev);
5395}
4a2da0b8 5396
b5ca15ad 5397int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
16c1975f 5398{
5e1e7612
MB		 5399 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5400 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
5401 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
5402
5403 return mlx5_ib_alloc_counters(dev);
5404 }
16c1975f
MB		 5405
5406 return 0;
5407}
5408
b5ca15ad 5409void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5410{
5411 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5412 mlx5_ib_dealloc_counters(dev);
5413}
5414
5415static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5416{
a9e546e7
PP		 5417 return mlx5_ib_init_cong_debugfs(dev,
5418 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5419}
5420
5421static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5422{
a9e546e7
PP		 5423 mlx5_ib_cleanup_cong_debugfs(dev,
5424 mlx5_core_native_port_num(dev->mdev) - 1);
16c1975f
MB		 5425}
5426
5427static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5428{
5fe9dec0
EC		 5429 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
5430 if (!dev->mdev->priv.uar)
16c1975f
MB		 5431 return -ENOMEM;
5432 return 0;
5433}
5434
5435static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5436{
5437 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5438}
5439
b5ca15ad 5440int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5441{
5442 int err;
5fe9dec0
EC		 5443
5444 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5445 if (err)
16c1975f 5446 return err;
5fe9dec0
EC		 5447
5448 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5449 if (err)
16c1975f 5450 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 5451
16c1975f
MB		 5452 return err;
5453}
0837e86a 5454
b5ca15ad 5455void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
16c1975f
MB		 5456{
5457 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5458 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5459}
e126ba97 5460
8c84660b
MB		 5461static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5462{
5463 return populate_specs_root(dev);
5464}
5465
b5ca15ad 5466int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5467{
5468 return ib_register_device(&dev->ib_dev, NULL);
5469}
5470
8c84660b
MB		 5471static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5472{
5473 depopulate_specs_root(dev);
5474}
5475
03fe2deb 5476void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5477{
42cea83f 5478 destroy_umrc_res(dev);
16c1975f
MB		 5479}
5480
03fe2deb 5481void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
16c1975f 5482{
42cea83f 5483 ib_unregister_device(&dev->ib_dev);
16c1975f
MB		 5484}
5485
03fe2deb 5486int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
16c1975f 5487{
42cea83f 5488 return create_umr_res(dev);
16c1975f
MB		 5489}
5490
5491static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5492{
03404e8a
MG		 5493 init_delay_drop(dev);
5494
16c1975f
MB		 5495 return 0;
5496}
5497
5498static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5499{
5500 cancel_delay_drop(dev);
5501}
5502
b5ca15ad 5503int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
16c1975f
MB		 5504{
5505 int err;
5506 int i;
5507
e126ba97 5508 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 5509 err = device_create_file(&dev->ib_dev.dev,
5510 mlx5_class_attributes[i]);
5511 if (err)
16c1975f 5512 return err;
e126ba97
EC		 5513 }
5514
16c1975f
MB		 5515 return 0;
5516}
5517
fc385b7a
MB		 5518static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5519{
5520 mlx5_ib_register_vport_reps(dev);
5521
5522 return 0;
5523}
5524
5525static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5526{
5527 mlx5_ib_unregister_vport_reps(dev);
5528}
5529
b5ca15ad
MB		 5530void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5531 const struct mlx5_ib_profile *profile,
5532 int stage)
16c1975f
MB		 5533{
5534 /* Number of stages to cleanup */
5535 while (stage) {
5536 stage--;
5537 if (profile->stage[stage].cleanup)
5538 profile->stage[stage].cleanup(dev);
5539 }
e126ba97 5540
16c1975f
MB		 5541 ib_dealloc_device((struct ib_device *)dev);
5542}
e126ba97 5543
32f69e4b
DJ		 5544static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5545
b5ca15ad
MB		 5546void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5547 const struct mlx5_ib_profile *profile)
16c1975f 5548{
16c1975f
MB		 5549 int err;
5550 int i;
e126ba97 5551
16c1975f 5552 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 5553
16c1975f
MB		 5554 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5555 if (profile->stage[i].init) {
5556 err = profile->stage[i].init(dev);
5557 if (err)
5558 goto err_out;
5559 }
5560 }
0837e86a 5561
16c1975f
MB		 5562 dev->profile = profile;
5563 dev->ib_active = true;
6aec21f6 5564
16c1975f 5565 return dev;
e126ba97 5566
16c1975f
MB		 5567err_out:
5568 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 5569
16c1975f
MB		 5570 return NULL;
5571}
0837e86a 5572
16c1975f
MB		 5573static const struct mlx5_ib_profile pf_profile = {
5574 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5575 mlx5_ib_stage_init_init,
5576 mlx5_ib_stage_init_cleanup),
9a4ca38d
MB		 5577 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5578 mlx5_ib_stage_flow_db_init,
5579 mlx5_ib_stage_flow_db_cleanup),
16c1975f
MB		 5580 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5581 mlx5_ib_stage_caps_init,
5582 NULL),
8e6efa3a
MB		 5583 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5584 mlx5_ib_stage_non_default_cb,
5585 NULL),
16c1975f
MB		 5586 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5587 mlx5_ib_stage_roce_init,
5588 mlx5_ib_stage_roce_cleanup),
5589 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5590 mlx5_ib_stage_dev_res_init,
5591 mlx5_ib_stage_dev_res_cleanup),
5592 STAGE_CREATE(MLX5_IB_STAGE_ODP,
5593 mlx5_ib_stage_odp_init,
3cc297db 5594 NULL),
16c1975f
MB		 5595 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5596 mlx5_ib_stage_counters_init,
5597 mlx5_ib_stage_counters_cleanup),
5598 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5599 mlx5_ib_stage_cong_debugfs_init,
5600 mlx5_ib_stage_cong_debugfs_cleanup),
5601 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5602 mlx5_ib_stage_uar_init,
5603 mlx5_ib_stage_uar_cleanup),
5604 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5605 mlx5_ib_stage_bfrag_init,
5606 mlx5_ib_stage_bfrag_cleanup),
42cea83f
MB		 5607 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5608 NULL,
5609 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 5610 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5611 mlx5_ib_stage_populate_specs,
5612 mlx5_ib_stage_depopulate_specs),
16c1975f
MB		 5613 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5614 mlx5_ib_stage_ib_reg_init,
5615 mlx5_ib_stage_ib_reg_cleanup),
42cea83f
MB		 5616 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5617 mlx5_ib_stage_post_ib_reg_umr_init,
5618 NULL),
16c1975f
MB		 5619 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5620 mlx5_ib_stage_delay_drop_init,
5621 mlx5_ib_stage_delay_drop_cleanup),
5622 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5623 mlx5_ib_stage_class_attr_init,
5624 NULL),
16c1975f 5625};
e126ba97 5626
b5ca15ad
MB		 5627static const struct mlx5_ib_profile nic_rep_profile = {
5628 STAGE_CREATE(MLX5_IB_STAGE_INIT,
5629 mlx5_ib_stage_init_init,
5630 mlx5_ib_stage_init_cleanup),
5631 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5632 mlx5_ib_stage_flow_db_init,
5633 mlx5_ib_stage_flow_db_cleanup),
5634 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5635 mlx5_ib_stage_caps_init,
5636 NULL),
5637 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5638 mlx5_ib_stage_rep_non_default_cb,
5639 NULL),
5640 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5641 mlx5_ib_stage_rep_roce_init,
5642 mlx5_ib_stage_rep_roce_cleanup),
5643 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5644 mlx5_ib_stage_dev_res_init,
5645 mlx5_ib_stage_dev_res_cleanup),
5646 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5647 mlx5_ib_stage_counters_init,
5648 mlx5_ib_stage_counters_cleanup),
5649 STAGE_CREATE(MLX5_IB_STAGE_UAR,
5650 mlx5_ib_stage_uar_init,
5651 mlx5_ib_stage_uar_cleanup),
5652 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5653 mlx5_ib_stage_bfrag_init,
5654 mlx5_ib_stage_bfrag_cleanup),
03fe2deb
DM		 5655 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5656 NULL,
5657 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
8c84660b
MB		 5658 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5659 mlx5_ib_stage_populate_specs,
5660 mlx5_ib_stage_depopulate_specs),
b5ca15ad
MB		 5661 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5662 mlx5_ib_stage_ib_reg_init,
5663 mlx5_ib_stage_ib_reg_cleanup),
03fe2deb
DM		 5664 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5665 mlx5_ib_stage_post_ib_reg_umr_init,
5666 NULL),
b5ca15ad
MB		 5667 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5668 mlx5_ib_stage_class_attr_init,
5669 NULL),
5670 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
5671 mlx5_ib_stage_rep_reg_init,
5672 mlx5_ib_stage_rep_reg_cleanup),
5673};
5674
32f69e4b
DJ		 5675static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5676{
5677 struct mlx5_ib_multiport_info *mpi;
5678 struct mlx5_ib_dev *dev;
5679 bool bound = false;
5680 int err;
5681
5682 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5683 if (!mpi)
5684 return NULL;
5685
5686 mpi->mdev = mdev;
5687
5688 err = mlx5_query_nic_vport_system_image_guid(mdev,
5689 &mpi->sys_image_guid);
5690 if (err) {
5691 kfree(mpi);
5692 return NULL;
5693 }
5694
5695 mutex_lock(&mlx5_ib_multiport_mutex);
5696 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5697 if (dev->sys_image_guid == mpi->sys_image_guid)
5698 bound = mlx5_ib_bind_slave_port(dev, mpi);
5699
5700 if (bound) {
5701 rdma_roce_rescan_device(&dev->ib_dev);
5702 break;
5703 }
5704 }
5705
5706 if (!bound) {
5707 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5708 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5709 } else {
5710 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5711 }
5712 mutex_unlock(&mlx5_ib_multiport_mutex);
5713
5714 return mpi;
5715}
5716
16c1975f
MB		 5717static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5718{
32f69e4b 5719 enum rdma_link_layer ll;
b5ca15ad 5720 struct mlx5_ib_dev *dev;
32f69e4b
DJ		 5721 int port_type_cap;
5722
b5ca15ad
MB		 5723 printk_once(KERN_INFO "%s", mlx5_version);
5724
32f69e4b
DJ		 5725 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5726 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5727
5728 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5729 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5730
5731 return mlx5_ib_add_slave_port(mdev, port_num);
5732 }
5733
b5ca15ad
MB		 5734 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
5735 if (!dev)
5736 return NULL;
5737
5738 dev->mdev = mdev;
5739 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5740 MLX5_CAP_GEN(mdev, num_vhca_ports));
5741
5742 if (MLX5_VPORT_MANAGER(mdev) &&
5743 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5744 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
5745
5746 return __mlx5_ib_add(dev, &nic_rep_profile);
5747 }
5748
5749 return __mlx5_ib_add(dev, &pf_profile);
e126ba97
EC		 5750}
5751
9603b61d 5752static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 5753{
32f69e4b
DJ		 5754 struct mlx5_ib_multiport_info *mpi;
5755 struct mlx5_ib_dev *dev;
5756
5757 if (mlx5_core_is_mp_slave(mdev)) {
5758 mpi = context;
5759 mutex_lock(&mlx5_ib_multiport_mutex);
5760 if (mpi->ibdev)
5761 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5762 list_del(&mpi->list);
5763 mutex_unlock(&mlx5_ib_multiport_mutex);
5764 return;
5765 }
6aec21f6 5766
32f69e4b 5767 dev = context;
16c1975f 5768 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 5769}
5770
9603b61d
JM		 5771static struct mlx5_interface mlx5_ib_interface = {
5772 .add = mlx5_ib_add,
5773 .remove = mlx5_ib_remove,
5774 .event = mlx5_ib_event,
d9aaed83
AK		 5775#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5776 .pfault = mlx5_ib_pfault,
5777#endif
64613d94 5778 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 5779};
5780
c44ef998
IL		 5781unsigned long mlx5_ib_get_xlt_emergency_page(void)
5782{
5783 mutex_lock(&xlt_emergency_page_mutex);
5784 return xlt_emergency_page;
5785}
5786
5787void mlx5_ib_put_xlt_emergency_page(void)
5788{
5789 mutex_unlock(&xlt_emergency_page_mutex);
5790}
5791
e126ba97
EC		 5792static int __init mlx5_ib_init(void)
5793{
6aec21f6
HE		 5794 int err;
5795
c44ef998
IL		 5796 xlt_emergency_page = __get_free_page(GFP_KERNEL);
5797 if (!xlt_emergency_page)
5798 return -ENOMEM;
5799
5800 mutex_init(&xlt_emergency_page_mutex);
5801
d69a24e0 5802 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
c44ef998
IL		 5803 if (!mlx5_ib_event_wq) {
5804 free_page(xlt_emergency_page);
d69a24e0 5805 return -ENOMEM;
c44ef998 5806 }
d69a24e0 5807
81713d37 5808 mlx5_ib_odp_init();
9603b61d 5809
6aec21f6 5810 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 5811
6aec21f6 5812 return err;
e126ba97
EC		 5813}
5814
5815static void __exit mlx5_ib_cleanup(void)
5816{
9603b61d 5817 mlx5_unregister_interface(&mlx5_ib_interface);
d69a24e0 5818 destroy_workqueue(mlx5_ib_event_wq);
c44ef998
IL		 5819 mutex_destroy(&xlt_emergency_page_mutex);
5820 free_page(xlt_emergency_page);
e126ba97
EC		 5821}
5822
5823module_init(mlx5_ib_init);
5824module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)