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IB/mlx5: Support IB device's callbacks for adding/deleting GIDs
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
3f89a643 43#include <rdma/ib_addr.h>
1b5daf11 44#include <linux/mlx5/vport.h>
e126ba97
EC		 45#include <rdma/ib_smi.h>
46#include <rdma/ib_umem.h>
47#include "user.h"
48#include "mlx5_ib.h"
49
50#define DRIVER_NAME "mlx5_ib"
169a1d85
AV		 51#define DRIVER_VERSION "2.2-1"
52#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 53
54MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
56MODULE_LICENSE("Dual BSD/GPL");
57MODULE_VERSION(DRIVER_VERSION);
58
9603b61d
JM		 59static int deprecated_prof_sel = 2;
60module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
61MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
e126ba97
EC		 62
63static char mlx5_version[] =
64 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
65 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
66
1b5daf11 67static enum rdma_link_layer
ebd61f68 68mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 69{
ebd61f68 70 switch (port_type_cap) {
1b5daf11
MD		 71 case MLX5_CAP_PORT_TYPE_IB:
72 return IB_LINK_LAYER_INFINIBAND;
73 case MLX5_CAP_PORT_TYPE_ETH:
74 return IB_LINK_LAYER_ETHERNET;
75 default:
76 return IB_LINK_LAYER_UNSPECIFIED;
77 }
78}
79
ebd61f68
AS		 80static enum rdma_link_layer
81mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
82{
83 struct mlx5_ib_dev *dev = to_mdev(device);
84 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
85
86 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
87}
88
fc24fc5e
AS		 89static int mlx5_netdev_event(struct notifier_block *this,
90 unsigned long event, void *ptr)
91{
92 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
93 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
94 roce.nb);
95
96 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
97 return NOTIFY_DONE;
98
99 write_lock(&ibdev->roce.netdev_lock);
100 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
101 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
102 write_unlock(&ibdev->roce.netdev_lock);
103
104 return NOTIFY_DONE;
105}
106
107static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
108 u8 port_num)
109{
110 struct mlx5_ib_dev *ibdev = to_mdev(device);
111 struct net_device *ndev;
112
113 /* Ensure ndev does not disappear before we invoke dev_hold()
114 */
115 read_lock(&ibdev->roce.netdev_lock);
116 ndev = ibdev->roce.netdev;
117 if (ndev)
118 dev_hold(ndev);
119 read_unlock(&ibdev->roce.netdev_lock);
120
121 return ndev;
122}
123
3f89a643
AS		 124static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
125 struct ib_port_attr *props)
126{
127 struct mlx5_ib_dev *dev = to_mdev(device);
128 struct net_device *ndev;
129 enum ib_mtu ndev_ib_mtu;
130
131 memset(props, 0, sizeof(*props));
132
133 props->port_cap_flags |= IB_PORT_CM_SUP;
134 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
135
136 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
137 roce_address_table_size);
138 props->max_mtu = IB_MTU_4096;
139 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
140 props->pkey_tbl_len = 1;
141 props->state = IB_PORT_DOWN;
142 props->phys_state = 3;
143
144 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev,
145 (u16 *)&props->qkey_viol_cntr);
146
147 ndev = mlx5_ib_get_netdev(device, port_num);
148 if (!ndev)
149 return 0;
150
151 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
152 props->state = IB_PORT_ACTIVE;
153 props->phys_state = 5;
154 }
155
156 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
157
158 dev_put(ndev);
159
160 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
161
162 props->active_width = IB_WIDTH_4X; /* TODO */
163 props->active_speed = IB_SPEED_QDR; /* TODO */
164
165 return 0;
166}
167
3cca2606
AS		 168static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
169 const struct ib_gid_attr *attr,
170 void *mlx5_addr)
171{
172#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
173 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
174 source_l3_address);
175 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
176 source_mac_47_32);
177
178 if (!gid)
179 return;
180
181 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
182
183 if (is_vlan_dev(attr->ndev)) {
184 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
185 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
186 }
187
188 switch (attr->gid_type) {
189 case IB_GID_TYPE_IB:
190 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
191 break;
192 case IB_GID_TYPE_ROCE_UDP_ENCAP:
193 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
194 break;
195
196 default:
197 WARN_ON(true);
198 }
199
200 if (attr->gid_type != IB_GID_TYPE_IB) {
201 if (ipv6_addr_v4mapped((void *)gid))
202 MLX5_SET_RA(mlx5_addr, roce_l3_type,
203 MLX5_ROCE_L3_TYPE_IPV4);
204 else
205 MLX5_SET_RA(mlx5_addr, roce_l3_type,
206 MLX5_ROCE_L3_TYPE_IPV6);
207 }
208
209 if ((attr->gid_type == IB_GID_TYPE_IB) ||
210 !ipv6_addr_v4mapped((void *)gid))
211 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
212 else
213 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
214}
215
216static int set_roce_addr(struct ib_device *device, u8 port_num,
217 unsigned int index,
218 const union ib_gid *gid,
219 const struct ib_gid_attr *attr)
220{
221 struct mlx5_ib_dev *dev = to_mdev(device);
222 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
223 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
224 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
225 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
226
227 if (ll != IB_LINK_LAYER_ETHERNET)
228 return -EINVAL;
229
230 memset(in, 0, sizeof(in));
231
232 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
233
234 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
235 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
236
237 memset(out, 0, sizeof(out));
238 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
239}
240
241static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
242 unsigned int index, const union ib_gid *gid,
243 const struct ib_gid_attr *attr,
244 __always_unused void **context)
245{
246 return set_roce_addr(device, port_num, index, gid, attr);
247}
248
249static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
250 unsigned int index, __always_unused void **context)
251{
252 return set_roce_addr(device, port_num, index, NULL, NULL);
253}
254
1b5daf11
MD		 255static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
256{
257 return !dev->mdev->issi;
258}
259
260enum {
261 MLX5_VPORT_ACCESS_METHOD_MAD,
262 MLX5_VPORT_ACCESS_METHOD_HCA,
263 MLX5_VPORT_ACCESS_METHOD_NIC,
264};
265
266static int mlx5_get_vport_access_method(struct ib_device *ibdev)
267{
268 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
269 return MLX5_VPORT_ACCESS_METHOD_MAD;
270
ebd61f68 271 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 272 IB_LINK_LAYER_ETHERNET)
273 return MLX5_VPORT_ACCESS_METHOD_NIC;
274
275 return MLX5_VPORT_ACCESS_METHOD_HCA;
276}
277
278static int mlx5_query_system_image_guid(struct ib_device *ibdev,
279 __be64 *sys_image_guid)
280{
281 struct mlx5_ib_dev *dev = to_mdev(ibdev);
282 struct mlx5_core_dev *mdev = dev->mdev;
283 u64 tmp;
284 int err;
285
286 switch (mlx5_get_vport_access_method(ibdev)) {
287 case MLX5_VPORT_ACCESS_METHOD_MAD:
288 return mlx5_query_mad_ifc_system_image_guid(ibdev,
289 sys_image_guid);
290
291 case MLX5_VPORT_ACCESS_METHOD_HCA:
292 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 293 break;
294
295 case MLX5_VPORT_ACCESS_METHOD_NIC:
296 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
297 break;
1b5daf11
MD		 298
299 default:
300 return -EINVAL;
301 }
3f89a643
AS		 302
303 if (!err)
304 *sys_image_guid = cpu_to_be64(tmp);
305
306 return err;
307
1b5daf11
MD		 308}
309
310static int mlx5_query_max_pkeys(struct ib_device *ibdev,
311 u16 *max_pkeys)
312{
313 struct mlx5_ib_dev *dev = to_mdev(ibdev);
314 struct mlx5_core_dev *mdev = dev->mdev;
315
316 switch (mlx5_get_vport_access_method(ibdev)) {
317 case MLX5_VPORT_ACCESS_METHOD_MAD:
318 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
319
320 case MLX5_VPORT_ACCESS_METHOD_HCA:
321 case MLX5_VPORT_ACCESS_METHOD_NIC:
322 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
323 pkey_table_size));
324 return 0;
325
326 default:
327 return -EINVAL;
328 }
329}
330
331static int mlx5_query_vendor_id(struct ib_device *ibdev,
332 u32 *vendor_id)
333{
334 struct mlx5_ib_dev *dev = to_mdev(ibdev);
335
336 switch (mlx5_get_vport_access_method(ibdev)) {
337 case MLX5_VPORT_ACCESS_METHOD_MAD:
338 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
339
340 case MLX5_VPORT_ACCESS_METHOD_HCA:
341 case MLX5_VPORT_ACCESS_METHOD_NIC:
342 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
343
344 default:
345 return -EINVAL;
346 }
347}
348
349static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
350 __be64 *node_guid)
351{
352 u64 tmp;
353 int err;
354
355 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
356 case MLX5_VPORT_ACCESS_METHOD_MAD:
357 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
358
359 case MLX5_VPORT_ACCESS_METHOD_HCA:
360 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 361 break;
362
363 case MLX5_VPORT_ACCESS_METHOD_NIC:
364 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
365 break;
1b5daf11
MD		 366
367 default:
368 return -EINVAL;
369 }
3f89a643
AS		 370
371 if (!err)
372 *node_guid = cpu_to_be64(tmp);
373
374 return err;
1b5daf11
MD		 375}
376
377struct mlx5_reg_node_desc {
378 u8 desc[64];
379};
380
381static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
382{
383 struct mlx5_reg_node_desc in;
384
385 if (mlx5_use_mad_ifc(dev))
386 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
387
388 memset(&in, 0, sizeof(in));
389
390 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
391 sizeof(struct mlx5_reg_node_desc),
392 MLX5_REG_NODE_DESC, 0, 0);
393}
394
e126ba97 395static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 396 struct ib_device_attr *props,
397 struct ib_udata *uhw)
e126ba97
EC		 398{
399 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 400 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97
EC		 401 int err = -ENOMEM;
402 int max_rq_sg;
403 int max_sq_sg;
e0238a6a 404 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
e126ba97 405
2528e33e
MB		 406 if (uhw->inlen || uhw->outlen)
407 return -EINVAL;
408
1b5daf11
MD		 409 memset(props, 0, sizeof(*props));
410 err = mlx5_query_system_image_guid(ibdev,
411 &props->sys_image_guid);
412 if (err)
413 return err;
e126ba97 414
1b5daf11 415 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 416 if (err)
1b5daf11 417 return err;
e126ba97 418
1b5daf11
MD		 419 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
420 if (err)
421 return err;
e126ba97 422
9603b61d
JM		 423 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
424 (fw_rev_min(dev->mdev) << 16) |
425 fw_rev_sub(dev->mdev);
e126ba97
EC		 426 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
427 IB_DEVICE_PORT_ACTIVE_EVENT |
428 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 429 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 430
431 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 432 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 433 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 434 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 435 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 436 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 437 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97
EC		 438 props->device_cap_flags |= IB_DEVICE_XRC;
439 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 440 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 441 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
442 /* At this stage no support for signature handover */
443 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
444 IB_PROT_T10DIF_TYPE_2 |
445 IB_PROT_T10DIF_TYPE_3;
446 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
447 IB_GUARD_T10DIF_CSUM;
448 }
938fe83c 449 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 450 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 451
1b5daf11
MD		 452 props->vendor_part_id = mdev->pdev->device;
453 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 454
455 props->max_mr_size = ~0ull;
e0238a6a 456 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 457 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
458 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
459 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
460 sizeof(struct mlx5_wqe_data_seg);
461 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
462 sizeof(struct mlx5_wqe_ctrl_seg)) /
463 sizeof(struct mlx5_wqe_data_seg);
e126ba97 464 props->max_sge = min(max_rq_sg, max_sq_sg);
18ebd407 465 props->max_sge_rd = props->max_sge;
938fe83c
SM		 466 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
467 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_eq_sz)) - 1;
468 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
469 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
470 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
471 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
472 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
473 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
474 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 475 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97
EC		 476 props->max_srq_sge = max_rq_sg - 1;
477 props->max_fast_reg_page_list_len = (unsigned int)-1;
81bea28f
EC		 478 props->atomic_cap = IB_ATOMIC_NONE;
479 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 480 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
481 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 482 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
483 props->max_mcast_grp;
484 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
485
8cdd312c 486#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 487 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 488 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
489 props->odp_caps = dev->odp_caps;
490#endif
491
1b5daf11 492 return 0;
e126ba97
EC		 493}
494
1b5daf11
MD		 495enum mlx5_ib_width {
496 MLX5_IB_WIDTH_1X = 1 << 0,
497 MLX5_IB_WIDTH_2X = 1 << 1,
498 MLX5_IB_WIDTH_4X = 1 << 2,
499 MLX5_IB_WIDTH_8X = 1 << 3,
500 MLX5_IB_WIDTH_12X = 1 << 4
501};
502
503static int translate_active_width(struct ib_device *ibdev, u8 active_width,
504 u8 *ib_width)
e126ba97
EC		 505{
506 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 507 int err = 0;
508
509 if (active_width & MLX5_IB_WIDTH_1X) {
510 *ib_width = IB_WIDTH_1X;
511 } else if (active_width & MLX5_IB_WIDTH_2X) {
512 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
513 (int)active_width);
514 err = -EINVAL;
515 } else if (active_width & MLX5_IB_WIDTH_4X) {
516 *ib_width = IB_WIDTH_4X;
517 } else if (active_width & MLX5_IB_WIDTH_8X) {
518 *ib_width = IB_WIDTH_8X;
519 } else if (active_width & MLX5_IB_WIDTH_12X) {
520 *ib_width = IB_WIDTH_12X;
521 } else {
522 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
523 (int)active_width);
524 err = -EINVAL;
e126ba97
EC		 525 }
526
1b5daf11
MD		 527 return err;
528}
e126ba97 529
1b5daf11
MD		 530static int mlx5_mtu_to_ib_mtu(int mtu)
531{
532 switch (mtu) {
533 case 256: return 1;
534 case 512: return 2;
535 case 1024: return 3;
536 case 2048: return 4;
537 case 4096: return 5;
538 default:
539 pr_warn("invalid mtu\n");
540 return -1;
e126ba97 541 }
1b5daf11 542}
e126ba97 543
1b5daf11
MD		 544enum ib_max_vl_num {
545 __IB_MAX_VL_0 = 1,
546 __IB_MAX_VL_0_1 = 2,
547 __IB_MAX_VL_0_3 = 3,
548 __IB_MAX_VL_0_7 = 4,
549 __IB_MAX_VL_0_14 = 5,
550};
e126ba97 551
1b5daf11
MD		 552enum mlx5_vl_hw_cap {
553 MLX5_VL_HW_0 = 1,
554 MLX5_VL_HW_0_1 = 2,
555 MLX5_VL_HW_0_2 = 3,
556 MLX5_VL_HW_0_3 = 4,
557 MLX5_VL_HW_0_4 = 5,
558 MLX5_VL_HW_0_5 = 6,
559 MLX5_VL_HW_0_6 = 7,
560 MLX5_VL_HW_0_7 = 8,
561 MLX5_VL_HW_0_14 = 15
562};
e126ba97 563
1b5daf11
MD		 564static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
565 u8 *max_vl_num)
566{
567 switch (vl_hw_cap) {
568 case MLX5_VL_HW_0:
569 *max_vl_num = __IB_MAX_VL_0;
570 break;
571 case MLX5_VL_HW_0_1:
572 *max_vl_num = __IB_MAX_VL_0_1;
573 break;
574 case MLX5_VL_HW_0_3:
575 *max_vl_num = __IB_MAX_VL_0_3;
576 break;
577 case MLX5_VL_HW_0_7:
578 *max_vl_num = __IB_MAX_VL_0_7;
579 break;
580 case MLX5_VL_HW_0_14:
581 *max_vl_num = __IB_MAX_VL_0_14;
582 break;
e126ba97 583
1b5daf11
MD		 584 default:
585 return -EINVAL;
e126ba97 586 }
e126ba97 587
1b5daf11 588 return 0;
e126ba97
EC		 589}
590
1b5daf11
MD		 591static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
592 struct ib_port_attr *props)
e126ba97 593{
1b5daf11
MD		 594 struct mlx5_ib_dev *dev = to_mdev(ibdev);
595 struct mlx5_core_dev *mdev = dev->mdev;
596 struct mlx5_hca_vport_context *rep;
597 int max_mtu;
598 int oper_mtu;
599 int err;
600 u8 ib_link_width_oper;
601 u8 vl_hw_cap;
e126ba97 602
1b5daf11
MD		 603 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
604 if (!rep) {
605 err = -ENOMEM;
e126ba97 606 goto out;
e126ba97 607 }
e126ba97 608
1b5daf11 609 memset(props, 0, sizeof(*props));
e126ba97 610
1b5daf11 611 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 612 if (err)
613 goto out;
614
1b5daf11
MD		 615 props->lid = rep->lid;
616 props->lmc = rep->lmc;
617 props->sm_lid = rep->sm_lid;
618 props->sm_sl = rep->sm_sl;
619 props->state = rep->vport_state;
620 props->phys_state = rep->port_physical_state;
621 props->port_cap_flags = rep->cap_mask1;
622 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
623 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
624 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
625 props->bad_pkey_cntr = rep->pkey_violation_counter;
626 props->qkey_viol_cntr = rep->qkey_violation_counter;
627 props->subnet_timeout = rep->subnet_timeout;
628 props->init_type_reply = rep->init_type_reply;
e126ba97 629
1b5daf11
MD		 630 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
631 if (err)
e126ba97 632 goto out;
e126ba97 633
1b5daf11
MD		 634 err = translate_active_width(ibdev, ib_link_width_oper,
635 &props->active_width);
636 if (err)
637 goto out;
638 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
639 port);
e126ba97
EC		 640 if (err)
641 goto out;
642
facc9699 643 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 644
1b5daf11 645 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 646
facc9699 647 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 648
1b5daf11 649 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 650
1b5daf11
MD		 651 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
652 if (err)
653 goto out;
e126ba97 654
1b5daf11
MD		 655 err = translate_max_vl_num(ibdev, vl_hw_cap,
656 &props->max_vl_num);
e126ba97 657out:
1b5daf11 658 kfree(rep);
e126ba97
EC		 659 return err;
660}
661
1b5daf11
MD		 662int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
663 struct ib_port_attr *props)
e126ba97 664{
1b5daf11
MD		 665 switch (mlx5_get_vport_access_method(ibdev)) {
666 case MLX5_VPORT_ACCESS_METHOD_MAD:
667 return mlx5_query_mad_ifc_port(ibdev, port, props);
e126ba97 668
1b5daf11
MD		 669 case MLX5_VPORT_ACCESS_METHOD_HCA:
670 return mlx5_query_hca_port(ibdev, port, props);
e126ba97 671
3f89a643
AS		 672 case MLX5_VPORT_ACCESS_METHOD_NIC:
673 return mlx5_query_port_roce(ibdev, port, props);
674
1b5daf11
MD		 675 default:
676 return -EINVAL;
677 }
678}
e126ba97 679
1b5daf11
MD		 680static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
681 union ib_gid *gid)
682{
683 struct mlx5_ib_dev *dev = to_mdev(ibdev);
684 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 685
1b5daf11
MD		 686 switch (mlx5_get_vport_access_method(ibdev)) {
687 case MLX5_VPORT_ACCESS_METHOD_MAD:
688 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 689
1b5daf11
MD		 690 case MLX5_VPORT_ACCESS_METHOD_HCA:
691 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
692
693 default:
694 return -EINVAL;
695 }
e126ba97 696
e126ba97
EC		 697}
698
1b5daf11
MD		 699static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
700 u16 *pkey)
701{
702 struct mlx5_ib_dev *dev = to_mdev(ibdev);
703 struct mlx5_core_dev *mdev = dev->mdev;
704
705 switch (mlx5_get_vport_access_method(ibdev)) {
706 case MLX5_VPORT_ACCESS_METHOD_MAD:
707 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
708
709 case MLX5_VPORT_ACCESS_METHOD_HCA:
710 case MLX5_VPORT_ACCESS_METHOD_NIC:
711 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
712 pkey);
713 default:
714 return -EINVAL;
715 }
716}
e126ba97
EC		 717
718static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
719 struct ib_device_modify *props)
720{
721 struct mlx5_ib_dev *dev = to_mdev(ibdev);
722 struct mlx5_reg_node_desc in;
723 struct mlx5_reg_node_desc out;
724 int err;
725
726 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
727 return -EOPNOTSUPP;
728
729 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
730 return 0;
731
732 /*
733 * If possible, pass node desc to FW, so it can generate
734 * a 144 trap. If cmd fails, just ignore.
735 */
736 memcpy(&in, props->node_desc, 64);
9603b61d 737 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 738 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
739 if (err)
740 return err;
741
742 memcpy(ibdev->node_desc, props->node_desc, 64);
743
744 return err;
745}
746
747static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
748 struct ib_port_modify *props)
749{
750 struct mlx5_ib_dev *dev = to_mdev(ibdev);
751 struct ib_port_attr attr;
752 u32 tmp;
753 int err;
754
755 mutex_lock(&dev->cap_mask_mutex);
756
757 err = mlx5_ib_query_port(ibdev, port, &attr);
758 if (err)
759 goto out;
760
761 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
762 ~props->clr_port_cap_mask;
763
9603b61d 764 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 765
766out:
767 mutex_unlock(&dev->cap_mask_mutex);
768 return err;
769}
770
771static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
772 struct ib_udata *udata)
773{
774 struct mlx5_ib_dev *dev = to_mdev(ibdev);
78c0f98c 775 struct mlx5_ib_alloc_ucontext_req_v2 req;
e126ba97
EC		 776 struct mlx5_ib_alloc_ucontext_resp resp;
777 struct mlx5_ib_ucontext *context;
778 struct mlx5_uuar_info *uuari;
779 struct mlx5_uar *uars;
c1be5232 780 int gross_uuars;
e126ba97 781 int num_uars;
78c0f98c 782 int ver;
e126ba97
EC		 783 int uuarn;
784 int err;
785 int i;
f241e749 786 size_t reqlen;
e126ba97
EC		 787
788 if (!dev->ib_active)
789 return ERR_PTR(-EAGAIN);
790
78c0f98c
EC		 791 memset(&req, 0, sizeof(req));
792 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
793 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
794 ver = 0;
795 else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
796 ver = 2;
797 else
798 return ERR_PTR(-EINVAL);
799
800 err = ib_copy_from_udata(&req, udata, reqlen);
e126ba97
EC		 801 if (err)
802 return ERR_PTR(err);
803
78c0f98c
EC		 804 if (req.flags || req.reserved)
805 return ERR_PTR(-EINVAL);
806
e126ba97
EC		 807 if (req.total_num_uuars > MLX5_MAX_UUARS)
808 return ERR_PTR(-ENOMEM);
809
810 if (req.total_num_uuars == 0)
811 return ERR_PTR(-EINVAL);
812
c1be5232
EC		 813 req.total_num_uuars = ALIGN(req.total_num_uuars,
814 MLX5_NON_FP_BF_REGS_PER_PAGE);
e126ba97
EC		 815 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
816 return ERR_PTR(-EINVAL);
817
c1be5232
EC		 818 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
819 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
938fe83c
SM		 820 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
821 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
822 resp.cache_line_size = L1_CACHE_BYTES;
823 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
824 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
825 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
826 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
827 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
e126ba97
EC		 828
829 context = kzalloc(sizeof(*context), GFP_KERNEL);
830 if (!context)
831 return ERR_PTR(-ENOMEM);
832
833 uuari = &context->uuari;
834 mutex_init(&uuari->lock);
835 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
836 if (!uars) {
837 err = -ENOMEM;
838 goto out_ctx;
839 }
840
c1be5232 841 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
e126ba97
EC		 842 sizeof(*uuari->bitmap),
843 GFP_KERNEL);
844 if (!uuari->bitmap) {
845 err = -ENOMEM;
846 goto out_uar_ctx;
847 }
848 /*
849 * clear all fast path uuars
850 */
c1be5232 851 for (i = 0; i < gross_uuars; i++) {
e126ba97
EC		 852 uuarn = i & 3;
853 if (uuarn == 2 || uuarn == 3)
854 set_bit(i, uuari->bitmap);
855 }
856
c1be5232 857 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
e126ba97
EC		 858 if (!uuari->count) {
859 err = -ENOMEM;
860 goto out_bitmap;
861 }
862
863 for (i = 0; i < num_uars; i++) {
9603b61d 864 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
e126ba97
EC		 865 if (err)
866 goto out_count;
867 }
868
b4cfe447
HE		 869#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
870 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
871#endif
872
e126ba97
EC		 873 INIT_LIST_HEAD(&context->db_page_list);
874 mutex_init(&context->db_page_mutex);
875
876 resp.tot_uuars = req.total_num_uuars;
938fe83c 877 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
92b0ca7c
DC		 878 err = ib_copy_to_udata(udata, &resp,
879 sizeof(resp) - sizeof(resp.reserved));
e126ba97
EC		 880 if (err)
881 goto out_uars;
882
78c0f98c 883 uuari->ver = ver;
e126ba97
EC		 884 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
885 uuari->uars = uars;
886 uuari->num_uars = num_uars;
887 return &context->ibucontext;
888
889out_uars:
890 for (i--; i >= 0; i--)
9603b61d 891 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
e126ba97
EC		 892out_count:
893 kfree(uuari->count);
894
895out_bitmap:
896 kfree(uuari->bitmap);
897
898out_uar_ctx:
899 kfree(uars);
900
901out_ctx:
902 kfree(context);
903 return ERR_PTR(err);
904}
905
906static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
907{
908 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
909 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
910 struct mlx5_uuar_info *uuari = &context->uuari;
911 int i;
912
913 for (i = 0; i < uuari->num_uars; i++) {
9603b61d 914 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
e126ba97
EC		 915 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
916 }
917
918 kfree(uuari->count);
919 kfree(uuari->bitmap);
920 kfree(uuari->uars);
921 kfree(context);
922
923 return 0;
924}
925
926static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
927{
9603b61d 928 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
e126ba97
EC		 929}
930
931static int get_command(unsigned long offset)
932{
933 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
934}
935
936static int get_arg(unsigned long offset)
937{
938 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
939}
940
941static int get_index(unsigned long offset)
942{
943 return get_arg(offset);
944}
945
946static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
947{
948 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
949 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
950 struct mlx5_uuar_info *uuari = &context->uuari;
951 unsigned long command;
952 unsigned long idx;
953 phys_addr_t pfn;
954
955 command = get_command(vma->vm_pgoff);
956 switch (command) {
957 case MLX5_IB_MMAP_REGULAR_PAGE:
958 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
959 return -EINVAL;
960
961 idx = get_index(vma->vm_pgoff);
1c3ce90d
EC		 962 if (idx >= uuari->num_uars)
963 return -EINVAL;
964
e126ba97
EC		 965 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
966 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
967 (unsigned long long)pfn);
968
e126ba97
EC		 969 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
970 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
971 PAGE_SIZE, vma->vm_page_prot))
972 return -EAGAIN;
973
974 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
975 vma->vm_start,
976 (unsigned long long)pfn << PAGE_SHIFT);
977 break;
978
979 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
980 return -ENOSYS;
981
982 default:
983 return -EINVAL;
984 }
985
986 return 0;
987}
988
e126ba97
EC		 989static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
990 struct ib_ucontext *context,
991 struct ib_udata *udata)
992{
993 struct mlx5_ib_alloc_pd_resp resp;
994 struct mlx5_ib_pd *pd;
995 int err;
996
997 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
998 if (!pd)
999 return ERR_PTR(-ENOMEM);
1000
9603b61d 1001 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 1002 if (err) {
1003 kfree(pd);
1004 return ERR_PTR(err);
1005 }
1006
1007 if (context) {
1008 resp.pdn = pd->pdn;
1009 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 1010 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 1011 kfree(pd);
1012 return ERR_PTR(-EFAULT);
1013 }
e126ba97
EC		 1014 }
1015
1016 return &pd->ibpd;
1017}
1018
1019static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1020{
1021 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1022 struct mlx5_ib_pd *mpd = to_mpd(pd);
1023
9603b61d 1024 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 1025 kfree(mpd);
1026
1027 return 0;
1028}
1029
1030static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1031{
1032 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1033 int err;
1034
9603b61d 1035 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1036 if (err)
1037 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1038 ibqp->qp_num, gid->raw);
1039
1040 return err;
1041}
1042
1043static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1044{
1045 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1046 int err;
1047
9603b61d 1048 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 1049 if (err)
1050 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1051 ibqp->qp_num, gid->raw);
1052
1053 return err;
1054}
1055
1056static int init_node_data(struct mlx5_ib_dev *dev)
1057{
1b5daf11 1058 int err;
e126ba97 1059
1b5daf11 1060 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 1061 if (err)
1b5daf11 1062 return err;
e126ba97 1063
1b5daf11 1064 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 1065
1b5daf11 1066 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 1067}
1068
1069static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1070 char *buf)
1071{
1072 struct mlx5_ib_dev *dev =
1073 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1074
9603b61d 1075 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 1076}
1077
1078static ssize_t show_reg_pages(struct device *device,
1079 struct device_attribute *attr, char *buf)
1080{
1081 struct mlx5_ib_dev *dev =
1082 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1083
6aec21f6 1084 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 1085}
1086
1087static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1088 char *buf)
1089{
1090 struct mlx5_ib_dev *dev =
1091 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1092 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 1093}
1094
1095static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1096 char *buf)
1097{
1098 struct mlx5_ib_dev *dev =
1099 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d
JM		 1100 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1101 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
e126ba97
EC		 1102}
1103
1104static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1105 char *buf)
1106{
1107 struct mlx5_ib_dev *dev =
1108 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 1109 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 1110}
1111
1112static ssize_t show_board(struct device *device, struct device_attribute *attr,
1113 char *buf)
1114{
1115 struct mlx5_ib_dev *dev =
1116 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1117 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 1118 dev->mdev->board_id);
e126ba97
EC		 1119}
1120
1121static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1122static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1123static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1124static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1125static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1126static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1127
1128static struct device_attribute *mlx5_class_attributes[] = {
1129 &dev_attr_hw_rev,
1130 &dev_attr_fw_ver,
1131 &dev_attr_hca_type,
1132 &dev_attr_board_id,
1133 &dev_attr_fw_pages,
1134 &dev_attr_reg_pages,
1135};
1136
9603b61d 1137static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 1138 enum mlx5_dev_event event, unsigned long param)
e126ba97 1139{
9603b61d 1140 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 1141 struct ib_event ibev;
9603b61d 1142
e126ba97
EC		 1143 u8 port = 0;
1144
1145 switch (event) {
1146 case MLX5_DEV_EVENT_SYS_ERROR:
1147 ibdev->ib_active = false;
1148 ibev.event = IB_EVENT_DEVICE_FATAL;
1149 break;
1150
1151 case MLX5_DEV_EVENT_PORT_UP:
1152 ibev.event = IB_EVENT_PORT_ACTIVE;
4d2f9bbb 1153 port = (u8)param;
e126ba97
EC		 1154 break;
1155
1156 case MLX5_DEV_EVENT_PORT_DOWN:
1157 ibev.event = IB_EVENT_PORT_ERR;
4d2f9bbb 1158 port = (u8)param;
e126ba97
EC		 1159 break;
1160
1161 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1162 /* not used by ULPs */
1163 return;
1164
1165 case MLX5_DEV_EVENT_LID_CHANGE:
1166 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 1167 port = (u8)param;
e126ba97
EC		 1168 break;
1169
1170 case MLX5_DEV_EVENT_PKEY_CHANGE:
1171 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 1172 port = (u8)param;
e126ba97
EC		 1173 break;
1174
1175 case MLX5_DEV_EVENT_GUID_CHANGE:
1176 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 1177 port = (u8)param;
e126ba97
EC		 1178 break;
1179
1180 case MLX5_DEV_EVENT_CLIENT_REREG:
1181 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 1182 port = (u8)param;
e126ba97
EC		 1183 break;
1184 }
1185
1186 ibev.device = &ibdev->ib_dev;
1187 ibev.element.port_num = port;
1188
a0c84c32
EC		 1189 if (port < 1 || port > ibdev->num_ports) {
1190 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1191 return;
1192 }
1193
e126ba97
EC		 1194 if (ibdev->ib_active)
1195 ib_dispatch_event(&ibev);
1196}
1197
1198static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1199{
1200 int port;
1201
938fe83c 1202 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
e126ba97
EC		 1203 mlx5_query_ext_port_caps(dev, port);
1204}
1205
1206static int get_port_caps(struct mlx5_ib_dev *dev)
1207{
1208 struct ib_device_attr *dprops = NULL;
1209 struct ib_port_attr *pprops = NULL;
f614fc15 1210 int err = -ENOMEM;
e126ba97 1211 int port;
2528e33e 1212 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 1213
1214 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1215 if (!pprops)
1216 goto out;
1217
1218 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1219 if (!dprops)
1220 goto out;
1221
2528e33e 1222 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 1223 if (err) {
1224 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1225 goto out;
1226 }
1227
938fe83c 1228 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
e126ba97
EC		 1229 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1230 if (err) {
938fe83c
SM		 1231 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1232 port, err);
e126ba97
EC		 1233 break;
1234 }
938fe83c
SM		 1235 dev->mdev->port_caps[port - 1].pkey_table_len =
1236 dprops->max_pkeys;
1237 dev->mdev->port_caps[port - 1].gid_table_len =
1238 pprops->gid_tbl_len;
e126ba97
EC		 1239 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1240 dprops->max_pkeys, pprops->gid_tbl_len);
1241 }
1242
1243out:
1244 kfree(pprops);
1245 kfree(dprops);
1246
1247 return err;
1248}
1249
1250static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1251{
1252 int err;
1253
1254 err = mlx5_mr_cache_cleanup(dev);
1255 if (err)
1256 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1257
1258 mlx5_ib_destroy_qp(dev->umrc.qp);
1259 ib_destroy_cq(dev->umrc.cq);
e126ba97
EC		 1260 ib_dealloc_pd(dev->umrc.pd);
1261}
1262
1263enum {
1264 MAX_UMR_WR = 128,
1265};
1266
1267static int create_umr_res(struct mlx5_ib_dev *dev)
1268{
1269 struct ib_qp_init_attr *init_attr = NULL;
1270 struct ib_qp_attr *attr = NULL;
1271 struct ib_pd *pd;
1272 struct ib_cq *cq;
1273 struct ib_qp *qp;
8e37210b 1274 struct ib_cq_init_attr cq_attr = {};
e126ba97
EC		 1275 int ret;
1276
1277 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1278 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1279 if (!attr || !init_attr) {
1280 ret = -ENOMEM;
1281 goto error_0;
1282 }
1283
1284 pd = ib_alloc_pd(&dev->ib_dev);
1285 if (IS_ERR(pd)) {
1286 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1287 ret = PTR_ERR(pd);
1288 goto error_0;
1289 }
1290
8e37210b
MB		 1291 cq_attr.cqe = 128;
1292 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
1293 &cq_attr);
e126ba97
EC		 1294 if (IS_ERR(cq)) {
1295 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1296 ret = PTR_ERR(cq);
1297 goto error_2;
1298 }
1299 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1300
1301 init_attr->send_cq = cq;
1302 init_attr->recv_cq = cq;
1303 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1304 init_attr->cap.max_send_wr = MAX_UMR_WR;
1305 init_attr->cap.max_send_sge = 1;
1306 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1307 init_attr->port_num = 1;
1308 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1309 if (IS_ERR(qp)) {
1310 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1311 ret = PTR_ERR(qp);
1312 goto error_3;
1313 }
1314 qp->device = &dev->ib_dev;
1315 qp->real_qp = qp;
1316 qp->uobject = NULL;
1317 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1318
1319 attr->qp_state = IB_QPS_INIT;
1320 attr->port_num = 1;
1321 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1322 IB_QP_PORT, NULL);
1323 if (ret) {
1324 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1325 goto error_4;
1326 }
1327
1328 memset(attr, 0, sizeof(*attr));
1329 attr->qp_state = IB_QPS_RTR;
1330 attr->path_mtu = IB_MTU_256;
1331
1332 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1333 if (ret) {
1334 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1335 goto error_4;
1336 }
1337
1338 memset(attr, 0, sizeof(*attr));
1339 attr->qp_state = IB_QPS_RTS;
1340 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1341 if (ret) {
1342 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1343 goto error_4;
1344 }
1345
1346 dev->umrc.qp = qp;
1347 dev->umrc.cq = cq;
e126ba97
EC		 1348 dev->umrc.pd = pd;
1349
1350 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1351 ret = mlx5_mr_cache_init(dev);
1352 if (ret) {
1353 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1354 goto error_4;
1355 }
1356
1357 kfree(attr);
1358 kfree(init_attr);
1359
1360 return 0;
1361
1362error_4:
1363 mlx5_ib_destroy_qp(qp);
1364
1365error_3:
1366 ib_destroy_cq(cq);
1367
1368error_2:
e126ba97
EC		 1369 ib_dealloc_pd(pd);
1370
1371error_0:
1372 kfree(attr);
1373 kfree(init_attr);
1374 return ret;
1375}
1376
1377static int create_dev_resources(struct mlx5_ib_resources *devr)
1378{
1379 struct ib_srq_init_attr attr;
1380 struct mlx5_ib_dev *dev;
bcf4c1ea 1381 struct ib_cq_init_attr cq_attr = {.cqe = 1};
e126ba97
EC		 1382 int ret = 0;
1383
1384 dev = container_of(devr, struct mlx5_ib_dev, devr);
1385
1386 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1387 if (IS_ERR(devr->p0)) {
1388 ret = PTR_ERR(devr->p0);
1389 goto error0;
1390 }
1391 devr->p0->device = &dev->ib_dev;
1392 devr->p0->uobject = NULL;
1393 atomic_set(&devr->p0->usecnt, 0);
1394
bcf4c1ea 1395 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 1396 if (IS_ERR(devr->c0)) {
1397 ret = PTR_ERR(devr->c0);
1398 goto error1;
1399 }
1400 devr->c0->device = &dev->ib_dev;
1401 devr->c0->uobject = NULL;
1402 devr->c0->comp_handler = NULL;
1403 devr->c0->event_handler = NULL;
1404 devr->c0->cq_context = NULL;
1405 atomic_set(&devr->c0->usecnt, 0);
1406
1407 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1408 if (IS_ERR(devr->x0)) {
1409 ret = PTR_ERR(devr->x0);
1410 goto error2;
1411 }
1412 devr->x0->device = &dev->ib_dev;
1413 devr->x0->inode = NULL;
1414 atomic_set(&devr->x0->usecnt, 0);
1415 mutex_init(&devr->x0->tgt_qp_mutex);
1416 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1417
1418 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1419 if (IS_ERR(devr->x1)) {
1420 ret = PTR_ERR(devr->x1);
1421 goto error3;
1422 }
1423 devr->x1->device = &dev->ib_dev;
1424 devr->x1->inode = NULL;
1425 atomic_set(&devr->x1->usecnt, 0);
1426 mutex_init(&devr->x1->tgt_qp_mutex);
1427 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1428
1429 memset(&attr, 0, sizeof(attr));
1430 attr.attr.max_sge = 1;
1431 attr.attr.max_wr = 1;
1432 attr.srq_type = IB_SRQT_XRC;
1433 attr.ext.xrc.cq = devr->c0;
1434 attr.ext.xrc.xrcd = devr->x0;
1435
1436 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1437 if (IS_ERR(devr->s0)) {
1438 ret = PTR_ERR(devr->s0);
1439 goto error4;
1440 }
1441 devr->s0->device = &dev->ib_dev;
1442 devr->s0->pd = devr->p0;
1443 devr->s0->uobject = NULL;
1444 devr->s0->event_handler = NULL;
1445 devr->s0->srq_context = NULL;
1446 devr->s0->srq_type = IB_SRQT_XRC;
1447 devr->s0->ext.xrc.xrcd = devr->x0;
1448 devr->s0->ext.xrc.cq = devr->c0;
1449 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1450 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1451 atomic_inc(&devr->p0->usecnt);
1452 atomic_set(&devr->s0->usecnt, 0);
1453
4aa17b28
HA		 1454 memset(&attr, 0, sizeof(attr));
1455 attr.attr.max_sge = 1;
1456 attr.attr.max_wr = 1;
1457 attr.srq_type = IB_SRQT_BASIC;
1458 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1459 if (IS_ERR(devr->s1)) {
1460 ret = PTR_ERR(devr->s1);
1461 goto error5;
1462 }
1463 devr->s1->device = &dev->ib_dev;
1464 devr->s1->pd = devr->p0;
1465 devr->s1->uobject = NULL;
1466 devr->s1->event_handler = NULL;
1467 devr->s1->srq_context = NULL;
1468 devr->s1->srq_type = IB_SRQT_BASIC;
1469 devr->s1->ext.xrc.cq = devr->c0;
1470 atomic_inc(&devr->p0->usecnt);
1471 atomic_set(&devr->s0->usecnt, 0);
1472
e126ba97
EC		 1473 return 0;
1474
4aa17b28
HA		 1475error5:
1476 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 1477error4:
1478 mlx5_ib_dealloc_xrcd(devr->x1);
1479error3:
1480 mlx5_ib_dealloc_xrcd(devr->x0);
1481error2:
1482 mlx5_ib_destroy_cq(devr->c0);
1483error1:
1484 mlx5_ib_dealloc_pd(devr->p0);
1485error0:
1486 return ret;
1487}
1488
1489static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1490{
4aa17b28 1491 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 1492 mlx5_ib_destroy_srq(devr->s0);
1493 mlx5_ib_dealloc_xrcd(devr->x0);
1494 mlx5_ib_dealloc_xrcd(devr->x1);
1495 mlx5_ib_destroy_cq(devr->c0);
1496 mlx5_ib_dealloc_pd(devr->p0);
1497}
1498
7738613e
IW		 1499static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
1500 struct ib_port_immutable *immutable)
1501{
1502 struct ib_port_attr attr;
1503 int err;
1504
1505 err = mlx5_ib_query_port(ibdev, port_num, &attr);
1506 if (err)
1507 return err;
1508
1509 immutable->pkey_tbl_len = attr.pkey_tbl_len;
1510 immutable->gid_tbl_len = attr.gid_tbl_len;
f9b22e35 1511 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
337877a4 1512 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 1513
1514 return 0;
1515}
1516
fc24fc5e
AS		 1517static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
1518{
1519 dev->roce.nb.notifier_call = mlx5_netdev_event;
1520 return register_netdevice_notifier(&dev->roce.nb);
1521}
1522
1523static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
1524{
1525 unregister_netdevice_notifier(&dev->roce.nb);
1526}
1527
9603b61d 1528static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
e126ba97 1529{
e126ba97 1530 struct mlx5_ib_dev *dev;
ebd61f68
AS		 1531 enum rdma_link_layer ll;
1532 int port_type_cap;
e126ba97
EC		 1533 int err;
1534 int i;
1535
ebd61f68
AS		 1536 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
1537 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
1538
647241ea 1539 /* don't create IB instance over Eth ports, no RoCE yet! */
ebd61f68 1540 if (ll == IB_LINK_LAYER_ETHERNET)
647241ea
MD		 1541 return NULL;
1542
e126ba97
EC		 1543 printk_once(KERN_INFO "%s", mlx5_version);
1544
1545 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1546 if (!dev)
9603b61d 1547 return NULL;
e126ba97 1548
9603b61d 1549 dev->mdev = mdev;
e126ba97 1550
fc24fc5e 1551 rwlock_init(&dev->roce.netdev_lock);
e126ba97
EC		 1552 err = get_port_caps(dev);
1553 if (err)
9603b61d 1554 goto err_dealloc;
e126ba97 1555
1b5daf11
MD		 1556 if (mlx5_use_mad_ifc(dev))
1557 get_ext_port_caps(dev);
e126ba97 1558
e126ba97
EC		 1559 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1560
1561 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1562 dev->ib_dev.owner = THIS_MODULE;
1563 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 1564 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
938fe83c 1565 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
e126ba97 1566 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 1567 dev->ib_dev.num_comp_vectors =
1568 dev->mdev->priv.eq_table.num_comp_vectors;
e126ba97
EC		 1569 dev->ib_dev.dma_device = &mdev->pdev->dev;
1570
1571 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1572 dev->ib_dev.uverbs_cmd_mask =
1573 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1574 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1575 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1576 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1577 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1578 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1579 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1580 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1581 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1582 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1583 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1584 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1585 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1586 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1587 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1588 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1589 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1590 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1591 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1592 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1593 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1594 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1595 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a
HE		 1596 dev->ib_dev.uverbs_ex_cmd_mask =
1597 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
e126ba97
EC		 1598
1599 dev->ib_dev.query_device = mlx5_ib_query_device;
1600 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 1601 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
fc24fc5e
AS		 1602 if (ll == IB_LINK_LAYER_ETHERNET)
1603 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
e126ba97 1604 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 1605 dev->ib_dev.add_gid = mlx5_ib_add_gid;
1606 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 1607 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1608 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1609 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1610 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1611 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1612 dev->ib_dev.mmap = mlx5_ib_mmap;
1613 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1614 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1615 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1616 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1617 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1618 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1619 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1620 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1621 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1622 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1623 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1624 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1625 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1626 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1627 dev->ib_dev.post_send = mlx5_ib_post_send;
1628 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1629 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1630 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1631 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1632 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1633 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1634 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1635 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1636 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1637 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
1638 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1639 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1640 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 1641 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 1642 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 1643 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 1644 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
e126ba97 1645
938fe83c 1646 mlx5_ib_internal_fill_odp_caps(dev);
8cdd312c 1647
938fe83c 1648 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 1649 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1650 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1651 dev->ib_dev.uverbs_cmd_mask |=
1652 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1653 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1654 }
1655
1656 err = init_node_data(dev);
1657 if (err)
233d05d2 1658 goto err_dealloc;
e126ba97
EC		 1659
1660 mutex_init(&dev->cap_mask_mutex);
e126ba97 1661
fc24fc5e
AS		 1662 if (ll == IB_LINK_LAYER_ETHERNET) {
1663 err = mlx5_enable_roce(dev);
1664 if (err)
1665 goto err_dealloc;
1666 }
1667
e126ba97
EC		 1668 err = create_dev_resources(&dev->devr);
1669 if (err)
fc24fc5e 1670 goto err_disable_roce;
e126ba97 1671
6aec21f6 1672 err = mlx5_ib_odp_init_one(dev);
281d1a92 1673 if (err)
e126ba97
EC		 1674 goto err_rsrc;
1675
6aec21f6
HE		 1676 err = ib_register_device(&dev->ib_dev, NULL);
1677 if (err)
1678 goto err_odp;
1679
e126ba97
EC		 1680 err = create_umr_res(dev);
1681 if (err)
1682 goto err_dev;
1683
1684 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 1685 err = device_create_file(&dev->ib_dev.dev,
1686 mlx5_class_attributes[i]);
1687 if (err)
e126ba97
EC		 1688 goto err_umrc;
1689 }
1690
1691 dev->ib_active = true;
1692
9603b61d 1693 return dev;
e126ba97
EC		 1694
1695err_umrc:
1696 destroy_umrc_res(dev);
1697
1698err_dev:
1699 ib_unregister_device(&dev->ib_dev);
1700
6aec21f6
HE		 1701err_odp:
1702 mlx5_ib_odp_remove_one(dev);
1703
e126ba97
EC		 1704err_rsrc:
1705 destroy_dev_resources(&dev->devr);
1706
fc24fc5e
AS		 1707err_disable_roce:
1708 if (ll == IB_LINK_LAYER_ETHERNET)
1709 mlx5_disable_roce(dev);
1710
9603b61d 1711err_dealloc:
e126ba97
EC		 1712 ib_dealloc_device((struct ib_device *)dev);
1713
9603b61d 1714 return NULL;
e126ba97
EC		 1715}
1716
9603b61d 1717static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 1718{
9603b61d 1719 struct mlx5_ib_dev *dev = context;
fc24fc5e 1720 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
6aec21f6 1721
e126ba97 1722 ib_unregister_device(&dev->ib_dev);
eefd56e5 1723 destroy_umrc_res(dev);
6aec21f6 1724 mlx5_ib_odp_remove_one(dev);
e126ba97 1725 destroy_dev_resources(&dev->devr);
fc24fc5e
AS		 1726 if (ll == IB_LINK_LAYER_ETHERNET)
1727 mlx5_disable_roce(dev);
e126ba97
EC		 1728 ib_dealloc_device(&dev->ib_dev);
1729}
1730
9603b61d
JM		 1731static struct mlx5_interface mlx5_ib_interface = {
1732 .add = mlx5_ib_add,
1733 .remove = mlx5_ib_remove,
1734 .event = mlx5_ib_event,
64613d94 1735 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 1736};
1737
1738static int __init mlx5_ib_init(void)
1739{
6aec21f6
HE		 1740 int err;
1741
9603b61d
JM		 1742 if (deprecated_prof_sel != 2)
1743 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
1744
6aec21f6
HE		 1745 err = mlx5_ib_odp_init();
1746 if (err)
1747 return err;
1748
1749 err = mlx5_register_interface(&mlx5_ib_interface);
1750 if (err)
1751 goto clean_odp;
1752
1753 return err;
1754
1755clean_odp:
1756 mlx5_ib_odp_cleanup();
1757 return err;
e126ba97
EC		 1758}
1759
1760static void __exit mlx5_ib_cleanup(void)
1761{
9603b61d 1762 mlx5_unregister_interface(&mlx5_ib_interface);
6aec21f6 1763 mlx5_ib_odp_cleanup();
e126ba97
EC		 1764}
1765
1766module_init(mlx5_ib_init);
1767module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)