projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
{net, IB}/mlx5: Manage port association for multiport RoCE
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
fe248c3a 33#include <linux/debugfs.h>
adec640e 34#include <linux/highmem.h>
e126ba97
EC		 35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
37aa5c36
GL		 41#if defined(CONFIG_X86)
42#include <asm/pat.h>
43#endif
e126ba97 44#include <linux/sched.h>
6e84f315 45#include <linux/sched/mm.h>
0881e7bd 46#include <linux/sched/task.h>
7c2344c3 47#include <linux/delay.h>
e126ba97 48#include <rdma/ib_user_verbs.h>
3f89a643 49#include <rdma/ib_addr.h>
2811ba51 50#include <rdma/ib_cache.h>
ada68c31 51#include <linux/mlx5/port.h>
1b5daf11 52#include <linux/mlx5/vport.h>
72c7fe90 53#include <linux/mlx5/fs.h>
7c2344c3 54#include <linux/list.h>
e126ba97
EC		 55#include <rdma/ib_smi.h>
56#include <rdma/ib_umem.h>
038d2ef8
MG		 57#include <linux/in.h>
58#include <linux/etherdevice.h>
e126ba97 59#include "mlx5_ib.h"
e1f24a79 60#include "cmd.h"
e126ba97
EC		 61
62#define DRIVER_NAME "mlx5_ib"
b359911d 63#define DRIVER_VERSION "5.0-0"
e126ba97
EC		 64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67MODULE_LICENSE("Dual BSD/GPL");
e126ba97 68
e126ba97
EC		 69static char mlx5_version[] =
70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
b359911d 71 DRIVER_VERSION "\n";
e126ba97 72
da7525d2
EBE		 73enum {
74 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
75};
76
32f69e4b
DJ		 77static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
78static LIST_HEAD(mlx5_ib_dev_list);
79/*
80 * This mutex should be held when accessing either of the above lists
81 */
82static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
83
84struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
85{
86 struct mlx5_ib_dev *dev;
87
88 mutex_lock(&mlx5_ib_multiport_mutex);
89 dev = mpi->ibdev;
90 mutex_unlock(&mlx5_ib_multiport_mutex);
91 return dev;
92}
93
1b5daf11 94static enum rdma_link_layer
ebd61f68 95mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
1b5daf11 96{
ebd61f68 97 switch (port_type_cap) {
1b5daf11
MD		 98 case MLX5_CAP_PORT_TYPE_IB:
99 return IB_LINK_LAYER_INFINIBAND;
100 case MLX5_CAP_PORT_TYPE_ETH:
101 return IB_LINK_LAYER_ETHERNET;
102 default:
103 return IB_LINK_LAYER_UNSPECIFIED;
104 }
105}
106
ebd61f68
AS		 107static enum rdma_link_layer
108mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
109{
110 struct mlx5_ib_dev *dev = to_mdev(device);
111 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
112
113 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
114}
115
fd65f1b8
MS		 116static int get_port_state(struct ib_device *ibdev,
117 u8 port_num,
118 enum ib_port_state *state)
119{
120 struct ib_port_attr attr;
121 int ret;
122
123 memset(&attr, 0, sizeof(attr));
124 ret = mlx5_ib_query_port(ibdev, port_num, &attr);
125 if (!ret)
126 *state = attr.state;
127 return ret;
128}
129
fc24fc5e
AS		 130static int mlx5_netdev_event(struct notifier_block *this,
131 unsigned long event, void *ptr)
132{
7fd8aefb 133 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
fc24fc5e 134 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
7fd8aefb
DJ		 135 u8 port_num = roce->native_port_num;
136 struct mlx5_core_dev *mdev;
137 struct mlx5_ib_dev *ibdev;
138
139 ibdev = roce->dev;
32f69e4b
DJ		 140 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
141 if (!mdev)
142 return NOTIFY_DONE;
fc24fc5e 143
5ec8c83e
AH		 144 switch (event) {
145 case NETDEV_REGISTER:
146 case NETDEV_UNREGISTER:
7fd8aefb
DJ		 147 write_lock(&roce->netdev_lock);
148
149 if (ndev->dev.parent == &mdev->pdev->dev)
150 roce->netdev = (event == NETDEV_UNREGISTER) ?
151 NULL : ndev;
152 write_unlock(&roce->netdev_lock);
5ec8c83e 153 break;
fc24fc5e 154
fd65f1b8 155 case NETDEV_CHANGE:
5ec8c83e 156 case NETDEV_UP:
88621dfe 157 case NETDEV_DOWN: {
7fd8aefb 158 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe
AH		 159 struct net_device *upper = NULL;
160
161 if (lag_ndev) {
162 upper = netdev_master_upper_dev_get(lag_ndev);
163 dev_put(lag_ndev);
164 }
165
7fd8aefb 166 if ((upper == ndev || (!upper && ndev == roce->netdev))
88621dfe 167 && ibdev->ib_active) {
626bc02d 168 struct ib_event ibev = { };
fd65f1b8 169 enum ib_port_state port_state;
5ec8c83e 170
7fd8aefb
DJ		 171 if (get_port_state(&ibdev->ib_dev, port_num,
172 &port_state))
173 goto done;
fd65f1b8 174
7fd8aefb
DJ		 175 if (roce->last_port_state == port_state)
176 goto done;
fd65f1b8 177
7fd8aefb 178 roce->last_port_state = port_state;
5ec8c83e 179 ibev.device = &ibdev->ib_dev;
fd65f1b8
MS		 180 if (port_state == IB_PORT_DOWN)
181 ibev.event = IB_EVENT_PORT_ERR;
182 else if (port_state == IB_PORT_ACTIVE)
183 ibev.event = IB_EVENT_PORT_ACTIVE;
184 else
7fd8aefb 185 goto done;
fd65f1b8 186
7fd8aefb 187 ibev.element.port_num = port_num;
5ec8c83e
AH		 188 ib_dispatch_event(&ibev);
189 }
190 break;
88621dfe 191 }
fc24fc5e 192
5ec8c83e
AH		 193 default:
194 break;
195 }
7fd8aefb 196done:
32f69e4b 197 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 198 return NOTIFY_DONE;
199}
200
201static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
202 u8 port_num)
203{
204 struct mlx5_ib_dev *ibdev = to_mdev(device);
205 struct net_device *ndev;
32f69e4b
DJ		 206 struct mlx5_core_dev *mdev;
207
208 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
209 if (!mdev)
210 return NULL;
fc24fc5e 211
32f69e4b 212 ndev = mlx5_lag_get_roce_netdev(mdev);
88621dfe 213 if (ndev)
32f69e4b 214 goto out;
88621dfe 215
fc24fc5e
AS		 216 /* Ensure ndev does not disappear before we invoke dev_hold()
217 */
7fd8aefb
DJ		 218 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
219 ndev = ibdev->roce[port_num - 1].netdev;
fc24fc5e
AS		 220 if (ndev)
221 dev_hold(ndev);
7fd8aefb 222 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
fc24fc5e 223
32f69e4b
DJ		 224out:
225 mlx5_ib_put_native_port_mdev(ibdev, port_num);
fc24fc5e
AS		 226 return ndev;
227}
228
32f69e4b
DJ		 229struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
230 u8 ib_port_num,
231 u8 *native_port_num)
232{
233 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
234 ib_port_num);
235 struct mlx5_core_dev *mdev = NULL;
236 struct mlx5_ib_multiport_info *mpi;
237 struct mlx5_ib_port *port;
238
239 if (native_port_num)
240 *native_port_num = 1;
241
242 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
243 return ibdev->mdev;
244
245 port = &ibdev->port[ib_port_num - 1];
246 if (!port)
247 return NULL;
248
249 spin_lock(&port->mp.mpi_lock);
250 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
251 if (mpi && !mpi->unaffiliate) {
252 mdev = mpi->mdev;
253 /* If it's the master no need to refcount, it'll exist
254 * as long as the ib_dev exists.
255 */
256 if (!mpi->is_master)
257 mpi->mdev_refcnt++;
258 }
259 spin_unlock(&port->mp.mpi_lock);
260
261 return mdev;
262}
263
264void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
265{
266 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
267 port_num);
268 struct mlx5_ib_multiport_info *mpi;
269 struct mlx5_ib_port *port;
270
271 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
272 return;
273
274 port = &ibdev->port[port_num - 1];
275
276 spin_lock(&port->mp.mpi_lock);
277 mpi = ibdev->port[port_num - 1].mp.mpi;
278 if (mpi->is_master)
279 goto out;
280
281 mpi->mdev_refcnt--;
282 if (mpi->unaffiliate)
283 complete(&mpi->unref_comp);
284out:
285 spin_unlock(&port->mp.mpi_lock);
286}
287
f1b65df5
NO		 288static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
289 u8 *active_width)
290{
291 switch (eth_proto_oper) {
292 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
293 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
294 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
295 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
296 *active_width = IB_WIDTH_1X;
297 *active_speed = IB_SPEED_SDR;
298 break;
299 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
300 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
301 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
302 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
303 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
304 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
305 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
306 *active_width = IB_WIDTH_1X;
307 *active_speed = IB_SPEED_QDR;
308 break;
309 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
310 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
311 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
312 *active_width = IB_WIDTH_1X;
313 *active_speed = IB_SPEED_EDR;
314 break;
315 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
316 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
317 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
318 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
319 *active_width = IB_WIDTH_4X;
320 *active_speed = IB_SPEED_QDR;
321 break;
322 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
323 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
324 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
325 *active_width = IB_WIDTH_1X;
326 *active_speed = IB_SPEED_HDR;
327 break;
328 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
329 *active_width = IB_WIDTH_4X;
330 *active_speed = IB_SPEED_FDR;
331 break;
332 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
333 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
334 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
335 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
336 *active_width = IB_WIDTH_4X;
337 *active_speed = IB_SPEED_EDR;
338 break;
339 default:
340 return -EINVAL;
341 }
342
343 return 0;
344}
345
095b0927
IT		 346static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
347 struct ib_port_attr *props)
3f89a643
AS		 348{
349 struct mlx5_ib_dev *dev = to_mdev(device);
f1b65df5 350 struct mlx5_core_dev *mdev = dev->mdev;
88621dfe 351 struct net_device *ndev, *upper;
3f89a643 352 enum ib_mtu ndev_ib_mtu;
c876a1b7 353 u16 qkey_viol_cntr;
f1b65df5 354 u32 eth_prot_oper;
095b0927 355 int err;
3f89a643 356
f1b65df5
NO		 357 /* Possible bad flows are checked before filling out props so in case
358 * of an error it will still be zeroed out.
50f22fd8 359 */
095b0927
IT		 360 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
361 if (err)
362 return err;
f1b65df5
NO		 363
364 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
365 &props->active_width);
3f89a643
AS		 366
367 props->port_cap_flags |= IB_PORT_CM_SUP;
368 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
369
370 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
371 roce_address_table_size);
372 props->max_mtu = IB_MTU_4096;
373 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
374 props->pkey_tbl_len = 1;
375 props->state = IB_PORT_DOWN;
376 props->phys_state = 3;
377
c876a1b7
LR		 378 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
379 props->qkey_viol_cntr = qkey_viol_cntr;
3f89a643
AS		 380
381 ndev = mlx5_ib_get_netdev(device, port_num);
382 if (!ndev)
095b0927 383 return 0;
3f89a643 384
88621dfe
AH		 385 if (mlx5_lag_is_active(dev->mdev)) {
386 rcu_read_lock();
387 upper = netdev_master_upper_dev_get_rcu(ndev);
388 if (upper) {
389 dev_put(ndev);
390 ndev = upper;
391 dev_hold(ndev);
392 }
393 rcu_read_unlock();
394 }
395
3f89a643
AS		 396 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
397 props->state = IB_PORT_ACTIVE;
398 props->phys_state = 5;
399 }
400
401 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
402
403 dev_put(ndev);
404
405 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
095b0927 406 return 0;
3f89a643
AS		 407}
408
095b0927
IT		 409static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
410 unsigned int index, const union ib_gid *gid,
411 const struct ib_gid_attr *attr)
3cca2606 412{
095b0927
IT		 413 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
414 u8 roce_version = 0;
415 u8 roce_l3_type = 0;
416 bool vlan = false;
417 u8 mac[ETH_ALEN];
418 u16 vlan_id = 0;
419
420 if (gid) {
421 gid_type = attr->gid_type;
422 ether_addr_copy(mac, attr->ndev->dev_addr);
423
424 if (is_vlan_dev(attr->ndev)) {
425 vlan = true;
426 vlan_id = vlan_dev_vlan_id(attr->ndev);
427 }
3cca2606
AS		 428 }
429
095b0927 430 switch (gid_type) {
3cca2606 431 case IB_GID_TYPE_IB:
095b0927 432 roce_version = MLX5_ROCE_VERSION_1;
3cca2606
AS		 433 break;
434 case IB_GID_TYPE_ROCE_UDP_ENCAP:
095b0927
IT		 435 roce_version = MLX5_ROCE_VERSION_2;
436 if (ipv6_addr_v4mapped((void *)gid))
437 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
438 else
439 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
3cca2606
AS		 440 break;
441
442 default:
095b0927 443 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
3cca2606
AS		 444 }
445
095b0927
IT		 446 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
447 roce_l3_type, gid->raw, mac, vlan,
448 vlan_id);
3cca2606
AS		 449}
450
451static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
452 unsigned int index, const union ib_gid *gid,
453 const struct ib_gid_attr *attr,
454 __always_unused void **context)
455{
095b0927 456 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
3cca2606
AS		 457}
458
459static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
460 unsigned int index, __always_unused void **context)
461{
095b0927 462 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
3cca2606
AS		 463}
464
2811ba51
AS		 465__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
466 int index)
467{
468 struct ib_gid_attr attr;
469 union ib_gid gid;
470
471 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
472 return 0;
473
474 if (!attr.ndev)
475 return 0;
476
477 dev_put(attr.ndev);
478
479 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
480 return 0;
481
482 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
483}
484
ed88451e
MD		 485int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
486 int index, enum ib_gid_type *gid_type)
487{
488 struct ib_gid_attr attr;
489 union ib_gid gid;
490 int ret;
491
492 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
493 if (ret)
494 return ret;
495
496 if (!attr.ndev)
497 return -ENODEV;
498
499 dev_put(attr.ndev);
500
501 *gid_type = attr.gid_type;
502
503 return 0;
504}
505
1b5daf11
MD		 506static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
507{
7fae6655
NO		 508 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
509 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
510 return 0;
1b5daf11
MD		 511}
512
513enum {
514 MLX5_VPORT_ACCESS_METHOD_MAD,
515 MLX5_VPORT_ACCESS_METHOD_HCA,
516 MLX5_VPORT_ACCESS_METHOD_NIC,
517};
518
519static int mlx5_get_vport_access_method(struct ib_device *ibdev)
520{
521 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
522 return MLX5_VPORT_ACCESS_METHOD_MAD;
523
ebd61f68 524 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1b5daf11
MD		 525 IB_LINK_LAYER_ETHERNET)
526 return MLX5_VPORT_ACCESS_METHOD_NIC;
527
528 return MLX5_VPORT_ACCESS_METHOD_HCA;
529}
530
da7525d2 531static void get_atomic_caps(struct mlx5_ib_dev *dev,
776a3906 532 u8 atomic_size_qp,
da7525d2
EBE		 533 struct ib_device_attr *props)
534{
535 u8 tmp;
536 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
da7525d2 537 u8 atomic_req_8B_endianness_mode =
bd10838a 538 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
da7525d2
EBE		 539
540 /* Check if HW supports 8 bytes standard atomic operations and capable
541 * of host endianness respond
542 */
543 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
544 if (((atomic_operations & tmp) == tmp) &&
545 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
546 (atomic_req_8B_endianness_mode)) {
547 props->atomic_cap = IB_ATOMIC_HCA;
548 } else {
549 props->atomic_cap = IB_ATOMIC_NONE;
550 }
551}
552
776a3906
MS		 553static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
554 struct ib_device_attr *props)
555{
556 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
557
558 get_atomic_caps(dev, atomic_size_qp, props);
559}
560
561static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
562 struct ib_device_attr *props)
563{
564 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
565
566 get_atomic_caps(dev, atomic_size_qp, props);
567}
568
569bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
570{
571 struct ib_device_attr props = {};
572
573 get_atomic_caps_dc(dev, &props);
574 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
575}
1b5daf11
MD		 576static int mlx5_query_system_image_guid(struct ib_device *ibdev,
577 __be64 *sys_image_guid)
578{
579 struct mlx5_ib_dev *dev = to_mdev(ibdev);
580 struct mlx5_core_dev *mdev = dev->mdev;
581 u64 tmp;
582 int err;
583
584 switch (mlx5_get_vport_access_method(ibdev)) {
585 case MLX5_VPORT_ACCESS_METHOD_MAD:
586 return mlx5_query_mad_ifc_system_image_guid(ibdev,
587 sys_image_guid);
588
589 case MLX5_VPORT_ACCESS_METHOD_HCA:
590 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
3f89a643
AS		 591 break;
592
593 case MLX5_VPORT_ACCESS_METHOD_NIC:
594 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
595 break;
1b5daf11
MD		 596
597 default:
598 return -EINVAL;
599 }
3f89a643
AS		 600
601 if (!err)
602 *sys_image_guid = cpu_to_be64(tmp);
603
604 return err;
605
1b5daf11
MD		 606}
607
608static int mlx5_query_max_pkeys(struct ib_device *ibdev,
609 u16 *max_pkeys)
610{
611 struct mlx5_ib_dev *dev = to_mdev(ibdev);
612 struct mlx5_core_dev *mdev = dev->mdev;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
617
618 case MLX5_VPORT_ACCESS_METHOD_HCA:
619 case MLX5_VPORT_ACCESS_METHOD_NIC:
620 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
621 pkey_table_size));
622 return 0;
623
624 default:
625 return -EINVAL;
626 }
627}
628
629static int mlx5_query_vendor_id(struct ib_device *ibdev,
630 u32 *vendor_id)
631{
632 struct mlx5_ib_dev *dev = to_mdev(ibdev);
633
634 switch (mlx5_get_vport_access_method(ibdev)) {
635 case MLX5_VPORT_ACCESS_METHOD_MAD:
636 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
637
638 case MLX5_VPORT_ACCESS_METHOD_HCA:
639 case MLX5_VPORT_ACCESS_METHOD_NIC:
640 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
641
642 default:
643 return -EINVAL;
644 }
645}
646
647static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
648 __be64 *node_guid)
649{
650 u64 tmp;
651 int err;
652
653 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
654 case MLX5_VPORT_ACCESS_METHOD_MAD:
655 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
656
657 case MLX5_VPORT_ACCESS_METHOD_HCA:
658 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
3f89a643
AS		 659 break;
660
661 case MLX5_VPORT_ACCESS_METHOD_NIC:
662 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
663 break;
1b5daf11
MD		 664
665 default:
666 return -EINVAL;
667 }
3f89a643
AS		 668
669 if (!err)
670 *node_guid = cpu_to_be64(tmp);
671
672 return err;
1b5daf11
MD		 673}
674
675struct mlx5_reg_node_desc {
bd99fdea 676 u8 desc[IB_DEVICE_NODE_DESC_MAX];
1b5daf11
MD		 677};
678
679static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
680{
681 struct mlx5_reg_node_desc in;
682
683 if (mlx5_use_mad_ifc(dev))
684 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
685
686 memset(&in, 0, sizeof(in));
687
688 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
689 sizeof(struct mlx5_reg_node_desc),
690 MLX5_REG_NODE_DESC, 0, 0);
691}
692
e126ba97 693static int mlx5_ib_query_device(struct ib_device *ibdev,
2528e33e
MB		 694 struct ib_device_attr *props,
695 struct ib_udata *uhw)
e126ba97
EC		 696{
697 struct mlx5_ib_dev *dev = to_mdev(ibdev);
938fe83c 698 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 699 int err = -ENOMEM;
288c01b7 700 int max_sq_desc;
e126ba97
EC		 701 int max_rq_sg;
702 int max_sq_sg;
e0238a6a 703 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
402ca536
BW		 704 struct mlx5_ib_query_device_resp resp = {};
705 size_t resp_len;
706 u64 max_tso;
e126ba97 707
402ca536
BW		 708 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
709 if (uhw->outlen && uhw->outlen < resp_len)
710 return -EINVAL;
711 else
712 resp.response_length = resp_len;
713
714 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
2528e33e
MB		 715 return -EINVAL;
716
1b5daf11
MD		 717 memset(props, 0, sizeof(*props));
718 err = mlx5_query_system_image_guid(ibdev,
719 &props->sys_image_guid);
720 if (err)
721 return err;
e126ba97 722
1b5daf11 723 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
e126ba97 724 if (err)
1b5daf11 725 return err;
e126ba97 726
1b5daf11
MD		 727 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
728 if (err)
729 return err;
e126ba97 730
9603b61d
JM		 731 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
732 (fw_rev_min(dev->mdev) << 16) |
733 fw_rev_sub(dev->mdev);
e126ba97
EC		 734 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
735 IB_DEVICE_PORT_ACTIVE_EVENT |
736 IB_DEVICE_SYS_IMAGE_GUID |
1a4c3a3d 737 IB_DEVICE_RC_RNR_NAK_GEN;
938fe83c
SM		 738
739 if (MLX5_CAP_GEN(mdev, pkv))
e126ba97 740 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
938fe83c 741 if (MLX5_CAP_GEN(mdev, qkv))
e126ba97 742 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
938fe83c 743 if (MLX5_CAP_GEN(mdev, apm))
e126ba97 744 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
938fe83c 745 if (MLX5_CAP_GEN(mdev, xrc))
e126ba97 746 props->device_cap_flags |= IB_DEVICE_XRC;
d2370e0a
MB		 747 if (MLX5_CAP_GEN(mdev, imaicl)) {
748 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
749 IB_DEVICE_MEM_WINDOW_TYPE_2B;
750 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
b005d316
SG		 751 /* We support 'Gappy' memory registration too */
752 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
d2370e0a 753 }
e126ba97 754 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
938fe83c 755 if (MLX5_CAP_GEN(mdev, sho)) {
2dea9094
SG		 756 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
757 /* At this stage no support for signature handover */
758 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
759 IB_PROT_T10DIF_TYPE_2 |
760 IB_PROT_T10DIF_TYPE_3;
761 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
762 IB_GUARD_T10DIF_CSUM;
763 }
938fe83c 764 if (MLX5_CAP_GEN(mdev, block_lb_mc))
f360d88a 765 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
e126ba97 766
402ca536 767 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
e8161334
NO		 768 if (MLX5_CAP_ETH(mdev, csum_cap)) {
769 /* Legacy bit to support old userspace libraries */
88115fe7 770 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
e8161334
NO		 771 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
772 }
773
774 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
775 props->raw_packet_caps |=
776 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
88115fe7 777
402ca536
BW		 778 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
779 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
780 if (max_tso) {
781 resp.tso_caps.max_tso = 1 << max_tso;
782 resp.tso_caps.supported_qpts |=
783 1 << IB_QPT_RAW_PACKET;
784 resp.response_length += sizeof(resp.tso_caps);
785 }
786 }
31f69a82
YH		 787
788 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
789 resp.rss_caps.rx_hash_function =
790 MLX5_RX_HASH_FUNC_TOEPLITZ;
791 resp.rss_caps.rx_hash_fields_mask =
792 MLX5_RX_HASH_SRC_IPV4 |
793 MLX5_RX_HASH_DST_IPV4 |
794 MLX5_RX_HASH_SRC_IPV6 |
795 MLX5_RX_HASH_DST_IPV6 |
796 MLX5_RX_HASH_SRC_PORT_TCP |
797 MLX5_RX_HASH_DST_PORT_TCP |
798 MLX5_RX_HASH_SRC_PORT_UDP |
4e2b53a5
MG		 799 MLX5_RX_HASH_DST_PORT_UDP |
800 MLX5_RX_HASH_INNER;
31f69a82
YH		 801 resp.response_length += sizeof(resp.rss_caps);
802 }
803 } else {
804 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
805 resp.response_length += sizeof(resp.tso_caps);
806 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
807 resp.response_length += sizeof(resp.rss_caps);
402ca536
BW		 808 }
809
f0313965
ES		 810 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
811 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
812 props->device_cap_flags |= IB_DEVICE_UD_TSO;
813 }
814
03404e8a
MG		 815 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
816 MLX5_CAP_GEN(dev->mdev, general_notification_event))
817 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
818
1d54f890
YH		 819 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
820 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
821 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
822
cff5a0f3 823 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
e8161334
NO		 824 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
825 /* Legacy bit to support old userspace libraries */
cff5a0f3 826 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
e8161334
NO		 827 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
828 }
cff5a0f3 829
da6d6ba3
MG		 830 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
831 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
832
b1383aa6
NO		 833 if (MLX5_CAP_GEN(mdev, end_pad))
834 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
835
1b5daf11
MD		 836 props->vendor_part_id = mdev->pdev->device;
837 props->hw_ver = mdev->pdev->revision;
e126ba97
EC		 838
839 props->max_mr_size = ~0ull;
e0238a6a 840 props->page_size_cap = ~(min_page_size - 1);
938fe83c
SM		 841 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
842 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
843 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
844 sizeof(struct mlx5_wqe_data_seg);
288c01b7
EC		 845 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
846 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
847 sizeof(struct mlx5_wqe_raddr_seg)) /
848 sizeof(struct mlx5_wqe_data_seg);
e126ba97 849 props->max_sge = min(max_rq_sg, max_sq_sg);
986ef95e 850 props->max_sge_rd = MLX5_MAX_SGE_RD;
938fe83c 851 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
9f177686 852 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
938fe83c
SM		 853 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
854 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
855 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
856 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
857 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
858 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
859 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
e126ba97 860 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
e126ba97 861 props->max_srq_sge = max_rq_sg - 1;
911f4331
SG		 862 props->max_fast_reg_page_list_len =
863 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
776a3906 864 get_atomic_caps_qp(dev, props);
81bea28f 865 props->masked_atomic_cap = IB_ATOMIC_NONE;
938fe83c
SM		 866 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
867 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
e126ba97
EC		 868 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
869 props->max_mcast_grp;
870 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
86695a65 871 props->max_ah = INT_MAX;
7c60bcbb
MB		 872 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
873 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
e126ba97 874
8cdd312c 875#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
938fe83c 876 if (MLX5_CAP_GEN(mdev, pg))
8cdd312c
HE		 877 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
878 props->odp_caps = dev->odp_caps;
879#endif
880
051f2630
LR		 881 if (MLX5_CAP_GEN(mdev, cd))
882 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
883
eff901d3
EC		 884 if (!mlx5_core_is_pf(mdev))
885 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
886
31f69a82
YH		 887 if (mlx5_ib_port_link_layer(ibdev, 1) ==
888 IB_LINK_LAYER_ETHERNET) {
889 props->rss_caps.max_rwq_indirection_tables =
890 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
891 props->rss_caps.max_rwq_indirection_table_size =
892 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
893 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
894 props->max_wq_type_rq =
895 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
896 }
897
eb761894 898 if (MLX5_CAP_GEN(mdev, tag_matching)) {
78b1beb0
LR		 899 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
900 props->tm_caps.max_num_tags =
eb761894 901 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
78b1beb0
LR		 902 props->tm_caps.flags = IB_TM_CAP_RC;
903 props->tm_caps.max_ops =
eb761894 904 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
78b1beb0 905 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
eb761894
AK		 906 }
907
87ab3f52
YC		 908 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
909 props->cq_caps.max_cq_moderation_count =
910 MLX5_MAX_CQ_COUNT;
911 props->cq_caps.max_cq_moderation_period =
912 MLX5_MAX_CQ_PERIOD;
913 }
914
7e43a2a5
BW		 915 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
916 resp.cqe_comp_caps.max_num =
917 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
918 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
919 resp.cqe_comp_caps.supported_format =
920 MLX5_IB_CQE_RES_FORMAT_HASH |
921 MLX5_IB_CQE_RES_FORMAT_CSUM;
922 resp.response_length += sizeof(resp.cqe_comp_caps);
923 }
924
d949167d
BW		 925 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
926 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
927 MLX5_CAP_GEN(mdev, qos)) {
928 resp.packet_pacing_caps.qp_rate_limit_max =
929 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
930 resp.packet_pacing_caps.qp_rate_limit_min =
931 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
932 resp.packet_pacing_caps.supported_qpts |=
933 1 << IB_QPT_RAW_PACKET;
934 }
935 resp.response_length += sizeof(resp.packet_pacing_caps);
936 }
937
9f885201
LR		 938 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
939 uhw->outlen)) {
795b609c
BW		 940 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
941 resp.mlx5_ib_support_multi_pkt_send_wqes =
942 MLX5_IB_ALLOW_MPW;
050da902
BW		 943
944 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
945 resp.mlx5_ib_support_multi_pkt_send_wqes |=
946 MLX5_IB_SUPPORT_EMPW;
947
9f885201
LR		 948 resp.response_length +=
949 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
950 }
951
de57f2ad
GL		 952 if (field_avail(typeof(resp), flags, uhw->outlen)) {
953 resp.response_length += sizeof(resp.flags);
7a0c8f42 954
de57f2ad
GL		 955 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
956 resp.flags |=
957 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
7a0c8f42
GL		 958
959 if (MLX5_CAP_GEN(mdev, cqe_128_always))
960 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
de57f2ad 961 }
9f885201 962
96dc3fc5
NO		 963 if (field_avail(typeof(resp), sw_parsing_caps,
964 uhw->outlen)) {
965 resp.response_length += sizeof(resp.sw_parsing_caps);
966 if (MLX5_CAP_ETH(mdev, swp)) {
967 resp.sw_parsing_caps.sw_parsing_offloads |=
968 MLX5_IB_SW_PARSING;
969
970 if (MLX5_CAP_ETH(mdev, swp_csum))
971 resp.sw_parsing_caps.sw_parsing_offloads |=
972 MLX5_IB_SW_PARSING_CSUM;
973
974 if (MLX5_CAP_ETH(mdev, swp_lso))
975 resp.sw_parsing_caps.sw_parsing_offloads |=
976 MLX5_IB_SW_PARSING_LSO;
977
978 if (resp.sw_parsing_caps.sw_parsing_offloads)
979 resp.sw_parsing_caps.supported_qpts =
980 BIT(IB_QPT_RAW_PACKET);
981 }
982 }
983
b4f34597
NO		 984 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen)) {
985 resp.response_length += sizeof(resp.striding_rq_caps);
986 if (MLX5_CAP_GEN(mdev, striding_rq)) {
987 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
988 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
989 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
990 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
991 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
992 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
993 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
994 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
995 resp.striding_rq_caps.supported_qpts =
996 BIT(IB_QPT_RAW_PACKET);
997 }
998 }
999
f95ef6cb
MG		 1000 if (field_avail(typeof(resp), tunnel_offloads_caps,
1001 uhw->outlen)) {
1002 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1003 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1004 resp.tunnel_offloads_caps |=
1005 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1006 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1007 resp.tunnel_offloads_caps |=
1008 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1009 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1010 resp.tunnel_offloads_caps |=
1011 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1012 }
1013
402ca536
BW		 1014 if (uhw->outlen) {
1015 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1016
1017 if (err)
1018 return err;
1019 }
1020
1b5daf11 1021 return 0;
e126ba97
EC		 1022}
1023
1b5daf11
MD		 1024enum mlx5_ib_width {
1025 MLX5_IB_WIDTH_1X = 1 << 0,
1026 MLX5_IB_WIDTH_2X = 1 << 1,
1027 MLX5_IB_WIDTH_4X = 1 << 2,
1028 MLX5_IB_WIDTH_8X = 1 << 3,
1029 MLX5_IB_WIDTH_12X = 1 << 4
1030};
1031
1032static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1033 u8 *ib_width)
e126ba97
EC		 1034{
1035 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1b5daf11
MD		 1036 int err = 0;
1037
1038 if (active_width & MLX5_IB_WIDTH_1X) {
1039 *ib_width = IB_WIDTH_1X;
1040 } else if (active_width & MLX5_IB_WIDTH_2X) {
1041 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1042 (int)active_width);
1043 err = -EINVAL;
1044 } else if (active_width & MLX5_IB_WIDTH_4X) {
1045 *ib_width = IB_WIDTH_4X;
1046 } else if (active_width & MLX5_IB_WIDTH_8X) {
1047 *ib_width = IB_WIDTH_8X;
1048 } else if (active_width & MLX5_IB_WIDTH_12X) {
1049 *ib_width = IB_WIDTH_12X;
1050 } else {
1051 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1052 (int)active_width);
1053 err = -EINVAL;
e126ba97
EC		 1054 }
1055
1b5daf11
MD		 1056 return err;
1057}
e126ba97 1058
1b5daf11
MD		 1059static int mlx5_mtu_to_ib_mtu(int mtu)
1060{
1061 switch (mtu) {
1062 case 256: return 1;
1063 case 512: return 2;
1064 case 1024: return 3;
1065 case 2048: return 4;
1066 case 4096: return 5;
1067 default:
1068 pr_warn("invalid mtu\n");
1069 return -1;
e126ba97 1070 }
1b5daf11 1071}
e126ba97 1072
1b5daf11
MD		 1073enum ib_max_vl_num {
1074 __IB_MAX_VL_0 = 1,
1075 __IB_MAX_VL_0_1 = 2,
1076 __IB_MAX_VL_0_3 = 3,
1077 __IB_MAX_VL_0_7 = 4,
1078 __IB_MAX_VL_0_14 = 5,
1079};
e126ba97 1080
1b5daf11
MD		 1081enum mlx5_vl_hw_cap {
1082 MLX5_VL_HW_0 = 1,
1083 MLX5_VL_HW_0_1 = 2,
1084 MLX5_VL_HW_0_2 = 3,
1085 MLX5_VL_HW_0_3 = 4,
1086 MLX5_VL_HW_0_4 = 5,
1087 MLX5_VL_HW_0_5 = 6,
1088 MLX5_VL_HW_0_6 = 7,
1089 MLX5_VL_HW_0_7 = 8,
1090 MLX5_VL_HW_0_14 = 15
1091};
e126ba97 1092
1b5daf11
MD		 1093static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1094 u8 *max_vl_num)
1095{
1096 switch (vl_hw_cap) {
1097 case MLX5_VL_HW_0:
1098 *max_vl_num = __IB_MAX_VL_0;
1099 break;
1100 case MLX5_VL_HW_0_1:
1101 *max_vl_num = __IB_MAX_VL_0_1;
1102 break;
1103 case MLX5_VL_HW_0_3:
1104 *max_vl_num = __IB_MAX_VL_0_3;
1105 break;
1106 case MLX5_VL_HW_0_7:
1107 *max_vl_num = __IB_MAX_VL_0_7;
1108 break;
1109 case MLX5_VL_HW_0_14:
1110 *max_vl_num = __IB_MAX_VL_0_14;
1111 break;
e126ba97 1112
1b5daf11
MD		 1113 default:
1114 return -EINVAL;
e126ba97 1115 }
e126ba97 1116
1b5daf11 1117 return 0;
e126ba97
EC		 1118}
1119
1b5daf11
MD		 1120static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1121 struct ib_port_attr *props)
e126ba97 1122{
1b5daf11
MD		 1123 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1124 struct mlx5_core_dev *mdev = dev->mdev;
1125 struct mlx5_hca_vport_context *rep;
046339ea
SM		 1126 u16 max_mtu;
1127 u16 oper_mtu;
1b5daf11
MD		 1128 int err;
1129 u8 ib_link_width_oper;
1130 u8 vl_hw_cap;
e126ba97 1131
1b5daf11
MD		 1132 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1133 if (!rep) {
1134 err = -ENOMEM;
e126ba97 1135 goto out;
e126ba97 1136 }
e126ba97 1137
c4550c63 1138 /* props being zeroed by the caller, avoid zeroing it here */
e126ba97 1139
1b5daf11 1140 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
e126ba97
EC		 1141 if (err)
1142 goto out;
1143
1b5daf11
MD		 1144 props->lid = rep->lid;
1145 props->lmc = rep->lmc;
1146 props->sm_lid = rep->sm_lid;
1147 props->sm_sl = rep->sm_sl;
1148 props->state = rep->vport_state;
1149 props->phys_state = rep->port_physical_state;
1150 props->port_cap_flags = rep->cap_mask1;
1151 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1152 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1153 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1154 props->bad_pkey_cntr = rep->pkey_violation_counter;
1155 props->qkey_viol_cntr = rep->qkey_violation_counter;
1156 props->subnet_timeout = rep->subnet_timeout;
1157 props->init_type_reply = rep->init_type_reply;
eff901d3 1158 props->grh_required = rep->grh_required;
e126ba97 1159
1b5daf11
MD		 1160 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1161 if (err)
e126ba97 1162 goto out;
e126ba97 1163
1b5daf11
MD		 1164 err = translate_active_width(ibdev, ib_link_width_oper,
1165 &props->active_width);
1166 if (err)
1167 goto out;
d5beb7f2 1168 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
e126ba97
EC		 1169 if (err)
1170 goto out;
1171
facc9699 1172 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
e126ba97 1173
1b5daf11 1174 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
e126ba97 1175
facc9699 1176 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
e126ba97 1177
1b5daf11 1178 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
e126ba97 1179
1b5daf11
MD		 1180 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1181 if (err)
1182 goto out;
e126ba97 1183
1b5daf11
MD		 1184 err = translate_max_vl_num(ibdev, vl_hw_cap,
1185 &props->max_vl_num);
e126ba97 1186out:
1b5daf11 1187 kfree(rep);
e126ba97
EC		 1188 return err;
1189}
1190
1b5daf11
MD		 1191int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1192 struct ib_port_attr *props)
e126ba97 1193{
095b0927
IT		 1194 unsigned int count;
1195 int ret;
1196
1b5daf11
MD		 1197 switch (mlx5_get_vport_access_method(ibdev)) {
1198 case MLX5_VPORT_ACCESS_METHOD_MAD:
095b0927
IT		 1199 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1200 break;
e126ba97 1201
1b5daf11 1202 case MLX5_VPORT_ACCESS_METHOD_HCA:
095b0927
IT		 1203 ret = mlx5_query_hca_port(ibdev, port, props);
1204 break;
e126ba97 1205
3f89a643 1206 case MLX5_VPORT_ACCESS_METHOD_NIC:
095b0927
IT		 1207 ret = mlx5_query_port_roce(ibdev, port, props);
1208 break;
3f89a643 1209
1b5daf11 1210 default:
095b0927
IT		 1211 ret = -EINVAL;
1212 }
1213
1214 if (!ret && props) {
1215 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
1216 props->gid_tbl_len -= count;
1b5daf11 1217 }
095b0927 1218 return ret;
1b5daf11 1219}
e126ba97 1220
1b5daf11
MD		 1221static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1222 union ib_gid *gid)
1223{
1224 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1225 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 1226
1b5daf11
MD		 1227 switch (mlx5_get_vport_access_method(ibdev)) {
1228 case MLX5_VPORT_ACCESS_METHOD_MAD:
1229 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
e126ba97 1230
1b5daf11
MD		 1231 case MLX5_VPORT_ACCESS_METHOD_HCA:
1232 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1233
1234 default:
1235 return -EINVAL;
1236 }
e126ba97 1237
e126ba97
EC		 1238}
1239
1b5daf11
MD		 1240static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1241 u16 *pkey)
1242{
1243 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1244 struct mlx5_core_dev *mdev = dev->mdev;
1245
1246 switch (mlx5_get_vport_access_method(ibdev)) {
1247 case MLX5_VPORT_ACCESS_METHOD_MAD:
1248 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1249
1250 case MLX5_VPORT_ACCESS_METHOD_HCA:
1251 case MLX5_VPORT_ACCESS_METHOD_NIC:
1252 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1253 pkey);
1254 default:
1255 return -EINVAL;
1256 }
1257}
e126ba97
EC		 1258
1259static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1260 struct ib_device_modify *props)
1261{
1262 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1263 struct mlx5_reg_node_desc in;
1264 struct mlx5_reg_node_desc out;
1265 int err;
1266
1267 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1268 return -EOPNOTSUPP;
1269
1270 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1271 return 0;
1272
1273 /*
1274 * If possible, pass node desc to FW, so it can generate
1275 * a 144 trap. If cmd fails, just ignore.
1276 */
bd99fdea 1277 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
9603b61d 1278 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
e126ba97
EC		 1279 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1280 if (err)
1281 return err;
1282
bd99fdea 1283 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
e126ba97
EC		 1284
1285 return err;
1286}
1287
cdbe33d0
EC		 1288static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1289 u32 value)
1290{
1291 struct mlx5_hca_vport_context ctx = {};
1292 int err;
1293
1294 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1295 port_num, 0, &ctx);
1296 if (err)
1297 return err;
1298
1299 if (~ctx.cap_mask1_perm & mask) {
1300 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1301 mask, ctx.cap_mask1_perm);
1302 return -EINVAL;
1303 }
1304
1305 ctx.cap_mask1 = value;
1306 ctx.cap_mask1_perm = mask;
1307 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1308 port_num, 0, &ctx);
1309
1310 return err;
1311}
1312
e126ba97
EC		 1313static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1314 struct ib_port_modify *props)
1315{
1316 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1317 struct ib_port_attr attr;
1318 u32 tmp;
1319 int err;
cdbe33d0
EC		 1320 u32 change_mask;
1321 u32 value;
1322 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1323 IB_LINK_LAYER_INFINIBAND);
1324
ec255879
MD		 1325 /* CM layer calls ib_modify_port() regardless of the link layer. For
1326 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1327 */
1328 if (!is_ib)
1329 return 0;
1330
cdbe33d0
EC		 1331 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1332 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1333 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1334 return set_port_caps_atomic(dev, port, change_mask, value);
1335 }
e126ba97
EC		 1336
1337 mutex_lock(&dev->cap_mask_mutex);
1338
c4550c63 1339 err = ib_query_port(ibdev, port, &attr);
e126ba97
EC		 1340 if (err)
1341 goto out;
1342
1343 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1344 ~props->clr_port_cap_mask;
1345
9603b61d 1346 err = mlx5_set_port_caps(dev->mdev, port, tmp);
e126ba97
EC		 1347
1348out:
1349 mutex_unlock(&dev->cap_mask_mutex);
1350 return err;
1351}
1352
30aa60b3
EC		 1353static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1354{
1355 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1356 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1357}
1358
31a78a5a
YH		 1359static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1360{
1361 /* Large page with non 4k uar support might limit the dynamic size */
1362 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1363 return MLX5_MIN_DYN_BFREGS;
1364
1365 return MLX5_MAX_DYN_BFREGS;
1366}
1367
b037c29a
EC		 1368static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1369 struct mlx5_ib_alloc_ucontext_req_v2 *req,
31a78a5a 1370 struct mlx5_bfreg_info *bfregi)
b037c29a
EC		 1371{
1372 int uars_per_sys_page;
1373 int bfregs_per_sys_page;
1374 int ref_bfregs = req->total_num_bfregs;
1375
1376 if (req->total_num_bfregs == 0)
1377 return -EINVAL;
1378
1379 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1380 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1381
1382 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1383 return -ENOMEM;
1384
1385 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1386 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
31a78a5a 1387 /* This holds the required static allocation asked by the user */
b037c29a 1388 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
b037c29a
EC		 1389 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1390 return -EINVAL;
1391
31a78a5a
YH		 1392 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1393 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1394 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1395 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1396
1397 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
b037c29a
EC		 1398 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1399 lib_uar_4k ? "yes" : "no", ref_bfregs,
31a78a5a
YH		 1400 req->total_num_bfregs, bfregi->total_num_bfregs,
1401 bfregi->num_sys_pages);
b037c29a
EC		 1402
1403 return 0;
1404}
1405
1406static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1407{
1408 struct mlx5_bfreg_info *bfregi;
1409 int err;
1410 int i;
1411
1412 bfregi = &context->bfregi;
31a78a5a 1413 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
b037c29a
EC		 1414 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1415 if (err)
1416 goto error;
1417
1418 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1419 }
4ed131d0
YH		 1420
1421 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1422 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1423
b037c29a
EC		 1424 return 0;
1425
1426error:
1427 for (--i; i >= 0; i--)
1428 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1429 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1430
1431 return err;
1432}
1433
1434static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1435{
1436 struct mlx5_bfreg_info *bfregi;
1437 int err;
1438 int i;
1439
1440 bfregi = &context->bfregi;
4ed131d0
YH		 1441 for (i = 0; i < bfregi->num_sys_pages; i++) {
1442 if (i < bfregi->num_static_sys_pages ||
1443 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1444 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1445 if (err) {
1446 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1447 return err;
1448 }
b037c29a
EC		 1449 }
1450 }
4ed131d0 1451
b037c29a
EC		 1452 return 0;
1453}
1454
c85023e1
HN		 1455static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1456{
1457 int err;
1458
1459 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1460 if (err)
1461 return err;
1462
1463 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1464 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1465 return err;
1466
1467 mutex_lock(&dev->lb_mutex);
1468 dev->user_td++;
1469
1470 if (dev->user_td == 2)
1471 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1472
1473 mutex_unlock(&dev->lb_mutex);
1474 return err;
1475}
1476
1477static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1478{
1479 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1480
1481 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1482 !MLX5_CAP_GEN(dev->mdev, disable_local_lb))
1483 return;
1484
1485 mutex_lock(&dev->lb_mutex);
1486 dev->user_td--;
1487
1488 if (dev->user_td < 2)
1489 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1490
1491 mutex_unlock(&dev->lb_mutex);
1492}
1493
e126ba97
EC		 1494static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1495 struct ib_udata *udata)
1496{
1497 struct mlx5_ib_dev *dev = to_mdev(ibdev);
b368d7cb
MB		 1498 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1499 struct mlx5_ib_alloc_ucontext_resp resp = {};
e126ba97 1500 struct mlx5_ib_ucontext *context;
2f5ff264 1501 struct mlx5_bfreg_info *bfregi;
78c0f98c 1502 int ver;
e126ba97 1503 int err;
a168a41c
MD		 1504 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1505 max_cqe_version);
b037c29a 1506 bool lib_uar_4k;
e126ba97
EC		 1507
1508 if (!dev->ib_active)
1509 return ERR_PTR(-EAGAIN);
1510
e093111d 1511 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
78c0f98c 1512 ver = 0;
e093111d 1513 else if (udata->inlen >= min_req_v2)
78c0f98c
EC		 1514 ver = 2;
1515 else
1516 return ERR_PTR(-EINVAL);
1517
e093111d 1518 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
e126ba97
EC		 1519 if (err)
1520 return ERR_PTR(err);
1521
b368d7cb 1522 if (req.flags)
78c0f98c
EC		 1523 return ERR_PTR(-EINVAL);
1524
f72300c5 1525 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
b368d7cb
MB		 1526 return ERR_PTR(-EOPNOTSUPP);
1527
2f5ff264
EC		 1528 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1529 MLX5_NON_FP_BFREGS_PER_UAR);
1530 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
e126ba97
EC		 1531 return ERR_PTR(-EINVAL);
1532
938fe83c 1533 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
2cc6ad5f
NO		 1534 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1535 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
b47bd6ea 1536 resp.cache_line_size = cache_line_size();
938fe83c
SM		 1537 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1538 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1539 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1540 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1541 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
f72300c5
HA		 1542 resp.cqe_version = min_t(__u8,
1543 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1544 req.max_cqe_version);
30aa60b3
EC		 1545 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1546 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1547 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1548 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
b368d7cb
MB		 1549 resp.response_length = min(offsetof(typeof(resp), response_length) +
1550 sizeof(resp.response_length), udata->outlen);
e126ba97
EC		 1551
1552 context = kzalloc(sizeof(*context), GFP_KERNEL);
1553 if (!context)
1554 return ERR_PTR(-ENOMEM);
1555
30aa60b3 1556 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
2f5ff264 1557 bfregi = &context->bfregi;
b037c29a
EC		 1558
1559 /* updates req->total_num_bfregs */
31a78a5a 1560 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
b037c29a 1561 if (err)
e126ba97 1562 goto out_ctx;
e126ba97 1563
b037c29a
EC		 1564 mutex_init(&bfregi->lock);
1565 bfregi->lib_uar_4k = lib_uar_4k;
31a78a5a 1566 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
e126ba97 1567 GFP_KERNEL);
b037c29a 1568 if (!bfregi->count) {
e126ba97 1569 err = -ENOMEM;
b037c29a 1570 goto out_ctx;
e126ba97
EC		 1571 }
1572
b037c29a
EC		 1573 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1574 sizeof(*bfregi->sys_pages),
1575 GFP_KERNEL);
1576 if (!bfregi->sys_pages) {
e126ba97 1577 err = -ENOMEM;
b037c29a 1578 goto out_count;
e126ba97
EC		 1579 }
1580
b037c29a
EC		 1581 err = allocate_uars(dev, context);
1582 if (err)
1583 goto out_sys_pages;
e126ba97 1584
b4cfe447
HE		 1585#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1586 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1587#endif
1588
7d0cc6ed
AK		 1589 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1590 if (!context->upd_xlt_page) {
1591 err = -ENOMEM;
1592 goto out_uars;
1593 }
1594 mutex_init(&context->upd_xlt_page_mutex);
1595
146d2f1a 1596 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
c85023e1 1597 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
146d2f1a 1598 if (err)
7d0cc6ed 1599 goto out_page;
146d2f1a 1600 }
1601
7c2344c3 1602 INIT_LIST_HEAD(&context->vma_private_list);
ad9a3668 1603 mutex_init(&context->vma_private_list_mutex);
e126ba97
EC		 1604 INIT_LIST_HEAD(&context->db_page_list);
1605 mutex_init(&context->db_page_mutex);
1606
2f5ff264 1607 resp.tot_bfregs = req.total_num_bfregs;
508562d6 1608 resp.num_ports = dev->num_ports;
b368d7cb 1609
f72300c5
HA		 1610 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1611 resp.response_length += sizeof(resp.cqe_version);
b368d7cb 1612
402ca536 1613 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
6ad279c5
MS		 1614 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1615 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
402ca536
BW		 1616 resp.response_length += sizeof(resp.cmds_supp_uhw);
1617 }
1618
78984898
OG		 1619 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1620 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1621 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1622 resp.eth_min_inline++;
1623 }
1624 resp.response_length += sizeof(resp.eth_min_inline);
1625 }
1626
bc5c6eed
NO		 1627 /*
1628 * We don't want to expose information from the PCI bar that is located
1629 * after 4096 bytes, so if the arch only supports larger pages, let's
1630 * pretend we don't support reading the HCA's core clock. This is also
1631 * forced by mmap function.
1632 */
de8d6e02
EC		 1633 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1634 if (PAGE_SIZE <= 4096) {
1635 resp.comp_mask |=
1636 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1637 resp.hca_core_clock_offset =
1638 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1639 }
f72300c5 1640 resp.response_length += sizeof(resp.hca_core_clock_offset) +
402ca536 1641 sizeof(resp.reserved2);
b368d7cb
MB		 1642 }
1643
30aa60b3
EC		 1644 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1645 resp.response_length += sizeof(resp.log_uar_size);
1646
1647 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1648 resp.response_length += sizeof(resp.num_uars_per_page);
1649
31a78a5a
YH		 1650 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1651 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1652 resp.response_length += sizeof(resp.num_dyn_bfregs);
1653 }
1654
b368d7cb 1655 err = ib_copy_to_udata(udata, &resp, resp.response_length);
e126ba97 1656 if (err)
146d2f1a 1657 goto out_td;
e126ba97 1658
2f5ff264
EC		 1659 bfregi->ver = ver;
1660 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
f72300c5 1661 context->cqe_version = resp.cqe_version;
30aa60b3
EC		 1662 context->lib_caps = req.lib_caps;
1663 print_lib_caps(dev, context->lib_caps);
f72300c5 1664
e126ba97
EC		 1665 return &context->ibucontext;
1666
146d2f1a 1667out_td:
1668 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1669 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1670
7d0cc6ed
AK		 1671out_page:
1672 free_page(context->upd_xlt_page);
1673
e126ba97 1674out_uars:
b037c29a 1675 deallocate_uars(dev, context);
e126ba97 1676
b037c29a
EC		 1677out_sys_pages:
1678 kfree(bfregi->sys_pages);
e126ba97 1679
b037c29a
EC		 1680out_count:
1681 kfree(bfregi->count);
e126ba97
EC		 1682
1683out_ctx:
1684 kfree(context);
b037c29a 1685
e126ba97
EC		 1686 return ERR_PTR(err);
1687}
1688
1689static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1690{
1691 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1692 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
b037c29a 1693 struct mlx5_bfreg_info *bfregi;
e126ba97 1694
b037c29a 1695 bfregi = &context->bfregi;
146d2f1a 1696 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
c85023e1 1697 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
146d2f1a 1698
7d0cc6ed 1699 free_page(context->upd_xlt_page);
b037c29a
EC		 1700 deallocate_uars(dev, context);
1701 kfree(bfregi->sys_pages);
2f5ff264 1702 kfree(bfregi->count);
e126ba97
EC		 1703 kfree(context);
1704
1705 return 0;
1706}
1707
b037c29a 1708static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
4ed131d0 1709 int uar_idx)
e126ba97 1710{
b037c29a
EC		 1711 int fw_uars_per_page;
1712
1713 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1714
4ed131d0 1715 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
e126ba97
EC		 1716}
1717
1718static int get_command(unsigned long offset)
1719{
1720 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1721}
1722
1723static int get_arg(unsigned long offset)
1724{
1725 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1726}
1727
1728static int get_index(unsigned long offset)
1729{
1730 return get_arg(offset);
1731}
1732
4ed131d0
YH		 1733/* Index resides in an extra byte to enable larger values than 255 */
1734static int get_extended_index(unsigned long offset)
1735{
1736 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1737}
1738
7c2344c3
MG		 1739static void mlx5_ib_vma_open(struct vm_area_struct *area)
1740{
1741 /* vma_open is called when a new VMA is created on top of our VMA. This
1742 * is done through either mremap flow or split_vma (usually due to
1743 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1744 * as this VMA is strongly hardware related. Therefore we set the
1745 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1746 * calling us again and trying to do incorrect actions. We assume that
1747 * the original VMA size is exactly a single page, and therefore all
1748 * "splitting" operation will not happen to it.
1749 */
1750 area->vm_ops = NULL;
1751}
1752
1753static void mlx5_ib_vma_close(struct vm_area_struct *area)
1754{
1755 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1756
1757 /* It's guaranteed that all VMAs opened on a FD are closed before the
1758 * file itself is closed, therefore no sync is needed with the regular
1759 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1760 * However need a sync with accessing the vma as part of
1761 * mlx5_ib_disassociate_ucontext.
1762 * The close operation is usually called under mm->mmap_sem except when
1763 * process is exiting.
1764 * The exiting case is handled explicitly as part of
1765 * mlx5_ib_disassociate_ucontext.
1766 */
1767 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1768
1769 /* setting the vma context pointer to null in the mlx5_ib driver's
1770 * private data, to protect a race condition in
1771 * mlx5_ib_disassociate_ucontext().
1772 */
1773 mlx5_ib_vma_priv_data->vma = NULL;
ad9a3668 1774 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3 1775 list_del(&mlx5_ib_vma_priv_data->list);
ad9a3668 1776 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
7c2344c3
MG		 1777 kfree(mlx5_ib_vma_priv_data);
1778}
1779
1780static const struct vm_operations_struct mlx5_ib_vm_ops = {
1781 .open = mlx5_ib_vma_open,
1782 .close = mlx5_ib_vma_close
1783};
1784
1785static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1786 struct mlx5_ib_ucontext *ctx)
1787{
1788 struct mlx5_ib_vma_private_data *vma_prv;
1789 struct list_head *vma_head = &ctx->vma_private_list;
1790
1791 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1792 if (!vma_prv)
1793 return -ENOMEM;
1794
1795 vma_prv->vma = vma;
ad9a3668 1796 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
7c2344c3
MG		 1797 vma->vm_private_data = vma_prv;
1798 vma->vm_ops = &mlx5_ib_vm_ops;
1799
ad9a3668 1800 mutex_lock(&ctx->vma_private_list_mutex);
7c2344c3 1801 list_add(&vma_prv->list, vma_head);
ad9a3668 1802 mutex_unlock(&ctx->vma_private_list_mutex);
7c2344c3
MG		 1803
1804 return 0;
1805}
1806
1807static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1808{
1809 int ret;
1810 struct vm_area_struct *vma;
1811 struct mlx5_ib_vma_private_data *vma_private, *n;
1812 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1813 struct task_struct *owning_process = NULL;
1814 struct mm_struct *owning_mm = NULL;
1815
1816 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1817 if (!owning_process)
1818 return;
1819
1820 owning_mm = get_task_mm(owning_process);
1821 if (!owning_mm) {
1822 pr_info("no mm, disassociate ucontext is pending task termination\n");
1823 while (1) {
1824 put_task_struct(owning_process);
1825 usleep_range(1000, 2000);
1826 owning_process = get_pid_task(ibcontext->tgid,
1827 PIDTYPE_PID);
1828 if (!owning_process ||
1829 owning_process->state == TASK_DEAD) {
1830 pr_info("disassociate ucontext done, task was terminated\n");
1831 /* in case task was dead need to release the
1832 * task struct.
1833 */
1834 if (owning_process)
1835 put_task_struct(owning_process);
1836 return;
1837 }
1838 }
1839 }
1840
1841 /* need to protect from a race on closing the vma as part of
1842 * mlx5_ib_vma_close.
1843 */
ecc7d83b 1844 down_write(&owning_mm->mmap_sem);
ad9a3668 1845 mutex_lock(&context->vma_private_list_mutex);
7c2344c3
MG		 1846 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1847 list) {
1848 vma = vma_private->vma;
1849 ret = zap_vma_ptes(vma, vma->vm_start,
1850 PAGE_SIZE);
1851 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1852 /* context going to be destroyed, should
1853 * not access ops any more.
1854 */
13776612 1855 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
7c2344c3
MG		 1856 vma->vm_ops = NULL;
1857 list_del(&vma_private->list);
1858 kfree(vma_private);
1859 }
ad9a3668 1860 mutex_unlock(&context->vma_private_list_mutex);
ecc7d83b 1861 up_write(&owning_mm->mmap_sem);
7c2344c3
MG		 1862 mmput(owning_mm);
1863 put_task_struct(owning_process);
1864}
1865
37aa5c36
GL		 1866static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1867{
1868 switch (cmd) {
1869 case MLX5_IB_MMAP_WC_PAGE:
1870 return "WC";
1871 case MLX5_IB_MMAP_REGULAR_PAGE:
1872 return "best effort WC";
1873 case MLX5_IB_MMAP_NC_PAGE:
1874 return "NC";
1875 default:
1876 return NULL;
1877 }
1878}
1879
1880static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
7c2344c3
MG		 1881 struct vm_area_struct *vma,
1882 struct mlx5_ib_ucontext *context)
37aa5c36 1883{
2f5ff264 1884 struct mlx5_bfreg_info *bfregi = &context->bfregi;
37aa5c36
GL		 1885 int err;
1886 unsigned long idx;
1887 phys_addr_t pfn, pa;
1888 pgprot_t prot;
4ed131d0
YH		 1889 u32 bfreg_dyn_idx = 0;
1890 u32 uar_index;
1891 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
1892 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
1893 bfregi->num_static_sys_pages;
b037c29a
EC		 1894
1895 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1896 return -EINVAL;
1897
4ed131d0
YH		 1898 if (dyn_uar)
1899 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
1900 else
1901 idx = get_index(vma->vm_pgoff);
1902
1903 if (idx >= max_valid_idx) {
1904 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
1905 idx, max_valid_idx);
b037c29a
EC		 1906 return -EINVAL;
1907 }
37aa5c36
GL		 1908
1909 switch (cmd) {
1910 case MLX5_IB_MMAP_WC_PAGE:
4ed131d0 1911 case MLX5_IB_MMAP_ALLOC_WC:
37aa5c36
GL		 1912/* Some architectures don't support WC memory */
1913#if defined(CONFIG_X86)
1914 if (!pat_enabled())
1915 return -EPERM;
1916#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1917 return -EPERM;
1918#endif
1919 /* fall through */
1920 case MLX5_IB_MMAP_REGULAR_PAGE:
1921 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1922 prot = pgprot_writecombine(vma->vm_page_prot);
1923 break;
1924 case MLX5_IB_MMAP_NC_PAGE:
1925 prot = pgprot_noncached(vma->vm_page_prot);
1926 break;
1927 default:
1928 return -EINVAL;
1929 }
1930
4ed131d0
YH		 1931 if (dyn_uar) {
1932 int uars_per_page;
1933
1934 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1935 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
1936 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
1937 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
1938 bfreg_dyn_idx, bfregi->total_num_bfregs);
1939 return -EINVAL;
1940 }
1941
1942 mutex_lock(&bfregi->lock);
1943 /* Fail if uar already allocated, first bfreg index of each
1944 * page holds its count.
1945 */
1946 if (bfregi->count[bfreg_dyn_idx]) {
1947 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
1948 mutex_unlock(&bfregi->lock);
1949 return -EINVAL;
1950 }
1951
1952 bfregi->count[bfreg_dyn_idx]++;
1953 mutex_unlock(&bfregi->lock);
1954
1955 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
1956 if (err) {
1957 mlx5_ib_warn(dev, "UAR alloc failed\n");
1958 goto free_bfreg;
1959 }
1960 } else {
1961 uar_index = bfregi->sys_pages[idx];
1962 }
1963
1964 pfn = uar_index2pfn(dev, uar_index);
37aa5c36
GL		 1965 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1966
1967 vma->vm_page_prot = prot;
1968 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1969 PAGE_SIZE, vma->vm_page_prot);
1970 if (err) {
1971 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1972 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
4ed131d0
YH		 1973 err = -EAGAIN;
1974 goto err;
37aa5c36
GL		 1975 }
1976
1977 pa = pfn << PAGE_SHIFT;
1978 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1979 vma->vm_start, &pa);
1980
4ed131d0
YH		 1981 err = mlx5_ib_set_vma_data(vma, context);
1982 if (err)
1983 goto err;
1984
1985 if (dyn_uar)
1986 bfregi->sys_pages[idx] = uar_index;
1987 return 0;
1988
1989err:
1990 if (!dyn_uar)
1991 return err;
1992
1993 mlx5_cmd_free_uar(dev->mdev, idx);
1994
1995free_bfreg:
1996 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
1997
1998 return err;
37aa5c36
GL		 1999}
2000
e126ba97
EC		 2001static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2002{
2003 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2004 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
e126ba97 2005 unsigned long command;
e126ba97
EC		 2006 phys_addr_t pfn;
2007
2008 command = get_command(vma->vm_pgoff);
2009 switch (command) {
37aa5c36
GL		 2010 case MLX5_IB_MMAP_WC_PAGE:
2011 case MLX5_IB_MMAP_NC_PAGE:
e126ba97 2012 case MLX5_IB_MMAP_REGULAR_PAGE:
4ed131d0 2013 case MLX5_IB_MMAP_ALLOC_WC:
7c2344c3 2014 return uar_mmap(dev, command, vma, context);
e126ba97
EC		 2015
2016 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2017 return -ENOSYS;
2018
d69e3bcf 2019 case MLX5_IB_MMAP_CORE_CLOCK:
d69e3bcf
MB		 2020 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2021 return -EINVAL;
2022
6cbac1e4 2023 if (vma->vm_flags & VM_WRITE)
d69e3bcf
MB		 2024 return -EPERM;
2025
2026 /* Don't expose to user-space information it shouldn't have */
2027 if (PAGE_SIZE > 4096)
2028 return -EOPNOTSUPP;
2029
2030 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2031 pfn = (dev->mdev->iseg_base +
2032 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2033 PAGE_SHIFT;
2034 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2035 PAGE_SIZE, vma->vm_page_prot))
2036 return -EAGAIN;
2037
2038 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2039 vma->vm_start,
2040 (unsigned long long)pfn << PAGE_SHIFT);
2041 break;
d69e3bcf 2042
e126ba97
EC		 2043 default:
2044 return -EINVAL;
2045 }
2046
2047 return 0;
2048}
2049
e126ba97
EC		 2050static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2051 struct ib_ucontext *context,
2052 struct ib_udata *udata)
2053{
2054 struct mlx5_ib_alloc_pd_resp resp;
2055 struct mlx5_ib_pd *pd;
2056 int err;
2057
2058 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2059 if (!pd)
2060 return ERR_PTR(-ENOMEM);
2061
9603b61d 2062 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
e126ba97
EC		 2063 if (err) {
2064 kfree(pd);
2065 return ERR_PTR(err);
2066 }
2067
2068 if (context) {
2069 resp.pdn = pd->pdn;
2070 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
9603b61d 2071 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
e126ba97
EC		 2072 kfree(pd);
2073 return ERR_PTR(-EFAULT);
2074 }
e126ba97
EC		 2075 }
2076
2077 return &pd->ibpd;
2078}
2079
2080static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2081{
2082 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2083 struct mlx5_ib_pd *mpd = to_mpd(pd);
2084
9603b61d 2085 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
e126ba97
EC		 2086 kfree(mpd);
2087
2088 return 0;
2089}
2090
466fa6d2
MG		 2091enum {
2092 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2093 MATCH_CRITERIA_ENABLE_MISC_BIT,
2094 MATCH_CRITERIA_ENABLE_INNER_BIT
2095};
2096
2097#define HEADER_IS_ZERO(match_criteria, headers) \
2098 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2099 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
038d2ef8 2100
466fa6d2 2101static u8 get_match_criteria_enable(u32 *match_criteria)
038d2ef8 2102{
466fa6d2 2103 u8 match_criteria_enable;
038d2ef8 2104
466fa6d2
MG		 2105 match_criteria_enable =
2106 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2107 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2108 match_criteria_enable |=
2109 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2110 MATCH_CRITERIA_ENABLE_MISC_BIT;
2111 match_criteria_enable |=
2112 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2113 MATCH_CRITERIA_ENABLE_INNER_BIT;
2114
2115 return match_criteria_enable;
038d2ef8
MG		 2116}
2117
ca0d4753
MG		 2118static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2119{
2120 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2121 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
038d2ef8
MG		 2122}
2123
2d1e697e
MR		 2124static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2125 bool inner)
2126{
2127 if (inner) {
2128 MLX5_SET(fte_match_set_misc,
2129 misc_c, inner_ipv6_flow_label, mask);
2130 MLX5_SET(fte_match_set_misc,
2131 misc_v, inner_ipv6_flow_label, val);
2132 } else {
2133 MLX5_SET(fte_match_set_misc,
2134 misc_c, outer_ipv6_flow_label, mask);
2135 MLX5_SET(fte_match_set_misc,
2136 misc_v, outer_ipv6_flow_label, val);
2137 }
2138}
2139
ca0d4753
MG		 2140static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2141{
2142 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2143 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2144 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2145 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2146}
2147
c47ac6ae
MG		 2148#define LAST_ETH_FIELD vlan_tag
2149#define LAST_IB_FIELD sl
ca0d4753 2150#define LAST_IPV4_FIELD tos
466fa6d2 2151#define LAST_IPV6_FIELD traffic_class
c47ac6ae 2152#define LAST_TCP_UDP_FIELD src_port
ffb30d8f 2153#define LAST_TUNNEL_FIELD tunnel_id
2ac693f9 2154#define LAST_FLOW_TAG_FIELD tag_id
a22ed86c 2155#define LAST_DROP_FIELD size
c47ac6ae
MG		 2156
2157/* Field is the last supported field */
2158#define FIELDS_NOT_SUPPORTED(filter, field)\
2159 memchr_inv((void *)&filter.field +\
2160 sizeof(filter.field), 0,\
2161 sizeof(filter) -\
2162 offsetof(typeof(filter), field) -\
2163 sizeof(filter.field))
2164
19cc7524
AL		 2165#define IPV4_VERSION 4
2166#define IPV6_VERSION 6
2167static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2168 u32 *match_v, const union ib_flow_spec *ib_spec,
a22ed86c 2169 u32 *tag_id, bool *is_drop)
038d2ef8 2170{
466fa6d2
MG		 2171 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2172 misc_parameters);
2173 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2174 misc_parameters);
2d1e697e
MR		 2175 void *headers_c;
2176 void *headers_v;
19cc7524 2177 int match_ipv;
2d1e697e
MR		 2178
2179 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2180 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2181 inner_headers);
2182 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2183 inner_headers);
19cc7524
AL		 2184 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2185 ft_field_support.inner_ip_version);
2d1e697e
MR		 2186 } else {
2187 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2188 outer_headers);
2189 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2190 outer_headers);
19cc7524
AL		 2191 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2192 ft_field_support.outer_ip_version);
2d1e697e 2193 }
466fa6d2 2194
2d1e697e 2195 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
038d2ef8 2196 case IB_FLOW_SPEC_ETH:
c47ac6ae 2197 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1ffd3a26 2198 return -EOPNOTSUPP;
038d2ef8 2199
2d1e697e 2200 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2201 dmac_47_16),
2202 ib_spec->eth.mask.dst_mac);
2d1e697e 2203 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2204 dmac_47_16),
2205 ib_spec->eth.val.dst_mac);
2206
2d1e697e 2207 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
ee3da804
MG		 2208 smac_47_16),
2209 ib_spec->eth.mask.src_mac);
2d1e697e 2210 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
ee3da804
MG		 2211 smac_47_16),
2212 ib_spec->eth.val.src_mac);
2213
038d2ef8 2214 if (ib_spec->eth.mask.vlan_tag) {
2d1e697e 2215 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
10543365 2216 cvlan_tag, 1);
2d1e697e 2217 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
10543365 2218 cvlan_tag, 1);
038d2ef8 2219
2d1e697e 2220 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2221 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2d1e697e 2222 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2223 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2224
2d1e697e 2225 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2226 first_cfi,
2227 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2d1e697e 2228 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2229 first_cfi,
2230 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2231
2d1e697e 2232 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2233 first_prio,
2234 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2d1e697e 2235 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2236 first_prio,
2237 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2238 }
2d1e697e 2239 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
038d2ef8 2240 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2d1e697e 2241 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2242 ethertype, ntohs(ib_spec->eth.val.ether_type));
2243 break;
2244 case IB_FLOW_SPEC_IPV4:
c47ac6ae 2245 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1ffd3a26 2246 return -EOPNOTSUPP;
038d2ef8 2247
19cc7524
AL		 2248 if (match_ipv) {
2249 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2250 ip_version, 0xf);
2251 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2252 ip_version, IPV4_VERSION);
2253 } else {
2254 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2255 ethertype, 0xffff);
2256 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2257 ethertype, ETH_P_IP);
2258 }
038d2ef8 2259
2d1e697e 2260 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2261 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2262 &ib_spec->ipv4.mask.src_ip,
2263 sizeof(ib_spec->ipv4.mask.src_ip));
2d1e697e 2264 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2265 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2266 &ib_spec->ipv4.val.src_ip,
2267 sizeof(ib_spec->ipv4.val.src_ip));
2d1e697e 2268 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
038d2ef8
MG		 2269 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2270 &ib_spec->ipv4.mask.dst_ip,
2271 sizeof(ib_spec->ipv4.mask.dst_ip));
2d1e697e 2272 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
038d2ef8
MG		 2273 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2274 &ib_spec->ipv4.val.dst_ip,
2275 sizeof(ib_spec->ipv4.val.dst_ip));
ca0d4753 2276
2d1e697e 2277 set_tos(headers_c, headers_v,
ca0d4753
MG		 2278 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2279
2d1e697e 2280 set_proto(headers_c, headers_v,
ca0d4753 2281 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
038d2ef8 2282 break;
026bae0c 2283 case IB_FLOW_SPEC_IPV6:
c47ac6ae 2284 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1ffd3a26 2285 return -EOPNOTSUPP;
026bae0c 2286
19cc7524
AL		 2287 if (match_ipv) {
2288 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2289 ip_version, 0xf);
2290 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2291 ip_version, IPV6_VERSION);
2292 } else {
2293 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2294 ethertype, 0xffff);
2295 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2296 ethertype, ETH_P_IPV6);
2297 }
026bae0c 2298
2d1e697e 2299 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2300 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2301 &ib_spec->ipv6.mask.src_ip,
2302 sizeof(ib_spec->ipv6.mask.src_ip));
2d1e697e 2303 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2304 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2305 &ib_spec->ipv6.val.src_ip,
2306 sizeof(ib_spec->ipv6.val.src_ip));
2d1e697e 2307 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
026bae0c
MG		 2308 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2309 &ib_spec->ipv6.mask.dst_ip,
2310 sizeof(ib_spec->ipv6.mask.dst_ip));
2d1e697e 2311 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
026bae0c
MG		 2312 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2313 &ib_spec->ipv6.val.dst_ip,
2314 sizeof(ib_spec->ipv6.val.dst_ip));
466fa6d2 2315
2d1e697e 2316 set_tos(headers_c, headers_v,
466fa6d2
MG		 2317 ib_spec->ipv6.mask.traffic_class,
2318 ib_spec->ipv6.val.traffic_class);
2319
2d1e697e 2320 set_proto(headers_c, headers_v,
466fa6d2
MG		 2321 ib_spec->ipv6.mask.next_hdr,
2322 ib_spec->ipv6.val.next_hdr);
2323
2d1e697e
MR		 2324 set_flow_label(misc_params_c, misc_params_v,
2325 ntohl(ib_spec->ipv6.mask.flow_label),
2326 ntohl(ib_spec->ipv6.val.flow_label),
2327 ib_spec->type & IB_FLOW_SPEC_INNER);
2328
026bae0c 2329 break;
038d2ef8 2330 case IB_FLOW_SPEC_TCP:
c47ac6ae
MG		 2331 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2332 LAST_TCP_UDP_FIELD))
1ffd3a26 2333 return -EOPNOTSUPP;
038d2ef8 2334
2d1e697e 2335 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2336 0xff);
2d1e697e 2337 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2338 IPPROTO_TCP);
2339
2d1e697e 2340 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
038d2ef8 2341 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2342 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
038d2ef8
MG		 2343 ntohs(ib_spec->tcp_udp.val.src_port));
2344
2d1e697e 2345 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
038d2ef8 2346 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2347 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
038d2ef8
MG		 2348 ntohs(ib_spec->tcp_udp.val.dst_port));
2349 break;
2350 case IB_FLOW_SPEC_UDP:
c47ac6ae
MG		 2351 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2352 LAST_TCP_UDP_FIELD))
1ffd3a26 2353 return -EOPNOTSUPP;
038d2ef8 2354
2d1e697e 2355 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
038d2ef8 2356 0xff);
2d1e697e 2357 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
038d2ef8
MG		 2358 IPPROTO_UDP);
2359
2d1e697e 2360 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
038d2ef8 2361 ntohs(ib_spec->tcp_udp.mask.src_port));
2d1e697e 2362 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
038d2ef8
MG		 2363 ntohs(ib_spec->tcp_udp.val.src_port));
2364
2d1e697e 2365 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
038d2ef8 2366 ntohs(ib_spec->tcp_udp.mask.dst_port));
2d1e697e 2367 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
038d2ef8
MG		 2368 ntohs(ib_spec->tcp_udp.val.dst_port));
2369 break;
ffb30d8f
MR		 2370 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2371 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2372 LAST_TUNNEL_FIELD))
1ffd3a26 2373 return -EOPNOTSUPP;
ffb30d8f
MR		 2374
2375 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2376 ntohl(ib_spec->tunnel.mask.tunnel_id));
2377 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2378 ntohl(ib_spec->tunnel.val.tunnel_id));
2379 break;
2ac693f9
MR		 2380 case IB_FLOW_SPEC_ACTION_TAG:
2381 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2382 LAST_FLOW_TAG_FIELD))
2383 return -EOPNOTSUPP;
2384 if (ib_spec->flow_tag.tag_id >= BIT(24))
2385 return -EINVAL;
2386
2387 *tag_id = ib_spec->flow_tag.tag_id;
2388 break;
a22ed86c
SS		 2389 case IB_FLOW_SPEC_ACTION_DROP:
2390 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2391 LAST_DROP_FIELD))
2392 return -EOPNOTSUPP;
2393 *is_drop = true;
2394 break;
038d2ef8
MG		 2395 default:
2396 return -EINVAL;
2397 }
2398
2399 return 0;
2400}
2401
2402/* If a flow could catch both multicast and unicast packets,
2403 * it won't fall into the multicast flow steering table and this rule
2404 * could steal other multicast packets.
2405 */
a550ddfc 2406static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
038d2ef8 2407{
81e30880 2408 union ib_flow_spec *flow_spec;
038d2ef8
MG		 2409
2410 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
038d2ef8
MG		 2411 ib_attr->num_of_specs < 1)
2412 return false;
2413
81e30880
YH		 2414 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2415 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2416 struct ib_flow_spec_ipv4 *ipv4_spec;
2417
2418 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2419 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2420 return true;
2421
038d2ef8 2422 return false;
81e30880
YH		 2423 }
2424
2425 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2426 struct ib_flow_spec_eth *eth_spec;
2427
2428 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2429 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2430 is_multicast_ether_addr(eth_spec->val.dst_mac);
2431 }
038d2ef8 2432
81e30880 2433 return false;
038d2ef8
MG		 2434}
2435
19cc7524
AL		 2436static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2437 const struct ib_flow_attr *flow_attr,
0f750966 2438 bool check_inner)
038d2ef8
MG		 2439{
2440 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
19cc7524
AL		 2441 int match_ipv = check_inner ?
2442 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2443 ft_field_support.inner_ip_version) :
2444 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2445 ft_field_support.outer_ip_version);
0f750966
AL		 2446 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2447 bool ipv4_spec_valid, ipv6_spec_valid;
2448 unsigned int ip_spec_type = 0;
2449 bool has_ethertype = false;
038d2ef8 2450 unsigned int spec_index;
0f750966
AL		 2451 bool mask_valid = true;
2452 u16 eth_type = 0;
2453 bool type_valid;
038d2ef8
MG		 2454
2455 /* Validate that ethertype is correct */
2456 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
0f750966 2457 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
038d2ef8 2458 ib_spec->eth.mask.ether_type) {
0f750966
AL		 2459 mask_valid = (ib_spec->eth.mask.ether_type ==
2460 htons(0xffff));
2461 has_ethertype = true;
2462 eth_type = ntohs(ib_spec->eth.val.ether_type);
2463 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2464 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2465 ip_spec_type = ib_spec->type;
038d2ef8
MG		 2466 }
2467 ib_spec = (void *)ib_spec + ib_spec->size;
2468 }
0f750966
AL		 2469
2470 type_valid = (!has_ethertype) || (!ip_spec_type);
2471 if (!type_valid && mask_valid) {
2472 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2473 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2474 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2475 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
19cc7524
AL		 2476
2477 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2478 (((eth_type == ETH_P_MPLS_UC) ||
2479 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
0f750966
AL		 2480 }
2481
2482 return type_valid;
2483}
2484
19cc7524
AL		 2485static bool is_valid_attr(struct mlx5_core_dev *mdev,
2486 const struct ib_flow_attr *flow_attr)
0f750966 2487{
19cc7524
AL		 2488 return is_valid_ethertype(mdev, flow_attr, false) &&
2489 is_valid_ethertype(mdev, flow_attr, true);
038d2ef8
MG		 2490}
2491
2492static void put_flow_table(struct mlx5_ib_dev *dev,
2493 struct mlx5_ib_flow_prio *prio, bool ft_added)
2494{
2495 prio->refcount -= !!ft_added;
2496 if (!prio->refcount) {
2497 mlx5_destroy_flow_table(prio->flow_table);
2498 prio->flow_table = NULL;
2499 }
2500}
2501
2502static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2503{
2504 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2505 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2506 struct mlx5_ib_flow_handler,
2507 ibflow);
2508 struct mlx5_ib_flow_handler *iter, *tmp;
2509
2510 mutex_lock(&dev->flow_db.lock);
2511
2512 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
74491de9 2513 mlx5_del_flow_rules(iter->rule);
cc0e5d42 2514 put_flow_table(dev, iter->prio, true);
038d2ef8
MG		 2515 list_del(&iter->list);
2516 kfree(iter);
2517 }
2518
74491de9 2519 mlx5_del_flow_rules(handler->rule);
5497adc6 2520 put_flow_table(dev, handler->prio, true);
038d2ef8
MG		 2521 mutex_unlock(&dev->flow_db.lock);
2522
2523 kfree(handler);
2524
2525 return 0;
2526}
2527
35d19011
MG		 2528static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2529{
2530 priority *= 2;
2531 if (!dont_trap)
2532 priority++;
2533 return priority;
2534}
2535
cc0e5d42
MG		 2536enum flow_table_type {
2537 MLX5_IB_FT_RX,
2538 MLX5_IB_FT_TX
2539};
2540
00b7c2ab
MG		 2541#define MLX5_FS_MAX_TYPES 6
2542#define MLX5_FS_MAX_ENTRIES BIT(16)
038d2ef8 2543static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
cc0e5d42
MG		 2544 struct ib_flow_attr *flow_attr,
2545 enum flow_table_type ft_type)
038d2ef8 2546{
35d19011 2547 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
038d2ef8
MG		 2548 struct mlx5_flow_namespace *ns = NULL;
2549 struct mlx5_ib_flow_prio *prio;
2550 struct mlx5_flow_table *ft;
dac388ef 2551 int max_table_size;
038d2ef8
MG		 2552 int num_entries;
2553 int num_groups;
2554 int priority;
2555 int err = 0;
2556
dac388ef
MG		 2557 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2558 log_max_ft_size));
038d2ef8 2559 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2560 if (flow_is_multicast_only(flow_attr) &&
2561 !dont_trap)
038d2ef8
MG		 2562 priority = MLX5_IB_FLOW_MCAST_PRIO;
2563 else
35d19011
MG		 2564 priority = ib_prio_to_core_prio(flow_attr->priority,
2565 dont_trap);
038d2ef8
MG		 2566 ns = mlx5_get_flow_namespace(dev->mdev,
2567 MLX5_FLOW_NAMESPACE_BYPASS);
2568 num_entries = MLX5_FS_MAX_ENTRIES;
2569 num_groups = MLX5_FS_MAX_TYPES;
2570 prio = &dev->flow_db.prios[priority];
2571 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2572 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2573 ns = mlx5_get_flow_namespace(dev->mdev,
2574 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2575 build_leftovers_ft_param(&priority,
2576 &num_entries,
2577 &num_groups);
2578 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
cc0e5d42
MG		 2579 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2580 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2581 allow_sniffer_and_nic_rx_shared_tir))
2582 return ERR_PTR(-ENOTSUPP);
2583
2584 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2585 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2586 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2587
2588 prio = &dev->flow_db.sniffer[ft_type];
2589 priority = 0;
2590 num_entries = 1;
2591 num_groups = 1;
038d2ef8
MG		 2592 }
2593
2594 if (!ns)
2595 return ERR_PTR(-ENOTSUPP);
2596
dac388ef
MG		 2597 if (num_entries > max_table_size)
2598 return ERR_PTR(-ENOMEM);
2599
038d2ef8
MG		 2600 ft = prio->flow_table;
2601 if (!ft) {
2602 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2603 num_entries,
d63cd286 2604 num_groups,
c9f1b073 2605 0, 0);
038d2ef8
MG		 2606
2607 if (!IS_ERR(ft)) {
2608 prio->refcount = 0;
2609 prio->flow_table = ft;
2610 } else {
2611 err = PTR_ERR(ft);
2612 }
2613 }
2614
2615 return err ? ERR_PTR(err) : prio;
2616}
2617
a550ddfc
YH		 2618static void set_underlay_qp(struct mlx5_ib_dev *dev,
2619 struct mlx5_flow_spec *spec,
2620 u32 underlay_qpn)
2621{
2622 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2623 spec->match_criteria,
2624 misc_parameters);
2625 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2626 misc_parameters);
2627
2628 if (underlay_qpn &&
2629 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2630 ft_field_support.bth_dst_qp)) {
2631 MLX5_SET(fte_match_set_misc,
2632 misc_params_v, bth_dst_qp, underlay_qpn);
2633 MLX5_SET(fte_match_set_misc,
2634 misc_params_c, bth_dst_qp, 0xffffff);
2635 }
2636}
2637
2638static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2639 struct mlx5_ib_flow_prio *ft_prio,
2640 const struct ib_flow_attr *flow_attr,
2641 struct mlx5_flow_destination *dst,
2642 u32 underlay_qpn)
038d2ef8
MG		 2643{
2644 struct mlx5_flow_table *ft = ft_prio->flow_table;
2645 struct mlx5_ib_flow_handler *handler;
66958ed9 2646 struct mlx5_flow_act flow_act = {0};
c5bb1730 2647 struct mlx5_flow_spec *spec;
a22ed86c 2648 struct mlx5_flow_destination *rule_dst = dst;
dd063d0e 2649 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
038d2ef8 2650 unsigned int spec_index;
2ac693f9 2651 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
a22ed86c 2652 bool is_drop = false;
038d2ef8 2653 int err = 0;
a22ed86c 2654 int dest_num = 1;
038d2ef8 2655
19cc7524 2656 if (!is_valid_attr(dev->mdev, flow_attr))
038d2ef8
MG		 2657 return ERR_PTR(-EINVAL);
2658
1b9a07ee 2659 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
038d2ef8 2660 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
c5bb1730 2661 if (!handler || !spec) {
038d2ef8
MG		 2662 err = -ENOMEM;
2663 goto free;
2664 }
2665
2666 INIT_LIST_HEAD(&handler->list);
2667
2668 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
19cc7524 2669 err = parse_flow_attr(dev->mdev, spec->match_criteria,
a22ed86c
SS		 2670 spec->match_value,
2671 ib_flow, &flow_tag, &is_drop);
038d2ef8
MG		 2672 if (err < 0)
2673 goto free;
2674
2675 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2676 }
2677
a550ddfc
YH		 2678 if (!flow_is_multicast_only(flow_attr))
2679 set_underlay_qp(dev, spec, underlay_qpn);
2680
466fa6d2 2681 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
a22ed86c
SS		 2682 if (is_drop) {
2683 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2684 rule_dst = NULL;
2685 dest_num = 0;
2686 } else {
2687 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2688 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2689 }
2ac693f9
MR		 2690
2691 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2692 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2693 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2694 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2695 flow_tag, flow_attr->type);
2696 err = -EINVAL;
2697 goto free;
2698 }
2699 flow_act.flow_tag = flow_tag;
74491de9 2700 handler->rule = mlx5_add_flow_rules(ft, spec,
66958ed9 2701 &flow_act,
a22ed86c 2702 rule_dst, dest_num);
038d2ef8
MG		 2703
2704 if (IS_ERR(handler->rule)) {
2705 err = PTR_ERR(handler->rule);
2706 goto free;
2707 }
2708
d9d4980a 2709 ft_prio->refcount++;
5497adc6 2710 handler->prio = ft_prio;
038d2ef8
MG		 2711
2712 ft_prio->flow_table = ft;
2713free:
2714 if (err)
2715 kfree(handler);
c5bb1730 2716 kvfree(spec);
038d2ef8
MG		 2717 return err ? ERR_PTR(err) : handler;
2718}
2719
a550ddfc
YH		 2720static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2721 struct mlx5_ib_flow_prio *ft_prio,
2722 const struct ib_flow_attr *flow_attr,
2723 struct mlx5_flow_destination *dst)
2724{
2725 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2726}
2727
35d19011
MG		 2728static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2729 struct mlx5_ib_flow_prio *ft_prio,
2730 struct ib_flow_attr *flow_attr,
2731 struct mlx5_flow_destination *dst)
2732{
2733 struct mlx5_ib_flow_handler *handler_dst = NULL;
2734 struct mlx5_ib_flow_handler *handler = NULL;
2735
2736 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2737 if (!IS_ERR(handler)) {
2738 handler_dst = create_flow_rule(dev, ft_prio,
2739 flow_attr, dst);
2740 if (IS_ERR(handler_dst)) {
74491de9 2741 mlx5_del_flow_rules(handler->rule);
d9d4980a 2742 ft_prio->refcount--;
35d19011
MG		 2743 kfree(handler);
2744 handler = handler_dst;
2745 } else {
2746 list_add(&handler_dst->list, &handler->list);
2747 }
2748 }
2749
2750 return handler;
2751}
038d2ef8
MG		 2752enum {
2753 LEFTOVERS_MC,
2754 LEFTOVERS_UC,
2755};
2756
2757static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2758 struct mlx5_ib_flow_prio *ft_prio,
2759 struct ib_flow_attr *flow_attr,
2760 struct mlx5_flow_destination *dst)
2761{
2762 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2763 struct mlx5_ib_flow_handler *handler = NULL;
2764
2765 static struct {
2766 struct ib_flow_attr flow_attr;
2767 struct ib_flow_spec_eth eth_flow;
2768 } leftovers_specs[] = {
2769 [LEFTOVERS_MC] = {
2770 .flow_attr = {
2771 .num_of_specs = 1,
2772 .size = sizeof(leftovers_specs[0])
2773 },
2774 .eth_flow = {
2775 .type = IB_FLOW_SPEC_ETH,
2776 .size = sizeof(struct ib_flow_spec_eth),
2777 .mask = {.dst_mac = {0x1} },
2778 .val = {.dst_mac = {0x1} }
2779 }
2780 },
2781 [LEFTOVERS_UC] = {
2782 .flow_attr = {
2783 .num_of_specs = 1,
2784 .size = sizeof(leftovers_specs[0])
2785 },
2786 .eth_flow = {
2787 .type = IB_FLOW_SPEC_ETH,
2788 .size = sizeof(struct ib_flow_spec_eth),
2789 .mask = {.dst_mac = {0x1} },
2790 .val = {.dst_mac = {} }
2791 }
2792 }
2793 };
2794
2795 handler = create_flow_rule(dev, ft_prio,
2796 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2797 dst);
2798 if (!IS_ERR(handler) &&
2799 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2800 handler_ucast = create_flow_rule(dev, ft_prio,
2801 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2802 dst);
2803 if (IS_ERR(handler_ucast)) {
74491de9 2804 mlx5_del_flow_rules(handler->rule);
d9d4980a 2805 ft_prio->refcount--;
038d2ef8
MG		 2806 kfree(handler);
2807 handler = handler_ucast;
2808 } else {
2809 list_add(&handler_ucast->list, &handler->list);
2810 }
2811 }
2812
2813 return handler;
2814}
2815
cc0e5d42
MG		 2816static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2817 struct mlx5_ib_flow_prio *ft_rx,
2818 struct mlx5_ib_flow_prio *ft_tx,
2819 struct mlx5_flow_destination *dst)
2820{
2821 struct mlx5_ib_flow_handler *handler_rx;
2822 struct mlx5_ib_flow_handler *handler_tx;
2823 int err;
2824 static const struct ib_flow_attr flow_attr = {
2825 .num_of_specs = 0,
2826 .size = sizeof(flow_attr)
2827 };
2828
2829 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2830 if (IS_ERR(handler_rx)) {
2831 err = PTR_ERR(handler_rx);
2832 goto err;
2833 }
2834
2835 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2836 if (IS_ERR(handler_tx)) {
2837 err = PTR_ERR(handler_tx);
2838 goto err_tx;
2839 }
2840
2841 list_add(&handler_tx->list, &handler_rx->list);
2842
2843 return handler_rx;
2844
2845err_tx:
74491de9 2846 mlx5_del_flow_rules(handler_rx->rule);
cc0e5d42
MG		 2847 ft_rx->refcount--;
2848 kfree(handler_rx);
2849err:
2850 return ERR_PTR(err);
2851}
2852
038d2ef8
MG		 2853static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2854 struct ib_flow_attr *flow_attr,
2855 int domain)
2856{
2857 struct mlx5_ib_dev *dev = to_mdev(qp->device);
d9f88e5a 2858 struct mlx5_ib_qp *mqp = to_mqp(qp);
038d2ef8
MG		 2859 struct mlx5_ib_flow_handler *handler = NULL;
2860 struct mlx5_flow_destination *dst = NULL;
cc0e5d42 2861 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
038d2ef8
MG		 2862 struct mlx5_ib_flow_prio *ft_prio;
2863 int err;
a550ddfc 2864 int underlay_qpn;
038d2ef8
MG		 2865
2866 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
dac388ef 2867 return ERR_PTR(-ENOMEM);
038d2ef8
MG		 2868
2869 if (domain != IB_FLOW_DOMAIN_USER ||
508562d6 2870 flow_attr->port > dev->num_ports ||
35d19011 2871 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
038d2ef8
MG		 2872 return ERR_PTR(-EINVAL);
2873
2874 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2875 if (!dst)
2876 return ERR_PTR(-ENOMEM);
2877
2878 mutex_lock(&dev->flow_db.lock);
2879
cc0e5d42 2880 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
038d2ef8
MG		 2881 if (IS_ERR(ft_prio)) {
2882 err = PTR_ERR(ft_prio);
2883 goto unlock;
2884 }
cc0e5d42
MG		 2885 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2886 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2887 if (IS_ERR(ft_prio_tx)) {
2888 err = PTR_ERR(ft_prio_tx);
2889 ft_prio_tx = NULL;
2890 goto destroy_ft;
2891 }
2892 }
038d2ef8
MG		 2893
2894 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
d9f88e5a
YH		 2895 if (mqp->flags & MLX5_IB_QP_RSS)
2896 dst->tir_num = mqp->rss_qp.tirn;
2897 else
2898 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
038d2ef8
MG		 2899
2900 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
35d19011
MG		 2901 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2902 handler = create_dont_trap_rule(dev, ft_prio,
2903 flow_attr, dst);
2904 } else {
a550ddfc
YH		 2905 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
2906 mqp->underlay_qpn : 0;
2907 handler = _create_flow_rule(dev, ft_prio, flow_attr,
2908 dst, underlay_qpn);
35d19011 2909 }
038d2ef8
MG		 2910 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2911 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2912 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2913 dst);
cc0e5d42
MG		 2914 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2915 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
038d2ef8
MG		 2916 } else {
2917 err = -EINVAL;
2918 goto destroy_ft;
2919 }
2920
2921 if (IS_ERR(handler)) {
2922 err = PTR_ERR(handler);
2923 handler = NULL;
2924 goto destroy_ft;
2925 }
2926
038d2ef8
MG		 2927 mutex_unlock(&dev->flow_db.lock);
2928 kfree(dst);
2929
2930 return &handler->ibflow;
2931
2932destroy_ft:
2933 put_flow_table(dev, ft_prio, false);
cc0e5d42
MG		 2934 if (ft_prio_tx)
2935 put_flow_table(dev, ft_prio_tx, false);
038d2ef8
MG		 2936unlock:
2937 mutex_unlock(&dev->flow_db.lock);
2938 kfree(dst);
2939 kfree(handler);
2940 return ERR_PTR(err);
2941}
2942
e126ba97
EC		 2943static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2944{
2945 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
81e30880 2946 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
e126ba97
EC		 2947 int err;
2948
81e30880
YH		 2949 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
2950 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2951 return -EOPNOTSUPP;
2952 }
2953
9603b61d 2954 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2955 if (err)
2956 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2957 ibqp->qp_num, gid->raw);
2958
2959 return err;
2960}
2961
2962static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2963{
2964 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2965 int err;
2966
9603b61d 2967 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
e126ba97
EC		 2968 if (err)
2969 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2970 ibqp->qp_num, gid->raw);
2971
2972 return err;
2973}
2974
2975static int init_node_data(struct mlx5_ib_dev *dev)
2976{
1b5daf11 2977 int err;
e126ba97 2978
1b5daf11 2979 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
e126ba97 2980 if (err)
1b5daf11 2981 return err;
e126ba97 2982
1b5daf11 2983 dev->mdev->rev_id = dev->mdev->pdev->revision;
e126ba97 2984
1b5daf11 2985 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
e126ba97
EC		 2986}
2987
2988static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2989 char *buf)
2990{
2991 struct mlx5_ib_dev *dev =
2992 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2993
9603b61d 2994 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
e126ba97
EC		 2995}
2996
2997static ssize_t show_reg_pages(struct device *device,
2998 struct device_attribute *attr, char *buf)
2999{
3000 struct mlx5_ib_dev *dev =
3001 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3002
6aec21f6 3003 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
e126ba97
EC		 3004}
3005
3006static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3007 char *buf)
3008{
3009 struct mlx5_ib_dev *dev =
3010 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3011 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
e126ba97
EC		 3012}
3013
e126ba97
EC		 3014static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3015 char *buf)
3016{
3017 struct mlx5_ib_dev *dev =
3018 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
9603b61d 3019 return sprintf(buf, "%x\n", dev->mdev->rev_id);
e126ba97
EC		 3020}
3021
3022static ssize_t show_board(struct device *device, struct device_attribute *attr,
3023 char *buf)
3024{
3025 struct mlx5_ib_dev *dev =
3026 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3027 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
9603b61d 3028 dev->mdev->board_id);
e126ba97
EC		 3029}
3030
3031static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
e126ba97
EC		 3032static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
3033static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
3034static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3035static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3036
3037static struct device_attribute *mlx5_class_attributes[] = {
3038 &dev_attr_hw_rev,
e126ba97
EC		 3039 &dev_attr_hca_type,
3040 &dev_attr_board_id,
3041 &dev_attr_fw_pages,
3042 &dev_attr_reg_pages,
3043};
3044
7722f47e
HE		 3045static void pkey_change_handler(struct work_struct *work)
3046{
3047 struct mlx5_ib_port_resources *ports =
3048 container_of(work, struct mlx5_ib_port_resources,
3049 pkey_change_work);
3050
3051 mutex_lock(&ports->devr->mutex);
3052 mlx5_ib_gsi_pkey_change(ports->gsi);
3053 mutex_unlock(&ports->devr->mutex);
3054}
3055
89ea94a7
MG		 3056static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3057{
3058 struct mlx5_ib_qp *mqp;
3059 struct mlx5_ib_cq *send_mcq, *recv_mcq;
3060 struct mlx5_core_cq *mcq;
3061 struct list_head cq_armed_list;
3062 unsigned long flags_qp;
3063 unsigned long flags_cq;
3064 unsigned long flags;
3065
3066 INIT_LIST_HEAD(&cq_armed_list);
3067
3068 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3069 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3070 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3071 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3072 if (mqp->sq.tail != mqp->sq.head) {
3073 send_mcq = to_mcq(mqp->ibqp.send_cq);
3074 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3075 if (send_mcq->mcq.comp &&
3076 mqp->ibqp.send_cq->comp_handler) {
3077 if (!send_mcq->mcq.reset_notify_added) {
3078 send_mcq->mcq.reset_notify_added = 1;
3079 list_add_tail(&send_mcq->mcq.reset_notify,
3080 &cq_armed_list);
3081 }
3082 }
3083 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3084 }
3085 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3086 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3087 /* no handling is needed for SRQ */
3088 if (!mqp->ibqp.srq) {
3089 if (mqp->rq.tail != mqp->rq.head) {
3090 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3091 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3092 if (recv_mcq->mcq.comp &&
3093 mqp->ibqp.recv_cq->comp_handler) {
3094 if (!recv_mcq->mcq.reset_notify_added) {
3095 recv_mcq->mcq.reset_notify_added = 1;
3096 list_add_tail(&recv_mcq->mcq.reset_notify,
3097 &cq_armed_list);
3098 }
3099 }
3100 spin_unlock_irqrestore(&recv_mcq->lock,
3101 flags_cq);
3102 }
3103 }
3104 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3105 }
3106 /*At that point all inflight post send were put to be executed as of we
3107 * lock/unlock above locks Now need to arm all involved CQs.
3108 */
3109 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3110 mcq->comp(mcq);
3111 }
3112 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3113}
3114
03404e8a
MG		 3115static void delay_drop_handler(struct work_struct *work)
3116{
3117 int err;
3118 struct mlx5_ib_delay_drop *delay_drop =
3119 container_of(work, struct mlx5_ib_delay_drop,
3120 delay_drop_work);
3121
fe248c3a
MG		 3122 atomic_inc(&delay_drop->events_cnt);
3123
03404e8a
MG		 3124 mutex_lock(&delay_drop->lock);
3125 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3126 delay_drop->timeout);
3127 if (err) {
3128 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3129 delay_drop->timeout);
3130 delay_drop->activate = false;
3131 }
3132 mutex_unlock(&delay_drop->lock);
3133}
3134
9603b61d 3135static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4d2f9bbb 3136 enum mlx5_dev_event event, unsigned long param)
e126ba97 3137{
9603b61d 3138 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
e126ba97 3139 struct ib_event ibev;
dbaaff2a 3140 bool fatal = false;
e126ba97
EC		 3141 u8 port = 0;
3142
3143 switch (event) {
3144 case MLX5_DEV_EVENT_SYS_ERROR:
e126ba97 3145 ibev.event = IB_EVENT_DEVICE_FATAL;
89ea94a7 3146 mlx5_ib_handle_internal_error(ibdev);
dbaaff2a 3147 fatal = true;
e126ba97
EC		 3148 break;
3149
3150 case MLX5_DEV_EVENT_PORT_UP:
e126ba97 3151 case MLX5_DEV_EVENT_PORT_DOWN:
2788cf3b 3152 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4d2f9bbb 3153 port = (u8)param;
5ec8c83e
AH		 3154
3155 /* In RoCE, port up/down events are handled in
3156 * mlx5_netdev_event().
3157 */
3158 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3159 IB_LINK_LAYER_ETHERNET)
3160 return;
3161
3162 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
3163 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
e126ba97
EC		 3164 break;
3165
e126ba97
EC		 3166 case MLX5_DEV_EVENT_LID_CHANGE:
3167 ibev.event = IB_EVENT_LID_CHANGE;
4d2f9bbb 3168 port = (u8)param;
e126ba97
EC		 3169 break;
3170
3171 case MLX5_DEV_EVENT_PKEY_CHANGE:
3172 ibev.event = IB_EVENT_PKEY_CHANGE;
4d2f9bbb 3173 port = (u8)param;
7722f47e
HE		 3174
3175 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
e126ba97
EC		 3176 break;
3177
3178 case MLX5_DEV_EVENT_GUID_CHANGE:
3179 ibev.event = IB_EVENT_GID_CHANGE;
4d2f9bbb 3180 port = (u8)param;
e126ba97
EC		 3181 break;
3182
3183 case MLX5_DEV_EVENT_CLIENT_REREG:
3184 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4d2f9bbb 3185 port = (u8)param;
e126ba97 3186 break;
03404e8a
MG		 3187 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3188 schedule_work(&ibdev->delay_drop.delay_drop_work);
3189 goto out;
bdc37924 3190 default:
03404e8a 3191 goto out;
e126ba97
EC		 3192 }
3193
3194 ibev.device = &ibdev->ib_dev;
3195 ibev.element.port_num = port;
3196
a0c84c32
EC		 3197 if (port < 1 || port > ibdev->num_ports) {
3198 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
03404e8a 3199 goto out;
a0c84c32
EC		 3200 }
3201
e126ba97
EC		 3202 if (ibdev->ib_active)
3203 ib_dispatch_event(&ibev);
dbaaff2a
EC		 3204
3205 if (fatal)
3206 ibdev->ib_active = false;
03404e8a
MG		 3207
3208out:
3209 return;
e126ba97
EC		 3210}
3211
c43f1112
MG		 3212static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3213{
3214 struct mlx5_hca_vport_context vport_ctx;
3215 int err;
3216 int port;
3217
508562d6 3218 for (port = 1; port <= dev->num_ports; port++) {
c43f1112
MG		 3219 dev->mdev->port_caps[port - 1].has_smi = false;
3220 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3221 MLX5_CAP_PORT_TYPE_IB) {
3222 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3223 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3224 port, 0,
3225 &vport_ctx);
3226 if (err) {
3227 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3228 port, err);
3229 return err;
3230 }
3231 dev->mdev->port_caps[port - 1].has_smi =
3232 vport_ctx.has_smi;
3233 } else {
3234 dev->mdev->port_caps[port - 1].has_smi = true;
3235 }
3236 }
3237 }
3238 return 0;
3239}
3240
e126ba97
EC		 3241static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3242{
3243 int port;
3244
508562d6 3245 for (port = 1; port <= dev->num_ports; port++)
e126ba97
EC		 3246 mlx5_query_ext_port_caps(dev, port);
3247}
3248
32f69e4b 3249static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
e126ba97
EC		 3250{
3251 struct ib_device_attr *dprops = NULL;
3252 struct ib_port_attr *pprops = NULL;
f614fc15 3253 int err = -ENOMEM;
2528e33e 3254 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
e126ba97
EC		 3255
3256 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3257 if (!pprops)
3258 goto out;
3259
3260 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3261 if (!dprops)
3262 goto out;
3263
c43f1112
MG		 3264 err = set_has_smi_cap(dev);
3265 if (err)
3266 goto out;
3267
2528e33e 3268 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
e126ba97
EC		 3269 if (err) {
3270 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3271 goto out;
3272 }
3273
32f69e4b
DJ		 3274 memset(pprops, 0, sizeof(*pprops));
3275 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3276 if (err) {
3277 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3278 port, err);
3279 goto out;
e126ba97
EC		 3280 }
3281
32f69e4b
DJ		 3282 dev->mdev->port_caps[port - 1].pkey_table_len =
3283 dprops->max_pkeys;
3284 dev->mdev->port_caps[port - 1].gid_table_len =
3285 pprops->gid_tbl_len;
3286 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3287 port, dprops->max_pkeys, pprops->gid_tbl_len);
3288
e126ba97
EC		 3289out:
3290 kfree(pprops);
3291 kfree(dprops);
3292
3293 return err;
3294}
3295
3296static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3297{
3298 int err;
3299
3300 err = mlx5_mr_cache_cleanup(dev);
3301 if (err)
3302 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3303
3304 mlx5_ib_destroy_qp(dev->umrc.qp);
add08d76 3305 ib_free_cq(dev->umrc.cq);
e126ba97
EC		 3306 ib_dealloc_pd(dev->umrc.pd);
3307}
3308
3309enum {
3310 MAX_UMR_WR = 128,
3311};
3312
3313static int create_umr_res(struct mlx5_ib_dev *dev)
3314{
3315 struct ib_qp_init_attr *init_attr = NULL;
3316 struct ib_qp_attr *attr = NULL;
3317 struct ib_pd *pd;
3318 struct ib_cq *cq;
3319 struct ib_qp *qp;
e126ba97
EC		 3320 int ret;
3321
3322 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3323 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3324 if (!attr || !init_attr) {
3325 ret = -ENOMEM;
3326 goto error_0;
3327 }
3328
ed082d36 3329 pd = ib_alloc_pd(&dev->ib_dev, 0);
e126ba97
EC		 3330 if (IS_ERR(pd)) {
3331 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3332 ret = PTR_ERR(pd);
3333 goto error_0;
3334 }
3335
add08d76 3336 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
e126ba97
EC		 3337 if (IS_ERR(cq)) {
3338 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3339 ret = PTR_ERR(cq);
3340 goto error_2;
3341 }
e126ba97
EC		 3342
3343 init_attr->send_cq = cq;
3344 init_attr->recv_cq = cq;
3345 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3346 init_attr->cap.max_send_wr = MAX_UMR_WR;
3347 init_attr->cap.max_send_sge = 1;
3348 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3349 init_attr->port_num = 1;
3350 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3351 if (IS_ERR(qp)) {
3352 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3353 ret = PTR_ERR(qp);
3354 goto error_3;
3355 }
3356 qp->device = &dev->ib_dev;
3357 qp->real_qp = qp;
3358 qp->uobject = NULL;
3359 qp->qp_type = MLX5_IB_QPT_REG_UMR;
31fde034
MD		 3360 qp->send_cq = init_attr->send_cq;
3361 qp->recv_cq = init_attr->recv_cq;
e126ba97
EC		 3362
3363 attr->qp_state = IB_QPS_INIT;
3364 attr->port_num = 1;
3365 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3366 IB_QP_PORT, NULL);
3367 if (ret) {
3368 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3369 goto error_4;
3370 }
3371
3372 memset(attr, 0, sizeof(*attr));
3373 attr->qp_state = IB_QPS_RTR;
3374 attr->path_mtu = IB_MTU_256;
3375
3376 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3377 if (ret) {
3378 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3379 goto error_4;
3380 }
3381
3382 memset(attr, 0, sizeof(*attr));
3383 attr->qp_state = IB_QPS_RTS;
3384 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3385 if (ret) {
3386 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3387 goto error_4;
3388 }
3389
3390 dev->umrc.qp = qp;
3391 dev->umrc.cq = cq;
e126ba97
EC		 3392 dev->umrc.pd = pd;
3393
3394 sema_init(&dev->umrc.sem, MAX_UMR_WR);
3395 ret = mlx5_mr_cache_init(dev);
3396 if (ret) {
3397 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3398 goto error_4;
3399 }
3400
3401 kfree(attr);
3402 kfree(init_attr);
3403
3404 return 0;
3405
3406error_4:
3407 mlx5_ib_destroy_qp(qp);
3408
3409error_3:
add08d76 3410 ib_free_cq(cq);
e126ba97
EC		 3411
3412error_2:
e126ba97
EC		 3413 ib_dealloc_pd(pd);
3414
3415error_0:
3416 kfree(attr);
3417 kfree(init_attr);
3418 return ret;
3419}
3420
6e8484c5
MG		 3421static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3422{
3423 switch (umr_fence_cap) {
3424 case MLX5_CAP_UMR_FENCE_NONE:
3425 return MLX5_FENCE_MODE_NONE;
3426 case MLX5_CAP_UMR_FENCE_SMALL:
3427 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3428 default:
3429 return MLX5_FENCE_MODE_STRONG_ORDERING;
3430 }
3431}
3432
e126ba97
EC		 3433static int create_dev_resources(struct mlx5_ib_resources *devr)
3434{
3435 struct ib_srq_init_attr attr;
3436 struct mlx5_ib_dev *dev;
bcf4c1ea 3437 struct ib_cq_init_attr cq_attr = {.cqe = 1};
7722f47e 3438 int port;
e126ba97
EC		 3439 int ret = 0;
3440
3441 dev = container_of(devr, struct mlx5_ib_dev, devr);
3442
d16e91da
HE		 3443 mutex_init(&devr->mutex);
3444
e126ba97
EC		 3445 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3446 if (IS_ERR(devr->p0)) {
3447 ret = PTR_ERR(devr->p0);
3448 goto error0;
3449 }
3450 devr->p0->device = &dev->ib_dev;
3451 devr->p0->uobject = NULL;
3452 atomic_set(&devr->p0->usecnt, 0);
3453
bcf4c1ea 3454 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
e126ba97
EC		 3455 if (IS_ERR(devr->c0)) {
3456 ret = PTR_ERR(devr->c0);
3457 goto error1;
3458 }
3459 devr->c0->device = &dev->ib_dev;
3460 devr->c0->uobject = NULL;
3461 devr->c0->comp_handler = NULL;
3462 devr->c0->event_handler = NULL;
3463 devr->c0->cq_context = NULL;
3464 atomic_set(&devr->c0->usecnt, 0);
3465
3466 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3467 if (IS_ERR(devr->x0)) {
3468 ret = PTR_ERR(devr->x0);
3469 goto error2;
3470 }
3471 devr->x0->device = &dev->ib_dev;
3472 devr->x0->inode = NULL;
3473 atomic_set(&devr->x0->usecnt, 0);
3474 mutex_init(&devr->x0->tgt_qp_mutex);
3475 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3476
3477 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3478 if (IS_ERR(devr->x1)) {
3479 ret = PTR_ERR(devr->x1);
3480 goto error3;
3481 }
3482 devr->x1->device = &dev->ib_dev;
3483 devr->x1->inode = NULL;
3484 atomic_set(&devr->x1->usecnt, 0);
3485 mutex_init(&devr->x1->tgt_qp_mutex);
3486 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3487
3488 memset(&attr, 0, sizeof(attr));
3489 attr.attr.max_sge = 1;
3490 attr.attr.max_wr = 1;
3491 attr.srq_type = IB_SRQT_XRC;
1a56ff6d 3492 attr.ext.cq = devr->c0;
e126ba97
EC		 3493 attr.ext.xrc.xrcd = devr->x0;
3494
3495 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3496 if (IS_ERR(devr->s0)) {
3497 ret = PTR_ERR(devr->s0);
3498 goto error4;
3499 }
3500 devr->s0->device = &dev->ib_dev;
3501 devr->s0->pd = devr->p0;
3502 devr->s0->uobject = NULL;
3503 devr->s0->event_handler = NULL;
3504 devr->s0->srq_context = NULL;
3505 devr->s0->srq_type = IB_SRQT_XRC;
3506 devr->s0->ext.xrc.xrcd = devr->x0;
1a56ff6d 3507 devr->s0->ext.cq = devr->c0;
e126ba97 3508 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1a56ff6d 3509 atomic_inc(&devr->s0->ext.cq->usecnt);
e126ba97
EC		 3510 atomic_inc(&devr->p0->usecnt);
3511 atomic_set(&devr->s0->usecnt, 0);
3512
4aa17b28
HA		 3513 memset(&attr, 0, sizeof(attr));
3514 attr.attr.max_sge = 1;
3515 attr.attr.max_wr = 1;
3516 attr.srq_type = IB_SRQT_BASIC;
3517 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3518 if (IS_ERR(devr->s1)) {
3519 ret = PTR_ERR(devr->s1);
3520 goto error5;
3521 }
3522 devr->s1->device = &dev->ib_dev;
3523 devr->s1->pd = devr->p0;
3524 devr->s1->uobject = NULL;
3525 devr->s1->event_handler = NULL;
3526 devr->s1->srq_context = NULL;
3527 devr->s1->srq_type = IB_SRQT_BASIC;
1a56ff6d 3528 devr->s1->ext.cq = devr->c0;
4aa17b28 3529 atomic_inc(&devr->p0->usecnt);
1a56ff6d 3530 atomic_set(&devr->s1->usecnt, 0);
4aa17b28 3531
7722f47e
HE		 3532 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3533 INIT_WORK(&devr->ports[port].pkey_change_work,
3534 pkey_change_handler);
3535 devr->ports[port].devr = devr;
3536 }
3537
e126ba97
EC		 3538 return 0;
3539
4aa17b28
HA		 3540error5:
3541 mlx5_ib_destroy_srq(devr->s0);
e126ba97
EC		 3542error4:
3543 mlx5_ib_dealloc_xrcd(devr->x1);
3544error3:
3545 mlx5_ib_dealloc_xrcd(devr->x0);
3546error2:
3547 mlx5_ib_destroy_cq(devr->c0);
3548error1:
3549 mlx5_ib_dealloc_pd(devr->p0);
3550error0:
3551 return ret;
3552}
3553
3554static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3555{
7722f47e
HE		 3556 struct mlx5_ib_dev *dev =
3557 container_of(devr, struct mlx5_ib_dev, devr);
3558 int port;
3559
4aa17b28 3560 mlx5_ib_destroy_srq(devr->s1);
e126ba97
EC		 3561 mlx5_ib_destroy_srq(devr->s0);
3562 mlx5_ib_dealloc_xrcd(devr->x0);
3563 mlx5_ib_dealloc_xrcd(devr->x1);
3564 mlx5_ib_destroy_cq(devr->c0);
3565 mlx5_ib_dealloc_pd(devr->p0);
7722f47e
HE		 3566
3567 /* Make sure no change P_Key work items are still executing */
3568 for (port = 0; port < dev->num_ports; ++port)
3569 cancel_work_sync(&devr->ports[port].pkey_change_work);
e126ba97
EC		 3570}
3571
e53505a8
AS		 3572static u32 get_core_cap_flags(struct ib_device *ibdev)
3573{
3574 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3575 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3576 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3577 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3578 u32 ret = 0;
3579
3580 if (ll == IB_LINK_LAYER_INFINIBAND)
3581 return RDMA_CORE_PORT_IBA_IB;
3582
72cd5717
OG		 3583 ret = RDMA_CORE_PORT_RAW_PACKET;
3584
e53505a8 3585 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
72cd5717 3586 return ret;
e53505a8
AS		 3587
3588 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
72cd5717 3589 return ret;
e53505a8
AS		 3590
3591 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3592 ret |= RDMA_CORE_PORT_IBA_ROCE;
3593
3594 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3595 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3596
3597 return ret;
3598}
3599
7738613e
IW		 3600static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3601 struct ib_port_immutable *immutable)
3602{
3603 struct ib_port_attr attr;
ca5b91d6
OG		 3604 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3605 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
7738613e
IW		 3606 int err;
3607
c4550c63
OG		 3608 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3609
3610 err = ib_query_port(ibdev, port_num, &attr);
7738613e
IW		 3611 if (err)
3612 return err;
3613
3614 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3615 immutable->gid_tbl_len = attr.gid_tbl_len;
e53505a8 3616 immutable->core_cap_flags = get_core_cap_flags(ibdev);
ca5b91d6
OG		 3617 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3618 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
7738613e
IW		 3619
3620 return 0;
3621}
3622
9abb0d1b 3623static void get_dev_fw_str(struct ib_device *ibdev, char *str)
c7342823
IW		 3624{
3625 struct mlx5_ib_dev *dev =
3626 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
9abb0d1b
LR		 3627 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3628 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3629 fw_rev_sub(dev->mdev));
c7342823
IW		 3630}
3631
45f95acd 3632static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3633{
3634 struct mlx5_core_dev *mdev = dev->mdev;
3635 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3636 MLX5_FLOW_NAMESPACE_LAG);
3637 struct mlx5_flow_table *ft;
3638 int err;
3639
3640 if (!ns || !mlx5_lag_is_active(mdev))
3641 return 0;
3642
3643 err = mlx5_cmd_create_vport_lag(mdev);
3644 if (err)
3645 return err;
3646
3647 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3648 if (IS_ERR(ft)) {
3649 err = PTR_ERR(ft);
3650 goto err_destroy_vport_lag;
3651 }
3652
3653 dev->flow_db.lag_demux_ft = ft;
3654 return 0;
3655
3656err_destroy_vport_lag:
3657 mlx5_cmd_destroy_vport_lag(mdev);
3658 return err;
3659}
3660
45f95acd 3661static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
9ef9c640
AH		 3662{
3663 struct mlx5_core_dev *mdev = dev->mdev;
3664
3665 if (dev->flow_db.lag_demux_ft) {
3666 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3667 dev->flow_db.lag_demux_ft = NULL;
3668
3669 mlx5_cmd_destroy_vport_lag(mdev);
3670 }
3671}
3672
7fd8aefb 3673static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
d012f5d6
OG		 3674{
3675 int err;
3676
7fd8aefb
DJ		 3677 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
3678 err = register_netdevice_notifier(&dev->roce[port_num].nb);
d012f5d6 3679 if (err) {
7fd8aefb 3680 dev->roce[port_num].nb.notifier_call = NULL;
d012f5d6
OG		 3681 return err;
3682 }
3683
3684 return 0;
3685}
3686
7fd8aefb 3687static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5ec8c83e 3688{
7fd8aefb
DJ		 3689 if (dev->roce[port_num].nb.notifier_call) {
3690 unregister_netdevice_notifier(&dev->roce[port_num].nb);
3691 dev->roce[port_num].nb.notifier_call = NULL;
5ec8c83e
AH		 3692 }
3693}
3694
7fd8aefb 3695static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
fc24fc5e 3696{
e53505a8
AS		 3697 int err;
3698
7fd8aefb 3699 err = mlx5_add_netdev_notifier(dev, port_num);
d012f5d6 3700 if (err)
e53505a8
AS		 3701 return err;
3702
ca5b91d6
OG		 3703 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3704 err = mlx5_nic_vport_enable_roce(dev->mdev);
3705 if (err)
3706 goto err_unregister_netdevice_notifier;
3707 }
e53505a8 3708
45f95acd 3709 err = mlx5_eth_lag_init(dev);
9ef9c640
AH		 3710 if (err)
3711 goto err_disable_roce;
3712
e53505a8
AS		 3713 return 0;
3714
9ef9c640 3715err_disable_roce:
ca5b91d6
OG		 3716 if (MLX5_CAP_GEN(dev->mdev, roce))
3717 mlx5_nic_vport_disable_roce(dev->mdev);
9ef9c640 3718
e53505a8 3719err_unregister_netdevice_notifier:
7fd8aefb 3720 mlx5_remove_netdev_notifier(dev, port_num);
e53505a8 3721 return err;
fc24fc5e
AS		 3722}
3723
45f95acd 3724static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
fc24fc5e 3725{
45f95acd 3726 mlx5_eth_lag_cleanup(dev);
ca5b91d6
OG		 3727 if (MLX5_CAP_GEN(dev->mdev, roce))
3728 mlx5_nic_vport_disable_roce(dev->mdev);
fc24fc5e
AS		 3729}
3730
e1f24a79 3731struct mlx5_ib_counter {
7c16f477
KH		 3732 const char *name;
3733 size_t offset;
3734};
3735
3736#define INIT_Q_COUNTER(_name) \
3737 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3738
e1f24a79 3739static const struct mlx5_ib_counter basic_q_cnts[] = {
7c16f477
KH		 3740 INIT_Q_COUNTER(rx_write_requests),
3741 INIT_Q_COUNTER(rx_read_requests),
3742 INIT_Q_COUNTER(rx_atomic_requests),
3743 INIT_Q_COUNTER(out_of_buffer),
3744};
3745
e1f24a79 3746static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
7c16f477
KH		 3747 INIT_Q_COUNTER(out_of_sequence),
3748};
3749
e1f24a79 3750static const struct mlx5_ib_counter retrans_q_cnts[] = {
7c16f477
KH		 3751 INIT_Q_COUNTER(duplicate_request),
3752 INIT_Q_COUNTER(rnr_nak_retry_err),
3753 INIT_Q_COUNTER(packet_seq_err),
3754 INIT_Q_COUNTER(implied_nak_seq_err),
3755 INIT_Q_COUNTER(local_ack_timeout_err),
3756};
3757
e1f24a79
PP		 3758#define INIT_CONG_COUNTER(_name) \
3759 { .name = #_name, .offset = \
3760 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3761
3762static const struct mlx5_ib_counter cong_cnts[] = {
3763 INIT_CONG_COUNTER(rp_cnp_ignored),
3764 INIT_CONG_COUNTER(rp_cnp_handled),
3765 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3766 INIT_CONG_COUNTER(np_cnp_sent),
3767};
3768
58dcb60a
PP		 3769static const struct mlx5_ib_counter extended_err_cnts[] = {
3770 INIT_Q_COUNTER(resp_local_length_error),
3771 INIT_Q_COUNTER(resp_cqe_error),
3772 INIT_Q_COUNTER(req_cqe_error),
3773 INIT_Q_COUNTER(req_remote_invalid_request),
3774 INIT_Q_COUNTER(req_remote_access_errors),
3775 INIT_Q_COUNTER(resp_remote_access_errors),
3776 INIT_Q_COUNTER(resp_cqe_flush_error),
3777 INIT_Q_COUNTER(req_cqe_flush_error),
3778};
3779
e1f24a79 3780static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3781{
3782 unsigned int i;
3783
7c16f477 3784 for (i = 0; i < dev->num_ports; i++) {
0837e86a 3785 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79
PP		 3786 dev->port[i].cnts.set_id);
3787 kfree(dev->port[i].cnts.names);
3788 kfree(dev->port[i].cnts.offsets);
7c16f477
KH		 3789 }
3790}
3791
e1f24a79
PP		 3792static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3793 struct mlx5_ib_counters *cnts)
7c16f477
KH		 3794{
3795 u32 num_counters;
3796
3797 num_counters = ARRAY_SIZE(basic_q_cnts);
3798
3799 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3800 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3801
3802 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3803 num_counters += ARRAY_SIZE(retrans_q_cnts);
58dcb60a
PP		 3804
3805 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3806 num_counters += ARRAY_SIZE(extended_err_cnts);
3807
e1f24a79 3808 cnts->num_q_counters = num_counters;
7c16f477 3809
e1f24a79
PP		 3810 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3811 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3812 num_counters += ARRAY_SIZE(cong_cnts);
3813 }
3814
3815 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3816 if (!cnts->names)
7c16f477
KH		 3817 return -ENOMEM;
3818
e1f24a79
PP		 3819 cnts->offsets = kcalloc(num_counters,
3820 sizeof(cnts->offsets), GFP_KERNEL);
3821 if (!cnts->offsets)
7c16f477
KH		 3822 goto err_names;
3823
7c16f477
KH		 3824 return 0;
3825
3826err_names:
e1f24a79 3827 kfree(cnts->names);
7c16f477
KH		 3828 return -ENOMEM;
3829}
3830
e1f24a79
PP		 3831static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3832 const char **names,
3833 size_t *offsets)
7c16f477
KH		 3834{
3835 int i;
3836 int j = 0;
3837
3838 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3839 names[j] = basic_q_cnts[i].name;
3840 offsets[j] = basic_q_cnts[i].offset;
3841 }
3842
3843 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3844 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3845 names[j] = out_of_seq_q_cnts[i].name;
3846 offsets[j] = out_of_seq_q_cnts[i].offset;
3847 }
3848 }
3849
3850 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3851 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3852 names[j] = retrans_q_cnts[i].name;
3853 offsets[j] = retrans_q_cnts[i].offset;
3854 }
3855 }
e1f24a79 3856
58dcb60a
PP		 3857 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
3858 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
3859 names[j] = extended_err_cnts[i].name;
3860 offsets[j] = extended_err_cnts[i].offset;
3861 }
3862 }
3863
e1f24a79
PP		 3864 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3865 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3866 names[j] = cong_cnts[i].name;
3867 offsets[j] = cong_cnts[i].offset;
3868 }
3869 }
0837e86a
MB		 3870}
3871
e1f24a79 3872static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
0837e86a
MB		 3873{
3874 int i;
3875 int ret;
3876
3877 for (i = 0; i < dev->num_ports; i++) {
7c16f477
KH		 3878 struct mlx5_ib_port *port = &dev->port[i];
3879
0837e86a 3880 ret = mlx5_core_alloc_q_counter(dev->mdev,
e1f24a79 3881 &port->cnts.set_id);
0837e86a
MB		 3882 if (ret) {
3883 mlx5_ib_warn(dev,
3884 "couldn't allocate queue counter for port %d, err %d\n",
3885 i + 1, ret);
3886 goto dealloc_counters;
3887 }
7c16f477 3888
e1f24a79 3889 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
7c16f477
KH		 3890 if (ret)
3891 goto dealloc_counters;
3892
e1f24a79
PP		 3893 mlx5_ib_fill_counters(dev, port->cnts.names,
3894 port->cnts.offsets);
0837e86a
MB		 3895 }
3896
3897 return 0;
3898
3899dealloc_counters:
3900 while (--i >= 0)
3901 mlx5_core_dealloc_q_counter(dev->mdev,
e1f24a79 3902 dev->port[i].cnts.set_id);
0837e86a
MB		 3903
3904 return ret;
3905}
3906
0ad17a8f
MB		 3907static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3908 u8 port_num)
3909{
7c16f477
KH		 3910 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3911 struct mlx5_ib_port *port = &dev->port[port_num - 1];
0ad17a8f
MB		 3912
3913 /* We support only per port stats */
3914 if (port_num == 0)
3915 return NULL;
3916
e1f24a79
PP		 3917 return rdma_alloc_hw_stats_struct(port->cnts.names,
3918 port->cnts.num_q_counters +
3919 port->cnts.num_cong_counters,
0ad17a8f
MB		 3920 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3921}
3922
e1f24a79
PP		 3923static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3924 struct mlx5_ib_port *port,
3925 struct rdma_hw_stats *stats)
0ad17a8f 3926{
0ad17a8f
MB		 3927 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3928 void *out;
3929 __be32 val;
e1f24a79 3930 int ret, i;
0ad17a8f 3931
1b9a07ee 3932 out = kvzalloc(outlen, GFP_KERNEL);
0ad17a8f
MB		 3933 if (!out)
3934 return -ENOMEM;
3935
3936 ret = mlx5_core_query_q_counter(dev->mdev,
e1f24a79 3937 port->cnts.set_id, 0,
0ad17a8f
MB		 3938 out, outlen);
3939 if (ret)
3940 goto free;
3941
e1f24a79
PP		 3942 for (i = 0; i < port->cnts.num_q_counters; i++) {
3943 val = *(__be32 *)(out + port->cnts.offsets[i]);
0ad17a8f
MB		 3944 stats->value[i] = (u64)be32_to_cpu(val);
3945 }
7c16f477 3946
0ad17a8f
MB		 3947free:
3948 kvfree(out);
e1f24a79
PP		 3949 return ret;
3950}
3951
e1f24a79
PP		 3952static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3953 struct rdma_hw_stats *stats,
3954 u8 port_num, int index)
3955{
3956 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3957 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3958 int ret, num_counters;
3959
3960 if (!stats)
3961 return -EINVAL;
3962
3963 ret = mlx5_ib_query_q_counters(dev, port, stats);
3964 if (ret)
3965 return ret;
3966 num_counters = port->cnts.num_q_counters;
3967
3968 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
71a0ff65
MD		 3969 ret = mlx5_lag_query_cong_counters(dev->mdev,
3970 stats->value +
3971 port->cnts.num_q_counters,
3972 port->cnts.num_cong_counters,
3973 port->cnts.offsets +
3974 port->cnts.num_q_counters);
e1f24a79
PP		 3975 if (ret)
3976 return ret;
3977 num_counters += port->cnts.num_cong_counters;
3978 }
3979
3980 return num_counters;
0ad17a8f
MB		 3981}
3982
8e959601
NV		 3983static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3984{
3985 return mlx5_rdma_netdev_free(netdev);
3986}
3987
693dfd5a
ES		 3988static struct net_device*
3989mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3990 u8 port_num,
3991 enum rdma_netdev_t type,
3992 const char *name,
3993 unsigned char name_assign_type,
3994 void (*setup)(struct net_device *))
3995{
8e959601
NV		 3996 struct net_device *netdev;
3997 struct rdma_netdev *rn;
3998
693dfd5a
ES		 3999 if (type != RDMA_NETDEV_IPOIB)
4000 return ERR_PTR(-EOPNOTSUPP);
4001
8e959601
NV		 4002 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4003 name, setup);
4004 if (likely(!IS_ERR_OR_NULL(netdev))) {
4005 rn = netdev_priv(netdev);
4006 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4007 }
4008 return netdev;
693dfd5a
ES		 4009}
4010
fe248c3a
MG		 4011static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4012{
4013 if (!dev->delay_drop.dbg)
4014 return;
4015 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4016 kfree(dev->delay_drop.dbg);
4017 dev->delay_drop.dbg = NULL;
4018}
4019
03404e8a
MG		 4020static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4021{
4022 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4023 return;
4024
4025 cancel_work_sync(&dev->delay_drop.delay_drop_work);
fe248c3a
MG		 4026 delay_drop_debugfs_cleanup(dev);
4027}
4028
4029static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4030 size_t count, loff_t *pos)
4031{
4032 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4033 char lbuf[20];
4034 int len;
4035
4036 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4037 return simple_read_from_buffer(buf, count, pos, lbuf, len);
4038}
4039
4040static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4041 size_t count, loff_t *pos)
4042{
4043 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4044 u32 timeout;
4045 u32 var;
4046
4047 if (kstrtouint_from_user(buf, count, 0, &var))
4048 return -EFAULT;
4049
4050 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4051 1000);
4052 if (timeout != var)
4053 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4054 timeout);
4055
4056 delay_drop->timeout = timeout;
4057
4058 return count;
4059}
4060
4061static const struct file_operations fops_delay_drop_timeout = {
4062 .owner = THIS_MODULE,
4063 .open = simple_open,
4064 .write = delay_drop_timeout_write,
4065 .read = delay_drop_timeout_read,
4066};
4067
4068static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4069{
4070 struct mlx5_ib_dbg_delay_drop *dbg;
4071
4072 if (!mlx5_debugfs_root)
4073 return 0;
4074
4075 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4076 if (!dbg)
4077 return -ENOMEM;
4078
cbafad87
SM		 4079 dev->delay_drop.dbg = dbg;
4080
fe248c3a
MG		 4081 dbg->dir_debugfs =
4082 debugfs_create_dir("delay_drop",
4083 dev->mdev->priv.dbg_root);
4084 if (!dbg->dir_debugfs)
cbafad87 4085 goto out_debugfs;
fe248c3a
MG		 4086
4087 dbg->events_cnt_debugfs =
4088 debugfs_create_atomic_t("num_timeout_events", 0400,
4089 dbg->dir_debugfs,
4090 &dev->delay_drop.events_cnt);
4091 if (!dbg->events_cnt_debugfs)
4092 goto out_debugfs;
4093
4094 dbg->rqs_cnt_debugfs =
4095 debugfs_create_atomic_t("num_rqs", 0400,
4096 dbg->dir_debugfs,
4097 &dev->delay_drop.rqs_cnt);
4098 if (!dbg->rqs_cnt_debugfs)
4099 goto out_debugfs;
4100
4101 dbg->timeout_debugfs =
4102 debugfs_create_file("timeout", 0600,
4103 dbg->dir_debugfs,
4104 &dev->delay_drop,
4105 &fops_delay_drop_timeout);
4106 if (!dbg->timeout_debugfs)
4107 goto out_debugfs;
4108
4109 return 0;
4110
4111out_debugfs:
4112 delay_drop_debugfs_cleanup(dev);
4113 return -ENOMEM;
03404e8a
MG		 4114}
4115
4116static void init_delay_drop(struct mlx5_ib_dev *dev)
4117{
4118 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4119 return;
4120
4121 mutex_init(&dev->delay_drop.lock);
4122 dev->delay_drop.dev = dev;
4123 dev->delay_drop.activate = false;
4124 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4125 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
fe248c3a
MG		 4126 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4127 atomic_set(&dev->delay_drop.events_cnt, 0);
4128
4129 if (delay_drop_debugfs_init(dev))
4130 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
03404e8a
MG		 4131}
4132
84305d71
LR		 4133static const struct cpumask *
4134mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
40b24403
SG		 4135{
4136 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4137
4138 return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4139}
4140
32f69e4b
DJ		 4141/* The mlx5_ib_multiport_mutex should be held when calling this function */
4142static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4143 struct mlx5_ib_multiport_info *mpi)
4144{
4145 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4146 struct mlx5_ib_port *port = &ibdev->port[port_num];
4147 int comps;
4148 int err;
4149 int i;
4150
4151 spin_lock(&port->mp.mpi_lock);
4152 if (!mpi->ibdev) {
4153 spin_unlock(&port->mp.mpi_lock);
4154 return;
4155 }
4156 mpi->ibdev = NULL;
4157
4158 spin_unlock(&port->mp.mpi_lock);
4159 mlx5_remove_netdev_notifier(ibdev, port_num);
4160 spin_lock(&port->mp.mpi_lock);
4161
4162 comps = mpi->mdev_refcnt;
4163 if (comps) {
4164 mpi->unaffiliate = true;
4165 init_completion(&mpi->unref_comp);
4166 spin_unlock(&port->mp.mpi_lock);
4167
4168 for (i = 0; i < comps; i++)
4169 wait_for_completion(&mpi->unref_comp);
4170
4171 spin_lock(&port->mp.mpi_lock);
4172 mpi->unaffiliate = false;
4173 }
4174
4175 port->mp.mpi = NULL;
4176
4177 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4178
4179 spin_unlock(&port->mp.mpi_lock);
4180
4181 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4182
4183 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4184 /* Log an error, still needed to cleanup the pointers and add
4185 * it back to the list.
4186 */
4187 if (err)
4188 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4189 port_num + 1);
4190
4191 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4192}
4193
4194/* The mlx5_ib_multiport_mutex should be held when calling this function */
4195static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4196 struct mlx5_ib_multiport_info *mpi)
4197{
4198 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4199 int err;
4200
4201 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4202 if (ibdev->port[port_num].mp.mpi) {
4203 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4204 port_num + 1);
4205 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4206 return false;
4207 }
4208
4209 ibdev->port[port_num].mp.mpi = mpi;
4210 mpi->ibdev = ibdev;
4211 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4212
4213 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4214 if (err)
4215 goto unbind;
4216
4217 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4218 if (err)
4219 goto unbind;
4220
4221 err = mlx5_add_netdev_notifier(ibdev, port_num);
4222 if (err) {
4223 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4224 port_num + 1);
4225 goto unbind;
4226 }
4227
4228 return true;
4229
4230unbind:
4231 mlx5_ib_unbind_slave_port(ibdev, mpi);
4232 return false;
4233}
4234
4235static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4236{
4237 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4238 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4239 port_num + 1);
4240 struct mlx5_ib_multiport_info *mpi;
4241 int err;
4242 int i;
4243
4244 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4245 return 0;
4246
4247 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4248 &dev->sys_image_guid);
4249 if (err)
4250 return err;
4251
4252 err = mlx5_nic_vport_enable_roce(dev->mdev);
4253 if (err)
4254 return err;
4255
4256 mutex_lock(&mlx5_ib_multiport_mutex);
4257 for (i = 0; i < dev->num_ports; i++) {
4258 bool bound = false;
4259
4260 /* build a stub multiport info struct for the native port. */
4261 if (i == port_num) {
4262 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4263 if (!mpi) {
4264 mutex_unlock(&mlx5_ib_multiport_mutex);
4265 mlx5_nic_vport_disable_roce(dev->mdev);
4266 return -ENOMEM;
4267 }
4268
4269 mpi->is_master = true;
4270 mpi->mdev = dev->mdev;
4271 mpi->sys_image_guid = dev->sys_image_guid;
4272 dev->port[i].mp.mpi = mpi;
4273 mpi->ibdev = dev;
4274 mpi = NULL;
4275 continue;
4276 }
4277
4278 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4279 list) {
4280 if (dev->sys_image_guid == mpi->sys_image_guid &&
4281 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4282 bound = mlx5_ib_bind_slave_port(dev, mpi);
4283 }
4284
4285 if (bound) {
4286 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4287 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4288 list_del(&mpi->list);
4289 break;
4290 }
4291 }
4292 if (!bound) {
4293 get_port_caps(dev, i + 1);
4294 mlx5_ib_dbg(dev, "no free port found for port %d\n",
4295 i + 1);
4296 }
4297 }
4298
4299 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4300 mutex_unlock(&mlx5_ib_multiport_mutex);
4301 return err;
4302}
4303
4304static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4305{
4306 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4307 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4308 port_num + 1);
4309 int i;
4310
4311 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4312 return;
4313
4314 mutex_lock(&mlx5_ib_multiport_mutex);
4315 for (i = 0; i < dev->num_ports; i++) {
4316 if (dev->port[i].mp.mpi) {
4317 /* Destroy the native port stub */
4318 if (i == port_num) {
4319 kfree(dev->port[i].mp.mpi);
4320 dev->port[i].mp.mpi = NULL;
4321 } else {
4322 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4323 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4324 }
4325 }
4326 }
4327
4328 mlx5_ib_dbg(dev, "removing from devlist\n");
4329 list_del(&dev->ib_dev_list);
4330 mutex_unlock(&mlx5_ib_multiport_mutex);
4331
4332 mlx5_nic_vport_disable_roce(dev->mdev);
4333}
4334
16c1975f 4335static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
e126ba97 4336{
32f69e4b 4337 mlx5_ib_cleanup_multiport_master(dev);
3cc297db
MB		 4338#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4339 cleanup_srcu_struct(&dev->mr_srcu);
4340#endif
16c1975f
MB		 4341 kfree(dev->port);
4342}
4343
4344static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4345{
4346 struct mlx5_core_dev *mdev = dev->mdev;
4babcf97 4347 const char *name;
e126ba97 4348 int err;
32f69e4b 4349 int i;
e126ba97 4350
508562d6 4351 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
0837e86a
MB		 4352 GFP_KERNEL);
4353 if (!dev->port)
16c1975f 4354 return -ENOMEM;
0837e86a 4355
32f69e4b
DJ		 4356 for (i = 0; i < dev->num_ports; i++) {
4357 spin_lock_init(&dev->port[i].mp.mpi_lock);
4358 rwlock_init(&dev->roce[i].netdev_lock);
4359 }
4360
4361 err = mlx5_ib_init_multiport_master(dev);
e126ba97 4362 if (err)
0837e86a 4363 goto err_free_port;
e126ba97 4364
32f69e4b
DJ		 4365 if (!mlx5_core_mp_enabled(mdev)) {
4366 int i;
4367
4368 for (i = 1; i <= dev->num_ports; i++) {
4369 err = get_port_caps(dev, i);
4370 if (err)
4371 break;
4372 }
4373 } else {
4374 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4375 }
4376 if (err)
4377 goto err_mp;
4378
1b5daf11
MD		 4379 if (mlx5_use_mad_ifc(dev))
4380 get_ext_port_caps(dev);
e126ba97 4381
4babcf97
AH		 4382 if (!mlx5_lag_is_active(mdev))
4383 name = "mlx5_%d";
4384 else
4385 name = "mlx5_bond_%d";
4386
4387 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
e126ba97
EC		 4388 dev->ib_dev.owner = THIS_MODULE;
4389 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
c6790aa9 4390 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
508562d6 4391 dev->ib_dev.phys_port_cnt = dev->num_ports;
233d05d2
SM		 4392 dev->ib_dev.num_comp_vectors =
4393 dev->mdev->priv.eq_table.num_comp_vectors;
9b0c289e 4394 dev->ib_dev.dev.parent = &mdev->pdev->dev;
e126ba97 4395
3cc297db
MB		 4396 mutex_init(&dev->flow_db.lock);
4397 mutex_init(&dev->cap_mask_mutex);
4398 INIT_LIST_HEAD(&dev->qp_list);
4399 spin_lock_init(&dev->reset_flow_resource_lock);
4400
4401#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4402 err = init_srcu_struct(&dev->mr_srcu);
4403 if (err)
4404 goto err_free_port;
4405#endif
4406
16c1975f 4407 return 0;
32f69e4b
DJ		 4408err_mp:
4409 mlx5_ib_cleanup_multiport_master(dev);
16c1975f
MB		 4410
4411err_free_port:
4412 kfree(dev->port);
4413
4414 return -ENOMEM;
4415}
4416
4417static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4418{
4419 struct mlx5_core_dev *mdev = dev->mdev;
16c1975f
MB		 4420 int err;
4421
e126ba97
EC		 4422 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
4423 dev->ib_dev.uverbs_cmd_mask =
4424 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
4425 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
4426 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
4427 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
4428 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
41c450fd
MS		 4429 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
4430 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
e126ba97 4431 (1ull << IB_USER_VERBS_CMD_REG_MR) |
56e11d62 4432 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
e126ba97
EC		 4433 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
4434 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4435 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
4436 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
4437 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
4438 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
4439 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
4440 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
4441 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
4442 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
4443 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
4444 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
4445 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
4446 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
4447 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
4448 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
4449 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1707cb4a 4450 dev->ib_dev.uverbs_ex_cmd_mask =
d4584ddf
MB		 4451 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
4452 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
7d29f349 4453 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
b0e9df6d
YC		 4454 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
4455 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
e126ba97
EC		 4456
4457 dev->ib_dev.query_device = mlx5_ib_query_device;
4458 dev->ib_dev.query_port = mlx5_ib_query_port;
ebd61f68 4459 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
e126ba97 4460 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3cca2606
AS		 4461 dev->ib_dev.add_gid = mlx5_ib_add_gid;
4462 dev->ib_dev.del_gid = mlx5_ib_del_gid;
e126ba97
EC		 4463 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
4464 dev->ib_dev.modify_device = mlx5_ib_modify_device;
4465 dev->ib_dev.modify_port = mlx5_ib_modify_port;
4466 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
4467 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
4468 dev->ib_dev.mmap = mlx5_ib_mmap;
4469 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
4470 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
4471 dev->ib_dev.create_ah = mlx5_ib_create_ah;
4472 dev->ib_dev.query_ah = mlx5_ib_query_ah;
4473 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
4474 dev->ib_dev.create_srq = mlx5_ib_create_srq;
4475 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
4476 dev->ib_dev.query_srq = mlx5_ib_query_srq;
4477 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
4478 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
4479 dev->ib_dev.create_qp = mlx5_ib_create_qp;
4480 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
4481 dev->ib_dev.query_qp = mlx5_ib_query_qp;
4482 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
4483 dev->ib_dev.post_send = mlx5_ib_post_send;
4484 dev->ib_dev.post_recv = mlx5_ib_post_recv;
4485 dev->ib_dev.create_cq = mlx5_ib_create_cq;
4486 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
4487 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
4488 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
4489 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
4490 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
4491 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
4492 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
56e11d62 4493 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
e126ba97
EC		 4494 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
4495 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
4496 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
4497 dev->ib_dev.process_mad = mlx5_ib_process_mad;
9bee178b 4498 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
8a187ee5 4499 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
d5436ba0 4500 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
7738613e 4501 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
c7342823 4502 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
40b24403 4503 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
8e959601 4504 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
022d038a 4505 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
8e959601 4506
eff901d3
EC		 4507 if (mlx5_core_is_pf(mdev)) {
4508 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
4509 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
4510 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
4511 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
4512 }
e126ba97 4513
7c2344c3
MG		 4514 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4515
6e8484c5
MG		 4516 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4517
d2370e0a
MB		 4518 if (MLX5_CAP_GEN(mdev, imaicl)) {
4519 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
4520 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
4521 dev->ib_dev.uverbs_cmd_mask |=
4522 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
4523 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4524 }
4525
938fe83c 4526 if (MLX5_CAP_GEN(mdev, xrc)) {
e126ba97
EC		 4527 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4528 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4529 dev->ib_dev.uverbs_cmd_mask |=
4530 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4531 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4532 }
4533
81e30880
YH		 4534 dev->ib_dev.create_flow = mlx5_ib_create_flow;
4535 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4536 dev->ib_dev.uverbs_ex_cmd_mask |=
4537 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4538 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4539
e126ba97
EC		 4540 err = init_node_data(dev);
4541 if (err)
16c1975f 4542 return err;
e126ba97 4543
c8b89924
MB		 4544 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4545 MLX5_CAP_GEN(dev->mdev, disable_local_lb))
4546 mutex_init(&dev->lb_mutex);
4547
16c1975f
MB		 4548 return 0;
4549}
4550
4551static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4552{
4553 struct mlx5_core_dev *mdev = dev->mdev;
4554 enum rdma_link_layer ll;
4555 int port_type_cap;
32f69e4b 4556 u8 port_num;
16c1975f 4557 int err;
7fd8aefb 4558 int i;
16c1975f 4559
32f69e4b 4560 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 4561 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4562 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4563
fc24fc5e 4564 if (ll == IB_LINK_LAYER_ETHERNET) {
7fd8aefb 4565 for (i = 0; i < dev->num_ports; i++) {
7fd8aefb
DJ		 4566 dev->roce[i].dev = dev;
4567 dev->roce[i].native_port_num = i + 1;
4568 dev->roce[i].last_port_state = IB_PORT_DOWN;
4569 }
4570
c11a226a
MB		 4571 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
4572 dev->ib_dev.create_wq = mlx5_ib_create_wq;
4573 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
4574 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
4575 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4576 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4577 dev->ib_dev.uverbs_ex_cmd_mask |=
4578 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4579 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4580 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4581 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4582 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
7fd8aefb 4583 err = mlx5_enable_eth(dev, port_num);
fc24fc5e 4584 if (err)
16c1975f 4585 return err;
fc24fc5e
AS		 4586 }
4587
16c1975f
MB		 4588 return 0;
4589}
e126ba97 4590
16c1975f
MB		 4591static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4592{
4593 struct mlx5_core_dev *mdev = dev->mdev;
4594 enum rdma_link_layer ll;
4595 int port_type_cap;
32f69e4b 4596 u8 port_num;
e126ba97 4597
32f69e4b 4598 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
16c1975f
MB		 4599 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4600 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4601
4602 if (ll == IB_LINK_LAYER_ETHERNET) {
4603 mlx5_disable_eth(dev);
7fd8aefb 4604 mlx5_remove_netdev_notifier(dev, port_num);
45bded2c 4605 }
16c1975f 4606}
6aec21f6 4607
16c1975f
MB		 4608static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
4609{
4610 return create_dev_resources(&dev->devr);
4611}
4612
4613static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
4614{
4615 destroy_dev_resources(&dev->devr);
4616}
4617
4618static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4619{
07321b3c
MB		 4620 mlx5_ib_internal_fill_odp_caps(dev);
4621
16c1975f
MB		 4622 return mlx5_ib_odp_init_one(dev);
4623}
4a2da0b8 4624
16c1975f
MB		 4625static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
4626{
5e1e7612
MB		 4627 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4628 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
4629 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
4630
4631 return mlx5_ib_alloc_counters(dev);
4632 }
16c1975f
MB		 4633
4634 return 0;
4635}
4636
4637static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
4638{
4639 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4640 mlx5_ib_dealloc_counters(dev);
4641}
4642
4643static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4644{
4645 return mlx5_ib_init_cong_debugfs(dev);
4646}
4647
4648static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4649{
4650 mlx5_ib_cleanup_cong_debugfs(dev);
4651}
4652
4653static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4654{
5fe9dec0
EC		 4655 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4656 if (!dev->mdev->priv.uar)
16c1975f
MB		 4657 return -ENOMEM;
4658 return 0;
4659}
4660
4661static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4662{
4663 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4664}
4665
4666static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4667{
4668 int err;
5fe9dec0
EC		 4669
4670 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4671 if (err)
16c1975f 4672 return err;
5fe9dec0
EC		 4673
4674 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4675 if (err)
16c1975f 4676 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5fe9dec0 4677
16c1975f
MB		 4678 return err;
4679}
0837e86a 4680
16c1975f
MB		 4681static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4682{
4683 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4684 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4685}
e126ba97 4686
16c1975f
MB		 4687static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4688{
4689 return ib_register_device(&dev->ib_dev, NULL);
4690}
4691
4692static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4693{
4694 ib_unregister_device(&dev->ib_dev);
4695}
4696
4697static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev)
4698{
4699 return create_umr_res(dev);
4700}
4701
4702static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev)
4703{
4704 destroy_umrc_res(dev);
4705}
4706
4707static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4708{
03404e8a
MG		 4709 init_delay_drop(dev);
4710
16c1975f
MB		 4711 return 0;
4712}
4713
4714static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4715{
4716 cancel_delay_drop(dev);
4717}
4718
4719static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
4720{
4721 int err;
4722 int i;
4723
e126ba97 4724 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 4725 err = device_create_file(&dev->ib_dev.dev,
4726 mlx5_class_attributes[i]);
4727 if (err)
16c1975f 4728 return err;
e126ba97
EC		 4729 }
4730
16c1975f
MB		 4731 return 0;
4732}
4733
16c1975f
MB		 4734static void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4735 const struct mlx5_ib_profile *profile,
4736 int stage)
4737{
4738 /* Number of stages to cleanup */
4739 while (stage) {
4740 stage--;
4741 if (profile->stage[stage].cleanup)
4742 profile->stage[stage].cleanup(dev);
4743 }
e126ba97 4744
16c1975f
MB		 4745 ib_dealloc_device((struct ib_device *)dev);
4746}
e126ba97 4747
32f69e4b
DJ		 4748static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
4749
16c1975f
MB		 4750static void *__mlx5_ib_add(struct mlx5_core_dev *mdev,
4751 const struct mlx5_ib_profile *profile)
4752{
4753 struct mlx5_ib_dev *dev;
4754 int err;
4755 int i;
e126ba97 4756
16c1975f 4757 printk_once(KERN_INFO "%s", mlx5_version);
5fe9dec0 4758
16c1975f
MB		 4759 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
4760 if (!dev)
4761 return NULL;
5fe9dec0 4762
16c1975f 4763 dev->mdev = mdev;
32f69e4b
DJ		 4764 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4765 MLX5_CAP_GEN(mdev, num_vhca_ports));
5fe9dec0 4766
16c1975f
MB		 4767 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4768 if (profile->stage[i].init) {
4769 err = profile->stage[i].init(dev);
4770 if (err)
4771 goto err_out;
4772 }
4773 }
0837e86a 4774
16c1975f
MB		 4775 dev->profile = profile;
4776 dev->ib_active = true;
6aec21f6 4777
16c1975f 4778 return dev;
e126ba97 4779
16c1975f
MB		 4780err_out:
4781 __mlx5_ib_remove(dev, profile, i);
fc24fc5e 4782
16c1975f
MB		 4783 return NULL;
4784}
0837e86a 4785
16c1975f
MB		 4786static const struct mlx5_ib_profile pf_profile = {
4787 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4788 mlx5_ib_stage_init_init,
4789 mlx5_ib_stage_init_cleanup),
4790 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4791 mlx5_ib_stage_caps_init,
4792 NULL),
4793 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4794 mlx5_ib_stage_roce_init,
4795 mlx5_ib_stage_roce_cleanup),
4796 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4797 mlx5_ib_stage_dev_res_init,
4798 mlx5_ib_stage_dev_res_cleanup),
4799 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4800 mlx5_ib_stage_odp_init,
3cc297db 4801 NULL),
16c1975f
MB		 4802 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4803 mlx5_ib_stage_counters_init,
4804 mlx5_ib_stage_counters_cleanup),
4805 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4806 mlx5_ib_stage_cong_debugfs_init,
4807 mlx5_ib_stage_cong_debugfs_cleanup),
4808 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4809 mlx5_ib_stage_uar_init,
4810 mlx5_ib_stage_uar_cleanup),
4811 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4812 mlx5_ib_stage_bfrag_init,
4813 mlx5_ib_stage_bfrag_cleanup),
4814 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4815 mlx5_ib_stage_ib_reg_init,
4816 mlx5_ib_stage_ib_reg_cleanup),
4817 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
4818 mlx5_ib_stage_umr_res_init,
4819 mlx5_ib_stage_umr_res_cleanup),
4820 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4821 mlx5_ib_stage_delay_drop_init,
4822 mlx5_ib_stage_delay_drop_cleanup),
4823 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
4824 mlx5_ib_stage_class_attr_init,
4825 NULL),
16c1975f 4826};
e126ba97 4827
32f69e4b
DJ		 4828static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
4829{
4830 struct mlx5_ib_multiport_info *mpi;
4831 struct mlx5_ib_dev *dev;
4832 bool bound = false;
4833 int err;
4834
4835 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4836 if (!mpi)
4837 return NULL;
4838
4839 mpi->mdev = mdev;
4840
4841 err = mlx5_query_nic_vport_system_image_guid(mdev,
4842 &mpi->sys_image_guid);
4843 if (err) {
4844 kfree(mpi);
4845 return NULL;
4846 }
4847
4848 mutex_lock(&mlx5_ib_multiport_mutex);
4849 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4850 if (dev->sys_image_guid == mpi->sys_image_guid)
4851 bound = mlx5_ib_bind_slave_port(dev, mpi);
4852
4853 if (bound) {
4854 rdma_roce_rescan_device(&dev->ib_dev);
4855 break;
4856 }
4857 }
4858
4859 if (!bound) {
4860 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4861 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
4862 } else {
4863 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
4864 }
4865 mutex_unlock(&mlx5_ib_multiport_mutex);
4866
4867 return mpi;
4868}
4869
16c1975f
MB		 4870static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
4871{
32f69e4b
DJ		 4872 enum rdma_link_layer ll;
4873 int port_type_cap;
4874
4875 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4876 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4877
4878 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
4879 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
4880
4881 return mlx5_ib_add_slave_port(mdev, port_num);
4882 }
4883
16c1975f 4884 return __mlx5_ib_add(mdev, &pf_profile);
e126ba97
EC		 4885}
4886
9603b61d 4887static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
e126ba97 4888{
32f69e4b
DJ		 4889 struct mlx5_ib_multiport_info *mpi;
4890 struct mlx5_ib_dev *dev;
4891
4892 if (mlx5_core_is_mp_slave(mdev)) {
4893 mpi = context;
4894 mutex_lock(&mlx5_ib_multiport_mutex);
4895 if (mpi->ibdev)
4896 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4897 list_del(&mpi->list);
4898 mutex_unlock(&mlx5_ib_multiport_mutex);
4899 return;
4900 }
6aec21f6 4901
32f69e4b 4902 dev = context;
16c1975f 4903 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
e126ba97
EC		 4904}
4905
9603b61d
JM		 4906static struct mlx5_interface mlx5_ib_interface = {
4907 .add = mlx5_ib_add,
4908 .remove = mlx5_ib_remove,
4909 .event = mlx5_ib_event,
d9aaed83
AK		 4910#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4911 .pfault = mlx5_ib_pfault,
4912#endif
64613d94 4913 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
e126ba97
EC		 4914};
4915
4916static int __init mlx5_ib_init(void)
4917{
6aec21f6
HE		 4918 int err;
4919
81713d37 4920 mlx5_ib_odp_init();
9603b61d 4921
6aec21f6 4922 err = mlx5_register_interface(&mlx5_ib_interface);
6aec21f6 4923
6aec21f6 4924 return err;
e126ba97
EC		 4925}
4926
4927static void __exit mlx5_ib_cleanup(void)
4928{
9603b61d 4929 mlx5_unregister_interface(&mlx5_ib_interface);
e126ba97
EC		 4930}
4931
4932module_init(mlx5_ib_init);
4933module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)