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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / main.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/sched.h>
42#include <rdma/ib_user_verbs.h>
43#include <rdma/ib_smi.h>
44#include <rdma/ib_umem.h>
45#include "user.h"
46#include "mlx5_ib.h"
47
48#define DRIVER_NAME "mlx5_ib"
49#define DRIVER_VERSION "1.0"
50#define DRIVER_RELDATE "June 2013"
51
52MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
53MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
54MODULE_LICENSE("Dual BSD/GPL");
55MODULE_VERSION(DRIVER_VERSION);
56
57static int prof_sel = 2;
58module_param_named(prof_sel, prof_sel, int, 0444);
59MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
60
61static char mlx5_version[] =
62 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
63 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
64
ad32b95f 65static struct mlx5_profile profile[] = {
e126ba97
EC		 66 [0] = {
67 .mask = 0,
68 },
69 [1] = {
70 .mask = MLX5_PROF_MASK_QP_SIZE,
71 .log_max_qp = 12,
72 },
73 [2] = {
74 .mask = MLX5_PROF_MASK_QP_SIZE |
75 MLX5_PROF_MASK_MR_CACHE,
76 .log_max_qp = 17,
77 .mr_cache[0] = {
78 .size = 500,
79 .limit = 250
80 },
81 .mr_cache[1] = {
82 .size = 500,
83 .limit = 250
84 },
85 .mr_cache[2] = {
86 .size = 500,
87 .limit = 250
88 },
89 .mr_cache[3] = {
90 .size = 500,
91 .limit = 250
92 },
93 .mr_cache[4] = {
94 .size = 500,
95 .limit = 250
96 },
97 .mr_cache[5] = {
98 .size = 500,
99 .limit = 250
100 },
101 .mr_cache[6] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[7] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[8] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[9] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[10] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[11] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[12] = {
126 .size = 64,
127 .limit = 32
128 },
129 .mr_cache[13] = {
130 .size = 32,
131 .limit = 16
132 },
133 .mr_cache[14] = {
134 .size = 16,
135 .limit = 8
136 },
137 .mr_cache[15] = {
138 .size = 8,
139 .limit = 4
140 },
141 },
142};
143
144int mlx5_vector2eqn(struct mlx5_ib_dev *dev, int vector, int *eqn, int *irqn)
145{
146 struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
147 struct mlx5_eq *eq, *n;
148 int err = -ENOENT;
149
150 spin_lock(&table->lock);
151 list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
152 if (eq->index == vector) {
153 *eqn = eq->eqn;
154 *irqn = eq->irqn;
155 err = 0;
156 break;
157 }
158 }
159 spin_unlock(&table->lock);
160
161 return err;
162}
163
164static int alloc_comp_eqs(struct mlx5_ib_dev *dev)
165{
166 struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
ada9f5d0 167 char name[MLX5_MAX_EQ_NAME];
e126ba97
EC		 168 struct mlx5_eq *eq, *n;
169 int ncomp_vec;
170 int nent;
171 int err;
172 int i;
173
174 INIT_LIST_HEAD(&dev->eqs_list);
175 ncomp_vec = table->num_comp_vectors;
176 nent = MLX5_COMP_EQ_SIZE;
177 for (i = 0; i < ncomp_vec; i++) {
178 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
179 if (!eq) {
180 err = -ENOMEM;
181 goto clean;
182 }
183
ada9f5d0 184 snprintf(name, MLX5_MAX_EQ_NAME, "mlx5_comp%d", i);
e126ba97
EC		 185 err = mlx5_create_map_eq(&dev->mdev, eq,
186 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
ada9f5d0 187 name, &dev->mdev.priv.uuari.uars[0]);
e126ba97
EC		 188 if (err) {
189 kfree(eq);
190 goto clean;
191 }
192 mlx5_ib_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
193 eq->index = i;
194 spin_lock(&table->lock);
195 list_add_tail(&eq->list, &dev->eqs_list);
196 spin_unlock(&table->lock);
197 }
198
199 dev->num_comp_vectors = ncomp_vec;
200 return 0;
201
202clean:
203 spin_lock(&table->lock);
204 list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
205 list_del(&eq->list);
206 spin_unlock(&table->lock);
207 if (mlx5_destroy_unmap_eq(&dev->mdev, eq))
208 mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
209 kfree(eq);
210 spin_lock(&table->lock);
211 }
212 spin_unlock(&table->lock);
213 return err;
214}
215
216static void free_comp_eqs(struct mlx5_ib_dev *dev)
217{
218 struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
219 struct mlx5_eq *eq, *n;
220
221 spin_lock(&table->lock);
222 list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
223 list_del(&eq->list);
224 spin_unlock(&table->lock);
225 if (mlx5_destroy_unmap_eq(&dev->mdev, eq))
226 mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
227 kfree(eq);
228 spin_lock(&table->lock);
229 }
230 spin_unlock(&table->lock);
231}
232
233static int mlx5_ib_query_device(struct ib_device *ibdev,
234 struct ib_device_attr *props)
235{
236 struct mlx5_ib_dev *dev = to_mdev(ibdev);
237 struct ib_smp *in_mad = NULL;
238 struct ib_smp *out_mad = NULL;
239 int err = -ENOMEM;
240 int max_rq_sg;
241 int max_sq_sg;
242 u64 flags;
243
244 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
245 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
246 if (!in_mad || !out_mad)
247 goto out;
248
249 init_query_mad(in_mad);
250 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
251
252 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, 1, NULL, NULL, in_mad, out_mad);
253 if (err)
254 goto out;
255
256 memset(props, 0, sizeof(*props));
257
258 props->fw_ver = ((u64)fw_rev_maj(&dev->mdev) << 32) |
259 (fw_rev_min(&dev->mdev) << 16) |
260 fw_rev_sub(&dev->mdev);
261 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
262 IB_DEVICE_PORT_ACTIVE_EVENT |
263 IB_DEVICE_SYS_IMAGE_GUID |
264 IB_DEVICE_RC_RNR_NAK_GEN |
265 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
266 flags = dev->mdev.caps.flags;
267 if (flags & MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR)
268 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
269 if (flags & MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR)
270 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
271 if (flags & MLX5_DEV_CAP_FLAG_APM)
272 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
273 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
274 if (flags & MLX5_DEV_CAP_FLAG_XRC)
275 props->device_cap_flags |= IB_DEVICE_XRC;
276 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
277
278 props->vendor_id = be32_to_cpup((__be32 *)(out_mad->data + 36)) &
279 0xffffff;
280 props->vendor_part_id = be16_to_cpup((__be16 *)(out_mad->data + 30));
281 props->hw_ver = be32_to_cpup((__be32 *)(out_mad->data + 32));
282 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
283
284 props->max_mr_size = ~0ull;
285 props->page_size_cap = dev->mdev.caps.min_page_sz;
286 props->max_qp = 1 << dev->mdev.caps.log_max_qp;
287 props->max_qp_wr = dev->mdev.caps.max_wqes;
288 max_rq_sg = dev->mdev.caps.max_rq_desc_sz / sizeof(struct mlx5_wqe_data_seg);
289 max_sq_sg = (dev->mdev.caps.max_sq_desc_sz - sizeof(struct mlx5_wqe_ctrl_seg)) /
290 sizeof(struct mlx5_wqe_data_seg);
291 props->max_sge = min(max_rq_sg, max_sq_sg);
292 props->max_cq = 1 << dev->mdev.caps.log_max_cq;
293 props->max_cqe = dev->mdev.caps.max_cqes - 1;
294 props->max_mr = 1 << dev->mdev.caps.log_max_mkey;
295 props->max_pd = 1 << dev->mdev.caps.log_max_pd;
296 props->max_qp_rd_atom = dev->mdev.caps.max_ra_req_qp;
297 props->max_qp_init_rd_atom = dev->mdev.caps.max_ra_res_qp;
298 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
299 props->max_srq = 1 << dev->mdev.caps.log_max_srq;
300 props->max_srq_wr = dev->mdev.caps.max_srq_wqes - 1;
301 props->max_srq_sge = max_rq_sg - 1;
302 props->max_fast_reg_page_list_len = (unsigned int)-1;
303 props->local_ca_ack_delay = dev->mdev.caps.local_ca_ack_delay;
81bea28f
EC		 304 props->atomic_cap = IB_ATOMIC_NONE;
305 props->masked_atomic_cap = IB_ATOMIC_NONE;
e126ba97
EC		 306 props->max_pkeys = be16_to_cpup((__be16 *)(out_mad->data + 28));
307 props->max_mcast_grp = 1 << dev->mdev.caps.log_max_mcg;
308 props->max_mcast_qp_attach = dev->mdev.caps.max_qp_mcg;
309 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
310 props->max_mcast_grp;
311 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
312
313out:
314 kfree(in_mad);
315 kfree(out_mad);
316
317 return err;
318}
319
320int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
321 struct ib_port_attr *props)
322{
323 struct mlx5_ib_dev *dev = to_mdev(ibdev);
324 struct ib_smp *in_mad = NULL;
325 struct ib_smp *out_mad = NULL;
326 int ext_active_speed;
327 int err = -ENOMEM;
328
329 if (port < 1 || port > dev->mdev.caps.num_ports) {
330 mlx5_ib_warn(dev, "invalid port number %d\n", port);
331 return -EINVAL;
332 }
333
334 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
335 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
336 if (!in_mad || !out_mad)
337 goto out;
338
339 memset(props, 0, sizeof(*props));
340
341 init_query_mad(in_mad);
342 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
343 in_mad->attr_mod = cpu_to_be32(port);
344
345 err = mlx5_MAD_IFC(dev, 1, 1, port, NULL, NULL, in_mad, out_mad);
346 if (err) {
347 mlx5_ib_warn(dev, "err %d\n", err);
348 goto out;
349 }
350
351
352 props->lid = be16_to_cpup((__be16 *)(out_mad->data + 16));
353 props->lmc = out_mad->data[34] & 0x7;
354 props->sm_lid = be16_to_cpup((__be16 *)(out_mad->data + 18));
355 props->sm_sl = out_mad->data[36] & 0xf;
356 props->state = out_mad->data[32] & 0xf;
357 props->phys_state = out_mad->data[33] >> 4;
358 props->port_cap_flags = be32_to_cpup((__be32 *)(out_mad->data + 20));
359 props->gid_tbl_len = out_mad->data[50];
360 props->max_msg_sz = 1 << to_mdev(ibdev)->mdev.caps.log_max_msg;
361 props->pkey_tbl_len = to_mdev(ibdev)->mdev.caps.port[port - 1].pkey_table_len;
362 props->bad_pkey_cntr = be16_to_cpup((__be16 *)(out_mad->data + 46));
363 props->qkey_viol_cntr = be16_to_cpup((__be16 *)(out_mad->data + 48));
364 props->active_width = out_mad->data[31] & 0xf;
365 props->active_speed = out_mad->data[35] >> 4;
366 props->max_mtu = out_mad->data[41] & 0xf;
367 props->active_mtu = out_mad->data[36] >> 4;
368 props->subnet_timeout = out_mad->data[51] & 0x1f;
369 props->max_vl_num = out_mad->data[37] >> 4;
370 props->init_type_reply = out_mad->data[41] >> 4;
371
372 /* Check if extended speeds (EDR/FDR/...) are supported */
373 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
374 ext_active_speed = out_mad->data[62] >> 4;
375
376 switch (ext_active_speed) {
377 case 1:
378 props->active_speed = 16; /* FDR */
379 break;
380 case 2:
381 props->active_speed = 32; /* EDR */
382 break;
383 }
384 }
385
386 /* If reported active speed is QDR, check if is FDR-10 */
387 if (props->active_speed == 4) {
388 if (dev->mdev.caps.ext_port_cap[port - 1] &
389 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO) {
390 init_query_mad(in_mad);
391 in_mad->attr_id = MLX5_ATTR_EXTENDED_PORT_INFO;
392 in_mad->attr_mod = cpu_to_be32(port);
393
394 err = mlx5_MAD_IFC(dev, 1, 1, port,
395 NULL, NULL, in_mad, out_mad);
396 if (err)
397 goto out;
398
399 /* Checking LinkSpeedActive for FDR-10 */
400 if (out_mad->data[15] & 0x1)
401 props->active_speed = 8;
402 }
403 }
404
405out:
406 kfree(in_mad);
407 kfree(out_mad);
408
409 return err;
410}
411
412static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
413 union ib_gid *gid)
414{
415 struct ib_smp *in_mad = NULL;
416 struct ib_smp *out_mad = NULL;
417 int err = -ENOMEM;
418
419 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
420 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
421 if (!in_mad || !out_mad)
422 goto out;
423
424 init_query_mad(in_mad);
425 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
426 in_mad->attr_mod = cpu_to_be32(port);
427
428 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
429 if (err)
430 goto out;
431
432 memcpy(gid->raw, out_mad->data + 8, 8);
433
434 init_query_mad(in_mad);
435 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
436 in_mad->attr_mod = cpu_to_be32(index / 8);
437
438 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
439 if (err)
440 goto out;
441
442 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
443
444out:
445 kfree(in_mad);
446 kfree(out_mad);
447 return err;
448}
449
450static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
451 u16 *pkey)
452{
453 struct ib_smp *in_mad = NULL;
454 struct ib_smp *out_mad = NULL;
455 int err = -ENOMEM;
456
457 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
458 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
459 if (!in_mad || !out_mad)
460 goto out;
461
462 init_query_mad(in_mad);
463 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
464 in_mad->attr_mod = cpu_to_be32(index / 32);
465
466 err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
467 if (err)
468 goto out;
469
470 *pkey = be16_to_cpu(((__be16 *)out_mad->data)[index % 32]);
471
472out:
473 kfree(in_mad);
474 kfree(out_mad);
475 return err;
476}
477
478struct mlx5_reg_node_desc {
479 u8 desc[64];
480};
481
482static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
483 struct ib_device_modify *props)
484{
485 struct mlx5_ib_dev *dev = to_mdev(ibdev);
486 struct mlx5_reg_node_desc in;
487 struct mlx5_reg_node_desc out;
488 int err;
489
490 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
491 return -EOPNOTSUPP;
492
493 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
494 return 0;
495
496 /*
497 * If possible, pass node desc to FW, so it can generate
498 * a 144 trap. If cmd fails, just ignore.
499 */
500 memcpy(&in, props->node_desc, 64);
501 err = mlx5_core_access_reg(&dev->mdev, &in, sizeof(in), &out,
502 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
503 if (err)
504 return err;
505
506 memcpy(ibdev->node_desc, props->node_desc, 64);
507
508 return err;
509}
510
511static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
512 struct ib_port_modify *props)
513{
514 struct mlx5_ib_dev *dev = to_mdev(ibdev);
515 struct ib_port_attr attr;
516 u32 tmp;
517 int err;
518
519 mutex_lock(&dev->cap_mask_mutex);
520
521 err = mlx5_ib_query_port(ibdev, port, &attr);
522 if (err)
523 goto out;
524
525 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
526 ~props->clr_port_cap_mask;
527
528 err = mlx5_set_port_caps(&dev->mdev, port, tmp);
529
530out:
531 mutex_unlock(&dev->cap_mask_mutex);
532 return err;
533}
534
535static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
536 struct ib_udata *udata)
537{
538 struct mlx5_ib_dev *dev = to_mdev(ibdev);
539 struct mlx5_ib_alloc_ucontext_req req;
540 struct mlx5_ib_alloc_ucontext_resp resp;
541 struct mlx5_ib_ucontext *context;
542 struct mlx5_uuar_info *uuari;
543 struct mlx5_uar *uars;
544 int num_uars;
545 int uuarn;
546 int err;
547 int i;
548
549 if (!dev->ib_active)
550 return ERR_PTR(-EAGAIN);
551
552 err = ib_copy_from_udata(&req, udata, sizeof(req));
553 if (err)
554 return ERR_PTR(err);
555
556 if (req.total_num_uuars > MLX5_MAX_UUARS)
557 return ERR_PTR(-ENOMEM);
558
559 if (req.total_num_uuars == 0)
560 return ERR_PTR(-EINVAL);
561
562 req.total_num_uuars = ALIGN(req.total_num_uuars, MLX5_BF_REGS_PER_PAGE);
563 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
564 return ERR_PTR(-EINVAL);
565
566 num_uars = req.total_num_uuars / MLX5_BF_REGS_PER_PAGE;
567 resp.qp_tab_size = 1 << dev->mdev.caps.log_max_qp;
568 resp.bf_reg_size = dev->mdev.caps.bf_reg_size;
569 resp.cache_line_size = L1_CACHE_BYTES;
570 resp.max_sq_desc_sz = dev->mdev.caps.max_sq_desc_sz;
571 resp.max_rq_desc_sz = dev->mdev.caps.max_rq_desc_sz;
572 resp.max_send_wqebb = dev->mdev.caps.max_wqes;
573 resp.max_recv_wr = dev->mdev.caps.max_wqes;
574 resp.max_srq_recv_wr = dev->mdev.caps.max_srq_wqes;
575
576 context = kzalloc(sizeof(*context), GFP_KERNEL);
577 if (!context)
578 return ERR_PTR(-ENOMEM);
579
580 uuari = &context->uuari;
581 mutex_init(&uuari->lock);
582 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
583 if (!uars) {
584 err = -ENOMEM;
585 goto out_ctx;
586 }
587
588 uuari->bitmap = kcalloc(BITS_TO_LONGS(req.total_num_uuars),
589 sizeof(*uuari->bitmap),
590 GFP_KERNEL);
591 if (!uuari->bitmap) {
592 err = -ENOMEM;
593 goto out_uar_ctx;
594 }
595 /*
596 * clear all fast path uuars
597 */
598 for (i = 0; i < req.total_num_uuars; i++) {
599 uuarn = i & 3;
600 if (uuarn == 2 || uuarn == 3)
601 set_bit(i, uuari->bitmap);
602 }
603
604 uuari->count = kcalloc(req.total_num_uuars, sizeof(*uuari->count), GFP_KERNEL);
605 if (!uuari->count) {
606 err = -ENOMEM;
607 goto out_bitmap;
608 }
609
610 for (i = 0; i < num_uars; i++) {
611 err = mlx5_cmd_alloc_uar(&dev->mdev, &uars[i].index);
612 if (err)
613 goto out_count;
614 }
615
616 INIT_LIST_HEAD(&context->db_page_list);
617 mutex_init(&context->db_page_mutex);
618
619 resp.tot_uuars = req.total_num_uuars;
620 resp.num_ports = dev->mdev.caps.num_ports;
92b0ca7c
DC		 621 err = ib_copy_to_udata(udata, &resp,
622 sizeof(resp) - sizeof(resp.reserved));
e126ba97
EC		 623 if (err)
624 goto out_uars;
625
626 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
627 uuari->uars = uars;
628 uuari->num_uars = num_uars;
629 return &context->ibucontext;
630
631out_uars:
632 for (i--; i >= 0; i--)
633 mlx5_cmd_free_uar(&dev->mdev, uars[i].index);
634out_count:
635 kfree(uuari->count);
636
637out_bitmap:
638 kfree(uuari->bitmap);
639
640out_uar_ctx:
641 kfree(uars);
642
643out_ctx:
644 kfree(context);
645 return ERR_PTR(err);
646}
647
648static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
649{
650 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
651 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
652 struct mlx5_uuar_info *uuari = &context->uuari;
653 int i;
654
655 for (i = 0; i < uuari->num_uars; i++) {
656 if (mlx5_cmd_free_uar(&dev->mdev, uuari->uars[i].index))
657 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
658 }
659
660 kfree(uuari->count);
661 kfree(uuari->bitmap);
662 kfree(uuari->uars);
663 kfree(context);
664
665 return 0;
666}
667
668static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
669{
670 return (pci_resource_start(dev->mdev.pdev, 0) >> PAGE_SHIFT) + index;
671}
672
673static int get_command(unsigned long offset)
674{
675 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
676}
677
678static int get_arg(unsigned long offset)
679{
680 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
681}
682
683static int get_index(unsigned long offset)
684{
685 return get_arg(offset);
686}
687
688static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
689{
690 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
691 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
692 struct mlx5_uuar_info *uuari = &context->uuari;
693 unsigned long command;
694 unsigned long idx;
695 phys_addr_t pfn;
696
697 command = get_command(vma->vm_pgoff);
698 switch (command) {
699 case MLX5_IB_MMAP_REGULAR_PAGE:
700 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
701 return -EINVAL;
702
703 idx = get_index(vma->vm_pgoff);
704 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
705 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
706 (unsigned long long)pfn);
707
708 if (idx >= uuari->num_uars)
709 return -EINVAL;
710
711 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
712 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
713 PAGE_SIZE, vma->vm_page_prot))
714 return -EAGAIN;
715
716 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
717 vma->vm_start,
718 (unsigned long long)pfn << PAGE_SHIFT);
719 break;
720
721 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
722 return -ENOSYS;
723
724 default:
725 return -EINVAL;
726 }
727
728 return 0;
729}
730
731static int alloc_pa_mkey(struct mlx5_ib_dev *dev, u32 *key, u32 pdn)
732{
733 struct mlx5_create_mkey_mbox_in *in;
734 struct mlx5_mkey_seg *seg;
735 struct mlx5_core_mr mr;
736 int err;
737
738 in = kzalloc(sizeof(*in), GFP_KERNEL);
739 if (!in)
740 return -ENOMEM;
741
742 seg = &in->seg;
743 seg->flags = MLX5_PERM_LOCAL_READ | MLX5_ACCESS_MODE_PA;
744 seg->flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
745 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
746 seg->start_addr = 0;
747
748 err = mlx5_core_create_mkey(&dev->mdev, &mr, in, sizeof(*in));
749 if (err) {
750 mlx5_ib_warn(dev, "failed to create mkey, %d\n", err);
751 goto err_in;
752 }
753
754 kfree(in);
755 *key = mr.key;
756
757 return 0;
758
759err_in:
760 kfree(in);
761
762 return err;
763}
764
765static void free_pa_mkey(struct mlx5_ib_dev *dev, u32 key)
766{
767 struct mlx5_core_mr mr;
768 int err;
769
770 memset(&mr, 0, sizeof(mr));
771 mr.key = key;
772 err = mlx5_core_destroy_mkey(&dev->mdev, &mr);
773 if (err)
774 mlx5_ib_warn(dev, "failed to destroy mkey 0x%x\n", key);
775}
776
777static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
778 struct ib_ucontext *context,
779 struct ib_udata *udata)
780{
781 struct mlx5_ib_alloc_pd_resp resp;
782 struct mlx5_ib_pd *pd;
783 int err;
784
785 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
786 if (!pd)
787 return ERR_PTR(-ENOMEM);
788
789 err = mlx5_core_alloc_pd(&to_mdev(ibdev)->mdev, &pd->pdn);
790 if (err) {
791 kfree(pd);
792 return ERR_PTR(err);
793 }
794
795 if (context) {
796 resp.pdn = pd->pdn;
797 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
798 mlx5_core_dealloc_pd(&to_mdev(ibdev)->mdev, pd->pdn);
799 kfree(pd);
800 return ERR_PTR(-EFAULT);
801 }
802 } else {
803 err = alloc_pa_mkey(to_mdev(ibdev), &pd->pa_lkey, pd->pdn);
804 if (err) {
805 mlx5_core_dealloc_pd(&to_mdev(ibdev)->mdev, pd->pdn);
806 kfree(pd);
807 return ERR_PTR(err);
808 }
809 }
810
811 return &pd->ibpd;
812}
813
814static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
815{
816 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
817 struct mlx5_ib_pd *mpd = to_mpd(pd);
818
819 if (!pd->uobject)
820 free_pa_mkey(mdev, mpd->pa_lkey);
821
822 mlx5_core_dealloc_pd(&mdev->mdev, mpd->pdn);
823 kfree(mpd);
824
825 return 0;
826}
827
828static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
829{
830 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
831 int err;
832
833 err = mlx5_core_attach_mcg(&dev->mdev, gid, ibqp->qp_num);
834 if (err)
835 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
836 ibqp->qp_num, gid->raw);
837
838 return err;
839}
840
841static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
842{
843 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
844 int err;
845
846 err = mlx5_core_detach_mcg(&dev->mdev, gid, ibqp->qp_num);
847 if (err)
848 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
849 ibqp->qp_num, gid->raw);
850
851 return err;
852}
853
854static int init_node_data(struct mlx5_ib_dev *dev)
855{
856 struct ib_smp *in_mad = NULL;
857 struct ib_smp *out_mad = NULL;
858 int err = -ENOMEM;
859
860 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
861 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
862 if (!in_mad || !out_mad)
863 goto out;
864
865 init_query_mad(in_mad);
866 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
867
868 err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
869 if (err)
870 goto out;
871
872 memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
873
874 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
875
876 err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
877 if (err)
878 goto out;
879
880 dev->mdev.rev_id = be32_to_cpup((__be32 *)(out_mad->data + 32));
881 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
882
883out:
884 kfree(in_mad);
885 kfree(out_mad);
886 return err;
887}
888
889static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
890 char *buf)
891{
892 struct mlx5_ib_dev *dev =
893 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
894
895 return sprintf(buf, "%d\n", dev->mdev.priv.fw_pages);
896}
897
898static ssize_t show_reg_pages(struct device *device,
899 struct device_attribute *attr, char *buf)
900{
901 struct mlx5_ib_dev *dev =
902 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
903
904 return sprintf(buf, "%d\n", dev->mdev.priv.reg_pages);
905}
906
907static ssize_t show_hca(struct device *device, struct device_attribute *attr,
908 char *buf)
909{
910 struct mlx5_ib_dev *dev =
911 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
912 return sprintf(buf, "MT%d\n", dev->mdev.pdev->device);
913}
914
915static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
916 char *buf)
917{
918 struct mlx5_ib_dev *dev =
919 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
920 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(&dev->mdev),
921 fw_rev_min(&dev->mdev), fw_rev_sub(&dev->mdev));
922}
923
924static ssize_t show_rev(struct device *device, struct device_attribute *attr,
925 char *buf)
926{
927 struct mlx5_ib_dev *dev =
928 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
929 return sprintf(buf, "%x\n", dev->mdev.rev_id);
930}
931
932static ssize_t show_board(struct device *device, struct device_attribute *attr,
933 char *buf)
934{
935 struct mlx5_ib_dev *dev =
936 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
937 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
938 dev->mdev.board_id);
939}
940
941static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
942static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
943static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
944static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
945static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
946static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
947
948static struct device_attribute *mlx5_class_attributes[] = {
949 &dev_attr_hw_rev,
950 &dev_attr_fw_ver,
951 &dev_attr_hca_type,
952 &dev_attr_board_id,
953 &dev_attr_fw_pages,
954 &dev_attr_reg_pages,
955};
956
957static void mlx5_ib_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
958 void *data)
959{
960 struct mlx5_ib_dev *ibdev = container_of(dev, struct mlx5_ib_dev, mdev);
961 struct ib_event ibev;
962 u8 port = 0;
963
964 switch (event) {
965 case MLX5_DEV_EVENT_SYS_ERROR:
966 ibdev->ib_active = false;
967 ibev.event = IB_EVENT_DEVICE_FATAL;
968 break;
969
970 case MLX5_DEV_EVENT_PORT_UP:
971 ibev.event = IB_EVENT_PORT_ACTIVE;
972 port = *(u8 *)data;
973 break;
974
975 case MLX5_DEV_EVENT_PORT_DOWN:
976 ibev.event = IB_EVENT_PORT_ERR;
977 port = *(u8 *)data;
978 break;
979
980 case MLX5_DEV_EVENT_PORT_INITIALIZED:
981 /* not used by ULPs */
982 return;
983
984 case MLX5_DEV_EVENT_LID_CHANGE:
985 ibev.event = IB_EVENT_LID_CHANGE;
986 port = *(u8 *)data;
987 break;
988
989 case MLX5_DEV_EVENT_PKEY_CHANGE:
990 ibev.event = IB_EVENT_PKEY_CHANGE;
991 port = *(u8 *)data;
992 break;
993
994 case MLX5_DEV_EVENT_GUID_CHANGE:
995 ibev.event = IB_EVENT_GID_CHANGE;
996 port = *(u8 *)data;
997 break;
998
999 case MLX5_DEV_EVENT_CLIENT_REREG:
1000 ibev.event = IB_EVENT_CLIENT_REREGISTER;
1001 port = *(u8 *)data;
1002 break;
1003 }
1004
1005 ibev.device = &ibdev->ib_dev;
1006 ibev.element.port_num = port;
1007
a0c84c32
EC		 1008 if (port < 1 || port > ibdev->num_ports) {
1009 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1010 return;
1011 }
1012
e126ba97
EC		 1013 if (ibdev->ib_active)
1014 ib_dispatch_event(&ibev);
1015}
1016
1017static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1018{
1019 int port;
1020
1021 for (port = 1; port <= dev->mdev.caps.num_ports; port++)
1022 mlx5_query_ext_port_caps(dev, port);
1023}
1024
1025static int get_port_caps(struct mlx5_ib_dev *dev)
1026{
1027 struct ib_device_attr *dprops = NULL;
1028 struct ib_port_attr *pprops = NULL;
1029 int err = 0;
1030 int port;
1031
1032 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1033 if (!pprops)
1034 goto out;
1035
1036 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1037 if (!dprops)
1038 goto out;
1039
1040 err = mlx5_ib_query_device(&dev->ib_dev, dprops);
1041 if (err) {
1042 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1043 goto out;
1044 }
1045
1046 for (port = 1; port <= dev->mdev.caps.num_ports; port++) {
1047 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1048 if (err) {
1049 mlx5_ib_warn(dev, "query_port %d failed %d\n", port, err);
1050 break;
1051 }
1052 dev->mdev.caps.port[port - 1].pkey_table_len = dprops->max_pkeys;
1053 dev->mdev.caps.port[port - 1].gid_table_len = pprops->gid_tbl_len;
1054 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1055 dprops->max_pkeys, pprops->gid_tbl_len);
1056 }
1057
1058out:
1059 kfree(pprops);
1060 kfree(dprops);
1061
1062 return err;
1063}
1064
1065static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1066{
1067 int err;
1068
1069 err = mlx5_mr_cache_cleanup(dev);
1070 if (err)
1071 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1072
1073 mlx5_ib_destroy_qp(dev->umrc.qp);
1074 ib_destroy_cq(dev->umrc.cq);
1075 ib_dereg_mr(dev->umrc.mr);
1076 ib_dealloc_pd(dev->umrc.pd);
1077}
1078
1079enum {
1080 MAX_UMR_WR = 128,
1081};
1082
1083static int create_umr_res(struct mlx5_ib_dev *dev)
1084{
1085 struct ib_qp_init_attr *init_attr = NULL;
1086 struct ib_qp_attr *attr = NULL;
1087 struct ib_pd *pd;
1088 struct ib_cq *cq;
1089 struct ib_qp *qp;
1090 struct ib_mr *mr;
1091 int ret;
1092
1093 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1094 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1095 if (!attr || !init_attr) {
1096 ret = -ENOMEM;
1097 goto error_0;
1098 }
1099
1100 pd = ib_alloc_pd(&dev->ib_dev);
1101 if (IS_ERR(pd)) {
1102 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1103 ret = PTR_ERR(pd);
1104 goto error_0;
1105 }
1106
1107 mr = ib_get_dma_mr(pd, IB_ACCESS_LOCAL_WRITE);
1108 if (IS_ERR(mr)) {
1109 mlx5_ib_dbg(dev, "Couldn't create DMA MR for sync UMR QP\n");
1110 ret = PTR_ERR(mr);
1111 goto error_1;
1112 }
1113
1114 cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, 128,
1115 0);
1116 if (IS_ERR(cq)) {
1117 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1118 ret = PTR_ERR(cq);
1119 goto error_2;
1120 }
1121 ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
1122
1123 init_attr->send_cq = cq;
1124 init_attr->recv_cq = cq;
1125 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1126 init_attr->cap.max_send_wr = MAX_UMR_WR;
1127 init_attr->cap.max_send_sge = 1;
1128 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1129 init_attr->port_num = 1;
1130 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1131 if (IS_ERR(qp)) {
1132 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1133 ret = PTR_ERR(qp);
1134 goto error_3;
1135 }
1136 qp->device = &dev->ib_dev;
1137 qp->real_qp = qp;
1138 qp->uobject = NULL;
1139 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1140
1141 attr->qp_state = IB_QPS_INIT;
1142 attr->port_num = 1;
1143 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1144 IB_QP_PORT, NULL);
1145 if (ret) {
1146 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1147 goto error_4;
1148 }
1149
1150 memset(attr, 0, sizeof(*attr));
1151 attr->qp_state = IB_QPS_RTR;
1152 attr->path_mtu = IB_MTU_256;
1153
1154 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1155 if (ret) {
1156 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1157 goto error_4;
1158 }
1159
1160 memset(attr, 0, sizeof(*attr));
1161 attr->qp_state = IB_QPS_RTS;
1162 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1163 if (ret) {
1164 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1165 goto error_4;
1166 }
1167
1168 dev->umrc.qp = qp;
1169 dev->umrc.cq = cq;
1170 dev->umrc.mr = mr;
1171 dev->umrc.pd = pd;
1172
1173 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1174 ret = mlx5_mr_cache_init(dev);
1175 if (ret) {
1176 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
1177 goto error_4;
1178 }
1179
1180 kfree(attr);
1181 kfree(init_attr);
1182
1183 return 0;
1184
1185error_4:
1186 mlx5_ib_destroy_qp(qp);
1187
1188error_3:
1189 ib_destroy_cq(cq);
1190
1191error_2:
1192 ib_dereg_mr(mr);
1193
1194error_1:
1195 ib_dealloc_pd(pd);
1196
1197error_0:
1198 kfree(attr);
1199 kfree(init_attr);
1200 return ret;
1201}
1202
1203static int create_dev_resources(struct mlx5_ib_resources *devr)
1204{
1205 struct ib_srq_init_attr attr;
1206 struct mlx5_ib_dev *dev;
1207 int ret = 0;
1208
1209 dev = container_of(devr, struct mlx5_ib_dev, devr);
1210
1211 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
1212 if (IS_ERR(devr->p0)) {
1213 ret = PTR_ERR(devr->p0);
1214 goto error0;
1215 }
1216 devr->p0->device = &dev->ib_dev;
1217 devr->p0->uobject = NULL;
1218 atomic_set(&devr->p0->usecnt, 0);
1219
1220 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, 1, 0, NULL, NULL);
1221 if (IS_ERR(devr->c0)) {
1222 ret = PTR_ERR(devr->c0);
1223 goto error1;
1224 }
1225 devr->c0->device = &dev->ib_dev;
1226 devr->c0->uobject = NULL;
1227 devr->c0->comp_handler = NULL;
1228 devr->c0->event_handler = NULL;
1229 devr->c0->cq_context = NULL;
1230 atomic_set(&devr->c0->usecnt, 0);
1231
1232 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1233 if (IS_ERR(devr->x0)) {
1234 ret = PTR_ERR(devr->x0);
1235 goto error2;
1236 }
1237 devr->x0->device = &dev->ib_dev;
1238 devr->x0->inode = NULL;
1239 atomic_set(&devr->x0->usecnt, 0);
1240 mutex_init(&devr->x0->tgt_qp_mutex);
1241 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
1242
1243 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
1244 if (IS_ERR(devr->x1)) {
1245 ret = PTR_ERR(devr->x1);
1246 goto error3;
1247 }
1248 devr->x1->device = &dev->ib_dev;
1249 devr->x1->inode = NULL;
1250 atomic_set(&devr->x1->usecnt, 0);
1251 mutex_init(&devr->x1->tgt_qp_mutex);
1252 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
1253
1254 memset(&attr, 0, sizeof(attr));
1255 attr.attr.max_sge = 1;
1256 attr.attr.max_wr = 1;
1257 attr.srq_type = IB_SRQT_XRC;
1258 attr.ext.xrc.cq = devr->c0;
1259 attr.ext.xrc.xrcd = devr->x0;
1260
1261 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
1262 if (IS_ERR(devr->s0)) {
1263 ret = PTR_ERR(devr->s0);
1264 goto error4;
1265 }
1266 devr->s0->device = &dev->ib_dev;
1267 devr->s0->pd = devr->p0;
1268 devr->s0->uobject = NULL;
1269 devr->s0->event_handler = NULL;
1270 devr->s0->srq_context = NULL;
1271 devr->s0->srq_type = IB_SRQT_XRC;
1272 devr->s0->ext.xrc.xrcd = devr->x0;
1273 devr->s0->ext.xrc.cq = devr->c0;
1274 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
1275 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
1276 atomic_inc(&devr->p0->usecnt);
1277 atomic_set(&devr->s0->usecnt, 0);
1278
1279 return 0;
1280
1281error4:
1282 mlx5_ib_dealloc_xrcd(devr->x1);
1283error3:
1284 mlx5_ib_dealloc_xrcd(devr->x0);
1285error2:
1286 mlx5_ib_destroy_cq(devr->c0);
1287error1:
1288 mlx5_ib_dealloc_pd(devr->p0);
1289error0:
1290 return ret;
1291}
1292
1293static void destroy_dev_resources(struct mlx5_ib_resources *devr)
1294{
1295 mlx5_ib_destroy_srq(devr->s0);
1296 mlx5_ib_dealloc_xrcd(devr->x0);
1297 mlx5_ib_dealloc_xrcd(devr->x1);
1298 mlx5_ib_destroy_cq(devr->c0);
1299 mlx5_ib_dealloc_pd(devr->p0);
1300}
1301
1302static int init_one(struct pci_dev *pdev,
1303 const struct pci_device_id *id)
1304{
1305 struct mlx5_core_dev *mdev;
1306 struct mlx5_ib_dev *dev;
1307 int err;
1308 int i;
1309
1310 printk_once(KERN_INFO "%s", mlx5_version);
1311
1312 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
1313 if (!dev)
1314 return -ENOMEM;
1315
1316 mdev = &dev->mdev;
1317 mdev->event = mlx5_ib_event;
1318 if (prof_sel >= ARRAY_SIZE(profile)) {
1319 pr_warn("selected pofile out of range, selceting default\n");
1320 prof_sel = 0;
1321 }
1322 mdev->profile = &profile[prof_sel];
1323 err = mlx5_dev_init(mdev, pdev);
1324 if (err)
1325 goto err_free;
1326
1327 err = get_port_caps(dev);
1328 if (err)
1329 goto err_cleanup;
1330
1331 get_ext_port_caps(dev);
1332
1333 err = alloc_comp_eqs(dev);
1334 if (err)
1335 goto err_cleanup;
1336
1337 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
1338
1339 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
1340 dev->ib_dev.owner = THIS_MODULE;
1341 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
1342 dev->ib_dev.local_dma_lkey = mdev->caps.reserved_lkey;
1343 dev->num_ports = mdev->caps.num_ports;
1344 dev->ib_dev.phys_port_cnt = dev->num_ports;
1345 dev->ib_dev.num_comp_vectors = dev->num_comp_vectors;
1346 dev->ib_dev.dma_device = &mdev->pdev->dev;
1347
1348 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
1349 dev->ib_dev.uverbs_cmd_mask =
1350 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
1351 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
1352 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
1353 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
1354 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
1355 (1ull << IB_USER_VERBS_CMD_REG_MR) |
1356 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
1357 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
1358 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
1359 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
1360 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
1361 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
1362 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
1363 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
1364 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
1365 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
1366 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
1367 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
1368 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
1369 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
1370 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
1371 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
1372 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
1373
1374 dev->ib_dev.query_device = mlx5_ib_query_device;
1375 dev->ib_dev.query_port = mlx5_ib_query_port;
1376 dev->ib_dev.query_gid = mlx5_ib_query_gid;
1377 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
1378 dev->ib_dev.modify_device = mlx5_ib_modify_device;
1379 dev->ib_dev.modify_port = mlx5_ib_modify_port;
1380 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
1381 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
1382 dev->ib_dev.mmap = mlx5_ib_mmap;
1383 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
1384 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
1385 dev->ib_dev.create_ah = mlx5_ib_create_ah;
1386 dev->ib_dev.query_ah = mlx5_ib_query_ah;
1387 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
1388 dev->ib_dev.create_srq = mlx5_ib_create_srq;
1389 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
1390 dev->ib_dev.query_srq = mlx5_ib_query_srq;
1391 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
1392 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
1393 dev->ib_dev.create_qp = mlx5_ib_create_qp;
1394 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
1395 dev->ib_dev.query_qp = mlx5_ib_query_qp;
1396 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
1397 dev->ib_dev.post_send = mlx5_ib_post_send;
1398 dev->ib_dev.post_recv = mlx5_ib_post_recv;
1399 dev->ib_dev.create_cq = mlx5_ib_create_cq;
1400 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
1401 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
1402 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
1403 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
1404 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
1405 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
1406 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
1407 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
1408 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
1409 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
1410 dev->ib_dev.process_mad = mlx5_ib_process_mad;
1411 dev->ib_dev.alloc_fast_reg_mr = mlx5_ib_alloc_fast_reg_mr;
1412 dev->ib_dev.alloc_fast_reg_page_list = mlx5_ib_alloc_fast_reg_page_list;
1413 dev->ib_dev.free_fast_reg_page_list = mlx5_ib_free_fast_reg_page_list;
1414
1415 if (mdev->caps.flags & MLX5_DEV_CAP_FLAG_XRC) {
1416 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
1417 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
1418 dev->ib_dev.uverbs_cmd_mask |=
1419 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
1420 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
1421 }
1422
1423 err = init_node_data(dev);
1424 if (err)
1425 goto err_eqs;
1426
1427 mutex_init(&dev->cap_mask_mutex);
1428 spin_lock_init(&dev->mr_lock);
1429
1430 err = create_dev_resources(&dev->devr);
1431 if (err)
1432 goto err_eqs;
1433
281d1a92
WY		 1434 err = ib_register_device(&dev->ib_dev, NULL);
1435 if (err)
e126ba97
EC		 1436 goto err_rsrc;
1437
1438 err = create_umr_res(dev);
1439 if (err)
1440 goto err_dev;
1441
1442 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
281d1a92
WY		 1443 err = device_create_file(&dev->ib_dev.dev,
1444 mlx5_class_attributes[i]);
1445 if (err)
e126ba97
EC		 1446 goto err_umrc;
1447 }
1448
1449 dev->ib_active = true;
1450
1451 return 0;
1452
1453err_umrc:
1454 destroy_umrc_res(dev);
1455
1456err_dev:
1457 ib_unregister_device(&dev->ib_dev);
1458
1459err_rsrc:
1460 destroy_dev_resources(&dev->devr);
1461
1462err_eqs:
1463 free_comp_eqs(dev);
1464
1465err_cleanup:
1466 mlx5_dev_cleanup(mdev);
1467
1468err_free:
1469 ib_dealloc_device((struct ib_device *)dev);
1470
1471 return err;
1472}
1473
1474static void remove_one(struct pci_dev *pdev)
1475{
1476 struct mlx5_ib_dev *dev = mlx5_pci2ibdev(pdev);
1477
1478 destroy_umrc_res(dev);
1479 ib_unregister_device(&dev->ib_dev);
1480 destroy_dev_resources(&dev->devr);
1481 free_comp_eqs(dev);
1482 mlx5_dev_cleanup(&dev->mdev);
1483 ib_dealloc_device(&dev->ib_dev);
1484}
1485
1486static DEFINE_PCI_DEVICE_TABLE(mlx5_ib_pci_table) = {
1487 { PCI_VDEVICE(MELLANOX, 4113) }, /* MT4113 Connect-IB */
1488 { 0, }
1489};
1490
1491MODULE_DEVICE_TABLE(pci, mlx5_ib_pci_table);
1492
1493static struct pci_driver mlx5_ib_driver = {
1494 .name = DRIVER_NAME,
1495 .id_table = mlx5_ib_pci_table,
1496 .probe = init_one,
1497 .remove = remove_one
1498};
1499
1500static int __init mlx5_ib_init(void)
1501{
1502 return pci_register_driver(&mlx5_ib_driver);
1503}
1504
1505static void __exit mlx5_ib_cleanup(void)
1506{
1507 pci_unregister_driver(&mlx5_ib_driver);
1508}
1509
1510module_init(mlx5_ib_init);
1511module_exit(mlx5_ib_cleanup);
Linux 6.x block layer and io_uring tree(s)