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IB/mlx5: Implement fragmented completion queue (CQ)
[linux-2.6-block.git] / drivers / infiniband / hw / mlx5 / cq.c
CommitLineData
e126ba97 1/*
6cf0a15f 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/kref.h>
34#include <rdma/ib_umem.h>
a8237b32 35#include <rdma/ib_user_verbs.h>
b636401f 36#include <rdma/ib_cache.h>
e126ba97 37#include "mlx5_ib.h"
e126ba97
EC		 38
39static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
40{
41 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
42
43 ibcq->comp_handler(ibcq, ibcq->cq_context);
44}
45
46static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
47{
48 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
49 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
50 struct ib_cq *ibcq = &cq->ibcq;
51 struct ib_event event;
52
53 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
54 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
55 type, mcq->cqn);
56 return;
57 }
58
59 if (ibcq->event_handler) {
60 event.device = &dev->ib_dev;
61 event.event = IB_EVENT_CQ_ERR;
62 event.element.cq = ibcq;
63 ibcq->event_handler(&event, ibcq->cq_context);
64 }
65}
66
e126ba97
EC		 67static void *get_cqe(struct mlx5_ib_cq *cq, int n)
68{
388ca8be 69 return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
e126ba97
EC		 70}
71
bde51583
EC		 72static u8 sw_ownership_bit(int n, int nent)
73{
74 return (n & nent) ? 1 : 0;
75}
76
e126ba97
EC		 77static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
78{
79 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
80 struct mlx5_cqe64 *cqe64;
81
82 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
bde51583
EC		 83
84 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
85 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
86 return cqe;
87 } else {
88 return NULL;
89 }
e126ba97
EC		 90}
91
92static void *next_cqe_sw(struct mlx5_ib_cq *cq)
93{
94 return get_sw_cqe(cq, cq->mcq.cons_index);
95}
96
97static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
98{
99 switch (wq->wr_data[idx]) {
100 case MLX5_IB_WR_UMR:
101 return 0;
102
103 case IB_WR_LOCAL_INV:
104 return IB_WC_LOCAL_INV;
105
8a187ee5
SG		 106 case IB_WR_REG_MR:
107 return IB_WC_REG_MR;
108
e126ba97
EC		 109 default:
110 pr_warn("unknown completion status\n");
111 return 0;
112 }
113}
114
115static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
116 struct mlx5_ib_wq *wq, int idx)
117{
118 wc->wc_flags = 0;
119 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
120 case MLX5_OPCODE_RDMA_WRITE_IMM:
121 wc->wc_flags |= IB_WC_WITH_IMM;
f6b1ee34 122 /* fall through */
e126ba97
EC		 123 case MLX5_OPCODE_RDMA_WRITE:
124 wc->opcode = IB_WC_RDMA_WRITE;
125 break;
126 case MLX5_OPCODE_SEND_IMM:
127 wc->wc_flags |= IB_WC_WITH_IMM;
f6b1ee34 128 /* fall through */
e126ba97
EC		 129 case MLX5_OPCODE_SEND:
130 case MLX5_OPCODE_SEND_INVAL:
131 wc->opcode = IB_WC_SEND;
132 break;
133 case MLX5_OPCODE_RDMA_READ:
134 wc->opcode = IB_WC_RDMA_READ;
135 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
136 break;
137 case MLX5_OPCODE_ATOMIC_CS:
138 wc->opcode = IB_WC_COMP_SWAP;
139 wc->byte_len = 8;
140 break;
141 case MLX5_OPCODE_ATOMIC_FA:
142 wc->opcode = IB_WC_FETCH_ADD;
143 wc->byte_len = 8;
144 break;
145 case MLX5_OPCODE_ATOMIC_MASKED_CS:
146 wc->opcode = IB_WC_MASKED_COMP_SWAP;
147 wc->byte_len = 8;
148 break;
149 case MLX5_OPCODE_ATOMIC_MASKED_FA:
150 wc->opcode = IB_WC_MASKED_FETCH_ADD;
151 wc->byte_len = 8;
152 break;
e126ba97
EC		 153 case MLX5_OPCODE_UMR:
154 wc->opcode = get_umr_comp(wq, idx);
155 break;
156 }
157}
158
159enum {
160 MLX5_GRH_IN_BUFFER = 1,
161 MLX5_GRH_IN_CQE = 2,
162};
163
164static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
165 struct mlx5_ib_qp *qp)
166{
cb34be6d 167 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
e126ba97
EC		 168 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
169 struct mlx5_ib_srq *srq;
170 struct mlx5_ib_wq *wq;
171 u16 wqe_ctr;
12f8fede
MS		 172 u8 roce_packet_type;
173 bool vlan_present;
e126ba97
EC		 174 u8 g;
175
176 if (qp->ibqp.srq || qp->ibqp.xrcd) {
177 struct mlx5_core_srq *msrq = NULL;
178
179 if (qp->ibqp.xrcd) {
9603b61d 180 msrq = mlx5_core_get_srq(dev->mdev,
e126ba97
EC		 181 be32_to_cpu(cqe->srqn));
182 srq = to_mibsrq(msrq);
183 } else {
184 srq = to_msrq(qp->ibqp.srq);
185 }
186 if (srq) {
187 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
188 wc->wr_id = srq->wrid[wqe_ctr];
189 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
190 if (msrq && atomic_dec_and_test(&msrq->refcount))
191 complete(&msrq->free);
192 }
193 } else {
194 wq = &qp->rq;
195 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
196 ++wq->tail;
197 }
198 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
199
200 switch (cqe->op_own >> 4) {
201 case MLX5_CQE_RESP_WR_IMM:
202 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
203 wc->wc_flags = IB_WC_WITH_IMM;
204 wc->ex.imm_data = cqe->imm_inval_pkey;
205 break;
206 case MLX5_CQE_RESP_SEND:
207 wc->opcode = IB_WC_RECV;
c7ce833b
ES		 208 wc->wc_flags = IB_WC_IP_CSUM_OK;
209 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
210 (cqe->hds_ip_ext & CQE_L4_OK))))
211 wc->wc_flags = 0;
e126ba97
EC		 212 break;
213 case MLX5_CQE_RESP_SEND_IMM:
214 wc->opcode = IB_WC_RECV;
215 wc->wc_flags = IB_WC_WITH_IMM;
216 wc->ex.imm_data = cqe->imm_inval_pkey;
217 break;
218 case MLX5_CQE_RESP_SEND_INV:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_INVALIDATE;
221 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
222 break;
223 }
224 wc->slid = be16_to_cpu(cqe->slid);
e126ba97
EC		 225 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
226 wc->dlid_path_bits = cqe->ml_path;
227 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
228 wc->wc_flags |= g ? IB_WC_GRH : 0;
b636401f
SG		 229 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
230 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
231
232 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
233 &wc->pkey_index);
234 } else {
235 wc->pkey_index = 0;
236 }
cb34be6d 237
12f8fede
MS		 238 if (ll != IB_LINK_LAYER_ETHERNET) {
239 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
cb34be6d 240 return;
12f8fede
MS		 241 }
242
243 vlan_present = cqe->l4_l3_hdr_type & 0x1;
244 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
245 if (vlan_present) {
246 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
247 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
248 wc->wc_flags |= IB_WC_WITH_VLAN;
249 } else {
250 wc->sl = 0;
251 }
cb34be6d 252
12f8fede 253 switch (roce_packet_type) {
cb34be6d
AS		 254 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
255 wc->network_hdr_type = RDMA_NETWORK_IB;
256 break;
257 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
258 wc->network_hdr_type = RDMA_NETWORK_IPV6;
259 break;
260 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
261 wc->network_hdr_type = RDMA_NETWORK_IPV4;
262 break;
263 }
264 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
e126ba97
EC		 265}
266
267static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
268{
269 __be32 *p = (__be32 *)cqe;
270 int i;
271
272 mlx5_ib_warn(dev, "dump error cqe\n");
273 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
274 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
275 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
276 be32_to_cpu(p[3]));
277}
278
279static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
280 struct mlx5_err_cqe *cqe,
281 struct ib_wc *wc)
282{
283 int dump = 1;
284
285 switch (cqe->syndrome) {
286 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
287 wc->status = IB_WC_LOC_LEN_ERR;
288 break;
289 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
290 wc->status = IB_WC_LOC_QP_OP_ERR;
291 break;
292 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
293 wc->status = IB_WC_LOC_PROT_ERR;
294 break;
295 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
296 dump = 0;
297 wc->status = IB_WC_WR_FLUSH_ERR;
298 break;
299 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
300 wc->status = IB_WC_MW_BIND_ERR;
301 break;
302 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
303 wc->status = IB_WC_BAD_RESP_ERR;
304 break;
305 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
306 wc->status = IB_WC_LOC_ACCESS_ERR;
307 break;
308 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
309 wc->status = IB_WC_REM_INV_REQ_ERR;
310 break;
311 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
312 wc->status = IB_WC_REM_ACCESS_ERR;
313 break;
314 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
315 wc->status = IB_WC_REM_OP_ERR;
316 break;
317 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
318 wc->status = IB_WC_RETRY_EXC_ERR;
319 dump = 0;
320 break;
321 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
322 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
323 dump = 0;
324 break;
325 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
326 wc->status = IB_WC_REM_ABORT_ERR;
327 break;
328 default:
329 wc->status = IB_WC_GENERAL_ERR;
330 break;
331 }
332
333 wc->vendor_err = cqe->vendor_err_synd;
334 if (dump)
335 dump_cqe(dev, cqe);
336}
337
338static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
339{
340 /* TBD: waiting decision
341 */
342 return 0;
343}
344
345static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
346{
347 struct mlx5_wqe_data_seg *dpseg;
348 void *addr;
349
350 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
351 sizeof(struct mlx5_wqe_raddr_seg) +
352 sizeof(struct mlx5_wqe_atomic_seg);
353 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
354 return addr;
355}
356
357static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
358 uint16_t idx)
359{
360 void *addr;
361 int byte_count;
362 int i;
363
364 if (!is_atomic_response(qp, idx))
365 return;
366
367 byte_count = be32_to_cpu(cqe64->byte_cnt);
368 addr = mlx5_get_atomic_laddr(qp, idx);
369
370 if (byte_count == 4) {
371 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
372 } else {
373 for (i = 0; i < byte_count; i += 8) {
374 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
375 addr += 8;
376 }
377 }
378
379 return;
380}
381
382static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
383 u16 tail, u16 head)
384{
f241e749 385 u16 idx;
e126ba97
EC		 386
387 do {
388 idx = tail & (qp->sq.wqe_cnt - 1);
389 handle_atomic(qp, cqe64, idx);
390 if (idx == head)
391 break;
392
393 tail = qp->sq.w_list[idx].next;
394 } while (1);
395 tail = qp->sq.w_list[idx].next;
396 qp->sq.last_poll = tail;
397}
398
bde51583
EC		 399static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
400{
388ca8be 401 mlx5_frag_buf_free(dev->mdev, &buf->fbc.frag_buf);
bde51583
EC		 402}
403
d5436ba0
SG		 404static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
405 struct ib_sig_err *item)
406{
407 u16 syndrome = be16_to_cpu(cqe->syndrome);
408
409#define GUARD_ERR (1 << 13)
410#define APPTAG_ERR (1 << 12)
411#define REFTAG_ERR (1 << 11)
412
413 if (syndrome & GUARD_ERR) {
414 item->err_type = IB_SIG_BAD_GUARD;
415 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
416 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
417 } else
418 if (syndrome & REFTAG_ERR) {
419 item->err_type = IB_SIG_BAD_REFTAG;
420 item->expected = be32_to_cpu(cqe->expected_reftag);
421 item->actual = be32_to_cpu(cqe->actual_reftag);
422 } else
423 if (syndrome & APPTAG_ERR) {
424 item->err_type = IB_SIG_BAD_APPTAG;
425 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
426 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
427 } else {
428 pr_err("Got signature completion error with bad syndrome %04x\n",
429 syndrome);
430 }
431
432 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
433 item->key = be32_to_cpu(cqe->mkey);
434}
435
89ea94a7
MG		 436static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
437 struct ib_wc *wc, int *npolled)
438{
439 struct mlx5_ib_wq *wq;
440 unsigned int cur;
441 unsigned int idx;
442 int np;
443 int i;
444
445 wq = &qp->sq;
446 cur = wq->head - wq->tail;
447 np = *npolled;
448
449 if (cur == 0)
450 return;
451
452 for (i = 0; i < cur && np < num_entries; i++) {
453 idx = wq->last_poll & (wq->wqe_cnt - 1);
454 wc->wr_id = wq->wrid[idx];
455 wc->status = IB_WC_WR_FLUSH_ERR;
456 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
457 wq->tail++;
458 np++;
459 wc->qp = &qp->ibqp;
460 wc++;
461 wq->last_poll = wq->w_list[idx].next;
462 }
463 *npolled = np;
464}
465
466static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
467 struct ib_wc *wc, int *npolled)
468{
469 struct mlx5_ib_wq *wq;
470 unsigned int cur;
471 int np;
472 int i;
473
474 wq = &qp->rq;
475 cur = wq->head - wq->tail;
476 np = *npolled;
477
478 if (cur == 0)
479 return;
480
481 for (i = 0; i < cur && np < num_entries; i++) {
482 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
483 wc->status = IB_WC_WR_FLUSH_ERR;
484 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
485 wq->tail++;
486 np++;
487 wc->qp = &qp->ibqp;
488 wc++;
489 }
490 *npolled = np;
491}
492
493static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
494 struct ib_wc *wc, int *npolled)
495{
496 struct mlx5_ib_qp *qp;
497
498 *npolled = 0;
4edf8d5c 499 /* Find uncompleted WQEs belonging to that cq and return mmics ones */
89ea94a7
MG		 500 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
501 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
502 if (*npolled >= num_entries)
503 return;
504 }
505
506 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
507 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
508 if (*npolled >= num_entries)
509 return;
510 }
511}
512
e126ba97
EC		 513static int mlx5_poll_one(struct mlx5_ib_cq *cq,
514 struct mlx5_ib_qp **cur_qp,
515 struct ib_wc *wc)
516{
517 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
518 struct mlx5_err_cqe *err_cqe;
519 struct mlx5_cqe64 *cqe64;
520 struct mlx5_core_qp *mqp;
521 struct mlx5_ib_wq *wq;
d5436ba0 522 struct mlx5_sig_err_cqe *sig_err_cqe;
a606b0f6 523 struct mlx5_core_mkey *mmkey;
d5436ba0 524 struct mlx5_ib_mr *mr;
e126ba97
EC		 525 uint8_t opcode;
526 uint32_t qpn;
527 u16 wqe_ctr;
528 void *cqe;
529 int idx;
530
bde51583 531repoll:
e126ba97
EC		 532 cqe = next_cqe_sw(cq);
533 if (!cqe)
534 return -EAGAIN;
535
536 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
537
538 ++cq->mcq.cons_index;
539
540 /* Make sure we read CQ entry contents after we've checked the
541 * ownership bit.
542 */
543 rmb();
544
bde51583
EC		 545 opcode = cqe64->op_own >> 4;
546 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
547 if (likely(cq->resize_buf)) {
548 free_cq_buf(dev, &cq->buf);
549 cq->buf = *cq->resize_buf;
550 kfree(cq->resize_buf);
551 cq->resize_buf = NULL;
552 goto repoll;
553 } else {
554 mlx5_ib_warn(dev, "unexpected resize cqe\n");
555 }
556 }
e126ba97
EC		 557
558 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
559 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
560 /* We do not have to take the QP table lock here,
561 * because CQs will be locked while QPs are removed
562 * from the table.
563 */
9603b61d 564 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
e126ba97
EC		 565 *cur_qp = to_mibqp(mqp);
566 }
567
568 wc->qp = &(*cur_qp)->ibqp;
e126ba97
EC		 569 switch (opcode) {
570 case MLX5_CQE_REQ:
571 wq = &(*cur_qp)->sq;
572 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
573 idx = wqe_ctr & (wq->wqe_cnt - 1);
574 handle_good_req(wc, cqe64, wq, idx);
575 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
576 wc->wr_id = wq->wrid[idx];
577 wq->tail = wq->wqe_head[idx] + 1;
578 wc->status = IB_WC_SUCCESS;
579 break;
580 case MLX5_CQE_RESP_WR_IMM:
581 case MLX5_CQE_RESP_SEND:
582 case MLX5_CQE_RESP_SEND_IMM:
583 case MLX5_CQE_RESP_SEND_INV:
584 handle_responder(wc, cqe64, *cur_qp);
585 wc->status = IB_WC_SUCCESS;
586 break;
587 case MLX5_CQE_RESIZE_CQ:
588 break;
589 case MLX5_CQE_REQ_ERR:
590 case MLX5_CQE_RESP_ERR:
591 err_cqe = (struct mlx5_err_cqe *)cqe64;
592 mlx5_handle_error_cqe(dev, err_cqe, wc);
593 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
594 opcode == MLX5_CQE_REQ_ERR ?
595 "Requestor" : "Responder", cq->mcq.cqn);
596 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
597 err_cqe->syndrome, err_cqe->vendor_err_synd);
598 if (opcode == MLX5_CQE_REQ_ERR) {
599 wq = &(*cur_qp)->sq;
600 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
601 idx = wqe_ctr & (wq->wqe_cnt - 1);
602 wc->wr_id = wq->wrid[idx];
603 wq->tail = wq->wqe_head[idx] + 1;
604 } else {
605 struct mlx5_ib_srq *srq;
606
607 if ((*cur_qp)->ibqp.srq) {
608 srq = to_msrq((*cur_qp)->ibqp.srq);
609 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
610 wc->wr_id = srq->wrid[wqe_ctr];
611 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
612 } else {
613 wq = &(*cur_qp)->rq;
614 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
615 ++wq->tail;
616 }
617 }
618 break;
d5436ba0
SG		 619 case MLX5_CQE_SIG_ERR:
620 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
621
a606b0f6
MB		 622 read_lock(&dev->mdev->priv.mkey_table.lock);
623 mmkey = __mlx5_mr_lookup(dev->mdev,
624 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
a606b0f6 625 mr = to_mibmr(mmkey);
d5436ba0
SG		 626 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
627 mr->sig->sig_err_exists = true;
628 mr->sig->sigerr_count++;
629
630 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
631 cq->mcq.cqn, mr->sig->err_item.key,
632 mr->sig->err_item.err_type,
633 mr->sig->err_item.sig_err_offset,
634 mr->sig->err_item.expected,
635 mr->sig->err_item.actual);
636
a606b0f6 637 read_unlock(&dev->mdev->priv.mkey_table.lock);
d5436ba0 638 goto repoll;
e126ba97
EC		 639 }
640
641 return 0;
642}
643
25361e02
HE		 644static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
645 struct ib_wc *wc)
646{
647 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
648 struct mlx5_ib_wc *soft_wc, *next;
649 int npolled = 0;
650
651 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
652 if (npolled >= num_entries)
653 break;
654
655 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
656 cq->mcq.cqn);
657
658 wc[npolled++] = soft_wc->wc;
659 list_del(&soft_wc->list);
660 kfree(soft_wc);
661 }
662
663 return npolled;
664}
665
e126ba97
EC		 666int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
667{
668 struct mlx5_ib_cq *cq = to_mcq(ibcq);
669 struct mlx5_ib_qp *cur_qp = NULL;
89ea94a7
MG		 670 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
671 struct mlx5_core_dev *mdev = dev->mdev;
e126ba97 672 unsigned long flags;
25361e02 673 int soft_polled = 0;
e126ba97 674 int npolled;
e126ba97
EC		 675
676 spin_lock_irqsave(&cq->lock, flags);
89ea94a7
MG		 677 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
678 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
679 goto out;
680 }
e126ba97 681
25361e02
HE		 682 if (unlikely(!list_empty(&cq->wc_list)))
683 soft_polled = poll_soft_wc(cq, num_entries, wc);
684
685 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
dbdf7d4e 686 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
e126ba97
EC		 687 break;
688 }
689
690 if (npolled)
691 mlx5_cq_set_ci(&cq->mcq);
89ea94a7 692out:
e126ba97
EC		 693 spin_unlock_irqrestore(&cq->lock, flags);
694
dbdf7d4e 695 return soft_polled + npolled;
e126ba97
EC		 696}
697
698int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
699{
ce0f7509 700 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
25361e02 701 struct mlx5_ib_cq *cq = to_mcq(ibcq);
5fe9dec0 702 void __iomem *uar_page = mdev->priv.uar->map;
25361e02
HE		 703 unsigned long irq_flags;
704 int ret = 0;
705
706 spin_lock_irqsave(&cq->lock, irq_flags);
707 if (cq->notify_flags != IB_CQ_NEXT_COMP)
708 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
ce0f7509 709
25361e02
HE		 710 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
711 ret = 1;
712 spin_unlock_irqrestore(&cq->lock, irq_flags);
713
714 mlx5_cq_arm(&cq->mcq,
e126ba97
EC		 715 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
716 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
5fe9dec0 717 uar_page, to_mcq(ibcq)->mcq.cons_index);
e126ba97 718
25361e02 719 return ret;
e126ba97
EC		 720}
721
388ca8be
YC		 722static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
723 struct mlx5_ib_cq_buf *buf,
724 int nent,
725 int cqe_size)
e126ba97 726{
388ca8be
YC		 727 struct mlx5_frag_buf_ctrl *c = &buf->fbc;
728 struct mlx5_frag_buf *frag_buf = &c->frag_buf;
729 u32 cqc_buff[MLX5_ST_SZ_DW(cqc)] = {0};
e126ba97
EC		 730 int err;
731
388ca8be
YC		 732 MLX5_SET(cqc, cqc_buff, log_cq_size, ilog2(cqe_size));
733 MLX5_SET(cqc, cqc_buff, cqe_sz, (cqe_size == 128) ? 1 : 0);
734
735 mlx5_core_init_cq_frag_buf(&buf->fbc, cqc_buff);
736
737 err = mlx5_frag_buf_alloc_node(dev->mdev,
738 nent * cqe_size,
739 frag_buf,
740 dev->mdev->priv.numa_node);
e126ba97
EC		 741 if (err)
742 return err;
743
744 buf->cqe_size = cqe_size;
bde51583 745 buf->nent = nent;
e126ba97
EC		 746
747 return 0;
748}
749
e126ba97
EC		 750static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
751 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
27827786 752 int entries, u32 **cqb,
e126ba97
EC		 753 int *cqe_size, int *index, int *inlen)
754{
1cbe6fc8 755 struct mlx5_ib_create_cq ucmd = {};
a8237b32 756 size_t ucmdlen;
e126ba97 757 int page_shift;
27827786 758 __be64 *pas;
e126ba97
EC		 759 int npages;
760 int ncont;
27827786 761 void *cqc;
e126ba97
EC		 762 int err;
763
e093111d 764 ucmdlen = udata->inlen < sizeof(ucmd) ?
7a0c8f42 765 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
a8237b32
YD		 766
767 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
e126ba97
EC		 768 return -EFAULT;
769
a8237b32 770 if (ucmdlen == sizeof(ucmd) &&
7a0c8f42 771 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
a8237b32
YD		 772 return -EINVAL;
773
e126ba97
EC		 774 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
775 return -EINVAL;
776
777 *cqe_size = ucmd.cqe_size;
778
779 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
780 entries * ucmd.cqe_size,
781 IB_ACCESS_LOCAL_WRITE, 1);
782 if (IS_ERR(cq->buf.umem)) {
783 err = PTR_ERR(cq->buf.umem);
784 return err;
785 }
786
787 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
788 &cq->db);
789 if (err)
790 goto err_umem;
791
762f899a 792 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
e126ba97
EC		 793 &ncont, NULL);
794 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
795 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
796
27827786
SM		 797 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
798 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
1b9a07ee 799 *cqb = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 800 if (!*cqb) {
801 err = -ENOMEM;
802 goto err_db;
803 }
27827786
SM		 804
805 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
806 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
807
808 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
809 MLX5_SET(cqc, cqc, log_page_size,
810 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
e126ba97 811
b037c29a 812 *index = to_mucontext(context)->bfregi.sys_pages[0];
e126ba97 813
1cbe6fc8 814 if (ucmd.cqe_comp_en == 1) {
de57f2ad
GL		 815 if (!((*cqe_size == 128 &&
816 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
817 (*cqe_size == 64 &&
818 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
1cbe6fc8
BW		 819 err = -EOPNOTSUPP;
820 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
821 *cqe_size);
822 goto err_cqb;
823 }
824
825 if (unlikely(!ucmd.cqe_comp_res_format ||
826 !(ucmd.cqe_comp_res_format <
827 MLX5_IB_CQE_RES_RESERVED) ||
828 (ucmd.cqe_comp_res_format &
829 (ucmd.cqe_comp_res_format - 1)))) {
830 err = -EOPNOTSUPP;
831 mlx5_ib_warn(dev, "CQE compression res format %d is not supported!\n",
832 ucmd.cqe_comp_res_format);
833 goto err_cqb;
834 }
835
836 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
837 MLX5_SET(cqc, cqc, mini_cqe_res_format,
838 ilog2(ucmd.cqe_comp_res_format));
839 }
840
7a0c8f42
GL		 841 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
842 if (*cqe_size != 128 ||
843 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
844 err = -EOPNOTSUPP;
845 mlx5_ib_warn(dev,
846 "CQE padding is not supported for CQE size of %dB!\n",
847 *cqe_size);
848 goto err_cqb;
849 }
850
851 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
852 }
853
e126ba97
EC		 854 return 0;
855
1cbe6fc8 856err_cqb:
44f2e99e 857 kfree(*cqb);
1cbe6fc8 858
e126ba97
EC		 859err_db:
860 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
861
862err_umem:
863 ib_umem_release(cq->buf.umem);
864 return err;
865}
866
867static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
868{
869 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
870 ib_umem_release(cq->buf.umem);
871}
872
388ca8be
YC		 873static void init_cq_frag_buf(struct mlx5_ib_cq *cq,
874 struct mlx5_ib_cq_buf *buf)
e126ba97
EC		 875{
876 int i;
877 void *cqe;
878 struct mlx5_cqe64 *cqe64;
879
bde51583 880 for (i = 0; i < buf->nent; i++) {
388ca8be 881 cqe = get_cqe(cq, i);
bde51583
EC		 882 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
883 cqe64->op_own = MLX5_CQE_INVALID << 4;
e126ba97
EC		 884 }
885}
886
887static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
888 int entries, int cqe_size,
27827786 889 u32 **cqb, int *index, int *inlen)
e126ba97 890{
27827786
SM		 891 __be64 *pas;
892 void *cqc;
e126ba97
EC		 893 int err;
894
9603b61d 895 err = mlx5_db_alloc(dev->mdev, &cq->db);
e126ba97
EC		 896 if (err)
897 return err;
898
899 cq->mcq.set_ci_db = cq->db.db;
900 cq->mcq.arm_db = cq->db.db + 1;
e126ba97
EC		 901 cq->mcq.cqe_sz = cqe_size;
902
388ca8be 903 err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
e126ba97
EC		 904 if (err)
905 goto err_db;
906
388ca8be 907 init_cq_frag_buf(cq, &cq->buf);
e126ba97 908
27827786 909 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
388ca8be
YC		 910 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
911 cq->buf.fbc.frag_buf.npages;
1b9a07ee 912 *cqb = kvzalloc(*inlen, GFP_KERNEL);
e126ba97
EC		 913 if (!*cqb) {
914 err = -ENOMEM;
915 goto err_buf;
916 }
e126ba97 917
27827786 918 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
388ca8be 919 mlx5_fill_page_frag_array(&cq->buf.fbc.frag_buf, pas);
27827786
SM		 920
921 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
922 MLX5_SET(cqc, cqc, log_page_size,
388ca8be
YC		 923 cq->buf.fbc.frag_buf.page_shift -
924 MLX5_ADAPTER_PAGE_SHIFT);
27827786 925
5fe9dec0 926 *index = dev->mdev->priv.uar->index;
e126ba97
EC		 927
928 return 0;
929
930err_buf:
931 free_cq_buf(dev, &cq->buf);
932
933err_db:
9603b61d 934 mlx5_db_free(dev->mdev, &cq->db);
e126ba97
EC		 935 return err;
936}
937
938static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
939{
940 free_cq_buf(dev, &cq->buf);
9603b61d 941 mlx5_db_free(dev->mdev, &cq->db);
e126ba97
EC		 942}
943
25361e02
HE		 944static void notify_soft_wc_handler(struct work_struct *work)
945{
946 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
947 notify_work);
948
949 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
950}
951
bcf4c1ea
MB		 952struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
953 const struct ib_cq_init_attr *attr,
954 struct ib_ucontext *context,
e126ba97
EC		 955 struct ib_udata *udata)
956{
bcf4c1ea
MB		 957 int entries = attr->cqe;
958 int vector = attr->comp_vector;
e126ba97
EC		 959 struct mlx5_ib_dev *dev = to_mdev(ibdev);
960 struct mlx5_ib_cq *cq;
961 int uninitialized_var(index);
962 int uninitialized_var(inlen);
27827786
SM		 963 u32 *cqb = NULL;
964 void *cqc;
e126ba97 965 int cqe_size;
0b6e26ce 966 unsigned int irqn;
e126ba97
EC		 967 int eqn;
968 int err;
969
9ea57852
NO		 970 if (entries < 0 ||
971 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
51ee86a4
EC		 972 return ERR_PTR(-EINVAL);
973
34356f64 974 if (check_cq_create_flags(attr->flags))
972ecb82
MB		 975 return ERR_PTR(-EOPNOTSUPP);
976
e126ba97 977 entries = roundup_pow_of_two(entries + 1);
938fe83c 978 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
e126ba97
EC		 979 return ERR_PTR(-EINVAL);
980
981 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
982 if (!cq)
983 return ERR_PTR(-ENOMEM);
984
985 cq->ibcq.cqe = entries - 1;
986 mutex_init(&cq->resize_mutex);
987 spin_lock_init(&cq->lock);
988 cq->resize_buf = NULL;
989 cq->resize_umem = NULL;
051f2630 990 cq->create_flags = attr->flags;
89ea94a7
MG		 991 INIT_LIST_HEAD(&cq->list_send_qp);
992 INIT_LIST_HEAD(&cq->list_recv_qp);
e126ba97
EC		 993
994 if (context) {
995 err = create_cq_user(dev, udata, context, cq, entries,
996 &cqb, &cqe_size, &index, &inlen);
997 if (err)
998 goto err_create;
999 } else {
16b0e069 1000 cqe_size = cache_line_size() == 128 ? 128 : 64;
e126ba97
EC		 1001 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
1002 &index, &inlen);
1003 if (err)
1004 goto err_create;
25361e02
HE		 1005
1006 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
e126ba97
EC		 1007 }
1008
233d05d2 1009 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
e126ba97
EC		 1010 if (err)
1011 goto err_cqb;
1012
27827786
SM		 1013 cq->cqe_size = cqe_size;
1014
1015 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
7a0c8f42
GL		 1016 MLX5_SET(cqc, cqc, cqe_sz,
1017 cqe_sz_to_mlx_sz(cqe_size,
1018 cq->private_flags &
1019 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
27827786
SM		 1020 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1021 MLX5_SET(cqc, cqc, uar_page, index);
1022 MLX5_SET(cqc, cqc, c_eqn, eqn);
1023 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
beb801ac 1024 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
27827786 1025 MLX5_SET(cqc, cqc, oi, 1);
e126ba97 1026
9603b61d 1027 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
e126ba97
EC		 1028 if (err)
1029 goto err_cqb;
1030
1031 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
1032 cq->mcq.irqn = irqn;
c16d2750
MB		 1033 if (context)
1034 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
1035 else
1036 cq->mcq.comp = mlx5_ib_cq_comp;
e126ba97
EC		 1037 cq->mcq.event = mlx5_ib_cq_event;
1038
25361e02
HE		 1039 INIT_LIST_HEAD(&cq->wc_list);
1040
e126ba97
EC		 1041 if (context)
1042 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1043 err = -EFAULT;
1044 goto err_cmd;
1045 }
1046
1047
479163f4 1048 kvfree(cqb);
e126ba97
EC		 1049 return &cq->ibcq;
1050
1051err_cmd:
9603b61d 1052 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
e126ba97
EC		 1053
1054err_cqb:
479163f4 1055 kvfree(cqb);
e126ba97
EC		 1056 if (context)
1057 destroy_cq_user(cq, context);
1058 else
1059 destroy_cq_kernel(dev, cq);
1060
1061err_create:
1062 kfree(cq);
1063
1064 return ERR_PTR(err);
1065}
1066
1067
1068int mlx5_ib_destroy_cq(struct ib_cq *cq)
1069{
1070 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1071 struct mlx5_ib_cq *mcq = to_mcq(cq);
1072 struct ib_ucontext *context = NULL;
1073
1074 if (cq->uobject)
1075 context = cq->uobject->context;
1076
9603b61d 1077 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
e126ba97
EC		 1078 if (context)
1079 destroy_cq_user(mcq, context);
1080 else
1081 destroy_cq_kernel(dev, mcq);
1082
1083 kfree(mcq);
1084
1085 return 0;
1086}
1087
cfd8f1d4 1088static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
e126ba97 1089{
cfd8f1d4 1090 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
e126ba97
EC		 1091}
1092
1093void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1094{
1095 struct mlx5_cqe64 *cqe64, *dest64;
1096 void *cqe, *dest;
1097 u32 prod_index;
1098 int nfreed = 0;
1099 u8 owner_bit;
1100
1101 if (!cq)
1102 return;
1103
1104 /* First we need to find the current producer index, so we
1105 * know where to start cleaning from. It doesn't matter if HW
1106 * adds new entries after this loop -- the QP we're worried
1107 * about is already in RESET, so the new entries won't come
1108 * from our QP and therefore don't need to be checked.
1109 */
1110 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1111 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1112 break;
1113
1114 /* Now sweep backwards through the CQ, removing CQ entries
1115 * that match our QP by copying older entries on top of them.
1116 */
1117 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1118 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1119 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
cfd8f1d4
ML		 1120 if (is_equal_rsn(cqe64, rsn)) {
1121 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
e126ba97
EC		 1122 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1123 ++nfreed;
1124 } else if (nfreed) {
1125 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1126 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1127 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1128 memcpy(dest, cqe, cq->mcq.cqe_sz);
1129 dest64->op_own = owner_bit |
1130 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1131 }
1132 }
1133
1134 if (nfreed) {
1135 cq->mcq.cons_index += nfreed;
1136 /* Make sure update of buffer contents is done before
1137 * updating consumer index.
1138 */
1139 wmb();
1140 mlx5_cq_set_ci(&cq->mcq);
1141 }
1142}
1143
1144void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1145{
1146 if (!cq)
1147 return;
1148
1149 spin_lock_irq(&cq->lock);
1150 __mlx5_ib_cq_clean(cq, qpn, srq);
1151 spin_unlock_irq(&cq->lock);
1152}
1153
1154int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1155{
3bdb31f6
EC		 1156 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1157 struct mlx5_ib_cq *mcq = to_mcq(cq);
1158 int err;
3bdb31f6 1159
938fe83c 1160 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
3bdb31f6
EC		 1161 return -ENOSYS;
1162
b0e9df6d
YC		 1163 if (cq_period > MLX5_MAX_CQ_PERIOD)
1164 return -EINVAL;
1165
27827786
SM		 1166 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1167 cq_period, cq_count);
3bdb31f6
EC		 1168 if (err)
1169 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1170
1171 return err;
e126ba97
EC		 1172}
1173
bde51583
EC		 1174static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1175 int entries, struct ib_udata *udata, int *npas,
1176 int *page_shift, int *cqe_size)
1177{
1178 struct mlx5_ib_resize_cq ucmd;
1179 struct ib_umem *umem;
1180 int err;
1181 int npages;
1182 struct ib_ucontext *context = cq->buf.umem->context;
1183
57761d8d
EC		 1184 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1185 if (err)
1186 return err;
1187
1188 if (ucmd.reserved0 || ucmd.reserved1)
1189 return -EINVAL;
bde51583
EC		 1190
1191 umem = ib_umem_get(context, ucmd.buf_addr, entries * ucmd.cqe_size,
1192 IB_ACCESS_LOCAL_WRITE, 1);
1193 if (IS_ERR(umem)) {
1194 err = PTR_ERR(umem);
1195 return err;
1196 }
1197
762f899a 1198 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
bde51583
EC		 1199 npas, NULL);
1200
1201 cq->resize_umem = umem;
1202 *cqe_size = ucmd.cqe_size;
1203
1204 return 0;
1205}
1206
1207static void un_resize_user(struct mlx5_ib_cq *cq)
1208{
1209 ib_umem_release(cq->resize_umem);
1210}
1211
1212static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1213 int entries, int cqe_size)
1214{
1215 int err;
1216
1217 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1218 if (!cq->resize_buf)
1219 return -ENOMEM;
1220
388ca8be 1221 err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
bde51583
EC		 1222 if (err)
1223 goto ex;
1224
388ca8be 1225 init_cq_frag_buf(cq, cq->resize_buf);
bde51583
EC		 1226
1227 return 0;
1228
1229ex:
1230 kfree(cq->resize_buf);
1231 return err;
1232}
1233
1234static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1235{
1236 free_cq_buf(dev, cq->resize_buf);
1237 cq->resize_buf = NULL;
1238}
1239
1240static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1241{
1242 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1243 struct mlx5_cqe64 *scqe64;
1244 struct mlx5_cqe64 *dcqe64;
1245 void *start_cqe;
1246 void *scqe;
1247 void *dcqe;
1248 int ssize;
1249 int dsize;
1250 int i;
1251 u8 sw_own;
1252
1253 ssize = cq->buf.cqe_size;
1254 dsize = cq->resize_buf->cqe_size;
1255 if (ssize != dsize) {
1256 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1257 return -EINVAL;
1258 }
1259
1260 i = cq->mcq.cons_index;
1261 scqe = get_sw_cqe(cq, i);
1262 scqe64 = ssize == 64 ? scqe : scqe + 64;
1263 start_cqe = scqe;
1264 if (!scqe) {
1265 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1266 return -EINVAL;
1267 }
1268
1269 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
388ca8be
YC		 1270 dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1271 (i + 1) & cq->resize_buf->nent);
bde51583
EC		 1272 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1273 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1274 memcpy(dcqe, scqe, dsize);
1275 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1276
1277 ++i;
1278 scqe = get_sw_cqe(cq, i);
1279 scqe64 = ssize == 64 ? scqe : scqe + 64;
1280 if (!scqe) {
1281 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1282 return -EINVAL;
1283 }
1284
1285 if (scqe == start_cqe) {
1286 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1287 cq->mcq.cqn);
1288 return -ENOMEM;
1289 }
1290 }
1291 ++cq->mcq.cons_index;
1292 return 0;
1293}
1294
e126ba97
EC		 1295int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1296{
bde51583
EC		 1297 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1298 struct mlx5_ib_cq *cq = to_mcq(ibcq);
27827786
SM		 1299 void *cqc;
1300 u32 *in;
bde51583
EC		 1301 int err;
1302 int npas;
27827786 1303 __be64 *pas;
bde51583
EC		 1304 int page_shift;
1305 int inlen;
1306 int uninitialized_var(cqe_size);
1307 unsigned long flags;
1308
938fe83c 1309 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
bde51583
EC		 1310 pr_info("Firmware does not support resize CQ\n");
1311 return -ENOSYS;
1312 }
1313
3c4c3774
NO		 1314 if (entries < 1 ||
1315 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1316 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1317 entries,
1318 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
bde51583 1319 return -EINVAL;
3c4c3774 1320 }
bde51583
EC		 1321
1322 entries = roundup_pow_of_two(entries + 1);
3c4c3774 1323 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
bde51583
EC		 1324 return -EINVAL;
1325
1326 if (entries == ibcq->cqe + 1)
1327 return 0;
1328
1329 mutex_lock(&cq->resize_mutex);
1330 if (udata) {
1331 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1332 &cqe_size);
1333 } else {
1334 cqe_size = 64;
1335 err = resize_kernel(dev, cq, entries, cqe_size);
1336 if (!err) {
388ca8be
YC		 1337 struct mlx5_frag_buf_ctrl *c;
1338
1339 c = &cq->resize_buf->fbc;
1340 npas = c->frag_buf.npages;
1341 page_shift = c->frag_buf.page_shift;
bde51583
EC		 1342 }
1343 }
1344
1345 if (err)
1346 goto ex;
1347
27827786
SM		 1348 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1349 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1350
1b9a07ee 1351 in = kvzalloc(inlen, GFP_KERNEL);
bde51583
EC		 1352 if (!in) {
1353 err = -ENOMEM;
1354 goto ex_resize;
1355 }
1356
27827786 1357 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
bde51583
EC		 1358 if (udata)
1359 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
27827786 1360 pas, 0);
bde51583 1361 else
388ca8be
YC		 1362 mlx5_fill_page_frag_array(&cq->resize_buf->fbc.frag_buf,
1363 pas);
27827786
SM		 1364
1365 MLX5_SET(modify_cq_in, in,
1366 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1367 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1368 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1369 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1370
1371 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1372
1373 MLX5_SET(cqc, cqc, log_page_size,
1374 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
7a0c8f42
GL		 1375 MLX5_SET(cqc, cqc, cqe_sz,
1376 cqe_sz_to_mlx_sz(cqe_size,
1377 cq->private_flags &
1378 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
27827786
SM		 1379 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1380
1381 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1382 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
bde51583 1383
9603b61d 1384 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
bde51583
EC		 1385 if (err)
1386 goto ex_alloc;
1387
1388 if (udata) {
1389 cq->ibcq.cqe = entries - 1;
1390 ib_umem_release(cq->buf.umem);
1391 cq->buf.umem = cq->resize_umem;
1392 cq->resize_umem = NULL;
1393 } else {
1394 struct mlx5_ib_cq_buf tbuf;
1395 int resized = 0;
1396
1397 spin_lock_irqsave(&cq->lock, flags);
1398 if (cq->resize_buf) {
1399 err = copy_resize_cqes(cq);
1400 if (!err) {
1401 tbuf = cq->buf;
1402 cq->buf = *cq->resize_buf;
1403 kfree(cq->resize_buf);
1404 cq->resize_buf = NULL;
1405 resized = 1;
1406 }
1407 }
1408 cq->ibcq.cqe = entries - 1;
1409 spin_unlock_irqrestore(&cq->lock, flags);
1410 if (resized)
1411 free_cq_buf(dev, &tbuf);
1412 }
1413 mutex_unlock(&cq->resize_mutex);
1414
479163f4 1415 kvfree(in);
bde51583
EC		 1416 return 0;
1417
1418ex_alloc:
479163f4 1419 kvfree(in);
bde51583
EC		 1420
1421ex_resize:
1422 if (udata)
1423 un_resize_user(cq);
1424 else
1425 un_resize_kernel(dev, cq);
1426ex:
1427 mutex_unlock(&cq->resize_mutex);
1428 return err;
e126ba97
EC		 1429}
1430
1431int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1432{
1433 struct mlx5_ib_cq *cq;
1434
1435 if (!ibcq)
1436 return 128;
1437
1438 cq = to_mcq(ibcq);
1439 return cq->cqe_size;
1440}
25361e02
HE		 1441
1442/* Called from atomic context */
1443int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1444{
1445 struct mlx5_ib_wc *soft_wc;
1446 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1447 unsigned long flags;
1448
1449 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1450 if (!soft_wc)
1451 return -ENOMEM;
1452
1453 soft_wc->wc = *wc;
1454 spin_lock_irqsave(&cq->lock, flags);
1455 list_add_tail(&soft_wc->list, &cq->wc_list);
1456 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1457 wc->status != IB_WC_SUCCESS) {
1458 cq->notify_flags = 0;
1459 schedule_work(&cq->notify_work);
1460 }
1461 spin_unlock_irqrestore(&cq->lock, flags);
1462
1463 return 0;
1464}
Linux 6.x block layer and io_uring tree(s)