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(IB, net)/mlx4: Add resource utilization support
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
0ef2f05c 39#include <linux/vmalloc.h>
ea54b10c 40
225c7b1f
RD		 41#include <rdma/ib_cache.h>
42#include <rdma/ib_pack.h>
4c3eb3ca 43#include <rdma/ib_addr.h>
1ffeb2eb 44#include <rdma/ib_mad.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
9ce28a20 50#include <rdma/mlx4-abi.h>
225c7b1f 51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
79struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 86 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 117};
118
119static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
120{
121 return container_of(mqp, struct mlx4_ib_sqp, qp);
122}
123
1ffeb2eb
JM		 124static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
125{
126 if (!mlx4_is_master(dev->dev))
127 return 0;
128
47605df9
JM		 129 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
130 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
131 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 132}
133
225c7b1f
RD		 134static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
135{
47605df9
JM		 136 int proxy_sqp = 0;
137 int real_sqp = 0;
138 int i;
139 /* PPF or Native -- real SQP */
140 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
141 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
142 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
143 if (real_sqp)
144 return 1;
145 /* VF or PF -- proxy SQP */
146 if (mlx4_is_mfunc(dev->dev)) {
147 for (i = 0; i < dev->dev->caps.num_ports; i++) {
148 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
149 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
150 proxy_sqp = 1;
151 break;
152 }
153 }
154 }
e1b866c6
MS		 155 if (proxy_sqp)
156 return 1;
157
158 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 159}
160
1ffeb2eb 161/* used for INIT/CLOSE port logic */
225c7b1f
RD		 162static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
163{
47605df9
JM		 164 int proxy_qp0 = 0;
165 int real_qp0 = 0;
166 int i;
167 /* PPF or Native -- real QP0 */
168 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
169 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
170 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
171 if (real_qp0)
172 return 1;
173 /* VF or PF -- proxy QP0 */
174 if (mlx4_is_mfunc(dev->dev)) {
175 for (i = 0; i < dev->dev->caps.num_ports; i++) {
176 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
177 proxy_qp0 = 1;
178 break;
179 }
180 }
181 }
182 return proxy_qp0;
225c7b1f
RD		 183}
184
185static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
186{
1c69fc2a 187 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 188}
189
190static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
191{
192 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
193}
194
195static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
198}
199
0e6e7416
RD		 200/*
201 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 202 * first four bytes of every 64 byte chunk with
203 * 0x7FFFFFF | (invalid_ownership_value << 31).
204 *
205 * When the max work request size is less than or equal to the WQE
206 * basic block size, as an optimization, we can stamp all WQEs with
207 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 208 */
ea54b10c 209static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 210{
d2ae16d5 211 __be32 *wqe;
0e6e7416 212 int i;
ea54b10c
JM		 213 int s;
214 int ind;
215 void *buf;
216 __be32 stamp;
9670e553 217 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 218
ea54b10c 219 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 220 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 221 for (i = 0; i < s; i += 64) {
222 ind = (i >> qp->sq.wqe_shift) + n;
223 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
224 cpu_to_be32(0xffffffff);
225 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
226 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
227 *wqe = stamp;
228 }
229 } else {
9670e553 230 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
224e92e0 231 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
ea54b10c
JM		 232 for (i = 64; i < s; i += 64) {
233 wqe = buf + i;
d2ae16d5 234 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 235 }
236 }
237}
238
239static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
240{
241 struct mlx4_wqe_ctrl_seg *ctrl;
242 struct mlx4_wqe_inline_seg *inl;
243 void *wqe;
244 int s;
245
246 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
247 s = sizeof(struct mlx4_wqe_ctrl_seg);
248
249 if (qp->ibqp.qp_type == IB_QPT_UD) {
250 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
251 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
252 memset(dgram, 0, sizeof *dgram);
253 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
254 s += sizeof(struct mlx4_wqe_datagram_seg);
255 }
256
257 /* Pad the remainder of the WQE with an inline data segment. */
258 if (size > s) {
259 inl = wqe + s;
260 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
261 }
262 ctrl->srcrb_flags = 0;
224e92e0 263 ctrl->qpn_vlan.fence_size = size / 16;
ea54b10c
JM		 264 /*
265 * Make sure descriptor is fully written before setting ownership bit
266 * (because HW can start executing as soon as we do).
267 */
268 wmb();
269
270 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
271 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 272
ea54b10c
JM		 273 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
274}
275
276/* Post NOP WQE to prevent wrap-around in the middle of WR */
277static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
278{
279 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
280 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
281 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
282 ind += s;
283 }
284 return ind;
0e6e7416
RD		 285}
286
225c7b1f
RD		 287static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
288{
289 struct ib_event event;
290 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
291
292 if (type == MLX4_EVENT_TYPE_PATH_MIG)
293 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
294
295 if (ibqp->event_handler) {
296 event.device = ibqp->device;
297 event.element.qp = ibqp;
298 switch (type) {
299 case MLX4_EVENT_TYPE_PATH_MIG:
300 event.event = IB_EVENT_PATH_MIG;
301 break;
302 case MLX4_EVENT_TYPE_COMM_EST:
303 event.event = IB_EVENT_COMM_EST;
304 break;
305 case MLX4_EVENT_TYPE_SQ_DRAINED:
306 event.event = IB_EVENT_SQ_DRAINED;
307 break;
308 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
309 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
310 break;
311 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
312 event.event = IB_EVENT_QP_FATAL;
313 break;
314 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
315 event.event = IB_EVENT_PATH_MIG_ERR;
316 break;
317 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
318 event.event = IB_EVENT_QP_REQ_ERR;
319 break;
320 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
321 event.event = IB_EVENT_QP_ACCESS_ERR;
322 break;
323 default:
987c8f8f 324 pr_warn("Unexpected event type %d "
225c7b1f
RD		 325 "on QP %06x\n", type, qp->qpn);
326 return;
327 }
328
329 ibqp->event_handler(&event, ibqp->qp_context);
330 }
331}
332
1ffeb2eb 333static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 334{
335 /*
336 * UD WQEs must have a datagram segment.
337 * RC and UC WQEs might have a remote address segment.
338 * MLX WQEs need two extra inline data segments (for the UD
339 * header and space for the ICRC).
340 */
341 switch (type) {
1ffeb2eb 342 case MLX4_IB_QPT_UD:
225c7b1f 343 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 344 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 345 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 346 case MLX4_IB_QPT_PROXY_SMI_OWNER:
347 case MLX4_IB_QPT_PROXY_SMI:
348 case MLX4_IB_QPT_PROXY_GSI:
349 return sizeof (struct mlx4_wqe_ctrl_seg) +
350 sizeof (struct mlx4_wqe_datagram_seg) + 64;
351 case MLX4_IB_QPT_TUN_SMI_OWNER:
352 case MLX4_IB_QPT_TUN_GSI:
353 return sizeof (struct mlx4_wqe_ctrl_seg) +
354 sizeof (struct mlx4_wqe_datagram_seg);
355
356 case MLX4_IB_QPT_UC:
225c7b1f
RD		 357 return sizeof (struct mlx4_wqe_ctrl_seg) +
358 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 359 case MLX4_IB_QPT_RC:
225c7b1f 360 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 361 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 362 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 363 case MLX4_IB_QPT_SMI:
364 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 365 return sizeof (struct mlx4_wqe_ctrl_seg) +
366 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 367 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
368 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 369 sizeof (struct mlx4_wqe_inline_seg),
370 sizeof (struct mlx4_wqe_data_seg)) +
371 ALIGN(4 +
372 sizeof (struct mlx4_wqe_inline_seg),
373 sizeof (struct mlx4_wqe_data_seg));
374 default:
375 return sizeof (struct mlx4_wqe_ctrl_seg);
376 }
377}
378
2446304d 379static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
ea30b966
MG		 380 int is_user, int has_rq, struct mlx4_ib_qp *qp,
381 u32 inl_recv_sz)
225c7b1f 382{
2446304d 383 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 384 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
385 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 386 return -EINVAL;
387
0a1405da 388 if (!has_rq) {
ea30b966 389 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 390 return -EINVAL;
2446304d 391
0e6e7416 392 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 393 } else {
ea30b966
MG		 394 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
395 sizeof(struct mlx4_wqe_data_seg);
396 u32 wqe_size;
397
a4cd7ed8 398 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 399 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
400 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 401 return -EINVAL;
402
0e6e7416 403 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 404 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 405 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
406 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 407 }
2446304d 408
fc2d0044
SG		 409 /* leave userspace return values as they were, so as not to break ABI */
410 if (is_user) {
411 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
412 cap->max_recv_sge = qp->rq.max_gs;
413 } else {
414 cap->max_recv_wr = qp->rq.max_post =
415 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
416 cap->max_recv_sge = min(qp->rq.max_gs,
417 min(dev->dev->caps.max_sq_sg,
418 dev->dev->caps.max_rq_sg));
419 }
2446304d
EC		 420
421 return 0;
422}
423
424static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
73898db0
HA		 425 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
426 bool shrink_wqe)
2446304d 427{
ea54b10c
JM		 428 int s;
429
2446304d 430 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 431 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
432 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 433 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 434 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
435 return -EINVAL;
436
437 /*
438 * For MLX transport we need 2 extra S/G entries:
439 * one for the header and one for the checksum at the end
440 */
1ffeb2eb
JM		 441 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
442 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 443 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
444 return -EINVAL;
445
ea54b10c
JM		 446 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
447 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 448 send_wqe_overhead(type, qp->flags);
225c7b1f 449
cd155c1c
RD		 450 if (s > dev->dev->caps.max_sq_desc_sz)
451 return -EINVAL;
452
0e6e7416 453 /*
ea54b10c
JM		 454 * Hermon supports shrinking WQEs, such that a single work
455 * request can include multiple units of 1 << wqe_shift. This
456 * way, work requests can differ in size, and do not have to
457 * be a power of 2 in size, saving memory and speeding up send
458 * WR posting. Unfortunately, if we do this then the
459 * wqe_index field in CQEs can't be used to look up the WR ID
460 * anymore, so we do this only if selective signaling is off.
461 *
462 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 463 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 464 * constant-sized WRs to make sure a WR is always fully within
465 * a single page-sized chunk.
466 *
467 * Finally, we use NOP work requests to pad the end of the
468 * work queue, to avoid wrap-around in the middle of WR. We
469 * set NEC bit to avoid getting completions with error for
470 * these NOP WRs, but since NEC is only supported starting
471 * with firmware 2.2.232, we use constant-sized WRs for older
472 * firmware.
473 *
474 * And, since MLX QPs only support SEND, we use constant-sized
475 * WRs in this case.
476 *
477 * We look for the smallest value of wqe_shift such that the
478 * resulting number of wqes does not exceed device
479 * capabilities.
480 *
481 * We set WQE size to at least 64 bytes, this way stamping
482 * invalidates each WQE.
0e6e7416 483 */
73898db0 484 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
ea54b10c 485 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 486 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
487 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
488 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 489 qp->sq.wqe_shift = ilog2(64);
490 else
491 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
492
493 for (;;) {
ea54b10c
JM		 494 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
495
496 /*
497 * We need to leave 2 KB + 1 WR of headroom in the SQ to
498 * allow HW to prefetch.
499 */
500 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
501 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
502 qp->sq_max_wqes_per_wr +
503 qp->sq_spare_wqes);
504
505 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
506 break;
507
508 if (qp->sq_max_wqes_per_wr <= 1)
509 return -EINVAL;
510
511 ++qp->sq.wqe_shift;
512 }
513
cd155c1c
RD		 514 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
515 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 516 send_wqe_overhead(type, qp->flags)) /
517 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 518
519 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
520 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 521 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
522 qp->rq.offset = 0;
0e6e7416 523 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 524 } else {
0e6e7416 525 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 526 qp->sq.offset = 0;
527 }
528
ea54b10c
JM		 529 cap->max_send_wr = qp->sq.max_post =
530 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 531 cap->max_send_sge = min(qp->sq.max_gs,
532 min(dev->dev->caps.max_sq_sg,
533 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 534 /* We don't support inline sends for kernel QPs (yet) */
535 cap->max_inline_data = 0;
225c7b1f
RD		 536
537 return 0;
538}
539
83904132
JM		 540static int set_user_sq_size(struct mlx4_ib_dev *dev,
541 struct mlx4_ib_qp *qp,
2446304d
EC		 542 struct mlx4_ib_create_qp *ucmd)
543{
83904132
JM		 544 /* Sanity check SQ size before proceeding */
545 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
546 ucmd->log_sq_stride >
547 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
548 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
549 return -EINVAL;
550
0e6e7416 551 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 552 qp->sq.wqe_shift = ucmd->log_sq_stride;
553
0e6e7416
RD		 554 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
555 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 556
557 return 0;
558}
559
1ffeb2eb
JM		 560static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
561{
562 int i;
563
564 qp->sqp_proxy_rcv =
565 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
566 GFP_KERNEL);
567 if (!qp->sqp_proxy_rcv)
568 return -ENOMEM;
569 for (i = 0; i < qp->rq.wqe_cnt; i++) {
570 qp->sqp_proxy_rcv[i].addr =
571 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
572 GFP_KERNEL);
573 if (!qp->sqp_proxy_rcv[i].addr)
574 goto err;
575 qp->sqp_proxy_rcv[i].map =
576 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
577 sizeof (struct mlx4_ib_proxy_sqp_hdr),
578 DMA_FROM_DEVICE);
cc47d369
SO		 579 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
580 kfree(qp->sqp_proxy_rcv[i].addr);
581 goto err;
582 }
1ffeb2eb
JM		 583 }
584 return 0;
585
586err:
587 while (i > 0) {
588 --i;
589 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
590 sizeof (struct mlx4_ib_proxy_sqp_hdr),
591 DMA_FROM_DEVICE);
592 kfree(qp->sqp_proxy_rcv[i].addr);
593 }
594 kfree(qp->sqp_proxy_rcv);
595 qp->sqp_proxy_rcv = NULL;
596 return -ENOMEM;
597}
598
599static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
600{
601 int i;
602
603 for (i = 0; i < qp->rq.wqe_cnt; i++) {
604 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
605 sizeof (struct mlx4_ib_proxy_sqp_hdr),
606 DMA_FROM_DEVICE);
607 kfree(qp->sqp_proxy_rcv[i].addr);
608 }
609 kfree(qp->sqp_proxy_rcv);
610}
611
0a1405da
SH		 612static int qp_has_rq(struct ib_qp_init_attr *attr)
613{
614 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
615 return 0;
616
617 return !attr->srq;
618}
619
99ec41d0
JM		 620static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
621{
622 int i;
623 for (i = 0; i < dev->caps.num_ports; i++) {
624 if (qpn == dev->caps.qp0_proxy[i])
625 return !!dev->caps.qp0_qkey[i];
626 }
627 return 0;
628}
629
7b59f0f9
EBE		 630static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
631 struct mlx4_ib_qp *qp)
632{
633 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
634 mlx4_counter_free(dev->dev, qp->counter_index->index);
635 list_del(&qp->counter_index->list);
636 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
637
638 kfree(qp->counter_index);
639 qp->counter_index = NULL;
640}
641
225c7b1f
RD		 642static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
643 struct ib_qp_init_attr *init_attr,
8900b894
LR		 644 struct ib_udata *udata, int sqpn,
645 struct mlx4_ib_qp **caller_qp)
225c7b1f 646{
a3cdcbfa 647 int qpn;
225c7b1f 648 int err;
73898db0 649 struct ib_qp_cap backup_cap;
b42dde47 650 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 651 struct mlx4_ib_qp *qp;
652 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 653 struct mlx4_ib_cq *mcq;
654 unsigned long flags;
1ffeb2eb
JM		 655
656 /* When tunneling special qps, we use a plain UD qp */
657 if (sqpn) {
658 if (mlx4_is_mfunc(dev->dev) &&
659 (!mlx4_is_master(dev->dev) ||
660 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
661 if (init_attr->qp_type == IB_QPT_GSI)
662 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 663 else {
664 if (mlx4_is_master(dev->dev) ||
665 qp0_enabled_vf(dev->dev, sqpn))
666 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
667 else
668 qp_type = MLX4_IB_QPT_PROXY_SMI;
669 }
1ffeb2eb
JM		 670 }
671 qpn = sqpn;
672 /* add extra sg entry for tunneling */
673 init_attr->cap.max_recv_sge++;
674 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
675 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
676 container_of(init_attr,
677 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
678 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
679 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
680 !mlx4_is_master(dev->dev))
681 return -EINVAL;
682 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
683 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 684 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
685 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
686 tnl_init->port))
1ffeb2eb
JM		 687 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
688 else
689 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 690 /* we are definitely in the PPF here, since we are creating
691 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
692 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
693 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 694 sqpn = qpn;
695 }
696
697 if (!*caller_qp) {
698 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
699 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
700 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 701 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 702 if (!sqp)
703 return -ENOMEM;
704 qp = &sqp->qp;
2f5bb473
JM		 705 qp->pri.vid = 0xFFFF;
706 qp->alt.vid = 0xFFFF;
1ffeb2eb 707 } else {
8900b894 708 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 709 if (!qp)
710 return -ENOMEM;
2f5bb473
JM		 711 qp->pri.vid = 0xFFFF;
712 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 713 }
714 } else
715 qp = *caller_qp;
716
717 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 718
719 mutex_init(&qp->mutex);
720 spin_lock_init(&qp->sq.lock);
721 spin_lock_init(&qp->rq.lock);
fa417f7b 722 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 723 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 724
725 qp->state = IB_QPS_RESET;
ea54b10c
JM		 726 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
727 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 728
225c7b1f
RD		 729
730 if (pd->uobject) {
731 struct mlx4_ib_create_qp ucmd;
732
733 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
734 err = -EFAULT;
735 goto err;
736 }
737
ea30b966
MG		 738 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
739 qp_has_rq(init_attr), qp, ucmd.inl_recv_sz);
740 if (err)
741 goto err;
742
743 qp->inl_recv_sz = ucmd.inl_recv_sz;
0e6e7416
RD		 744 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
745
83904132 746 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 747 if (err)
748 goto err;
749
225c7b1f 750 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 751 qp->buf_size, 0, 0);
225c7b1f
RD		 752 if (IS_ERR(qp->umem)) {
753 err = PTR_ERR(qp->umem);
754 goto err;
755 }
756
757 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
3e7e1193 758 qp->umem->page_shift, &qp->mtt);
225c7b1f
RD		 759 if (err)
760 goto err_buf;
761
762 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
763 if (err)
764 goto err_mtt;
765
0a1405da 766 if (qp_has_rq(init_attr)) {
02d89b87
RD		 767 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
768 ucmd.db_addr, &qp->db);
769 if (err)
770 goto err_mtt;
771 }
f3301870 772 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 773 } else {
ea30b966
MG		 774 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
775 qp_has_rq(init_attr), qp, 0);
776 if (err)
777 goto err;
778
0e6e7416
RD		 779 qp->sq_no_prefetch = 0;
780
b832be1e
EC		 781 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
782 qp->flags |= MLX4_IB_QP_LSO;
783
c1c98501
MB		 784 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
785 if (dev->steering_support ==
786 MLX4_STEERING_MODE_DEVICE_MANAGED)
787 qp->flags |= MLX4_IB_QP_NETIF;
788 else
789 goto err;
790 }
791
73898db0
HA		 792 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
793 err = set_kernel_sq_size(dev, &init_attr->cap,
794 qp_type, qp, true);
2446304d
EC		 795 if (err)
796 goto err;
797
0a1405da 798 if (qp_has_rq(init_attr)) {
8900b894 799 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 800 if (err)
801 goto err;
225c7b1f 802
02d89b87
RD		 803 *qp->db.db = 0;
804 }
225c7b1f 805
73898db0 806 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
8900b894 807 &qp->buf)) {
73898db0
HA		 808 memcpy(&init_attr->cap, &backup_cap,
809 sizeof(backup_cap));
810 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
811 qp, false);
812 if (err)
813 goto err_db;
814
815 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
8900b894 816 PAGE_SIZE * 2, &qp->buf)) {
73898db0
HA		 817 err = -ENOMEM;
818 goto err_db;
819 }
225c7b1f
RD		 820 }
821
822 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
823 &qp->mtt);
824 if (err)
825 goto err_buf;
826
8900b894 827 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 828 if (err)
829 goto err_mtt;
830
ee370950 831 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
8900b894 832 GFP_KERNEL | __GFP_NOWARN);
0ef2f05c
WW		 833 if (!qp->sq.wrid)
834 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
8900b894 835 GFP_KERNEL, PAGE_KERNEL);
ee370950 836 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
8900b894 837 GFP_KERNEL | __GFP_NOWARN);
0ef2f05c
WW		 838 if (!qp->rq.wrid)
839 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
8900b894 840 GFP_KERNEL, PAGE_KERNEL);
225c7b1f
RD		 841 if (!qp->sq.wrid || !qp->rq.wrid) {
842 err = -ENOMEM;
843 goto err_wrid;
844 }
f3301870 845 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 846 }
847
a3cdcbfa 848 if (sqpn) {
1ffeb2eb
JM		 849 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
850 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
851 if (alloc_proxy_bufs(pd->device, qp)) {
852 err = -ENOMEM;
853 goto err_wrid;
854 }
855 }
a3cdcbfa 856 } else {
ddae0349
EE		 857 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
858 * otherwise, the WQE BlueFlame setup flow wrongly causes
859 * VLAN insertion. */
3987a2d3 860 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 861 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 862 (init_attr->cap.max_send_wr ?
863 MLX4_RESERVE_ETH_BF_QP : 0) |
864 (init_attr->cap.max_recv_wr ?
f3301870
MS		 865 MLX4_RESERVE_A0_QP : 0),
866 qp->mqp.usage);
3987a2d3 867 else
c1c98501
MB		 868 if (qp->flags & MLX4_IB_QP_NETIF)
869 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
870 else
871 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 872 &qpn, 0, qp->mqp.usage);
a3cdcbfa 873 if (err)
1ffeb2eb 874 goto err_proxy;
a3cdcbfa
YP		 875 }
876
fbfb6625
EBE		 877 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
878 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
879
8900b894 880 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 881 if (err)
a3cdcbfa 882 goto err_qpn;
225c7b1f 883
0a1405da
SH		 884 if (init_attr->qp_type == IB_QPT_XRC_TGT)
885 qp->mqp.qpn |= (1 << 23);
886
225c7b1f
RD		 887 /*
888 * Hardware wants QPN written in big-endian order (after
889 * shifting) for send doorbell. Precompute this value to save
890 * a little bit when posting sends.
891 */
892 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
893
225c7b1f 894 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 895 if (!*caller_qp)
896 *caller_qp = qp;
35f05dab
YH		 897
898 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
899 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
900 to_mcq(init_attr->recv_cq));
901 /* Maintain device to QPs access, needed for further handling
902 * via reset flow
903 */
904 list_add_tail(&qp->qps_list, &dev->qp_list);
905 /* Maintain CQ to QPs access, needed for further handling
906 * via reset flow
907 */
908 mcq = to_mcq(init_attr->send_cq);
909 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
910 mcq = to_mcq(init_attr->recv_cq);
911 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
912 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
913 to_mcq(init_attr->recv_cq));
914 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 915 return 0;
916
a3cdcbfa 917err_qpn:
c1c98501
MB		 918 if (!sqpn) {
919 if (qp->flags & MLX4_IB_QP_NETIF)
920 mlx4_ib_steer_qp_free(dev, qpn, 1);
921 else
922 mlx4_qp_release_range(dev->dev, qpn, 1);
923 }
1ffeb2eb
JM		 924err_proxy:
925 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
926 free_proxy_bufs(pd->device, qp);
225c7b1f 927err_wrid:
23f1b384 928 if (pd->uobject) {
0a1405da
SH		 929 if (qp_has_rq(init_attr))
930 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 931 } else {
0ef2f05c
WW		 932 kvfree(qp->sq.wrid);
933 kvfree(qp->rq.wrid);
225c7b1f
RD		 934 }
935
936err_mtt:
937 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
938
939err_buf:
940 if (pd->uobject)
941 ib_umem_release(qp->umem);
942 else
943 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
944
945err_db:
0a1405da 946 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 947 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 948
949err:
b42dde47
BVA		 950 if (sqp)
951 kfree(sqp);
952 else if (!*caller_qp)
1ffeb2eb 953 kfree(qp);
225c7b1f
RD		 954 return err;
955}
956
957static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
958{
959 switch (state) {
960 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
961 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
962 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
963 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
964 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
965 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
966 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
967 default: return -1;
968 }
969}
970
971static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 972 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 973{
338a8fad 974 if (send_cq == recv_cq) {
35f05dab 975 spin_lock(&send_cq->lock);
338a8fad
RD		 976 __acquire(&recv_cq->lock);
977 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 978 spin_lock(&send_cq->lock);
225c7b1f
RD		 979 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
980 } else {
35f05dab 981 spin_lock(&recv_cq->lock);
225c7b1f
RD		 982 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
983 }
984}
985
986static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 987 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 988{
338a8fad
RD		 989 if (send_cq == recv_cq) {
990 __release(&recv_cq->lock);
35f05dab 991 spin_unlock(&send_cq->lock);
338a8fad 992 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 993 spin_unlock(&recv_cq->lock);
35f05dab 994 spin_unlock(&send_cq->lock);
225c7b1f
RD		 995 } else {
996 spin_unlock(&send_cq->lock);
35f05dab 997 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 998 }
999}
1000
fa417f7b
EC		 1001static void del_gid_entries(struct mlx4_ib_qp *qp)
1002{
1003 struct mlx4_ib_gid_entry *ge, *tmp;
1004
1005 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1006 list_del(&ge->list);
1007 kfree(ge);
1008 }
1009}
1010
0a1405da
SH		 1011static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1012{
1013 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1014 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1015 else
1016 return to_mpd(qp->ibqp.pd);
1017}
1018
1019static void get_cqs(struct mlx4_ib_qp *qp,
1020 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1021{
1022 switch (qp->ibqp.qp_type) {
1023 case IB_QPT_XRC_TGT:
1024 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1025 *recv_cq = *send_cq;
1026 break;
1027 case IB_QPT_XRC_INI:
1028 *send_cq = to_mcq(qp->ibqp.send_cq);
1029 *recv_cq = *send_cq;
1030 break;
1031 default:
1032 *send_cq = to_mcq(qp->ibqp.send_cq);
1033 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1034 break;
1035 }
1036}
1037
225c7b1f
RD		 1038static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1039 int is_user)
1040{
1041 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1042 unsigned long flags;
225c7b1f 1043
2f5bb473 1044 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1045 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1046 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1047 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1048 qp->mqp.qpn);
25476b02 1049 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1050 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1051 qp->pri.smac = 0;
25476b02 1052 qp->pri.smac_port = 0;
2f5bb473
JM		 1053 }
1054 if (qp->alt.smac) {
1055 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1056 qp->alt.smac = 0;
1057 }
1058 if (qp->pri.vid < 0x1000) {
1059 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1060 qp->pri.vid = 0xFFFF;
1061 qp->pri.candidate_vid = 0xFFFF;
1062 qp->pri.update_vid = 0;
1063 }
1064 if (qp->alt.vid < 0x1000) {
1065 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1066 qp->alt.vid = 0xFFFF;
1067 qp->alt.candidate_vid = 0xFFFF;
1068 qp->alt.update_vid = 0;
1069 }
1070 }
225c7b1f 1071
0a1405da 1072 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1073
35f05dab 1074 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1075 mlx4_ib_lock_cqs(send_cq, recv_cq);
1076
35f05dab
YH		 1077 /* del from lists under both locks above to protect reset flow paths */
1078 list_del(&qp->qps_list);
1079 list_del(&qp->cq_send_list);
1080 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1081 if (!is_user) {
1082 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1083 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1084 if (send_cq != recv_cq)
1085 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1086 }
1087
1088 mlx4_qp_remove(dev->dev, &qp->mqp);
1089
1090 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1091 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1092
1093 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1094
c1c98501
MB		 1095 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1096 if (qp->flags & MLX4_IB_QP_NETIF)
1097 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1098 else
1099 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1100 }
a3cdcbfa 1101
225c7b1f
RD		 1102 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1103
1104 if (is_user) {
0a1405da 1105 if (qp->rq.wqe_cnt)
02d89b87
RD		 1106 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1107 &qp->db);
225c7b1f
RD		 1108 ib_umem_release(qp->umem);
1109 } else {
0ef2f05c
WW		 1110 kvfree(qp->sq.wrid);
1111 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1112 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1113 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1114 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1115 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1116 if (qp->rq.wqe_cnt)
6296883c 1117 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1118 }
fa417f7b
EC		 1119
1120 del_gid_entries(qp);
225c7b1f
RD		 1121}
1122
47605df9
JM		 1123static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1124{
1125 /* Native or PPF */
1126 if (!mlx4_is_mfunc(dev->dev) ||
1127 (mlx4_is_master(dev->dev) &&
1128 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1129 return dev->dev->phys_caps.base_sqpn +
1130 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1131 attr->port_num - 1;
1132 }
1133 /* PF or VF -- creating proxies */
1134 if (attr->qp_type == IB_QPT_SMI)
1135 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1136 else
1137 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1138}
1139
e1b866c6
MS		 1140static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1141 struct ib_qp_init_attr *init_attr,
1142 struct ib_udata *udata)
225c7b1f 1143{
1ffeb2eb 1144 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1145 int err;
fbfb6625 1146 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1147 u16 xrcdn = 0;
225c7b1f 1148
521e575b 1149 /*
1ffeb2eb
JM		 1150 * We only support LSO, vendor flag1, and multicast loopback blocking,
1151 * and only for kernel UD QPs.
521e575b 1152 */
1ffeb2eb
JM		 1153 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1154 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1155 MLX4_IB_SRIOV_TUNNEL_QP |
1156 MLX4_IB_SRIOV_SQP |
40f2287b 1157 MLX4_IB_QP_NETIF |
8900b894 1158 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1159 return ERR_PTR(-EINVAL);
521e575b 1160
c1c98501
MB		 1161 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1162 if (init_attr->qp_type != IB_QPT_UD)
1163 return ERR_PTR(-EINVAL);
1164 }
1165
e1b866c6
MS		 1166 if (init_attr->create_flags) {
1167 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1168 return ERR_PTR(-EINVAL);
1169
1170 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1171 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1172 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1173 init_attr->qp_type != IB_QPT_UD) ||
1174 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1175 init_attr->qp_type > IB_QPT_GSI) ||
1176 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1177 init_attr->qp_type != IB_QPT_GSI))
1178 return ERR_PTR(-EINVAL);
1179 }
b846f25a 1180
225c7b1f 1181 switch (init_attr->qp_type) {
0a1405da
SH		 1182 case IB_QPT_XRC_TGT:
1183 pd = to_mxrcd(init_attr->xrcd)->pd;
1184 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1185 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1186 /* fall through */
1187 case IB_QPT_XRC_INI:
1188 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1189 return ERR_PTR(-ENOSYS);
1190 init_attr->recv_cq = init_attr->send_cq;
1191 /* fall through */
225c7b1f
RD		 1192 case IB_QPT_RC:
1193 case IB_QPT_UC:
3987a2d3 1194 case IB_QPT_RAW_PACKET:
8900b894 1195 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1196 if (!qp)
1197 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1198 qp->pri.vid = 0xFFFF;
1199 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1200 /* fall through */
1201 case IB_QPT_UD:
1202 {
1203 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
8900b894 1204 udata, 0, &qp);
5b420d9c
DB		 1205 if (err) {
1206 kfree(qp);
225c7b1f 1207 return ERR_PTR(err);
5b420d9c 1208 }
225c7b1f
RD		 1209
1210 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1211 qp->xrcdn = xrcdn;
225c7b1f
RD		 1212
1213 break;
1214 }
1215 case IB_QPT_SMI:
1216 case IB_QPT_GSI:
1217 {
e1b866c6
MS		 1218 int sqpn;
1219
225c7b1f 1220 /* Userspace is not allowed to create special QPs: */
0a1405da 1221 if (udata)
225c7b1f 1222 return ERR_PTR(-EINVAL);
e1b866c6 1223 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1224 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1225 1, 1, &sqpn, 0,
1226 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1227
1228 if (res)
1229 return ERR_PTR(res);
1230 } else {
1231 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1232 }
225c7b1f 1233
0a1405da 1234 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
8900b894 1235 sqpn, &qp);
1ffeb2eb 1236 if (err)
225c7b1f 1237 return ERR_PTR(err);
225c7b1f
RD		 1238
1239 qp->port = init_attr->port_num;
e1b866c6
MS		 1240 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1241 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1242 break;
1243 }
1244 default:
1245 /* Don't support raw QPs */
1246 return ERR_PTR(-EINVAL);
1247 }
1248
1249 return &qp->ibqp;
1250}
1251
e1b866c6
MS		 1252struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1253 struct ib_qp_init_attr *init_attr,
1254 struct ib_udata *udata) {
1255 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1256 struct ib_qp *ibqp;
1257 struct mlx4_ib_dev *dev = to_mdev(device);
1258
1259 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1260
1261 if (!IS_ERR(ibqp) &&
1262 (init_attr->qp_type == IB_QPT_GSI) &&
1263 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1264 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1265 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1266
1267 if (is_eth &&
1268 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1269 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1270 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1271
1272 if (IS_ERR(sqp->roce_v2_gsi)) {
1273 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1274 sqp->roce_v2_gsi = NULL;
1275 } else {
1276 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1277 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1278 }
1279
1280 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1281 }
1282 }
1283 return ibqp;
1284}
1285
1286static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1287{
1288 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1289 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1290 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1291
1292 if (is_qp0(dev, mqp))
1293 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1294
c482af64
JM		 1295 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1296 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1297 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1298 dev->qp1_proxy[mqp->port - 1] = NULL;
1299 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1300 }
1301
7b59f0f9
EBE		 1302 if (mqp->counter_index)
1303 mlx4_ib_free_qp_counter(dev, mqp);
1304
0a1405da
SH		 1305 pd = get_pd(mqp);
1306 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1307
1308 if (is_sqp(dev, mqp))
1309 kfree(to_msqp(mqp));
1310 else
1311 kfree(mqp);
1312
1313 return 0;
1314}
1315
e1b866c6
MS		 1316int mlx4_ib_destroy_qp(struct ib_qp *qp)
1317{
1318 struct mlx4_ib_qp *mqp = to_mqp(qp);
1319
1320 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1321 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1322
1323 if (sqp->roce_v2_gsi)
1324 ib_destroy_qp(sqp->roce_v2_gsi);
1325 }
1326
1327 return _mlx4_ib_destroy_qp(qp);
1328}
1329
1ffeb2eb 1330static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1331{
1332 switch (type) {
1ffeb2eb
JM		 1333 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1334 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1335 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1336 case MLX4_IB_QPT_XRC_INI:
1337 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1338 case MLX4_IB_QPT_SMI:
1339 case MLX4_IB_QPT_GSI:
1340 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1341
1342 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1343 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1344 MLX4_QP_ST_MLX : -1);
1345 case MLX4_IB_QPT_PROXY_SMI:
1346 case MLX4_IB_QPT_TUN_SMI:
1347 case MLX4_IB_QPT_PROXY_GSI:
1348 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1349 MLX4_QP_ST_UD : -1);
1350 default: return -1;
225c7b1f
RD		 1351 }
1352}
1353
65adfa91 1354static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1355 int attr_mask)
1356{
1357 u8 dest_rd_atomic;
1358 u32 access_flags;
1359 u32 hw_access_flags = 0;
1360
1361 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1362 dest_rd_atomic = attr->max_dest_rd_atomic;
1363 else
1364 dest_rd_atomic = qp->resp_depth;
1365
1366 if (attr_mask & IB_QP_ACCESS_FLAGS)
1367 access_flags = attr->qp_access_flags;
1368 else
1369 access_flags = qp->atomic_rd_en;
1370
1371 if (!dest_rd_atomic)
1372 access_flags &= IB_ACCESS_REMOTE_WRITE;
1373
1374 if (access_flags & IB_ACCESS_REMOTE_READ)
1375 hw_access_flags |= MLX4_QP_BIT_RRE;
1376 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1377 hw_access_flags |= MLX4_QP_BIT_RAE;
1378 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1379 hw_access_flags |= MLX4_QP_BIT_RWE;
1380
1381 return cpu_to_be32(hw_access_flags);
1382}
1383
65adfa91 1384static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1385 int attr_mask)
1386{
1387 if (attr_mask & IB_QP_PKEY_INDEX)
1388 sqp->pkey_index = attr->pkey_index;
1389 if (attr_mask & IB_QP_QKEY)
1390 sqp->qkey = attr->qkey;
1391 if (attr_mask & IB_QP_SQ_PSN)
1392 sqp->send_psn = attr->sq_psn;
1393}
1394
1395static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1396{
1397 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1398}
1399
90898850
DC		 1400static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1401 const struct rdma_ah_attr *ah,
297e0dad 1402 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1403 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1404{
4c3eb3ca 1405 int vidx;
297e0dad 1406 int smac_index;
2f5bb473 1407 int err;
297e0dad 1408
d8966fcd
DC		 1409 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1410 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1411 if (rdma_ah_get_static_rate(ah)) {
1412 path->static_rate = rdma_ah_get_static_rate(ah) +
1413 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1414 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1415 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1416 --path->static_rate;
1417 } else
1418 path->static_rate = 0;
225c7b1f 1419
d8966fcd
DC		 1420 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1421 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1422 int real_sgid_index =
1423 mlx4_ib_gid_index_to_real_index(dev, port,
1424 grh->sgid_index);
5070cd22
MS		 1425
1426 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1427 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1428 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1429 return -1;
1430 }
1431
1432 path->grh_mylmc |= 1 << 7;
5070cd22 1433 path->mgid_index = real_sgid_index;
d8966fcd 1434 path->hop_limit = grh->hop_limit;
225c7b1f 1435 path->tclass_flowlabel =
d8966fcd
DC		 1436 cpu_to_be32((grh->traffic_class << 20) |
1437 (grh->flow_label));
1438 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1439 }
1440
44c58487 1441 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1442 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1443 return -1;
1444
2f5bb473 1445 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1446 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1447
297e0dad 1448 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1449 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1450 if (smac_info->vid < 0x1000) {
1451 /* both valid vlan ids */
1452 if (smac_info->vid != vlan_tag) {
1453 /* different VIDs. unreg old and reg new */
1454 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1455 if (err)
1456 return err;
1457 smac_info->candidate_vid = vlan_tag;
1458 smac_info->candidate_vlan_index = vidx;
1459 smac_info->candidate_vlan_port = port;
1460 smac_info->update_vid = 1;
1461 path->vlan_index = vidx;
1462 } else {
1463 path->vlan_index = smac_info->vlan_index;
1464 }
1465 } else {
1466 /* no current vlan tag in qp */
1467 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1468 if (err)
1469 return err;
1470 smac_info->candidate_vid = vlan_tag;
1471 smac_info->candidate_vlan_index = vidx;
1472 smac_info->candidate_vlan_port = port;
1473 smac_info->update_vid = 1;
1474 path->vlan_index = vidx;
1475 }
297e0dad 1476 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1477 path->fl = 1 << 6;
1478 } else {
1479 /* have current vlan tag. unregister it at modify-qp success */
1480 if (smac_info->vid < 0x1000) {
1481 smac_info->candidate_vid = 0xFFFF;
1482 smac_info->update_vid = 1;
1483 }
4c3eb3ca 1484 }
2f5bb473
JM		 1485
1486 /* get smac_index for RoCE use.
1487 * If no smac was yet assigned, register one.
1488 * If one was already assigned, but the new mac differs,
1489 * unregister the old one and register the new one.
1490 */
25476b02
JM		 1491 if ((!smac_info->smac && !smac_info->smac_port) ||
1492 smac_info->smac != smac) {
2f5bb473
JM		 1493 /* register candidate now, unreg if needed, after success */
1494 smac_index = mlx4_register_mac(dev->dev, port, smac);
1495 if (smac_index >= 0) {
1496 smac_info->candidate_smac_index = smac_index;
1497 smac_info->candidate_smac = smac;
1498 smac_info->candidate_smac_port = port;
1499 } else {
1500 return -EINVAL;
1501 }
1502 } else {
1503 smac_index = smac_info->smac_index;
1504 }
44c58487 1505 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1506 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1507 /* put MAC table smac index for IBoE */
1508 path->grh_mylmc = (u8) (smac_index) | 0x80;
1509 } else {
4c3eb3ca 1510 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1511 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1512 }
fa417f7b 1513
225c7b1f
RD		 1514 return 0;
1515}
1516
297e0dad
MS		 1517static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1518 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1519 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1520 struct mlx4_qp_path *path, u8 port,
1521 u16 vlan_id, u8 *smac)
297e0dad
MS		 1522{
1523 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1524 mlx4_mac_to_u64(smac),
1525 vlan_id,
2f5bb473 1526 path, &mqp->pri, port);
297e0dad
MS		 1527}
1528
1529static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1530 const struct ib_qp_attr *qp,
1531 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1532 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1533 struct mlx4_qp_path *path, u8 port)
1534{
1535 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1536 0,
1537 0xffff,
2f5bb473 1538 path, &mqp->alt, port);
297e0dad
MS		 1539}
1540
fa417f7b
EC		 1541static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1542{
1543 struct mlx4_ib_gid_entry *ge, *tmp;
1544
1545 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1546 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1547 ge->added = 1;
1548 ge->port = qp->port;
1549 }
1550 }
1551}
1552
dbf727de
MB		 1553static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1554 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1555 struct mlx4_qp_context *context)
1556{
2f5bb473
JM		 1557 u64 u64_mac;
1558 int smac_index;
1559
3e0629cb 1560 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1561
1562 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1563 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1564 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1565 if (smac_index >= 0) {
1566 qp->pri.candidate_smac_index = smac_index;
1567 qp->pri.candidate_smac = u64_mac;
1568 qp->pri.candidate_smac_port = qp->port;
1569 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1570 } else {
1571 return -ENOENT;
1572 }
1573 }
1574 return 0;
1575}
1576
7b59f0f9
EBE		 1577static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1578{
1579 struct counter_index *new_counter_index;
1580 int err;
1581 u32 tmp_idx;
1582
1583 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1584 IB_LINK_LAYER_ETHERNET ||
1585 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1586 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1587 return 0;
1588
f3301870 1589 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1590 if (err)
1591 return err;
1592
1593 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1594 if (!new_counter_index) {
1595 mlx4_counter_free(dev->dev, tmp_idx);
1596 return -ENOMEM;
1597 }
1598
1599 new_counter_index->index = tmp_idx;
1600 new_counter_index->allocated = 1;
1601 qp->counter_index = new_counter_index;
1602
1603 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1604 list_add_tail(&new_counter_index->list,
1605 &dev->counters_table[qp->port - 1].counters_list);
1606 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1607
1608 return 0;
1609}
1610
3b5daf28
MS		 1611enum {
1612 MLX4_QPC_ROCE_MODE_1 = 0,
1613 MLX4_QPC_ROCE_MODE_2 = 2,
1614 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1615};
1616
1617static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1618{
1619 switch (gid_type) {
1620 case IB_GID_TYPE_ROCE:
1621 return MLX4_QPC_ROCE_MODE_1;
1622 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1623 return MLX4_QPC_ROCE_MODE_2;
1624 default:
1625 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1626 }
1627}
1628
65adfa91
MT		 1629static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1630 const struct ib_qp_attr *attr, int attr_mask,
1631 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1632{
1633 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1634 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1635 struct mlx4_ib_pd *pd;
1636 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1637 struct mlx4_qp_context *context;
1638 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1639 int sqd_event;
c1c98501 1640 int steer_qp = 0;
225c7b1f 1641 int err = -EINVAL;
3ba8e31d 1642 int counter_index;
225c7b1f 1643
3dec4878
JM		 1644 /* APM is not supported under RoCE */
1645 if (attr_mask & IB_QP_ALT_PATH &&
1646 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1647 IB_LINK_LAYER_ETHERNET)
1648 return -ENOTSUPP;
1649
225c7b1f
RD		 1650 context = kzalloc(sizeof *context, GFP_KERNEL);
1651 if (!context)
1652 return -ENOMEM;
1653
225c7b1f 1654 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1655 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1656
1657 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1658 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1659 else {
1660 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1661 switch (attr->path_mig_state) {
1662 case IB_MIG_MIGRATED:
1663 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1664 break;
1665 case IB_MIG_REARM:
1666 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1667 break;
1668 case IB_MIG_ARMED:
1669 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1670 break;
1671 }
1672 }
1673
ea30b966
MG		 1674 if (qp->inl_recv_sz)
1675 context->param3 |= cpu_to_be32(1 << 25);
1676
b832be1e 1677 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1678 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1679 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1680 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1681 else if (ibqp->qp_type == IB_QPT_UD) {
1682 if (qp->flags & MLX4_IB_QP_LSO)
1683 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1684 ilog2(dev->dev->caps.max_gso_sz);
1685 else
6e0d733d 1686 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1687 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1688 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1689 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1690 attr->path_mtu);
f5b40431 1691 goto out;
225c7b1f 1692 }
d1f2cd89
EC		 1693 context->mtu_msgmax = (attr->path_mtu << 5) |
1694 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1695 }
1696
0e6e7416
RD		 1697 if (qp->rq.wqe_cnt)
1698 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1699 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1700
0e6e7416
RD		 1701 if (qp->sq.wqe_cnt)
1702 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1703 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1704
7b59f0f9
EBE		 1705 if (new_state == IB_QPS_RESET && qp->counter_index)
1706 mlx4_ib_free_qp_counter(dev, qp);
1707
0a1405da 1708 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1709 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1710 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1711 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1712 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1713 }
0e6e7416 1714
225c7b1f 1715 if (qp->ibqp.uobject)
85743f1e
HN		 1716 context->usr_page = cpu_to_be32(
1717 mlx4_to_hw_uar_index(dev->dev,
1718 to_mucontext(ibqp->uobject->context)->uar.index));
225c7b1f 1719 else
85743f1e
HN		 1720 context->usr_page = cpu_to_be32(
1721 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 1722
1723 if (attr_mask & IB_QP_DEST_QPN)
1724 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1725
1726 if (attr_mask & IB_QP_PORT) {
1727 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1728 !(attr_mask & IB_QP_AV)) {
1729 mlx4_set_sched(&context->pri_path, attr->port_num);
1730 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1731 }
1732 }
1733
cfcde11c 1734 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1735 err = create_qp_lb_counter(dev, qp);
1736 if (err)
1737 goto out;
1738
3ba8e31d
EBE		 1739 counter_index =
1740 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1741 if (qp->counter_index)
1742 counter_index = qp->counter_index->index;
1743
3ba8e31d
EBE		 1744 if (counter_index != -1) {
1745 context->pri_path.counter_index = counter_index;
cfcde11c 1746 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1747 if (qp->counter_index) {
1748 context->pri_path.fl |=
1749 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1750 context->pri_path.vlan_control |=
1751 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1752 }
cfcde11c 1753 } else
47d8417f
EBE		 1754 context->pri_path.counter_index =
1755 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1756
1757 if (qp->flags & MLX4_IB_QP_NETIF) {
1758 mlx4_ib_steer_qp_reg(dev, qp, 1);
1759 steer_qp = 1;
1760 }
e1b866c6
MS		 1761
1762 if (ibqp->qp_type == IB_QPT_GSI) {
1763 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
1764 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
1765 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
1766
1767 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1768 }
cfcde11c
OG		 1769 }
1770
225c7b1f 1771 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1772 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1773 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1774 context->pri_path.pkey_index = attr->pkey_index;
1775 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1776 }
1777
225c7b1f 1778 if (attr_mask & IB_QP_AV) {
dbf727de
MB		 1779 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1780 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1781 union ib_gid gid;
bf08e884 1782 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
dbf727de
MB		 1783 u16 vlan = 0xffff;
1784 u8 smac[ETH_ALEN];
1785 int status = 0;
d8966fcd
DC		 1786 int is_eth =
1787 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1788 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 1789
d8966fcd
DC		 1790 if (is_eth) {
1791 int index =
1792 rdma_ah_read_grh(&attr->ah_attr)->sgid_index;
dbf727de
MB		 1793
1794 status = ib_get_cached_gid(ibqp->device, port_num,
1795 index, &gid, &gid_attr);
1796 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1797 status = -ENOENT;
1798 if (!status && gid_attr.ndev) {
1799 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1800 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1801 dev_put(gid_attr.ndev);
1802 }
1803 }
1804 if (status)
1805 goto out;
1806
2f5bb473 1807 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 1808 port_num, vlan, smac))
225c7b1f 1809 goto out;
225c7b1f
RD		 1810
1811 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1812 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 1813
1814 if (is_eth &&
1815 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1816 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1817
1818 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1819 err = -EINVAL;
1820 goto out;
1821 }
1822 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1823 }
1824
225c7b1f
RD		 1825 }
1826
1827 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1828 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1829 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1830 }
1831
1832 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1833 if (attr->alt_port_num == 0 ||
1834 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1835 goto out;
225c7b1f 1836
5ae2a7a8
RD		 1837 if (attr->alt_pkey_index >=
1838 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1839 goto out;
5ae2a7a8 1840
2f5bb473
JM		 1841 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1842 &context->alt_path,
297e0dad 1843 attr->alt_port_num))
f5b40431 1844 goto out;
225c7b1f
RD		 1845
1846 context->alt_path.pkey_index = attr->alt_pkey_index;
1847 context->alt_path.ackto = attr->alt_timeout << 3;
1848 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1849 }
1850
0a1405da
SH		 1851 pd = get_pd(qp);
1852 get_cqs(qp, &send_cq, &recv_cq);
1853 context->pd = cpu_to_be32(pd->pdn);
1854 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1855 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1856 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1857
95d04f07
RD		 1858 /* Set "fast registration enabled" for all kernel QPs */
1859 if (!qp->ibqp.uobject)
1860 context->params1 |= cpu_to_be32(1 << 11);
1861
57f01b53
JM		 1862 if (attr_mask & IB_QP_RNR_RETRY) {
1863 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1864 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1865 }
1866
225c7b1f
RD		 1867 if (attr_mask & IB_QP_RETRY_CNT) {
1868 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1869 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1870 }
1871
1872 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1873 if (attr->max_rd_atomic)
1874 context->params1 |=
1875 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1876 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1877 }
1878
1879 if (attr_mask & IB_QP_SQ_PSN)
1880 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1881
225c7b1f
RD		 1882 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1883 if (attr->max_dest_rd_atomic)
1884 context->params2 |=
1885 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1886 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1887 }
1888
1889 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1890 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1891 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1892 }
1893
1894 if (ibqp->srq)
1895 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1896
1897 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1898 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1899 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1900 }
1901 if (attr_mask & IB_QP_RQ_PSN)
1902 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1903
1ffeb2eb 1904 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1905 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1906 if (qp->mlx4_ib_qp_type &
1907 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1908 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1909 else {
1910 if (mlx4_is_mfunc(dev->dev) &&
1911 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1912 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1913 MLX4_RESERVED_QKEY_BASE) {
1914 pr_err("Cannot use reserved QKEY"
1915 " 0x%x (range 0xffff0000..0xffffffff"
1916 " is reserved)\n", attr->qkey);
1917 err = -EINVAL;
1918 goto out;
1919 }
1920 context->qkey = cpu_to_be32(attr->qkey);
1921 }
225c7b1f
RD		 1922 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1923 }
1924
1925 if (ibqp->srq)
1926 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1927
0a1405da 1928 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1929 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1930
1931 if (cur_state == IB_QPS_INIT &&
1932 new_state == IB_QPS_RTR &&
1933 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1934 ibqp->qp_type == IB_QPT_UD ||
1935 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1936 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1937 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1938 qp->mlx4_ib_qp_type &
1939 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1940 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1941 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1942 context->pri_path.fl = 0x80;
1943 } else {
1944 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1945 context->pri_path.fl = 0x80;
225c7b1f 1946 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1947 }
2f5bb473
JM		 1948 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1949 IB_LINK_LAYER_ETHERNET) {
1950 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1951 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1952 context->pri_path.feup = 1 << 7; /* don't fsm */
1953 /* handle smac_index */
1954 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1955 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1956 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 1957 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 1958 if (err) {
1959 err = -EINVAL;
1960 goto out;
1961 }
9433c188
MB		 1962 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1963 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1964 }
1965 }
225c7b1f
RD		 1966 }
1967
d2fce8a9 1968 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1969 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1970 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1971 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1972 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1973 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1974 context->srqn = cpu_to_be32(7 << 28);
1975 }
1976 }
3528f696 1977
297e0dad
MS		 1978 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1979 int is_eth = rdma_port_get_link_layer(
1980 &dev->ib_dev, qp->port) ==
1981 IB_LINK_LAYER_ETHERNET;
1982 if (is_eth) {
1983 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1984 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1985 }
1986 }
1987
1988
225c7b1f
RD		 1989 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1990 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1991 sqd_event = 1;
1992 else
1993 sqd_event = 0;
1994
d57f5f72 1995 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3b5daf28 1996 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 1997
c0be5fb5
EC		 1998 /*
1999 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2000 * ownership bits of the send queue are set and the SQ
2001 * headroom is stamped so that the hardware doesn't start
2002 * processing stale work requests.
c0be5fb5
EC		 2003 */
2004 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2005 struct mlx4_wqe_ctrl_seg *ctrl;
2006 int i;
2007
0e6e7416 2008 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2009 ctrl = get_send_wqe(qp, i);
2010 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553 2011 if (qp->sq_max_wqes_per_wr == 1)
224e92e0
BB		 2012 ctrl->qpn_vlan.fence_size =
2013 1 << (qp->sq.wqe_shift - 4);
0e6e7416 2014
ea54b10c 2015 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 2016 }
2017 }
2018
225c7b1f
RD		 2019 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2020 to_mlx4_state(new_state), context, optpar,
2021 sqd_event, &qp->mqp);
2022 if (err)
2023 goto out;
2024
2025 qp->state = new_state;
2026
2027 if (attr_mask & IB_QP_ACCESS_FLAGS)
2028 qp->atomic_rd_en = attr->qp_access_flags;
2029 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2030 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2031 if (attr_mask & IB_QP_PORT) {
225c7b1f 2032 qp->port = attr->port_num;
fa417f7b
EC		 2033 update_mcg_macs(dev, qp);
2034 }
225c7b1f
RD		 2035 if (attr_mask & IB_QP_ALT_PATH)
2036 qp->alt_port = attr->alt_port_num;
2037
2038 if (is_sqp(dev, qp))
2039 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2040
2041 /*
2042 * If we moved QP0 to RTR, bring the IB link up; if we moved
2043 * QP0 to RESET or ERROR, bring the link back down.
2044 */
2045 if (is_qp0(dev, qp)) {
2046 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2047 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2048 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2049 qp->port);
225c7b1f
RD		 2050
2051 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2052 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2053 mlx4_CLOSE_PORT(dev->dev, qp->port);
2054 }
2055
2056 /*
2057 * If we moved a kernel QP to RESET, clean up all old CQ
2058 * entries and reinitialize the QP.
2059 */
2f5bb473
JM		 2060 if (new_state == IB_QPS_RESET) {
2061 if (!ibqp->uobject) {
2062 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2063 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2064 if (send_cq != recv_cq)
2065 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2066
2067 qp->rq.head = 0;
2068 qp->rq.tail = 0;
2069 qp->sq.head = 0;
2070 qp->sq.tail = 0;
2071 qp->sq_next_wqe = 0;
2072 if (qp->rq.wqe_cnt)
2073 *qp->db.db = 0;
225c7b1f 2074
2f5bb473
JM		 2075 if (qp->flags & MLX4_IB_QP_NETIF)
2076 mlx4_ib_steer_qp_reg(dev, qp, 0);
2077 }
25476b02 2078 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2079 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2080 qp->pri.smac = 0;
25476b02 2081 qp->pri.smac_port = 0;
2f5bb473
JM		 2082 }
2083 if (qp->alt.smac) {
2084 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2085 qp->alt.smac = 0;
2086 }
2087 if (qp->pri.vid < 0x1000) {
2088 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2089 qp->pri.vid = 0xFFFF;
2090 qp->pri.candidate_vid = 0xFFFF;
2091 qp->pri.update_vid = 0;
2092 }
c1c98501 2093
2f5bb473
JM		 2094 if (qp->alt.vid < 0x1000) {
2095 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2096 qp->alt.vid = 0xFFFF;
2097 qp->alt.candidate_vid = 0xFFFF;
2098 qp->alt.update_vid = 0;
2099 }
225c7b1f 2100 }
225c7b1f 2101out:
7b59f0f9
EBE		 2102 if (err && qp->counter_index)
2103 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2104 if (err && steer_qp)
2105 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2106 kfree(context);
25476b02
JM		 2107 if (qp->pri.candidate_smac ||
2108 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2109 if (err) {
2110 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2111 } else {
25476b02 2112 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2113 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2114 qp->pri.smac = qp->pri.candidate_smac;
2115 qp->pri.smac_index = qp->pri.candidate_smac_index;
2116 qp->pri.smac_port = qp->pri.candidate_smac_port;
2117 }
2118 qp->pri.candidate_smac = 0;
2119 qp->pri.candidate_smac_index = 0;
2120 qp->pri.candidate_smac_port = 0;
2121 }
2122 if (qp->alt.candidate_smac) {
2123 if (err) {
2124 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2125 } else {
2126 if (qp->alt.smac)
2127 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2128 qp->alt.smac = qp->alt.candidate_smac;
2129 qp->alt.smac_index = qp->alt.candidate_smac_index;
2130 qp->alt.smac_port = qp->alt.candidate_smac_port;
2131 }
2132 qp->alt.candidate_smac = 0;
2133 qp->alt.candidate_smac_index = 0;
2134 qp->alt.candidate_smac_port = 0;
2135 }
2136
2137 if (qp->pri.update_vid) {
2138 if (err) {
2139 if (qp->pri.candidate_vid < 0x1000)
2140 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2141 qp->pri.candidate_vid);
2142 } else {
2143 if (qp->pri.vid < 0x1000)
2144 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2145 qp->pri.vid);
2146 qp->pri.vid = qp->pri.candidate_vid;
2147 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2148 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2149 }
2150 qp->pri.candidate_vid = 0xFFFF;
2151 qp->pri.update_vid = 0;
2152 }
2153
2154 if (qp->alt.update_vid) {
2155 if (err) {
2156 if (qp->alt.candidate_vid < 0x1000)
2157 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2158 qp->alt.candidate_vid);
2159 } else {
2160 if (qp->alt.vid < 0x1000)
2161 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2162 qp->alt.vid);
2163 qp->alt.vid = qp->alt.candidate_vid;
2164 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2165 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2166 }
2167 qp->alt.candidate_vid = 0xFFFF;
2168 qp->alt.update_vid = 0;
2169 }
2170
225c7b1f
RD		 2171 return err;
2172}
2173
e1b866c6
MS		 2174static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2175 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2176{
2177 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2178 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2179 enum ib_qp_state cur_state, new_state;
2180 int err = -EINVAL;
297e0dad 2181 int ll;
65adfa91
MT		 2182 mutex_lock(&qp->mutex);
2183
2184 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2185 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2186
297e0dad
MS		 2187 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2188 ll = IB_LINK_LAYER_UNSPECIFIED;
2189 } else {
2190 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2191 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2192 }
dd5f03be
MB		 2193
2194 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2195 attr_mask, ll)) {
b1d8eb5a
JM		 2196 pr_debug("qpn 0x%x: invalid attribute mask specified "
2197 "for transition %d to %d. qp_type %d,"
2198 " attr_mask 0x%x\n",
2199 ibqp->qp_num, cur_state, new_state,
2200 ibqp->qp_type, attr_mask);
65adfa91 2201 goto out;
b1d8eb5a 2202 }
65adfa91 2203
c6215745
MS		 2204 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2205 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2206 if ((ibqp->qp_type == IB_QPT_RC) ||
2207 (ibqp->qp_type == IB_QPT_UD) ||
2208 (ibqp->qp_type == IB_QPT_UC) ||
2209 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2210 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2211 attr->port_num = mlx4_ib_bond_next_port(dev);
2212 }
2213 } else {
2214 /* no sense in changing port_num
2215 * when ports are bonded */
2216 attr_mask &= ~IB_QP_PORT;
2217 }
2218 }
2219
65adfa91 2220 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2221 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2222 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2223 "for transition %d to %d. qp_type %d\n",
2224 ibqp->qp_num, attr->port_num, cur_state,
2225 new_state, ibqp->qp_type);
65adfa91
MT		 2226 goto out;
2227 }
2228
3987a2d3
OG		 2229 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2230 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2231 IB_LINK_LAYER_ETHERNET))
2232 goto out;
2233
5ae2a7a8
RD		 2234 if (attr_mask & IB_QP_PKEY_INDEX) {
2235 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2236 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2237 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2238 "for transition %d to %d. qp_type %d\n",
2239 ibqp->qp_num, attr->pkey_index, cur_state,
2240 new_state, ibqp->qp_type);
5ae2a7a8 2241 goto out;
b1d8eb5a 2242 }
5ae2a7a8
RD		 2243 }
2244
65adfa91
MT		 2245 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2246 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2247 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2248 "Transition %d to %d. qp_type %d\n",
2249 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2250 new_state, ibqp->qp_type);
65adfa91
MT		 2251 goto out;
2252 }
2253
2254 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2255 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2256 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2257 "Transition %d to %d. qp_type %d\n",
2258 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2259 new_state, ibqp->qp_type);
65adfa91
MT		 2260 goto out;
2261 }
2262
2263 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2264 err = 0;
2265 goto out;
2266 }
2267
65adfa91
MT		 2268 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2269
c6215745
MS		 2270 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2271 attr->port_num = 1;
2272
65adfa91
MT		 2273out:
2274 mutex_unlock(&qp->mutex);
2275 return err;
2276}
2277
e1b866c6
MS		 2278int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2279 int attr_mask, struct ib_udata *udata)
2280{
2281 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2282 int ret;
2283
2284 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2285
2286 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2287 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2288 int err = 0;
2289
2290 if (sqp->roce_v2_gsi)
2291 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2292 if (err)
2293 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2294 err);
2295 }
2296 return ret;
2297}
2298
99ec41d0
JM		 2299static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2300{
2301 int i;
2302 for (i = 0; i < dev->caps.num_ports; i++) {
2303 if (qpn == dev->caps.qp0_proxy[i] ||
2304 qpn == dev->caps.qp0_tunnel[i]) {
2305 *qkey = dev->caps.qp0_qkey[i];
2306 return 0;
2307 }
2308 }
2309 return -EINVAL;
2310}
2311
1ffeb2eb 2312static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2313 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2314 void *wqe, unsigned *mlx_seg_len)
2315{
2316 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2317 struct ib_device *ib_dev = &mdev->ib_dev;
2318 struct mlx4_wqe_mlx_seg *mlx = wqe;
2319 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2320 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2321 u16 pkey;
2322 u32 qkey;
2323 int send_size;
2324 int header_size;
2325 int spc;
2326 int i;
2327
e622f2f4 2328 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2329 return -EINVAL;
2330
2331 send_size = 0;
2332
e622f2f4
CH		 2333 for (i = 0; i < wr->wr.num_sge; ++i)
2334 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2335
2336 /* for proxy-qp0 sends, need to add in size of tunnel header */
2337 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2338 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2339 send_size += sizeof (struct mlx4_ib_tunnel_header);
2340
25f40220 2341 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2342
2343 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2344 sqp->ud_header.lrh.service_level =
2345 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2346 sqp->ud_header.lrh.destination_lid =
2347 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2348 sqp->ud_header.lrh.source_lid =
2349 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2350 }
2351
2352 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2353
2354 /* force loopback */
2355 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2356 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2357
2358 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2359 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2360 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2361 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2362 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2363 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2364 else
2365 sqp->ud_header.bth.destination_qpn =
47605df9 2366 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2367
2368 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2369 if (mlx4_is_master(mdev->dev)) {
2370 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2371 return -EINVAL;
2372 } else {
2373 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2374 return -EINVAL;
2375 }
1ffeb2eb
JM		 2376 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2377 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2378
2379 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2380 sqp->ud_header.immediate_present = 0;
2381
2382 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2383
2384 /*
2385 * Inline data segments may not cross a 64 byte boundary. If
2386 * our UD header is bigger than the space available up to the
2387 * next 64 byte boundary in the WQE, use two inline data
2388 * segments to hold the UD header.
2389 */
2390 spc = MLX4_INLINE_ALIGN -
2391 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2392 if (header_size <= spc) {
2393 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2394 memcpy(inl + 1, sqp->header_buf, header_size);
2395 i = 1;
2396 } else {
2397 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2398 memcpy(inl + 1, sqp->header_buf, spc);
2399
2400 inl = (void *) (inl + 1) + spc;
2401 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2402 /*
2403 * Need a barrier here to make sure all the data is
2404 * visible before the byte_count field is set.
2405 * Otherwise the HCA prefetcher could grab the 64-byte
2406 * chunk with this inline segment and get a valid (!=
2407 * 0xffffffff) byte count but stale data, and end up
2408 * generating a packet with bad headers.
2409 *
2410 * The first inline segment's byte_count field doesn't
2411 * need a barrier, because it comes after a
2412 * control/MLX segment and therefore is at an offset
2413 * of 16 mod 64.
2414 */
2415 wmb();
2416 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2417 i = 2;
2418 }
2419
2420 *mlx_seg_len =
2421 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2422 return 0;
2423}
2424
fd10ed8e
JM		 2425static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2426{
2427 union sl2vl_tbl_to_u64 tmp_vltab;
2428 u8 vl;
2429
2430 if (sl > 15)
2431 return 0xf;
2432 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2433 vl = tmp_vltab.sl8[sl >> 1];
2434 if (sl & 1)
2435 vl &= 0x0f;
2436 else
2437 vl >>= 4;
2438 return vl;
2439}
2440
a748d60d
TB		 2441static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2442 int index, union ib_gid *gid,
2443 enum ib_gid_type *gid_type)
2444{
2445 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2446 struct mlx4_port_gid_table *port_gid_table;
2447 unsigned long flags;
2448
2449 port_gid_table = &iboe->gids[port_num - 1];
2450 spin_lock_irqsave(&iboe->lock, flags);
2451 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2452 *gid_type = port_gid_table->gids[index].gid_type;
2453 spin_unlock_irqrestore(&iboe->lock, flags);
2454 if (!memcmp(gid, &zgid, sizeof(*gid)))
2455 return -ENOENT;
2456
2457 return 0;
2458}
2459
3ef967a4 2460#define MLX4_ROCEV2_QP1_SPORT 0xC000
e622f2f4 2461static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 2462 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2463{
a478868a 2464 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 2465 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 2466 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2467 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2468 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2469 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2470 union ib_gid sgid;
225c7b1f
RD		 2471 u16 pkey;
2472 int send_size;
2473 int header_size;
e61ef241 2474 int spc;
225c7b1f 2475 int i;
1ffeb2eb 2476 int err = 0;
57d88cff 2477 u16 vlan = 0xffff;
a29bec12
RD		 2478 bool is_eth;
2479 bool is_vlan = false;
2480 bool is_grh;
3ef967a4
MS		 2481 bool is_udp = false;
2482 int ip_version = 0;
225c7b1f
RD		 2483
2484 send_size = 0;
e622f2f4
CH		 2485 for (i = 0; i < wr->wr.num_sge; ++i)
2486 send_size += wr->wr.sg_list[i].length;
225c7b1f 2487
fa417f7b
EC		 2488 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2489 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2490 if (is_eth) {
a748d60d 2491 enum ib_gid_type gid_type;
1ffeb2eb
JM		 2492 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2493 /* When multi-function is enabled, the ib_core gid
2494 * indexes don't necessarily match the hw ones, so
2495 * we must use our own cache */
6ee51a4e
JM		 2496 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2497 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2498 ah->av.ib.gid_index, &sgid.raw[0]);
2499 if (err)
2500 return err;
1ffeb2eb 2501 } else {
a748d60d
TB		 2502 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
2503 ah->av.ib.gid_index,
2504 &sgid, &gid_type);
3ef967a4 2505 if (!err) {
a748d60d 2506 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 2507 if (is_udp) {
2508 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2509 ip_version = 4;
2510 else
2511 ip_version = 6;
2512 is_grh = false;
2513 }
2514 } else {
1ffeb2eb 2515 return err;
3ef967a4 2516 }
1ffeb2eb 2517 }
0e9855db 2518 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2519 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2520 is_vlan = 1;
2521 }
4c3eb3ca 2522 }
25f40220 2523 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 2524 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 2525 if (err)
2526 return err;
fa417f7b
EC		 2527
2528 if (!is_eth) {
2529 sqp->ud_header.lrh.service_level =
2530 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2531 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2532 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2533 }
225c7b1f 2534
3ef967a4 2535 if (is_grh || (ip_version == 6)) {
225c7b1f 2536 sqp->ud_header.grh.traffic_class =
fa417f7b 2537 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2538 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2539 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2540 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 2541 if (is_eth) {
6ee51a4e 2542 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 2543 } else {
2544 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2545 /* When multi-function is enabled, the ib_core gid
2546 * indexes don't necessarily match the hw ones, so
2547 * we must use our own cache
2548 */
2549 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 2550 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
2551 demux[sqp->qp.port - 1].
2552 subnet_prefix)));
baa0be70
JM		 2553 sqp->ud_header.grh.source_gid.global.interface_id =
2554 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2555 guid_cache[ah->av.ib.gid_index];
2556 } else {
2557 ib_get_cached_gid(ib_dev,
2558 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2559 ah->av.ib.gid_index,
2560 &sqp->ud_header.grh.source_gid, NULL);
2561 }
6ee51a4e 2562 }
225c7b1f 2563 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2564 ah->av.ib.dgid, 16);
225c7b1f
RD		 2565 }
2566
3ef967a4
MS		 2567 if (ip_version == 4) {
2568 sqp->ud_header.ip4.tos =
2569 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2570 sqp->ud_header.ip4.id = 0;
2571 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2572 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2573
2574 memcpy(&sqp->ud_header.ip4.saddr,
2575 sgid.raw + 12, 4);
2576 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2577 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2578 }
2579
2580 if (is_udp) {
2581 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2582 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2583 sqp->ud_header.udp.csum = 0;
2584 }
2585
225c7b1f 2586 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2587
2588 if (!is_eth) {
2589 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2590 (sqp->ud_header.lrh.destination_lid ==
2591 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2592 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2593 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2594 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2595 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2596 }
225c7b1f 2597
e622f2f4 2598 switch (wr->wr.opcode) {
225c7b1f
RD		 2599 case IB_WR_SEND:
2600 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2601 sqp->ud_header.immediate_present = 0;
2602 break;
2603 case IB_WR_SEND_WITH_IMM:
2604 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2605 sqp->ud_header.immediate_present = 1;
e622f2f4 2606 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 2607 break;
2608 default:
2609 return -EINVAL;
2610 }
2611
fa417f7b 2612 if (is_eth) {
6ee51a4e 2613 struct in6_addr in6;
3ef967a4 2614 u16 ether_type;
c0c1d3d7
OD		 2615 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2616
69ae5439 2617 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 2618 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2619
c0c1d3d7 2620 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 2621
1049f138 2622 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 2623 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 2624 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2625 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2626 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2627
3e0629cb 2628
fa417f7b
EC		 2629 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2630 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 2631 if (!is_vlan) {
3ef967a4 2632 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 2633 } else {
3ef967a4 2634 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 2635 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2636 }
fa417f7b 2637 } else {
fd10ed8e
JM		 2638 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
2639 sl_to_vl(to_mdev(ib_dev),
2640 sqp->ud_header.lrh.service_level,
2641 sqp->qp.port);
2642 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
2643 return -EINVAL;
fa417f7b
EC		 2644 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2645 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2646 }
e622f2f4 2647 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 2648 if (!sqp->qp.ibqp.qp_num)
2649 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2650 else
e622f2f4 2651 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 2652 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 2653 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 2654 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 2655 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2656 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 2657 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2658
2659 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2660
2661 if (0) {
987c8f8f 2662 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2663 for (i = 0; i < header_size / 4; ++i) {
2664 if (i % 8 == 0)
987c8f8f
SP		 2665 pr_err(" [%02x] ", i * 4);
2666 pr_cont(" %08x",
2667 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2668 if ((i + 1) % 8 == 0)
987c8f8f 2669 pr_cont("\n");
225c7b1f 2670 }
987c8f8f 2671 pr_err("\n");
225c7b1f
RD		 2672 }
2673
e61ef241
RD		 2674 /*
2675 * Inline data segments may not cross a 64 byte boundary. If
2676 * our UD header is bigger than the space available up to the
2677 * next 64 byte boundary in the WQE, use two inline data
2678 * segments to hold the UD header.
2679 */
2680 spc = MLX4_INLINE_ALIGN -
2681 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2682 if (header_size <= spc) {
2683 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2684 memcpy(inl + 1, sqp->header_buf, header_size);
2685 i = 1;
2686 } else {
2687 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2688 memcpy(inl + 1, sqp->header_buf, spc);
2689
2690 inl = (void *) (inl + 1) + spc;
2691 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2692 /*
2693 * Need a barrier here to make sure all the data is
2694 * visible before the byte_count field is set.
2695 * Otherwise the HCA prefetcher could grab the 64-byte
2696 * chunk with this inline segment and get a valid (!=
2697 * 0xffffffff) byte count but stale data, and end up
2698 * generating a packet with bad headers.
2699 *
2700 * The first inline segment's byte_count field doesn't
2701 * need a barrier, because it comes after a
2702 * control/MLX segment and therefore is at an offset
2703 * of 16 mod 64.
2704 */
2705 wmb();
2706 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2707 i = 2;
2708 }
225c7b1f 2709
f438000f
RD		 2710 *mlx_seg_len =
2711 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2712 return 0;
225c7b1f
RD		 2713}
2714
2715static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2716{
2717 unsigned cur;
2718 struct mlx4_ib_cq *cq;
2719
2720 cur = wq->head - wq->tail;
0e6e7416 2721 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2722 return 0;
2723
2724 cq = to_mcq(ib_cq);
2725 spin_lock(&cq->lock);
2726 cur = wq->head - wq->tail;
2727 spin_unlock(&cq->lock);
2728
0e6e7416 2729 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2730}
2731
95d04f07
RD		 2732static __be32 convert_access(int acc)
2733{
6ff63e19
SM		 2734 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2735 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2736 (acc & IB_ACCESS_REMOTE_WRITE ?
2737 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2738 (acc & IB_ACCESS_REMOTE_READ ?
2739 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2740 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2741 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2742}
2743
1b2cd0fc
SG		 2744static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2745 struct ib_reg_wr *wr)
2746{
2747 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2748
2749 fseg->flags = convert_access(wr->access);
2750 fseg->mem_key = cpu_to_be32(wr->key);
2751 fseg->buf_list = cpu_to_be64(mr->page_map);
2752 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2753 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2754 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2755 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2756 fseg->reserved[0] = 0;
2757 fseg->reserved[1] = 0;
2758}
2759
95d04f07
RD		 2760static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2761{
aee38fad
SM		 2762 memset(iseg, 0, sizeof(*iseg));
2763 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2764}
2765
0fbfa6a9
RD		 2766static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2767 u64 remote_addr, u32 rkey)
2768{
2769 rseg->raddr = cpu_to_be64(remote_addr);
2770 rseg->rkey = cpu_to_be32(rkey);
2771 rseg->reserved = 0;
2772}
2773
e622f2f4
CH		 2774static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2775 struct ib_atomic_wr *wr)
0fbfa6a9 2776{
e622f2f4
CH		 2777 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2778 aseg->swap_add = cpu_to_be64(wr->swap);
2779 aseg->compare = cpu_to_be64(wr->compare_add);
2780 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2781 aseg->swap_add = cpu_to_be64(wr->compare_add);
2782 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 2783 } else {
e622f2f4 2784 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 2785 aseg->compare = 0;
2786 }
2787
2788}
2789
6fa8f719 2790static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 2791 struct ib_atomic_wr *wr)
6fa8f719 2792{
e622f2f4
CH		 2793 aseg->swap_add = cpu_to_be64(wr->swap);
2794 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2795 aseg->compare = cpu_to_be64(wr->compare_add);
2796 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 2797}
2798
0fbfa6a9 2799static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2800 struct ib_ud_wr *wr)
0fbfa6a9 2801{
e622f2f4
CH		 2802 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2803 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2804 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2805 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2806 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2807}
2808
1ffeb2eb
JM		 2809static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2810 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2811 struct ib_ud_wr *wr,
97982f5a 2812 enum mlx4_ib_qp_type qpt)
1ffeb2eb 2813{
e622f2f4 2814 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 2815 struct mlx4_av sqp_av = {0};
2816 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2817
2818 /* force loopback */
2819 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2820 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2821 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2822 cpu_to_be32(0xf0000000);
2823
2824 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2825 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2826 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2827 else
2828 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2829 /* Use QKEY from the QP context, which is set by master */
2830 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2831}
2832
e622f2f4 2833static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 2834{
2835 struct mlx4_wqe_inline_seg *inl = wqe;
2836 struct mlx4_ib_tunnel_header hdr;
e622f2f4 2837 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2838 int spc;
2839 int i;
2840
2841 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 2842 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2843 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2844 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 2845 memcpy(hdr.mac, ah->av.eth.mac, 6);
2846 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2847
2848 spc = MLX4_INLINE_ALIGN -
2849 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2850 if (sizeof (hdr) <= spc) {
2851 memcpy(inl + 1, &hdr, sizeof (hdr));
2852 wmb();
2853 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2854 i = 1;
2855 } else {
2856 memcpy(inl + 1, &hdr, spc);
2857 wmb();
2858 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2859
2860 inl = (void *) (inl + 1) + spc;
2861 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2862 wmb();
2863 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2864 i = 2;
2865 }
2866
2867 *mlx_seg_len =
2868 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2869}
2870
6e694ea3
JM		 2871static void set_mlx_icrc_seg(void *dseg)
2872{
2873 u32 *t = dseg;
2874 struct mlx4_wqe_inline_seg *iseg = dseg;
2875
2876 t[1] = 0;
2877
2878 /*
2879 * Need a barrier here before writing the byte_count field to
2880 * make sure that all the data is visible before the
2881 * byte_count field is set. Otherwise, if the segment begins
2882 * a new cacheline, the HCA prefetcher could grab the 64-byte
2883 * chunk and get a valid (!= * 0xffffffff) byte count but
2884 * stale data, and end up sending the wrong data.
2885 */
2886 wmb();
2887
2888 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2889}
2890
2891static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2892{
d420d9e3
RD		 2893 dseg->lkey = cpu_to_be32(sg->lkey);
2894 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2895
2896 /*
2897 * Need a barrier here before writing the byte_count field to
2898 * make sure that all the data is visible before the
2899 * byte_count field is set. Otherwise, if the segment begins
2900 * a new cacheline, the HCA prefetcher could grab the 64-byte
2901 * chunk and get a valid (!= * 0xffffffff) byte count but
2902 * stale data, and end up sending the wrong data.
2903 */
2904 wmb();
2905
2906 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2907}
2908
2242fa4f
RD		 2909static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2910{
2911 dseg->byte_count = cpu_to_be32(sg->length);
2912 dseg->lkey = cpu_to_be32(sg->lkey);
2913 dseg->addr = cpu_to_be64(sg->addr);
2914}
2915
e622f2f4 2916static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 2917 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2918 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 2919{
e622f2f4 2920 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 2921
417608c2
EC		 2922 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2923 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2924
2925 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 2926 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 2927 return -EINVAL;
2928
e622f2f4 2929 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 2930
e622f2f4 2931 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 2932 *lso_seg_len = halign;
2933 return 0;
2934}
2935
95d04f07
RD		 2936static __be32 send_ieth(struct ib_send_wr *wr)
2937{
2938 switch (wr->opcode) {
2939 case IB_WR_SEND_WITH_IMM:
2940 case IB_WR_RDMA_WRITE_WITH_IMM:
2941 return wr->ex.imm_data;
2942
2943 case IB_WR_SEND_WITH_INV:
2944 return cpu_to_be32(wr->ex.invalidate_rkey);
2945
2946 default:
2947 return 0;
2948 }
2949}
2950
1ffeb2eb
JM		 2951static void add_zero_len_inline(void *wqe)
2952{
2953 struct mlx4_wqe_inline_seg *inl = wqe;
2954 memset(wqe, 0, 16);
2955 inl->byte_count = cpu_to_be32(1 << 31);
2956}
2957
225c7b1f
RD		 2958int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2959 struct ib_send_wr **bad_wr)
2960{
2961 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2962 void *wqe;
2963 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2964 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2965 unsigned long flags;
2966 int nreq;
2967 int err = 0;
ea54b10c
JM		 2968 unsigned ind;
2969 int uninitialized_var(stamp);
2970 int uninitialized_var(size);
a3d8e159 2971 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2972 __be32 dummy;
2973 __be32 *lso_wqe;
2974 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2975 __be32 blh;
225c7b1f 2976 int i;
35f05dab 2977 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2978
e1b866c6
MS		 2979 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2980 struct mlx4_ib_sqp *sqp = to_msqp(qp);
2981
2982 if (sqp->roce_v2_gsi) {
2983 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 2984 enum ib_gid_type gid_type;
e1b866c6
MS		 2985 union ib_gid gid;
2986
a748d60d
TB		 2987 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
2988 ah->av.ib.gid_index,
2989 &gid, &gid_type))
2990 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
2991 to_mqp(sqp->roce_v2_gsi) : qp;
2992 else
e1b866c6
MS		 2993 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
2994 ah->av.ib.gid_index);
e1b866c6
MS		 2995 }
2996 }
2997
96db0e03 2998 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2999 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3000 err = -EIO;
3001 *bad_wr = wr;
3002 nreq = 0;
3003 goto out;
3004 }
225c7b1f 3005
ea54b10c 3006 ind = qp->sq_next_wqe;
225c7b1f
RD		 3007
3008 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3009 lso_wqe = &dummy;
417608c2 3010 blh = 0;
0fd7e1d8 3011
225c7b1f
RD		 3012 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3013 err = -ENOMEM;
3014 *bad_wr = wr;
3015 goto out;
3016 }
3017
3018 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3019 err = -EINVAL;
3020 *bad_wr = wr;
3021 goto out;
3022 }
3023
0e6e7416 3024 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3025 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3026
3027 ctrl->srcrb_flags =
3028 (wr->send_flags & IB_SEND_SIGNALED ?
3029 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3030 (wr->send_flags & IB_SEND_SOLICITED ?
3031 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3032 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3033 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3034 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3035 qp->sq_signal_bits;
3036
95d04f07 3037 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3038
3039 wqe += sizeof *ctrl;
3040 size = sizeof *ctrl / 16;
3041
1ffeb2eb
JM		 3042 switch (qp->mlx4_ib_qp_type) {
3043 case MLX4_IB_QPT_RC:
3044 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3045 switch (wr->opcode) {
3046 case IB_WR_ATOMIC_CMP_AND_SWP:
3047 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3048 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3049 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3050 atomic_wr(wr)->rkey);
225c7b1f
RD		 3051 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3052
e622f2f4 3053 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3054 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3055
225c7b1f
RD		 3056 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3057 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3058
3059 break;
3060
3061 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3062 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3063 atomic_wr(wr)->rkey);
6fa8f719
VS		 3064 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3065
e622f2f4 3066 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3067 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3068
3069 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3070 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3071
3072 break;
3073
3074 case IB_WR_RDMA_READ:
3075 case IB_WR_RDMA_WRITE:
3076 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3077 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3078 rdma_wr(wr)->rkey);
225c7b1f
RD		 3079 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3080 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3081 break;
95d04f07
RD		 3082
3083 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3084 ctrl->srcrb_flags |=
3085 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3086 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3087 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3088 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3089 break;
3090
1b2cd0fc
SG		 3091 case IB_WR_REG_MR:
3092 ctrl->srcrb_flags |=
3093 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3094 set_reg_seg(wqe, reg_wr(wr));
3095 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3096 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3097 break;
3098
225c7b1f
RD		 3099 default:
3100 /* No extra segments required for sends */
3101 break;
3102 }
3103 break;
3104
1ffeb2eb 3105 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3106 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3107 ctrl, &seglen);
1ffeb2eb
JM		 3108 if (unlikely(err)) {
3109 *bad_wr = wr;
3110 goto out;
3111 }
3112 wqe += seglen;
3113 size += seglen / 16;
3114 break;
3115 case MLX4_IB_QPT_TUN_SMI:
3116 case MLX4_IB_QPT_TUN_GSI:
3117 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3118 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3119 /* set the forced-loopback bit in the data seg av */
3120 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3121 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3122 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3123 break;
3124 case MLX4_IB_QPT_UD:
e622f2f4 3125 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3126 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3127 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3128
3129 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3130 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3131 &lso_hdr_sz, &blh);
b832be1e
EC		 3132 if (unlikely(err)) {
3133 *bad_wr = wr;
3134 goto out;
3135 }
0fd7e1d8 3136 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3137 wqe += seglen;
3138 size += seglen / 16;
3139 }
225c7b1f
RD		 3140 break;
3141
1ffeb2eb 3142 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3143 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3144 ctrl, &seglen);
1ffeb2eb
JM		 3145 if (unlikely(err)) {
3146 *bad_wr = wr;
3147 goto out;
3148 }
3149 wqe += seglen;
3150 size += seglen / 16;
3151 /* to start tunnel header on a cache-line boundary */
3152 add_zero_len_inline(wqe);
3153 wqe += 16;
3154 size++;
e622f2f4 3155 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3156 wqe += seglen;
3157 size += seglen / 16;
3158 break;
3159 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3160 case MLX4_IB_QPT_PROXY_GSI:
3161 /* If we are tunneling special qps, this is a UD qp.
3162 * In this case we first add a UD segment targeting
3163 * the tunnel qp, and then add a header with address
3164 * information */
e622f2f4
CH		 3165 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3166 ud_wr(wr),
97982f5a 3167 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3168 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3169 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3170 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3171 wqe += seglen;
3172 size += seglen / 16;
3173 break;
3174
3175 case MLX4_IB_QPT_SMI:
3176 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3177 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3178 &seglen);
f438000f 3179 if (unlikely(err)) {
225c7b1f
RD		 3180 *bad_wr = wr;
3181 goto out;
3182 }
f438000f
RD		 3183 wqe += seglen;
3184 size += seglen / 16;
225c7b1f
RD		 3185 break;
3186
3187 default:
3188 break;
3189 }
3190
6e694ea3
JM		 3191 /*
3192 * Write data segments in reverse order, so as to
3193 * overwrite cacheline stamp last within each
3194 * cacheline. This avoids issues with WQE
3195 * prefetching.
3196 */
225c7b1f 3197
6e694ea3
JM		 3198 dseg = wqe;
3199 dseg += wr->num_sge - 1;
3200 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3201
3202 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3203 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3204 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3205 qp->mlx4_ib_qp_type &
3206 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3207 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3208 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3209 }
3210
6e694ea3
JM		 3211 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3212 set_data_seg(dseg, wr->sg_list + i);
3213
0fd7e1d8
RD		 3214 /*
3215 * Possibly overwrite stamping in cacheline with LSO
3216 * segment only after making sure all data segments
3217 * are written.
3218 */
3219 wmb();
3220 *lso_wqe = lso_hdr_sz;
3221
224e92e0
BB		 3222 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3223 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3224
3225 /*
3226 * Make sure descriptor is fully written before
3227 * setting ownership bit (because HW can start
3228 * executing as soon as we do).
3229 */
3230 wmb();
3231
59b0ed12 3232 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3233 *bad_wr = wr;
225c7b1f
RD		 3234 err = -EINVAL;
3235 goto out;
3236 }
3237
3238 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3239 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3240
ea54b10c
JM		 3241 stamp = ind + qp->sq_spare_wqes;
3242 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3243
0e6e7416
RD		 3244 /*
3245 * We can improve latency by not stamping the last
3246 * send queue WQE until after ringing the doorbell, so
3247 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3248 *
3249 * Same optimization applies to padding with NOP wqe
3250 * in case of WQE shrinking (used to prevent wrap-around
3251 * in the middle of WR).
0e6e7416 3252 */
ea54b10c
JM		 3253 if (wr->next) {
3254 stamp_send_wqe(qp, stamp, size * 16);
3255 ind = pad_wraparound(qp, ind);
3256 }
225c7b1f
RD		 3257 }
3258
3259out:
3260 if (likely(nreq)) {
3261 qp->sq.head += nreq;
3262
3263 /*
3264 * Make sure that descriptors are written before
3265 * doorbell record.
3266 */
3267 wmb();
3268
3269 writel(qp->doorbell_qpn,
3270 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3271
3272 /*
3273 * Make sure doorbells don't leak out of SQ spinlock
3274 * and reach the HCA out of order.
3275 */
3276 mmiowb();
0e6e7416 3277
ea54b10c
JM		 3278 stamp_send_wqe(qp, stamp, size * 16);
3279
3280 ind = pad_wraparound(qp, ind);
3281 qp->sq_next_wqe = ind;
225c7b1f
RD		 3282 }
3283
96db0e03 3284 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3285
3286 return err;
3287}
3288
3289int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3290 struct ib_recv_wr **bad_wr)
3291{
3292 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3293 struct mlx4_wqe_data_seg *scat;
3294 unsigned long flags;
3295 int err = 0;
3296 int nreq;
3297 int ind;
1ffeb2eb 3298 int max_gs;
225c7b1f 3299 int i;
35f05dab 3300 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3301
1ffeb2eb 3302 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3303 spin_lock_irqsave(&qp->rq.lock, flags);
3304
35f05dab
YH		 3305 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3306 err = -EIO;
3307 *bad_wr = wr;
3308 nreq = 0;
3309 goto out;
3310 }
3311
0e6e7416 3312 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3313
3314 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3315 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3316 err = -ENOMEM;
3317 *bad_wr = wr;
3318 goto out;
3319 }
3320
3321 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3322 err = -EINVAL;
3323 *bad_wr = wr;
3324 goto out;
3325 }
3326
3327 scat = get_recv_wqe(qp, ind);
3328
1ffeb2eb
JM		 3329 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3330 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3331 ib_dma_sync_single_for_device(ibqp->device,
3332 qp->sqp_proxy_rcv[ind].map,
3333 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3334 DMA_FROM_DEVICE);
3335 scat->byte_count =
3336 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3337 /* use dma lkey from upper layer entry */
3338 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3339 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3340 scat++;
3341 max_gs--;
3342 }
3343
2242fa4f
RD		 3344 for (i = 0; i < wr->num_sge; ++i)
3345 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3346
1ffeb2eb 3347 if (i < max_gs) {
225c7b1f
RD		 3348 scat[i].byte_count = 0;
3349 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3350 scat[i].addr = 0;
3351 }
3352
3353 qp->rq.wrid[ind] = wr->wr_id;
3354
0e6e7416 3355 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3356 }
3357
3358out:
3359 if (likely(nreq)) {
3360 qp->rq.head += nreq;
3361
3362 /*
3363 * Make sure that descriptors are written before
3364 * doorbell record.
3365 */
3366 wmb();
3367
3368 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3369 }
3370
3371 spin_unlock_irqrestore(&qp->rq.lock, flags);
3372
3373 return err;
3374}
6a775e2b
JM		 3375
3376static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3377{
3378 switch (mlx4_state) {
3379 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3380 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3381 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3382 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3383 case MLX4_QP_STATE_SQ_DRAINING:
3384 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3385 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3386 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3387 default: return -1;
3388 }
3389}
3390
3391static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3392{
3393 switch (mlx4_mig_state) {
3394 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3395 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3396 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3397 default: return -1;
3398 }
3399}
3400
3401static int to_ib_qp_access_flags(int mlx4_flags)
3402{
3403 int ib_flags = 0;
3404
3405 if (mlx4_flags & MLX4_QP_BIT_RRE)
3406 ib_flags |= IB_ACCESS_REMOTE_READ;
3407 if (mlx4_flags & MLX4_QP_BIT_RWE)
3408 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3409 if (mlx4_flags & MLX4_QP_BIT_RAE)
3410 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3411
3412 return ib_flags;
3413}
3414
71d53ab4 3415static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3416 struct rdma_ah_attr *ah_attr,
71d53ab4 3417 struct mlx4_qp_path *path)
6a775e2b 3418{
4c3eb3ca 3419 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3420 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 3421
d8966fcd 3422 memset(ah_attr, 0, sizeof(*ah_attr));
44c58487 3423 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
d8966fcd 3424 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b
JM		 3425 return;
3426
44c58487 3427 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 3428 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3429 ((path->sched_queue & 4) << 1));
4c3eb3ca 3430 else
d8966fcd 3431 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 3432 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 3433
d8966fcd
DC		 3434 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3435 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3436 rdma_ah_set_static_rate(ah_attr,
3437 path->static_rate ? path->static_rate - 5 : 0);
3438 if (path->grh_mylmc & (1 << 7)) {
3439 rdma_ah_set_grh(ah_attr, NULL,
3440 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3441 path->mgid_index,
3442 path->hop_limit,
3443 (be32_to_cpu(path->tclass_flowlabel)
3444 >> 20) & 0xff);
3445 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 3446 }
3447}
3448
3449int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3450 struct ib_qp_init_attr *qp_init_attr)
3451{
3452 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3453 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3454 struct mlx4_qp_context context;
3455 int mlx4_state;
0df67030
DB		 3456 int err = 0;
3457
3458 mutex_lock(&qp->mutex);
6a775e2b
JM		 3459
3460 if (qp->state == IB_QPS_RESET) {
3461 qp_attr->qp_state = IB_QPS_RESET;
3462 goto done;
3463 }
3464
3465 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3466 if (err) {
3467 err = -EINVAL;
3468 goto out;
3469 }
6a775e2b
JM		 3470
3471 mlx4_state = be32_to_cpu(context.flags) >> 28;
3472
0df67030
DB		 3473 qp->state = to_ib_qp_state(mlx4_state);
3474 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3475 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3476 qp_attr->path_mig_state =
3477 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3478 qp_attr->qkey = be32_to_cpu(context.qkey);
3479 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3480 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3481 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3482 qp_attr->qp_access_flags =
3483 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3484
3485 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 3486 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3487 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 3488 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 3489 qp_attr->alt_port_num =
3490 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 3491 }
3492
3493 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3494 if (qp_attr->qp_state == IB_QPS_INIT)
3495 qp_attr->port_num = qp->port;
3496 else
3497 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3498
3499 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3500 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3501
3502 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3503
3504 qp_attr->max_dest_rd_atomic =
3505 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3506 qp_attr->min_rnr_timer =
3507 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3508 qp_attr->timeout = context.pri_path.ackto >> 3;
3509 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3510 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3511 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3512
3513done:
3514 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3515 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3516 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3517
6a775e2b 3518 if (!ibqp->uobject) {
7f5eb9bb
RD		 3519 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3520 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3521 } else {
3522 qp_attr->cap.max_send_wr = 0;
3523 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3524 }
3525
7f5eb9bb
RD		 3526 /*
3527 * We don't support inline sends for kernel QPs (yet), and we
3528 * don't know what userspace's value should be.
3529 */
3530 qp_attr->cap.max_inline_data = 0;
3531
3532 qp_init_attr->cap = qp_attr->cap;
3533
521e575b
RL		 3534 qp_init_attr->create_flags = 0;
3535 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3536 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3537
3538 if (qp->flags & MLX4_IB_QP_LSO)
3539 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3540
c1c98501
MB		 3541 if (qp->flags & MLX4_IB_QP_NETIF)
3542 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3543
46db567d
DB		 3544 qp_init_attr->sq_sig_type =
3545 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3546 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3547
0df67030
DB		 3548out:
3549 mutex_unlock(&qp->mutex);
3550 return err;
6a775e2b
JM		 3551}
3552
Linux 6.x block layer and io_uring tree(s)