projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RDMA/mlx5: Delete not needed GSI QP signal QP type
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
89944450 44#include <rdma/uverbs_ioctl.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
9ce28a20 50#include <rdma/mlx4-abi.h>
225c7b1f 51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
89944450
SR		 56static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
57 struct ib_udata *udata);
35f05dab 58
225c7b1f
RD		 59enum {
60 MLX4_IB_ACK_REQ_FREQ = 8,
61};
62
63enum {
64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
66 MLX4_IB_LINK_TYPE_IB = 0,
67 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 68};
69
70enum {
71 /*
fa417f7b 72 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 73 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
74 * tag. (LRH would only use 8 bytes, so Ethernet is the
75 * biggest case)
225c7b1f 76 */
4c3eb3ca 77 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 78 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 79};
80
81struct mlx4_ib_sqp {
82 struct mlx4_ib_qp qp;
83 int pkey_index;
84 u32 qkey;
85 u32 send_psn;
86 struct ib_ud_header ud_header;
87 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 88 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 89};
90
83904132 91enum {
417608c2
EC		 92 MLX4_IB_MIN_SQ_STRIDE = 6,
93 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 94};
95
3987a2d3
OG		 96enum {
97 MLX4_RAW_QP_MTU = 7,
98 MLX4_RAW_QP_MSGMAX = 31,
99};
100
297e0dad
MS		 101#ifndef ETH_ALEN
102#define ETH_ALEN 6
103#endif
297e0dad 104
225c7b1f 105static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 106 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
107 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
108 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
109 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
110 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
111 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
112 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
113 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
114 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
115 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 116 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 117 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
118 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 119};
120
400b1ebc
GL		 121enum mlx4_ib_source_type {
122 MLX4_IB_QP_SRC = 0,
123 MLX4_IB_RWQ_SRC = 1,
124};
125
225c7b1f
RD		 126static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
127{
128 return container_of(mqp, struct mlx4_ib_sqp, qp);
129}
130
1ffeb2eb
JM		 131static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
132{
133 if (!mlx4_is_master(dev->dev))
134 return 0;
135
47605df9
JM		 136 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
137 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
138 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 139}
140
225c7b1f
RD		 141static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
142{
47605df9
JM		 143 int proxy_sqp = 0;
144 int real_sqp = 0;
145 int i;
146 /* PPF or Native -- real SQP */
147 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
148 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
149 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
150 if (real_sqp)
151 return 1;
152 /* VF or PF -- proxy SQP */
153 if (mlx4_is_mfunc(dev->dev)) {
154 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 155 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
156 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 157 proxy_sqp = 1;
158 break;
159 }
160 }
161 }
e1b866c6
MS		 162 if (proxy_sqp)
163 return 1;
164
165 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 166}
167
1ffeb2eb 168/* used for INIT/CLOSE port logic */
225c7b1f
RD		 169static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
170{
47605df9
JM		 171 int proxy_qp0 = 0;
172 int real_qp0 = 0;
173 int i;
174 /* PPF or Native -- real QP0 */
175 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
176 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
177 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
178 if (real_qp0)
179 return 1;
180 /* VF or PF -- proxy QP0 */
181 if (mlx4_is_mfunc(dev->dev)) {
182 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 183 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 184 proxy_qp0 = 1;
185 break;
186 }
187 }
188 }
189 return proxy_qp0;
225c7b1f
RD		 190}
191
192static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
193{
1c69fc2a 194 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 195}
196
197static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
198{
199 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
200}
201
202static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
203{
204 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
205}
206
0e6e7416
RD		 207/*
208 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
f95ccffc
JM		 209 * first four bytes of every 64 byte chunk with 0xffffffff, except for
210 * the very first chunk of the WQE.
0e6e7416 211 */
f95ccffc 212static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
0e6e7416 213{
d2ae16d5 214 __be32 *wqe;
0e6e7416 215 int i;
ea54b10c 216 int s;
ea54b10c 217 void *buf;
ea54b10c 218 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 219
f95ccffc
JM		 220 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
221 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
222 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
223 for (i = 64; i < s; i += 64) {
224 wqe = buf + i;
225 *wqe = cpu_to_be32(0xffffffff);
ea54b10c 226 }
0e6e7416
RD		 227}
228
225c7b1f
RD		 229static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
230{
231 struct ib_event event;
232 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
233
234 if (type == MLX4_EVENT_TYPE_PATH_MIG)
235 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
236
237 if (ibqp->event_handler) {
238 event.device = ibqp->device;
239 event.element.qp = ibqp;
240 switch (type) {
241 case MLX4_EVENT_TYPE_PATH_MIG:
242 event.event = IB_EVENT_PATH_MIG;
243 break;
244 case MLX4_EVENT_TYPE_COMM_EST:
245 event.event = IB_EVENT_COMM_EST;
246 break;
247 case MLX4_EVENT_TYPE_SQ_DRAINED:
248 event.event = IB_EVENT_SQ_DRAINED;
249 break;
250 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
251 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
252 break;
253 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
254 event.event = IB_EVENT_QP_FATAL;
255 break;
256 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
257 event.event = IB_EVENT_PATH_MIG_ERR;
258 break;
259 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
260 event.event = IB_EVENT_QP_REQ_ERR;
261 break;
262 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
263 event.event = IB_EVENT_QP_ACCESS_ERR;
264 break;
265 default:
987c8f8f 266 pr_warn("Unexpected event type %d "
225c7b1f
RD		 267 "on QP %06x\n", type, qp->qpn);
268 return;
269 }
270
271 ibqp->event_handler(&event, ibqp->qp_context);
272 }
273}
274
400b1ebc
GL		 275static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
276{
277 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
278 type, qp->qpn);
279}
280
1ffeb2eb 281static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 282{
283 /*
284 * UD WQEs must have a datagram segment.
285 * RC and UC WQEs might have a remote address segment.
286 * MLX WQEs need two extra inline data segments (for the UD
287 * header and space for the ICRC).
288 */
289 switch (type) {
1ffeb2eb 290 case MLX4_IB_QPT_UD:
225c7b1f 291 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 292 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 293 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 294 case MLX4_IB_QPT_PROXY_SMI_OWNER:
295 case MLX4_IB_QPT_PROXY_SMI:
296 case MLX4_IB_QPT_PROXY_GSI:
297 return sizeof (struct mlx4_wqe_ctrl_seg) +
298 sizeof (struct mlx4_wqe_datagram_seg) + 64;
299 case MLX4_IB_QPT_TUN_SMI_OWNER:
300 case MLX4_IB_QPT_TUN_GSI:
301 return sizeof (struct mlx4_wqe_ctrl_seg) +
302 sizeof (struct mlx4_wqe_datagram_seg);
303
304 case MLX4_IB_QPT_UC:
225c7b1f
RD		 305 return sizeof (struct mlx4_wqe_ctrl_seg) +
306 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 307 case MLX4_IB_QPT_RC:
225c7b1f 308 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 309 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 310 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 311 case MLX4_IB_QPT_SMI:
312 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 313 return sizeof (struct mlx4_wqe_ctrl_seg) +
314 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 315 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
316 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 317 sizeof (struct mlx4_wqe_inline_seg),
318 sizeof (struct mlx4_wqe_data_seg)) +
319 ALIGN(4 +
320 sizeof (struct mlx4_wqe_inline_seg),
321 sizeof (struct mlx4_wqe_data_seg));
322 default:
323 return sizeof (struct mlx4_wqe_ctrl_seg);
324 }
325}
326
2446304d 327static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
913df8c3 328 bool is_user, bool has_rq, struct mlx4_ib_qp *qp,
ea30b966 329 u32 inl_recv_sz)
225c7b1f 330{
2446304d 331 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 332 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
333 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 334 return -EINVAL;
335
0a1405da 336 if (!has_rq) {
ea30b966 337 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 338 return -EINVAL;
2446304d 339
0e6e7416 340 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 341 } else {
ea30b966
MG		 342 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
343 sizeof(struct mlx4_wqe_data_seg);
344 u32 wqe_size;
345
a4cd7ed8 346 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 347 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
348 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 349 return -EINVAL;
350
0e6e7416 351 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 352 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 353 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
354 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 355 }
2446304d 356
fc2d0044
SG		 357 /* leave userspace return values as they were, so as not to break ABI */
358 if (is_user) {
359 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
360 cap->max_recv_sge = qp->rq.max_gs;
361 } else {
362 cap->max_recv_wr = qp->rq.max_post =
363 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
364 cap->max_recv_sge = min(qp->rq.max_gs,
365 min(dev->dev->caps.max_sq_sg,
366 dev->dev->caps.max_rq_sg));
367 }
2446304d
EC		 368
369 return 0;
370}
371
372static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
f95ccffc 373 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 374{
ea54b10c
JM		 375 int s;
376
2446304d 377 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 378 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
379 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 380 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 381 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
382 return -EINVAL;
383
384 /*
385 * For MLX transport we need 2 extra S/G entries:
386 * one for the header and one for the checksum at the end
387 */
1ffeb2eb
JM		 388 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
389 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 390 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
391 return -EINVAL;
392
ea54b10c
JM		 393 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
394 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 395 send_wqe_overhead(type, qp->flags);
225c7b1f 396
cd155c1c
RD		 397 if (s > dev->dev->caps.max_sq_desc_sz)
398 return -EINVAL;
399
f95ccffc
JM		 400 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
401
0e6e7416 402 /*
f95ccffc
JM		 403 * We need to leave 2 KB + 1 WR of headroom in the SQ to
404 * allow HW to prefetch.
0e6e7416 405 */
350b4c8a 406 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
f95ccffc
JM		 407 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
408 qp->sq_spare_wqes);
409
410 qp->sq.max_gs =
411 (min(dev->dev->caps.max_sq_desc_sz,
412 (1 << qp->sq.wqe_shift)) -
413 send_wqe_overhead(type, qp->flags)) /
b832be1e 414 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 415
416 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
417 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 418 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
419 qp->rq.offset = 0;
0e6e7416 420 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 421 } else {
0e6e7416 422 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 423 qp->sq.offset = 0;
424 }
425
ea54b10c 426 cap->max_send_wr = qp->sq.max_post =
f95ccffc 427 qp->sq.wqe_cnt - qp->sq_spare_wqes;
cd155c1c
RD		 428 cap->max_send_sge = min(qp->sq.max_gs,
429 min(dev->dev->caps.max_sq_sg,
430 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 431 /* We don't support inline sends for kernel QPs (yet) */
432 cap->max_inline_data = 0;
225c7b1f
RD		 433
434 return 0;
435}
436
83904132
JM		 437static int set_user_sq_size(struct mlx4_ib_dev *dev,
438 struct mlx4_ib_qp *qp,
2446304d
EC		 439 struct mlx4_ib_create_qp *ucmd)
440{
83904132
JM		 441 /* Sanity check SQ size before proceeding */
442 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
443 ucmd->log_sq_stride >
444 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
445 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
446 return -EINVAL;
447
0e6e7416 448 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 449 qp->sq.wqe_shift = ucmd->log_sq_stride;
450
0e6e7416
RD		 451 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
452 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 453
454 return 0;
455}
456
1ffeb2eb
JM		 457static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
458{
459 int i;
460
461 qp->sqp_proxy_rcv =
6da2ec56
KC		 462 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
463 GFP_KERNEL);
1ffeb2eb
JM		 464 if (!qp->sqp_proxy_rcv)
465 return -ENOMEM;
466 for (i = 0; i < qp->rq.wqe_cnt; i++) {
467 qp->sqp_proxy_rcv[i].addr =
468 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
469 GFP_KERNEL);
470 if (!qp->sqp_proxy_rcv[i].addr)
471 goto err;
472 qp->sqp_proxy_rcv[i].map =
473 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
474 sizeof (struct mlx4_ib_proxy_sqp_hdr),
475 DMA_FROM_DEVICE);
cc47d369
SO		 476 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
477 kfree(qp->sqp_proxy_rcv[i].addr);
478 goto err;
479 }
1ffeb2eb
JM		 480 }
481 return 0;
482
483err:
484 while (i > 0) {
485 --i;
486 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
487 sizeof (struct mlx4_ib_proxy_sqp_hdr),
488 DMA_FROM_DEVICE);
489 kfree(qp->sqp_proxy_rcv[i].addr);
490 }
491 kfree(qp->sqp_proxy_rcv);
492 qp->sqp_proxy_rcv = NULL;
493 return -ENOMEM;
494}
495
496static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
497{
498 int i;
499
500 for (i = 0; i < qp->rq.wqe_cnt; i++) {
501 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
502 sizeof (struct mlx4_ib_proxy_sqp_hdr),
503 DMA_FROM_DEVICE);
504 kfree(qp->sqp_proxy_rcv[i].addr);
505 }
506 kfree(qp->sqp_proxy_rcv);
507}
508
913df8c3 509static bool qp_has_rq(struct ib_qp_init_attr *attr)
0a1405da
SH		 510{
511 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
913df8c3 512 return false;
0a1405da
SH		 513
514 return !attr->srq;
515}
516
99ec41d0
JM		 517static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
518{
519 int i;
520 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 521 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
522 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 523 }
524 return 0;
525}
526
7b59f0f9
EBE		 527static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
528 struct mlx4_ib_qp *qp)
529{
530 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
531 mlx4_counter_free(dev->dev, qp->counter_index->index);
532 list_del(&qp->counter_index->list);
533 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
534
535 kfree(qp->counter_index);
536 qp->counter_index = NULL;
537}
538
3078f5f1
GL		 539static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
540 struct ib_qp_init_attr *init_attr,
541 struct mlx4_ib_create_qp_rss *ucmd)
542{
543 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
544 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
545
546 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
547 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
548 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
549 MLX4_EN_RSS_KEY_SIZE);
550 } else {
551 pr_debug("RX Hash function is not supported\n");
552 return (-EOPNOTSUPP);
553 }
554
4d02ebd9
GL		 555 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
556 MLX4_IB_RX_HASH_DST_IPV4 |
557 MLX4_IB_RX_HASH_SRC_IPV6 |
558 MLX4_IB_RX_HASH_DST_IPV6 |
559 MLX4_IB_RX_HASH_SRC_PORT_TCP |
560 MLX4_IB_RX_HASH_DST_PORT_TCP |
561 MLX4_IB_RX_HASH_SRC_PORT_UDP |
4f9ca2d8
LR		 562 MLX4_IB_RX_HASH_DST_PORT_UDP |
563 MLX4_IB_RX_HASH_INNER)) {
4d02ebd9
GL		 564 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
565 ucmd->rx_hash_fields_mask);
566 return (-EOPNOTSUPP);
567 }
568
3078f5f1
GL		 569 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
570 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
571 rss_ctx->flags = MLX4_RSS_IPV4;
572 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
573 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
574 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
575 return (-EOPNOTSUPP);
576 }
577
578 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
579 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
580 rss_ctx->flags |= MLX4_RSS_IPV6;
581 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
582 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
583 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
584 return (-EOPNOTSUPP);
585 }
586
587 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
588 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
589 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
590 pr_debug("RX Hash fields_mask for UDP is not supported\n");
591 return (-EOPNOTSUPP);
592 }
593
4d02ebd9 594 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 595 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 596 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 597 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 598 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 599 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
600 return (-EOPNOTSUPP);
601 }
602 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
603 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
604 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
605 return (-EOPNOTSUPP);
606 }
607
608 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
609 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 610 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 611 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 612 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 613 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 614 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 615 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
616 return (-EOPNOTSUPP);
617 }
3078f5f1
GL		 618 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
619 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
620 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
621 return (-EOPNOTSUPP);
622 }
623
07d84f7b
GL		 624 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
625 if (dev->dev->caps.tunnel_offload_mode ==
626 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
627 /*
628 * Hash according to inner headers if exist, otherwise
629 * according to outer headers.
630 */
631 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
632 } else {
633 pr_debug("RSS Hash for inner headers isn't supported\n");
634 return (-EOPNOTSUPP);
635 }
636 }
637
3078f5f1
GL		 638 return 0;
639}
640
d7c0557a 641static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 642 struct ib_qp_init_attr *init_attr,
643 struct mlx4_ib_create_qp_rss *ucmd,
644 struct mlx4_ib_qp *qp)
645{
646 int qpn;
647 int err;
648
649 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
650
651 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
652 if (err)
653 return err;
654
655 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
656 if (err)
657 goto err_qpn;
658
659 mutex_init(&qp->mutex);
660
661 INIT_LIST_HEAD(&qp->gid_list);
662 INIT_LIST_HEAD(&qp->steering_rules);
663
c3f1ee29 664 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 665 qp->state = IB_QPS_RESET;
666
667 /* Set dummy send resources to be compatible with HV and PRM */
668 qp->sq_no_prefetch = 1;
669 qp->sq.wqe_cnt = 1;
670 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
671 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
672 qp->mtt = (to_mqp(
673 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
674
675 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
676 if (!qp->rss_ctx) {
677 err = -ENOMEM;
678 goto err_qp_alloc;
679 }
680
681 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
682 if (err)
683 goto err;
684
685 return 0;
686
687err:
688 kfree(qp->rss_ctx);
689
690err_qp_alloc:
691 mlx4_qp_remove(dev->dev, &qp->mqp);
692 mlx4_qp_free(dev->dev, &qp->mqp);
693
694err_qpn:
695 mlx4_qp_release_range(dev->dev, qpn, 1);
696 return err;
697}
698
699static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
700 struct ib_qp_init_attr *init_attr,
701 struct ib_udata *udata)
702{
703 struct mlx4_ib_qp *qp;
704 struct mlx4_ib_create_qp_rss ucmd = {};
705 size_t required_cmd_sz;
706 int err;
707
708 if (!udata) {
709 pr_debug("RSS QP with NULL udata\n");
710 return ERR_PTR(-EINVAL);
711 }
712
713 if (udata->outlen)
714 return ERR_PTR(-EOPNOTSUPP);
715
716 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
717 sizeof(ucmd.reserved1);
718 if (udata->inlen < required_cmd_sz) {
719 pr_debug("invalid inlen\n");
720 return ERR_PTR(-EINVAL);
721 }
722
723 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
724 pr_debug("copy failed\n");
725 return ERR_PTR(-EFAULT);
726 }
727
f9bfea99
GL		 728 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
729 return ERR_PTR(-EOPNOTSUPP);
730
3078f5f1
GL		 731 if (ucmd.comp_mask || ucmd.reserved1)
732 return ERR_PTR(-EOPNOTSUPP);
733
734 if (udata->inlen > sizeof(ucmd) &&
735 !ib_is_udata_cleared(udata, sizeof(ucmd),
736 udata->inlen - sizeof(ucmd))) {
737 pr_debug("inlen is not supported\n");
738 return ERR_PTR(-EOPNOTSUPP);
739 }
740
741 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
742 pr_debug("RSS QP with unsupported QP type %d\n",
743 init_attr->qp_type);
744 return ERR_PTR(-EOPNOTSUPP);
745 }
746
747 if (init_attr->create_flags) {
748 pr_debug("RSS QP doesn't support create flags\n");
749 return ERR_PTR(-EOPNOTSUPP);
750 }
751
752 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
753 pr_debug("RSS QP with unsupported send attributes\n");
754 return ERR_PTR(-EOPNOTSUPP);
755 }
756
757 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
758 if (!qp)
759 return ERR_PTR(-ENOMEM);
760
761 qp->pri.vid = 0xFFFF;
762 qp->alt.vid = 0xFFFF;
763
d7c0557a 764 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
3078f5f1
GL		 765 if (err) {
766 kfree(qp);
767 return ERR_PTR(err);
768 }
769
770 qp->ibqp.qp_num = qp->mqp.qpn;
771
772 return &qp->ibqp;
773}
774
400b1ebc
GL		 775/*
776 * This function allocates a WQN from a range which is consecutive and aligned
777 * to its size. In case the range is full, then it creates a new range and
778 * allocates WQN from it. The new range will be used for following allocations.
779 */
780static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
781 struct mlx4_ib_qp *qp, int range_size, int *wqn)
782{
783 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
784 struct mlx4_wqn_range *range;
785 int err = 0;
786
787 mutex_lock(&context->wqn_ranges_mutex);
788
789 range = list_first_entry_or_null(&context->wqn_ranges_list,
790 struct mlx4_wqn_range, list);
791
792 if (!range || (range->refcount == range->size) || range->dirty) {
793 range = kzalloc(sizeof(*range), GFP_KERNEL);
794 if (!range) {
795 err = -ENOMEM;
796 goto out;
797 }
798
799 err = mlx4_qp_reserve_range(dev->dev, range_size,
800 range_size, &range->base_wqn, 0,
801 qp->mqp.usage);
802 if (err) {
803 kfree(range);
804 goto out;
805 }
806
807 range->size = range_size;
808 list_add(&range->list, &context->wqn_ranges_list);
809 } else if (range_size != 1) {
810 /*
811 * Requesting a new range (>1) when last range is still open, is
812 * not valid.
813 */
814 err = -EINVAL;
815 goto out;
816 }
817
818 qp->wqn_range = range;
819
820 *wqn = range->base_wqn + range->refcount;
821
822 range->refcount++;
823
824out:
825 mutex_unlock(&context->wqn_ranges_mutex);
826
827 return err;
828}
829
830static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
831 struct mlx4_ib_qp *qp, bool dirty_release)
832{
833 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
834 struct mlx4_wqn_range *range;
835
836 mutex_lock(&context->wqn_ranges_mutex);
837
838 range = qp->wqn_range;
839
840 range->refcount--;
841 if (!range->refcount) {
842 mlx4_qp_release_range(dev->dev, range->base_wqn,
843 range->size);
844 list_del(&range->list);
845 kfree(range);
846 } else if (dirty_release) {
847 /*
848 * A range which one of its WQNs is destroyed, won't be able to be
849 * reused for further WQN allocations.
850 * The next created WQ will allocate a new range.
851 */
cf368beb 852 range->dirty = true;
400b1ebc
GL		 853 }
854
855 mutex_unlock(&context->wqn_ranges_mutex);
856}
857
089b645d
LR		 858static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
859 struct ib_udata *udata, struct mlx4_ib_qp *qp)
860{
861 struct mlx4_ib_dev *dev = to_mdev(pd->device);
862 int qpn;
863 int err;
864 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
865 udata, struct mlx4_ib_ucontext, ibucontext);
866 struct mlx4_ib_cq *mcq;
867 unsigned long flags;
868 int range_size;
869 struct mlx4_ib_create_wq wq;
870 size_t copy_len;
871 int shift;
872 int n;
873
874 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
875
876 mutex_init(&qp->mutex);
877 spin_lock_init(&qp->sq.lock);
878 spin_lock_init(&qp->rq.lock);
879 INIT_LIST_HEAD(&qp->gid_list);
880 INIT_LIST_HEAD(&qp->steering_rules);
881
882 qp->state = IB_QPS_RESET;
883
884 copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
885
886 if (ib_copy_from_udata(&wq, udata, copy_len)) {
887 err = -EFAULT;
888 goto err;
889 }
890
891 if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] ||
892 wq.reserved[2]) {
893 pr_debug("user command isn't supported\n");
894 err = -EOPNOTSUPP;
895 goto err;
896 }
897
898 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) {
899 pr_debug("WQN range size must be equal or smaller than %d\n",
900 dev->dev->caps.max_rss_tbl_sz);
901 err = -EOPNOTSUPP;
902 goto err;
903 }
904 range_size = 1 << wq.log_range_size;
905
906 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS)
907 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
908
913df8c3 909 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz);
089b645d
LR		 910 if (err)
911 goto err;
912
913 qp->sq_no_prefetch = 1;
914 qp->sq.wqe_cnt = 1;
915 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
916 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
917 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
918
c320e527 919 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0);
089b645d
LR		 920 if (IS_ERR(qp->umem)) {
921 err = PTR_ERR(qp->umem);
922 goto err;
923 }
924
089b645d
LR		 925 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
926 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
927
928 if (err)
929 goto err_buf;
930
931 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
932 if (err)
933 goto err_mtt;
934
935 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db);
936 if (err)
937 goto err_mtt;
938 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
939
940 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn);
941 if (err)
942 goto err_wrid;
943
944 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
945 if (err)
946 goto err_qpn;
947
948 /*
949 * Hardware wants QPN written in big-endian order (after
950 * shifting) for send doorbell. Precompute this value to save
951 * a little bit when posting sends.
952 */
953 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
954
955 qp->mqp.event = mlx4_ib_wq_event;
956
957 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
958 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
959 to_mcq(init_attr->recv_cq));
960 /* Maintain device to QPs access, needed for further handling
961 * via reset flow
962 */
963 list_add_tail(&qp->qps_list, &dev->qp_list);
964 /* Maintain CQ to QPs access, needed for further handling
965 * via reset flow
966 */
967 mcq = to_mcq(init_attr->send_cq);
968 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
969 mcq = to_mcq(init_attr->recv_cq);
970 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
971 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
972 to_mcq(init_attr->recv_cq));
973 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
974 return 0;
975
976err_qpn:
977 mlx4_ib_release_wqn(context, qp, 0);
978err_wrid:
979 mlx4_ib_db_unmap_user(context, &qp->db);
980
981err_mtt:
982 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
983err_buf:
984 ib_umem_release(qp->umem);
985err:
986 return err;
987}
988
989static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
8900b894
LR		 990 struct ib_udata *udata, int sqpn,
991 struct mlx4_ib_qp **caller_qp)
225c7b1f 992{
089b645d 993 struct mlx4_ib_dev *dev = to_mdev(pd->device);
a3cdcbfa 994 int qpn;
225c7b1f 995 int err;
b42dde47 996 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb 997 struct mlx4_ib_qp *qp;
89944450
SR		 998 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
999 udata, struct mlx4_ib_ucontext, ibucontext);
1ffeb2eb 1000 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 1001 struct mlx4_ib_cq *mcq;
1002 unsigned long flags;
1ffeb2eb
JM		 1003
1004 /* When tunneling special qps, we use a plain UD qp */
1005 if (sqpn) {
1006 if (mlx4_is_mfunc(dev->dev) &&
1007 (!mlx4_is_master(dev->dev) ||
1008 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
1009 if (init_attr->qp_type == IB_QPT_GSI)
1010 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 1011 else {
1012 if (mlx4_is_master(dev->dev) ||
1013 qp0_enabled_vf(dev->dev, sqpn))
1014 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
1015 else
1016 qp_type = MLX4_IB_QPT_PROXY_SMI;
1017 }
1ffeb2eb
JM		 1018 }
1019 qpn = sqpn;
1020 /* add extra sg entry for tunneling */
1021 init_attr->cap.max_recv_sge++;
1022 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
1023 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
1024 container_of(init_attr,
1025 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
1026 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
1027 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
1028 !mlx4_is_master(dev->dev))
1029 return -EINVAL;
1030 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1031 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 1032 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1033 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1034 tnl_init->port))
1ffeb2eb
JM		 1035 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1036 else
1037 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 1038 /* we are definitely in the PPF here, since we are creating
1039 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1040 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1041 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 1042 sqpn = qpn;
1043 }
1044
1045 if (!*caller_qp) {
1046 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1047 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1048 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 1049 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 1050 if (!sqp)
1051 return -ENOMEM;
1052 qp = &sqp->qp;
1053 } else {
8900b894 1054 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 1055 if (!qp)
1056 return -ENOMEM;
1057 }
089b645d
LR		 1058 qp->pri.vid = 0xFFFF;
1059 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1060 } else
1061 qp = *caller_qp;
1062
1063 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 1064
1065 mutex_init(&qp->mutex);
1066 spin_lock_init(&qp->sq.lock);
1067 spin_lock_init(&qp->rq.lock);
fa417f7b 1068 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1069 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f 1070
089b645d 1071 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1072 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1073 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1074
e00b64f7 1075 if (udata) {
089b645d 1076 struct mlx4_ib_create_qp ucmd;
400b1ebc 1077 size_t copy_len;
ed8637d3
GL		 1078 int shift;
1079 int n;
400b1ebc 1080
089b645d 1081 copy_len = sizeof(struct mlx4_ib_create_qp);
225c7b1f 1082
400b1ebc 1083 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1084 err = -EFAULT;
1085 goto err;
1086 }
1087
089b645d 1088 qp->inl_recv_sz = ucmd.inl_recv_sz;
0e6e7416 1089
6d06c9aa
GL		 1090 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1091 if (!(dev->dev->caps.flags &
1092 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1093 pr_debug("scatter FCS is unsupported\n");
1094 err = -EOPNOTSUPP;
1095 goto err;
1096 }
1097
1098 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1099 }
1100
e00b64f7 1101 err = set_rq_size(dev, &init_attr->cap, udata,
400b1ebc 1102 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1103 if (err)
1104 goto err;
1105
089b645d 1106 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
400b1ebc 1107
089b645d
LR		 1108 err = set_user_sq_size(dev, qp, &ucmd);
1109 if (err)
1110 goto err;
400b1ebc 1111
c320e527
MS		 1112 qp->umem =
1113 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0);
225c7b1f
RD		 1114 if (IS_ERR(qp->umem)) {
1115 err = PTR_ERR(qp->umem);
1116 goto err;
1117 }
1118
ed8637d3
GL		 1119 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1120 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1121
225c7b1f
RD		 1122 if (err)
1123 goto err_buf;
1124
1125 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1126 if (err)
1127 goto err_mtt;
1128
0a1405da 1129 if (qp_has_rq(init_attr)) {
089b645d 1130 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db);
02d89b87
RD		 1131 if (err)
1132 goto err_mtt;
1133 }
f3301870 1134 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1135 } else {
e00b64f7 1136 err = set_rq_size(dev, &init_attr->cap, udata,
ea30b966
MG		 1137 qp_has_rq(init_attr), qp, 0);
1138 if (err)
1139 goto err;
1140
0e6e7416
RD		 1141 qp->sq_no_prefetch = 0;
1142
b832be1e
EC		 1143 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1144 qp->flags |= MLX4_IB_QP_LSO;
1145
c1c98501
MB		 1146 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1147 if (dev->steering_support ==
1148 MLX4_STEERING_MODE_DEVICE_MANAGED)
1149 qp->flags |= MLX4_IB_QP_NETIF;
1150 else
1151 goto err;
1152 }
1153
f95ccffc 1154 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 1155 if (err)
1156 goto err;
1157
0a1405da 1158 if (qp_has_rq(init_attr)) {
8900b894 1159 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1160 if (err)
1161 goto err;
225c7b1f 1162
02d89b87
RD		 1163 *qp->db.db = 0;
1164 }
225c7b1f 1165
f95ccffc 1166 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
8900b894 1167 &qp->buf)) {
f95ccffc
JM		 1168 err = -ENOMEM;
1169 goto err_db;
225c7b1f
RD		 1170 }
1171
1172 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1173 &qp->mtt);
1174 if (err)
1175 goto err_buf;
1176
8900b894 1177 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1178 if (err)
1179 goto err_mtt;
1180
e9105cde
LD		 1181 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1182 sizeof(u64), GFP_KERNEL);
1183 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1184 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1185 if (!qp->sq.wrid || !qp->rq.wrid) {
1186 err = -ENOMEM;
1187 goto err_wrid;
1188 }
f3301870 1189 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1190 }
1191
a3cdcbfa 1192 if (sqpn) {
1ffeb2eb
JM		 1193 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1194 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1195 if (alloc_proxy_bufs(pd->device, qp)) {
1196 err = -ENOMEM;
1197 goto err_wrid;
1198 }
1199 }
a3cdcbfa 1200 } else {
ddae0349
EE		 1201 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1202 * otherwise, the WQE BlueFlame setup flow wrongly causes
1203 * VLAN insertion. */
3987a2d3 1204 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1205 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1206 (init_attr->cap.max_send_wr ?
1207 MLX4_RESERVE_ETH_BF_QP : 0) |
1208 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1209 MLX4_RESERVE_A0_QP : 0),
1210 qp->mqp.usage);
3987a2d3 1211 else
c1c98501
MB		 1212 if (qp->flags & MLX4_IB_QP_NETIF)
1213 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1214 else
1215 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1216 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1217 if (err)
1ffeb2eb 1218 goto err_proxy;
a3cdcbfa
YP		 1219 }
1220
fbfb6625
EBE		 1221 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1222 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1223
8900b894 1224 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1225 if (err)
a3cdcbfa 1226 goto err_qpn;
225c7b1f 1227
0a1405da
SH		 1228 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1229 qp->mqp.qpn |= (1 << 23);
1230
225c7b1f
RD		 1231 /*
1232 * Hardware wants QPN written in big-endian order (after
1233 * shifting) for send doorbell. Precompute this value to save
1234 * a little bit when posting sends.
1235 */
1236 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1237
089b645d 1238 qp->mqp.event = mlx4_ib_qp_event;
400b1ebc 1239
1ffeb2eb
JM		 1240 if (!*caller_qp)
1241 *caller_qp = qp;
35f05dab
YH		 1242
1243 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1244 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1245 to_mcq(init_attr->recv_cq));
1246 /* Maintain device to QPs access, needed for further handling
1247 * via reset flow
1248 */
1249 list_add_tail(&qp->qps_list, &dev->qp_list);
1250 /* Maintain CQ to QPs access, needed for further handling
1251 * via reset flow
1252 */
1253 mcq = to_mcq(init_attr->send_cq);
1254 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1255 mcq = to_mcq(init_attr->recv_cq);
1256 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1257 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1258 to_mcq(init_attr->recv_cq));
1259 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1260 return 0;
1261
a3cdcbfa 1262err_qpn:
c1c98501
MB		 1263 if (!sqpn) {
1264 if (qp->flags & MLX4_IB_QP_NETIF)
1265 mlx4_ib_steer_qp_free(dev, qpn, 1);
1266 else
1267 mlx4_qp_release_range(dev->dev, qpn, 1);
1268 }
1ffeb2eb
JM		 1269err_proxy:
1270 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1271 free_proxy_bufs(pd->device, qp);
225c7b1f 1272err_wrid:
e00b64f7 1273 if (udata) {
0a1405da 1274 if (qp_has_rq(init_attr))
89944450 1275 mlx4_ib_db_unmap_user(context, &qp->db);
23f1b384 1276 } else {
0ef2f05c
WW		 1277 kvfree(qp->sq.wrid);
1278 kvfree(qp->rq.wrid);
225c7b1f
RD		 1279 }
1280
1281err_mtt:
1282 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1283
1284err_buf:
836a0fbb 1285 if (!qp->umem)
225c7b1f 1286 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
836a0fbb 1287 ib_umem_release(qp->umem);
225c7b1f
RD		 1288
1289err_db:
e00b64f7 1290 if (!udata && qp_has_rq(init_attr))
6296883c 1291 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1292
1293err:
2dd8e44c 1294 if (!sqp && !*caller_qp)
1ffeb2eb 1295 kfree(qp);
2dd8e44c
YS		 1296 kfree(sqp);
1297
225c7b1f
RD		 1298 return err;
1299}
1300
1301static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1302{
1303 switch (state) {
1304 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1305 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1306 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1307 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1308 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1309 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1310 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1311 default: return -1;
1312 }
1313}
1314
1315static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1316 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1317{
338a8fad 1318 if (send_cq == recv_cq) {
35f05dab 1319 spin_lock(&send_cq->lock);
338a8fad
RD		 1320 __acquire(&recv_cq->lock);
1321 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1322 spin_lock(&send_cq->lock);
225c7b1f
RD		 1323 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1324 } else {
35f05dab 1325 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1326 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1327 }
1328}
1329
1330static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1331 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1332{
338a8fad
RD		 1333 if (send_cq == recv_cq) {
1334 __release(&recv_cq->lock);
35f05dab 1335 spin_unlock(&send_cq->lock);
338a8fad 1336 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1337 spin_unlock(&recv_cq->lock);
35f05dab 1338 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1339 } else {
1340 spin_unlock(&send_cq->lock);
35f05dab 1341 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1342 }
1343}
1344
fa417f7b
EC		 1345static void del_gid_entries(struct mlx4_ib_qp *qp)
1346{
1347 struct mlx4_ib_gid_entry *ge, *tmp;
1348
1349 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1350 list_del(&ge->list);
1351 kfree(ge);
1352 }
1353}
1354
0a1405da
SH		 1355static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1356{
1357 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1358 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1359 else
1360 return to_mpd(qp->ibqp.pd);
1361}
1362
400b1ebc 1363static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1364 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1365{
1366 switch (qp->ibqp.qp_type) {
1367 case IB_QPT_XRC_TGT:
1368 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1369 *recv_cq = *send_cq;
1370 break;
1371 case IB_QPT_XRC_INI:
1372 *send_cq = to_mcq(qp->ibqp.send_cq);
1373 *recv_cq = *send_cq;
1374 break;
1375 default:
400b1ebc
GL		 1376 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1377 to_mcq(qp->ibwq.cq);
1378 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1379 *recv_cq;
0a1405da
SH		 1380 break;
1381 }
1382}
1383
3078f5f1
GL		 1384static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1385{
1386 if (qp->state != IB_QPS_RESET) {
1387 int i;
1388
1389 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1390 i++) {
1391 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1392 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1393
1394 mutex_lock(&wq->mutex);
1395
1396 wq->rss_usecnt--;
1397
1398 mutex_unlock(&wq->mutex);
1399 }
1400
1401 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1402 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1403 pr_warn("modify QP %06x to RESET failed.\n",
1404 qp->mqp.qpn);
1405 }
1406
1407 mlx4_qp_remove(dev->dev, &qp->mqp);
1408 mlx4_qp_free(dev->dev, &qp->mqp);
1409 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1410 del_gid_entries(qp);
1411 kfree(qp->rss_ctx);
1412}
1413
225c7b1f 1414static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
bdeacabd
SR		 1415 enum mlx4_ib_source_type src,
1416 struct ib_udata *udata)
225c7b1f
RD		 1417{
1418 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1419 unsigned long flags;
225c7b1f 1420
2f5bb473 1421 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1422 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1423 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1424 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1425 qp->mqp.qpn);
25476b02 1426 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1427 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1428 qp->pri.smac = 0;
25476b02 1429 qp->pri.smac_port = 0;
2f5bb473
JM		 1430 }
1431 if (qp->alt.smac) {
1432 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1433 qp->alt.smac = 0;
1434 }
1435 if (qp->pri.vid < 0x1000) {
1436 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1437 qp->pri.vid = 0xFFFF;
1438 qp->pri.candidate_vid = 0xFFFF;
1439 qp->pri.update_vid = 0;
1440 }
1441 if (qp->alt.vid < 0x1000) {
1442 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1443 qp->alt.vid = 0xFFFF;
1444 qp->alt.candidate_vid = 0xFFFF;
1445 qp->alt.update_vid = 0;
1446 }
1447 }
225c7b1f 1448
400b1ebc 1449 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1450
35f05dab 1451 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1452 mlx4_ib_lock_cqs(send_cq, recv_cq);
1453
35f05dab
YH		 1454 /* del from lists under both locks above to protect reset flow paths */
1455 list_del(&qp->qps_list);
1456 list_del(&qp->cq_send_list);
1457 list_del(&qp->cq_recv_list);
bdeacabd 1458 if (!udata) {
225c7b1f
RD		 1459 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1460 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1461 if (send_cq != recv_cq)
1462 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1463 }
1464
1465 mlx4_qp_remove(dev->dev, &qp->mqp);
1466
1467 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1468 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1469
1470 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1471
c1c98501
MB		 1472 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1473 if (qp->flags & MLX4_IB_QP_NETIF)
1474 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc 1475 else if (src == MLX4_IB_RWQ_SRC)
bdeacabd
SR		 1476 mlx4_ib_release_wqn(
1477 rdma_udata_to_drv_context(
1478 udata,
1479 struct mlx4_ib_ucontext,
1480 ibucontext),
1481 qp, 1);
c1c98501
MB		 1482 else
1483 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1484 }
a3cdcbfa 1485
225c7b1f
RD		 1486 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1487
bdeacabd 1488 if (udata) {
400b1ebc 1489 if (qp->rq.wqe_cnt) {
bdeacabd
SR		 1490 struct mlx4_ib_ucontext *mcontext =
1491 rdma_udata_to_drv_context(
1492 udata,
1493 struct mlx4_ib_ucontext,
1494 ibucontext);
1495
400b1ebc
GL		 1496 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1497 }
225c7b1f 1498 } else {
0ef2f05c
WW		 1499 kvfree(qp->sq.wrid);
1500 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1501 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1502 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1503 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1504 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1505 if (qp->rq.wqe_cnt)
6296883c 1506 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1507 }
836a0fbb 1508 ib_umem_release(qp->umem);
fa417f7b
EC		 1509
1510 del_gid_entries(qp);
225c7b1f
RD		 1511}
1512
47605df9
JM		 1513static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1514{
1515 /* Native or PPF */
1516 if (!mlx4_is_mfunc(dev->dev) ||
1517 (mlx4_is_master(dev->dev) &&
1518 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1519 return dev->dev->phys_caps.base_sqpn +
1520 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1521 attr->port_num - 1;
1522 }
1523 /* PF or VF -- creating proxies */
1524 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1525 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1526 else
c73c8b1e 1527 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1528}
1529
e1b866c6
MS		 1530static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1531 struct ib_qp_init_attr *init_attr,
1532 struct ib_udata *udata)
225c7b1f 1533{
1ffeb2eb 1534 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1535 int err;
fbfb6625 1536 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1537 u16 xrcdn = 0;
225c7b1f 1538
3078f5f1
GL		 1539 if (init_attr->rwq_ind_tbl)
1540 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1541
521e575b 1542 /*
1ffeb2eb
JM		 1543 * We only support LSO, vendor flag1, and multicast loopback blocking,
1544 * and only for kernel UD QPs.
521e575b 1545 */
1ffeb2eb
JM		 1546 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1547 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1548 MLX4_IB_SRIOV_TUNNEL_QP |
1549 MLX4_IB_SRIOV_SQP |
40f2287b 1550 MLX4_IB_QP_NETIF |
8900b894 1551 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1552 return ERR_PTR(-EINVAL);
521e575b 1553
c1c98501
MB		 1554 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1555 if (init_attr->qp_type != IB_QPT_UD)
1556 return ERR_PTR(-EINVAL);
1557 }
1558
e1b866c6
MS		 1559 if (init_attr->create_flags) {
1560 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1561 return ERR_PTR(-EINVAL);
1562
1563 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1564 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1565 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1566 init_attr->qp_type != IB_QPT_UD) ||
1567 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1568 init_attr->qp_type > IB_QPT_GSI) ||
1569 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1570 init_attr->qp_type != IB_QPT_GSI))
1571 return ERR_PTR(-EINVAL);
1572 }
b846f25a 1573
225c7b1f 1574 switch (init_attr->qp_type) {
0a1405da
SH		 1575 case IB_QPT_XRC_TGT:
1576 pd = to_mxrcd(init_attr->xrcd)->pd;
1577 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1578 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
df561f66 1579 fallthrough;
0a1405da
SH		 1580 case IB_QPT_XRC_INI:
1581 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1582 return ERR_PTR(-ENOSYS);
1583 init_attr->recv_cq = init_attr->send_cq;
df561f66 1584 fallthrough;
225c7b1f
RD		 1585 case IB_QPT_RC:
1586 case IB_QPT_UC:
3987a2d3 1587 case IB_QPT_RAW_PACKET:
8900b894 1588 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1589 if (!qp)
1590 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1591 qp->pri.vid = 0xFFFF;
1592 qp->alt.vid = 0xFFFF;
df561f66 1593 fallthrough;
1ffeb2eb
JM		 1594 case IB_QPT_UD:
1595 {
089b645d 1596 err = create_qp_common(pd, init_attr, udata, 0, &qp);
5b420d9c
DB		 1597 if (err) {
1598 kfree(qp);
225c7b1f 1599 return ERR_PTR(err);
5b420d9c 1600 }
225c7b1f
RD		 1601
1602 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1603 qp->xrcdn = xrcdn;
225c7b1f
RD		 1604
1605 break;
1606 }
1607 case IB_QPT_SMI:
1608 case IB_QPT_GSI:
1609 {
e1b866c6
MS		 1610 int sqpn;
1611
225c7b1f 1612 /* Userspace is not allowed to create special QPs: */
0a1405da 1613 if (udata)
225c7b1f 1614 return ERR_PTR(-EINVAL);
e1b866c6 1615 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1616 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1617 1, 1, &sqpn, 0,
1618 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1619
1620 if (res)
1621 return ERR_PTR(res);
1622 } else {
1623 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1624 }
225c7b1f 1625
089b645d 1626 err = create_qp_common(pd, init_attr, udata, sqpn, &qp);
1ffeb2eb 1627 if (err)
225c7b1f 1628 return ERR_PTR(err);
225c7b1f
RD		 1629
1630 qp->port = init_attr->port_num;
e1b866c6
MS		 1631 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1632 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1633 break;
1634 }
1635 default:
1636 /* Don't support raw QPs */
bb8865f4 1637 return ERR_PTR(-EOPNOTSUPP);
225c7b1f
RD		 1638 }
1639
1640 return &qp->ibqp;
1641}
1642
e1b866c6
MS		 1643struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1644 struct ib_qp_init_attr *init_attr,
1645 struct ib_udata *udata) {
1646 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1647 struct ib_qp *ibqp;
1648 struct mlx4_ib_dev *dev = to_mdev(device);
1649
1650 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1651
1652 if (!IS_ERR(ibqp) &&
1653 (init_attr->qp_type == IB_QPT_GSI) &&
1654 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1655 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1656 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1657
1658 if (is_eth &&
1659 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1660 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1661 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1662
1663 if (IS_ERR(sqp->roce_v2_gsi)) {
1664 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1665 sqp->roce_v2_gsi = NULL;
1666 } else {
1667 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1668 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1669 }
1670
1671 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1672 }
1673 }
1674 return ibqp;
1675}
1676
bdeacabd 1677static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
225c7b1f
RD		 1678{
1679 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1680 struct mlx4_ib_qp *mqp = to_mqp(qp);
1681
1682 if (is_qp0(dev, mqp))
1683 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1684
c482af64
JM		 1685 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1686 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1687 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1688 dev->qp1_proxy[mqp->port - 1] = NULL;
1689 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1690 }
1691
7b59f0f9
EBE		 1692 if (mqp->counter_index)
1693 mlx4_ib_free_qp_counter(dev, mqp);
1694
3078f5f1
GL		 1695 if (qp->rwq_ind_tbl) {
1696 destroy_qp_rss(dev, mqp);
1697 } else {
bdeacabd 1698 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata);
3078f5f1 1699 }
225c7b1f
RD		 1700
1701 if (is_sqp(dev, mqp))
1702 kfree(to_msqp(mqp));
1703 else
1704 kfree(mqp);
1705
1706 return 0;
1707}
1708
c4367a26 1709int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
e1b866c6
MS		 1710{
1711 struct mlx4_ib_qp *mqp = to_mqp(qp);
1712
1713 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1714 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1715
1716 if (sqp->roce_v2_gsi)
1717 ib_destroy_qp(sqp->roce_v2_gsi);
1718 }
1719
bdeacabd 1720 return _mlx4_ib_destroy_qp(qp, udata);
e1b866c6
MS		 1721}
1722
1ffeb2eb 1723static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1724{
1725 switch (type) {
1ffeb2eb
JM		 1726 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1727 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1728 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1729 case MLX4_IB_QPT_XRC_INI:
1730 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1731 case MLX4_IB_QPT_SMI:
1732 case MLX4_IB_QPT_GSI:
1733 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1734
1735 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1736 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1737 MLX4_QP_ST_MLX : -1);
1738 case MLX4_IB_QPT_PROXY_SMI:
1739 case MLX4_IB_QPT_TUN_SMI:
1740 case MLX4_IB_QPT_PROXY_GSI:
1741 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1742 MLX4_QP_ST_UD : -1);
1743 default: return -1;
225c7b1f
RD		 1744 }
1745}
1746
65adfa91 1747static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1748 int attr_mask)
1749{
1750 u8 dest_rd_atomic;
1751 u32 access_flags;
1752 u32 hw_access_flags = 0;
1753
1754 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1755 dest_rd_atomic = attr->max_dest_rd_atomic;
1756 else
1757 dest_rd_atomic = qp->resp_depth;
1758
1759 if (attr_mask & IB_QP_ACCESS_FLAGS)
1760 access_flags = attr->qp_access_flags;
1761 else
1762 access_flags = qp->atomic_rd_en;
1763
1764 if (!dest_rd_atomic)
1765 access_flags &= IB_ACCESS_REMOTE_WRITE;
1766
1767 if (access_flags & IB_ACCESS_REMOTE_READ)
1768 hw_access_flags |= MLX4_QP_BIT_RRE;
1769 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1770 hw_access_flags |= MLX4_QP_BIT_RAE;
1771 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1772 hw_access_flags |= MLX4_QP_BIT_RWE;
1773
1774 return cpu_to_be32(hw_access_flags);
1775}
1776
65adfa91 1777static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1778 int attr_mask)
1779{
1780 if (attr_mask & IB_QP_PKEY_INDEX)
1781 sqp->pkey_index = attr->pkey_index;
1782 if (attr_mask & IB_QP_QKEY)
1783 sqp->qkey = attr->qkey;
1784 if (attr_mask & IB_QP_SQ_PSN)
1785 sqp->send_psn = attr->sq_psn;
1786}
1787
1788static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1789{
1790 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1791}
1792
90898850
DC		 1793static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1794 const struct rdma_ah_attr *ah,
297e0dad 1795 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1796 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1797{
4c3eb3ca 1798 int vidx;
297e0dad 1799 int smac_index;
2f5bb473 1800 int err;
297e0dad 1801
d8966fcd
DC		 1802 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1803 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1804 if (rdma_ah_get_static_rate(ah)) {
1805 path->static_rate = rdma_ah_get_static_rate(ah) +
1806 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1807 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1808 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1809 --path->static_rate;
1810 } else
1811 path->static_rate = 0;
225c7b1f 1812
d8966fcd
DC		 1813 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1814 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1815 int real_sgid_index =
7492052a 1816 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
5070cd22 1817
54a6d63f
DC		 1818 if (real_sgid_index < 0)
1819 return real_sgid_index;
5070cd22 1820 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1821 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1822 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1823 return -1;
1824 }
1825
1826 path->grh_mylmc |= 1 << 7;
5070cd22 1827 path->mgid_index = real_sgid_index;
d8966fcd 1828 path->hop_limit = grh->hop_limit;
225c7b1f 1829 path->tclass_flowlabel =
d8966fcd
DC		 1830 cpu_to_be32((grh->traffic_class << 20) |
1831 (grh->flow_label));
1832 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1833 }
1834
44c58487 1835 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1836 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1837 return -1;
1838
2f5bb473 1839 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1840 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1841
297e0dad 1842 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1843 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1844 if (smac_info->vid < 0x1000) {
1845 /* both valid vlan ids */
1846 if (smac_info->vid != vlan_tag) {
1847 /* different VIDs. unreg old and reg new */
1848 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1849 if (err)
1850 return err;
1851 smac_info->candidate_vid = vlan_tag;
1852 smac_info->candidate_vlan_index = vidx;
1853 smac_info->candidate_vlan_port = port;
1854 smac_info->update_vid = 1;
1855 path->vlan_index = vidx;
1856 } else {
1857 path->vlan_index = smac_info->vlan_index;
1858 }
1859 } else {
1860 /* no current vlan tag in qp */
1861 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1862 if (err)
1863 return err;
1864 smac_info->candidate_vid = vlan_tag;
1865 smac_info->candidate_vlan_index = vidx;
1866 smac_info->candidate_vlan_port = port;
1867 smac_info->update_vid = 1;
1868 path->vlan_index = vidx;
1869 }
297e0dad 1870 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1871 path->fl = 1 << 6;
1872 } else {
1873 /* have current vlan tag. unregister it at modify-qp success */
1874 if (smac_info->vid < 0x1000) {
1875 smac_info->candidate_vid = 0xFFFF;
1876 smac_info->update_vid = 1;
1877 }
4c3eb3ca 1878 }
2f5bb473
JM		 1879
1880 /* get smac_index for RoCE use.
1881 * If no smac was yet assigned, register one.
1882 * If one was already assigned, but the new mac differs,
1883 * unregister the old one and register the new one.
1884 */
25476b02
JM		 1885 if ((!smac_info->smac && !smac_info->smac_port) ||
1886 smac_info->smac != smac) {
2f5bb473
JM		 1887 /* register candidate now, unreg if needed, after success */
1888 smac_index = mlx4_register_mac(dev->dev, port, smac);
1889 if (smac_index >= 0) {
1890 smac_info->candidate_smac_index = smac_index;
1891 smac_info->candidate_smac = smac;
1892 smac_info->candidate_smac_port = port;
1893 } else {
1894 return -EINVAL;
1895 }
1896 } else {
1897 smac_index = smac_info->smac_index;
1898 }
44c58487 1899 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1900 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1901 /* put MAC table smac index for IBoE */
1902 path->grh_mylmc = (u8) (smac_index) | 0x80;
1903 } else {
4c3eb3ca 1904 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1905 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1906 }
fa417f7b 1907
225c7b1f
RD		 1908 return 0;
1909}
1910
297e0dad
MS		 1911static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1912 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1913 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1914 struct mlx4_qp_path *path, u8 port,
1915 u16 vlan_id, u8 *smac)
297e0dad
MS		 1916{
1917 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1918 mlx4_mac_to_u64(smac),
1919 vlan_id,
2f5bb473 1920 path, &mqp->pri, port);
297e0dad
MS		 1921}
1922
1923static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1924 const struct ib_qp_attr *qp,
1925 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1926 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1927 struct mlx4_qp_path *path, u8 port)
1928{
1929 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1930 0,
1931 0xffff,
2f5bb473 1932 path, &mqp->alt, port);
297e0dad
MS		 1933}
1934
fa417f7b
EC		 1935static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1936{
1937 struct mlx4_ib_gid_entry *ge, *tmp;
1938
1939 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1940 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1941 ge->added = 1;
1942 ge->port = qp->port;
1943 }
1944 }
1945}
1946
dbf727de
MB		 1947static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1948 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1949 struct mlx4_qp_context *context)
1950{
2f5bb473
JM		 1951 u64 u64_mac;
1952 int smac_index;
1953
3e0629cb 1954 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1955
1956 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1957 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1958 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1959 if (smac_index >= 0) {
1960 qp->pri.candidate_smac_index = smac_index;
1961 qp->pri.candidate_smac = u64_mac;
1962 qp->pri.candidate_smac_port = qp->port;
1963 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1964 } else {
1965 return -ENOENT;
1966 }
1967 }
1968 return 0;
1969}
1970
7b59f0f9
EBE		 1971static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1972{
1973 struct counter_index *new_counter_index;
1974 int err;
1975 u32 tmp_idx;
1976
1977 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1978 IB_LINK_LAYER_ETHERNET ||
1979 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1980 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1981 return 0;
1982
f3301870 1983 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1984 if (err)
1985 return err;
1986
1987 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1988 if (!new_counter_index) {
1989 mlx4_counter_free(dev->dev, tmp_idx);
1990 return -ENOMEM;
1991 }
1992
1993 new_counter_index->index = tmp_idx;
1994 new_counter_index->allocated = 1;
1995 qp->counter_index = new_counter_index;
1996
1997 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1998 list_add_tail(&new_counter_index->list,
1999 &dev->counters_table[qp->port - 1].counters_list);
2000 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2001
2002 return 0;
2003}
2004
3b5daf28
MS		 2005enum {
2006 MLX4_QPC_ROCE_MODE_1 = 0,
2007 MLX4_QPC_ROCE_MODE_2 = 2,
2008 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2009};
2010
2011static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2012{
2013 switch (gid_type) {
2014 case IB_GID_TYPE_ROCE:
2015 return MLX4_QPC_ROCE_MODE_1;
2016 case IB_GID_TYPE_ROCE_UDP_ENCAP:
2017 return MLX4_QPC_ROCE_MODE_2;
2018 default:
2019 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2020 }
2021}
2022
3078f5f1
GL		 2023/*
2024 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2025 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2026 */
89944450
SR		 2027static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num,
2028 struct ib_udata *udata)
3078f5f1 2029{
fba02e6c 2030 int err = 0;
3078f5f1 2031 int i;
3078f5f1
GL		 2032
2033 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2034 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2035 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2036
2037 mutex_lock(&wq->mutex);
2038
2039 /* Mlx4_ib restrictions:
2040 * WQ's is associated to a port according to the RSS QP it is
2041 * associates to.
2042 * In case the WQ is associated to a different port by another
2043 * RSS QP, return a failure.
2044 */
2045 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2046 err = -EINVAL;
2047 mutex_unlock(&wq->mutex);
2048 break;
2049 }
2050 wq->port = port_num;
2051 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
89944450 2052 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata);
3078f5f1
GL		 2053 if (err) {
2054 mutex_unlock(&wq->mutex);
2055 break;
2056 }
2057 }
2058 wq->rss_usecnt++;
2059
2060 mutex_unlock(&wq->mutex);
2061 }
2062
2063 if (i && err) {
2064 int j;
2065
2066 for (j = (i - 1); j >= 0; j--) {
2067 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2068 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2069
2070 mutex_lock(&wq->mutex);
2071
2072 if ((wq->rss_usecnt == 1) &&
2073 (ibwq->state == IB_WQS_RDY))
89944450
SR		 2074 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET,
2075 udata))
3078f5f1
GL		 2076 pr_warn("failed to reverse WQN=0x%06x\n",
2077 ibwq->wq_num);
2078 wq->rss_usecnt--;
2079
2080 mutex_unlock(&wq->mutex);
2081 }
2082 }
2083
2084 return err;
2085}
2086
89944450
SR		 2087static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl,
2088 struct ib_udata *udata)
3078f5f1
GL		 2089{
2090 int i;
2091
2092 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2093 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2094 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2095
2096 mutex_lock(&wq->mutex);
2097
2098 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
89944450 2099 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata))
3078f5f1
GL		 2100 pr_warn("failed to reverse WQN=%x\n",
2101 ibwq->wq_num);
2102 wq->rss_usecnt--;
2103
2104 mutex_unlock(&wq->mutex);
2105 }
2106}
2107
2108static void fill_qp_rss_context(struct mlx4_qp_context *context,
2109 struct mlx4_ib_qp *qp)
2110{
2111 struct mlx4_rss_context *rss_context;
2112
2113 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2114 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2115
2116 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2117 rss_context->default_qpn =
2118 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2119 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2120 rss_context->base_qpn_udp = rss_context->default_qpn;
2121 rss_context->flags = qp->rss_ctx->flags;
2122 /* Currently support just toeplitz */
2123 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2124
2125 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2126 MLX4_EN_RSS_KEY_SIZE);
2127}
2128
400b1ebc 2129static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91 2130 const struct ib_qp_attr *attr, int attr_mask,
89944450
SR		 2131 enum ib_qp_state cur_state,
2132 enum ib_qp_state new_state,
2133 struct ib_udata *udata)
225c7b1f 2134{
400b1ebc 2135 struct ib_srq *ibsrq;
47ec3866 2136 const struct ib_gid_attr *gid_attr = NULL;
3078f5f1 2137 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2138 enum ib_qp_type qp_type;
2139 struct mlx4_ib_dev *dev;
2140 struct mlx4_ib_qp *qp;
0a1405da
SH		 2141 struct mlx4_ib_pd *pd;
2142 struct mlx4_ib_cq *send_cq, *recv_cq;
89944450
SR		 2143 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2144 udata, struct mlx4_ib_ucontext, ibucontext);
225c7b1f
RD		 2145 struct mlx4_qp_context *context;
2146 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2147 int sqd_event;
c1c98501 2148 int steer_qp = 0;
225c7b1f 2149 int err = -EINVAL;
3ba8e31d 2150 int counter_index;
225c7b1f 2151
400b1ebc
GL		 2152 if (src_type == MLX4_IB_RWQ_SRC) {
2153 struct ib_wq *ibwq;
2154
3078f5f1 2155 ibwq = (struct ib_wq *)src;
3078f5f1
GL		 2156 ibsrq = NULL;
2157 rwq_ind_tbl = NULL;
2158 qp_type = IB_QPT_RAW_PACKET;
2159 qp = to_mqp((struct ib_qp *)ibwq);
2160 dev = to_mdev(ibwq->device);
2161 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2162 } else {
2163 struct ib_qp *ibqp;
2164
3078f5f1 2165 ibqp = (struct ib_qp *)src;
3078f5f1
GL		 2166 ibsrq = ibqp->srq;
2167 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2168 qp_type = ibqp->qp_type;
2169 qp = to_mqp(ibqp);
2170 dev = to_mdev(ibqp->device);
2171 pd = get_pd(qp);
400b1ebc
GL		 2172 }
2173
3dec4878
JM		 2174 /* APM is not supported under RoCE */
2175 if (attr_mask & IB_QP_ALT_PATH &&
2176 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2177 IB_LINK_LAYER_ETHERNET)
2178 return -ENOTSUPP;
2179
225c7b1f
RD		 2180 context = kzalloc(sizeof *context, GFP_KERNEL);
2181 if (!context)
2182 return -ENOMEM;
2183
225c7b1f 2184 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2185 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2186
2187 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2188 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2189 else {
2190 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2191 switch (attr->path_mig_state) {
2192 case IB_MIG_MIGRATED:
2193 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2194 break;
2195 case IB_MIG_REARM:
2196 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2197 break;
2198 case IB_MIG_ARMED:
2199 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2200 break;
2201 }
2202 }
2203
ea30b966
MG		 2204 if (qp->inl_recv_sz)
2205 context->param3 |= cpu_to_be32(1 << 25);
2206
6d06c9aa
GL		 2207 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2208 context->param3 |= cpu_to_be32(1 << 29);
2209
400b1ebc 2210 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2211 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2212 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2213 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2214 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2215 if (qp->flags & MLX4_IB_QP_LSO)
2216 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2217 ilog2(dev->dev->caps.max_gso_sz);
2218 else
5f22a1d8 2219 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2220 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2221 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2222 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2223 attr->path_mtu);
f5b40431 2224 goto out;
225c7b1f 2225 }
d1f2cd89
EC		 2226 context->mtu_msgmax = (attr->path_mtu << 5) |
2227 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2228 }
2229
3078f5f1
GL		 2230 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2231 if (qp->rq.wqe_cnt)
2232 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2233 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2234 }
225c7b1f 2235
0e6e7416
RD		 2236 if (qp->sq.wqe_cnt)
2237 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2238 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2239
7b59f0f9
EBE		 2240 if (new_state == IB_QPS_RESET && qp->counter_index)
2241 mlx4_ib_free_qp_counter(dev, qp);
2242
0a1405da 2243 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2244 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2245 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2246 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2247 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2248 }
0e6e7416 2249
89944450 2250 if (ucontext)
85743f1e 2251 context->usr_page = cpu_to_be32(
89944450 2252 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index));
225c7b1f 2253 else
85743f1e
HN		 2254 context->usr_page = cpu_to_be32(
2255 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2256
2257 if (attr_mask & IB_QP_DEST_QPN)
2258 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2259
2260 if (attr_mask & IB_QP_PORT) {
2261 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2262 !(attr_mask & IB_QP_AV)) {
2263 mlx4_set_sched(&context->pri_path, attr->port_num);
2264 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2265 }
2266 }
2267
cfcde11c 2268 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2269 err = create_qp_lb_counter(dev, qp);
2270 if (err)
2271 goto out;
2272
3ba8e31d
EBE		 2273 counter_index =
2274 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2275 if (qp->counter_index)
2276 counter_index = qp->counter_index->index;
2277
3ba8e31d
EBE		 2278 if (counter_index != -1) {
2279 context->pri_path.counter_index = counter_index;
cfcde11c 2280 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2281 if (qp->counter_index) {
2282 context->pri_path.fl |=
2283 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2284 context->pri_path.vlan_control |=
2285 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2286 }
cfcde11c 2287 } else
47d8417f
EBE		 2288 context->pri_path.counter_index =
2289 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2290
2291 if (qp->flags & MLX4_IB_QP_NETIF) {
2292 mlx4_ib_steer_qp_reg(dev, qp, 1);
2293 steer_qp = 1;
2294 }
e1b866c6 2295
400b1ebc 2296 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2297 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2298 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2299 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2300
2301 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2302 }
cfcde11c
OG		 2303 }
2304
225c7b1f 2305 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2306 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2307 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2308 context->pri_path.pkey_index = attr->pkey_index;
2309 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2310 }
2311
225c7b1f 2312 if (attr_mask & IB_QP_AV) {
400b1ebc 2313 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de 2314 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
dbf727de
MB		 2315 u16 vlan = 0xffff;
2316 u8 smac[ETH_ALEN];
d8966fcd
DC		 2317 int is_eth =
2318 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2319 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2320
d8966fcd 2321 if (is_eth) {
47ec3866 2322 gid_attr = attr->ah_attr.grh.sgid_attr;
a70c0739
PP		 2323 err = rdma_read_gid_l2_fields(gid_attr, &vlan,
2324 &smac[0]);
2325 if (err)
2326 goto out;
dbf727de 2327 }
dbf727de 2328
2f5bb473 2329 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2330 port_num, vlan, smac))
225c7b1f 2331 goto out;
225c7b1f
RD		 2332
2333 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2334 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2335
2336 if (is_eth &&
2337 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
47ec3866 2338 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
3b5daf28
MS		 2339
2340 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2341 err = -EINVAL;
2342 goto out;
2343 }
2344 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2345 }
2346
225c7b1f
RD		 2347 }
2348
2349 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2350 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2351 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2352 }
2353
2354 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2355 if (attr->alt_port_num == 0 ||
2356 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2357 goto out;
225c7b1f 2358
5ae2a7a8
RD		 2359 if (attr->alt_pkey_index >=
2360 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2361 goto out;
5ae2a7a8 2362
2f5bb473
JM		 2363 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2364 &context->alt_path,
297e0dad 2365 attr->alt_port_num))
f5b40431 2366 goto out;
225c7b1f
RD		 2367
2368 context->alt_path.pkey_index = attr->alt_pkey_index;
2369 context->alt_path.ackto = attr->alt_timeout << 3;
2370 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2371 }
2372
3078f5f1
GL		 2373 context->pd = cpu_to_be32(pd->pdn);
2374
2375 if (!rwq_ind_tbl) {
108809a0 2376 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2377 get_cqs(qp, src_type, &send_cq, &recv_cq);
2378 } else { /* Set dummy CQs to be compatible with HV and PRM */
2379 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2380 recv_cq = send_cq;
2381 }
0a1405da
SH		 2382 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2383 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2384
95d04f07 2385 /* Set "fast registration enabled" for all kernel QPs */
89944450 2386 if (!ucontext)
95d04f07
RD		 2387 context->params1 |= cpu_to_be32(1 << 11);
2388
57f01b53
JM		 2389 if (attr_mask & IB_QP_RNR_RETRY) {
2390 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2391 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2392 }
2393
225c7b1f
RD		 2394 if (attr_mask & IB_QP_RETRY_CNT) {
2395 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2396 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2397 }
2398
2399 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2400 if (attr->max_rd_atomic)
2401 context->params1 |=
2402 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2403 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2404 }
2405
2406 if (attr_mask & IB_QP_SQ_PSN)
2407 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2408
225c7b1f
RD		 2409 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2410 if (attr->max_dest_rd_atomic)
2411 context->params2 |=
2412 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2413 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2414 }
2415
2416 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2417 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2418 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2419 }
2420
400b1ebc 2421 if (ibsrq)
225c7b1f
RD		 2422 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2423
2424 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2425 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2426 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2427 }
2428 if (attr_mask & IB_QP_RQ_PSN)
2429 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2430
1ffeb2eb 2431 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2432 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2433 if (qp->mlx4_ib_qp_type &
2434 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2435 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2436 else {
2437 if (mlx4_is_mfunc(dev->dev) &&
2438 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2439 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2440 MLX4_RESERVED_QKEY_BASE) {
2441 pr_err("Cannot use reserved QKEY"
2442 " 0x%x (range 0xffff0000..0xffffffff"
2443 " is reserved)\n", attr->qkey);
2444 err = -EINVAL;
2445 goto out;
2446 }
2447 context->qkey = cpu_to_be32(attr->qkey);
2448 }
225c7b1f
RD		 2449 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2450 }
2451
400b1ebc
GL		 2452 if (ibsrq)
2453 context->srqn = cpu_to_be32(1 << 24 |
2454 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2455
400b1ebc
GL		 2456 if (qp->rq.wqe_cnt &&
2457 cur_state == IB_QPS_RESET &&
2458 new_state == IB_QPS_INIT)
225c7b1f
RD		 2459 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2460
2461 if (cur_state == IB_QPS_INIT &&
2462 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2463 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2464 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2465 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2466 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2467 qp->mlx4_ib_qp_type &
2468 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2469 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2470 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2471 context->pri_path.fl = 0x80;
2472 } else {
2473 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2474 context->pri_path.fl = 0x80;
225c7b1f 2475 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2476 }
2f5bb473
JM		 2477 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2478 IB_LINK_LAYER_ETHERNET) {
2479 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2480 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2481 context->pri_path.feup = 1 << 7; /* don't fsm */
2482 /* handle smac_index */
2483 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2484 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2485 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2486 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2487 if (err) {
2488 err = -EINVAL;
2489 goto out;
2490 }
9433c188
MB		 2491 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2492 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2493 }
2494 }
225c7b1f
RD		 2495 }
2496
400b1ebc 2497 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2498 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2499 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2500 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2501 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2502 if (!rwq_ind_tbl)
d2fce8a9
OG		 2503 context->srqn = cpu_to_be32(7 << 28);
2504 }
2505 }
3528f696 2506
400b1ebc 2507 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2508 int is_eth = rdma_port_get_link_layer(
2509 &dev->ib_dev, qp->port) ==
2510 IB_LINK_LAYER_ETHERNET;
2511 if (is_eth) {
2512 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2513 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2514 }
2515 }
2516
225c7b1f
RD		 2517 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2518 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2519 sqd_event = 1;
2520 else
2521 sqd_event = 0;
2522
89944450 2523 if (!ucontext &&
400b1ebc
GL		 2524 cur_state == IB_QPS_RESET &&
2525 new_state == IB_QPS_INIT)
3b5daf28 2526 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2527
c0be5fb5
EC		 2528 /*
2529 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2530 * ownership bits of the send queue are set and the SQ
2531 * headroom is stamped so that the hardware doesn't start
2532 * processing stale work requests.
c0be5fb5 2533 */
89944450 2534 if (!ucontext &&
400b1ebc
GL		 2535 cur_state == IB_QPS_RESET &&
2536 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2537 struct mlx4_wqe_ctrl_seg *ctrl;
2538 int i;
2539
0e6e7416 2540 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2541 ctrl = get_send_wqe(qp, i);
2542 ctrl->owner_opcode = cpu_to_be32(1 << 31);
f95ccffc
JM		 2543 ctrl->qpn_vlan.fence_size =
2544 1 << (qp->sq.wqe_shift - 4);
2545 stamp_send_wqe(qp, i);
c0be5fb5
EC		 2546 }
2547 }
2548
108809a0
GL		 2549 if (rwq_ind_tbl &&
2550 cur_state == IB_QPS_RESET &&
2551 new_state == IB_QPS_INIT) {
2552 fill_qp_rss_context(context, qp);
2553 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2554 }
2555
225c7b1f
RD		 2556 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2557 to_mlx4_state(new_state), context, optpar,
2558 sqd_event, &qp->mqp);
2559 if (err)
2560 goto out;
2561
2562 qp->state = new_state;
2563
2564 if (attr_mask & IB_QP_ACCESS_FLAGS)
2565 qp->atomic_rd_en = attr->qp_access_flags;
2566 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2567 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2568 if (attr_mask & IB_QP_PORT) {
225c7b1f 2569 qp->port = attr->port_num;
fa417f7b
EC		 2570 update_mcg_macs(dev, qp);
2571 }
225c7b1f
RD		 2572 if (attr_mask & IB_QP_ALT_PATH)
2573 qp->alt_port = attr->alt_port_num;
2574
2575 if (is_sqp(dev, qp))
2576 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2577
2578 /*
2579 * If we moved QP0 to RTR, bring the IB link up; if we moved
2580 * QP0 to RESET or ERROR, bring the link back down.
2581 */
2582 if (is_qp0(dev, qp)) {
2583 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2584 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2585 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2586 qp->port);
225c7b1f
RD		 2587
2588 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2589 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2590 mlx4_CLOSE_PORT(dev->dev, qp->port);
2591 }
2592
2593 /*
2594 * If we moved a kernel QP to RESET, clean up all old CQ
2595 * entries and reinitialize the QP.
2596 */
2f5bb473 2597 if (new_state == IB_QPS_RESET) {
89944450 2598 if (!ucontext) {
2f5bb473 2599 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2600 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2601 if (send_cq != recv_cq)
2602 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2603
2604 qp->rq.head = 0;
2605 qp->rq.tail = 0;
2606 qp->sq.head = 0;
2607 qp->sq.tail = 0;
2608 qp->sq_next_wqe = 0;
2609 if (qp->rq.wqe_cnt)
2610 *qp->db.db = 0;
225c7b1f 2611
2f5bb473
JM		 2612 if (qp->flags & MLX4_IB_QP_NETIF)
2613 mlx4_ib_steer_qp_reg(dev, qp, 0);
2614 }
25476b02 2615 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2616 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2617 qp->pri.smac = 0;
25476b02 2618 qp->pri.smac_port = 0;
2f5bb473
JM		 2619 }
2620 if (qp->alt.smac) {
2621 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2622 qp->alt.smac = 0;
2623 }
2624 if (qp->pri.vid < 0x1000) {
2625 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2626 qp->pri.vid = 0xFFFF;
2627 qp->pri.candidate_vid = 0xFFFF;
2628 qp->pri.update_vid = 0;
2629 }
c1c98501 2630
2f5bb473
JM		 2631 if (qp->alt.vid < 0x1000) {
2632 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2633 qp->alt.vid = 0xFFFF;
2634 qp->alt.candidate_vid = 0xFFFF;
2635 qp->alt.update_vid = 0;
2636 }
225c7b1f 2637 }
225c7b1f 2638out:
7b59f0f9
EBE		 2639 if (err && qp->counter_index)
2640 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2641 if (err && steer_qp)
2642 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2643 kfree(context);
25476b02
JM		 2644 if (qp->pri.candidate_smac ||
2645 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2646 if (err) {
2647 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2648 } else {
25476b02 2649 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2650 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2651 qp->pri.smac = qp->pri.candidate_smac;
2652 qp->pri.smac_index = qp->pri.candidate_smac_index;
2653 qp->pri.smac_port = qp->pri.candidate_smac_port;
2654 }
2655 qp->pri.candidate_smac = 0;
2656 qp->pri.candidate_smac_index = 0;
2657 qp->pri.candidate_smac_port = 0;
2658 }
2659 if (qp->alt.candidate_smac) {
2660 if (err) {
2661 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2662 } else {
2663 if (qp->alt.smac)
2664 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2665 qp->alt.smac = qp->alt.candidate_smac;
2666 qp->alt.smac_index = qp->alt.candidate_smac_index;
2667 qp->alt.smac_port = qp->alt.candidate_smac_port;
2668 }
2669 qp->alt.candidate_smac = 0;
2670 qp->alt.candidate_smac_index = 0;
2671 qp->alt.candidate_smac_port = 0;
2672 }
2673
2674 if (qp->pri.update_vid) {
2675 if (err) {
2676 if (qp->pri.candidate_vid < 0x1000)
2677 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2678 qp->pri.candidate_vid);
2679 } else {
2680 if (qp->pri.vid < 0x1000)
2681 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2682 qp->pri.vid);
2683 qp->pri.vid = qp->pri.candidate_vid;
2684 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2685 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2686 }
2687 qp->pri.candidate_vid = 0xFFFF;
2688 qp->pri.update_vid = 0;
2689 }
2690
2691 if (qp->alt.update_vid) {
2692 if (err) {
2693 if (qp->alt.candidate_vid < 0x1000)
2694 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2695 qp->alt.candidate_vid);
2696 } else {
2697 if (qp->alt.vid < 0x1000)
2698 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2699 qp->alt.vid);
2700 qp->alt.vid = qp->alt.candidate_vid;
2701 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2702 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2703 }
2704 qp->alt.candidate_vid = 0xFFFF;
2705 qp->alt.update_vid = 0;
2706 }
2707
225c7b1f
RD		 2708 return err;
2709}
2710
3078f5f1
GL		 2711enum {
2712 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2713 IB_QP_PORT),
2714};
2715
e1b866c6
MS		 2716static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2717 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2718{
2719 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2720 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2721 enum ib_qp_state cur_state, new_state;
2722 int err = -EINVAL;
65adfa91
MT		 2723 mutex_lock(&qp->mutex);
2724
2725 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2726 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2727
dd5f03be 2728 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
d31131bb 2729 attr_mask)) {
b1d8eb5a
JM		 2730 pr_debug("qpn 0x%x: invalid attribute mask specified "
2731 "for transition %d to %d. qp_type %d,"
2732 " attr_mask 0x%x\n",
2733 ibqp->qp_num, cur_state, new_state,
2734 ibqp->qp_type, attr_mask);
65adfa91 2735 goto out;
b1d8eb5a 2736 }
65adfa91 2737
3078f5f1
GL		 2738 if (ibqp->rwq_ind_tbl) {
2739 if (!(((cur_state == IB_QPS_RESET) &&
2740 (new_state == IB_QPS_INIT)) ||
2741 ((cur_state == IB_QPS_INIT) &&
2742 (new_state == IB_QPS_RTR)))) {
2743 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2744 ibqp->qp_num, cur_state, new_state);
2745
2746 err = -EOPNOTSUPP;
2747 goto out;
2748 }
2749
2750 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2751 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2752 ibqp->qp_num, attr_mask, cur_state, new_state);
2753
2754 err = -EOPNOTSUPP;
2755 goto out;
2756 }
2757 }
2758
c6215745
MS		 2759 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2760 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2761 if ((ibqp->qp_type == IB_QPT_RC) ||
2762 (ibqp->qp_type == IB_QPT_UD) ||
2763 (ibqp->qp_type == IB_QPT_UC) ||
2764 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2765 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2766 attr->port_num = mlx4_ib_bond_next_port(dev);
2767 }
2768 } else {
2769 /* no sense in changing port_num
2770 * when ports are bonded */
2771 attr_mask &= ~IB_QP_PORT;
2772 }
2773 }
2774
65adfa91 2775 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2776 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2777 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2778 "for transition %d to %d. qp_type %d\n",
2779 ibqp->qp_num, attr->port_num, cur_state,
2780 new_state, ibqp->qp_type);
65adfa91
MT		 2781 goto out;
2782 }
2783
3987a2d3
OG		 2784 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2785 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2786 IB_LINK_LAYER_ETHERNET))
2787 goto out;
2788
5ae2a7a8
RD		 2789 if (attr_mask & IB_QP_PKEY_INDEX) {
2790 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2791 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2792 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2793 "for transition %d to %d. qp_type %d\n",
2794 ibqp->qp_num, attr->pkey_index, cur_state,
2795 new_state, ibqp->qp_type);
5ae2a7a8 2796 goto out;
b1d8eb5a 2797 }
5ae2a7a8
RD		 2798 }
2799
65adfa91
MT		 2800 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2801 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2802 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2803 "Transition %d to %d. qp_type %d\n",
2804 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2805 new_state, ibqp->qp_type);
65adfa91
MT		 2806 goto out;
2807 }
2808
2809 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2810 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2811 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2812 "Transition %d to %d. qp_type %d\n",
2813 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2814 new_state, ibqp->qp_type);
65adfa91
MT		 2815 goto out;
2816 }
2817
2818 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2819 err = 0;
2820 goto out;
2821 }
2822
3078f5f1 2823 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
89944450
SR		 2824 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num,
2825 udata);
3078f5f1
GL		 2826 if (err)
2827 goto out;
2828 }
2829
400b1ebc 2830 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
89944450 2831 cur_state, new_state, udata);
65adfa91 2832
3078f5f1 2833 if (ibqp->rwq_ind_tbl && err)
89944450 2834 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata);
3078f5f1 2835
c6215745
MS		 2836 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2837 attr->port_num = 1;
2838
65adfa91
MT		 2839out:
2840 mutex_unlock(&qp->mutex);
2841 return err;
2842}
2843
e1b866c6
MS		 2844int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2845 int attr_mask, struct ib_udata *udata)
2846{
2847 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2848 int ret;
2849
2850 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2851
2852 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2853 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2854 int err = 0;
2855
2856 if (sqp->roce_v2_gsi)
2857 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2858 if (err)
2859 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2860 err);
2861 }
2862 return ret;
2863}
2864
99ec41d0
JM		 2865static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2866{
2867 int i;
2868 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2869 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2870 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2871 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2872 return 0;
2873 }
2874 }
2875 return -EINVAL;
2876}
2877
1ffeb2eb 2878static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
f696bf6d 2879 const struct ib_ud_wr *wr,
1ffeb2eb
JM		 2880 void *wqe, unsigned *mlx_seg_len)
2881{
2882 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2883 struct ib_device *ib_dev = &mdev->ib_dev;
2884 struct mlx4_wqe_mlx_seg *mlx = wqe;
2885 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2886 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2887 u16 pkey;
2888 u32 qkey;
2889 int send_size;
2890 int header_size;
2891 int spc;
6693ca95 2892 int err;
1ffeb2eb
JM		 2893 int i;
2894
e622f2f4 2895 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2896 return -EINVAL;
2897
2898 send_size = 0;
2899
e622f2f4
CH		 2900 for (i = 0; i < wr->wr.num_sge; ++i)
2901 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2902
2903 /* for proxy-qp0 sends, need to add in size of tunnel header */
2904 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2905 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2906 send_size += sizeof (struct mlx4_ib_tunnel_header);
2907
25f40220 2908 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2909
2910 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2911 sqp->ud_header.lrh.service_level =
2912 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2913 sqp->ud_header.lrh.destination_lid =
2914 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2915 sqp->ud_header.lrh.source_lid =
2916 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2917 }
2918
2919 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2920
2921 /* force loopback */
2922 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2923 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2924
2925 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2926 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
6693ca95
JM		 2927 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2928 if (err)
2929 return err;
1ffeb2eb
JM		 2930 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2931 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2932 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2933 else
2934 sqp->ud_header.bth.destination_qpn =
c73c8b1e 2935 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
1ffeb2eb
JM		 2936
2937 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2938 if (mlx4_is_master(mdev->dev)) {
2939 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2940 return -EINVAL;
2941 } else {
2942 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2943 return -EINVAL;
2944 }
1ffeb2eb
JM		 2945 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2946 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2947
2948 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2949 sqp->ud_header.immediate_present = 0;
2950
2951 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2952
2953 /*
2954 * Inline data segments may not cross a 64 byte boundary. If
2955 * our UD header is bigger than the space available up to the
2956 * next 64 byte boundary in the WQE, use two inline data
2957 * segments to hold the UD header.
2958 */
2959 spc = MLX4_INLINE_ALIGN -
2960 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2961 if (header_size <= spc) {
2962 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2963 memcpy(inl + 1, sqp->header_buf, header_size);
2964 i = 1;
2965 } else {
2966 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2967 memcpy(inl + 1, sqp->header_buf, spc);
2968
2969 inl = (void *) (inl + 1) + spc;
2970 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2971 /*
2972 * Need a barrier here to make sure all the data is
2973 * visible before the byte_count field is set.
2974 * Otherwise the HCA prefetcher could grab the 64-byte
2975 * chunk with this inline segment and get a valid (!=
2976 * 0xffffffff) byte count but stale data, and end up
2977 * generating a packet with bad headers.
2978 *
2979 * The first inline segment's byte_count field doesn't
2980 * need a barrier, because it comes after a
2981 * control/MLX segment and therefore is at an offset
2982 * of 16 mod 64.
2983 */
2984 wmb();
2985 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2986 i = 2;
2987 }
2988
2989 *mlx_seg_len =
2990 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2991 return 0;
2992}
2993
fd10ed8e
JM		 2994static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2995{
2996 union sl2vl_tbl_to_u64 tmp_vltab;
2997 u8 vl;
2998
2999 if (sl > 15)
3000 return 0xf;
3001 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3002 vl = tmp_vltab.sl8[sl >> 1];
3003 if (sl & 1)
3004 vl &= 0x0f;
3005 else
3006 vl >>= 4;
3007 return vl;
3008}
3009
a748d60d
TB		 3010static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3011 int index, union ib_gid *gid,
3012 enum ib_gid_type *gid_type)
3013{
3014 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3015 struct mlx4_port_gid_table *port_gid_table;
3016 unsigned long flags;
3017
3018 port_gid_table = &iboe->gids[port_num - 1];
3019 spin_lock_irqsave(&iboe->lock, flags);
3020 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3021 *gid_type = port_gid_table->gids[index].gid_type;
3022 spin_unlock_irqrestore(&iboe->lock, flags);
25e62655 3023 if (rdma_is_zero_gid(gid))
a748d60d
TB		 3024 return -ENOENT;
3025
3026 return 0;
3027}
3028
3ef967a4 3029#define MLX4_ROCEV2_QP1_SPORT 0xC000
f696bf6d 3030static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr,
f438000f 3031 void *wqe, unsigned *mlx_seg_len)
225c7b1f 3032{
a478868a 3033 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 3034 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 3035 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 3036 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 3037 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 3038 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 3039 union ib_gid sgid;
225c7b1f
RD		 3040 u16 pkey;
3041 int send_size;
3042 int header_size;
e61ef241 3043 int spc;
225c7b1f 3044 int i;
1ffeb2eb 3045 int err = 0;
57d88cff 3046 u16 vlan = 0xffff;
a29bec12
RD		 3047 bool is_eth;
3048 bool is_vlan = false;
3049 bool is_grh;
3ef967a4
MS		 3050 bool is_udp = false;
3051 int ip_version = 0;
225c7b1f
RD		 3052
3053 send_size = 0;
e622f2f4
CH		 3054 for (i = 0; i < wr->wr.num_sge; ++i)
3055 send_size += wr->wr.sg_list[i].length;
225c7b1f 3056
fa417f7b
EC		 3057 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3058 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3059 if (is_eth) {
a748d60d 3060 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3061 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3062 /* When multi-function is enabled, the ib_core gid
3063 * indexes don't necessarily match the hw ones, so
3064 * we must use our own cache */
6ee51a4e
JM		 3065 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3066 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3067 ah->av.ib.gid_index, &sgid.raw[0]);
3068 if (err)
3069 return err;
1ffeb2eb 3070 } else {
a748d60d
TB		 3071 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3072 ah->av.ib.gid_index,
3073 &sgid, &gid_type);
3ef967a4 3074 if (!err) {
a748d60d 3075 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3076 if (is_udp) {
3077 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3078 ip_version = 4;
3079 else
3080 ip_version = 6;
3081 is_grh = false;
3082 }
3083 } else {
1ffeb2eb 3084 return err;
3ef967a4 3085 }
1ffeb2eb 3086 }
0e9855db 3087 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad 3088 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
cf368beb 3089 is_vlan = true;
297e0dad 3090 }
4c3eb3ca 3091 }
25f40220 3092 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3093 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3094 if (err)
3095 return err;
fa417f7b
EC		 3096
3097 if (!is_eth) {
3098 sqp->ud_header.lrh.service_level =
3099 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3100 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3101 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3102 }
225c7b1f 3103
3ef967a4 3104 if (is_grh || (ip_version == 6)) {
225c7b1f 3105 sqp->ud_header.grh.traffic_class =
fa417f7b 3106 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3107 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3108 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3109 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3110 if (is_eth) {
6ee51a4e 3111 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3112 } else {
3113 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3114 /* When multi-function is enabled, the ib_core gid
3115 * indexes don't necessarily match the hw ones, so
3116 * we must use our own cache
3117 */
3118 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3119 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3120 demux[sqp->qp.port - 1].
3121 subnet_prefix)));
baa0be70
JM		 3122 sqp->ud_header.grh.source_gid.global.interface_id =
3123 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3124 guid_cache[ah->av.ib.gid_index];
3125 } else {
89af969a
PP		 3126 sqp->ud_header.grh.source_gid =
3127 ah->ibah.sgid_attr->gid;
baa0be70 3128 }
6ee51a4e 3129 }
225c7b1f 3130 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3131 ah->av.ib.dgid, 16);
225c7b1f
RD		 3132 }
3133
3ef967a4
MS		 3134 if (ip_version == 4) {
3135 sqp->ud_header.ip4.tos =
3136 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3137 sqp->ud_header.ip4.id = 0;
3138 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3139 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3140
3141 memcpy(&sqp->ud_header.ip4.saddr,
3142 sgid.raw + 12, 4);
3143 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3144 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3145 }
3146
3147 if (is_udp) {
3148 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3149 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3150 sqp->ud_header.udp.csum = 0;
3151 }
3152
225c7b1f 3153 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3154
3155 if (!is_eth) {
3156 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3157 (sqp->ud_header.lrh.destination_lid ==
3158 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3159 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3160 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3161 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3162 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3163 }
225c7b1f 3164
e622f2f4 3165 switch (wr->wr.opcode) {
225c7b1f
RD		 3166 case IB_WR_SEND:
3167 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3168 sqp->ud_header.immediate_present = 0;
3169 break;
3170 case IB_WR_SEND_WITH_IMM:
3171 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3172 sqp->ud_header.immediate_present = 1;
e622f2f4 3173 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3174 break;
3175 default:
3176 return -EINVAL;
3177 }
3178
fa417f7b 3179 if (is_eth) {
6ee51a4e 3180 struct in6_addr in6;
3ef967a4 3181 u16 ether_type;
c0c1d3d7
OD		 3182 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3183
69ae5439 3184 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3185 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3186
c0c1d3d7 3187 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3188
1049f138 3189 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3190 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3191 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3192 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3193 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3194
3e0629cb 3195
fa417f7b
EC		 3196 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3197 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3198 if (!is_vlan) {
3ef967a4 3199 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3200 } else {
3ef967a4 3201 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3202 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3203 }
fa417f7b 3204 } else {
fd10ed8e
JM		 3205 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3206 sl_to_vl(to_mdev(ib_dev),
3207 sqp->ud_header.lrh.service_level,
3208 sqp->qp.port);
3209 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3210 return -EINVAL;
fa417f7b
EC		 3211 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3212 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3213 }
e622f2f4 3214 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f 3215 if (!sqp->qp.ibqp.qp_num)
6693ca95
JM		 3216 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
3217 &pkey);
225c7b1f 3218 else
6693ca95
JM		 3219 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
3220 &pkey);
3221 if (err)
3222 return err;
3223
225c7b1f 3224 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3225 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3226 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3227 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3228 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3229 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3230
3231 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3232
3233 if (0) {
987c8f8f 3234 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3235 for (i = 0; i < header_size / 4; ++i) {
3236 if (i % 8 == 0)
987c8f8f
SP		 3237 pr_err(" [%02x] ", i * 4);
3238 pr_cont(" %08x",
3239 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3240 if ((i + 1) % 8 == 0)
987c8f8f 3241 pr_cont("\n");
225c7b1f 3242 }
987c8f8f 3243 pr_err("\n");
225c7b1f
RD		 3244 }
3245
e61ef241
RD		 3246 /*
3247 * Inline data segments may not cross a 64 byte boundary. If
3248 * our UD header is bigger than the space available up to the
3249 * next 64 byte boundary in the WQE, use two inline data
3250 * segments to hold the UD header.
3251 */
3252 spc = MLX4_INLINE_ALIGN -
3253 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3254 if (header_size <= spc) {
3255 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3256 memcpy(inl + 1, sqp->header_buf, header_size);
3257 i = 1;
3258 } else {
3259 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3260 memcpy(inl + 1, sqp->header_buf, spc);
3261
3262 inl = (void *) (inl + 1) + spc;
3263 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3264 /*
3265 * Need a barrier here to make sure all the data is
3266 * visible before the byte_count field is set.
3267 * Otherwise the HCA prefetcher could grab the 64-byte
3268 * chunk with this inline segment and get a valid (!=
3269 * 0xffffffff) byte count but stale data, and end up
3270 * generating a packet with bad headers.
3271 *
3272 * The first inline segment's byte_count field doesn't
3273 * need a barrier, because it comes after a
3274 * control/MLX segment and therefore is at an offset
3275 * of 16 mod 64.
3276 */
3277 wmb();
3278 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3279 i = 2;
3280 }
225c7b1f 3281
f438000f
RD		 3282 *mlx_seg_len =
3283 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3284 return 0;
225c7b1f
RD		 3285}
3286
3287static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3288{
3289 unsigned cur;
3290 struct mlx4_ib_cq *cq;
3291
3292 cur = wq->head - wq->tail;
0e6e7416 3293 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3294 return 0;
3295
3296 cq = to_mcq(ib_cq);
3297 spin_lock(&cq->lock);
3298 cur = wq->head - wq->tail;
3299 spin_unlock(&cq->lock);
3300
0e6e7416 3301 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3302}
3303
95d04f07
RD		 3304static __be32 convert_access(int acc)
3305{
6ff63e19
SM		 3306 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3307 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3308 (acc & IB_ACCESS_REMOTE_WRITE ?
3309 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3310 (acc & IB_ACCESS_REMOTE_READ ?
3311 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3312 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3313 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3314}
3315
1b2cd0fc 3316static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
f696bf6d 3317 const struct ib_reg_wr *wr)
1b2cd0fc
SG		 3318{
3319 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3320
3321 fseg->flags = convert_access(wr->access);
3322 fseg->mem_key = cpu_to_be32(wr->key);
3323 fseg->buf_list = cpu_to_be64(mr->page_map);
3324 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3325 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3326 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3327 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3328 fseg->reserved[0] = 0;
3329 fseg->reserved[1] = 0;
3330}
3331
95d04f07
RD		 3332static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3333{
aee38fad
SM		 3334 memset(iseg, 0, sizeof(*iseg));
3335 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3336}
3337
0fbfa6a9
RD		 3338static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3339 u64 remote_addr, u32 rkey)
3340{
3341 rseg->raddr = cpu_to_be64(remote_addr);
3342 rseg->rkey = cpu_to_be32(rkey);
3343 rseg->reserved = 0;
3344}
3345
e622f2f4 3346static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
f696bf6d 3347 const struct ib_atomic_wr *wr)
0fbfa6a9 3348{
e622f2f4
CH		 3349 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3350 aseg->swap_add = cpu_to_be64(wr->swap);
3351 aseg->compare = cpu_to_be64(wr->compare_add);
3352 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3353 aseg->swap_add = cpu_to_be64(wr->compare_add);
3354 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3355 } else {
e622f2f4 3356 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3357 aseg->compare = 0;
3358 }
3359
3360}
3361
6fa8f719 3362static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
f696bf6d 3363 const struct ib_atomic_wr *wr)
6fa8f719 3364{
e622f2f4
CH		 3365 aseg->swap_add = cpu_to_be64(wr->swap);
3366 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3367 aseg->compare = cpu_to_be64(wr->compare_add);
3368 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3369}
3370
0fbfa6a9 3371static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3372 const struct ib_ud_wr *wr)
0fbfa6a9 3373{
e622f2f4
CH		 3374 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3375 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3376 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3377 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3378 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3379}
3380
1ffeb2eb
JM		 3381static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3382 struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3383 const struct ib_ud_wr *wr,
97982f5a 3384 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3385{
e622f2f4 3386 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3387 struct mlx4_av sqp_av = {0};
3388 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3389
3390 /* force loopback */
3391 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3392 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3393 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3394 cpu_to_be32(0xf0000000);
3395
3396 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3397 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3398 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3399 else
c73c8b1e 3400 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3401 /* Use QKEY from the QP context, which is set by master */
3402 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3403}
3404
f696bf6d
BVA		 3405static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3406 unsigned *mlx_seg_len)
1ffeb2eb
JM		 3407{
3408 struct mlx4_wqe_inline_seg *inl = wqe;
3409 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3410 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3411 int spc;
3412 int i;
3413
3414 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3415 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3416 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3417 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3418 memcpy(hdr.mac, ah->av.eth.mac, 6);
3419 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3420
3421 spc = MLX4_INLINE_ALIGN -
3422 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3423 if (sizeof (hdr) <= spc) {
3424 memcpy(inl + 1, &hdr, sizeof (hdr));
3425 wmb();
3426 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3427 i = 1;
3428 } else {
3429 memcpy(inl + 1, &hdr, spc);
3430 wmb();
3431 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3432
3433 inl = (void *) (inl + 1) + spc;
3434 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3435 wmb();
3436 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3437 i = 2;
3438 }
3439
3440 *mlx_seg_len =
3441 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3442}
3443
6e694ea3
JM		 3444static void set_mlx_icrc_seg(void *dseg)
3445{
3446 u32 *t = dseg;
3447 struct mlx4_wqe_inline_seg *iseg = dseg;
3448
3449 t[1] = 0;
3450
3451 /*
3452 * Need a barrier here before writing the byte_count field to
3453 * make sure that all the data is visible before the
3454 * byte_count field is set. Otherwise, if the segment begins
3455 * a new cacheline, the HCA prefetcher could grab the 64-byte
3456 * chunk and get a valid (!= * 0xffffffff) byte count but
3457 * stale data, and end up sending the wrong data.
3458 */
3459 wmb();
3460
3461 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3462}
3463
3464static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3465{
d420d9e3
RD		 3466 dseg->lkey = cpu_to_be32(sg->lkey);
3467 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3468
3469 /*
3470 * Need a barrier here before writing the byte_count field to
3471 * make sure that all the data is visible before the
3472 * byte_count field is set. Otherwise, if the segment begins
3473 * a new cacheline, the HCA prefetcher could grab the 64-byte
3474 * chunk and get a valid (!= * 0xffffffff) byte count but
3475 * stale data, and end up sending the wrong data.
3476 */
3477 wmb();
3478
3479 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3480}
3481
2242fa4f
RD		 3482static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3483{
3484 dseg->byte_count = cpu_to_be32(sg->length);
3485 dseg->lkey = cpu_to_be32(sg->lkey);
3486 dseg->addr = cpu_to_be64(sg->addr);
3487}
3488
f696bf6d
BVA		 3489static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3490 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3491 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3492{
e622f2f4 3493 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3494
417608c2
EC		 3495 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3496 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3497
3498 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3499 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3500 return -EINVAL;
3501
e622f2f4 3502 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3503
e622f2f4 3504 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3505 *lso_seg_len = halign;
3506 return 0;
3507}
3508
f696bf6d 3509static __be32 send_ieth(const struct ib_send_wr *wr)
95d04f07
RD		 3510{
3511 switch (wr->opcode) {
3512 case IB_WR_SEND_WITH_IMM:
3513 case IB_WR_RDMA_WRITE_WITH_IMM:
3514 return wr->ex.imm_data;
3515
3516 case IB_WR_SEND_WITH_INV:
3517 return cpu_to_be32(wr->ex.invalidate_rkey);
3518
3519 default:
3520 return 0;
3521 }
3522}
3523
1ffeb2eb
JM		 3524static void add_zero_len_inline(void *wqe)
3525{
3526 struct mlx4_wqe_inline_seg *inl = wqe;
3527 memset(wqe, 0, 16);
3528 inl->byte_count = cpu_to_be32(1 << 31);
3529}
3530
d34ac5cd
BVA		 3531static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3532 const struct ib_send_wr **bad_wr, bool drain)
225c7b1f
RD		 3533{
3534 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3535 void *wqe;
3536 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3537 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3538 unsigned long flags;
3539 int nreq;
3540 int err = 0;
ea54b10c 3541 unsigned ind;
3f649ab7
KC		 3542 int size;
3543 unsigned seglen;
0fd7e1d8
RD		 3544 __be32 dummy;
3545 __be32 *lso_wqe;
3f649ab7 3546 __be32 lso_hdr_sz;
417608c2 3547 __be32 blh;
225c7b1f 3548 int i;
35f05dab 3549 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3550
e1b866c6
MS		 3551 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3552 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3553
3554 if (sqp->roce_v2_gsi) {
3555 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3556 enum ib_gid_type gid_type;
e1b866c6
MS		 3557 union ib_gid gid;
3558
a748d60d
TB		 3559 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3560 ah->av.ib.gid_index,
3561 &gid, &gid_type))
3562 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3563 to_mqp(sqp->roce_v2_gsi) : qp;
3564 else
e1b866c6
MS		 3565 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3566 ah->av.ib.gid_index);
e1b866c6
MS		 3567 }
3568 }
3569
96db0e03 3570 spin_lock_irqsave(&qp->sq.lock, flags);
1975acd9
YH		 3571 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3572 !drain) {
35f05dab
YH		 3573 err = -EIO;
3574 *bad_wr = wr;
3575 nreq = 0;
3576 goto out;
3577 }
225c7b1f 3578
ea54b10c 3579 ind = qp->sq_next_wqe;
225c7b1f
RD		 3580
3581 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3582 lso_wqe = &dummy;
417608c2 3583 blh = 0;
0fd7e1d8 3584
225c7b1f
RD		 3585 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3586 err = -ENOMEM;
3587 *bad_wr = wr;
3588 goto out;
3589 }
3590
3591 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3592 err = -EINVAL;
3593 *bad_wr = wr;
3594 goto out;
3595 }
3596
0e6e7416 3597 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3598 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3599
3600 ctrl->srcrb_flags =
3601 (wr->send_flags & IB_SEND_SIGNALED ?
3602 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3603 (wr->send_flags & IB_SEND_SOLICITED ?
3604 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3605 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3606 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3607 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3608 qp->sq_signal_bits;
3609
95d04f07 3610 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3611
3612 wqe += sizeof *ctrl;
3613 size = sizeof *ctrl / 16;
3614
1ffeb2eb
JM		 3615 switch (qp->mlx4_ib_qp_type) {
3616 case MLX4_IB_QPT_RC:
3617 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3618 switch (wr->opcode) {
3619 case IB_WR_ATOMIC_CMP_AND_SWP:
3620 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3621 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3622 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3623 atomic_wr(wr)->rkey);
225c7b1f
RD		 3624 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3625
e622f2f4 3626 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3627 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3628
225c7b1f
RD		 3629 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3630 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3631
3632 break;
3633
3634 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3635 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3636 atomic_wr(wr)->rkey);
6fa8f719
VS		 3637 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3638
e622f2f4 3639 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3640 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3641
3642 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3643 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3644
3645 break;
3646
3647 case IB_WR_RDMA_READ:
3648 case IB_WR_RDMA_WRITE:
3649 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3650 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3651 rdma_wr(wr)->rkey);
225c7b1f
RD		 3652 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3653 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3654 break;
95d04f07
RD		 3655
3656 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3657 ctrl->srcrb_flags |=
3658 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3659 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3660 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3661 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3662 break;
3663
1b2cd0fc
SG		 3664 case IB_WR_REG_MR:
3665 ctrl->srcrb_flags |=
3666 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3667 set_reg_seg(wqe, reg_wr(wr));
3668 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3669 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3670 break;
3671
225c7b1f
RD		 3672 default:
3673 /* No extra segments required for sends */
3674 break;
3675 }
3676 break;
3677
1ffeb2eb 3678 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3679 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3680 ctrl, &seglen);
1ffeb2eb
JM		 3681 if (unlikely(err)) {
3682 *bad_wr = wr;
3683 goto out;
3684 }
3685 wqe += seglen;
3686 size += seglen / 16;
3687 break;
3688 case MLX4_IB_QPT_TUN_SMI:
3689 case MLX4_IB_QPT_TUN_GSI:
3690 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3691 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3692 /* set the forced-loopback bit in the data seg av */
3693 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3694 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3695 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3696 break;
3697 case MLX4_IB_QPT_UD:
e622f2f4 3698 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3699 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3700 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3701
3702 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3703 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3704 &lso_hdr_sz, &blh);
b832be1e
EC		 3705 if (unlikely(err)) {
3706 *bad_wr = wr;
3707 goto out;
3708 }
0fd7e1d8 3709 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3710 wqe += seglen;
3711 size += seglen / 16;
3712 }
225c7b1f
RD		 3713 break;
3714
1ffeb2eb 3715 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3716 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3717 ctrl, &seglen);
1ffeb2eb
JM		 3718 if (unlikely(err)) {
3719 *bad_wr = wr;
3720 goto out;
3721 }
3722 wqe += seglen;
3723 size += seglen / 16;
3724 /* to start tunnel header on a cache-line boundary */
3725 add_zero_len_inline(wqe);
3726 wqe += 16;
3727 size++;
e622f2f4 3728 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3729 wqe += seglen;
3730 size += seglen / 16;
3731 break;
3732 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3733 case MLX4_IB_QPT_PROXY_GSI:
3734 /* If we are tunneling special qps, this is a UD qp.
3735 * In this case we first add a UD segment targeting
3736 * the tunnel qp, and then add a header with address
3737 * information */
e622f2f4
CH		 3738 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3739 ud_wr(wr),
97982f5a 3740 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3741 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3742 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3743 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3744 wqe += seglen;
3745 size += seglen / 16;
3746 break;
3747
3748 case MLX4_IB_QPT_SMI:
3749 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3750 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3751 &seglen);
f438000f 3752 if (unlikely(err)) {
225c7b1f
RD		 3753 *bad_wr = wr;
3754 goto out;
3755 }
f438000f
RD		 3756 wqe += seglen;
3757 size += seglen / 16;
225c7b1f
RD		 3758 break;
3759
3760 default:
3761 break;
3762 }
3763
6e694ea3
JM		 3764 /*
3765 * Write data segments in reverse order, so as to
3766 * overwrite cacheline stamp last within each
3767 * cacheline. This avoids issues with WQE
3768 * prefetching.
3769 */
225c7b1f 3770
6e694ea3
JM		 3771 dseg = wqe;
3772 dseg += wr->num_sge - 1;
3773 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3774
3775 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3776 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3777 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3778 qp->mlx4_ib_qp_type &
3779 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3780 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3781 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3782 }
3783
6e694ea3
JM		 3784 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3785 set_data_seg(dseg, wr->sg_list + i);
3786
0fd7e1d8
RD		 3787 /*
3788 * Possibly overwrite stamping in cacheline with LSO
3789 * segment only after making sure all data segments
3790 * are written.
3791 */
3792 wmb();
3793 *lso_wqe = lso_hdr_sz;
3794
224e92e0
BB		 3795 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3796 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3797
3798 /*
3799 * Make sure descriptor is fully written before
3800 * setting ownership bit (because HW can start
3801 * executing as soon as we do).
3802 */
3803 wmb();
3804
59b0ed12 3805 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3806 *bad_wr = wr;
225c7b1f
RD		 3807 err = -EINVAL;
3808 goto out;
3809 }
3810
3811 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3812 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416
RD		 3813
3814 /*
3815 * We can improve latency by not stamping the last
3816 * send queue WQE until after ringing the doorbell, so
3817 * only stamp here if there are still more WQEs to post.
3818 */
f95ccffc
JM		 3819 if (wr->next)
3820 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3821 ind++;
225c7b1f
RD		 3822 }
3823
3824out:
3825 if (likely(nreq)) {
3826 qp->sq.head += nreq;
3827
3828 /*
3829 * Make sure that descriptors are written before
3830 * doorbell record.
3831 */
3832 wmb();
3833
97d82a48
SK		 3834 writel_relaxed(qp->doorbell_qpn,
3835 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
225c7b1f 3836
f95ccffc 3837 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
ea54b10c 3838
ea54b10c 3839 qp->sq_next_wqe = ind;
225c7b1f
RD		 3840 }
3841
96db0e03 3842 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3843
3844 return err;
3845}
3846
d34ac5cd
BVA		 3847int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3848 const struct ib_send_wr **bad_wr)
1975acd9
YH		 3849{
3850 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3851}
3852
d34ac5cd
BVA		 3853static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3854 const struct ib_recv_wr **bad_wr, bool drain)
225c7b1f
RD		 3855{
3856 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3857 struct mlx4_wqe_data_seg *scat;
3858 unsigned long flags;
3859 int err = 0;
3860 int nreq;
3861 int ind;
1ffeb2eb 3862 int max_gs;
225c7b1f 3863 int i;
35f05dab 3864 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3865
1ffeb2eb 3866 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3867 spin_lock_irqsave(&qp->rq.lock, flags);
3868
1975acd9
YH		 3869 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3870 !drain) {
35f05dab
YH		 3871 err = -EIO;
3872 *bad_wr = wr;
3873 nreq = 0;
3874 goto out;
3875 }
3876
0e6e7416 3877 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3878
3879 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3880 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3881 err = -ENOMEM;
3882 *bad_wr = wr;
3883 goto out;
3884 }
3885
3886 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3887 err = -EINVAL;
3888 *bad_wr = wr;
3889 goto out;
3890 }
3891
3892 scat = get_recv_wqe(qp, ind);
3893
1ffeb2eb
JM		 3894 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3895 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3896 ib_dma_sync_single_for_device(ibqp->device,
3897 qp->sqp_proxy_rcv[ind].map,
3898 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3899 DMA_FROM_DEVICE);
3900 scat->byte_count =
3901 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3902 /* use dma lkey from upper layer entry */
3903 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3904 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3905 scat++;
3906 max_gs--;
3907 }
3908
2242fa4f
RD		 3909 for (i = 0; i < wr->num_sge; ++i)
3910 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3911
1ffeb2eb 3912 if (i < max_gs) {
225c7b1f
RD		 3913 scat[i].byte_count = 0;
3914 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3915 scat[i].addr = 0;
3916 }
3917
3918 qp->rq.wrid[ind] = wr->wr_id;
3919
0e6e7416 3920 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3921 }
3922
3923out:
3924 if (likely(nreq)) {
3925 qp->rq.head += nreq;
3926
3927 /*
3928 * Make sure that descriptors are written before
3929 * doorbell record.
3930 */
3931 wmb();
3932
3933 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3934 }
3935
3936 spin_unlock_irqrestore(&qp->rq.lock, flags);
3937
3938 return err;
3939}
6a775e2b 3940
d34ac5cd
BVA		 3941int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3942 const struct ib_recv_wr **bad_wr)
1975acd9
YH		 3943{
3944 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3945}
3946
6a775e2b
JM		 3947static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3948{
3949 switch (mlx4_state) {
3950 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3951 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3952 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3953 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3954 case MLX4_QP_STATE_SQ_DRAINING:
3955 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3956 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3957 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3958 default: return -1;
3959 }
3960}
3961
3962static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3963{
3964 switch (mlx4_mig_state) {
3965 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3966 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3967 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3968 default: return -1;
3969 }
3970}
3971
3972static int to_ib_qp_access_flags(int mlx4_flags)
3973{
3974 int ib_flags = 0;
3975
3976 if (mlx4_flags & MLX4_QP_BIT_RRE)
3977 ib_flags |= IB_ACCESS_REMOTE_READ;
3978 if (mlx4_flags & MLX4_QP_BIT_RWE)
3979 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3980 if (mlx4_flags & MLX4_QP_BIT_RAE)
3981 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3982
3983 return ib_flags;
3984}
3985
71d53ab4 3986static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3987 struct rdma_ah_attr *ah_attr,
71d53ab4 3988 struct mlx4_qp_path *path)
6a775e2b 3989{
4c3eb3ca 3990 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3991 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 3992
d8966fcd 3993 memset(ah_attr, 0, sizeof(*ah_attr));
d8966fcd 3994 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b 3995 return;
f1228867 3996 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
6a775e2b 3997
44c58487 3998 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 3999 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4000 ((path->sched_queue & 4) << 1));
4c3eb3ca 4001 else
d8966fcd 4002 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 4003 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 4004
d8966fcd
DC		 4005 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4006 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4007 rdma_ah_set_static_rate(ah_attr,
4008 path->static_rate ? path->static_rate - 5 : 0);
4009 if (path->grh_mylmc & (1 << 7)) {
4010 rdma_ah_set_grh(ah_attr, NULL,
4011 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4012 path->mgid_index,
4013 path->hop_limit,
4014 (be32_to_cpu(path->tclass_flowlabel)
4015 >> 20) & 0xff);
4016 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 4017 }
4018}
4019
4020int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4021 struct ib_qp_init_attr *qp_init_attr)
4022{
4023 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4024 struct mlx4_ib_qp *qp = to_mqp(ibqp);
4025 struct mlx4_qp_context context;
4026 int mlx4_state;
0df67030
DB		 4027 int err = 0;
4028
3078f5f1
GL		 4029 if (ibqp->rwq_ind_tbl)
4030 return -EOPNOTSUPP;
4031
0df67030 4032 mutex_lock(&qp->mutex);
6a775e2b
JM		 4033
4034 if (qp->state == IB_QPS_RESET) {
4035 qp_attr->qp_state = IB_QPS_RESET;
4036 goto done;
4037 }
4038
4039 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 4040 if (err) {
4041 err = -EINVAL;
4042 goto out;
4043 }
6a775e2b
JM		 4044
4045 mlx4_state = be32_to_cpu(context.flags) >> 28;
4046
0df67030
DB		 4047 qp->state = to_ib_qp_state(mlx4_state);
4048 qp_attr->qp_state = qp->state;
6a775e2b
JM		 4049 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4050 qp_attr->path_mig_state =
4051 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4052 qp_attr->qkey = be32_to_cpu(context.qkey);
4053 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4054 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4055 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4056 qp_attr->qp_access_flags =
4057 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4058
4059 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 4060 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4061 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4062 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4063 qp_attr->alt_port_num =
4064 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4065 }
4066
4067 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4068 if (qp_attr->qp_state == IB_QPS_INIT)
4069 qp_attr->port_num = qp->port;
4070 else
4071 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4072
4073 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4074 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4075
4076 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4077
4078 qp_attr->max_dest_rd_atomic =
4079 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4080 qp_attr->min_rnr_timer =
4081 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4082 qp_attr->timeout = context.pri_path.ackto >> 3;
4083 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4084 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4085 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4086
4087done:
4088 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4089 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4090 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4091
6a775e2b 4092 if (!ibqp->uobject) {
7f5eb9bb
RD		 4093 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4094 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4095 } else {
4096 qp_attr->cap.max_send_wr = 0;
4097 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4098 }
4099
7f5eb9bb
RD		 4100 /*
4101 * We don't support inline sends for kernel QPs (yet), and we
4102 * don't know what userspace's value should be.
4103 */
4104 qp_attr->cap.max_inline_data = 0;
4105
4106 qp_init_attr->cap = qp_attr->cap;
4107
521e575b
RL		 4108 qp_init_attr->create_flags = 0;
4109 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4110 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4111
4112 if (qp->flags & MLX4_IB_QP_LSO)
4113 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4114
c1c98501
MB		 4115 if (qp->flags & MLX4_IB_QP_NETIF)
4116 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4117
46db567d
DB		 4118 qp_init_attr->sq_sig_type =
4119 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4120 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4121
0df67030
DB		 4122out:
4123 mutex_unlock(&qp->mutex);
4124 return err;
6a775e2b
JM		 4125}
4126
400b1ebc
GL		 4127struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4128 struct ib_wq_init_attr *init_attr,
4129 struct ib_udata *udata)
4130{
089b645d
LR		 4131 struct mlx4_dev *dev = to_mdev(pd->device)->dev;
4132 struct ib_qp_init_attr ib_qp_init_attr = {};
400b1ebc
GL		 4133 struct mlx4_ib_qp *qp;
4134 struct mlx4_ib_create_wq ucmd;
4135 int err, required_cmd_sz;
4136
e00b64f7 4137 if (!udata)
400b1ebc
GL		 4138 return ERR_PTR(-EINVAL);
4139
078b3573
GL		 4140 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4141 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4142 if (udata->inlen < required_cmd_sz) {
4143 pr_debug("invalid inlen\n");
4144 return ERR_PTR(-EINVAL);
4145 }
4146
4147 if (udata->inlen > sizeof(ucmd) &&
4148 !ib_is_udata_cleared(udata, sizeof(ucmd),
4149 udata->inlen - sizeof(ucmd))) {
4150 pr_debug("inlen is not supported\n");
4151 return ERR_PTR(-EOPNOTSUPP);
4152 }
4153
4154 if (udata->outlen)
4155 return ERR_PTR(-EOPNOTSUPP);
4156
400b1ebc
GL		 4157 if (init_attr->wq_type != IB_WQT_RQ) {
4158 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4159 return ERR_PTR(-EOPNOTSUPP);
4160 }
4161
089b645d
LR		 4162 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS ||
4163 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
400b1ebc
GL		 4164 pr_debug("unsupported create_flags %u\n",
4165 init_attr->create_flags);
4166 return ERR_PTR(-EOPNOTSUPP);
4167 }
4168
4169 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4170 if (!qp)
4171 return ERR_PTR(-ENOMEM);
4172
4173 qp->pri.vid = 0xFFFF;
4174 qp->alt.vid = 0xFFFF;
4175
400b1ebc
GL		 4176 ib_qp_init_attr.qp_context = init_attr->wq_context;
4177 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4178 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4179 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4180 ib_qp_init_attr.recv_cq = init_attr->cq;
4181 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4182
6d06c9aa
GL		 4183 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4184 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4185
089b645d 4186 err = create_rq(pd, &ib_qp_init_attr, udata, qp);
400b1ebc
GL		 4187 if (err) {
4188 kfree(qp);
4189 return ERR_PTR(err);
4190 }
4191
4192 qp->ibwq.event_handler = init_attr->event_handler;
4193 qp->ibwq.wq_num = qp->mqp.qpn;
4194 qp->ibwq.state = IB_WQS_RESET;
4195
4196 return &qp->ibwq;
4197}
4198
4199static int ib_wq2qp_state(enum ib_wq_state state)
4200{
4201 switch (state) {
4202 case IB_WQS_RESET:
4203 return IB_QPS_RESET;
4204 case IB_WQS_RDY:
4205 return IB_QPS_RTR;
4206 default:
4207 return IB_QPS_ERR;
4208 }
4209}
4210
89944450
SR		 4211static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
4212 struct ib_udata *udata)
400b1ebc
GL		 4213{
4214 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4215 enum ib_qp_state qp_cur_state;
4216 enum ib_qp_state qp_new_state;
4217 int attr_mask;
4218 int err;
4219
4220 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4221 * the WQ logic state.
4222 */
4223 qp_cur_state = qp->state;
4224 qp_new_state = ib_wq2qp_state(new_state);
4225
4226 if (ib_wq2qp_state(new_state) == qp_cur_state)
4227 return 0;
4228
4229 if (new_state == IB_WQS_RDY) {
4230 struct ib_qp_attr attr = {};
4231
4232 attr.port_num = qp->port;
4233 attr_mask = IB_QP_PORT;
4234
4235 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
89944450
SR		 4236 attr_mask, IB_QPS_RESET, IB_QPS_INIT,
4237 udata);
400b1ebc
GL		 4238 if (err) {
4239 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4240 ibwq->wq_num);
4241 return err;
4242 }
4243
4244 qp_cur_state = IB_QPS_INIT;
4245 }
4246
4247 attr_mask = 0;
4248 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
89944450 4249 qp_cur_state, qp_new_state, udata);
400b1ebc
GL		 4250
4251 if (err && (qp_cur_state == IB_QPS_INIT)) {
4252 qp_new_state = IB_QPS_RESET;
4253 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
89944450
SR		 4254 attr_mask, IB_QPS_INIT, IB_QPS_RESET,
4255 udata)) {
400b1ebc
GL		 4256 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4257 ibwq->wq_num);
4258 qp_new_state = IB_QPS_INIT;
4259 }
4260 }
4261
4262 qp->state = qp_new_state;
4263
4264 return err;
4265}
4266
4267int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4268 u32 wq_attr_mask, struct ib_udata *udata)
4269{
4270 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4271 struct mlx4_ib_modify_wq ucmd = {};
4272 size_t required_cmd_sz;
4273 enum ib_wq_state cur_state, new_state;
4274 int err = 0;
4275
4276 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4277 sizeof(ucmd.reserved);
4278 if (udata->inlen < required_cmd_sz)
4279 return -EINVAL;
4280
4281 if (udata->inlen > sizeof(ucmd) &&
4282 !ib_is_udata_cleared(udata, sizeof(ucmd),
4283 udata->inlen - sizeof(ucmd)))
4284 return -EOPNOTSUPP;
4285
4286 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4287 return -EFAULT;
4288
4289 if (ucmd.comp_mask || ucmd.reserved)
4290 return -EOPNOTSUPP;
4291
4292 if (wq_attr_mask & IB_WQ_FLAGS)
4293 return -EOPNOTSUPP;
4294
4295 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4296 ibwq->state;
4297 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4298
4299 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4300 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4301 return -EINVAL;
4302
4303 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4304 return -EINVAL;
4305
4306 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4307 return -EINVAL;
4308
3078f5f1
GL		 4309 /* Need to protect against the parent RSS which also may modify WQ
4310 * state.
4311 */
4312 mutex_lock(&qp->mutex);
4313
400b1ebc
GL		 4314 /* Can update HW state only if a RSS QP has already associated to this
4315 * WQ, so we can apply its port on the WQ.
4316 */
4317 if (qp->rss_usecnt)
89944450 4318 err = _mlx4_ib_modify_wq(ibwq, new_state, udata);
400b1ebc
GL		 4319
4320 if (!err)
4321 ibwq->state = new_state;
4322
3078f5f1
GL		 4323 mutex_unlock(&qp->mutex);
4324
400b1ebc
GL		 4325 return err;
4326}
4327
add53535 4328int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata)
400b1ebc
GL		 4329{
4330 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4331 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4332
4333 if (qp->counter_index)
4334 mlx4_ib_free_qp_counter(dev, qp);
4335
bdeacabd 4336 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata);
400b1ebc
GL		 4337
4338 kfree(qp);
add53535 4339 return 0;
400b1ebc 4340}
b8d46ca0 4341
c0a6b5ec
LR		 4342int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table,
4343 struct ib_rwq_ind_table_init_attr *init_attr,
4344 struct ib_udata *udata)
b8d46ca0 4345{
b8d46ca0
GL		 4346 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4347 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
c0a6b5ec 4348 struct ib_device *device = rwq_ind_table->device;
b8d46ca0
GL		 4349 unsigned int base_wqn;
4350 size_t min_resp_len;
c0a6b5ec 4351 int i, err = 0;
b8d46ca0
GL		 4352
4353 if (udata->inlen > 0 &&
4354 !ib_is_udata_cleared(udata, 0,
4355 udata->inlen))
c0a6b5ec 4356 return -EOPNOTSUPP;
b8d46ca0
GL		 4357
4358 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4359 if (udata->outlen && udata->outlen < min_resp_len)
c0a6b5ec 4360 return -EINVAL;
b8d46ca0
GL		 4361
4362 if (ind_tbl_size >
4363 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4364 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4365 ind_tbl_size,
4366 device->attrs.rss_caps.max_rwq_indirection_table_size);
c0a6b5ec 4367 return -EINVAL;
b8d46ca0
GL		 4368 }
4369
4370 base_wqn = init_attr->ind_tbl[0]->wq_num;
4371
4372 if (base_wqn % ind_tbl_size) {
4373 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4374 base_wqn);
c0a6b5ec 4375 return -EINVAL;
b8d46ca0
GL		 4376 }
4377
4378 for (i = 1; i < ind_tbl_size; i++) {
4379 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4380 pr_debug("indirection table's WQNs aren't consecutive\n");
c0a6b5ec 4381 return -EINVAL;
b8d46ca0
GL		 4382 }
4383 }
4384
b8d46ca0
GL		 4385 if (udata->outlen) {
4386 resp.response_length = offsetof(typeof(resp), response_length) +
4387 sizeof(resp.response_length);
4388 err = ib_copy_to_udata(udata, &resp, resp.response_length);
b8d46ca0
GL		 4389 }
4390
c0a6b5ec 4391 return err;
b8d46ca0 4392}
1975acd9
YH		 4393
4394struct mlx4_ib_drain_cqe {
4395 struct ib_cqe cqe;
4396 struct completion done;
4397};
4398
4399static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4400{
4401 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4402 struct mlx4_ib_drain_cqe,
4403 cqe);
4404
4405 complete(&cqe->done);
4406}
4407
4408/* This function returns only once the drained WR was completed */
4409static void handle_drain_completion(struct ib_cq *cq,
4410 struct mlx4_ib_drain_cqe *sdrain,
4411 struct mlx4_ib_dev *dev)
4412{
4413 struct mlx4_dev *mdev = dev->dev;
4414
4415 if (cq->poll_ctx == IB_POLL_DIRECT) {
4416 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4417 ib_process_cq_direct(cq, -1);
4418 return;
4419 }
4420
4421 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4422 struct mlx4_ib_cq *mcq = to_mcq(cq);
4423 bool triggered = false;
4424 unsigned long flags;
4425
4426 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4427 /* Make sure that the CQ handler won't run if wasn't run yet */
4428 if (!mcq->mcq.reset_notify_added)
4429 mcq->mcq.reset_notify_added = 1;
4430 else
4431 triggered = true;
4432 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4433
4434 if (triggered) {
4435 /* Wait for any scheduled/running task to be ended */
4436 switch (cq->poll_ctx) {
4437 case IB_POLL_SOFTIRQ:
4438 irq_poll_disable(&cq->iop);
4439 irq_poll_enable(&cq->iop);
4440 break;
4441 case IB_POLL_WORKQUEUE:
4442 cancel_work_sync(&cq->work);
4443 break;
4444 default:
4445 WARN_ON_ONCE(1);
4446 }
4447 }
4448
4449 /* Run the CQ handler - this makes sure that the drain WR will
4450 * be processed if wasn't processed yet.
4451 */
4452 mcq->mcq.comp(&mcq->mcq);
4453 }
4454
4455 wait_for_completion(&sdrain->done);
4456}
4457
4458void mlx4_ib_drain_sq(struct ib_qp *qp)
4459{
4460 struct ib_cq *cq = qp->send_cq;
4461 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4462 struct mlx4_ib_drain_cqe sdrain;
d34ac5cd 4463 const struct ib_send_wr *bad_swr;
1975acd9
YH		 4464 struct ib_rdma_wr swr = {
4465 .wr = {
4466 .next = NULL,
4467 { .wr_cqe = &sdrain.cqe, },
4468 .opcode = IB_WR_RDMA_WRITE,
4469 },
4470 };
4471 int ret;
4472 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4473 struct mlx4_dev *mdev = dev->dev;
4474
4475 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4476 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4477 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4478 return;
4479 }
4480
4481 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4482 init_completion(&sdrain.done);
4483
4484 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4485 if (ret) {
4486 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4487 return;
4488 }
4489
4490 handle_drain_completion(cq, &sdrain, dev);
4491}
4492
4493void mlx4_ib_drain_rq(struct ib_qp *qp)
4494{
4495 struct ib_cq *cq = qp->recv_cq;
4496 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4497 struct mlx4_ib_drain_cqe rdrain;
d34ac5cd
BVA		 4498 struct ib_recv_wr rwr = {};
4499 const struct ib_recv_wr *bad_rwr;
1975acd9
YH		 4500 int ret;
4501 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4502 struct mlx4_dev *mdev = dev->dev;
4503
4504 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4505 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4506 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4507 return;
4508 }
4509
4510 rwr.wr_cqe = &rdrain.cqe;
4511 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4512 init_completion(&rdrain.done);
4513
4514 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4515 if (ret) {
4516 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4517 return;
4518 }
4519
4520 handle_drain_completion(cq, &rdrain, dev);
4521}
Linux 6.x block layer and io_uring tree(s)