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IB/mlx5: Fix blue flame buffer size calculation
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
0ef2f05c 39#include <linux/vmalloc.h>
ea54b10c 40
225c7b1f
RD		 41#include <rdma/ib_cache.h>
42#include <rdma/ib_pack.h>
4c3eb3ca 43#include <rdma/ib_addr.h>
1ffeb2eb 44#include <rdma/ib_mad.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
9ce28a20 50#include <rdma/mlx4-abi.h>
225c7b1f 51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
fa417f7b
EC		 79enum {
80 MLX4_IB_IBOE_ETHERTYPE = 0x8915
81};
82
225c7b1f
RD		 83struct mlx4_ib_sqp {
84 struct mlx4_ib_qp qp;
85 int pkey_index;
86 u32 qkey;
87 u32 send_psn;
88 struct ib_ud_header ud_header;
89 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 90 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 91};
92
83904132 93enum {
417608c2
EC		 94 MLX4_IB_MIN_SQ_STRIDE = 6,
95 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 96};
97
3987a2d3
OG		 98enum {
99 MLX4_RAW_QP_MTU = 7,
100 MLX4_RAW_QP_MSGMAX = 31,
101};
102
297e0dad
MS		 103#ifndef ETH_ALEN
104#define ETH_ALEN 6
105#endif
297e0dad 106
225c7b1f 107static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 108 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
109 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
110 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
111 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
112 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
113 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
114 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
115 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
116 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
117 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 118 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 119 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
120 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 121};
122
123static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
124{
125 return container_of(mqp, struct mlx4_ib_sqp, qp);
126}
127
1ffeb2eb
JM		 128static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
129{
130 if (!mlx4_is_master(dev->dev))
131 return 0;
132
47605df9
JM		 133 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
134 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
135 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 136}
137
225c7b1f
RD		 138static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
139{
47605df9
JM		 140 int proxy_sqp = 0;
141 int real_sqp = 0;
142 int i;
143 /* PPF or Native -- real SQP */
144 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
145 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
146 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
147 if (real_sqp)
148 return 1;
149 /* VF or PF -- proxy SQP */
150 if (mlx4_is_mfunc(dev->dev)) {
151 for (i = 0; i < dev->dev->caps.num_ports; i++) {
152 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
153 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
154 proxy_sqp = 1;
155 break;
156 }
157 }
158 }
e1b866c6
MS		 159 if (proxy_sqp)
160 return 1;
161
162 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 163}
164
1ffeb2eb 165/* used for INIT/CLOSE port logic */
225c7b1f
RD		 166static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
167{
47605df9
JM		 168 int proxy_qp0 = 0;
169 int real_qp0 = 0;
170 int i;
171 /* PPF or Native -- real QP0 */
172 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
173 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
174 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
175 if (real_qp0)
176 return 1;
177 /* VF or PF -- proxy QP0 */
178 if (mlx4_is_mfunc(dev->dev)) {
179 for (i = 0; i < dev->dev->caps.num_ports; i++) {
180 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
181 proxy_qp0 = 1;
182 break;
183 }
184 }
185 }
186 return proxy_qp0;
225c7b1f
RD		 187}
188
189static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
190{
1c69fc2a 191 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 192}
193
194static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
195{
196 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
197}
198
199static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
200{
201 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
202}
203
0e6e7416
RD		 204/*
205 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 206 * first four bytes of every 64 byte chunk with
207 * 0x7FFFFFF | (invalid_ownership_value << 31).
208 *
209 * When the max work request size is less than or equal to the WQE
210 * basic block size, as an optimization, we can stamp all WQEs with
211 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 212 */
ea54b10c 213static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 214{
d2ae16d5 215 __be32 *wqe;
0e6e7416 216 int i;
ea54b10c
JM		 217 int s;
218 int ind;
219 void *buf;
220 __be32 stamp;
9670e553 221 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 222
ea54b10c 223 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 224 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 225 for (i = 0; i < s; i += 64) {
226 ind = (i >> qp->sq.wqe_shift) + n;
227 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
228 cpu_to_be32(0xffffffff);
229 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
230 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
231 *wqe = stamp;
232 }
233 } else {
9670e553 234 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
224e92e0 235 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
ea54b10c
JM		 236 for (i = 64; i < s; i += 64) {
237 wqe = buf + i;
d2ae16d5 238 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 239 }
240 }
241}
242
243static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
244{
245 struct mlx4_wqe_ctrl_seg *ctrl;
246 struct mlx4_wqe_inline_seg *inl;
247 void *wqe;
248 int s;
249
250 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
251 s = sizeof(struct mlx4_wqe_ctrl_seg);
252
253 if (qp->ibqp.qp_type == IB_QPT_UD) {
254 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
255 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
256 memset(dgram, 0, sizeof *dgram);
257 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
258 s += sizeof(struct mlx4_wqe_datagram_seg);
259 }
260
261 /* Pad the remainder of the WQE with an inline data segment. */
262 if (size > s) {
263 inl = wqe + s;
264 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
265 }
266 ctrl->srcrb_flags = 0;
224e92e0 267 ctrl->qpn_vlan.fence_size = size / 16;
ea54b10c
JM		 268 /*
269 * Make sure descriptor is fully written before setting ownership bit
270 * (because HW can start executing as soon as we do).
271 */
272 wmb();
273
274 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
275 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 276
ea54b10c
JM		 277 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
278}
279
280/* Post NOP WQE to prevent wrap-around in the middle of WR */
281static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
282{
283 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
284 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
285 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
286 ind += s;
287 }
288 return ind;
0e6e7416
RD		 289}
290
225c7b1f
RD		 291static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
292{
293 struct ib_event event;
294 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
295
296 if (type == MLX4_EVENT_TYPE_PATH_MIG)
297 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
298
299 if (ibqp->event_handler) {
300 event.device = ibqp->device;
301 event.element.qp = ibqp;
302 switch (type) {
303 case MLX4_EVENT_TYPE_PATH_MIG:
304 event.event = IB_EVENT_PATH_MIG;
305 break;
306 case MLX4_EVENT_TYPE_COMM_EST:
307 event.event = IB_EVENT_COMM_EST;
308 break;
309 case MLX4_EVENT_TYPE_SQ_DRAINED:
310 event.event = IB_EVENT_SQ_DRAINED;
311 break;
312 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
313 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
314 break;
315 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
316 event.event = IB_EVENT_QP_FATAL;
317 break;
318 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
319 event.event = IB_EVENT_PATH_MIG_ERR;
320 break;
321 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
322 event.event = IB_EVENT_QP_REQ_ERR;
323 break;
324 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
325 event.event = IB_EVENT_QP_ACCESS_ERR;
326 break;
327 default:
987c8f8f 328 pr_warn("Unexpected event type %d "
225c7b1f
RD		 329 "on QP %06x\n", type, qp->qpn);
330 return;
331 }
332
333 ibqp->event_handler(&event, ibqp->qp_context);
334 }
335}
336
1ffeb2eb 337static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 338{
339 /*
340 * UD WQEs must have a datagram segment.
341 * RC and UC WQEs might have a remote address segment.
342 * MLX WQEs need two extra inline data segments (for the UD
343 * header and space for the ICRC).
344 */
345 switch (type) {
1ffeb2eb 346 case MLX4_IB_QPT_UD:
225c7b1f 347 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 348 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 349 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 350 case MLX4_IB_QPT_PROXY_SMI_OWNER:
351 case MLX4_IB_QPT_PROXY_SMI:
352 case MLX4_IB_QPT_PROXY_GSI:
353 return sizeof (struct mlx4_wqe_ctrl_seg) +
354 sizeof (struct mlx4_wqe_datagram_seg) + 64;
355 case MLX4_IB_QPT_TUN_SMI_OWNER:
356 case MLX4_IB_QPT_TUN_GSI:
357 return sizeof (struct mlx4_wqe_ctrl_seg) +
358 sizeof (struct mlx4_wqe_datagram_seg);
359
360 case MLX4_IB_QPT_UC:
225c7b1f
RD		 361 return sizeof (struct mlx4_wqe_ctrl_seg) +
362 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 363 case MLX4_IB_QPT_RC:
225c7b1f 364 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 365 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 366 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 367 case MLX4_IB_QPT_SMI:
368 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 369 return sizeof (struct mlx4_wqe_ctrl_seg) +
370 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 371 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
372 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 373 sizeof (struct mlx4_wqe_inline_seg),
374 sizeof (struct mlx4_wqe_data_seg)) +
375 ALIGN(4 +
376 sizeof (struct mlx4_wqe_inline_seg),
377 sizeof (struct mlx4_wqe_data_seg));
378 default:
379 return sizeof (struct mlx4_wqe_ctrl_seg);
380 }
381}
382
2446304d 383static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 384 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 385{
2446304d 386 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 387 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
388 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 389 return -EINVAL;
390
0a1405da 391 if (!has_rq) {
a4cd7ed8
RD		 392 if (cap->max_recv_wr)
393 return -EINVAL;
2446304d 394
0e6e7416 395 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 396 } else {
397 /* HW requires >= 1 RQ entry with >= 1 gather entry */
398 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
399 return -EINVAL;
400
0e6e7416 401 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 402 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 403 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
404 }
2446304d 405
fc2d0044
SG		 406 /* leave userspace return values as they were, so as not to break ABI */
407 if (is_user) {
408 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
409 cap->max_recv_sge = qp->rq.max_gs;
410 } else {
411 cap->max_recv_wr = qp->rq.max_post =
412 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
413 cap->max_recv_sge = min(qp->rq.max_gs,
414 min(dev->dev->caps.max_sq_sg,
415 dev->dev->caps.max_rq_sg));
416 }
2446304d
EC		 417
418 return 0;
419}
420
421static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
73898db0
HA		 422 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
423 bool shrink_wqe)
2446304d 424{
ea54b10c
JM		 425 int s;
426
2446304d 427 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 428 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
429 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 430 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 431 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
432 return -EINVAL;
433
434 /*
435 * For MLX transport we need 2 extra S/G entries:
436 * one for the header and one for the checksum at the end
437 */
1ffeb2eb
JM		 438 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
439 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 440 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
441 return -EINVAL;
442
ea54b10c
JM		 443 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
444 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 445 send_wqe_overhead(type, qp->flags);
225c7b1f 446
cd155c1c
RD		 447 if (s > dev->dev->caps.max_sq_desc_sz)
448 return -EINVAL;
449
0e6e7416 450 /*
ea54b10c
JM		 451 * Hermon supports shrinking WQEs, such that a single work
452 * request can include multiple units of 1 << wqe_shift. This
453 * way, work requests can differ in size, and do not have to
454 * be a power of 2 in size, saving memory and speeding up send
455 * WR posting. Unfortunately, if we do this then the
456 * wqe_index field in CQEs can't be used to look up the WR ID
457 * anymore, so we do this only if selective signaling is off.
458 *
459 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 460 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 461 * constant-sized WRs to make sure a WR is always fully within
462 * a single page-sized chunk.
463 *
464 * Finally, we use NOP work requests to pad the end of the
465 * work queue, to avoid wrap-around in the middle of WR. We
466 * set NEC bit to avoid getting completions with error for
467 * these NOP WRs, but since NEC is only supported starting
468 * with firmware 2.2.232, we use constant-sized WRs for older
469 * firmware.
470 *
471 * And, since MLX QPs only support SEND, we use constant-sized
472 * WRs in this case.
473 *
474 * We look for the smallest value of wqe_shift such that the
475 * resulting number of wqes does not exceed device
476 * capabilities.
477 *
478 * We set WQE size to at least 64 bytes, this way stamping
479 * invalidates each WQE.
0e6e7416 480 */
73898db0 481 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
ea54b10c 482 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 483 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
484 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
485 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 486 qp->sq.wqe_shift = ilog2(64);
487 else
488 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
489
490 for (;;) {
ea54b10c
JM		 491 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
492
493 /*
494 * We need to leave 2 KB + 1 WR of headroom in the SQ to
495 * allow HW to prefetch.
496 */
497 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
498 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
499 qp->sq_max_wqes_per_wr +
500 qp->sq_spare_wqes);
501
502 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
503 break;
504
505 if (qp->sq_max_wqes_per_wr <= 1)
506 return -EINVAL;
507
508 ++qp->sq.wqe_shift;
509 }
510
cd155c1c
RD		 511 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
512 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 513 send_wqe_overhead(type, qp->flags)) /
514 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 515
516 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
517 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 518 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
519 qp->rq.offset = 0;
0e6e7416 520 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 521 } else {
0e6e7416 522 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 523 qp->sq.offset = 0;
524 }
525
ea54b10c
JM		 526 cap->max_send_wr = qp->sq.max_post =
527 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 528 cap->max_send_sge = min(qp->sq.max_gs,
529 min(dev->dev->caps.max_sq_sg,
530 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 531 /* We don't support inline sends for kernel QPs (yet) */
532 cap->max_inline_data = 0;
225c7b1f
RD		 533
534 return 0;
535}
536
83904132
JM		 537static int set_user_sq_size(struct mlx4_ib_dev *dev,
538 struct mlx4_ib_qp *qp,
2446304d
EC		 539 struct mlx4_ib_create_qp *ucmd)
540{
83904132
JM		 541 /* Sanity check SQ size before proceeding */
542 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
543 ucmd->log_sq_stride >
544 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
545 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
546 return -EINVAL;
547
0e6e7416 548 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 549 qp->sq.wqe_shift = ucmd->log_sq_stride;
550
0e6e7416
RD		 551 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
552 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 553
554 return 0;
555}
556
1ffeb2eb
JM		 557static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
558{
559 int i;
560
561 qp->sqp_proxy_rcv =
562 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
563 GFP_KERNEL);
564 if (!qp->sqp_proxy_rcv)
565 return -ENOMEM;
566 for (i = 0; i < qp->rq.wqe_cnt; i++) {
567 qp->sqp_proxy_rcv[i].addr =
568 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
569 GFP_KERNEL);
570 if (!qp->sqp_proxy_rcv[i].addr)
571 goto err;
572 qp->sqp_proxy_rcv[i].map =
573 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
574 sizeof (struct mlx4_ib_proxy_sqp_hdr),
575 DMA_FROM_DEVICE);
cc47d369
SO		 576 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
577 kfree(qp->sqp_proxy_rcv[i].addr);
578 goto err;
579 }
1ffeb2eb
JM		 580 }
581 return 0;
582
583err:
584 while (i > 0) {
585 --i;
586 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
587 sizeof (struct mlx4_ib_proxy_sqp_hdr),
588 DMA_FROM_DEVICE);
589 kfree(qp->sqp_proxy_rcv[i].addr);
590 }
591 kfree(qp->sqp_proxy_rcv);
592 qp->sqp_proxy_rcv = NULL;
593 return -ENOMEM;
594}
595
596static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
597{
598 int i;
599
600 for (i = 0; i < qp->rq.wqe_cnt; i++) {
601 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
602 sizeof (struct mlx4_ib_proxy_sqp_hdr),
603 DMA_FROM_DEVICE);
604 kfree(qp->sqp_proxy_rcv[i].addr);
605 }
606 kfree(qp->sqp_proxy_rcv);
607}
608
0a1405da
SH		 609static int qp_has_rq(struct ib_qp_init_attr *attr)
610{
611 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
612 return 0;
613
614 return !attr->srq;
615}
616
99ec41d0
JM		 617static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
618{
619 int i;
620 for (i = 0; i < dev->caps.num_ports; i++) {
621 if (qpn == dev->caps.qp0_proxy[i])
622 return !!dev->caps.qp0_qkey[i];
623 }
624 return 0;
625}
626
7b59f0f9
EBE		 627static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
628 struct mlx4_ib_qp *qp)
629{
630 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
631 mlx4_counter_free(dev->dev, qp->counter_index->index);
632 list_del(&qp->counter_index->list);
633 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
634
635 kfree(qp->counter_index);
636 qp->counter_index = NULL;
637}
638
225c7b1f
RD		 639static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
640 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 641 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
642 gfp_t gfp)
225c7b1f 643{
a3cdcbfa 644 int qpn;
225c7b1f 645 int err;
73898db0 646 struct ib_qp_cap backup_cap;
b42dde47 647 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 648 struct mlx4_ib_qp *qp;
649 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 650 struct mlx4_ib_cq *mcq;
651 unsigned long flags;
1ffeb2eb
JM		 652
653 /* When tunneling special qps, we use a plain UD qp */
654 if (sqpn) {
655 if (mlx4_is_mfunc(dev->dev) &&
656 (!mlx4_is_master(dev->dev) ||
657 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
658 if (init_attr->qp_type == IB_QPT_GSI)
659 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 660 else {
661 if (mlx4_is_master(dev->dev) ||
662 qp0_enabled_vf(dev->dev, sqpn))
663 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
664 else
665 qp_type = MLX4_IB_QPT_PROXY_SMI;
666 }
1ffeb2eb
JM		 667 }
668 qpn = sqpn;
669 /* add extra sg entry for tunneling */
670 init_attr->cap.max_recv_sge++;
671 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
672 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
673 container_of(init_attr,
674 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
675 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
676 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
677 !mlx4_is_master(dev->dev))
678 return -EINVAL;
679 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
680 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 681 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
682 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
683 tnl_init->port))
1ffeb2eb
JM		 684 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
685 else
686 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 687 /* we are definitely in the PPF here, since we are creating
688 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
689 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
690 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 691 sqpn = qpn;
692 }
693
694 if (!*caller_qp) {
695 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
696 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
697 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 698 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 699 if (!sqp)
700 return -ENOMEM;
701 qp = &sqp->qp;
2f5bb473
JM		 702 qp->pri.vid = 0xFFFF;
703 qp->alt.vid = 0xFFFF;
1ffeb2eb 704 } else {
6fcd8d0d 705 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 706 if (!qp)
707 return -ENOMEM;
2f5bb473
JM		 708 qp->pri.vid = 0xFFFF;
709 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 710 }
711 } else
712 qp = *caller_qp;
713
714 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 715
716 mutex_init(&qp->mutex);
717 spin_lock_init(&qp->sq.lock);
718 spin_lock_init(&qp->rq.lock);
fa417f7b 719 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 720 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 721
722 qp->state = IB_QPS_RESET;
ea54b10c
JM		 723 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
724 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 725
0a1405da 726 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 727 if (err)
728 goto err;
729
730 if (pd->uobject) {
731 struct mlx4_ib_create_qp ucmd;
732
733 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
734 err = -EFAULT;
735 goto err;
736 }
737
0e6e7416
RD		 738 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
739
83904132 740 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 741 if (err)
742 goto err;
743
225c7b1f 744 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 745 qp->buf_size, 0, 0);
225c7b1f
RD		 746 if (IS_ERR(qp->umem)) {
747 err = PTR_ERR(qp->umem);
748 goto err;
749 }
750
751 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
752 ilog2(qp->umem->page_size), &qp->mtt);
753 if (err)
754 goto err_buf;
755
756 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
757 if (err)
758 goto err_mtt;
759
0a1405da 760 if (qp_has_rq(init_attr)) {
02d89b87
RD		 761 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
762 ucmd.db_addr, &qp->db);
763 if (err)
764 goto err_mtt;
765 }
225c7b1f 766 } else {
0e6e7416
RD		 767 qp->sq_no_prefetch = 0;
768
b832be1e
EC		 769 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
770 qp->flags |= MLX4_IB_QP_LSO;
771
c1c98501
MB		 772 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
773 if (dev->steering_support ==
774 MLX4_STEERING_MODE_DEVICE_MANAGED)
775 qp->flags |= MLX4_IB_QP_NETIF;
776 else
777 goto err;
778 }
779
73898db0
HA		 780 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
781 err = set_kernel_sq_size(dev, &init_attr->cap,
782 qp_type, qp, true);
2446304d
EC		 783 if (err)
784 goto err;
785
0a1405da 786 if (qp_has_rq(init_attr)) {
40f2287b 787 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 788 if (err)
789 goto err;
225c7b1f 790
02d89b87
RD		 791 *qp->db.db = 0;
792 }
225c7b1f 793
73898db0
HA		 794 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
795 &qp->buf, gfp)) {
796 memcpy(&init_attr->cap, &backup_cap,
797 sizeof(backup_cap));
798 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
799 qp, false);
800 if (err)
801 goto err_db;
802
803 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
804 PAGE_SIZE * 2, &qp->buf, gfp)) {
805 err = -ENOMEM;
806 goto err_db;
807 }
225c7b1f
RD		 808 }
809
810 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
811 &qp->mtt);
812 if (err)
813 goto err_buf;
814
40f2287b 815 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 816 if (err)
817 goto err_mtt;
818
ee370950 819 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
9afc60dc 820 gfp | __GFP_NOWARN);
0ef2f05c
WW		 821 if (!qp->sq.wrid)
822 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
823 gfp, PAGE_KERNEL);
ee370950 824 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
9afc60dc 825 gfp | __GFP_NOWARN);
0ef2f05c
WW		 826 if (!qp->rq.wrid)
827 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
828 gfp, PAGE_KERNEL);
225c7b1f
RD		 829 if (!qp->sq.wrid || !qp->rq.wrid) {
830 err = -ENOMEM;
831 goto err_wrid;
832 }
225c7b1f
RD		 833 }
834
a3cdcbfa 835 if (sqpn) {
1ffeb2eb
JM		 836 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
837 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
838 if (alloc_proxy_bufs(pd->device, qp)) {
839 err = -ENOMEM;
840 goto err_wrid;
841 }
842 }
a3cdcbfa 843 } else {
ddae0349
EE		 844 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
845 * otherwise, the WQE BlueFlame setup flow wrongly causes
846 * VLAN insertion. */
3987a2d3 847 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 848 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 849 (init_attr->cap.max_send_wr ?
850 MLX4_RESERVE_ETH_BF_QP : 0) |
851 (init_attr->cap.max_recv_wr ?
852 MLX4_RESERVE_A0_QP : 0));
3987a2d3 853 else
c1c98501
MB		 854 if (qp->flags & MLX4_IB_QP_NETIF)
855 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
856 else
857 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 858 &qpn, 0);
a3cdcbfa 859 if (err)
1ffeb2eb 860 goto err_proxy;
a3cdcbfa
YP		 861 }
862
fbfb6625
EBE		 863 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
864 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
865
40f2287b 866 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 867 if (err)
a3cdcbfa 868 goto err_qpn;
225c7b1f 869
0a1405da
SH		 870 if (init_attr->qp_type == IB_QPT_XRC_TGT)
871 qp->mqp.qpn |= (1 << 23);
872
225c7b1f
RD		 873 /*
874 * Hardware wants QPN written in big-endian order (after
875 * shifting) for send doorbell. Precompute this value to save
876 * a little bit when posting sends.
877 */
878 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
879
225c7b1f 880 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 881 if (!*caller_qp)
882 *caller_qp = qp;
35f05dab
YH		 883
884 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
885 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
886 to_mcq(init_attr->recv_cq));
887 /* Maintain device to QPs access, needed for further handling
888 * via reset flow
889 */
890 list_add_tail(&qp->qps_list, &dev->qp_list);
891 /* Maintain CQ to QPs access, needed for further handling
892 * via reset flow
893 */
894 mcq = to_mcq(init_attr->send_cq);
895 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
896 mcq = to_mcq(init_attr->recv_cq);
897 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
898 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
899 to_mcq(init_attr->recv_cq));
900 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 901 return 0;
902
a3cdcbfa 903err_qpn:
c1c98501
MB		 904 if (!sqpn) {
905 if (qp->flags & MLX4_IB_QP_NETIF)
906 mlx4_ib_steer_qp_free(dev, qpn, 1);
907 else
908 mlx4_qp_release_range(dev->dev, qpn, 1);
909 }
1ffeb2eb
JM		 910err_proxy:
911 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
912 free_proxy_bufs(pd->device, qp);
225c7b1f 913err_wrid:
23f1b384 914 if (pd->uobject) {
0a1405da
SH		 915 if (qp_has_rq(init_attr))
916 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 917 } else {
0ef2f05c
WW		 918 kvfree(qp->sq.wrid);
919 kvfree(qp->rq.wrid);
225c7b1f
RD		 920 }
921
922err_mtt:
923 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
924
925err_buf:
926 if (pd->uobject)
927 ib_umem_release(qp->umem);
928 else
929 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
930
931err_db:
0a1405da 932 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 933 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 934
935err:
b42dde47
BVA		 936 if (sqp)
937 kfree(sqp);
938 else if (!*caller_qp)
1ffeb2eb 939 kfree(qp);
225c7b1f
RD		 940 return err;
941}
942
943static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
944{
945 switch (state) {
946 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
947 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
948 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
949 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
950 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
951 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
952 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
953 default: return -1;
954 }
955}
956
957static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 958 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 959{
338a8fad 960 if (send_cq == recv_cq) {
35f05dab 961 spin_lock(&send_cq->lock);
338a8fad
RD		 962 __acquire(&recv_cq->lock);
963 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 964 spin_lock(&send_cq->lock);
225c7b1f
RD		 965 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
966 } else {
35f05dab 967 spin_lock(&recv_cq->lock);
225c7b1f
RD		 968 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
969 }
970}
971
972static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 973 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 974{
338a8fad
RD		 975 if (send_cq == recv_cq) {
976 __release(&recv_cq->lock);
35f05dab 977 spin_unlock(&send_cq->lock);
338a8fad 978 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 979 spin_unlock(&recv_cq->lock);
35f05dab 980 spin_unlock(&send_cq->lock);
225c7b1f
RD		 981 } else {
982 spin_unlock(&send_cq->lock);
35f05dab 983 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 984 }
985}
986
fa417f7b
EC		 987static void del_gid_entries(struct mlx4_ib_qp *qp)
988{
989 struct mlx4_ib_gid_entry *ge, *tmp;
990
991 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
992 list_del(&ge->list);
993 kfree(ge);
994 }
995}
996
0a1405da
SH		 997static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
998{
999 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1000 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1001 else
1002 return to_mpd(qp->ibqp.pd);
1003}
1004
1005static void get_cqs(struct mlx4_ib_qp *qp,
1006 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1007{
1008 switch (qp->ibqp.qp_type) {
1009 case IB_QPT_XRC_TGT:
1010 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1011 *recv_cq = *send_cq;
1012 break;
1013 case IB_QPT_XRC_INI:
1014 *send_cq = to_mcq(qp->ibqp.send_cq);
1015 *recv_cq = *send_cq;
1016 break;
1017 default:
1018 *send_cq = to_mcq(qp->ibqp.send_cq);
1019 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1020 break;
1021 }
1022}
1023
225c7b1f
RD		 1024static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1025 int is_user)
1026{
1027 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1028 unsigned long flags;
225c7b1f 1029
2f5bb473 1030 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1031 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1032 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1033 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1034 qp->mqp.qpn);
25476b02 1035 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1036 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1037 qp->pri.smac = 0;
25476b02 1038 qp->pri.smac_port = 0;
2f5bb473
JM		 1039 }
1040 if (qp->alt.smac) {
1041 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1042 qp->alt.smac = 0;
1043 }
1044 if (qp->pri.vid < 0x1000) {
1045 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1046 qp->pri.vid = 0xFFFF;
1047 qp->pri.candidate_vid = 0xFFFF;
1048 qp->pri.update_vid = 0;
1049 }
1050 if (qp->alt.vid < 0x1000) {
1051 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1052 qp->alt.vid = 0xFFFF;
1053 qp->alt.candidate_vid = 0xFFFF;
1054 qp->alt.update_vid = 0;
1055 }
1056 }
225c7b1f 1057
0a1405da 1058 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1059
35f05dab 1060 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1061 mlx4_ib_lock_cqs(send_cq, recv_cq);
1062
35f05dab
YH		 1063 /* del from lists under both locks above to protect reset flow paths */
1064 list_del(&qp->qps_list);
1065 list_del(&qp->cq_send_list);
1066 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1067 if (!is_user) {
1068 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1069 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1070 if (send_cq != recv_cq)
1071 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1072 }
1073
1074 mlx4_qp_remove(dev->dev, &qp->mqp);
1075
1076 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1077 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1078
1079 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1080
c1c98501
MB		 1081 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1082 if (qp->flags & MLX4_IB_QP_NETIF)
1083 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1084 else
1085 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1086 }
a3cdcbfa 1087
225c7b1f
RD		 1088 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1089
1090 if (is_user) {
0a1405da 1091 if (qp->rq.wqe_cnt)
02d89b87
RD		 1092 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1093 &qp->db);
225c7b1f
RD		 1094 ib_umem_release(qp->umem);
1095 } else {
0ef2f05c
WW		 1096 kvfree(qp->sq.wrid);
1097 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1098 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1099 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1100 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1101 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1102 if (qp->rq.wqe_cnt)
6296883c 1103 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1104 }
fa417f7b
EC		 1105
1106 del_gid_entries(qp);
225c7b1f
RD		 1107}
1108
47605df9
JM		 1109static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1110{
1111 /* Native or PPF */
1112 if (!mlx4_is_mfunc(dev->dev) ||
1113 (mlx4_is_master(dev->dev) &&
1114 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1115 return dev->dev->phys_caps.base_sqpn +
1116 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1117 attr->port_num - 1;
1118 }
1119 /* PF or VF -- creating proxies */
1120 if (attr->qp_type == IB_QPT_SMI)
1121 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1122 else
1123 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1124}
1125
e1b866c6
MS		 1126static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1127 struct ib_qp_init_attr *init_attr,
1128 struct ib_udata *udata)
225c7b1f 1129{
1ffeb2eb 1130 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1131 int err;
fbfb6625 1132 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1133 u16 xrcdn = 0;
40f2287b 1134 gfp_t gfp;
225c7b1f 1135
40f2287b
JK		 1136 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1137 GFP_NOIO : GFP_KERNEL;
521e575b 1138 /*
1ffeb2eb
JM		 1139 * We only support LSO, vendor flag1, and multicast loopback blocking,
1140 * and only for kernel UD QPs.
521e575b 1141 */
1ffeb2eb
JM		 1142 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1143 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1144 MLX4_IB_SRIOV_TUNNEL_QP |
1145 MLX4_IB_SRIOV_SQP |
40f2287b 1146 MLX4_IB_QP_NETIF |
e1b866c6 1147 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
40f2287b 1148 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1149 return ERR_PTR(-EINVAL);
521e575b 1150
c1c98501
MB		 1151 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1152 if (init_attr->qp_type != IB_QPT_UD)
1153 return ERR_PTR(-EINVAL);
1154 }
1155
e1b866c6
MS		 1156 if (init_attr->create_flags) {
1157 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1158 return ERR_PTR(-EINVAL);
1159
1160 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1161 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1162 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1163 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1164 init_attr->qp_type != IB_QPT_UD) ||
1165 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1166 init_attr->qp_type > IB_QPT_GSI) ||
1167 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1168 init_attr->qp_type != IB_QPT_GSI))
1169 return ERR_PTR(-EINVAL);
1170 }
b846f25a 1171
225c7b1f 1172 switch (init_attr->qp_type) {
0a1405da
SH		 1173 case IB_QPT_XRC_TGT:
1174 pd = to_mxrcd(init_attr->xrcd)->pd;
1175 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1176 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1177 /* fall through */
1178 case IB_QPT_XRC_INI:
1179 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1180 return ERR_PTR(-ENOSYS);
1181 init_attr->recv_cq = init_attr->send_cq;
1182 /* fall through */
225c7b1f
RD		 1183 case IB_QPT_RC:
1184 case IB_QPT_UC:
3987a2d3 1185 case IB_QPT_RAW_PACKET:
40f2287b 1186 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1187 if (!qp)
1188 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1189 qp->pri.vid = 0xFFFF;
1190 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1191 /* fall through */
1192 case IB_QPT_UD:
1193 {
1194 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1195 udata, 0, &qp, gfp);
5b420d9c
DB		 1196 if (err) {
1197 kfree(qp);
225c7b1f 1198 return ERR_PTR(err);
5b420d9c 1199 }
225c7b1f
RD		 1200
1201 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1202 qp->xrcdn = xrcdn;
225c7b1f
RD		 1203
1204 break;
1205 }
1206 case IB_QPT_SMI:
1207 case IB_QPT_GSI:
1208 {
e1b866c6
MS		 1209 int sqpn;
1210
225c7b1f 1211 /* Userspace is not allowed to create special QPs: */
0a1405da 1212 if (udata)
225c7b1f 1213 return ERR_PTR(-EINVAL);
e1b866c6
MS		 1214 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1215 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0);
1216
1217 if (res)
1218 return ERR_PTR(res);
1219 } else {
1220 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1221 }
225c7b1f 1222
0a1405da 1223 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
e1b866c6 1224 sqpn,
40f2287b 1225 &qp, gfp);
1ffeb2eb 1226 if (err)
225c7b1f 1227 return ERR_PTR(err);
225c7b1f
RD		 1228
1229 qp->port = init_attr->port_num;
e1b866c6
MS		 1230 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1231 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1232 break;
1233 }
1234 default:
1235 /* Don't support raw QPs */
1236 return ERR_PTR(-EINVAL);
1237 }
1238
1239 return &qp->ibqp;
1240}
1241
e1b866c6
MS		 1242struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1243 struct ib_qp_init_attr *init_attr,
1244 struct ib_udata *udata) {
1245 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1246 struct ib_qp *ibqp;
1247 struct mlx4_ib_dev *dev = to_mdev(device);
1248
1249 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1250
1251 if (!IS_ERR(ibqp) &&
1252 (init_attr->qp_type == IB_QPT_GSI) &&
1253 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1254 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1255 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1256
1257 if (is_eth &&
1258 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1259 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1260 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1261
1262 if (IS_ERR(sqp->roce_v2_gsi)) {
1263 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1264 sqp->roce_v2_gsi = NULL;
1265 } else {
1266 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1267 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1268 }
1269
1270 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1271 }
1272 }
1273 return ibqp;
1274}
1275
1276static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1277{
1278 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1279 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1280 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1281
1282 if (is_qp0(dev, mqp))
1283 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1284
c482af64
JM		 1285 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1286 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1287 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1288 dev->qp1_proxy[mqp->port - 1] = NULL;
1289 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1290 }
1291
7b59f0f9
EBE		 1292 if (mqp->counter_index)
1293 mlx4_ib_free_qp_counter(dev, mqp);
1294
0a1405da
SH		 1295 pd = get_pd(mqp);
1296 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1297
1298 if (is_sqp(dev, mqp))
1299 kfree(to_msqp(mqp));
1300 else
1301 kfree(mqp);
1302
1303 return 0;
1304}
1305
e1b866c6
MS		 1306int mlx4_ib_destroy_qp(struct ib_qp *qp)
1307{
1308 struct mlx4_ib_qp *mqp = to_mqp(qp);
1309
1310 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1311 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1312
1313 if (sqp->roce_v2_gsi)
1314 ib_destroy_qp(sqp->roce_v2_gsi);
1315 }
1316
1317 return _mlx4_ib_destroy_qp(qp);
1318}
1319
1ffeb2eb 1320static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1321{
1322 switch (type) {
1ffeb2eb
JM		 1323 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1324 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1325 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1326 case MLX4_IB_QPT_XRC_INI:
1327 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1328 case MLX4_IB_QPT_SMI:
1329 case MLX4_IB_QPT_GSI:
1330 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1331
1332 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1333 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1334 MLX4_QP_ST_MLX : -1);
1335 case MLX4_IB_QPT_PROXY_SMI:
1336 case MLX4_IB_QPT_TUN_SMI:
1337 case MLX4_IB_QPT_PROXY_GSI:
1338 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1339 MLX4_QP_ST_UD : -1);
1340 default: return -1;
225c7b1f
RD		 1341 }
1342}
1343
65adfa91 1344static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1345 int attr_mask)
1346{
1347 u8 dest_rd_atomic;
1348 u32 access_flags;
1349 u32 hw_access_flags = 0;
1350
1351 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1352 dest_rd_atomic = attr->max_dest_rd_atomic;
1353 else
1354 dest_rd_atomic = qp->resp_depth;
1355
1356 if (attr_mask & IB_QP_ACCESS_FLAGS)
1357 access_flags = attr->qp_access_flags;
1358 else
1359 access_flags = qp->atomic_rd_en;
1360
1361 if (!dest_rd_atomic)
1362 access_flags &= IB_ACCESS_REMOTE_WRITE;
1363
1364 if (access_flags & IB_ACCESS_REMOTE_READ)
1365 hw_access_flags |= MLX4_QP_BIT_RRE;
1366 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1367 hw_access_flags |= MLX4_QP_BIT_RAE;
1368 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1369 hw_access_flags |= MLX4_QP_BIT_RWE;
1370
1371 return cpu_to_be32(hw_access_flags);
1372}
1373
65adfa91 1374static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1375 int attr_mask)
1376{
1377 if (attr_mask & IB_QP_PKEY_INDEX)
1378 sqp->pkey_index = attr->pkey_index;
1379 if (attr_mask & IB_QP_QKEY)
1380 sqp->qkey = attr->qkey;
1381 if (attr_mask & IB_QP_SQ_PSN)
1382 sqp->send_psn = attr->sq_psn;
1383}
1384
1385static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1386{
1387 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1388}
1389
297e0dad
MS		 1390static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1391 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1392 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1393{
fa417f7b
EC		 1394 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1395 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1396 int vidx;
297e0dad 1397 int smac_index;
2f5bb473 1398 int err;
297e0dad 1399
fa417f7b 1400
225c7b1f
RD		 1401 path->grh_mylmc = ah->src_path_bits & 0x7f;
1402 path->rlid = cpu_to_be16(ah->dlid);
1403 if (ah->static_rate) {
1404 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1405 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1406 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1407 --path->static_rate;
1408 } else
1409 path->static_rate = 0;
225c7b1f
RD		 1410
1411 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1412 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1413 port,
1414 ah->grh.sgid_index);
1415
1416 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1417 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1418 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1419 return -1;
1420 }
1421
1422 path->grh_mylmc |= 1 << 7;
5070cd22 1423 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1424 path->hop_limit = ah->grh.hop_limit;
1425 path->tclass_flowlabel =
1426 cpu_to_be32((ah->grh.traffic_class << 20) |
1427 (ah->grh.flow_label));
1428 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1429 }
1430
fa417f7b
EC		 1431 if (is_eth) {
1432 if (!(ah->ah_flags & IB_AH_GRH))
1433 return -1;
1434
2f5bb473
JM		 1435 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1436 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1437
297e0dad 1438 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1439 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1440 if (smac_info->vid < 0x1000) {
1441 /* both valid vlan ids */
1442 if (smac_info->vid != vlan_tag) {
1443 /* different VIDs. unreg old and reg new */
1444 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1445 if (err)
1446 return err;
1447 smac_info->candidate_vid = vlan_tag;
1448 smac_info->candidate_vlan_index = vidx;
1449 smac_info->candidate_vlan_port = port;
1450 smac_info->update_vid = 1;
1451 path->vlan_index = vidx;
1452 } else {
1453 path->vlan_index = smac_info->vlan_index;
1454 }
1455 } else {
1456 /* no current vlan tag in qp */
1457 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1458 if (err)
1459 return err;
1460 smac_info->candidate_vid = vlan_tag;
1461 smac_info->candidate_vlan_index = vidx;
1462 smac_info->candidate_vlan_port = port;
1463 smac_info->update_vid = 1;
1464 path->vlan_index = vidx;
1465 }
297e0dad 1466 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1467 path->fl = 1 << 6;
1468 } else {
1469 /* have current vlan tag. unregister it at modify-qp success */
1470 if (smac_info->vid < 0x1000) {
1471 smac_info->candidate_vid = 0xFFFF;
1472 smac_info->update_vid = 1;
1473 }
4c3eb3ca 1474 }
2f5bb473
JM		 1475
1476 /* get smac_index for RoCE use.
1477 * If no smac was yet assigned, register one.
1478 * If one was already assigned, but the new mac differs,
1479 * unregister the old one and register the new one.
1480 */
25476b02
JM		 1481 if ((!smac_info->smac && !smac_info->smac_port) ||
1482 smac_info->smac != smac) {
2f5bb473
JM		 1483 /* register candidate now, unreg if needed, after success */
1484 smac_index = mlx4_register_mac(dev->dev, port, smac);
1485 if (smac_index >= 0) {
1486 smac_info->candidate_smac_index = smac_index;
1487 smac_info->candidate_smac = smac;
1488 smac_info->candidate_smac_port = port;
1489 } else {
1490 return -EINVAL;
1491 }
1492 } else {
1493 smac_index = smac_info->smac_index;
1494 }
1495
1496 memcpy(path->dmac, ah->dmac, 6);
1497 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1498 /* put MAC table smac index for IBoE */
1499 path->grh_mylmc = (u8) (smac_index) | 0x80;
1500 } else {
4c3eb3ca
EC		 1501 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1502 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1503 }
fa417f7b 1504
225c7b1f
RD		 1505 return 0;
1506}
1507
297e0dad
MS		 1508static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1509 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1510 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1511 struct mlx4_qp_path *path, u8 port,
1512 u16 vlan_id, u8 *smac)
297e0dad
MS		 1513{
1514 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1515 mlx4_mac_to_u64(smac),
1516 vlan_id,
2f5bb473 1517 path, &mqp->pri, port);
297e0dad
MS		 1518}
1519
1520static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1521 const struct ib_qp_attr *qp,
1522 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1523 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1524 struct mlx4_qp_path *path, u8 port)
1525{
1526 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1527 0,
1528 0xffff,
2f5bb473 1529 path, &mqp->alt, port);
297e0dad
MS		 1530}
1531
fa417f7b
EC		 1532static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1533{
1534 struct mlx4_ib_gid_entry *ge, *tmp;
1535
1536 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1537 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1538 ge->added = 1;
1539 ge->port = qp->port;
1540 }
1541 }
1542}
1543
dbf727de
MB		 1544static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1545 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1546 struct mlx4_qp_context *context)
1547{
2f5bb473
JM		 1548 u64 u64_mac;
1549 int smac_index;
1550
3e0629cb 1551 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1552
1553 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1554 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1555 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1556 if (smac_index >= 0) {
1557 qp->pri.candidate_smac_index = smac_index;
1558 qp->pri.candidate_smac = u64_mac;
1559 qp->pri.candidate_smac_port = qp->port;
1560 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1561 } else {
1562 return -ENOENT;
1563 }
1564 }
1565 return 0;
1566}
1567
7b59f0f9
EBE		 1568static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1569{
1570 struct counter_index *new_counter_index;
1571 int err;
1572 u32 tmp_idx;
1573
1574 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1575 IB_LINK_LAYER_ETHERNET ||
1576 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1577 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1578 return 0;
1579
1580 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1581 if (err)
1582 return err;
1583
1584 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1585 if (!new_counter_index) {
1586 mlx4_counter_free(dev->dev, tmp_idx);
1587 return -ENOMEM;
1588 }
1589
1590 new_counter_index->index = tmp_idx;
1591 new_counter_index->allocated = 1;
1592 qp->counter_index = new_counter_index;
1593
1594 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1595 list_add_tail(&new_counter_index->list,
1596 &dev->counters_table[qp->port - 1].counters_list);
1597 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1598
1599 return 0;
1600}
1601
3b5daf28
MS		 1602enum {
1603 MLX4_QPC_ROCE_MODE_1 = 0,
1604 MLX4_QPC_ROCE_MODE_2 = 2,
1605 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1606};
1607
1608static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1609{
1610 switch (gid_type) {
1611 case IB_GID_TYPE_ROCE:
1612 return MLX4_QPC_ROCE_MODE_1;
1613 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1614 return MLX4_QPC_ROCE_MODE_2;
1615 default:
1616 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1617 }
1618}
1619
65adfa91
MT		 1620static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1621 const struct ib_qp_attr *attr, int attr_mask,
1622 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1623{
1624 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1625 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1626 struct mlx4_ib_pd *pd;
1627 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1628 struct mlx4_qp_context *context;
1629 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1630 int sqd_event;
c1c98501 1631 int steer_qp = 0;
225c7b1f 1632 int err = -EINVAL;
3ba8e31d 1633 int counter_index;
225c7b1f 1634
3dec4878
JM		 1635 /* APM is not supported under RoCE */
1636 if (attr_mask & IB_QP_ALT_PATH &&
1637 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1638 IB_LINK_LAYER_ETHERNET)
1639 return -ENOTSUPP;
1640
225c7b1f
RD		 1641 context = kzalloc(sizeof *context, GFP_KERNEL);
1642 if (!context)
1643 return -ENOMEM;
1644
225c7b1f 1645 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1646 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1647
1648 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1649 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1650 else {
1651 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1652 switch (attr->path_mig_state) {
1653 case IB_MIG_MIGRATED:
1654 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1655 break;
1656 case IB_MIG_REARM:
1657 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1658 break;
1659 case IB_MIG_ARMED:
1660 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1661 break;
1662 }
1663 }
1664
b832be1e 1665 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1666 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1667 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1668 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1669 else if (ibqp->qp_type == IB_QPT_UD) {
1670 if (qp->flags & MLX4_IB_QP_LSO)
1671 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1672 ilog2(dev->dev->caps.max_gso_sz);
1673 else
6e0d733d 1674 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1675 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1676 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1677 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1678 attr->path_mtu);
f5b40431 1679 goto out;
225c7b1f 1680 }
d1f2cd89
EC		 1681 context->mtu_msgmax = (attr->path_mtu << 5) |
1682 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1683 }
1684
0e6e7416
RD		 1685 if (qp->rq.wqe_cnt)
1686 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1687 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1688
0e6e7416
RD		 1689 if (qp->sq.wqe_cnt)
1690 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1691 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1692
7b59f0f9
EBE		 1693 if (new_state == IB_QPS_RESET && qp->counter_index)
1694 mlx4_ib_free_qp_counter(dev, qp);
1695
0a1405da 1696 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1697 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1698 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1699 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1700 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1701 }
0e6e7416 1702
225c7b1f 1703 if (qp->ibqp.uobject)
85743f1e
HN		 1704 context->usr_page = cpu_to_be32(
1705 mlx4_to_hw_uar_index(dev->dev,
1706 to_mucontext(ibqp->uobject->context)->uar.index));
225c7b1f 1707 else
85743f1e
HN		 1708 context->usr_page = cpu_to_be32(
1709 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 1710
1711 if (attr_mask & IB_QP_DEST_QPN)
1712 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1713
1714 if (attr_mask & IB_QP_PORT) {
1715 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1716 !(attr_mask & IB_QP_AV)) {
1717 mlx4_set_sched(&context->pri_path, attr->port_num);
1718 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1719 }
1720 }
1721
cfcde11c 1722 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1723 err = create_qp_lb_counter(dev, qp);
1724 if (err)
1725 goto out;
1726
3ba8e31d
EBE		 1727 counter_index =
1728 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1729 if (qp->counter_index)
1730 counter_index = qp->counter_index->index;
1731
3ba8e31d
EBE		 1732 if (counter_index != -1) {
1733 context->pri_path.counter_index = counter_index;
cfcde11c 1734 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1735 if (qp->counter_index) {
1736 context->pri_path.fl |=
1737 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1738 context->pri_path.vlan_control |=
1739 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1740 }
cfcde11c 1741 } else
47d8417f
EBE		 1742 context->pri_path.counter_index =
1743 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1744
1745 if (qp->flags & MLX4_IB_QP_NETIF) {
1746 mlx4_ib_steer_qp_reg(dev, qp, 1);
1747 steer_qp = 1;
1748 }
e1b866c6
MS		 1749
1750 if (ibqp->qp_type == IB_QPT_GSI) {
1751 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
1752 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
1753 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
1754
1755 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1756 }
cfcde11c
OG		 1757 }
1758
225c7b1f 1759 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1760 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1761 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1762 context->pri_path.pkey_index = attr->pkey_index;
1763 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1764 }
1765
225c7b1f 1766 if (attr_mask & IB_QP_AV) {
dbf727de
MB		 1767 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1768 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1769 union ib_gid gid;
bf08e884 1770 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
dbf727de
MB		 1771 u16 vlan = 0xffff;
1772 u8 smac[ETH_ALEN];
1773 int status = 0;
3b5daf28
MS		 1774 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1775 attr->ah_attr.ah_flags & IB_AH_GRH;
dbf727de 1776
bf08e884 1777 if (is_eth && attr->ah_attr.ah_flags & IB_AH_GRH) {
dbf727de
MB		 1778 int index = attr->ah_attr.grh.sgid_index;
1779
1780 status = ib_get_cached_gid(ibqp->device, port_num,
1781 index, &gid, &gid_attr);
1782 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1783 status = -ENOENT;
1784 if (!status && gid_attr.ndev) {
1785 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1786 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1787 dev_put(gid_attr.ndev);
1788 }
1789 }
1790 if (status)
1791 goto out;
1792
2f5bb473 1793 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 1794 port_num, vlan, smac))
225c7b1f 1795 goto out;
225c7b1f
RD		 1796
1797 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1798 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 1799
1800 if (is_eth &&
1801 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1802 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1803
1804 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1805 err = -EINVAL;
1806 goto out;
1807 }
1808 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1809 }
1810
225c7b1f
RD		 1811 }
1812
1813 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1814 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1815 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1816 }
1817
1818 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1819 if (attr->alt_port_num == 0 ||
1820 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1821 goto out;
225c7b1f 1822
5ae2a7a8
RD		 1823 if (attr->alt_pkey_index >=
1824 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1825 goto out;
5ae2a7a8 1826
2f5bb473
JM		 1827 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1828 &context->alt_path,
297e0dad 1829 attr->alt_port_num))
f5b40431 1830 goto out;
225c7b1f
RD		 1831
1832 context->alt_path.pkey_index = attr->alt_pkey_index;
1833 context->alt_path.ackto = attr->alt_timeout << 3;
1834 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1835 }
1836
0a1405da
SH		 1837 pd = get_pd(qp);
1838 get_cqs(qp, &send_cq, &recv_cq);
1839 context->pd = cpu_to_be32(pd->pdn);
1840 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1841 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1842 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1843
95d04f07
RD		 1844 /* Set "fast registration enabled" for all kernel QPs */
1845 if (!qp->ibqp.uobject)
1846 context->params1 |= cpu_to_be32(1 << 11);
1847
57f01b53
JM		 1848 if (attr_mask & IB_QP_RNR_RETRY) {
1849 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1850 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1851 }
1852
225c7b1f
RD		 1853 if (attr_mask & IB_QP_RETRY_CNT) {
1854 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1855 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1856 }
1857
1858 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1859 if (attr->max_rd_atomic)
1860 context->params1 |=
1861 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1862 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1863 }
1864
1865 if (attr_mask & IB_QP_SQ_PSN)
1866 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1867
225c7b1f
RD		 1868 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1869 if (attr->max_dest_rd_atomic)
1870 context->params2 |=
1871 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1872 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1873 }
1874
1875 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1876 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1877 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1878 }
1879
1880 if (ibqp->srq)
1881 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1882
1883 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1884 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1885 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1886 }
1887 if (attr_mask & IB_QP_RQ_PSN)
1888 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1889
1ffeb2eb 1890 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1891 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1892 if (qp->mlx4_ib_qp_type &
1893 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1894 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1895 else {
1896 if (mlx4_is_mfunc(dev->dev) &&
1897 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1898 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1899 MLX4_RESERVED_QKEY_BASE) {
1900 pr_err("Cannot use reserved QKEY"
1901 " 0x%x (range 0xffff0000..0xffffffff"
1902 " is reserved)\n", attr->qkey);
1903 err = -EINVAL;
1904 goto out;
1905 }
1906 context->qkey = cpu_to_be32(attr->qkey);
1907 }
225c7b1f
RD		 1908 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1909 }
1910
1911 if (ibqp->srq)
1912 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1913
0a1405da 1914 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1915 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1916
1917 if (cur_state == IB_QPS_INIT &&
1918 new_state == IB_QPS_RTR &&
1919 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1920 ibqp->qp_type == IB_QPT_UD ||
1921 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1922 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1923 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1924 qp->mlx4_ib_qp_type &
1925 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1926 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1927 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1928 context->pri_path.fl = 0x80;
1929 } else {
1930 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1931 context->pri_path.fl = 0x80;
225c7b1f 1932 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1933 }
2f5bb473
JM		 1934 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1935 IB_LINK_LAYER_ETHERNET) {
1936 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1937 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1938 context->pri_path.feup = 1 << 7; /* don't fsm */
1939 /* handle smac_index */
1940 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1941 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1942 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 1943 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 1944 if (err) {
1945 err = -EINVAL;
1946 goto out;
1947 }
9433c188
MB		 1948 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1949 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1950 }
1951 }
225c7b1f
RD		 1952 }
1953
d2fce8a9 1954 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1955 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1956 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1957 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1958 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1959 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1960 context->srqn = cpu_to_be32(7 << 28);
1961 }
1962 }
3528f696 1963
297e0dad
MS		 1964 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1965 int is_eth = rdma_port_get_link_layer(
1966 &dev->ib_dev, qp->port) ==
1967 IB_LINK_LAYER_ETHERNET;
1968 if (is_eth) {
1969 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1970 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1971 }
1972 }
1973
1974
225c7b1f
RD		 1975 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1976 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1977 sqd_event = 1;
1978 else
1979 sqd_event = 0;
1980
d57f5f72 1981 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3b5daf28 1982 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 1983
c0be5fb5
EC		 1984 /*
1985 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1986 * ownership bits of the send queue are set and the SQ
1987 * headroom is stamped so that the hardware doesn't start
1988 * processing stale work requests.
c0be5fb5
EC		 1989 */
1990 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1991 struct mlx4_wqe_ctrl_seg *ctrl;
1992 int i;
1993
0e6e7416 1994 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1995 ctrl = get_send_wqe(qp, i);
1996 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553 1997 if (qp->sq_max_wqes_per_wr == 1)
224e92e0
BB		 1998 ctrl->qpn_vlan.fence_size =
1999 1 << (qp->sq.wqe_shift - 4);
0e6e7416 2000
ea54b10c 2001 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 2002 }
2003 }
2004
225c7b1f
RD		 2005 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2006 to_mlx4_state(new_state), context, optpar,
2007 sqd_event, &qp->mqp);
2008 if (err)
2009 goto out;
2010
2011 qp->state = new_state;
2012
2013 if (attr_mask & IB_QP_ACCESS_FLAGS)
2014 qp->atomic_rd_en = attr->qp_access_flags;
2015 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2016 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2017 if (attr_mask & IB_QP_PORT) {
225c7b1f 2018 qp->port = attr->port_num;
fa417f7b
EC		 2019 update_mcg_macs(dev, qp);
2020 }
225c7b1f
RD		 2021 if (attr_mask & IB_QP_ALT_PATH)
2022 qp->alt_port = attr->alt_port_num;
2023
2024 if (is_sqp(dev, qp))
2025 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2026
2027 /*
2028 * If we moved QP0 to RTR, bring the IB link up; if we moved
2029 * QP0 to RESET or ERROR, bring the link back down.
2030 */
2031 if (is_qp0(dev, qp)) {
2032 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2033 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2034 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2035 qp->port);
225c7b1f
RD		 2036
2037 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2038 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2039 mlx4_CLOSE_PORT(dev->dev, qp->port);
2040 }
2041
2042 /*
2043 * If we moved a kernel QP to RESET, clean up all old CQ
2044 * entries and reinitialize the QP.
2045 */
2f5bb473
JM		 2046 if (new_state == IB_QPS_RESET) {
2047 if (!ibqp->uobject) {
2048 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2049 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2050 if (send_cq != recv_cq)
2051 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2052
2053 qp->rq.head = 0;
2054 qp->rq.tail = 0;
2055 qp->sq.head = 0;
2056 qp->sq.tail = 0;
2057 qp->sq_next_wqe = 0;
2058 if (qp->rq.wqe_cnt)
2059 *qp->db.db = 0;
225c7b1f 2060
2f5bb473
JM		 2061 if (qp->flags & MLX4_IB_QP_NETIF)
2062 mlx4_ib_steer_qp_reg(dev, qp, 0);
2063 }
25476b02 2064 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2065 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2066 qp->pri.smac = 0;
25476b02 2067 qp->pri.smac_port = 0;
2f5bb473
JM		 2068 }
2069 if (qp->alt.smac) {
2070 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2071 qp->alt.smac = 0;
2072 }
2073 if (qp->pri.vid < 0x1000) {
2074 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2075 qp->pri.vid = 0xFFFF;
2076 qp->pri.candidate_vid = 0xFFFF;
2077 qp->pri.update_vid = 0;
2078 }
c1c98501 2079
2f5bb473
JM		 2080 if (qp->alt.vid < 0x1000) {
2081 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2082 qp->alt.vid = 0xFFFF;
2083 qp->alt.candidate_vid = 0xFFFF;
2084 qp->alt.update_vid = 0;
2085 }
225c7b1f 2086 }
225c7b1f 2087out:
7b59f0f9
EBE		 2088 if (err && qp->counter_index)
2089 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2090 if (err && steer_qp)
2091 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2092 kfree(context);
25476b02
JM		 2093 if (qp->pri.candidate_smac ||
2094 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2095 if (err) {
2096 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2097 } else {
25476b02 2098 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2099 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2100 qp->pri.smac = qp->pri.candidate_smac;
2101 qp->pri.smac_index = qp->pri.candidate_smac_index;
2102 qp->pri.smac_port = qp->pri.candidate_smac_port;
2103 }
2104 qp->pri.candidate_smac = 0;
2105 qp->pri.candidate_smac_index = 0;
2106 qp->pri.candidate_smac_port = 0;
2107 }
2108 if (qp->alt.candidate_smac) {
2109 if (err) {
2110 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2111 } else {
2112 if (qp->alt.smac)
2113 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2114 qp->alt.smac = qp->alt.candidate_smac;
2115 qp->alt.smac_index = qp->alt.candidate_smac_index;
2116 qp->alt.smac_port = qp->alt.candidate_smac_port;
2117 }
2118 qp->alt.candidate_smac = 0;
2119 qp->alt.candidate_smac_index = 0;
2120 qp->alt.candidate_smac_port = 0;
2121 }
2122
2123 if (qp->pri.update_vid) {
2124 if (err) {
2125 if (qp->pri.candidate_vid < 0x1000)
2126 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2127 qp->pri.candidate_vid);
2128 } else {
2129 if (qp->pri.vid < 0x1000)
2130 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2131 qp->pri.vid);
2132 qp->pri.vid = qp->pri.candidate_vid;
2133 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2134 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2135 }
2136 qp->pri.candidate_vid = 0xFFFF;
2137 qp->pri.update_vid = 0;
2138 }
2139
2140 if (qp->alt.update_vid) {
2141 if (err) {
2142 if (qp->alt.candidate_vid < 0x1000)
2143 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2144 qp->alt.candidate_vid);
2145 } else {
2146 if (qp->alt.vid < 0x1000)
2147 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2148 qp->alt.vid);
2149 qp->alt.vid = qp->alt.candidate_vid;
2150 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2151 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2152 }
2153 qp->alt.candidate_vid = 0xFFFF;
2154 qp->alt.update_vid = 0;
2155 }
2156
225c7b1f
RD		 2157 return err;
2158}
2159
e1b866c6
MS		 2160static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2161 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2162{
2163 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2164 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2165 enum ib_qp_state cur_state, new_state;
2166 int err = -EINVAL;
297e0dad 2167 int ll;
65adfa91
MT		 2168 mutex_lock(&qp->mutex);
2169
2170 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2171 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2172
297e0dad
MS		 2173 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2174 ll = IB_LINK_LAYER_UNSPECIFIED;
2175 } else {
2176 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2177 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2178 }
dd5f03be
MB		 2179
2180 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2181 attr_mask, ll)) {
b1d8eb5a
JM		 2182 pr_debug("qpn 0x%x: invalid attribute mask specified "
2183 "for transition %d to %d. qp_type %d,"
2184 " attr_mask 0x%x\n",
2185 ibqp->qp_num, cur_state, new_state,
2186 ibqp->qp_type, attr_mask);
65adfa91 2187 goto out;
b1d8eb5a 2188 }
65adfa91 2189
c6215745
MS		 2190 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2191 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2192 if ((ibqp->qp_type == IB_QPT_RC) ||
2193 (ibqp->qp_type == IB_QPT_UD) ||
2194 (ibqp->qp_type == IB_QPT_UC) ||
2195 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2196 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2197 attr->port_num = mlx4_ib_bond_next_port(dev);
2198 }
2199 } else {
2200 /* no sense in changing port_num
2201 * when ports are bonded */
2202 attr_mask &= ~IB_QP_PORT;
2203 }
2204 }
2205
65adfa91 2206 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2207 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2208 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2209 "for transition %d to %d. qp_type %d\n",
2210 ibqp->qp_num, attr->port_num, cur_state,
2211 new_state, ibqp->qp_type);
65adfa91
MT		 2212 goto out;
2213 }
2214
3987a2d3
OG		 2215 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2216 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2217 IB_LINK_LAYER_ETHERNET))
2218 goto out;
2219
5ae2a7a8
RD		 2220 if (attr_mask & IB_QP_PKEY_INDEX) {
2221 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2222 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2223 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2224 "for transition %d to %d. qp_type %d\n",
2225 ibqp->qp_num, attr->pkey_index, cur_state,
2226 new_state, ibqp->qp_type);
5ae2a7a8 2227 goto out;
b1d8eb5a 2228 }
5ae2a7a8
RD		 2229 }
2230
65adfa91
MT		 2231 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2232 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2233 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2234 "Transition %d to %d. qp_type %d\n",
2235 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2236 new_state, ibqp->qp_type);
65adfa91
MT		 2237 goto out;
2238 }
2239
2240 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2241 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2242 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2243 "Transition %d to %d. qp_type %d\n",
2244 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2245 new_state, ibqp->qp_type);
65adfa91
MT		 2246 goto out;
2247 }
2248
2249 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2250 err = 0;
2251 goto out;
2252 }
2253
65adfa91
MT		 2254 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2255
c6215745
MS		 2256 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2257 attr->port_num = 1;
2258
65adfa91
MT		 2259out:
2260 mutex_unlock(&qp->mutex);
2261 return err;
2262}
2263
e1b866c6
MS		 2264int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2265 int attr_mask, struct ib_udata *udata)
2266{
2267 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2268 int ret;
2269
2270 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2271
2272 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2273 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2274 int err = 0;
2275
2276 if (sqp->roce_v2_gsi)
2277 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2278 if (err)
2279 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2280 err);
2281 }
2282 return ret;
2283}
2284
99ec41d0
JM		 2285static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2286{
2287 int i;
2288 for (i = 0; i < dev->caps.num_ports; i++) {
2289 if (qpn == dev->caps.qp0_proxy[i] ||
2290 qpn == dev->caps.qp0_tunnel[i]) {
2291 *qkey = dev->caps.qp0_qkey[i];
2292 return 0;
2293 }
2294 }
2295 return -EINVAL;
2296}
2297
1ffeb2eb 2298static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2299 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2300 void *wqe, unsigned *mlx_seg_len)
2301{
2302 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2303 struct ib_device *ib_dev = &mdev->ib_dev;
2304 struct mlx4_wqe_mlx_seg *mlx = wqe;
2305 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2306 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2307 u16 pkey;
2308 u32 qkey;
2309 int send_size;
2310 int header_size;
2311 int spc;
2312 int i;
2313
e622f2f4 2314 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2315 return -EINVAL;
2316
2317 send_size = 0;
2318
e622f2f4
CH		 2319 for (i = 0; i < wr->wr.num_sge; ++i)
2320 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2321
2322 /* for proxy-qp0 sends, need to add in size of tunnel header */
2323 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2324 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2325 send_size += sizeof (struct mlx4_ib_tunnel_header);
2326
25f40220 2327 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2328
2329 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2330 sqp->ud_header.lrh.service_level =
2331 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2332 sqp->ud_header.lrh.destination_lid =
2333 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2334 sqp->ud_header.lrh.source_lid =
2335 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2336 }
2337
2338 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2339
2340 /* force loopback */
2341 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2342 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2343
2344 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2345 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2346 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2347 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2348 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2349 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2350 else
2351 sqp->ud_header.bth.destination_qpn =
47605df9 2352 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2353
2354 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2355 if (mlx4_is_master(mdev->dev)) {
2356 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2357 return -EINVAL;
2358 } else {
2359 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2360 return -EINVAL;
2361 }
1ffeb2eb
JM		 2362 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2363 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2364
2365 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2366 sqp->ud_header.immediate_present = 0;
2367
2368 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2369
2370 /*
2371 * Inline data segments may not cross a 64 byte boundary. If
2372 * our UD header is bigger than the space available up to the
2373 * next 64 byte boundary in the WQE, use two inline data
2374 * segments to hold the UD header.
2375 */
2376 spc = MLX4_INLINE_ALIGN -
2377 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2378 if (header_size <= spc) {
2379 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2380 memcpy(inl + 1, sqp->header_buf, header_size);
2381 i = 1;
2382 } else {
2383 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2384 memcpy(inl + 1, sqp->header_buf, spc);
2385
2386 inl = (void *) (inl + 1) + spc;
2387 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2388 /*
2389 * Need a barrier here to make sure all the data is
2390 * visible before the byte_count field is set.
2391 * Otherwise the HCA prefetcher could grab the 64-byte
2392 * chunk with this inline segment and get a valid (!=
2393 * 0xffffffff) byte count but stale data, and end up
2394 * generating a packet with bad headers.
2395 *
2396 * The first inline segment's byte_count field doesn't
2397 * need a barrier, because it comes after a
2398 * control/MLX segment and therefore is at an offset
2399 * of 16 mod 64.
2400 */
2401 wmb();
2402 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2403 i = 2;
2404 }
2405
2406 *mlx_seg_len =
2407 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2408 return 0;
2409}
2410
fd10ed8e
JM		 2411static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2412{
2413 union sl2vl_tbl_to_u64 tmp_vltab;
2414 u8 vl;
2415
2416 if (sl > 15)
2417 return 0xf;
2418 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2419 vl = tmp_vltab.sl8[sl >> 1];
2420 if (sl & 1)
2421 vl &= 0x0f;
2422 else
2423 vl >>= 4;
2424 return vl;
2425}
2426
3ef967a4 2427#define MLX4_ROCEV2_QP1_SPORT 0xC000
e622f2f4 2428static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 2429 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2430{
a478868a 2431 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2432 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2433 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2434 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2435 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2436 union ib_gid sgid;
225c7b1f
RD		 2437 u16 pkey;
2438 int send_size;
2439 int header_size;
e61ef241 2440 int spc;
225c7b1f 2441 int i;
1ffeb2eb 2442 int err = 0;
57d88cff 2443 u16 vlan = 0xffff;
a29bec12
RD		 2444 bool is_eth;
2445 bool is_vlan = false;
2446 bool is_grh;
3ef967a4
MS		 2447 bool is_udp = false;
2448 int ip_version = 0;
225c7b1f
RD		 2449
2450 send_size = 0;
e622f2f4
CH		 2451 for (i = 0; i < wr->wr.num_sge; ++i)
2452 send_size += wr->wr.sg_list[i].length;
225c7b1f 2453
fa417f7b
EC		 2454 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2455 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2456 if (is_eth) {
3ef967a4
MS		 2457 struct ib_gid_attr gid_attr;
2458
1ffeb2eb
JM		 2459 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2460 /* When multi-function is enabled, the ib_core gid
2461 * indexes don't necessarily match the hw ones, so
2462 * we must use our own cache */
6ee51a4e
JM		 2463 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2464 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2465 ah->av.ib.gid_index, &sgid.raw[0]);
2466 if (err)
2467 return err;
1ffeb2eb
JM		 2468 } else {
2469 err = ib_get_cached_gid(ib_dev,
2470 be32_to_cpu(ah->av.ib.port_pd) >> 24,
55ee3ab2 2471 ah->av.ib.gid_index, &sgid,
3ef967a4
MS		 2472 &gid_attr);
2473 if (!err) {
2474 if (gid_attr.ndev)
2475 dev_put(gid_attr.ndev);
2476 if (!memcmp(&sgid, &zgid, sizeof(sgid)))
2477 err = -ENOENT;
2478 }
2479 if (!err) {
2480 is_udp = gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2481 if (is_udp) {
2482 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2483 ip_version = 4;
2484 else
2485 ip_version = 6;
2486 is_grh = false;
2487 }
2488 } else {
1ffeb2eb 2489 return err;
3ef967a4 2490 }
1ffeb2eb 2491 }
0e9855db 2492 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2493 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2494 is_vlan = 1;
2495 }
4c3eb3ca 2496 }
25f40220 2497 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 2498 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 2499 if (err)
2500 return err;
fa417f7b
EC		 2501
2502 if (!is_eth) {
2503 sqp->ud_header.lrh.service_level =
2504 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2505 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2506 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2507 }
225c7b1f 2508
3ef967a4 2509 if (is_grh || (ip_version == 6)) {
225c7b1f 2510 sqp->ud_header.grh.traffic_class =
fa417f7b 2511 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2512 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2513 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2514 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 2515 if (is_eth) {
6ee51a4e 2516 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 2517 } else {
2518 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2519 /* When multi-function is enabled, the ib_core gid
2520 * indexes don't necessarily match the hw ones, so
2521 * we must use our own cache
2522 */
2523 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 2524 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
2525 demux[sqp->qp.port - 1].
2526 subnet_prefix)));
baa0be70
JM		 2527 sqp->ud_header.grh.source_gid.global.interface_id =
2528 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2529 guid_cache[ah->av.ib.gid_index];
2530 } else {
2531 ib_get_cached_gid(ib_dev,
2532 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2533 ah->av.ib.gid_index,
2534 &sqp->ud_header.grh.source_gid, NULL);
2535 }
6ee51a4e 2536 }
225c7b1f 2537 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2538 ah->av.ib.dgid, 16);
225c7b1f
RD		 2539 }
2540
3ef967a4
MS		 2541 if (ip_version == 4) {
2542 sqp->ud_header.ip4.tos =
2543 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2544 sqp->ud_header.ip4.id = 0;
2545 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2546 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2547
2548 memcpy(&sqp->ud_header.ip4.saddr,
2549 sgid.raw + 12, 4);
2550 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2551 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2552 }
2553
2554 if (is_udp) {
2555 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2556 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2557 sqp->ud_header.udp.csum = 0;
2558 }
2559
225c7b1f 2560 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2561
2562 if (!is_eth) {
2563 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2564 (sqp->ud_header.lrh.destination_lid ==
2565 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2566 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2567 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2568 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2569 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2570 }
225c7b1f 2571
e622f2f4 2572 switch (wr->wr.opcode) {
225c7b1f
RD		 2573 case IB_WR_SEND:
2574 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2575 sqp->ud_header.immediate_present = 0;
2576 break;
2577 case IB_WR_SEND_WITH_IMM:
2578 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2579 sqp->ud_header.immediate_present = 1;
e622f2f4 2580 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 2581 break;
2582 default:
2583 return -EINVAL;
2584 }
2585
fa417f7b 2586 if (is_eth) {
6ee51a4e 2587 struct in6_addr in6;
3ef967a4 2588 u16 ether_type;
c0c1d3d7
OD		 2589 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2590
3ef967a4
MS		 2591 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE :
2592 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2593
c0c1d3d7 2594 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 2595
1049f138 2596 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 2597 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 2598 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2599 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2600 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2601
3e0629cb 2602
fa417f7b
EC		 2603 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2604 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 2605 if (!is_vlan) {
3ef967a4 2606 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 2607 } else {
3ef967a4 2608 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 2609 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2610 }
fa417f7b 2611 } else {
fd10ed8e
JM		 2612 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
2613 sl_to_vl(to_mdev(ib_dev),
2614 sqp->ud_header.lrh.service_level,
2615 sqp->qp.port);
2616 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
2617 return -EINVAL;
fa417f7b
EC		 2618 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2619 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2620 }
e622f2f4 2621 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 2622 if (!sqp->qp.ibqp.qp_num)
2623 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2624 else
e622f2f4 2625 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 2626 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 2627 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 2628 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 2629 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2630 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 2631 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2632
2633 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2634
2635 if (0) {
987c8f8f 2636 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2637 for (i = 0; i < header_size / 4; ++i) {
2638 if (i % 8 == 0)
987c8f8f
SP		 2639 pr_err(" [%02x] ", i * 4);
2640 pr_cont(" %08x",
2641 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2642 if ((i + 1) % 8 == 0)
987c8f8f 2643 pr_cont("\n");
225c7b1f 2644 }
987c8f8f 2645 pr_err("\n");
225c7b1f
RD		 2646 }
2647
e61ef241
RD		 2648 /*
2649 * Inline data segments may not cross a 64 byte boundary. If
2650 * our UD header is bigger than the space available up to the
2651 * next 64 byte boundary in the WQE, use two inline data
2652 * segments to hold the UD header.
2653 */
2654 spc = MLX4_INLINE_ALIGN -
2655 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2656 if (header_size <= spc) {
2657 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2658 memcpy(inl + 1, sqp->header_buf, header_size);
2659 i = 1;
2660 } else {
2661 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2662 memcpy(inl + 1, sqp->header_buf, spc);
2663
2664 inl = (void *) (inl + 1) + spc;
2665 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2666 /*
2667 * Need a barrier here to make sure all the data is
2668 * visible before the byte_count field is set.
2669 * Otherwise the HCA prefetcher could grab the 64-byte
2670 * chunk with this inline segment and get a valid (!=
2671 * 0xffffffff) byte count but stale data, and end up
2672 * generating a packet with bad headers.
2673 *
2674 * The first inline segment's byte_count field doesn't
2675 * need a barrier, because it comes after a
2676 * control/MLX segment and therefore is at an offset
2677 * of 16 mod 64.
2678 */
2679 wmb();
2680 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2681 i = 2;
2682 }
225c7b1f 2683
f438000f
RD		 2684 *mlx_seg_len =
2685 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2686 return 0;
225c7b1f
RD		 2687}
2688
2689static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2690{
2691 unsigned cur;
2692 struct mlx4_ib_cq *cq;
2693
2694 cur = wq->head - wq->tail;
0e6e7416 2695 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2696 return 0;
2697
2698 cq = to_mcq(ib_cq);
2699 spin_lock(&cq->lock);
2700 cur = wq->head - wq->tail;
2701 spin_unlock(&cq->lock);
2702
0e6e7416 2703 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2704}
2705
95d04f07
RD		 2706static __be32 convert_access(int acc)
2707{
6ff63e19
SM		 2708 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2709 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2710 (acc & IB_ACCESS_REMOTE_WRITE ?
2711 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2712 (acc & IB_ACCESS_REMOTE_READ ?
2713 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2714 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2715 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2716}
2717
1b2cd0fc
SG		 2718static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2719 struct ib_reg_wr *wr)
2720{
2721 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2722
2723 fseg->flags = convert_access(wr->access);
2724 fseg->mem_key = cpu_to_be32(wr->key);
2725 fseg->buf_list = cpu_to_be64(mr->page_map);
2726 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2727 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2728 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2729 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2730 fseg->reserved[0] = 0;
2731 fseg->reserved[1] = 0;
2732}
2733
95d04f07
RD		 2734static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2735{
aee38fad
SM		 2736 memset(iseg, 0, sizeof(*iseg));
2737 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2738}
2739
0fbfa6a9
RD		 2740static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2741 u64 remote_addr, u32 rkey)
2742{
2743 rseg->raddr = cpu_to_be64(remote_addr);
2744 rseg->rkey = cpu_to_be32(rkey);
2745 rseg->reserved = 0;
2746}
2747
e622f2f4
CH		 2748static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2749 struct ib_atomic_wr *wr)
0fbfa6a9 2750{
e622f2f4
CH		 2751 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2752 aseg->swap_add = cpu_to_be64(wr->swap);
2753 aseg->compare = cpu_to_be64(wr->compare_add);
2754 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2755 aseg->swap_add = cpu_to_be64(wr->compare_add);
2756 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 2757 } else {
e622f2f4 2758 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 2759 aseg->compare = 0;
2760 }
2761
2762}
2763
6fa8f719 2764static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 2765 struct ib_atomic_wr *wr)
6fa8f719 2766{
e622f2f4
CH		 2767 aseg->swap_add = cpu_to_be64(wr->swap);
2768 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2769 aseg->compare = cpu_to_be64(wr->compare_add);
2770 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 2771}
2772
0fbfa6a9 2773static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2774 struct ib_ud_wr *wr)
0fbfa6a9 2775{
e622f2f4
CH		 2776 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2777 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2778 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2779 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2780 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2781}
2782
1ffeb2eb
JM		 2783static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2784 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2785 struct ib_ud_wr *wr,
97982f5a 2786 enum mlx4_ib_qp_type qpt)
1ffeb2eb 2787{
e622f2f4 2788 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 2789 struct mlx4_av sqp_av = {0};
2790 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2791
2792 /* force loopback */
2793 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2794 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2795 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2796 cpu_to_be32(0xf0000000);
2797
2798 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2799 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2800 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2801 else
2802 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2803 /* Use QKEY from the QP context, which is set by master */
2804 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2805}
2806
e622f2f4 2807static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 2808{
2809 struct mlx4_wqe_inline_seg *inl = wqe;
2810 struct mlx4_ib_tunnel_header hdr;
e622f2f4 2811 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2812 int spc;
2813 int i;
2814
2815 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 2816 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2817 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2818 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 2819 memcpy(hdr.mac, ah->av.eth.mac, 6);
2820 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2821
2822 spc = MLX4_INLINE_ALIGN -
2823 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2824 if (sizeof (hdr) <= spc) {
2825 memcpy(inl + 1, &hdr, sizeof (hdr));
2826 wmb();
2827 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2828 i = 1;
2829 } else {
2830 memcpy(inl + 1, &hdr, spc);
2831 wmb();
2832 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2833
2834 inl = (void *) (inl + 1) + spc;
2835 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2836 wmb();
2837 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2838 i = 2;
2839 }
2840
2841 *mlx_seg_len =
2842 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2843}
2844
6e694ea3
JM		 2845static void set_mlx_icrc_seg(void *dseg)
2846{
2847 u32 *t = dseg;
2848 struct mlx4_wqe_inline_seg *iseg = dseg;
2849
2850 t[1] = 0;
2851
2852 /*
2853 * Need a barrier here before writing the byte_count field to
2854 * make sure that all the data is visible before the
2855 * byte_count field is set. Otherwise, if the segment begins
2856 * a new cacheline, the HCA prefetcher could grab the 64-byte
2857 * chunk and get a valid (!= * 0xffffffff) byte count but
2858 * stale data, and end up sending the wrong data.
2859 */
2860 wmb();
2861
2862 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2863}
2864
2865static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2866{
d420d9e3
RD		 2867 dseg->lkey = cpu_to_be32(sg->lkey);
2868 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2869
2870 /*
2871 * Need a barrier here before writing the byte_count field to
2872 * make sure that all the data is visible before the
2873 * byte_count field is set. Otherwise, if the segment begins
2874 * a new cacheline, the HCA prefetcher could grab the 64-byte
2875 * chunk and get a valid (!= * 0xffffffff) byte count but
2876 * stale data, and end up sending the wrong data.
2877 */
2878 wmb();
2879
2880 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2881}
2882
2242fa4f
RD		 2883static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2884{
2885 dseg->byte_count = cpu_to_be32(sg->length);
2886 dseg->lkey = cpu_to_be32(sg->lkey);
2887 dseg->addr = cpu_to_be64(sg->addr);
2888}
2889
e622f2f4 2890static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 2891 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2892 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 2893{
e622f2f4 2894 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 2895
417608c2
EC		 2896 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2897 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2898
2899 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 2900 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 2901 return -EINVAL;
2902
e622f2f4 2903 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 2904
e622f2f4 2905 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 2906 *lso_seg_len = halign;
2907 return 0;
2908}
2909
95d04f07
RD		 2910static __be32 send_ieth(struct ib_send_wr *wr)
2911{
2912 switch (wr->opcode) {
2913 case IB_WR_SEND_WITH_IMM:
2914 case IB_WR_RDMA_WRITE_WITH_IMM:
2915 return wr->ex.imm_data;
2916
2917 case IB_WR_SEND_WITH_INV:
2918 return cpu_to_be32(wr->ex.invalidate_rkey);
2919
2920 default:
2921 return 0;
2922 }
2923}
2924
1ffeb2eb
JM		 2925static void add_zero_len_inline(void *wqe)
2926{
2927 struct mlx4_wqe_inline_seg *inl = wqe;
2928 memset(wqe, 0, 16);
2929 inl->byte_count = cpu_to_be32(1 << 31);
2930}
2931
225c7b1f
RD		 2932int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2933 struct ib_send_wr **bad_wr)
2934{
2935 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2936 void *wqe;
2937 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2938 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2939 unsigned long flags;
2940 int nreq;
2941 int err = 0;
ea54b10c
JM		 2942 unsigned ind;
2943 int uninitialized_var(stamp);
2944 int uninitialized_var(size);
a3d8e159 2945 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2946 __be32 dummy;
2947 __be32 *lso_wqe;
2948 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2949 __be32 blh;
225c7b1f 2950 int i;
35f05dab 2951 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2952
e1b866c6
MS		 2953 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2954 struct mlx4_ib_sqp *sqp = to_msqp(qp);
2955
2956 if (sqp->roce_v2_gsi) {
2957 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
2958 struct ib_gid_attr gid_attr;
2959 union ib_gid gid;
2960
2961 if (!ib_get_cached_gid(ibqp->device,
2962 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2963 ah->av.ib.gid_index, &gid,
2964 &gid_attr)) {
2965 if (gid_attr.ndev)
2966 dev_put(gid_attr.ndev);
2967 qp = (gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
2968 to_mqp(sqp->roce_v2_gsi) : qp;
2969 } else {
2970 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
2971 ah->av.ib.gid_index);
2972 }
2973 }
2974 }
2975
96db0e03 2976 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2977 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2978 err = -EIO;
2979 *bad_wr = wr;
2980 nreq = 0;
2981 goto out;
2982 }
225c7b1f 2983
ea54b10c 2984 ind = qp->sq_next_wqe;
225c7b1f
RD		 2985
2986 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2987 lso_wqe = &dummy;
417608c2 2988 blh = 0;
0fd7e1d8 2989
225c7b1f
RD		 2990 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2991 err = -ENOMEM;
2992 *bad_wr = wr;
2993 goto out;
2994 }
2995
2996 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2997 err = -EINVAL;
2998 *bad_wr = wr;
2999 goto out;
3000 }
3001
0e6e7416 3002 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3003 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3004
3005 ctrl->srcrb_flags =
3006 (wr->send_flags & IB_SEND_SIGNALED ?
3007 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3008 (wr->send_flags & IB_SEND_SOLICITED ?
3009 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3010 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3011 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3012 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3013 qp->sq_signal_bits;
3014
95d04f07 3015 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3016
3017 wqe += sizeof *ctrl;
3018 size = sizeof *ctrl / 16;
3019
1ffeb2eb
JM		 3020 switch (qp->mlx4_ib_qp_type) {
3021 case MLX4_IB_QPT_RC:
3022 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3023 switch (wr->opcode) {
3024 case IB_WR_ATOMIC_CMP_AND_SWP:
3025 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3026 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3027 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3028 atomic_wr(wr)->rkey);
225c7b1f
RD		 3029 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3030
e622f2f4 3031 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3032 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3033
225c7b1f
RD		 3034 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3035 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3036
3037 break;
3038
3039 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3040 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3041 atomic_wr(wr)->rkey);
6fa8f719
VS		 3042 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3043
e622f2f4 3044 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3045 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3046
3047 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3048 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3049
3050 break;
3051
3052 case IB_WR_RDMA_READ:
3053 case IB_WR_RDMA_WRITE:
3054 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3055 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3056 rdma_wr(wr)->rkey);
225c7b1f
RD		 3057 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3058 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3059 break;
95d04f07
RD		 3060
3061 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3062 ctrl->srcrb_flags |=
3063 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3064 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3065 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3066 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3067 break;
3068
1b2cd0fc
SG		 3069 case IB_WR_REG_MR:
3070 ctrl->srcrb_flags |=
3071 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3072 set_reg_seg(wqe, reg_wr(wr));
3073 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3074 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3075 break;
3076
225c7b1f
RD		 3077 default:
3078 /* No extra segments required for sends */
3079 break;
3080 }
3081 break;
3082
1ffeb2eb 3083 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3084 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3085 ctrl, &seglen);
1ffeb2eb
JM		 3086 if (unlikely(err)) {
3087 *bad_wr = wr;
3088 goto out;
3089 }
3090 wqe += seglen;
3091 size += seglen / 16;
3092 break;
3093 case MLX4_IB_QPT_TUN_SMI:
3094 case MLX4_IB_QPT_TUN_GSI:
3095 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3096 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3097 /* set the forced-loopback bit in the data seg av */
3098 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3099 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3100 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3101 break;
3102 case MLX4_IB_QPT_UD:
e622f2f4 3103 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3104 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3105 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3106
3107 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3108 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3109 &lso_hdr_sz, &blh);
b832be1e
EC		 3110 if (unlikely(err)) {
3111 *bad_wr = wr;
3112 goto out;
3113 }
0fd7e1d8 3114 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3115 wqe += seglen;
3116 size += seglen / 16;
3117 }
225c7b1f
RD		 3118 break;
3119
1ffeb2eb 3120 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3121 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3122 ctrl, &seglen);
1ffeb2eb
JM		 3123 if (unlikely(err)) {
3124 *bad_wr = wr;
3125 goto out;
3126 }
3127 wqe += seglen;
3128 size += seglen / 16;
3129 /* to start tunnel header on a cache-line boundary */
3130 add_zero_len_inline(wqe);
3131 wqe += 16;
3132 size++;
e622f2f4 3133 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3134 wqe += seglen;
3135 size += seglen / 16;
3136 break;
3137 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3138 case MLX4_IB_QPT_PROXY_GSI:
3139 /* If we are tunneling special qps, this is a UD qp.
3140 * In this case we first add a UD segment targeting
3141 * the tunnel qp, and then add a header with address
3142 * information */
e622f2f4
CH		 3143 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3144 ud_wr(wr),
97982f5a 3145 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3146 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3147 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3148 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3149 wqe += seglen;
3150 size += seglen / 16;
3151 break;
3152
3153 case MLX4_IB_QPT_SMI:
3154 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3155 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3156 &seglen);
f438000f 3157 if (unlikely(err)) {
225c7b1f
RD		 3158 *bad_wr = wr;
3159 goto out;
3160 }
f438000f
RD		 3161 wqe += seglen;
3162 size += seglen / 16;
225c7b1f
RD		 3163 break;
3164
3165 default:
3166 break;
3167 }
3168
6e694ea3
JM		 3169 /*
3170 * Write data segments in reverse order, so as to
3171 * overwrite cacheline stamp last within each
3172 * cacheline. This avoids issues with WQE
3173 * prefetching.
3174 */
225c7b1f 3175
6e694ea3
JM		 3176 dseg = wqe;
3177 dseg += wr->num_sge - 1;
3178 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3179
3180 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3181 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3182 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3183 qp->mlx4_ib_qp_type &
3184 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3185 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3186 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3187 }
3188
6e694ea3
JM		 3189 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3190 set_data_seg(dseg, wr->sg_list + i);
3191
0fd7e1d8
RD		 3192 /*
3193 * Possibly overwrite stamping in cacheline with LSO
3194 * segment only after making sure all data segments
3195 * are written.
3196 */
3197 wmb();
3198 *lso_wqe = lso_hdr_sz;
3199
224e92e0
BB		 3200 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3201 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3202
3203 /*
3204 * Make sure descriptor is fully written before
3205 * setting ownership bit (because HW can start
3206 * executing as soon as we do).
3207 */
3208 wmb();
3209
59b0ed12 3210 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3211 *bad_wr = wr;
225c7b1f
RD		 3212 err = -EINVAL;
3213 goto out;
3214 }
3215
3216 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3217 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3218
ea54b10c
JM		 3219 stamp = ind + qp->sq_spare_wqes;
3220 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3221
0e6e7416
RD		 3222 /*
3223 * We can improve latency by not stamping the last
3224 * send queue WQE until after ringing the doorbell, so
3225 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3226 *
3227 * Same optimization applies to padding with NOP wqe
3228 * in case of WQE shrinking (used to prevent wrap-around
3229 * in the middle of WR).
0e6e7416 3230 */
ea54b10c
JM		 3231 if (wr->next) {
3232 stamp_send_wqe(qp, stamp, size * 16);
3233 ind = pad_wraparound(qp, ind);
3234 }
225c7b1f
RD		 3235 }
3236
3237out:
3238 if (likely(nreq)) {
3239 qp->sq.head += nreq;
3240
3241 /*
3242 * Make sure that descriptors are written before
3243 * doorbell record.
3244 */
3245 wmb();
3246
3247 writel(qp->doorbell_qpn,
3248 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3249
3250 /*
3251 * Make sure doorbells don't leak out of SQ spinlock
3252 * and reach the HCA out of order.
3253 */
3254 mmiowb();
0e6e7416 3255
ea54b10c
JM		 3256 stamp_send_wqe(qp, stamp, size * 16);
3257
3258 ind = pad_wraparound(qp, ind);
3259 qp->sq_next_wqe = ind;
225c7b1f
RD		 3260 }
3261
96db0e03 3262 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3263
3264 return err;
3265}
3266
3267int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3268 struct ib_recv_wr **bad_wr)
3269{
3270 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3271 struct mlx4_wqe_data_seg *scat;
3272 unsigned long flags;
3273 int err = 0;
3274 int nreq;
3275 int ind;
1ffeb2eb 3276 int max_gs;
225c7b1f 3277 int i;
35f05dab 3278 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3279
1ffeb2eb 3280 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3281 spin_lock_irqsave(&qp->rq.lock, flags);
3282
35f05dab
YH		 3283 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3284 err = -EIO;
3285 *bad_wr = wr;
3286 nreq = 0;
3287 goto out;
3288 }
3289
0e6e7416 3290 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3291
3292 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3293 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3294 err = -ENOMEM;
3295 *bad_wr = wr;
3296 goto out;
3297 }
3298
3299 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3300 err = -EINVAL;
3301 *bad_wr = wr;
3302 goto out;
3303 }
3304
3305 scat = get_recv_wqe(qp, ind);
3306
1ffeb2eb
JM		 3307 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3308 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3309 ib_dma_sync_single_for_device(ibqp->device,
3310 qp->sqp_proxy_rcv[ind].map,
3311 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3312 DMA_FROM_DEVICE);
3313 scat->byte_count =
3314 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3315 /* use dma lkey from upper layer entry */
3316 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3317 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3318 scat++;
3319 max_gs--;
3320 }
3321
2242fa4f
RD		 3322 for (i = 0; i < wr->num_sge; ++i)
3323 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3324
1ffeb2eb 3325 if (i < max_gs) {
225c7b1f
RD		 3326 scat[i].byte_count = 0;
3327 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3328 scat[i].addr = 0;
3329 }
3330
3331 qp->rq.wrid[ind] = wr->wr_id;
3332
0e6e7416 3333 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3334 }
3335
3336out:
3337 if (likely(nreq)) {
3338 qp->rq.head += nreq;
3339
3340 /*
3341 * Make sure that descriptors are written before
3342 * doorbell record.
3343 */
3344 wmb();
3345
3346 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3347 }
3348
3349 spin_unlock_irqrestore(&qp->rq.lock, flags);
3350
3351 return err;
3352}
6a775e2b
JM		 3353
3354static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3355{
3356 switch (mlx4_state) {
3357 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3358 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3359 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3360 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3361 case MLX4_QP_STATE_SQ_DRAINING:
3362 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3363 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3364 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3365 default: return -1;
3366 }
3367}
3368
3369static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3370{
3371 switch (mlx4_mig_state) {
3372 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3373 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3374 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3375 default: return -1;
3376 }
3377}
3378
3379static int to_ib_qp_access_flags(int mlx4_flags)
3380{
3381 int ib_flags = 0;
3382
3383 if (mlx4_flags & MLX4_QP_BIT_RRE)
3384 ib_flags |= IB_ACCESS_REMOTE_READ;
3385 if (mlx4_flags & MLX4_QP_BIT_RWE)
3386 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3387 if (mlx4_flags & MLX4_QP_BIT_RAE)
3388 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3389
3390 return ib_flags;
3391}
3392
4c3eb3ca 3393static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3394 struct mlx4_qp_path *path)
3395{
4c3eb3ca
EC		 3396 struct mlx4_dev *dev = ibdev->dev;
3397 int is_eth;
3398
8fcea95a 3399 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3400 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3401
3402 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3403 return;
3404
4c3eb3ca
EC		 3405 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3406 IB_LINK_LAYER_ETHERNET;
3407 if (is_eth)
3408 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3409 ((path->sched_queue & 4) << 1);
3410 else
3411 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3412
6a775e2b 3413 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3414 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3415 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3416 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3417 if (ib_ah_attr->ah_flags) {
3418 ib_ah_attr->grh.sgid_index = path->mgid_index;
3419 ib_ah_attr->grh.hop_limit = path->hop_limit;
3420 ib_ah_attr->grh.traffic_class =
3421 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3422 ib_ah_attr->grh.flow_label =
586bb586 3423 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3424 memcpy(ib_ah_attr->grh.dgid.raw,
3425 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3426 }
3427}
3428
3429int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3430 struct ib_qp_init_attr *qp_init_attr)
3431{
3432 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3433 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3434 struct mlx4_qp_context context;
3435 int mlx4_state;
0df67030
DB		 3436 int err = 0;
3437
3438 mutex_lock(&qp->mutex);
6a775e2b
JM		 3439
3440 if (qp->state == IB_QPS_RESET) {
3441 qp_attr->qp_state = IB_QPS_RESET;
3442 goto done;
3443 }
3444
3445 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3446 if (err) {
3447 err = -EINVAL;
3448 goto out;
3449 }
6a775e2b
JM		 3450
3451 mlx4_state = be32_to_cpu(context.flags) >> 28;
3452
0df67030
DB		 3453 qp->state = to_ib_qp_state(mlx4_state);
3454 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3455 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3456 qp_attr->path_mig_state =
3457 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3458 qp_attr->qkey = be32_to_cpu(context.qkey);
3459 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3460 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3461 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3462 qp_attr->qp_access_flags =
3463 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3464
3465 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3466 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3467 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3468 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3469 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3470 }
3471
3472 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3473 if (qp_attr->qp_state == IB_QPS_INIT)
3474 qp_attr->port_num = qp->port;
3475 else
3476 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3477
3478 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3479 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3480
3481 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3482
3483 qp_attr->max_dest_rd_atomic =
3484 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3485 qp_attr->min_rnr_timer =
3486 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3487 qp_attr->timeout = context.pri_path.ackto >> 3;
3488 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3489 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3490 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3491
3492done:
3493 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3494 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3495 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3496
6a775e2b 3497 if (!ibqp->uobject) {
7f5eb9bb
RD		 3498 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3499 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3500 } else {
3501 qp_attr->cap.max_send_wr = 0;
3502 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3503 }
3504
7f5eb9bb
RD		 3505 /*
3506 * We don't support inline sends for kernel QPs (yet), and we
3507 * don't know what userspace's value should be.
3508 */
3509 qp_attr->cap.max_inline_data = 0;
3510
3511 qp_init_attr->cap = qp_attr->cap;
3512
521e575b
RL		 3513 qp_init_attr->create_flags = 0;
3514 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3515 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3516
3517 if (qp->flags & MLX4_IB_QP_LSO)
3518 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3519
c1c98501
MB		 3520 if (qp->flags & MLX4_IB_QP_NETIF)
3521 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3522
46db567d
DB		 3523 qp_init_attr->sq_sig_type =
3524 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3525 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3526
0df67030
DB		 3527out:
3528 mutex_unlock(&qp->mutex);
3529 return err;
6a775e2b
JM		 3530}
3531
Linux 6.x block layer and io_uring tree(s)