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IB/uverbs: Add UVERBS_ATTR_FLAGS_IN to the specs language
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
225c7b1f 44
2f48485d 45#include <linux/mlx4/driver.h>
225c7b1f
RD		 46#include <linux/mlx4/qp.h>
47
48#include "mlx4_ib.h"
9ce28a20 49#include <rdma/mlx4-abi.h>
225c7b1f 50
35f05dab
YH		 51static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
3078f5f1 55static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
35f05dab 56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
79struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 86 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 117};
118
400b1ebc
GL		 119enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122};
123
225c7b1f
RD		 124static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125{
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127}
128
1ffeb2eb
JM		 129static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130{
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
47605df9
JM		 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 137}
138
225c7b1f
RD		 139static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140{
47605df9
JM		 141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
e1b866c6
MS		 160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 164}
165
1ffeb2eb 166/* used for INIT/CLOSE port logic */
225c7b1f
RD		 167static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168{
47605df9
JM		 169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
225c7b1f
RD		 188}
189
190static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191{
1c69fc2a 192 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 193}
194
195static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198}
199
200static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201{
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203}
204
0e6e7416
RD		 205/*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 207 * first four bytes of every 64 byte chunk with
208 * 0x7FFFFFF | (invalid_ownership_value << 31).
209 *
210 * When the max work request size is less than or equal to the WQE
211 * basic block size, as an optimization, we can stamp all WQEs with
212 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 213 */
ea54b10c 214static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 215{
d2ae16d5 216 __be32 *wqe;
0e6e7416 217 int i;
ea54b10c
JM		 218 int s;
219 int ind;
220 void *buf;
221 __be32 stamp;
9670e553 222 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 223
ea54b10c 224 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 225 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 226 for (i = 0; i < s; i += 64) {
227 ind = (i >> qp->sq.wqe_shift) + n;
228 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
229 cpu_to_be32(0xffffffff);
230 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
231 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
232 *wqe = stamp;
233 }
234 } else {
9670e553 235 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
224e92e0 236 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
ea54b10c
JM		 237 for (i = 64; i < s; i += 64) {
238 wqe = buf + i;
d2ae16d5 239 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 240 }
241 }
242}
243
244static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
245{
246 struct mlx4_wqe_ctrl_seg *ctrl;
247 struct mlx4_wqe_inline_seg *inl;
248 void *wqe;
249 int s;
250
251 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
252 s = sizeof(struct mlx4_wqe_ctrl_seg);
253
254 if (qp->ibqp.qp_type == IB_QPT_UD) {
255 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
256 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
257 memset(dgram, 0, sizeof *dgram);
258 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
259 s += sizeof(struct mlx4_wqe_datagram_seg);
260 }
261
262 /* Pad the remainder of the WQE with an inline data segment. */
263 if (size > s) {
264 inl = wqe + s;
265 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
266 }
267 ctrl->srcrb_flags = 0;
224e92e0 268 ctrl->qpn_vlan.fence_size = size / 16;
ea54b10c
JM		 269 /*
270 * Make sure descriptor is fully written before setting ownership bit
271 * (because HW can start executing as soon as we do).
272 */
273 wmb();
274
275 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
276 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 277
ea54b10c
JM		 278 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
279}
280
281/* Post NOP WQE to prevent wrap-around in the middle of WR */
282static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
283{
284 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
285 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
286 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
287 ind += s;
288 }
289 return ind;
0e6e7416
RD		 290}
291
225c7b1f
RD		 292static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
293{
294 struct ib_event event;
295 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
296
297 if (type == MLX4_EVENT_TYPE_PATH_MIG)
298 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
299
300 if (ibqp->event_handler) {
301 event.device = ibqp->device;
302 event.element.qp = ibqp;
303 switch (type) {
304 case MLX4_EVENT_TYPE_PATH_MIG:
305 event.event = IB_EVENT_PATH_MIG;
306 break;
307 case MLX4_EVENT_TYPE_COMM_EST:
308 event.event = IB_EVENT_COMM_EST;
309 break;
310 case MLX4_EVENT_TYPE_SQ_DRAINED:
311 event.event = IB_EVENT_SQ_DRAINED;
312 break;
313 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
314 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
315 break;
316 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
317 event.event = IB_EVENT_QP_FATAL;
318 break;
319 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
320 event.event = IB_EVENT_PATH_MIG_ERR;
321 break;
322 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
323 event.event = IB_EVENT_QP_REQ_ERR;
324 break;
325 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
326 event.event = IB_EVENT_QP_ACCESS_ERR;
327 break;
328 default:
987c8f8f 329 pr_warn("Unexpected event type %d "
225c7b1f
RD		 330 "on QP %06x\n", type, qp->qpn);
331 return;
332 }
333
334 ibqp->event_handler(&event, ibqp->qp_context);
335 }
336}
337
400b1ebc
GL		 338static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
339{
340 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
341 type, qp->qpn);
342}
343
1ffeb2eb 344static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 345{
346 /*
347 * UD WQEs must have a datagram segment.
348 * RC and UC WQEs might have a remote address segment.
349 * MLX WQEs need two extra inline data segments (for the UD
350 * header and space for the ICRC).
351 */
352 switch (type) {
1ffeb2eb 353 case MLX4_IB_QPT_UD:
225c7b1f 354 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 355 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 356 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 357 case MLX4_IB_QPT_PROXY_SMI_OWNER:
358 case MLX4_IB_QPT_PROXY_SMI:
359 case MLX4_IB_QPT_PROXY_GSI:
360 return sizeof (struct mlx4_wqe_ctrl_seg) +
361 sizeof (struct mlx4_wqe_datagram_seg) + 64;
362 case MLX4_IB_QPT_TUN_SMI_OWNER:
363 case MLX4_IB_QPT_TUN_GSI:
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_datagram_seg);
366
367 case MLX4_IB_QPT_UC:
225c7b1f
RD		 368 return sizeof (struct mlx4_wqe_ctrl_seg) +
369 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 370 case MLX4_IB_QPT_RC:
225c7b1f 371 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 372 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 373 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 374 case MLX4_IB_QPT_SMI:
375 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 376 return sizeof (struct mlx4_wqe_ctrl_seg) +
377 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 378 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
379 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 380 sizeof (struct mlx4_wqe_inline_seg),
381 sizeof (struct mlx4_wqe_data_seg)) +
382 ALIGN(4 +
383 sizeof (struct mlx4_wqe_inline_seg),
384 sizeof (struct mlx4_wqe_data_seg));
385 default:
386 return sizeof (struct mlx4_wqe_ctrl_seg);
387 }
388}
389
2446304d 390static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
ea30b966
MG		 391 int is_user, int has_rq, struct mlx4_ib_qp *qp,
392 u32 inl_recv_sz)
225c7b1f 393{
2446304d 394 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 395 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
396 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 397 return -EINVAL;
398
0a1405da 399 if (!has_rq) {
ea30b966 400 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 401 return -EINVAL;
2446304d 402
0e6e7416 403 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 404 } else {
ea30b966
MG		 405 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
406 sizeof(struct mlx4_wqe_data_seg);
407 u32 wqe_size;
408
a4cd7ed8 409 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 410 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
411 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 412 return -EINVAL;
413
0e6e7416 414 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 415 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 416 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
417 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 418 }
2446304d 419
fc2d0044
SG		 420 /* leave userspace return values as they were, so as not to break ABI */
421 if (is_user) {
422 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
423 cap->max_recv_sge = qp->rq.max_gs;
424 } else {
425 cap->max_recv_wr = qp->rq.max_post =
426 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
427 cap->max_recv_sge = min(qp->rq.max_gs,
428 min(dev->dev->caps.max_sq_sg,
429 dev->dev->caps.max_rq_sg));
430 }
2446304d
EC		 431
432 return 0;
433}
434
435static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
73898db0
HA		 436 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
437 bool shrink_wqe)
2446304d 438{
ea54b10c
JM		 439 int s;
440
2446304d 441 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 442 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
443 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 444 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 445 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
446 return -EINVAL;
447
448 /*
449 * For MLX transport we need 2 extra S/G entries:
450 * one for the header and one for the checksum at the end
451 */
1ffeb2eb
JM		 452 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
453 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 454 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
455 return -EINVAL;
456
ea54b10c
JM		 457 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
458 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 459 send_wqe_overhead(type, qp->flags);
225c7b1f 460
cd155c1c
RD		 461 if (s > dev->dev->caps.max_sq_desc_sz)
462 return -EINVAL;
463
0e6e7416 464 /*
ea54b10c
JM		 465 * Hermon supports shrinking WQEs, such that a single work
466 * request can include multiple units of 1 << wqe_shift. This
467 * way, work requests can differ in size, and do not have to
468 * be a power of 2 in size, saving memory and speeding up send
469 * WR posting. Unfortunately, if we do this then the
470 * wqe_index field in CQEs can't be used to look up the WR ID
471 * anymore, so we do this only if selective signaling is off.
472 *
473 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 474 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 475 * constant-sized WRs to make sure a WR is always fully within
476 * a single page-sized chunk.
477 *
478 * Finally, we use NOP work requests to pad the end of the
479 * work queue, to avoid wrap-around in the middle of WR. We
480 * set NEC bit to avoid getting completions with error for
481 * these NOP WRs, but since NEC is only supported starting
482 * with firmware 2.2.232, we use constant-sized WRs for older
483 * firmware.
484 *
485 * And, since MLX QPs only support SEND, we use constant-sized
486 * WRs in this case.
487 *
488 * We look for the smallest value of wqe_shift such that the
489 * resulting number of wqes does not exceed device
490 * capabilities.
491 *
492 * We set WQE size to at least 64 bytes, this way stamping
493 * invalidates each WQE.
0e6e7416 494 */
73898db0 495 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
ea54b10c 496 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 497 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
498 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
499 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 500 qp->sq.wqe_shift = ilog2(64);
501 else
502 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
503
504 for (;;) {
ea54b10c
JM		 505 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
506
507 /*
508 * We need to leave 2 KB + 1 WR of headroom in the SQ to
509 * allow HW to prefetch.
510 */
511 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
512 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
513 qp->sq_max_wqes_per_wr +
514 qp->sq_spare_wqes);
515
516 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
517 break;
518
519 if (qp->sq_max_wqes_per_wr <= 1)
520 return -EINVAL;
521
522 ++qp->sq.wqe_shift;
523 }
524
cd155c1c
RD		 525 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
526 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 527 send_wqe_overhead(type, qp->flags)) /
528 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 529
530 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
531 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 532 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
533 qp->rq.offset = 0;
0e6e7416 534 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 535 } else {
0e6e7416 536 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 537 qp->sq.offset = 0;
538 }
539
ea54b10c
JM		 540 cap->max_send_wr = qp->sq.max_post =
541 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 542 cap->max_send_sge = min(qp->sq.max_gs,
543 min(dev->dev->caps.max_sq_sg,
544 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 545 /* We don't support inline sends for kernel QPs (yet) */
546 cap->max_inline_data = 0;
225c7b1f
RD		 547
548 return 0;
549}
550
83904132
JM		 551static int set_user_sq_size(struct mlx4_ib_dev *dev,
552 struct mlx4_ib_qp *qp,
2446304d
EC		 553 struct mlx4_ib_create_qp *ucmd)
554{
83904132
JM		 555 /* Sanity check SQ size before proceeding */
556 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
557 ucmd->log_sq_stride >
558 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
559 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
560 return -EINVAL;
561
0e6e7416 562 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 563 qp->sq.wqe_shift = ucmd->log_sq_stride;
564
0e6e7416
RD		 565 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
566 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 567
568 return 0;
569}
570
1ffeb2eb
JM		 571static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
572{
573 int i;
574
575 qp->sqp_proxy_rcv =
6da2ec56
KC		 576 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
577 GFP_KERNEL);
1ffeb2eb
JM		 578 if (!qp->sqp_proxy_rcv)
579 return -ENOMEM;
580 for (i = 0; i < qp->rq.wqe_cnt; i++) {
581 qp->sqp_proxy_rcv[i].addr =
582 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
583 GFP_KERNEL);
584 if (!qp->sqp_proxy_rcv[i].addr)
585 goto err;
586 qp->sqp_proxy_rcv[i].map =
587 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
588 sizeof (struct mlx4_ib_proxy_sqp_hdr),
589 DMA_FROM_DEVICE);
cc47d369
SO		 590 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
591 kfree(qp->sqp_proxy_rcv[i].addr);
592 goto err;
593 }
1ffeb2eb
JM		 594 }
595 return 0;
596
597err:
598 while (i > 0) {
599 --i;
600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
601 sizeof (struct mlx4_ib_proxy_sqp_hdr),
602 DMA_FROM_DEVICE);
603 kfree(qp->sqp_proxy_rcv[i].addr);
604 }
605 kfree(qp->sqp_proxy_rcv);
606 qp->sqp_proxy_rcv = NULL;
607 return -ENOMEM;
608}
609
610static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
611{
612 int i;
613
614 for (i = 0; i < qp->rq.wqe_cnt; i++) {
615 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
616 sizeof (struct mlx4_ib_proxy_sqp_hdr),
617 DMA_FROM_DEVICE);
618 kfree(qp->sqp_proxy_rcv[i].addr);
619 }
620 kfree(qp->sqp_proxy_rcv);
621}
622
0a1405da
SH		 623static int qp_has_rq(struct ib_qp_init_attr *attr)
624{
625 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
626 return 0;
627
628 return !attr->srq;
629}
630
99ec41d0
JM		 631static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
632{
633 int i;
634 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 635 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
636 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 637 }
638 return 0;
639}
640
7b59f0f9
EBE		 641static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
642 struct mlx4_ib_qp *qp)
643{
644 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
645 mlx4_counter_free(dev->dev, qp->counter_index->index);
646 list_del(&qp->counter_index->list);
647 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
648
649 kfree(qp->counter_index);
650 qp->counter_index = NULL;
651}
652
3078f5f1
GL		 653static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
654 struct ib_qp_init_attr *init_attr,
655 struct mlx4_ib_create_qp_rss *ucmd)
656{
657 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
658 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
659
660 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
661 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
662 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
663 MLX4_EN_RSS_KEY_SIZE);
664 } else {
665 pr_debug("RX Hash function is not supported\n");
666 return (-EOPNOTSUPP);
667 }
668
4d02ebd9
GL		 669 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
670 MLX4_IB_RX_HASH_DST_IPV4 |
671 MLX4_IB_RX_HASH_SRC_IPV6 |
672 MLX4_IB_RX_HASH_DST_IPV6 |
673 MLX4_IB_RX_HASH_SRC_PORT_TCP |
674 MLX4_IB_RX_HASH_DST_PORT_TCP |
675 MLX4_IB_RX_HASH_SRC_PORT_UDP |
4f9ca2d8
LR		 676 MLX4_IB_RX_HASH_DST_PORT_UDP |
677 MLX4_IB_RX_HASH_INNER)) {
4d02ebd9
GL		 678 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
679 ucmd->rx_hash_fields_mask);
680 return (-EOPNOTSUPP);
681 }
682
3078f5f1
GL		 683 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
684 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
685 rss_ctx->flags = MLX4_RSS_IPV4;
686 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
687 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
688 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
689 return (-EOPNOTSUPP);
690 }
691
692 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
693 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
694 rss_ctx->flags |= MLX4_RSS_IPV6;
695 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
696 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
697 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
698 return (-EOPNOTSUPP);
699 }
700
701 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
702 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
703 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
704 pr_debug("RX Hash fields_mask for UDP is not supported\n");
705 return (-EOPNOTSUPP);
706 }
707
4d02ebd9 708 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 709 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 710 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 711 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 712 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 713 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
714 return (-EOPNOTSUPP);
715 }
716 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
717 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
718 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
719 return (-EOPNOTSUPP);
720 }
721
722 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
723 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 724 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 725 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 726 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 727 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 728 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 729 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
730 return (-EOPNOTSUPP);
731 }
3078f5f1
GL		 732 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
733 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
734 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
735 return (-EOPNOTSUPP);
736 }
737
07d84f7b
GL		 738 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
739 if (dev->dev->caps.tunnel_offload_mode ==
740 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
741 /*
742 * Hash according to inner headers if exist, otherwise
743 * according to outer headers.
744 */
745 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
746 } else {
747 pr_debug("RSS Hash for inner headers isn't supported\n");
748 return (-EOPNOTSUPP);
749 }
750 }
751
3078f5f1
GL		 752 return 0;
753}
754
d7c0557a 755static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 756 struct ib_qp_init_attr *init_attr,
757 struct mlx4_ib_create_qp_rss *ucmd,
758 struct mlx4_ib_qp *qp)
759{
760 int qpn;
761 int err;
762
763 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
764
765 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
766 if (err)
767 return err;
768
769 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
770 if (err)
771 goto err_qpn;
772
773 mutex_init(&qp->mutex);
774
775 INIT_LIST_HEAD(&qp->gid_list);
776 INIT_LIST_HEAD(&qp->steering_rules);
777
c3f1ee29 778 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 779 qp->state = IB_QPS_RESET;
780
781 /* Set dummy send resources to be compatible with HV and PRM */
782 qp->sq_no_prefetch = 1;
783 qp->sq.wqe_cnt = 1;
784 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
785 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
786 qp->mtt = (to_mqp(
787 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
788
789 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
790 if (!qp->rss_ctx) {
791 err = -ENOMEM;
792 goto err_qp_alloc;
793 }
794
795 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
796 if (err)
797 goto err;
798
799 return 0;
800
801err:
802 kfree(qp->rss_ctx);
803
804err_qp_alloc:
805 mlx4_qp_remove(dev->dev, &qp->mqp);
806 mlx4_qp_free(dev->dev, &qp->mqp);
807
808err_qpn:
809 mlx4_qp_release_range(dev->dev, qpn, 1);
810 return err;
811}
812
813static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
814 struct ib_qp_init_attr *init_attr,
815 struct ib_udata *udata)
816{
817 struct mlx4_ib_qp *qp;
818 struct mlx4_ib_create_qp_rss ucmd = {};
819 size_t required_cmd_sz;
820 int err;
821
822 if (!udata) {
823 pr_debug("RSS QP with NULL udata\n");
824 return ERR_PTR(-EINVAL);
825 }
826
827 if (udata->outlen)
828 return ERR_PTR(-EOPNOTSUPP);
829
830 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
831 sizeof(ucmd.reserved1);
832 if (udata->inlen < required_cmd_sz) {
833 pr_debug("invalid inlen\n");
834 return ERR_PTR(-EINVAL);
835 }
836
837 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
838 pr_debug("copy failed\n");
839 return ERR_PTR(-EFAULT);
840 }
841
f9bfea99
GL		 842 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
843 return ERR_PTR(-EOPNOTSUPP);
844
3078f5f1
GL		 845 if (ucmd.comp_mask || ucmd.reserved1)
846 return ERR_PTR(-EOPNOTSUPP);
847
848 if (udata->inlen > sizeof(ucmd) &&
849 !ib_is_udata_cleared(udata, sizeof(ucmd),
850 udata->inlen - sizeof(ucmd))) {
851 pr_debug("inlen is not supported\n");
852 return ERR_PTR(-EOPNOTSUPP);
853 }
854
855 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
856 pr_debug("RSS QP with unsupported QP type %d\n",
857 init_attr->qp_type);
858 return ERR_PTR(-EOPNOTSUPP);
859 }
860
861 if (init_attr->create_flags) {
862 pr_debug("RSS QP doesn't support create flags\n");
863 return ERR_PTR(-EOPNOTSUPP);
864 }
865
866 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
867 pr_debug("RSS QP with unsupported send attributes\n");
868 return ERR_PTR(-EOPNOTSUPP);
869 }
870
871 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
872 if (!qp)
873 return ERR_PTR(-ENOMEM);
874
875 qp->pri.vid = 0xFFFF;
876 qp->alt.vid = 0xFFFF;
877
d7c0557a 878 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
3078f5f1
GL		 879 if (err) {
880 kfree(qp);
881 return ERR_PTR(err);
882 }
883
884 qp->ibqp.qp_num = qp->mqp.qpn;
885
886 return &qp->ibqp;
887}
888
400b1ebc
GL		 889/*
890 * This function allocates a WQN from a range which is consecutive and aligned
891 * to its size. In case the range is full, then it creates a new range and
892 * allocates WQN from it. The new range will be used for following allocations.
893 */
894static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
895 struct mlx4_ib_qp *qp, int range_size, int *wqn)
896{
897 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
898 struct mlx4_wqn_range *range;
899 int err = 0;
900
901 mutex_lock(&context->wqn_ranges_mutex);
902
903 range = list_first_entry_or_null(&context->wqn_ranges_list,
904 struct mlx4_wqn_range, list);
905
906 if (!range || (range->refcount == range->size) || range->dirty) {
907 range = kzalloc(sizeof(*range), GFP_KERNEL);
908 if (!range) {
909 err = -ENOMEM;
910 goto out;
911 }
912
913 err = mlx4_qp_reserve_range(dev->dev, range_size,
914 range_size, &range->base_wqn, 0,
915 qp->mqp.usage);
916 if (err) {
917 kfree(range);
918 goto out;
919 }
920
921 range->size = range_size;
922 list_add(&range->list, &context->wqn_ranges_list);
923 } else if (range_size != 1) {
924 /*
925 * Requesting a new range (>1) when last range is still open, is
926 * not valid.
927 */
928 err = -EINVAL;
929 goto out;
930 }
931
932 qp->wqn_range = range;
933
934 *wqn = range->base_wqn + range->refcount;
935
936 range->refcount++;
937
938out:
939 mutex_unlock(&context->wqn_ranges_mutex);
940
941 return err;
942}
943
944static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
945 struct mlx4_ib_qp *qp, bool dirty_release)
946{
947 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
948 struct mlx4_wqn_range *range;
949
950 mutex_lock(&context->wqn_ranges_mutex);
951
952 range = qp->wqn_range;
953
954 range->refcount--;
955 if (!range->refcount) {
956 mlx4_qp_release_range(dev->dev, range->base_wqn,
957 range->size);
958 list_del(&range->list);
959 kfree(range);
960 } else if (dirty_release) {
961 /*
962 * A range which one of its WQNs is destroyed, won't be able to be
963 * reused for further WQN allocations.
964 * The next created WQ will allocate a new range.
965 */
966 range->dirty = 1;
967 }
968
969 mutex_unlock(&context->wqn_ranges_mutex);
970}
971
225c7b1f 972static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
400b1ebc 973 enum mlx4_ib_source_type src,
225c7b1f 974 struct ib_qp_init_attr *init_attr,
8900b894
LR		 975 struct ib_udata *udata, int sqpn,
976 struct mlx4_ib_qp **caller_qp)
225c7b1f 977{
a3cdcbfa 978 int qpn;
225c7b1f 979 int err;
73898db0 980 struct ib_qp_cap backup_cap;
b42dde47 981 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 982 struct mlx4_ib_qp *qp;
983 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 984 struct mlx4_ib_cq *mcq;
985 unsigned long flags;
400b1ebc 986 int range_size = 0;
1ffeb2eb
JM		 987
988 /* When tunneling special qps, we use a plain UD qp */
989 if (sqpn) {
990 if (mlx4_is_mfunc(dev->dev) &&
991 (!mlx4_is_master(dev->dev) ||
992 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
993 if (init_attr->qp_type == IB_QPT_GSI)
994 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 995 else {
996 if (mlx4_is_master(dev->dev) ||
997 qp0_enabled_vf(dev->dev, sqpn))
998 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
999 else
1000 qp_type = MLX4_IB_QPT_PROXY_SMI;
1001 }
1ffeb2eb
JM		 1002 }
1003 qpn = sqpn;
1004 /* add extra sg entry for tunneling */
1005 init_attr->cap.max_recv_sge++;
1006 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
1007 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
1008 container_of(init_attr,
1009 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
1010 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
1011 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
1012 !mlx4_is_master(dev->dev))
1013 return -EINVAL;
1014 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1015 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 1016 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1017 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1018 tnl_init->port))
1ffeb2eb
JM		 1019 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1020 else
1021 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 1022 /* we are definitely in the PPF here, since we are creating
1023 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1024 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1025 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 1026 sqpn = qpn;
1027 }
1028
1029 if (!*caller_qp) {
1030 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1031 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1032 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 1033 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 1034 if (!sqp)
1035 return -ENOMEM;
1036 qp = &sqp->qp;
2f5bb473
JM		 1037 qp->pri.vid = 0xFFFF;
1038 qp->alt.vid = 0xFFFF;
1ffeb2eb 1039 } else {
8900b894 1040 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 1041 if (!qp)
1042 return -ENOMEM;
2f5bb473
JM		 1043 qp->pri.vid = 0xFFFF;
1044 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1045 }
1046 } else
1047 qp = *caller_qp;
1048
1049 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 1050
1051 mutex_init(&qp->mutex);
1052 spin_lock_init(&qp->sq.lock);
1053 spin_lock_init(&qp->rq.lock);
fa417f7b 1054 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1055 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 1056
1057 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1058 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1059 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1060
225c7b1f
RD		 1061
1062 if (pd->uobject) {
400b1ebc
GL		 1063 union {
1064 struct mlx4_ib_create_qp qp;
1065 struct mlx4_ib_create_wq wq;
1066 } ucmd;
1067 size_t copy_len;
ed8637d3
GL		 1068 int shift;
1069 int n;
400b1ebc
GL		 1070
1071 copy_len = (src == MLX4_IB_QP_SRC) ?
1072 sizeof(struct mlx4_ib_create_qp) :
1073 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
225c7b1f 1074
400b1ebc 1075 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1076 err = -EFAULT;
1077 goto err;
1078 }
1079
400b1ebc 1080 if (src == MLX4_IB_RWQ_SRC) {
078b3573
GL		 1081 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
1082 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
400b1ebc
GL		 1083 pr_debug("user command isn't supported\n");
1084 err = -EOPNOTSUPP;
1085 goto err;
1086 }
ea30b966 1087
400b1ebc
GL		 1088 if (ucmd.wq.log_range_size >
1089 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1090 pr_debug("WQN range size must be equal or smaller than %d\n",
1091 dev->dev->caps.max_rss_tbl_sz);
1092 err = -EOPNOTSUPP;
1093 goto err;
1094 }
1095 range_size = 1 << ucmd.wq.log_range_size;
1096 } else {
1097 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1098 }
0e6e7416 1099
6d06c9aa
GL		 1100 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1101 if (!(dev->dev->caps.flags &
1102 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1103 pr_debug("scatter FCS is unsupported\n");
1104 err = -EOPNOTSUPP;
1105 goto err;
1106 }
1107
1108 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1109 }
1110
400b1ebc
GL		 1111 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1112 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1113 if (err)
1114 goto err;
1115
400b1ebc
GL		 1116 if (src == MLX4_IB_QP_SRC) {
1117 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1118
1119 err = set_user_sq_size(dev, qp,
1120 (struct mlx4_ib_create_qp *)
1121 &ucmd);
1122 if (err)
1123 goto err;
1124 } else {
1125 qp->sq_no_prefetch = 1;
1126 qp->sq.wqe_cnt = 1;
1127 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1128 /* Allocated buffer expects to have at least that SQ
1129 * size.
1130 */
1131 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1132 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1133 }
1134
1135 qp->umem = ib_umem_get(pd->uobject->context,
1136 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1137 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
225c7b1f
RD		 1138 if (IS_ERR(qp->umem)) {
1139 err = PTR_ERR(qp->umem);
1140 goto err;
1141 }
1142
ed8637d3
GL		 1143 n = ib_umem_page_count(qp->umem);
1144 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1145 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1146
225c7b1f
RD		 1147 if (err)
1148 goto err_buf;
1149
1150 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1151 if (err)
1152 goto err_mtt;
1153
0a1405da 1154 if (qp_has_rq(init_attr)) {
02d89b87 1155 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
400b1ebc
GL		 1156 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1157 ucmd.wq.db_addr, &qp->db);
02d89b87
RD		 1158 if (err)
1159 goto err_mtt;
1160 }
f3301870 1161 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1162 } else {
ea30b966
MG		 1163 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1164 qp_has_rq(init_attr), qp, 0);
1165 if (err)
1166 goto err;
1167
0e6e7416
RD		 1168 qp->sq_no_prefetch = 0;
1169
b832be1e
EC		 1170 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1171 qp->flags |= MLX4_IB_QP_LSO;
1172
c1c98501
MB		 1173 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1174 if (dev->steering_support ==
1175 MLX4_STEERING_MODE_DEVICE_MANAGED)
1176 qp->flags |= MLX4_IB_QP_NETIF;
1177 else
1178 goto err;
1179 }
1180
73898db0
HA		 1181 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1182 err = set_kernel_sq_size(dev, &init_attr->cap,
1183 qp_type, qp, true);
2446304d
EC		 1184 if (err)
1185 goto err;
1186
0a1405da 1187 if (qp_has_rq(init_attr)) {
8900b894 1188 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1189 if (err)
1190 goto err;
225c7b1f 1191
02d89b87
RD		 1192 *qp->db.db = 0;
1193 }
225c7b1f 1194
73898db0 1195 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
8900b894 1196 &qp->buf)) {
73898db0
HA		 1197 memcpy(&init_attr->cap, &backup_cap,
1198 sizeof(backup_cap));
1199 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1200 qp, false);
1201 if (err)
1202 goto err_db;
1203
1204 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
8900b894 1205 PAGE_SIZE * 2, &qp->buf)) {
73898db0
HA		 1206 err = -ENOMEM;
1207 goto err_db;
1208 }
225c7b1f
RD		 1209 }
1210
1211 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1212 &qp->mtt);
1213 if (err)
1214 goto err_buf;
1215
8900b894 1216 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1217 if (err)
1218 goto err_mtt;
1219
e9105cde
LD		 1220 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1221 sizeof(u64), GFP_KERNEL);
1222 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1223 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1224 if (!qp->sq.wrid || !qp->rq.wrid) {
1225 err = -ENOMEM;
1226 goto err_wrid;
1227 }
f3301870 1228 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1229 }
1230
a3cdcbfa 1231 if (sqpn) {
1ffeb2eb
JM		 1232 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1233 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1234 if (alloc_proxy_bufs(pd->device, qp)) {
1235 err = -ENOMEM;
1236 goto err_wrid;
1237 }
1238 }
400b1ebc
GL		 1239 } else if (src == MLX4_IB_RWQ_SRC) {
1240 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1241 range_size, &qpn);
1242 if (err)
1243 goto err_wrid;
a3cdcbfa 1244 } else {
ddae0349
EE		 1245 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1246 * otherwise, the WQE BlueFlame setup flow wrongly causes
1247 * VLAN insertion. */
3987a2d3 1248 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1249 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1250 (init_attr->cap.max_send_wr ?
1251 MLX4_RESERVE_ETH_BF_QP : 0) |
1252 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1253 MLX4_RESERVE_A0_QP : 0),
1254 qp->mqp.usage);
3987a2d3 1255 else
c1c98501
MB		 1256 if (qp->flags & MLX4_IB_QP_NETIF)
1257 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1258 else
1259 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1260 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1261 if (err)
1ffeb2eb 1262 goto err_proxy;
a3cdcbfa
YP		 1263 }
1264
fbfb6625
EBE		 1265 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1266 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1267
8900b894 1268 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1269 if (err)
a3cdcbfa 1270 goto err_qpn;
225c7b1f 1271
0a1405da
SH		 1272 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1273 qp->mqp.qpn |= (1 << 23);
1274
225c7b1f
RD		 1275 /*
1276 * Hardware wants QPN written in big-endian order (after
1277 * shifting) for send doorbell. Precompute this value to save
1278 * a little bit when posting sends.
1279 */
1280 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1281
400b1ebc
GL		 1282 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1283 mlx4_ib_wq_event;
1284
1ffeb2eb
JM		 1285 if (!*caller_qp)
1286 *caller_qp = qp;
35f05dab
YH		 1287
1288 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1289 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1290 to_mcq(init_attr->recv_cq));
1291 /* Maintain device to QPs access, needed for further handling
1292 * via reset flow
1293 */
1294 list_add_tail(&qp->qps_list, &dev->qp_list);
1295 /* Maintain CQ to QPs access, needed for further handling
1296 * via reset flow
1297 */
1298 mcq = to_mcq(init_attr->send_cq);
1299 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1300 mcq = to_mcq(init_attr->recv_cq);
1301 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1302 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1303 to_mcq(init_attr->recv_cq));
1304 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1305 return 0;
1306
a3cdcbfa 1307err_qpn:
c1c98501
MB		 1308 if (!sqpn) {
1309 if (qp->flags & MLX4_IB_QP_NETIF)
1310 mlx4_ib_steer_qp_free(dev, qpn, 1);
400b1ebc
GL		 1311 else if (src == MLX4_IB_RWQ_SRC)
1312 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1313 qp, 0);
c1c98501
MB		 1314 else
1315 mlx4_qp_release_range(dev->dev, qpn, 1);
1316 }
1ffeb2eb
JM		 1317err_proxy:
1318 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1319 free_proxy_bufs(pd->device, qp);
225c7b1f 1320err_wrid:
23f1b384 1321 if (pd->uobject) {
0a1405da
SH		 1322 if (qp_has_rq(init_attr))
1323 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 1324 } else {
0ef2f05c
WW		 1325 kvfree(qp->sq.wrid);
1326 kvfree(qp->rq.wrid);
225c7b1f
RD		 1327 }
1328
1329err_mtt:
1330 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1331
1332err_buf:
1333 if (pd->uobject)
1334 ib_umem_release(qp->umem);
1335 else
1336 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1337
1338err_db:
0a1405da 1339 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 1340 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1341
1342err:
b42dde47
BVA		 1343 if (sqp)
1344 kfree(sqp);
1345 else if (!*caller_qp)
1ffeb2eb 1346 kfree(qp);
225c7b1f
RD		 1347 return err;
1348}
1349
1350static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1351{
1352 switch (state) {
1353 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1354 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1355 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1356 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1357 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1358 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1359 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1360 default: return -1;
1361 }
1362}
1363
1364static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1365 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1366{
338a8fad 1367 if (send_cq == recv_cq) {
35f05dab 1368 spin_lock(&send_cq->lock);
338a8fad
RD		 1369 __acquire(&recv_cq->lock);
1370 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1371 spin_lock(&send_cq->lock);
225c7b1f
RD		 1372 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1373 } else {
35f05dab 1374 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1375 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1376 }
1377}
1378
1379static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1380 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1381{
338a8fad
RD		 1382 if (send_cq == recv_cq) {
1383 __release(&recv_cq->lock);
35f05dab 1384 spin_unlock(&send_cq->lock);
338a8fad 1385 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1386 spin_unlock(&recv_cq->lock);
35f05dab 1387 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1388 } else {
1389 spin_unlock(&send_cq->lock);
35f05dab 1390 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1391 }
1392}
1393
fa417f7b
EC		 1394static void del_gid_entries(struct mlx4_ib_qp *qp)
1395{
1396 struct mlx4_ib_gid_entry *ge, *tmp;
1397
1398 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1399 list_del(&ge->list);
1400 kfree(ge);
1401 }
1402}
1403
0a1405da
SH		 1404static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1405{
1406 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1407 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1408 else
1409 return to_mpd(qp->ibqp.pd);
1410}
1411
400b1ebc 1412static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1413 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1414{
1415 switch (qp->ibqp.qp_type) {
1416 case IB_QPT_XRC_TGT:
1417 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1418 *recv_cq = *send_cq;
1419 break;
1420 case IB_QPT_XRC_INI:
1421 *send_cq = to_mcq(qp->ibqp.send_cq);
1422 *recv_cq = *send_cq;
1423 break;
1424 default:
400b1ebc
GL		 1425 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1426 to_mcq(qp->ibwq.cq);
1427 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1428 *recv_cq;
0a1405da
SH		 1429 break;
1430 }
1431}
1432
3078f5f1
GL		 1433static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1434{
1435 if (qp->state != IB_QPS_RESET) {
1436 int i;
1437
1438 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1439 i++) {
1440 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1441 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1442
1443 mutex_lock(&wq->mutex);
1444
1445 wq->rss_usecnt--;
1446
1447 mutex_unlock(&wq->mutex);
1448 }
1449
1450 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1451 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1452 pr_warn("modify QP %06x to RESET failed.\n",
1453 qp->mqp.qpn);
1454 }
1455
1456 mlx4_qp_remove(dev->dev, &qp->mqp);
1457 mlx4_qp_free(dev->dev, &qp->mqp);
1458 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1459 del_gid_entries(qp);
1460 kfree(qp->rss_ctx);
1461}
1462
225c7b1f 1463static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
400b1ebc 1464 enum mlx4_ib_source_type src, int is_user)
225c7b1f
RD		 1465{
1466 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1467 unsigned long flags;
225c7b1f 1468
2f5bb473 1469 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1470 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1471 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1472 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1473 qp->mqp.qpn);
25476b02 1474 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1475 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1476 qp->pri.smac = 0;
25476b02 1477 qp->pri.smac_port = 0;
2f5bb473
JM		 1478 }
1479 if (qp->alt.smac) {
1480 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1481 qp->alt.smac = 0;
1482 }
1483 if (qp->pri.vid < 0x1000) {
1484 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1485 qp->pri.vid = 0xFFFF;
1486 qp->pri.candidate_vid = 0xFFFF;
1487 qp->pri.update_vid = 0;
1488 }
1489 if (qp->alt.vid < 0x1000) {
1490 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1491 qp->alt.vid = 0xFFFF;
1492 qp->alt.candidate_vid = 0xFFFF;
1493 qp->alt.update_vid = 0;
1494 }
1495 }
225c7b1f 1496
400b1ebc 1497 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1498
35f05dab 1499 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1500 mlx4_ib_lock_cqs(send_cq, recv_cq);
1501
35f05dab
YH		 1502 /* del from lists under both locks above to protect reset flow paths */
1503 list_del(&qp->qps_list);
1504 list_del(&qp->cq_send_list);
1505 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1506 if (!is_user) {
1507 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1508 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1509 if (send_cq != recv_cq)
1510 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1511 }
1512
1513 mlx4_qp_remove(dev->dev, &qp->mqp);
1514
1515 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1516 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1517
1518 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1519
c1c98501
MB		 1520 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1521 if (qp->flags & MLX4_IB_QP_NETIF)
1522 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc
GL		 1523 else if (src == MLX4_IB_RWQ_SRC)
1524 mlx4_ib_release_wqn(to_mucontext(
1525 qp->ibwq.uobject->context), qp, 1);
c1c98501
MB		 1526 else
1527 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1528 }
a3cdcbfa 1529
225c7b1f
RD		 1530 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1531
1532 if (is_user) {
400b1ebc
GL		 1533 if (qp->rq.wqe_cnt) {
1534 struct mlx4_ib_ucontext *mcontext = !src ?
1535 to_mucontext(qp->ibqp.uobject->context) :
1536 to_mucontext(qp->ibwq.uobject->context);
1537 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1538 }
225c7b1f
RD		 1539 ib_umem_release(qp->umem);
1540 } else {
0ef2f05c
WW		 1541 kvfree(qp->sq.wrid);
1542 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1543 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1544 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1545 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1546 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1547 if (qp->rq.wqe_cnt)
6296883c 1548 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1549 }
fa417f7b
EC		 1550
1551 del_gid_entries(qp);
225c7b1f
RD		 1552}
1553
47605df9
JM		 1554static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1555{
1556 /* Native or PPF */
1557 if (!mlx4_is_mfunc(dev->dev) ||
1558 (mlx4_is_master(dev->dev) &&
1559 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1560 return dev->dev->phys_caps.base_sqpn +
1561 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1562 attr->port_num - 1;
1563 }
1564 /* PF or VF -- creating proxies */
1565 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1566 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1567 else
c73c8b1e 1568 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1569}
1570
e1b866c6
MS		 1571static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1572 struct ib_qp_init_attr *init_attr,
1573 struct ib_udata *udata)
225c7b1f 1574{
1ffeb2eb 1575 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1576 int err;
fbfb6625 1577 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1578 u16 xrcdn = 0;
225c7b1f 1579
3078f5f1
GL		 1580 if (init_attr->rwq_ind_tbl)
1581 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1582
521e575b 1583 /*
1ffeb2eb
JM		 1584 * We only support LSO, vendor flag1, and multicast loopback blocking,
1585 * and only for kernel UD QPs.
521e575b 1586 */
1ffeb2eb
JM		 1587 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1588 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1589 MLX4_IB_SRIOV_TUNNEL_QP |
1590 MLX4_IB_SRIOV_SQP |
40f2287b 1591 MLX4_IB_QP_NETIF |
8900b894 1592 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1593 return ERR_PTR(-EINVAL);
521e575b 1594
c1c98501
MB		 1595 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1596 if (init_attr->qp_type != IB_QPT_UD)
1597 return ERR_PTR(-EINVAL);
1598 }
1599
e1b866c6
MS		 1600 if (init_attr->create_flags) {
1601 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1602 return ERR_PTR(-EINVAL);
1603
1604 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1605 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1606 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1607 init_attr->qp_type != IB_QPT_UD) ||
1608 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1609 init_attr->qp_type > IB_QPT_GSI) ||
1610 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1611 init_attr->qp_type != IB_QPT_GSI))
1612 return ERR_PTR(-EINVAL);
1613 }
b846f25a 1614
225c7b1f 1615 switch (init_attr->qp_type) {
0a1405da
SH		 1616 case IB_QPT_XRC_TGT:
1617 pd = to_mxrcd(init_attr->xrcd)->pd;
1618 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1619 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1620 /* fall through */
1621 case IB_QPT_XRC_INI:
1622 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1623 return ERR_PTR(-ENOSYS);
1624 init_attr->recv_cq = init_attr->send_cq;
1625 /* fall through */
225c7b1f
RD		 1626 case IB_QPT_RC:
1627 case IB_QPT_UC:
3987a2d3 1628 case IB_QPT_RAW_PACKET:
8900b894 1629 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1630 if (!qp)
1631 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1632 qp->pri.vid = 0xFFFF;
1633 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1634 /* fall through */
1635 case IB_QPT_UD:
1636 {
400b1ebc
GL		 1637 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1638 init_attr, udata, 0, &qp);
5b420d9c
DB		 1639 if (err) {
1640 kfree(qp);
225c7b1f 1641 return ERR_PTR(err);
5b420d9c 1642 }
225c7b1f
RD		 1643
1644 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1645 qp->xrcdn = xrcdn;
225c7b1f
RD		 1646
1647 break;
1648 }
1649 case IB_QPT_SMI:
1650 case IB_QPT_GSI:
1651 {
e1b866c6
MS		 1652 int sqpn;
1653
225c7b1f 1654 /* Userspace is not allowed to create special QPs: */
0a1405da 1655 if (udata)
225c7b1f 1656 return ERR_PTR(-EINVAL);
e1b866c6 1657 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1658 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1659 1, 1, &sqpn, 0,
1660 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1661
1662 if (res)
1663 return ERR_PTR(res);
1664 } else {
1665 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1666 }
225c7b1f 1667
400b1ebc
GL		 1668 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1669 init_attr, udata, sqpn, &qp);
1ffeb2eb 1670 if (err)
225c7b1f 1671 return ERR_PTR(err);
225c7b1f
RD		 1672
1673 qp->port = init_attr->port_num;
e1b866c6
MS		 1674 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1675 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1676 break;
1677 }
1678 default:
1679 /* Don't support raw QPs */
1680 return ERR_PTR(-EINVAL);
1681 }
1682
1683 return &qp->ibqp;
1684}
1685
e1b866c6
MS		 1686struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1687 struct ib_qp_init_attr *init_attr,
1688 struct ib_udata *udata) {
1689 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1690 struct ib_qp *ibqp;
1691 struct mlx4_ib_dev *dev = to_mdev(device);
1692
1693 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1694
1695 if (!IS_ERR(ibqp) &&
1696 (init_attr->qp_type == IB_QPT_GSI) &&
1697 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1698 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1699 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1700
1701 if (is_eth &&
1702 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1703 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1704 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1705
1706 if (IS_ERR(sqp->roce_v2_gsi)) {
1707 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1708 sqp->roce_v2_gsi = NULL;
1709 } else {
1710 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1711 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1712 }
1713
1714 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1715 }
1716 }
1717 return ibqp;
1718}
1719
1720static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1721{
1722 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1723 struct mlx4_ib_qp *mqp = to_mqp(qp);
1724
1725 if (is_qp0(dev, mqp))
1726 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1727
c482af64
JM		 1728 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1729 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1730 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1731 dev->qp1_proxy[mqp->port - 1] = NULL;
1732 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1733 }
1734
7b59f0f9
EBE		 1735 if (mqp->counter_index)
1736 mlx4_ib_free_qp_counter(dev, mqp);
1737
3078f5f1
GL		 1738 if (qp->rwq_ind_tbl) {
1739 destroy_qp_rss(dev, mqp);
1740 } else {
1741 struct mlx4_ib_pd *pd;
1742
1743 pd = get_pd(mqp);
1744 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1745 }
225c7b1f
RD		 1746
1747 if (is_sqp(dev, mqp))
1748 kfree(to_msqp(mqp));
1749 else
1750 kfree(mqp);
1751
1752 return 0;
1753}
1754
e1b866c6
MS		 1755int mlx4_ib_destroy_qp(struct ib_qp *qp)
1756{
1757 struct mlx4_ib_qp *mqp = to_mqp(qp);
1758
1759 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1760 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1761
1762 if (sqp->roce_v2_gsi)
1763 ib_destroy_qp(sqp->roce_v2_gsi);
1764 }
1765
1766 return _mlx4_ib_destroy_qp(qp);
1767}
1768
1ffeb2eb 1769static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1770{
1771 switch (type) {
1ffeb2eb
JM		 1772 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1773 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1774 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1775 case MLX4_IB_QPT_XRC_INI:
1776 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1777 case MLX4_IB_QPT_SMI:
1778 case MLX4_IB_QPT_GSI:
1779 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1780
1781 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1782 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1783 MLX4_QP_ST_MLX : -1);
1784 case MLX4_IB_QPT_PROXY_SMI:
1785 case MLX4_IB_QPT_TUN_SMI:
1786 case MLX4_IB_QPT_PROXY_GSI:
1787 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1788 MLX4_QP_ST_UD : -1);
1789 default: return -1;
225c7b1f
RD		 1790 }
1791}
1792
65adfa91 1793static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1794 int attr_mask)
1795{
1796 u8 dest_rd_atomic;
1797 u32 access_flags;
1798 u32 hw_access_flags = 0;
1799
1800 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1801 dest_rd_atomic = attr->max_dest_rd_atomic;
1802 else
1803 dest_rd_atomic = qp->resp_depth;
1804
1805 if (attr_mask & IB_QP_ACCESS_FLAGS)
1806 access_flags = attr->qp_access_flags;
1807 else
1808 access_flags = qp->atomic_rd_en;
1809
1810 if (!dest_rd_atomic)
1811 access_flags &= IB_ACCESS_REMOTE_WRITE;
1812
1813 if (access_flags & IB_ACCESS_REMOTE_READ)
1814 hw_access_flags |= MLX4_QP_BIT_RRE;
1815 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1816 hw_access_flags |= MLX4_QP_BIT_RAE;
1817 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1818 hw_access_flags |= MLX4_QP_BIT_RWE;
1819
1820 return cpu_to_be32(hw_access_flags);
1821}
1822
65adfa91 1823static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1824 int attr_mask)
1825{
1826 if (attr_mask & IB_QP_PKEY_INDEX)
1827 sqp->pkey_index = attr->pkey_index;
1828 if (attr_mask & IB_QP_QKEY)
1829 sqp->qkey = attr->qkey;
1830 if (attr_mask & IB_QP_SQ_PSN)
1831 sqp->send_psn = attr->sq_psn;
1832}
1833
1834static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1835{
1836 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1837}
1838
90898850
DC		 1839static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1840 const struct rdma_ah_attr *ah,
297e0dad 1841 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1842 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1843{
4c3eb3ca 1844 int vidx;
297e0dad 1845 int smac_index;
2f5bb473 1846 int err;
297e0dad 1847
d8966fcd
DC		 1848 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1849 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1850 if (rdma_ah_get_static_rate(ah)) {
1851 path->static_rate = rdma_ah_get_static_rate(ah) +
1852 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1853 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1854 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1855 --path->static_rate;
1856 } else
1857 path->static_rate = 0;
225c7b1f 1858
d8966fcd
DC		 1859 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1860 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1861 int real_sgid_index =
7492052a 1862 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
5070cd22 1863
54a6d63f
DC		 1864 if (real_sgid_index < 0)
1865 return real_sgid_index;
5070cd22 1866 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1867 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1868 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1869 return -1;
1870 }
1871
1872 path->grh_mylmc |= 1 << 7;
5070cd22 1873 path->mgid_index = real_sgid_index;
d8966fcd 1874 path->hop_limit = grh->hop_limit;
225c7b1f 1875 path->tclass_flowlabel =
d8966fcd
DC		 1876 cpu_to_be32((grh->traffic_class << 20) |
1877 (grh->flow_label));
1878 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1879 }
1880
44c58487 1881 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1882 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1883 return -1;
1884
2f5bb473 1885 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1886 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1887
297e0dad 1888 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1889 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1890 if (smac_info->vid < 0x1000) {
1891 /* both valid vlan ids */
1892 if (smac_info->vid != vlan_tag) {
1893 /* different VIDs. unreg old and reg new */
1894 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1895 if (err)
1896 return err;
1897 smac_info->candidate_vid = vlan_tag;
1898 smac_info->candidate_vlan_index = vidx;
1899 smac_info->candidate_vlan_port = port;
1900 smac_info->update_vid = 1;
1901 path->vlan_index = vidx;
1902 } else {
1903 path->vlan_index = smac_info->vlan_index;
1904 }
1905 } else {
1906 /* no current vlan tag in qp */
1907 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1908 if (err)
1909 return err;
1910 smac_info->candidate_vid = vlan_tag;
1911 smac_info->candidate_vlan_index = vidx;
1912 smac_info->candidate_vlan_port = port;
1913 smac_info->update_vid = 1;
1914 path->vlan_index = vidx;
1915 }
297e0dad 1916 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1917 path->fl = 1 << 6;
1918 } else {
1919 /* have current vlan tag. unregister it at modify-qp success */
1920 if (smac_info->vid < 0x1000) {
1921 smac_info->candidate_vid = 0xFFFF;
1922 smac_info->update_vid = 1;
1923 }
4c3eb3ca 1924 }
2f5bb473
JM		 1925
1926 /* get smac_index for RoCE use.
1927 * If no smac was yet assigned, register one.
1928 * If one was already assigned, but the new mac differs,
1929 * unregister the old one and register the new one.
1930 */
25476b02
JM		 1931 if ((!smac_info->smac && !smac_info->smac_port) ||
1932 smac_info->smac != smac) {
2f5bb473
JM		 1933 /* register candidate now, unreg if needed, after success */
1934 smac_index = mlx4_register_mac(dev->dev, port, smac);
1935 if (smac_index >= 0) {
1936 smac_info->candidate_smac_index = smac_index;
1937 smac_info->candidate_smac = smac;
1938 smac_info->candidate_smac_port = port;
1939 } else {
1940 return -EINVAL;
1941 }
1942 } else {
1943 smac_index = smac_info->smac_index;
1944 }
44c58487 1945 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1946 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1947 /* put MAC table smac index for IBoE */
1948 path->grh_mylmc = (u8) (smac_index) | 0x80;
1949 } else {
4c3eb3ca 1950 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1951 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1952 }
fa417f7b 1953
225c7b1f
RD		 1954 return 0;
1955}
1956
297e0dad
MS		 1957static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1958 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1959 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1960 struct mlx4_qp_path *path, u8 port,
1961 u16 vlan_id, u8 *smac)
297e0dad
MS		 1962{
1963 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1964 mlx4_mac_to_u64(smac),
1965 vlan_id,
2f5bb473 1966 path, &mqp->pri, port);
297e0dad
MS		 1967}
1968
1969static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1970 const struct ib_qp_attr *qp,
1971 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1972 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1973 struct mlx4_qp_path *path, u8 port)
1974{
1975 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1976 0,
1977 0xffff,
2f5bb473 1978 path, &mqp->alt, port);
297e0dad
MS		 1979}
1980
fa417f7b
EC		 1981static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1982{
1983 struct mlx4_ib_gid_entry *ge, *tmp;
1984
1985 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1986 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1987 ge->added = 1;
1988 ge->port = qp->port;
1989 }
1990 }
1991}
1992
dbf727de
MB		 1993static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1994 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1995 struct mlx4_qp_context *context)
1996{
2f5bb473
JM		 1997 u64 u64_mac;
1998 int smac_index;
1999
3e0629cb 2000 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 2001
2002 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 2003 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 2004 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
2005 if (smac_index >= 0) {
2006 qp->pri.candidate_smac_index = smac_index;
2007 qp->pri.candidate_smac = u64_mac;
2008 qp->pri.candidate_smac_port = qp->port;
2009 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
2010 } else {
2011 return -ENOENT;
2012 }
2013 }
2014 return 0;
2015}
2016
7b59f0f9
EBE		 2017static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
2018{
2019 struct counter_index *new_counter_index;
2020 int err;
2021 u32 tmp_idx;
2022
2023 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
2024 IB_LINK_LAYER_ETHERNET ||
2025 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
2026 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
2027 return 0;
2028
f3301870 2029 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 2030 if (err)
2031 return err;
2032
2033 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
2034 if (!new_counter_index) {
2035 mlx4_counter_free(dev->dev, tmp_idx);
2036 return -ENOMEM;
2037 }
2038
2039 new_counter_index->index = tmp_idx;
2040 new_counter_index->allocated = 1;
2041 qp->counter_index = new_counter_index;
2042
2043 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
2044 list_add_tail(&new_counter_index->list,
2045 &dev->counters_table[qp->port - 1].counters_list);
2046 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2047
2048 return 0;
2049}
2050
3b5daf28
MS		 2051enum {
2052 MLX4_QPC_ROCE_MODE_1 = 0,
2053 MLX4_QPC_ROCE_MODE_2 = 2,
2054 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2055};
2056
2057static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2058{
2059 switch (gid_type) {
2060 case IB_GID_TYPE_ROCE:
2061 return MLX4_QPC_ROCE_MODE_1;
2062 case IB_GID_TYPE_ROCE_UDP_ENCAP:
2063 return MLX4_QPC_ROCE_MODE_2;
2064 default:
2065 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2066 }
2067}
2068
3078f5f1
GL		 2069/*
2070 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2071 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2072 */
2073static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2074{
fba02e6c 2075 int err = 0;
3078f5f1 2076 int i;
3078f5f1
GL		 2077
2078 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2079 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2080 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2081
2082 mutex_lock(&wq->mutex);
2083
2084 /* Mlx4_ib restrictions:
2085 * WQ's is associated to a port according to the RSS QP it is
2086 * associates to.
2087 * In case the WQ is associated to a different port by another
2088 * RSS QP, return a failure.
2089 */
2090 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2091 err = -EINVAL;
2092 mutex_unlock(&wq->mutex);
2093 break;
2094 }
2095 wq->port = port_num;
2096 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2097 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2098 if (err) {
2099 mutex_unlock(&wq->mutex);
2100 break;
2101 }
2102 }
2103 wq->rss_usecnt++;
2104
2105 mutex_unlock(&wq->mutex);
2106 }
2107
2108 if (i && err) {
2109 int j;
2110
2111 for (j = (i - 1); j >= 0; j--) {
2112 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2113 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2114
2115 mutex_lock(&wq->mutex);
2116
2117 if ((wq->rss_usecnt == 1) &&
2118 (ibwq->state == IB_WQS_RDY))
2119 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2120 pr_warn("failed to reverse WQN=0x%06x\n",
2121 ibwq->wq_num);
2122 wq->rss_usecnt--;
2123
2124 mutex_unlock(&wq->mutex);
2125 }
2126 }
2127
2128 return err;
2129}
2130
2131static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2132{
2133 int i;
2134
2135 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2136 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2137 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2138
2139 mutex_lock(&wq->mutex);
2140
2141 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2142 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2143 pr_warn("failed to reverse WQN=%x\n",
2144 ibwq->wq_num);
2145 wq->rss_usecnt--;
2146
2147 mutex_unlock(&wq->mutex);
2148 }
2149}
2150
2151static void fill_qp_rss_context(struct mlx4_qp_context *context,
2152 struct mlx4_ib_qp *qp)
2153{
2154 struct mlx4_rss_context *rss_context;
2155
2156 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2157 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2158
2159 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2160 rss_context->default_qpn =
2161 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2162 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2163 rss_context->base_qpn_udp = rss_context->default_qpn;
2164 rss_context->flags = qp->rss_ctx->flags;
2165 /* Currently support just toeplitz */
2166 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2167
2168 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2169 MLX4_EN_RSS_KEY_SIZE);
2170}
2171
400b1ebc 2172static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91
MT		 2173 const struct ib_qp_attr *attr, int attr_mask,
2174 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f 2175{
400b1ebc
GL		 2176 struct ib_uobject *ibuobject;
2177 struct ib_srq *ibsrq;
47ec3866 2178 const struct ib_gid_attr *gid_attr = NULL;
3078f5f1 2179 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2180 enum ib_qp_type qp_type;
2181 struct mlx4_ib_dev *dev;
2182 struct mlx4_ib_qp *qp;
0a1405da
SH		 2183 struct mlx4_ib_pd *pd;
2184 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 2185 struct mlx4_qp_context *context;
2186 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2187 int sqd_event;
c1c98501 2188 int steer_qp = 0;
225c7b1f 2189 int err = -EINVAL;
3ba8e31d 2190 int counter_index;
225c7b1f 2191
400b1ebc
GL		 2192 if (src_type == MLX4_IB_RWQ_SRC) {
2193 struct ib_wq *ibwq;
2194
3078f5f1
GL		 2195 ibwq = (struct ib_wq *)src;
2196 ibuobject = ibwq->uobject;
2197 ibsrq = NULL;
2198 rwq_ind_tbl = NULL;
2199 qp_type = IB_QPT_RAW_PACKET;
2200 qp = to_mqp((struct ib_qp *)ibwq);
2201 dev = to_mdev(ibwq->device);
2202 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2203 } else {
2204 struct ib_qp *ibqp;
2205
3078f5f1
GL		 2206 ibqp = (struct ib_qp *)src;
2207 ibuobject = ibqp->uobject;
2208 ibsrq = ibqp->srq;
2209 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2210 qp_type = ibqp->qp_type;
2211 qp = to_mqp(ibqp);
2212 dev = to_mdev(ibqp->device);
2213 pd = get_pd(qp);
400b1ebc
GL		 2214 }
2215
3dec4878
JM		 2216 /* APM is not supported under RoCE */
2217 if (attr_mask & IB_QP_ALT_PATH &&
2218 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2219 IB_LINK_LAYER_ETHERNET)
2220 return -ENOTSUPP;
2221
225c7b1f
RD		 2222 context = kzalloc(sizeof *context, GFP_KERNEL);
2223 if (!context)
2224 return -ENOMEM;
2225
225c7b1f 2226 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2227 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2228
2229 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2230 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2231 else {
2232 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2233 switch (attr->path_mig_state) {
2234 case IB_MIG_MIGRATED:
2235 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2236 break;
2237 case IB_MIG_REARM:
2238 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2239 break;
2240 case IB_MIG_ARMED:
2241 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2242 break;
2243 }
2244 }
2245
ea30b966
MG		 2246 if (qp->inl_recv_sz)
2247 context->param3 |= cpu_to_be32(1 << 25);
2248
6d06c9aa
GL		 2249 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2250 context->param3 |= cpu_to_be32(1 << 29);
2251
400b1ebc 2252 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2253 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2254 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2255 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2256 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2257 if (qp->flags & MLX4_IB_QP_LSO)
2258 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2259 ilog2(dev->dev->caps.max_gso_sz);
2260 else
5f22a1d8 2261 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2262 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2263 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2264 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2265 attr->path_mtu);
f5b40431 2266 goto out;
225c7b1f 2267 }
d1f2cd89
EC		 2268 context->mtu_msgmax = (attr->path_mtu << 5) |
2269 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2270 }
2271
3078f5f1
GL		 2272 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2273 if (qp->rq.wqe_cnt)
2274 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2275 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2276 }
225c7b1f 2277
0e6e7416
RD		 2278 if (qp->sq.wqe_cnt)
2279 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2280 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2281
7b59f0f9
EBE		 2282 if (new_state == IB_QPS_RESET && qp->counter_index)
2283 mlx4_ib_free_qp_counter(dev, qp);
2284
0a1405da 2285 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2286 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2287 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2288 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2289 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2290 }
0e6e7416 2291
400b1ebc 2292 if (ibuobject)
85743f1e
HN		 2293 context->usr_page = cpu_to_be32(
2294 mlx4_to_hw_uar_index(dev->dev,
400b1ebc
GL		 2295 to_mucontext(ibuobject->context)
2296 ->uar.index));
225c7b1f 2297 else
85743f1e
HN		 2298 context->usr_page = cpu_to_be32(
2299 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2300
2301 if (attr_mask & IB_QP_DEST_QPN)
2302 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2303
2304 if (attr_mask & IB_QP_PORT) {
2305 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2306 !(attr_mask & IB_QP_AV)) {
2307 mlx4_set_sched(&context->pri_path, attr->port_num);
2308 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2309 }
2310 }
2311
cfcde11c 2312 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2313 err = create_qp_lb_counter(dev, qp);
2314 if (err)
2315 goto out;
2316
3ba8e31d
EBE		 2317 counter_index =
2318 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2319 if (qp->counter_index)
2320 counter_index = qp->counter_index->index;
2321
3ba8e31d
EBE		 2322 if (counter_index != -1) {
2323 context->pri_path.counter_index = counter_index;
cfcde11c 2324 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2325 if (qp->counter_index) {
2326 context->pri_path.fl |=
2327 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2328 context->pri_path.vlan_control |=
2329 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2330 }
cfcde11c 2331 } else
47d8417f
EBE		 2332 context->pri_path.counter_index =
2333 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2334
2335 if (qp->flags & MLX4_IB_QP_NETIF) {
2336 mlx4_ib_steer_qp_reg(dev, qp, 1);
2337 steer_qp = 1;
2338 }
e1b866c6 2339
400b1ebc 2340 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2341 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2342 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2343 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2344
2345 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2346 }
cfcde11c
OG		 2347 }
2348
225c7b1f 2349 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2350 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2351 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2352 context->pri_path.pkey_index = attr->pkey_index;
2353 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2354 }
2355
225c7b1f 2356 if (attr_mask & IB_QP_AV) {
400b1ebc 2357 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de 2358 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
dbf727de
MB		 2359 u16 vlan = 0xffff;
2360 u8 smac[ETH_ALEN];
d8966fcd
DC		 2361 int is_eth =
2362 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2363 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2364
d8966fcd 2365 if (is_eth) {
47ec3866
PP		 2366 gid_attr = attr->ah_attr.grh.sgid_attr;
2367 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
2368 memcpy(smac, gid_attr->ndev->dev_addr, ETH_ALEN);
dbf727de 2369 }
dbf727de 2370
2f5bb473 2371 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2372 port_num, vlan, smac))
225c7b1f 2373 goto out;
225c7b1f
RD		 2374
2375 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2376 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2377
2378 if (is_eth &&
2379 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
47ec3866 2380 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
3b5daf28
MS		 2381
2382 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2383 err = -EINVAL;
2384 goto out;
2385 }
2386 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2387 }
2388
225c7b1f
RD		 2389 }
2390
2391 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2392 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2393 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2394 }
2395
2396 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2397 if (attr->alt_port_num == 0 ||
2398 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2399 goto out;
225c7b1f 2400
5ae2a7a8
RD		 2401 if (attr->alt_pkey_index >=
2402 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2403 goto out;
5ae2a7a8 2404
2f5bb473
JM		 2405 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2406 &context->alt_path,
297e0dad 2407 attr->alt_port_num))
f5b40431 2408 goto out;
225c7b1f
RD		 2409
2410 context->alt_path.pkey_index = attr->alt_pkey_index;
2411 context->alt_path.ackto = attr->alt_timeout << 3;
2412 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2413 }
2414
3078f5f1
GL		 2415 context->pd = cpu_to_be32(pd->pdn);
2416
2417 if (!rwq_ind_tbl) {
108809a0 2418 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2419 get_cqs(qp, src_type, &send_cq, &recv_cq);
2420 } else { /* Set dummy CQs to be compatible with HV and PRM */
2421 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2422 recv_cq = send_cq;
2423 }
0a1405da
SH		 2424 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2425 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2426
95d04f07 2427 /* Set "fast registration enabled" for all kernel QPs */
400b1ebc 2428 if (!ibuobject)
95d04f07
RD		 2429 context->params1 |= cpu_to_be32(1 << 11);
2430
57f01b53
JM		 2431 if (attr_mask & IB_QP_RNR_RETRY) {
2432 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2433 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2434 }
2435
225c7b1f
RD		 2436 if (attr_mask & IB_QP_RETRY_CNT) {
2437 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2438 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2439 }
2440
2441 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2442 if (attr->max_rd_atomic)
2443 context->params1 |=
2444 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2445 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2446 }
2447
2448 if (attr_mask & IB_QP_SQ_PSN)
2449 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2450
225c7b1f
RD		 2451 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2452 if (attr->max_dest_rd_atomic)
2453 context->params2 |=
2454 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2455 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2456 }
2457
2458 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2459 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2460 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2461 }
2462
400b1ebc 2463 if (ibsrq)
225c7b1f
RD		 2464 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2465
2466 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2467 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2468 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2469 }
2470 if (attr_mask & IB_QP_RQ_PSN)
2471 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2472
1ffeb2eb 2473 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2474 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2475 if (qp->mlx4_ib_qp_type &
2476 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2477 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2478 else {
2479 if (mlx4_is_mfunc(dev->dev) &&
2480 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2481 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2482 MLX4_RESERVED_QKEY_BASE) {
2483 pr_err("Cannot use reserved QKEY"
2484 " 0x%x (range 0xffff0000..0xffffffff"
2485 " is reserved)\n", attr->qkey);
2486 err = -EINVAL;
2487 goto out;
2488 }
2489 context->qkey = cpu_to_be32(attr->qkey);
2490 }
225c7b1f
RD		 2491 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2492 }
2493
400b1ebc
GL		 2494 if (ibsrq)
2495 context->srqn = cpu_to_be32(1 << 24 |
2496 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2497
400b1ebc
GL		 2498 if (qp->rq.wqe_cnt &&
2499 cur_state == IB_QPS_RESET &&
2500 new_state == IB_QPS_INIT)
225c7b1f
RD		 2501 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2502
2503 if (cur_state == IB_QPS_INIT &&
2504 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2505 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2506 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2507 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2508 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2509 qp->mlx4_ib_qp_type &
2510 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2511 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2512 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2513 context->pri_path.fl = 0x80;
2514 } else {
2515 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2516 context->pri_path.fl = 0x80;
225c7b1f 2517 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2518 }
2f5bb473
JM		 2519 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2520 IB_LINK_LAYER_ETHERNET) {
2521 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2522 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2523 context->pri_path.feup = 1 << 7; /* don't fsm */
2524 /* handle smac_index */
2525 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2526 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2527 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2528 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2529 if (err) {
2530 err = -EINVAL;
2531 goto out;
2532 }
9433c188
MB		 2533 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2534 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2535 }
2536 }
225c7b1f
RD		 2537 }
2538
400b1ebc 2539 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2540 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2541 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2542 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2543 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2544 if (!rwq_ind_tbl)
d2fce8a9
OG		 2545 context->srqn = cpu_to_be32(7 << 28);
2546 }
2547 }
3528f696 2548
400b1ebc 2549 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2550 int is_eth = rdma_port_get_link_layer(
2551 &dev->ib_dev, qp->port) ==
2552 IB_LINK_LAYER_ETHERNET;
2553 if (is_eth) {
2554 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2555 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2556 }
2557 }
2558
225c7b1f
RD		 2559 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2560 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2561 sqd_event = 1;
2562 else
2563 sqd_event = 0;
2564
400b1ebc
GL		 2565 if (!ibuobject &&
2566 cur_state == IB_QPS_RESET &&
2567 new_state == IB_QPS_INIT)
3b5daf28 2568 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2569
c0be5fb5
EC		 2570 /*
2571 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2572 * ownership bits of the send queue are set and the SQ
2573 * headroom is stamped so that the hardware doesn't start
2574 * processing stale work requests.
c0be5fb5 2575 */
400b1ebc
GL		 2576 if (!ibuobject &&
2577 cur_state == IB_QPS_RESET &&
2578 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2579 struct mlx4_wqe_ctrl_seg *ctrl;
2580 int i;
2581
0e6e7416 2582 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2583 ctrl = get_send_wqe(qp, i);
2584 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553 2585 if (qp->sq_max_wqes_per_wr == 1)
224e92e0
BB		 2586 ctrl->qpn_vlan.fence_size =
2587 1 << (qp->sq.wqe_shift - 4);
0e6e7416 2588
ea54b10c 2589 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 2590 }
2591 }
2592
108809a0
GL		 2593 if (rwq_ind_tbl &&
2594 cur_state == IB_QPS_RESET &&
2595 new_state == IB_QPS_INIT) {
2596 fill_qp_rss_context(context, qp);
2597 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2598 }
2599
225c7b1f
RD		 2600 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2601 to_mlx4_state(new_state), context, optpar,
2602 sqd_event, &qp->mqp);
2603 if (err)
2604 goto out;
2605
2606 qp->state = new_state;
2607
2608 if (attr_mask & IB_QP_ACCESS_FLAGS)
2609 qp->atomic_rd_en = attr->qp_access_flags;
2610 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2611 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2612 if (attr_mask & IB_QP_PORT) {
225c7b1f 2613 qp->port = attr->port_num;
fa417f7b
EC		 2614 update_mcg_macs(dev, qp);
2615 }
225c7b1f
RD		 2616 if (attr_mask & IB_QP_ALT_PATH)
2617 qp->alt_port = attr->alt_port_num;
2618
2619 if (is_sqp(dev, qp))
2620 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2621
2622 /*
2623 * If we moved QP0 to RTR, bring the IB link up; if we moved
2624 * QP0 to RESET or ERROR, bring the link back down.
2625 */
2626 if (is_qp0(dev, qp)) {
2627 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2628 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2629 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2630 qp->port);
225c7b1f
RD		 2631
2632 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2633 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2634 mlx4_CLOSE_PORT(dev->dev, qp->port);
2635 }
2636
2637 /*
2638 * If we moved a kernel QP to RESET, clean up all old CQ
2639 * entries and reinitialize the QP.
2640 */
2f5bb473 2641 if (new_state == IB_QPS_RESET) {
400b1ebc 2642 if (!ibuobject) {
2f5bb473 2643 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2644 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2645 if (send_cq != recv_cq)
2646 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2647
2648 qp->rq.head = 0;
2649 qp->rq.tail = 0;
2650 qp->sq.head = 0;
2651 qp->sq.tail = 0;
2652 qp->sq_next_wqe = 0;
2653 if (qp->rq.wqe_cnt)
2654 *qp->db.db = 0;
225c7b1f 2655
2f5bb473
JM		 2656 if (qp->flags & MLX4_IB_QP_NETIF)
2657 mlx4_ib_steer_qp_reg(dev, qp, 0);
2658 }
25476b02 2659 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2660 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2661 qp->pri.smac = 0;
25476b02 2662 qp->pri.smac_port = 0;
2f5bb473
JM		 2663 }
2664 if (qp->alt.smac) {
2665 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2666 qp->alt.smac = 0;
2667 }
2668 if (qp->pri.vid < 0x1000) {
2669 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2670 qp->pri.vid = 0xFFFF;
2671 qp->pri.candidate_vid = 0xFFFF;
2672 qp->pri.update_vid = 0;
2673 }
c1c98501 2674
2f5bb473
JM		 2675 if (qp->alt.vid < 0x1000) {
2676 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2677 qp->alt.vid = 0xFFFF;
2678 qp->alt.candidate_vid = 0xFFFF;
2679 qp->alt.update_vid = 0;
2680 }
225c7b1f 2681 }
225c7b1f 2682out:
7b59f0f9
EBE		 2683 if (err && qp->counter_index)
2684 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2685 if (err && steer_qp)
2686 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2687 kfree(context);
25476b02
JM		 2688 if (qp->pri.candidate_smac ||
2689 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2690 if (err) {
2691 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2692 } else {
25476b02 2693 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2694 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2695 qp->pri.smac = qp->pri.candidate_smac;
2696 qp->pri.smac_index = qp->pri.candidate_smac_index;
2697 qp->pri.smac_port = qp->pri.candidate_smac_port;
2698 }
2699 qp->pri.candidate_smac = 0;
2700 qp->pri.candidate_smac_index = 0;
2701 qp->pri.candidate_smac_port = 0;
2702 }
2703 if (qp->alt.candidate_smac) {
2704 if (err) {
2705 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2706 } else {
2707 if (qp->alt.smac)
2708 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2709 qp->alt.smac = qp->alt.candidate_smac;
2710 qp->alt.smac_index = qp->alt.candidate_smac_index;
2711 qp->alt.smac_port = qp->alt.candidate_smac_port;
2712 }
2713 qp->alt.candidate_smac = 0;
2714 qp->alt.candidate_smac_index = 0;
2715 qp->alt.candidate_smac_port = 0;
2716 }
2717
2718 if (qp->pri.update_vid) {
2719 if (err) {
2720 if (qp->pri.candidate_vid < 0x1000)
2721 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2722 qp->pri.candidate_vid);
2723 } else {
2724 if (qp->pri.vid < 0x1000)
2725 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2726 qp->pri.vid);
2727 qp->pri.vid = qp->pri.candidate_vid;
2728 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2729 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2730 }
2731 qp->pri.candidate_vid = 0xFFFF;
2732 qp->pri.update_vid = 0;
2733 }
2734
2735 if (qp->alt.update_vid) {
2736 if (err) {
2737 if (qp->alt.candidate_vid < 0x1000)
2738 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2739 qp->alt.candidate_vid);
2740 } else {
2741 if (qp->alt.vid < 0x1000)
2742 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2743 qp->alt.vid);
2744 qp->alt.vid = qp->alt.candidate_vid;
2745 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2746 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2747 }
2748 qp->alt.candidate_vid = 0xFFFF;
2749 qp->alt.update_vid = 0;
2750 }
2751
225c7b1f
RD		 2752 return err;
2753}
2754
3078f5f1
GL		 2755enum {
2756 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2757 IB_QP_PORT),
2758};
2759
e1b866c6
MS		 2760static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2761 int attr_mask, struct ib_udata *udata)
65adfa91 2762{
17bf1ad2 2763 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
65adfa91
MT		 2764 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2765 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2766 enum ib_qp_state cur_state, new_state;
2767 int err = -EINVAL;
65adfa91
MT		 2768 mutex_lock(&qp->mutex);
2769
2770 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2771 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2772
17bf1ad2 2773 if (cur_state != new_state || cur_state != IB_QPS_RESET) {
297e0dad
MS		 2774 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2775 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2776 }
dd5f03be
MB		 2777
2778 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2779 attr_mask, ll)) {
b1d8eb5a
JM		 2780 pr_debug("qpn 0x%x: invalid attribute mask specified "
2781 "for transition %d to %d. qp_type %d,"
2782 " attr_mask 0x%x\n",
2783 ibqp->qp_num, cur_state, new_state,
2784 ibqp->qp_type, attr_mask);
65adfa91 2785 goto out;
b1d8eb5a 2786 }
65adfa91 2787
3078f5f1
GL		 2788 if (ibqp->rwq_ind_tbl) {
2789 if (!(((cur_state == IB_QPS_RESET) &&
2790 (new_state == IB_QPS_INIT)) ||
2791 ((cur_state == IB_QPS_INIT) &&
2792 (new_state == IB_QPS_RTR)))) {
2793 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2794 ibqp->qp_num, cur_state, new_state);
2795
2796 err = -EOPNOTSUPP;
2797 goto out;
2798 }
2799
2800 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2801 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2802 ibqp->qp_num, attr_mask, cur_state, new_state);
2803
2804 err = -EOPNOTSUPP;
2805 goto out;
2806 }
2807 }
2808
c6215745
MS		 2809 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2810 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2811 if ((ibqp->qp_type == IB_QPT_RC) ||
2812 (ibqp->qp_type == IB_QPT_UD) ||
2813 (ibqp->qp_type == IB_QPT_UC) ||
2814 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2815 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2816 attr->port_num = mlx4_ib_bond_next_port(dev);
2817 }
2818 } else {
2819 /* no sense in changing port_num
2820 * when ports are bonded */
2821 attr_mask &= ~IB_QP_PORT;
2822 }
2823 }
2824
65adfa91 2825 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2826 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2827 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2828 "for transition %d to %d. qp_type %d\n",
2829 ibqp->qp_num, attr->port_num, cur_state,
2830 new_state, ibqp->qp_type);
65adfa91
MT		 2831 goto out;
2832 }
2833
3987a2d3
OG		 2834 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2835 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2836 IB_LINK_LAYER_ETHERNET))
2837 goto out;
2838
5ae2a7a8
RD		 2839 if (attr_mask & IB_QP_PKEY_INDEX) {
2840 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2841 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2842 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2843 "for transition %d to %d. qp_type %d\n",
2844 ibqp->qp_num, attr->pkey_index, cur_state,
2845 new_state, ibqp->qp_type);
5ae2a7a8 2846 goto out;
b1d8eb5a 2847 }
5ae2a7a8
RD		 2848 }
2849
65adfa91
MT		 2850 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2851 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2852 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2853 "Transition %d to %d. qp_type %d\n",
2854 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2855 new_state, ibqp->qp_type);
65adfa91
MT		 2856 goto out;
2857 }
2858
2859 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2860 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2861 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2862 "Transition %d to %d. qp_type %d\n",
2863 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2864 new_state, ibqp->qp_type);
65adfa91
MT		 2865 goto out;
2866 }
2867
2868 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2869 err = 0;
2870 goto out;
2871 }
2872
3078f5f1
GL		 2873 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2874 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2875 if (err)
2876 goto out;
2877 }
2878
400b1ebc
GL		 2879 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2880 cur_state, new_state);
65adfa91 2881
3078f5f1
GL		 2882 if (ibqp->rwq_ind_tbl && err)
2883 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2884
c6215745
MS		 2885 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2886 attr->port_num = 1;
2887
65adfa91
MT		 2888out:
2889 mutex_unlock(&qp->mutex);
2890 return err;
2891}
2892
e1b866c6
MS		 2893int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2894 int attr_mask, struct ib_udata *udata)
2895{
2896 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2897 int ret;
2898
2899 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2900
2901 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2902 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2903 int err = 0;
2904
2905 if (sqp->roce_v2_gsi)
2906 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2907 if (err)
2908 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2909 err);
2910 }
2911 return ret;
2912}
2913
99ec41d0
JM		 2914static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2915{
2916 int i;
2917 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2918 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2919 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2920 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2921 return 0;
2922 }
2923 }
2924 return -EINVAL;
2925}
2926
1ffeb2eb 2927static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
f696bf6d 2928 const struct ib_ud_wr *wr,
1ffeb2eb
JM		 2929 void *wqe, unsigned *mlx_seg_len)
2930{
2931 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2932 struct ib_device *ib_dev = &mdev->ib_dev;
2933 struct mlx4_wqe_mlx_seg *mlx = wqe;
2934 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2935 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2936 u16 pkey;
2937 u32 qkey;
2938 int send_size;
2939 int header_size;
2940 int spc;
2941 int i;
2942
e622f2f4 2943 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2944 return -EINVAL;
2945
2946 send_size = 0;
2947
e622f2f4
CH		 2948 for (i = 0; i < wr->wr.num_sge; ++i)
2949 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2950
2951 /* for proxy-qp0 sends, need to add in size of tunnel header */
2952 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2953 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2954 send_size += sizeof (struct mlx4_ib_tunnel_header);
2955
25f40220 2956 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2957
2958 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2959 sqp->ud_header.lrh.service_level =
2960 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2961 sqp->ud_header.lrh.destination_lid =
2962 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2963 sqp->ud_header.lrh.source_lid =
2964 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2965 }
2966
2967 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2968
2969 /* force loopback */
2970 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2971 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2972
2973 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2974 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2975 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2976 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2977 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2978 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2979 else
2980 sqp->ud_header.bth.destination_qpn =
c73c8b1e 2981 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
1ffeb2eb
JM		 2982
2983 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2984 if (mlx4_is_master(mdev->dev)) {
2985 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2986 return -EINVAL;
2987 } else {
2988 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2989 return -EINVAL;
2990 }
1ffeb2eb
JM		 2991 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2992 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2993
2994 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2995 sqp->ud_header.immediate_present = 0;
2996
2997 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2998
2999 /*
3000 * Inline data segments may not cross a 64 byte boundary. If
3001 * our UD header is bigger than the space available up to the
3002 * next 64 byte boundary in the WQE, use two inline data
3003 * segments to hold the UD header.
3004 */
3005 spc = MLX4_INLINE_ALIGN -
3006 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3007 if (header_size <= spc) {
3008 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3009 memcpy(inl + 1, sqp->header_buf, header_size);
3010 i = 1;
3011 } else {
3012 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3013 memcpy(inl + 1, sqp->header_buf, spc);
3014
3015 inl = (void *) (inl + 1) + spc;
3016 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3017 /*
3018 * Need a barrier here to make sure all the data is
3019 * visible before the byte_count field is set.
3020 * Otherwise the HCA prefetcher could grab the 64-byte
3021 * chunk with this inline segment and get a valid (!=
3022 * 0xffffffff) byte count but stale data, and end up
3023 * generating a packet with bad headers.
3024 *
3025 * The first inline segment's byte_count field doesn't
3026 * need a barrier, because it comes after a
3027 * control/MLX segment and therefore is at an offset
3028 * of 16 mod 64.
3029 */
3030 wmb();
3031 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3032 i = 2;
3033 }
3034
3035 *mlx_seg_len =
3036 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3037 return 0;
3038}
3039
fd10ed8e
JM		 3040static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3041{
3042 union sl2vl_tbl_to_u64 tmp_vltab;
3043 u8 vl;
3044
3045 if (sl > 15)
3046 return 0xf;
3047 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3048 vl = tmp_vltab.sl8[sl >> 1];
3049 if (sl & 1)
3050 vl &= 0x0f;
3051 else
3052 vl >>= 4;
3053 return vl;
3054}
3055
a748d60d
TB		 3056static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3057 int index, union ib_gid *gid,
3058 enum ib_gid_type *gid_type)
3059{
3060 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3061 struct mlx4_port_gid_table *port_gid_table;
3062 unsigned long flags;
3063
3064 port_gid_table = &iboe->gids[port_num - 1];
3065 spin_lock_irqsave(&iboe->lock, flags);
3066 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3067 *gid_type = port_gid_table->gids[index].gid_type;
3068 spin_unlock_irqrestore(&iboe->lock, flags);
25e62655 3069 if (rdma_is_zero_gid(gid))
a748d60d
TB		 3070 return -ENOENT;
3071
3072 return 0;
3073}
3074
3ef967a4 3075#define MLX4_ROCEV2_QP1_SPORT 0xC000
f696bf6d 3076static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr,
f438000f 3077 void *wqe, unsigned *mlx_seg_len)
225c7b1f 3078{
a478868a 3079 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 3080 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 3081 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 3082 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 3083 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 3084 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 3085 union ib_gid sgid;
225c7b1f
RD		 3086 u16 pkey;
3087 int send_size;
3088 int header_size;
e61ef241 3089 int spc;
225c7b1f 3090 int i;
1ffeb2eb 3091 int err = 0;
57d88cff 3092 u16 vlan = 0xffff;
a29bec12
RD		 3093 bool is_eth;
3094 bool is_vlan = false;
3095 bool is_grh;
3ef967a4
MS		 3096 bool is_udp = false;
3097 int ip_version = 0;
225c7b1f
RD		 3098
3099 send_size = 0;
e622f2f4
CH		 3100 for (i = 0; i < wr->wr.num_sge; ++i)
3101 send_size += wr->wr.sg_list[i].length;
225c7b1f 3102
fa417f7b
EC		 3103 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3104 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3105 if (is_eth) {
a748d60d 3106 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3107 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3108 /* When multi-function is enabled, the ib_core gid
3109 * indexes don't necessarily match the hw ones, so
3110 * we must use our own cache */
6ee51a4e
JM		 3111 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3112 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3113 ah->av.ib.gid_index, &sgid.raw[0]);
3114 if (err)
3115 return err;
1ffeb2eb 3116 } else {
a748d60d
TB		 3117 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3118 ah->av.ib.gid_index,
3119 &sgid, &gid_type);
3ef967a4 3120 if (!err) {
a748d60d 3121 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3122 if (is_udp) {
3123 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3124 ip_version = 4;
3125 else
3126 ip_version = 6;
3127 is_grh = false;
3128 }
3129 } else {
1ffeb2eb 3130 return err;
3ef967a4 3131 }
1ffeb2eb 3132 }
0e9855db 3133 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 3134 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3135 is_vlan = 1;
3136 }
4c3eb3ca 3137 }
25f40220 3138 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3139 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3140 if (err)
3141 return err;
fa417f7b
EC		 3142
3143 if (!is_eth) {
3144 sqp->ud_header.lrh.service_level =
3145 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3146 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3147 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3148 }
225c7b1f 3149
3ef967a4 3150 if (is_grh || (ip_version == 6)) {
225c7b1f 3151 sqp->ud_header.grh.traffic_class =
fa417f7b 3152 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3153 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3154 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3155 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3156 if (is_eth) {
6ee51a4e 3157 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3158 } else {
3159 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3160 /* When multi-function is enabled, the ib_core gid
3161 * indexes don't necessarily match the hw ones, so
3162 * we must use our own cache
3163 */
3164 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3165 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3166 demux[sqp->qp.port - 1].
3167 subnet_prefix)));
baa0be70
JM		 3168 sqp->ud_header.grh.source_gid.global.interface_id =
3169 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3170 guid_cache[ah->av.ib.gid_index];
3171 } else {
89af969a
PP		 3172 sqp->ud_header.grh.source_gid =
3173 ah->ibah.sgid_attr->gid;
baa0be70 3174 }
6ee51a4e 3175 }
225c7b1f 3176 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3177 ah->av.ib.dgid, 16);
225c7b1f
RD		 3178 }
3179
3ef967a4
MS		 3180 if (ip_version == 4) {
3181 sqp->ud_header.ip4.tos =
3182 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3183 sqp->ud_header.ip4.id = 0;
3184 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3185 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3186
3187 memcpy(&sqp->ud_header.ip4.saddr,
3188 sgid.raw + 12, 4);
3189 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3190 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3191 }
3192
3193 if (is_udp) {
3194 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3195 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3196 sqp->ud_header.udp.csum = 0;
3197 }
3198
225c7b1f 3199 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3200
3201 if (!is_eth) {
3202 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3203 (sqp->ud_header.lrh.destination_lid ==
3204 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3205 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3206 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3207 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3208 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3209 }
225c7b1f 3210
e622f2f4 3211 switch (wr->wr.opcode) {
225c7b1f
RD		 3212 case IB_WR_SEND:
3213 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3214 sqp->ud_header.immediate_present = 0;
3215 break;
3216 case IB_WR_SEND_WITH_IMM:
3217 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3218 sqp->ud_header.immediate_present = 1;
e622f2f4 3219 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3220 break;
3221 default:
3222 return -EINVAL;
3223 }
3224
fa417f7b 3225 if (is_eth) {
6ee51a4e 3226 struct in6_addr in6;
3ef967a4 3227 u16 ether_type;
c0c1d3d7
OD		 3228 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3229
69ae5439 3230 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3231 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3232
c0c1d3d7 3233 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3234
1049f138 3235 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3236 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3237 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3238 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3239 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3240
3e0629cb 3241
fa417f7b
EC		 3242 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3243 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3244 if (!is_vlan) {
3ef967a4 3245 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3246 } else {
3ef967a4 3247 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3248 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3249 }
fa417f7b 3250 } else {
fd10ed8e
JM		 3251 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3252 sl_to_vl(to_mdev(ib_dev),
3253 sqp->ud_header.lrh.service_level,
3254 sqp->qp.port);
3255 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3256 return -EINVAL;
fa417f7b
EC		 3257 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3258 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3259 }
e622f2f4 3260 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 3261 if (!sqp->qp.ibqp.qp_num)
3262 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3263 else
e622f2f4 3264 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 3265 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3266 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3267 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3268 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3269 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3270 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3271
3272 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3273
3274 if (0) {
987c8f8f 3275 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3276 for (i = 0; i < header_size / 4; ++i) {
3277 if (i % 8 == 0)
987c8f8f
SP		 3278 pr_err(" [%02x] ", i * 4);
3279 pr_cont(" %08x",
3280 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3281 if ((i + 1) % 8 == 0)
987c8f8f 3282 pr_cont("\n");
225c7b1f 3283 }
987c8f8f 3284 pr_err("\n");
225c7b1f
RD		 3285 }
3286
e61ef241
RD		 3287 /*
3288 * Inline data segments may not cross a 64 byte boundary. If
3289 * our UD header is bigger than the space available up to the
3290 * next 64 byte boundary in the WQE, use two inline data
3291 * segments to hold the UD header.
3292 */
3293 spc = MLX4_INLINE_ALIGN -
3294 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3295 if (header_size <= spc) {
3296 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3297 memcpy(inl + 1, sqp->header_buf, header_size);
3298 i = 1;
3299 } else {
3300 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3301 memcpy(inl + 1, sqp->header_buf, spc);
3302
3303 inl = (void *) (inl + 1) + spc;
3304 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3305 /*
3306 * Need a barrier here to make sure all the data is
3307 * visible before the byte_count field is set.
3308 * Otherwise the HCA prefetcher could grab the 64-byte
3309 * chunk with this inline segment and get a valid (!=
3310 * 0xffffffff) byte count but stale data, and end up
3311 * generating a packet with bad headers.
3312 *
3313 * The first inline segment's byte_count field doesn't
3314 * need a barrier, because it comes after a
3315 * control/MLX segment and therefore is at an offset
3316 * of 16 mod 64.
3317 */
3318 wmb();
3319 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3320 i = 2;
3321 }
225c7b1f 3322
f438000f
RD		 3323 *mlx_seg_len =
3324 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3325 return 0;
225c7b1f
RD		 3326}
3327
3328static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3329{
3330 unsigned cur;
3331 struct mlx4_ib_cq *cq;
3332
3333 cur = wq->head - wq->tail;
0e6e7416 3334 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3335 return 0;
3336
3337 cq = to_mcq(ib_cq);
3338 spin_lock(&cq->lock);
3339 cur = wq->head - wq->tail;
3340 spin_unlock(&cq->lock);
3341
0e6e7416 3342 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3343}
3344
95d04f07
RD		 3345static __be32 convert_access(int acc)
3346{
6ff63e19
SM		 3347 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3348 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3349 (acc & IB_ACCESS_REMOTE_WRITE ?
3350 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3351 (acc & IB_ACCESS_REMOTE_READ ?
3352 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3353 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3354 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3355}
3356
1b2cd0fc 3357static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
f696bf6d 3358 const struct ib_reg_wr *wr)
1b2cd0fc
SG		 3359{
3360 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3361
3362 fseg->flags = convert_access(wr->access);
3363 fseg->mem_key = cpu_to_be32(wr->key);
3364 fseg->buf_list = cpu_to_be64(mr->page_map);
3365 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3366 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3367 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3368 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3369 fseg->reserved[0] = 0;
3370 fseg->reserved[1] = 0;
3371}
3372
95d04f07
RD		 3373static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3374{
aee38fad
SM		 3375 memset(iseg, 0, sizeof(*iseg));
3376 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3377}
3378
0fbfa6a9
RD		 3379static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3380 u64 remote_addr, u32 rkey)
3381{
3382 rseg->raddr = cpu_to_be64(remote_addr);
3383 rseg->rkey = cpu_to_be32(rkey);
3384 rseg->reserved = 0;
3385}
3386
e622f2f4 3387static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
f696bf6d 3388 const struct ib_atomic_wr *wr)
0fbfa6a9 3389{
e622f2f4
CH		 3390 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3391 aseg->swap_add = cpu_to_be64(wr->swap);
3392 aseg->compare = cpu_to_be64(wr->compare_add);
3393 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3394 aseg->swap_add = cpu_to_be64(wr->compare_add);
3395 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3396 } else {
e622f2f4 3397 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3398 aseg->compare = 0;
3399 }
3400
3401}
3402
6fa8f719 3403static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
f696bf6d 3404 const struct ib_atomic_wr *wr)
6fa8f719 3405{
e622f2f4
CH		 3406 aseg->swap_add = cpu_to_be64(wr->swap);
3407 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3408 aseg->compare = cpu_to_be64(wr->compare_add);
3409 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3410}
3411
0fbfa6a9 3412static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3413 const struct ib_ud_wr *wr)
0fbfa6a9 3414{
e622f2f4
CH		 3415 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3416 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3417 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3418 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3419 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3420}
3421
1ffeb2eb
JM		 3422static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3423 struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3424 const struct ib_ud_wr *wr,
97982f5a 3425 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3426{
e622f2f4 3427 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3428 struct mlx4_av sqp_av = {0};
3429 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3430
3431 /* force loopback */
3432 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3433 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3434 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3435 cpu_to_be32(0xf0000000);
3436
3437 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3438 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3439 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3440 else
c73c8b1e 3441 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3442 /* Use QKEY from the QP context, which is set by master */
3443 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3444}
3445
f696bf6d
BVA		 3446static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3447 unsigned *mlx_seg_len)
1ffeb2eb
JM		 3448{
3449 struct mlx4_wqe_inline_seg *inl = wqe;
3450 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3451 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3452 int spc;
3453 int i;
3454
3455 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3456 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3457 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3458 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3459 memcpy(hdr.mac, ah->av.eth.mac, 6);
3460 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3461
3462 spc = MLX4_INLINE_ALIGN -
3463 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3464 if (sizeof (hdr) <= spc) {
3465 memcpy(inl + 1, &hdr, sizeof (hdr));
3466 wmb();
3467 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3468 i = 1;
3469 } else {
3470 memcpy(inl + 1, &hdr, spc);
3471 wmb();
3472 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3473
3474 inl = (void *) (inl + 1) + spc;
3475 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3476 wmb();
3477 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3478 i = 2;
3479 }
3480
3481 *mlx_seg_len =
3482 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3483}
3484
6e694ea3
JM		 3485static void set_mlx_icrc_seg(void *dseg)
3486{
3487 u32 *t = dseg;
3488 struct mlx4_wqe_inline_seg *iseg = dseg;
3489
3490 t[1] = 0;
3491
3492 /*
3493 * Need a barrier here before writing the byte_count field to
3494 * make sure that all the data is visible before the
3495 * byte_count field is set. Otherwise, if the segment begins
3496 * a new cacheline, the HCA prefetcher could grab the 64-byte
3497 * chunk and get a valid (!= * 0xffffffff) byte count but
3498 * stale data, and end up sending the wrong data.
3499 */
3500 wmb();
3501
3502 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3503}
3504
3505static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3506{
d420d9e3
RD		 3507 dseg->lkey = cpu_to_be32(sg->lkey);
3508 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3509
3510 /*
3511 * Need a barrier here before writing the byte_count field to
3512 * make sure that all the data is visible before the
3513 * byte_count field is set. Otherwise, if the segment begins
3514 * a new cacheline, the HCA prefetcher could grab the 64-byte
3515 * chunk and get a valid (!= * 0xffffffff) byte count but
3516 * stale data, and end up sending the wrong data.
3517 */
3518 wmb();
3519
3520 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3521}
3522
2242fa4f
RD		 3523static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3524{
3525 dseg->byte_count = cpu_to_be32(sg->length);
3526 dseg->lkey = cpu_to_be32(sg->lkey);
3527 dseg->addr = cpu_to_be64(sg->addr);
3528}
3529
f696bf6d
BVA		 3530static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3531 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3532 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3533{
e622f2f4 3534 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3535
417608c2
EC		 3536 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3537 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3538
3539 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3540 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3541 return -EINVAL;
3542
e622f2f4 3543 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3544
e622f2f4 3545 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3546 *lso_seg_len = halign;
3547 return 0;
3548}
3549
f696bf6d 3550static __be32 send_ieth(const struct ib_send_wr *wr)
95d04f07
RD		 3551{
3552 switch (wr->opcode) {
3553 case IB_WR_SEND_WITH_IMM:
3554 case IB_WR_RDMA_WRITE_WITH_IMM:
3555 return wr->ex.imm_data;
3556
3557 case IB_WR_SEND_WITH_INV:
3558 return cpu_to_be32(wr->ex.invalidate_rkey);
3559
3560 default:
3561 return 0;
3562 }
3563}
3564
1ffeb2eb
JM		 3565static void add_zero_len_inline(void *wqe)
3566{
3567 struct mlx4_wqe_inline_seg *inl = wqe;
3568 memset(wqe, 0, 16);
3569 inl->byte_count = cpu_to_be32(1 << 31);
3570}
3571
d34ac5cd
BVA		 3572static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3573 const struct ib_send_wr **bad_wr, bool drain)
225c7b1f
RD		 3574{
3575 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3576 void *wqe;
3577 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3578 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3579 unsigned long flags;
3580 int nreq;
3581 int err = 0;
ea54b10c
JM		 3582 unsigned ind;
3583 int uninitialized_var(stamp);
3584 int uninitialized_var(size);
a3d8e159 3585 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 3586 __be32 dummy;
3587 __be32 *lso_wqe;
3588 __be32 uninitialized_var(lso_hdr_sz);
417608c2 3589 __be32 blh;
225c7b1f 3590 int i;
35f05dab 3591 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3592
e1b866c6
MS		 3593 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3594 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3595
3596 if (sqp->roce_v2_gsi) {
3597 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3598 enum ib_gid_type gid_type;
e1b866c6
MS		 3599 union ib_gid gid;
3600
a748d60d
TB		 3601 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3602 ah->av.ib.gid_index,
3603 &gid, &gid_type))
3604 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3605 to_mqp(sqp->roce_v2_gsi) : qp;
3606 else
e1b866c6
MS		 3607 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3608 ah->av.ib.gid_index);
e1b866c6
MS		 3609 }
3610 }
3611
96db0e03 3612 spin_lock_irqsave(&qp->sq.lock, flags);
1975acd9
YH		 3613 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3614 !drain) {
35f05dab
YH		 3615 err = -EIO;
3616 *bad_wr = wr;
3617 nreq = 0;
3618 goto out;
3619 }
225c7b1f 3620
ea54b10c 3621 ind = qp->sq_next_wqe;
225c7b1f
RD		 3622
3623 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3624 lso_wqe = &dummy;
417608c2 3625 blh = 0;
0fd7e1d8 3626
225c7b1f
RD		 3627 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3628 err = -ENOMEM;
3629 *bad_wr = wr;
3630 goto out;
3631 }
3632
3633 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3634 err = -EINVAL;
3635 *bad_wr = wr;
3636 goto out;
3637 }
3638
0e6e7416 3639 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3640 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3641
3642 ctrl->srcrb_flags =
3643 (wr->send_flags & IB_SEND_SIGNALED ?
3644 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3645 (wr->send_flags & IB_SEND_SOLICITED ?
3646 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3647 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3648 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3649 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3650 qp->sq_signal_bits;
3651
95d04f07 3652 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3653
3654 wqe += sizeof *ctrl;
3655 size = sizeof *ctrl / 16;
3656
1ffeb2eb
JM		 3657 switch (qp->mlx4_ib_qp_type) {
3658 case MLX4_IB_QPT_RC:
3659 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3660 switch (wr->opcode) {
3661 case IB_WR_ATOMIC_CMP_AND_SWP:
3662 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3663 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3664 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3665 atomic_wr(wr)->rkey);
225c7b1f
RD		 3666 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3667
e622f2f4 3668 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3669 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3670
225c7b1f
RD		 3671 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3672 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3673
3674 break;
3675
3676 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3677 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3678 atomic_wr(wr)->rkey);
6fa8f719
VS		 3679 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3680
e622f2f4 3681 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3682 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3683
3684 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3685 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3686
3687 break;
3688
3689 case IB_WR_RDMA_READ:
3690 case IB_WR_RDMA_WRITE:
3691 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3692 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3693 rdma_wr(wr)->rkey);
225c7b1f
RD		 3694 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3695 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3696 break;
95d04f07
RD		 3697
3698 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3699 ctrl->srcrb_flags |=
3700 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3701 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3702 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3703 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3704 break;
3705
1b2cd0fc
SG		 3706 case IB_WR_REG_MR:
3707 ctrl->srcrb_flags |=
3708 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3709 set_reg_seg(wqe, reg_wr(wr));
3710 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3711 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3712 break;
3713
225c7b1f
RD		 3714 default:
3715 /* No extra segments required for sends */
3716 break;
3717 }
3718 break;
3719
1ffeb2eb 3720 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3721 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3722 ctrl, &seglen);
1ffeb2eb
JM		 3723 if (unlikely(err)) {
3724 *bad_wr = wr;
3725 goto out;
3726 }
3727 wqe += seglen;
3728 size += seglen / 16;
3729 break;
3730 case MLX4_IB_QPT_TUN_SMI:
3731 case MLX4_IB_QPT_TUN_GSI:
3732 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3733 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3734 /* set the forced-loopback bit in the data seg av */
3735 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3736 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3737 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3738 break;
3739 case MLX4_IB_QPT_UD:
e622f2f4 3740 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3741 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3742 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3743
3744 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3745 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3746 &lso_hdr_sz, &blh);
b832be1e
EC		 3747 if (unlikely(err)) {
3748 *bad_wr = wr;
3749 goto out;
3750 }
0fd7e1d8 3751 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3752 wqe += seglen;
3753 size += seglen / 16;
3754 }
225c7b1f
RD		 3755 break;
3756
1ffeb2eb 3757 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3758 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3759 ctrl, &seglen);
1ffeb2eb
JM		 3760 if (unlikely(err)) {
3761 *bad_wr = wr;
3762 goto out;
3763 }
3764 wqe += seglen;
3765 size += seglen / 16;
3766 /* to start tunnel header on a cache-line boundary */
3767 add_zero_len_inline(wqe);
3768 wqe += 16;
3769 size++;
e622f2f4 3770 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3771 wqe += seglen;
3772 size += seglen / 16;
3773 break;
3774 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3775 case MLX4_IB_QPT_PROXY_GSI:
3776 /* If we are tunneling special qps, this is a UD qp.
3777 * In this case we first add a UD segment targeting
3778 * the tunnel qp, and then add a header with address
3779 * information */
e622f2f4
CH		 3780 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3781 ud_wr(wr),
97982f5a 3782 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3783 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3784 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3785 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3786 wqe += seglen;
3787 size += seglen / 16;
3788 break;
3789
3790 case MLX4_IB_QPT_SMI:
3791 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3792 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3793 &seglen);
f438000f 3794 if (unlikely(err)) {
225c7b1f
RD		 3795 *bad_wr = wr;
3796 goto out;
3797 }
f438000f
RD		 3798 wqe += seglen;
3799 size += seglen / 16;
225c7b1f
RD		 3800 break;
3801
3802 default:
3803 break;
3804 }
3805
6e694ea3
JM		 3806 /*
3807 * Write data segments in reverse order, so as to
3808 * overwrite cacheline stamp last within each
3809 * cacheline. This avoids issues with WQE
3810 * prefetching.
3811 */
225c7b1f 3812
6e694ea3
JM		 3813 dseg = wqe;
3814 dseg += wr->num_sge - 1;
3815 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3816
3817 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3818 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3819 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3820 qp->mlx4_ib_qp_type &
3821 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3822 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3823 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3824 }
3825
6e694ea3
JM		 3826 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3827 set_data_seg(dseg, wr->sg_list + i);
3828
0fd7e1d8
RD		 3829 /*
3830 * Possibly overwrite stamping in cacheline with LSO
3831 * segment only after making sure all data segments
3832 * are written.
3833 */
3834 wmb();
3835 *lso_wqe = lso_hdr_sz;
3836
224e92e0
BB		 3837 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3838 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3839
3840 /*
3841 * Make sure descriptor is fully written before
3842 * setting ownership bit (because HW can start
3843 * executing as soon as we do).
3844 */
3845 wmb();
3846
59b0ed12 3847 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3848 *bad_wr = wr;
225c7b1f
RD		 3849 err = -EINVAL;
3850 goto out;
3851 }
3852
3853 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3854 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3855
ea54b10c
JM		 3856 stamp = ind + qp->sq_spare_wqes;
3857 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3858
0e6e7416
RD		 3859 /*
3860 * We can improve latency by not stamping the last
3861 * send queue WQE until after ringing the doorbell, so
3862 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3863 *
3864 * Same optimization applies to padding with NOP wqe
3865 * in case of WQE shrinking (used to prevent wrap-around
3866 * in the middle of WR).
0e6e7416 3867 */
ea54b10c
JM		 3868 if (wr->next) {
3869 stamp_send_wqe(qp, stamp, size * 16);
3870 ind = pad_wraparound(qp, ind);
3871 }
225c7b1f
RD		 3872 }
3873
3874out:
3875 if (likely(nreq)) {
3876 qp->sq.head += nreq;
3877
3878 /*
3879 * Make sure that descriptors are written before
3880 * doorbell record.
3881 */
3882 wmb();
3883
97d82a48
SK		 3884 writel_relaxed(qp->doorbell_qpn,
3885 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
225c7b1f
RD		 3886
3887 /*
3888 * Make sure doorbells don't leak out of SQ spinlock
3889 * and reach the HCA out of order.
3890 */
3891 mmiowb();
0e6e7416 3892
ea54b10c
JM		 3893 stamp_send_wqe(qp, stamp, size * 16);
3894
3895 ind = pad_wraparound(qp, ind);
3896 qp->sq_next_wqe = ind;
225c7b1f
RD		 3897 }
3898
96db0e03 3899 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3900
3901 return err;
3902}
3903
d34ac5cd
BVA		 3904int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3905 const struct ib_send_wr **bad_wr)
1975acd9
YH		 3906{
3907 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3908}
3909
d34ac5cd
BVA		 3910static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3911 const struct ib_recv_wr **bad_wr, bool drain)
225c7b1f
RD		 3912{
3913 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3914 struct mlx4_wqe_data_seg *scat;
3915 unsigned long flags;
3916 int err = 0;
3917 int nreq;
3918 int ind;
1ffeb2eb 3919 int max_gs;
225c7b1f 3920 int i;
35f05dab 3921 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3922
1ffeb2eb 3923 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3924 spin_lock_irqsave(&qp->rq.lock, flags);
3925
1975acd9
YH		 3926 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3927 !drain) {
35f05dab
YH		 3928 err = -EIO;
3929 *bad_wr = wr;
3930 nreq = 0;
3931 goto out;
3932 }
3933
0e6e7416 3934 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3935
3936 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3937 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3938 err = -ENOMEM;
3939 *bad_wr = wr;
3940 goto out;
3941 }
3942
3943 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3944 err = -EINVAL;
3945 *bad_wr = wr;
3946 goto out;
3947 }
3948
3949 scat = get_recv_wqe(qp, ind);
3950
1ffeb2eb
JM		 3951 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3952 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3953 ib_dma_sync_single_for_device(ibqp->device,
3954 qp->sqp_proxy_rcv[ind].map,
3955 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3956 DMA_FROM_DEVICE);
3957 scat->byte_count =
3958 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3959 /* use dma lkey from upper layer entry */
3960 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3961 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3962 scat++;
3963 max_gs--;
3964 }
3965
2242fa4f
RD		 3966 for (i = 0; i < wr->num_sge; ++i)
3967 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3968
1ffeb2eb 3969 if (i < max_gs) {
225c7b1f
RD		 3970 scat[i].byte_count = 0;
3971 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3972 scat[i].addr = 0;
3973 }
3974
3975 qp->rq.wrid[ind] = wr->wr_id;
3976
0e6e7416 3977 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3978 }
3979
3980out:
3981 if (likely(nreq)) {
3982 qp->rq.head += nreq;
3983
3984 /*
3985 * Make sure that descriptors are written before
3986 * doorbell record.
3987 */
3988 wmb();
3989
3990 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3991 }
3992
3993 spin_unlock_irqrestore(&qp->rq.lock, flags);
3994
3995 return err;
3996}
6a775e2b 3997
d34ac5cd
BVA		 3998int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3999 const struct ib_recv_wr **bad_wr)
1975acd9
YH		 4000{
4001 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
4002}
4003
6a775e2b
JM		 4004static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
4005{
4006 switch (mlx4_state) {
4007 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
4008 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
4009 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
4010 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
4011 case MLX4_QP_STATE_SQ_DRAINING:
4012 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
4013 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
4014 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
4015 default: return -1;
4016 }
4017}
4018
4019static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
4020{
4021 switch (mlx4_mig_state) {
4022 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
4023 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
4024 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4025 default: return -1;
4026 }
4027}
4028
4029static int to_ib_qp_access_flags(int mlx4_flags)
4030{
4031 int ib_flags = 0;
4032
4033 if (mlx4_flags & MLX4_QP_BIT_RRE)
4034 ib_flags |= IB_ACCESS_REMOTE_READ;
4035 if (mlx4_flags & MLX4_QP_BIT_RWE)
4036 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4037 if (mlx4_flags & MLX4_QP_BIT_RAE)
4038 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4039
4040 return ib_flags;
4041}
4042
71d53ab4 4043static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 4044 struct rdma_ah_attr *ah_attr,
71d53ab4 4045 struct mlx4_qp_path *path)
6a775e2b 4046{
4c3eb3ca 4047 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 4048 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 4049
d8966fcd 4050 memset(ah_attr, 0, sizeof(*ah_attr));
d8966fcd 4051 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b 4052 return;
f1228867 4053 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
6a775e2b 4054
44c58487 4055 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 4056 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4057 ((path->sched_queue & 4) << 1));
4c3eb3ca 4058 else
d8966fcd 4059 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 4060 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 4061
d8966fcd
DC		 4062 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4063 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4064 rdma_ah_set_static_rate(ah_attr,
4065 path->static_rate ? path->static_rate - 5 : 0);
4066 if (path->grh_mylmc & (1 << 7)) {
4067 rdma_ah_set_grh(ah_attr, NULL,
4068 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4069 path->mgid_index,
4070 path->hop_limit,
4071 (be32_to_cpu(path->tclass_flowlabel)
4072 >> 20) & 0xff);
4073 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 4074 }
4075}
4076
4077int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4078 struct ib_qp_init_attr *qp_init_attr)
4079{
4080 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4081 struct mlx4_ib_qp *qp = to_mqp(ibqp);
4082 struct mlx4_qp_context context;
4083 int mlx4_state;
0df67030
DB		 4084 int err = 0;
4085
3078f5f1
GL		 4086 if (ibqp->rwq_ind_tbl)
4087 return -EOPNOTSUPP;
4088
0df67030 4089 mutex_lock(&qp->mutex);
6a775e2b
JM		 4090
4091 if (qp->state == IB_QPS_RESET) {
4092 qp_attr->qp_state = IB_QPS_RESET;
4093 goto done;
4094 }
4095
4096 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 4097 if (err) {
4098 err = -EINVAL;
4099 goto out;
4100 }
6a775e2b
JM		 4101
4102 mlx4_state = be32_to_cpu(context.flags) >> 28;
4103
0df67030
DB		 4104 qp->state = to_ib_qp_state(mlx4_state);
4105 qp_attr->qp_state = qp->state;
6a775e2b
JM		 4106 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4107 qp_attr->path_mig_state =
4108 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4109 qp_attr->qkey = be32_to_cpu(context.qkey);
4110 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4111 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4112 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4113 qp_attr->qp_access_flags =
4114 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4115
4116 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 4117 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4118 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4119 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4120 qp_attr->alt_port_num =
4121 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4122 }
4123
4124 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4125 if (qp_attr->qp_state == IB_QPS_INIT)
4126 qp_attr->port_num = qp->port;
4127 else
4128 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4129
4130 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4131 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4132
4133 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4134
4135 qp_attr->max_dest_rd_atomic =
4136 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4137 qp_attr->min_rnr_timer =
4138 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4139 qp_attr->timeout = context.pri_path.ackto >> 3;
4140 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4141 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4142 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4143
4144done:
4145 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4146 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4147 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4148
6a775e2b 4149 if (!ibqp->uobject) {
7f5eb9bb
RD		 4150 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4151 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4152 } else {
4153 qp_attr->cap.max_send_wr = 0;
4154 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4155 }
4156
7f5eb9bb
RD		 4157 /*
4158 * We don't support inline sends for kernel QPs (yet), and we
4159 * don't know what userspace's value should be.
4160 */
4161 qp_attr->cap.max_inline_data = 0;
4162
4163 qp_init_attr->cap = qp_attr->cap;
4164
521e575b
RL		 4165 qp_init_attr->create_flags = 0;
4166 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4167 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4168
4169 if (qp->flags & MLX4_IB_QP_LSO)
4170 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4171
c1c98501
MB		 4172 if (qp->flags & MLX4_IB_QP_NETIF)
4173 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4174
46db567d
DB		 4175 qp_init_attr->sq_sig_type =
4176 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4177 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4178
0df67030
DB		 4179out:
4180 mutex_unlock(&qp->mutex);
4181 return err;
6a775e2b
JM		 4182}
4183
400b1ebc
GL		 4184struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4185 struct ib_wq_init_attr *init_attr,
4186 struct ib_udata *udata)
4187{
4188 struct mlx4_ib_dev *dev;
4189 struct ib_qp_init_attr ib_qp_init_attr;
4190 struct mlx4_ib_qp *qp;
4191 struct mlx4_ib_create_wq ucmd;
4192 int err, required_cmd_sz;
4193
4194 if (!(udata && pd->uobject))
4195 return ERR_PTR(-EINVAL);
4196
078b3573
GL		 4197 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4198 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4199 if (udata->inlen < required_cmd_sz) {
4200 pr_debug("invalid inlen\n");
4201 return ERR_PTR(-EINVAL);
4202 }
4203
4204 if (udata->inlen > sizeof(ucmd) &&
4205 !ib_is_udata_cleared(udata, sizeof(ucmd),
4206 udata->inlen - sizeof(ucmd))) {
4207 pr_debug("inlen is not supported\n");
4208 return ERR_PTR(-EOPNOTSUPP);
4209 }
4210
4211 if (udata->outlen)
4212 return ERR_PTR(-EOPNOTSUPP);
4213
4214 dev = to_mdev(pd->device);
4215
4216 if (init_attr->wq_type != IB_WQT_RQ) {
4217 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4218 return ERR_PTR(-EOPNOTSUPP);
4219 }
4220
6d06c9aa 4221 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) {
400b1ebc
GL		 4222 pr_debug("unsupported create_flags %u\n",
4223 init_attr->create_flags);
4224 return ERR_PTR(-EOPNOTSUPP);
4225 }
4226
4227 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4228 if (!qp)
4229 return ERR_PTR(-ENOMEM);
4230
4231 qp->pri.vid = 0xFFFF;
4232 qp->alt.vid = 0xFFFF;
4233
4234 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4235 ib_qp_init_attr.qp_context = init_attr->wq_context;
4236 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4237 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4238 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4239 ib_qp_init_attr.recv_cq = init_attr->cq;
4240 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4241
6d06c9aa
GL		 4242 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4243 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4244
400b1ebc
GL		 4245 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4246 udata, 0, &qp);
4247 if (err) {
4248 kfree(qp);
4249 return ERR_PTR(err);
4250 }
4251
4252 qp->ibwq.event_handler = init_attr->event_handler;
4253 qp->ibwq.wq_num = qp->mqp.qpn;
4254 qp->ibwq.state = IB_WQS_RESET;
4255
4256 return &qp->ibwq;
4257}
4258
4259static int ib_wq2qp_state(enum ib_wq_state state)
4260{
4261 switch (state) {
4262 case IB_WQS_RESET:
4263 return IB_QPS_RESET;
4264 case IB_WQS_RDY:
4265 return IB_QPS_RTR;
4266 default:
4267 return IB_QPS_ERR;
4268 }
4269}
4270
4271static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4272{
4273 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4274 enum ib_qp_state qp_cur_state;
4275 enum ib_qp_state qp_new_state;
4276 int attr_mask;
4277 int err;
4278
4279 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4280 * the WQ logic state.
4281 */
4282 qp_cur_state = qp->state;
4283 qp_new_state = ib_wq2qp_state(new_state);
4284
4285 if (ib_wq2qp_state(new_state) == qp_cur_state)
4286 return 0;
4287
4288 if (new_state == IB_WQS_RDY) {
4289 struct ib_qp_attr attr = {};
4290
4291 attr.port_num = qp->port;
4292 attr_mask = IB_QP_PORT;
4293
4294 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4295 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4296 if (err) {
4297 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4298 ibwq->wq_num);
4299 return err;
4300 }
4301
4302 qp_cur_state = IB_QPS_INIT;
4303 }
4304
4305 attr_mask = 0;
4306 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4307 qp_cur_state, qp_new_state);
4308
4309 if (err && (qp_cur_state == IB_QPS_INIT)) {
4310 qp_new_state = IB_QPS_RESET;
4311 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4312 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4313 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4314 ibwq->wq_num);
4315 qp_new_state = IB_QPS_INIT;
4316 }
4317 }
4318
4319 qp->state = qp_new_state;
4320
4321 return err;
4322}
4323
4324int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4325 u32 wq_attr_mask, struct ib_udata *udata)
4326{
4327 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4328 struct mlx4_ib_modify_wq ucmd = {};
4329 size_t required_cmd_sz;
4330 enum ib_wq_state cur_state, new_state;
4331 int err = 0;
4332
4333 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4334 sizeof(ucmd.reserved);
4335 if (udata->inlen < required_cmd_sz)
4336 return -EINVAL;
4337
4338 if (udata->inlen > sizeof(ucmd) &&
4339 !ib_is_udata_cleared(udata, sizeof(ucmd),
4340 udata->inlen - sizeof(ucmd)))
4341 return -EOPNOTSUPP;
4342
4343 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4344 return -EFAULT;
4345
4346 if (ucmd.comp_mask || ucmd.reserved)
4347 return -EOPNOTSUPP;
4348
4349 if (wq_attr_mask & IB_WQ_FLAGS)
4350 return -EOPNOTSUPP;
4351
4352 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4353 ibwq->state;
4354 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4355
4356 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4357 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4358 return -EINVAL;
4359
4360 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4361 return -EINVAL;
4362
4363 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4364 return -EINVAL;
4365
3078f5f1
GL		 4366 /* Need to protect against the parent RSS which also may modify WQ
4367 * state.
4368 */
4369 mutex_lock(&qp->mutex);
4370
400b1ebc
GL		 4371 /* Can update HW state only if a RSS QP has already associated to this
4372 * WQ, so we can apply its port on the WQ.
4373 */
4374 if (qp->rss_usecnt)
4375 err = _mlx4_ib_modify_wq(ibwq, new_state);
4376
4377 if (!err)
4378 ibwq->state = new_state;
4379
3078f5f1
GL		 4380 mutex_unlock(&qp->mutex);
4381
400b1ebc
GL		 4382 return err;
4383}
4384
4385int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4386{
4387 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4388 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4389
4390 if (qp->counter_index)
4391 mlx4_ib_free_qp_counter(dev, qp);
4392
4393 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4394
4395 kfree(qp);
4396
4397 return 0;
4398}
b8d46ca0
GL		 4399
4400struct ib_rwq_ind_table
4401*mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4402 struct ib_rwq_ind_table_init_attr *init_attr,
4403 struct ib_udata *udata)
4404{
4405 struct ib_rwq_ind_table *rwq_ind_table;
4406 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4407 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4408 unsigned int base_wqn;
4409 size_t min_resp_len;
4410 int i;
4411 int err;
4412
4413 if (udata->inlen > 0 &&
4414 !ib_is_udata_cleared(udata, 0,
4415 udata->inlen))
4416 return ERR_PTR(-EOPNOTSUPP);
4417
4418 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4419 if (udata->outlen && udata->outlen < min_resp_len)
4420 return ERR_PTR(-EINVAL);
4421
4422 if (ind_tbl_size >
4423 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4424 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4425 ind_tbl_size,
4426 device->attrs.rss_caps.max_rwq_indirection_table_size);
4427 return ERR_PTR(-EINVAL);
4428 }
4429
4430 base_wqn = init_attr->ind_tbl[0]->wq_num;
4431
4432 if (base_wqn % ind_tbl_size) {
4433 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4434 base_wqn);
4435 return ERR_PTR(-EINVAL);
4436 }
4437
4438 for (i = 1; i < ind_tbl_size; i++) {
4439 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4440 pr_debug("indirection table's WQNs aren't consecutive\n");
4441 return ERR_PTR(-EINVAL);
4442 }
4443 }
4444
4445 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4446 if (!rwq_ind_table)
4447 return ERR_PTR(-ENOMEM);
4448
4449 if (udata->outlen) {
4450 resp.response_length = offsetof(typeof(resp), response_length) +
4451 sizeof(resp.response_length);
4452 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4453 if (err)
4454 goto err;
4455 }
4456
4457 return rwq_ind_table;
4458
4459err:
4460 kfree(rwq_ind_table);
4461 return ERR_PTR(err);
4462}
4463
4464int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4465{
4466 kfree(ib_rwq_ind_tbl);
4467 return 0;
4468}
1975acd9
YH		 4469
4470struct mlx4_ib_drain_cqe {
4471 struct ib_cqe cqe;
4472 struct completion done;
4473};
4474
4475static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4476{
4477 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4478 struct mlx4_ib_drain_cqe,
4479 cqe);
4480
4481 complete(&cqe->done);
4482}
4483
4484/* This function returns only once the drained WR was completed */
4485static void handle_drain_completion(struct ib_cq *cq,
4486 struct mlx4_ib_drain_cqe *sdrain,
4487 struct mlx4_ib_dev *dev)
4488{
4489 struct mlx4_dev *mdev = dev->dev;
4490
4491 if (cq->poll_ctx == IB_POLL_DIRECT) {
4492 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4493 ib_process_cq_direct(cq, -1);
4494 return;
4495 }
4496
4497 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4498 struct mlx4_ib_cq *mcq = to_mcq(cq);
4499 bool triggered = false;
4500 unsigned long flags;
4501
4502 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4503 /* Make sure that the CQ handler won't run if wasn't run yet */
4504 if (!mcq->mcq.reset_notify_added)
4505 mcq->mcq.reset_notify_added = 1;
4506 else
4507 triggered = true;
4508 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4509
4510 if (triggered) {
4511 /* Wait for any scheduled/running task to be ended */
4512 switch (cq->poll_ctx) {
4513 case IB_POLL_SOFTIRQ:
4514 irq_poll_disable(&cq->iop);
4515 irq_poll_enable(&cq->iop);
4516 break;
4517 case IB_POLL_WORKQUEUE:
4518 cancel_work_sync(&cq->work);
4519 break;
4520 default:
4521 WARN_ON_ONCE(1);
4522 }
4523 }
4524
4525 /* Run the CQ handler - this makes sure that the drain WR will
4526 * be processed if wasn't processed yet.
4527 */
4528 mcq->mcq.comp(&mcq->mcq);
4529 }
4530
4531 wait_for_completion(&sdrain->done);
4532}
4533
4534void mlx4_ib_drain_sq(struct ib_qp *qp)
4535{
4536 struct ib_cq *cq = qp->send_cq;
4537 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4538 struct mlx4_ib_drain_cqe sdrain;
d34ac5cd 4539 const struct ib_send_wr *bad_swr;
1975acd9
YH		 4540 struct ib_rdma_wr swr = {
4541 .wr = {
4542 .next = NULL,
4543 { .wr_cqe = &sdrain.cqe, },
4544 .opcode = IB_WR_RDMA_WRITE,
4545 },
4546 };
4547 int ret;
4548 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4549 struct mlx4_dev *mdev = dev->dev;
4550
4551 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4552 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4553 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4554 return;
4555 }
4556
4557 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4558 init_completion(&sdrain.done);
4559
4560 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4561 if (ret) {
4562 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4563 return;
4564 }
4565
4566 handle_drain_completion(cq, &sdrain, dev);
4567}
4568
4569void mlx4_ib_drain_rq(struct ib_qp *qp)
4570{
4571 struct ib_cq *cq = qp->recv_cq;
4572 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4573 struct mlx4_ib_drain_cqe rdrain;
d34ac5cd
BVA		 4574 struct ib_recv_wr rwr = {};
4575 const struct ib_recv_wr *bad_rwr;
1975acd9
YH		 4576 int ret;
4577 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4578 struct mlx4_dev *mdev = dev->dev;
4579
4580 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4581 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4582 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4583 return;
4584 }
4585
4586 rwr.wr_cqe = &rdrain.cqe;
4587 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4588 init_completion(&rdrain.done);
4589
4590 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4591 if (ret) {
4592 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4593 return;
4594 }
4595
4596 handle_drain_completion(cq, &rdrain, dev);
4597}
Linux 6.x block layer and io_uring tree(s)