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IB/mlx4: Remove redundant attribute in mlx4_ib_create_qp_rss struct
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
225c7b1f 44
2f48485d 45#include <linux/mlx4/driver.h>
225c7b1f
RD		 46#include <linux/mlx4/qp.h>
47
48#include "mlx4_ib.h"
9ce28a20 49#include <rdma/mlx4-abi.h>
225c7b1f 50
35f05dab
YH		 51static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
3078f5f1 55static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
35f05dab 56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
79struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 86 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 117};
118
400b1ebc
GL		 119enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122};
123
225c7b1f
RD		 124static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125{
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127}
128
1ffeb2eb
JM		 129static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130{
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
47605df9
JM		 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 137}
138
225c7b1f
RD		 139static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140{
47605df9
JM		 141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
153 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
154 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
e1b866c6
MS		 160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 164}
165
1ffeb2eb 166/* used for INIT/CLOSE port logic */
225c7b1f
RD		 167static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168{
47605df9
JM		 169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
181 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
225c7b1f
RD		 188}
189
190static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191{
1c69fc2a 192 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 193}
194
195static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198}
199
200static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201{
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203}
204
0e6e7416
RD		 205/*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 207 * first four bytes of every 64 byte chunk with
208 * 0x7FFFFFF | (invalid_ownership_value << 31).
209 *
210 * When the max work request size is less than or equal to the WQE
211 * basic block size, as an optimization, we can stamp all WQEs with
212 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 213 */
ea54b10c 214static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 215{
d2ae16d5 216 __be32 *wqe;
0e6e7416 217 int i;
ea54b10c
JM		 218 int s;
219 int ind;
220 void *buf;
221 __be32 stamp;
9670e553 222 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 223
ea54b10c 224 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 225 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 226 for (i = 0; i < s; i += 64) {
227 ind = (i >> qp->sq.wqe_shift) + n;
228 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
229 cpu_to_be32(0xffffffff);
230 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
231 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
232 *wqe = stamp;
233 }
234 } else {
9670e553 235 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
224e92e0 236 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
ea54b10c
JM		 237 for (i = 64; i < s; i += 64) {
238 wqe = buf + i;
d2ae16d5 239 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 240 }
241 }
242}
243
244static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
245{
246 struct mlx4_wqe_ctrl_seg *ctrl;
247 struct mlx4_wqe_inline_seg *inl;
248 void *wqe;
249 int s;
250
251 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
252 s = sizeof(struct mlx4_wqe_ctrl_seg);
253
254 if (qp->ibqp.qp_type == IB_QPT_UD) {
255 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
256 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
257 memset(dgram, 0, sizeof *dgram);
258 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
259 s += sizeof(struct mlx4_wqe_datagram_seg);
260 }
261
262 /* Pad the remainder of the WQE with an inline data segment. */
263 if (size > s) {
264 inl = wqe + s;
265 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
266 }
267 ctrl->srcrb_flags = 0;
224e92e0 268 ctrl->qpn_vlan.fence_size = size / 16;
ea54b10c
JM		 269 /*
270 * Make sure descriptor is fully written before setting ownership bit
271 * (because HW can start executing as soon as we do).
272 */
273 wmb();
274
275 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
276 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 277
ea54b10c
JM		 278 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
279}
280
281/* Post NOP WQE to prevent wrap-around in the middle of WR */
282static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
283{
284 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
285 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
286 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
287 ind += s;
288 }
289 return ind;
0e6e7416
RD		 290}
291
225c7b1f
RD		 292static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
293{
294 struct ib_event event;
295 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
296
297 if (type == MLX4_EVENT_TYPE_PATH_MIG)
298 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
299
300 if (ibqp->event_handler) {
301 event.device = ibqp->device;
302 event.element.qp = ibqp;
303 switch (type) {
304 case MLX4_EVENT_TYPE_PATH_MIG:
305 event.event = IB_EVENT_PATH_MIG;
306 break;
307 case MLX4_EVENT_TYPE_COMM_EST:
308 event.event = IB_EVENT_COMM_EST;
309 break;
310 case MLX4_EVENT_TYPE_SQ_DRAINED:
311 event.event = IB_EVENT_SQ_DRAINED;
312 break;
313 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
314 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
315 break;
316 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
317 event.event = IB_EVENT_QP_FATAL;
318 break;
319 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
320 event.event = IB_EVENT_PATH_MIG_ERR;
321 break;
322 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
323 event.event = IB_EVENT_QP_REQ_ERR;
324 break;
325 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
326 event.event = IB_EVENT_QP_ACCESS_ERR;
327 break;
328 default:
987c8f8f 329 pr_warn("Unexpected event type %d "
225c7b1f
RD		 330 "on QP %06x\n", type, qp->qpn);
331 return;
332 }
333
334 ibqp->event_handler(&event, ibqp->qp_context);
335 }
336}
337
400b1ebc
GL		 338static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
339{
340 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
341 type, qp->qpn);
342}
343
1ffeb2eb 344static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 345{
346 /*
347 * UD WQEs must have a datagram segment.
348 * RC and UC WQEs might have a remote address segment.
349 * MLX WQEs need two extra inline data segments (for the UD
350 * header and space for the ICRC).
351 */
352 switch (type) {
1ffeb2eb 353 case MLX4_IB_QPT_UD:
225c7b1f 354 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 355 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 356 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 357 case MLX4_IB_QPT_PROXY_SMI_OWNER:
358 case MLX4_IB_QPT_PROXY_SMI:
359 case MLX4_IB_QPT_PROXY_GSI:
360 return sizeof (struct mlx4_wqe_ctrl_seg) +
361 sizeof (struct mlx4_wqe_datagram_seg) + 64;
362 case MLX4_IB_QPT_TUN_SMI_OWNER:
363 case MLX4_IB_QPT_TUN_GSI:
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_datagram_seg);
366
367 case MLX4_IB_QPT_UC:
225c7b1f
RD		 368 return sizeof (struct mlx4_wqe_ctrl_seg) +
369 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 370 case MLX4_IB_QPT_RC:
225c7b1f 371 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 372 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 373 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 374 case MLX4_IB_QPT_SMI:
375 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 376 return sizeof (struct mlx4_wqe_ctrl_seg) +
377 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 378 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
379 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 380 sizeof (struct mlx4_wqe_inline_seg),
381 sizeof (struct mlx4_wqe_data_seg)) +
382 ALIGN(4 +
383 sizeof (struct mlx4_wqe_inline_seg),
384 sizeof (struct mlx4_wqe_data_seg));
385 default:
386 return sizeof (struct mlx4_wqe_ctrl_seg);
387 }
388}
389
2446304d 390static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
ea30b966
MG		 391 int is_user, int has_rq, struct mlx4_ib_qp *qp,
392 u32 inl_recv_sz)
225c7b1f 393{
2446304d 394 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 395 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
396 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 397 return -EINVAL;
398
0a1405da 399 if (!has_rq) {
ea30b966 400 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 401 return -EINVAL;
2446304d 402
0e6e7416 403 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 404 } else {
ea30b966
MG		 405 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
406 sizeof(struct mlx4_wqe_data_seg);
407 u32 wqe_size;
408
a4cd7ed8 409 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 410 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
411 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 412 return -EINVAL;
413
0e6e7416 414 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 415 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 416 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
417 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 418 }
2446304d 419
fc2d0044
SG		 420 /* leave userspace return values as they were, so as not to break ABI */
421 if (is_user) {
422 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
423 cap->max_recv_sge = qp->rq.max_gs;
424 } else {
425 cap->max_recv_wr = qp->rq.max_post =
426 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
427 cap->max_recv_sge = min(qp->rq.max_gs,
428 min(dev->dev->caps.max_sq_sg,
429 dev->dev->caps.max_rq_sg));
430 }
2446304d
EC		 431
432 return 0;
433}
434
435static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
73898db0
HA		 436 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
437 bool shrink_wqe)
2446304d 438{
ea54b10c
JM		 439 int s;
440
2446304d 441 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 442 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
443 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 444 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 445 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
446 return -EINVAL;
447
448 /*
449 * For MLX transport we need 2 extra S/G entries:
450 * one for the header and one for the checksum at the end
451 */
1ffeb2eb
JM		 452 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
453 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 454 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
455 return -EINVAL;
456
ea54b10c
JM		 457 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
458 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 459 send_wqe_overhead(type, qp->flags);
225c7b1f 460
cd155c1c
RD		 461 if (s > dev->dev->caps.max_sq_desc_sz)
462 return -EINVAL;
463
0e6e7416 464 /*
ea54b10c
JM		 465 * Hermon supports shrinking WQEs, such that a single work
466 * request can include multiple units of 1 << wqe_shift. This
467 * way, work requests can differ in size, and do not have to
468 * be a power of 2 in size, saving memory and speeding up send
469 * WR posting. Unfortunately, if we do this then the
470 * wqe_index field in CQEs can't be used to look up the WR ID
471 * anymore, so we do this only if selective signaling is off.
472 *
473 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 474 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 475 * constant-sized WRs to make sure a WR is always fully within
476 * a single page-sized chunk.
477 *
478 * Finally, we use NOP work requests to pad the end of the
479 * work queue, to avoid wrap-around in the middle of WR. We
480 * set NEC bit to avoid getting completions with error for
481 * these NOP WRs, but since NEC is only supported starting
482 * with firmware 2.2.232, we use constant-sized WRs for older
483 * firmware.
484 *
485 * And, since MLX QPs only support SEND, we use constant-sized
486 * WRs in this case.
487 *
488 * We look for the smallest value of wqe_shift such that the
489 * resulting number of wqes does not exceed device
490 * capabilities.
491 *
492 * We set WQE size to at least 64 bytes, this way stamping
493 * invalidates each WQE.
0e6e7416 494 */
73898db0 495 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
ea54b10c 496 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 497 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
498 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
499 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 500 qp->sq.wqe_shift = ilog2(64);
501 else
502 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
503
504 for (;;) {
ea54b10c
JM		 505 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
506
507 /*
508 * We need to leave 2 KB + 1 WR of headroom in the SQ to
509 * allow HW to prefetch.
510 */
511 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
512 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
513 qp->sq_max_wqes_per_wr +
514 qp->sq_spare_wqes);
515
516 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
517 break;
518
519 if (qp->sq_max_wqes_per_wr <= 1)
520 return -EINVAL;
521
522 ++qp->sq.wqe_shift;
523 }
524
cd155c1c
RD		 525 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
526 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 527 send_wqe_overhead(type, qp->flags)) /
528 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 529
530 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
531 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 532 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
533 qp->rq.offset = 0;
0e6e7416 534 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 535 } else {
0e6e7416 536 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 537 qp->sq.offset = 0;
538 }
539
ea54b10c
JM		 540 cap->max_send_wr = qp->sq.max_post =
541 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 542 cap->max_send_sge = min(qp->sq.max_gs,
543 min(dev->dev->caps.max_sq_sg,
544 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 545 /* We don't support inline sends for kernel QPs (yet) */
546 cap->max_inline_data = 0;
225c7b1f
RD		 547
548 return 0;
549}
550
83904132
JM		 551static int set_user_sq_size(struct mlx4_ib_dev *dev,
552 struct mlx4_ib_qp *qp,
2446304d
EC		 553 struct mlx4_ib_create_qp *ucmd)
554{
83904132
JM		 555 /* Sanity check SQ size before proceeding */
556 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
557 ucmd->log_sq_stride >
558 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
559 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
560 return -EINVAL;
561
0e6e7416 562 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 563 qp->sq.wqe_shift = ucmd->log_sq_stride;
564
0e6e7416
RD		 565 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
566 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 567
568 return 0;
569}
570
1ffeb2eb
JM		 571static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
572{
573 int i;
574
575 qp->sqp_proxy_rcv =
576 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
577 GFP_KERNEL);
578 if (!qp->sqp_proxy_rcv)
579 return -ENOMEM;
580 for (i = 0; i < qp->rq.wqe_cnt; i++) {
581 qp->sqp_proxy_rcv[i].addr =
582 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
583 GFP_KERNEL);
584 if (!qp->sqp_proxy_rcv[i].addr)
585 goto err;
586 qp->sqp_proxy_rcv[i].map =
587 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
588 sizeof (struct mlx4_ib_proxy_sqp_hdr),
589 DMA_FROM_DEVICE);
cc47d369
SO		 590 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
591 kfree(qp->sqp_proxy_rcv[i].addr);
592 goto err;
593 }
1ffeb2eb
JM		 594 }
595 return 0;
596
597err:
598 while (i > 0) {
599 --i;
600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
601 sizeof (struct mlx4_ib_proxy_sqp_hdr),
602 DMA_FROM_DEVICE);
603 kfree(qp->sqp_proxy_rcv[i].addr);
604 }
605 kfree(qp->sqp_proxy_rcv);
606 qp->sqp_proxy_rcv = NULL;
607 return -ENOMEM;
608}
609
610static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
611{
612 int i;
613
614 for (i = 0; i < qp->rq.wqe_cnt; i++) {
615 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
616 sizeof (struct mlx4_ib_proxy_sqp_hdr),
617 DMA_FROM_DEVICE);
618 kfree(qp->sqp_proxy_rcv[i].addr);
619 }
620 kfree(qp->sqp_proxy_rcv);
621}
622
0a1405da
SH		 623static int qp_has_rq(struct ib_qp_init_attr *attr)
624{
625 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
626 return 0;
627
628 return !attr->srq;
629}
630
99ec41d0
JM		 631static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
632{
633 int i;
634 for (i = 0; i < dev->caps.num_ports; i++) {
635 if (qpn == dev->caps.qp0_proxy[i])
636 return !!dev->caps.qp0_qkey[i];
637 }
638 return 0;
639}
640
7b59f0f9
EBE		 641static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
642 struct mlx4_ib_qp *qp)
643{
644 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
645 mlx4_counter_free(dev->dev, qp->counter_index->index);
646 list_del(&qp->counter_index->list);
647 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
648
649 kfree(qp->counter_index);
650 qp->counter_index = NULL;
651}
652
3078f5f1
GL		 653static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
654 struct ib_qp_init_attr *init_attr,
655 struct mlx4_ib_create_qp_rss *ucmd)
656{
657 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
658 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
659
660 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
661 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
662 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
663 MLX4_EN_RSS_KEY_SIZE);
664 } else {
665 pr_debug("RX Hash function is not supported\n");
666 return (-EOPNOTSUPP);
667 }
668
669 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
670 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
671 rss_ctx->flags = MLX4_RSS_IPV4;
672 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
673 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
674 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
675 return (-EOPNOTSUPP);
676 }
677
678 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
679 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
680 rss_ctx->flags |= MLX4_RSS_IPV6;
681 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
682 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
683 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
684 return (-EOPNOTSUPP);
685 }
686
687 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
688 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
689 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
690 pr_debug("RX Hash fields_mask for UDP is not supported\n");
691 return (-EOPNOTSUPP);
692 }
693
694 if (rss_ctx->flags & MLX4_RSS_IPV4) {
695 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
696 } else if (rss_ctx->flags & MLX4_RSS_IPV6) {
697 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
698 } else {
699 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
700 return (-EOPNOTSUPP);
701 }
702 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
703 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
704 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
705 return (-EOPNOTSUPP);
706 }
707
708 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
709 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
710 if (rss_ctx->flags & MLX4_RSS_IPV4) {
711 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
712 } else if (rss_ctx->flags & MLX4_RSS_IPV6) {
713 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
714 } else {
715 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
716 return (-EOPNOTSUPP);
717 }
718
719 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
720 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
721 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
722 return (-EOPNOTSUPP);
723 }
724
725 return 0;
726}
727
728static int create_qp_rss(struct mlx4_ib_dev *dev, struct ib_pd *ibpd,
729 struct ib_qp_init_attr *init_attr,
730 struct mlx4_ib_create_qp_rss *ucmd,
731 struct mlx4_ib_qp *qp)
732{
733 int qpn;
734 int err;
735
736 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
737
738 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
739 if (err)
740 return err;
741
742 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
743 if (err)
744 goto err_qpn;
745
746 mutex_init(&qp->mutex);
747
748 INIT_LIST_HEAD(&qp->gid_list);
749 INIT_LIST_HEAD(&qp->steering_rules);
750
c3f1ee29 751 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 752 qp->state = IB_QPS_RESET;
753
754 /* Set dummy send resources to be compatible with HV and PRM */
755 qp->sq_no_prefetch = 1;
756 qp->sq.wqe_cnt = 1;
757 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
758 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
759 qp->mtt = (to_mqp(
760 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
761
762 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
763 if (!qp->rss_ctx) {
764 err = -ENOMEM;
765 goto err_qp_alloc;
766 }
767
768 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
769 if (err)
770 goto err;
771
772 return 0;
773
774err:
775 kfree(qp->rss_ctx);
776
777err_qp_alloc:
778 mlx4_qp_remove(dev->dev, &qp->mqp);
779 mlx4_qp_free(dev->dev, &qp->mqp);
780
781err_qpn:
782 mlx4_qp_release_range(dev->dev, qpn, 1);
783 return err;
784}
785
786static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
787 struct ib_qp_init_attr *init_attr,
788 struct ib_udata *udata)
789{
790 struct mlx4_ib_qp *qp;
791 struct mlx4_ib_create_qp_rss ucmd = {};
792 size_t required_cmd_sz;
793 int err;
794
795 if (!udata) {
796 pr_debug("RSS QP with NULL udata\n");
797 return ERR_PTR(-EINVAL);
798 }
799
800 if (udata->outlen)
801 return ERR_PTR(-EOPNOTSUPP);
802
803 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
804 sizeof(ucmd.reserved1);
805 if (udata->inlen < required_cmd_sz) {
806 pr_debug("invalid inlen\n");
807 return ERR_PTR(-EINVAL);
808 }
809
810 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
811 pr_debug("copy failed\n");
812 return ERR_PTR(-EFAULT);
813 }
814
815 if (ucmd.comp_mask || ucmd.reserved1)
816 return ERR_PTR(-EOPNOTSUPP);
817
818 if (udata->inlen > sizeof(ucmd) &&
819 !ib_is_udata_cleared(udata, sizeof(ucmd),
820 udata->inlen - sizeof(ucmd))) {
821 pr_debug("inlen is not supported\n");
822 return ERR_PTR(-EOPNOTSUPP);
823 }
824
825 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
826 pr_debug("RSS QP with unsupported QP type %d\n",
827 init_attr->qp_type);
828 return ERR_PTR(-EOPNOTSUPP);
829 }
830
831 if (init_attr->create_flags) {
832 pr_debug("RSS QP doesn't support create flags\n");
833 return ERR_PTR(-EOPNOTSUPP);
834 }
835
836 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
837 pr_debug("RSS QP with unsupported send attributes\n");
838 return ERR_PTR(-EOPNOTSUPP);
839 }
840
841 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
842 if (!qp)
843 return ERR_PTR(-ENOMEM);
844
845 qp->pri.vid = 0xFFFF;
846 qp->alt.vid = 0xFFFF;
847
848 err = create_qp_rss(to_mdev(pd->device), pd, init_attr, &ucmd, qp);
849 if (err) {
850 kfree(qp);
851 return ERR_PTR(err);
852 }
853
854 qp->ibqp.qp_num = qp->mqp.qpn;
855
856 return &qp->ibqp;
857}
858
400b1ebc
GL		 859/*
860 * This function allocates a WQN from a range which is consecutive and aligned
861 * to its size. In case the range is full, then it creates a new range and
862 * allocates WQN from it. The new range will be used for following allocations.
863 */
864static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
865 struct mlx4_ib_qp *qp, int range_size, int *wqn)
866{
867 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
868 struct mlx4_wqn_range *range;
869 int err = 0;
870
871 mutex_lock(&context->wqn_ranges_mutex);
872
873 range = list_first_entry_or_null(&context->wqn_ranges_list,
874 struct mlx4_wqn_range, list);
875
876 if (!range || (range->refcount == range->size) || range->dirty) {
877 range = kzalloc(sizeof(*range), GFP_KERNEL);
878 if (!range) {
879 err = -ENOMEM;
880 goto out;
881 }
882
883 err = mlx4_qp_reserve_range(dev->dev, range_size,
884 range_size, &range->base_wqn, 0,
885 qp->mqp.usage);
886 if (err) {
887 kfree(range);
888 goto out;
889 }
890
891 range->size = range_size;
892 list_add(&range->list, &context->wqn_ranges_list);
893 } else if (range_size != 1) {
894 /*
895 * Requesting a new range (>1) when last range is still open, is
896 * not valid.
897 */
898 err = -EINVAL;
899 goto out;
900 }
901
902 qp->wqn_range = range;
903
904 *wqn = range->base_wqn + range->refcount;
905
906 range->refcount++;
907
908out:
909 mutex_unlock(&context->wqn_ranges_mutex);
910
911 return err;
912}
913
914static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
915 struct mlx4_ib_qp *qp, bool dirty_release)
916{
917 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
918 struct mlx4_wqn_range *range;
919
920 mutex_lock(&context->wqn_ranges_mutex);
921
922 range = qp->wqn_range;
923
924 range->refcount--;
925 if (!range->refcount) {
926 mlx4_qp_release_range(dev->dev, range->base_wqn,
927 range->size);
928 list_del(&range->list);
929 kfree(range);
930 } else if (dirty_release) {
931 /*
932 * A range which one of its WQNs is destroyed, won't be able to be
933 * reused for further WQN allocations.
934 * The next created WQ will allocate a new range.
935 */
936 range->dirty = 1;
937 }
938
939 mutex_unlock(&context->wqn_ranges_mutex);
940}
941
225c7b1f 942static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
400b1ebc 943 enum mlx4_ib_source_type src,
225c7b1f 944 struct ib_qp_init_attr *init_attr,
8900b894
LR		 945 struct ib_udata *udata, int sqpn,
946 struct mlx4_ib_qp **caller_qp)
225c7b1f 947{
a3cdcbfa 948 int qpn;
225c7b1f 949 int err;
73898db0 950 struct ib_qp_cap backup_cap;
b42dde47 951 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 952 struct mlx4_ib_qp *qp;
953 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 954 struct mlx4_ib_cq *mcq;
955 unsigned long flags;
400b1ebc 956 int range_size = 0;
1ffeb2eb
JM		 957
958 /* When tunneling special qps, we use a plain UD qp */
959 if (sqpn) {
960 if (mlx4_is_mfunc(dev->dev) &&
961 (!mlx4_is_master(dev->dev) ||
962 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
963 if (init_attr->qp_type == IB_QPT_GSI)
964 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 965 else {
966 if (mlx4_is_master(dev->dev) ||
967 qp0_enabled_vf(dev->dev, sqpn))
968 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
969 else
970 qp_type = MLX4_IB_QPT_PROXY_SMI;
971 }
1ffeb2eb
JM		 972 }
973 qpn = sqpn;
974 /* add extra sg entry for tunneling */
975 init_attr->cap.max_recv_sge++;
976 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
977 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
978 container_of(init_attr,
979 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
980 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
981 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
982 !mlx4_is_master(dev->dev))
983 return -EINVAL;
984 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
985 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 986 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
987 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
988 tnl_init->port))
1ffeb2eb
JM		 989 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
990 else
991 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 992 /* we are definitely in the PPF here, since we are creating
993 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
994 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
995 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 996 sqpn = qpn;
997 }
998
999 if (!*caller_qp) {
1000 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1001 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1002 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 1003 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 1004 if (!sqp)
1005 return -ENOMEM;
1006 qp = &sqp->qp;
2f5bb473
JM		 1007 qp->pri.vid = 0xFFFF;
1008 qp->alt.vid = 0xFFFF;
1ffeb2eb 1009 } else {
8900b894 1010 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 1011 if (!qp)
1012 return -ENOMEM;
2f5bb473
JM		 1013 qp->pri.vid = 0xFFFF;
1014 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1015 }
1016 } else
1017 qp = *caller_qp;
1018
1019 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 1020
1021 mutex_init(&qp->mutex);
1022 spin_lock_init(&qp->sq.lock);
1023 spin_lock_init(&qp->rq.lock);
fa417f7b 1024 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1025 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 1026
1027 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1028 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1029 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1030
225c7b1f
RD		 1031
1032 if (pd->uobject) {
400b1ebc
GL		 1033 union {
1034 struct mlx4_ib_create_qp qp;
1035 struct mlx4_ib_create_wq wq;
1036 } ucmd;
1037 size_t copy_len;
1038
1039 copy_len = (src == MLX4_IB_QP_SRC) ?
1040 sizeof(struct mlx4_ib_create_qp) :
1041 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
225c7b1f 1042
400b1ebc 1043 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1044 err = -EFAULT;
1045 goto err;
1046 }
1047
400b1ebc 1048 if (src == MLX4_IB_RWQ_SRC) {
078b3573
GL		 1049 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
1050 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
400b1ebc
GL		 1051 pr_debug("user command isn't supported\n");
1052 err = -EOPNOTSUPP;
1053 goto err;
1054 }
ea30b966 1055
400b1ebc
GL		 1056 if (ucmd.wq.log_range_size >
1057 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1058 pr_debug("WQN range size must be equal or smaller than %d\n",
1059 dev->dev->caps.max_rss_tbl_sz);
1060 err = -EOPNOTSUPP;
1061 goto err;
1062 }
1063 range_size = 1 << ucmd.wq.log_range_size;
1064 } else {
1065 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1066 }
0e6e7416 1067
400b1ebc
GL		 1068 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1069 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1070 if (err)
1071 goto err;
1072
400b1ebc
GL		 1073 if (src == MLX4_IB_QP_SRC) {
1074 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1075
1076 err = set_user_sq_size(dev, qp,
1077 (struct mlx4_ib_create_qp *)
1078 &ucmd);
1079 if (err)
1080 goto err;
1081 } else {
1082 qp->sq_no_prefetch = 1;
1083 qp->sq.wqe_cnt = 1;
1084 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1085 /* Allocated buffer expects to have at least that SQ
1086 * size.
1087 */
1088 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1089 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1090 }
1091
1092 qp->umem = ib_umem_get(pd->uobject->context,
1093 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1094 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
225c7b1f
RD		 1095 if (IS_ERR(qp->umem)) {
1096 err = PTR_ERR(qp->umem);
1097 goto err;
1098 }
1099
1100 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
3e7e1193 1101 qp->umem->page_shift, &qp->mtt);
225c7b1f
RD		 1102 if (err)
1103 goto err_buf;
1104
1105 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1106 if (err)
1107 goto err_mtt;
1108
0a1405da 1109 if (qp_has_rq(init_attr)) {
02d89b87 1110 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
400b1ebc
GL		 1111 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1112 ucmd.wq.db_addr, &qp->db);
02d89b87
RD		 1113 if (err)
1114 goto err_mtt;
1115 }
f3301870 1116 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1117 } else {
ea30b966
MG		 1118 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1119 qp_has_rq(init_attr), qp, 0);
1120 if (err)
1121 goto err;
1122
0e6e7416
RD		 1123 qp->sq_no_prefetch = 0;
1124
b832be1e
EC		 1125 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1126 qp->flags |= MLX4_IB_QP_LSO;
1127
c1c98501
MB		 1128 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1129 if (dev->steering_support ==
1130 MLX4_STEERING_MODE_DEVICE_MANAGED)
1131 qp->flags |= MLX4_IB_QP_NETIF;
1132 else
1133 goto err;
1134 }
1135
73898db0
HA		 1136 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1137 err = set_kernel_sq_size(dev, &init_attr->cap,
1138 qp_type, qp, true);
2446304d
EC		 1139 if (err)
1140 goto err;
1141
0a1405da 1142 if (qp_has_rq(init_attr)) {
8900b894 1143 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1144 if (err)
1145 goto err;
225c7b1f 1146
02d89b87
RD		 1147 *qp->db.db = 0;
1148 }
225c7b1f 1149
73898db0 1150 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
8900b894 1151 &qp->buf)) {
73898db0
HA		 1152 memcpy(&init_attr->cap, &backup_cap,
1153 sizeof(backup_cap));
1154 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1155 qp, false);
1156 if (err)
1157 goto err_db;
1158
1159 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
8900b894 1160 PAGE_SIZE * 2, &qp->buf)) {
73898db0
HA		 1161 err = -ENOMEM;
1162 goto err_db;
1163 }
225c7b1f
RD		 1164 }
1165
1166 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1167 &qp->mtt);
1168 if (err)
1169 goto err_buf;
1170
8900b894 1171 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1172 if (err)
1173 goto err_mtt;
1174
e9105cde
LD		 1175 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1176 sizeof(u64), GFP_KERNEL);
1177 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1178 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1179 if (!qp->sq.wrid || !qp->rq.wrid) {
1180 err = -ENOMEM;
1181 goto err_wrid;
1182 }
f3301870 1183 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1184 }
1185
a3cdcbfa 1186 if (sqpn) {
1ffeb2eb
JM		 1187 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1188 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1189 if (alloc_proxy_bufs(pd->device, qp)) {
1190 err = -ENOMEM;
1191 goto err_wrid;
1192 }
1193 }
400b1ebc
GL		 1194 } else if (src == MLX4_IB_RWQ_SRC) {
1195 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1196 range_size, &qpn);
1197 if (err)
1198 goto err_wrid;
a3cdcbfa 1199 } else {
ddae0349
EE		 1200 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1201 * otherwise, the WQE BlueFlame setup flow wrongly causes
1202 * VLAN insertion. */
3987a2d3 1203 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1204 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1205 (init_attr->cap.max_send_wr ?
1206 MLX4_RESERVE_ETH_BF_QP : 0) |
1207 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1208 MLX4_RESERVE_A0_QP : 0),
1209 qp->mqp.usage);
3987a2d3 1210 else
c1c98501
MB		 1211 if (qp->flags & MLX4_IB_QP_NETIF)
1212 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1213 else
1214 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1215 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1216 if (err)
1ffeb2eb 1217 goto err_proxy;
a3cdcbfa
YP		 1218 }
1219
fbfb6625
EBE		 1220 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1221 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1222
8900b894 1223 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1224 if (err)
a3cdcbfa 1225 goto err_qpn;
225c7b1f 1226
0a1405da
SH		 1227 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1228 qp->mqp.qpn |= (1 << 23);
1229
225c7b1f
RD		 1230 /*
1231 * Hardware wants QPN written in big-endian order (after
1232 * shifting) for send doorbell. Precompute this value to save
1233 * a little bit when posting sends.
1234 */
1235 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1236
400b1ebc
GL		 1237 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1238 mlx4_ib_wq_event;
1239
1ffeb2eb
JM		 1240 if (!*caller_qp)
1241 *caller_qp = qp;
35f05dab
YH		 1242
1243 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1244 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1245 to_mcq(init_attr->recv_cq));
1246 /* Maintain device to QPs access, needed for further handling
1247 * via reset flow
1248 */
1249 list_add_tail(&qp->qps_list, &dev->qp_list);
1250 /* Maintain CQ to QPs access, needed for further handling
1251 * via reset flow
1252 */
1253 mcq = to_mcq(init_attr->send_cq);
1254 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1255 mcq = to_mcq(init_attr->recv_cq);
1256 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1257 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1258 to_mcq(init_attr->recv_cq));
1259 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1260 return 0;
1261
a3cdcbfa 1262err_qpn:
c1c98501
MB		 1263 if (!sqpn) {
1264 if (qp->flags & MLX4_IB_QP_NETIF)
1265 mlx4_ib_steer_qp_free(dev, qpn, 1);
400b1ebc
GL		 1266 else if (src == MLX4_IB_RWQ_SRC)
1267 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1268 qp, 0);
c1c98501
MB		 1269 else
1270 mlx4_qp_release_range(dev->dev, qpn, 1);
1271 }
1ffeb2eb
JM		 1272err_proxy:
1273 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1274 free_proxy_bufs(pd->device, qp);
225c7b1f 1275err_wrid:
23f1b384 1276 if (pd->uobject) {
0a1405da
SH		 1277 if (qp_has_rq(init_attr))
1278 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 1279 } else {
0ef2f05c
WW		 1280 kvfree(qp->sq.wrid);
1281 kvfree(qp->rq.wrid);
225c7b1f
RD		 1282 }
1283
1284err_mtt:
1285 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1286
1287err_buf:
1288 if (pd->uobject)
1289 ib_umem_release(qp->umem);
1290 else
1291 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1292
1293err_db:
0a1405da 1294 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 1295 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1296
1297err:
b42dde47
BVA		 1298 if (sqp)
1299 kfree(sqp);
1300 else if (!*caller_qp)
1ffeb2eb 1301 kfree(qp);
225c7b1f
RD		 1302 return err;
1303}
1304
1305static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1306{
1307 switch (state) {
1308 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1309 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1310 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1311 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1312 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1313 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1314 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1315 default: return -1;
1316 }
1317}
1318
1319static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1320 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1321{
338a8fad 1322 if (send_cq == recv_cq) {
35f05dab 1323 spin_lock(&send_cq->lock);
338a8fad
RD		 1324 __acquire(&recv_cq->lock);
1325 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1326 spin_lock(&send_cq->lock);
225c7b1f
RD		 1327 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1328 } else {
35f05dab 1329 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1330 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1331 }
1332}
1333
1334static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1335 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1336{
338a8fad
RD		 1337 if (send_cq == recv_cq) {
1338 __release(&recv_cq->lock);
35f05dab 1339 spin_unlock(&send_cq->lock);
338a8fad 1340 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1341 spin_unlock(&recv_cq->lock);
35f05dab 1342 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1343 } else {
1344 spin_unlock(&send_cq->lock);
35f05dab 1345 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1346 }
1347}
1348
fa417f7b
EC		 1349static void del_gid_entries(struct mlx4_ib_qp *qp)
1350{
1351 struct mlx4_ib_gid_entry *ge, *tmp;
1352
1353 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1354 list_del(&ge->list);
1355 kfree(ge);
1356 }
1357}
1358
0a1405da
SH		 1359static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1360{
1361 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1362 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1363 else
1364 return to_mpd(qp->ibqp.pd);
1365}
1366
400b1ebc 1367static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1368 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1369{
1370 switch (qp->ibqp.qp_type) {
1371 case IB_QPT_XRC_TGT:
1372 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1373 *recv_cq = *send_cq;
1374 break;
1375 case IB_QPT_XRC_INI:
1376 *send_cq = to_mcq(qp->ibqp.send_cq);
1377 *recv_cq = *send_cq;
1378 break;
1379 default:
400b1ebc
GL		 1380 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1381 to_mcq(qp->ibwq.cq);
1382 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1383 *recv_cq;
0a1405da
SH		 1384 break;
1385 }
1386}
1387
3078f5f1
GL		 1388static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1389{
1390 if (qp->state != IB_QPS_RESET) {
1391 int i;
1392
1393 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1394 i++) {
1395 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1396 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1397
1398 mutex_lock(&wq->mutex);
1399
1400 wq->rss_usecnt--;
1401
1402 mutex_unlock(&wq->mutex);
1403 }
1404
1405 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1406 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1407 pr_warn("modify QP %06x to RESET failed.\n",
1408 qp->mqp.qpn);
1409 }
1410
1411 mlx4_qp_remove(dev->dev, &qp->mqp);
1412 mlx4_qp_free(dev->dev, &qp->mqp);
1413 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1414 del_gid_entries(qp);
1415 kfree(qp->rss_ctx);
1416}
1417
225c7b1f 1418static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
400b1ebc 1419 enum mlx4_ib_source_type src, int is_user)
225c7b1f
RD		 1420{
1421 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1422 unsigned long flags;
225c7b1f 1423
2f5bb473 1424 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1425 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1426 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1427 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1428 qp->mqp.qpn);
25476b02 1429 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1430 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1431 qp->pri.smac = 0;
25476b02 1432 qp->pri.smac_port = 0;
2f5bb473
JM		 1433 }
1434 if (qp->alt.smac) {
1435 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1436 qp->alt.smac = 0;
1437 }
1438 if (qp->pri.vid < 0x1000) {
1439 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1440 qp->pri.vid = 0xFFFF;
1441 qp->pri.candidate_vid = 0xFFFF;
1442 qp->pri.update_vid = 0;
1443 }
1444 if (qp->alt.vid < 0x1000) {
1445 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1446 qp->alt.vid = 0xFFFF;
1447 qp->alt.candidate_vid = 0xFFFF;
1448 qp->alt.update_vid = 0;
1449 }
1450 }
225c7b1f 1451
400b1ebc 1452 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1453
35f05dab 1454 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1455 mlx4_ib_lock_cqs(send_cq, recv_cq);
1456
35f05dab
YH		 1457 /* del from lists under both locks above to protect reset flow paths */
1458 list_del(&qp->qps_list);
1459 list_del(&qp->cq_send_list);
1460 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1461 if (!is_user) {
1462 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1463 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1464 if (send_cq != recv_cq)
1465 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1466 }
1467
1468 mlx4_qp_remove(dev->dev, &qp->mqp);
1469
1470 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1471 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1472
1473 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1474
c1c98501
MB		 1475 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1476 if (qp->flags & MLX4_IB_QP_NETIF)
1477 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc
GL		 1478 else if (src == MLX4_IB_RWQ_SRC)
1479 mlx4_ib_release_wqn(to_mucontext(
1480 qp->ibwq.uobject->context), qp, 1);
c1c98501
MB		 1481 else
1482 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1483 }
a3cdcbfa 1484
225c7b1f
RD		 1485 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1486
1487 if (is_user) {
400b1ebc
GL		 1488 if (qp->rq.wqe_cnt) {
1489 struct mlx4_ib_ucontext *mcontext = !src ?
1490 to_mucontext(qp->ibqp.uobject->context) :
1491 to_mucontext(qp->ibwq.uobject->context);
1492 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1493 }
225c7b1f
RD		 1494 ib_umem_release(qp->umem);
1495 } else {
0ef2f05c
WW		 1496 kvfree(qp->sq.wrid);
1497 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1498 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1499 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1500 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1501 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1502 if (qp->rq.wqe_cnt)
6296883c 1503 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1504 }
fa417f7b
EC		 1505
1506 del_gid_entries(qp);
225c7b1f
RD		 1507}
1508
47605df9
JM		 1509static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1510{
1511 /* Native or PPF */
1512 if (!mlx4_is_mfunc(dev->dev) ||
1513 (mlx4_is_master(dev->dev) &&
1514 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1515 return dev->dev->phys_caps.base_sqpn +
1516 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1517 attr->port_num - 1;
1518 }
1519 /* PF or VF -- creating proxies */
1520 if (attr->qp_type == IB_QPT_SMI)
1521 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1522 else
1523 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1524}
1525
e1b866c6
MS		 1526static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1527 struct ib_qp_init_attr *init_attr,
1528 struct ib_udata *udata)
225c7b1f 1529{
1ffeb2eb 1530 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1531 int err;
fbfb6625 1532 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1533 u16 xrcdn = 0;
225c7b1f 1534
3078f5f1
GL		 1535 if (init_attr->rwq_ind_tbl)
1536 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1537
521e575b 1538 /*
1ffeb2eb
JM		 1539 * We only support LSO, vendor flag1, and multicast loopback blocking,
1540 * and only for kernel UD QPs.
521e575b 1541 */
1ffeb2eb
JM		 1542 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1543 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1544 MLX4_IB_SRIOV_TUNNEL_QP |
1545 MLX4_IB_SRIOV_SQP |
40f2287b 1546 MLX4_IB_QP_NETIF |
8900b894 1547 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1548 return ERR_PTR(-EINVAL);
521e575b 1549
c1c98501
MB		 1550 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1551 if (init_attr->qp_type != IB_QPT_UD)
1552 return ERR_PTR(-EINVAL);
1553 }
1554
e1b866c6
MS		 1555 if (init_attr->create_flags) {
1556 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1557 return ERR_PTR(-EINVAL);
1558
1559 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1560 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1561 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1562 init_attr->qp_type != IB_QPT_UD) ||
1563 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1564 init_attr->qp_type > IB_QPT_GSI) ||
1565 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1566 init_attr->qp_type != IB_QPT_GSI))
1567 return ERR_PTR(-EINVAL);
1568 }
b846f25a 1569
225c7b1f 1570 switch (init_attr->qp_type) {
0a1405da
SH		 1571 case IB_QPT_XRC_TGT:
1572 pd = to_mxrcd(init_attr->xrcd)->pd;
1573 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1574 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1575 /* fall through */
1576 case IB_QPT_XRC_INI:
1577 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1578 return ERR_PTR(-ENOSYS);
1579 init_attr->recv_cq = init_attr->send_cq;
1580 /* fall through */
225c7b1f
RD		 1581 case IB_QPT_RC:
1582 case IB_QPT_UC:
3987a2d3 1583 case IB_QPT_RAW_PACKET:
8900b894 1584 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1585 if (!qp)
1586 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1587 qp->pri.vid = 0xFFFF;
1588 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1589 /* fall through */
1590 case IB_QPT_UD:
1591 {
400b1ebc
GL		 1592 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1593 init_attr, udata, 0, &qp);
5b420d9c
DB		 1594 if (err) {
1595 kfree(qp);
225c7b1f 1596 return ERR_PTR(err);
5b420d9c 1597 }
225c7b1f
RD		 1598
1599 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1600 qp->xrcdn = xrcdn;
225c7b1f
RD		 1601
1602 break;
1603 }
1604 case IB_QPT_SMI:
1605 case IB_QPT_GSI:
1606 {
e1b866c6
MS		 1607 int sqpn;
1608
225c7b1f 1609 /* Userspace is not allowed to create special QPs: */
0a1405da 1610 if (udata)
225c7b1f 1611 return ERR_PTR(-EINVAL);
e1b866c6 1612 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1613 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1614 1, 1, &sqpn, 0,
1615 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1616
1617 if (res)
1618 return ERR_PTR(res);
1619 } else {
1620 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1621 }
225c7b1f 1622
400b1ebc
GL		 1623 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1624 init_attr, udata, sqpn, &qp);
1ffeb2eb 1625 if (err)
225c7b1f 1626 return ERR_PTR(err);
225c7b1f
RD		 1627
1628 qp->port = init_attr->port_num;
e1b866c6
MS		 1629 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1630 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1631 break;
1632 }
1633 default:
1634 /* Don't support raw QPs */
1635 return ERR_PTR(-EINVAL);
1636 }
1637
1638 return &qp->ibqp;
1639}
1640
e1b866c6
MS		 1641struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1642 struct ib_qp_init_attr *init_attr,
1643 struct ib_udata *udata) {
1644 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1645 struct ib_qp *ibqp;
1646 struct mlx4_ib_dev *dev = to_mdev(device);
1647
1648 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1649
1650 if (!IS_ERR(ibqp) &&
1651 (init_attr->qp_type == IB_QPT_GSI) &&
1652 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1653 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1654 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1655
1656 if (is_eth &&
1657 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1658 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1659 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1660
1661 if (IS_ERR(sqp->roce_v2_gsi)) {
1662 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1663 sqp->roce_v2_gsi = NULL;
1664 } else {
1665 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1666 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1667 }
1668
1669 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1670 }
1671 }
1672 return ibqp;
1673}
1674
1675static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1676{
1677 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1678 struct mlx4_ib_qp *mqp = to_mqp(qp);
1679
1680 if (is_qp0(dev, mqp))
1681 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1682
c482af64
JM		 1683 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1684 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1685 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1686 dev->qp1_proxy[mqp->port - 1] = NULL;
1687 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1688 }
1689
7b59f0f9
EBE		 1690 if (mqp->counter_index)
1691 mlx4_ib_free_qp_counter(dev, mqp);
1692
3078f5f1
GL		 1693 if (qp->rwq_ind_tbl) {
1694 destroy_qp_rss(dev, mqp);
1695 } else {
1696 struct mlx4_ib_pd *pd;
1697
1698 pd = get_pd(mqp);
1699 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1700 }
225c7b1f
RD		 1701
1702 if (is_sqp(dev, mqp))
1703 kfree(to_msqp(mqp));
1704 else
1705 kfree(mqp);
1706
1707 return 0;
1708}
1709
e1b866c6
MS		 1710int mlx4_ib_destroy_qp(struct ib_qp *qp)
1711{
1712 struct mlx4_ib_qp *mqp = to_mqp(qp);
1713
1714 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1715 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1716
1717 if (sqp->roce_v2_gsi)
1718 ib_destroy_qp(sqp->roce_v2_gsi);
1719 }
1720
1721 return _mlx4_ib_destroy_qp(qp);
1722}
1723
1ffeb2eb 1724static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1725{
1726 switch (type) {
1ffeb2eb
JM		 1727 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1728 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1729 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1730 case MLX4_IB_QPT_XRC_INI:
1731 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1732 case MLX4_IB_QPT_SMI:
1733 case MLX4_IB_QPT_GSI:
1734 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1735
1736 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1737 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1738 MLX4_QP_ST_MLX : -1);
1739 case MLX4_IB_QPT_PROXY_SMI:
1740 case MLX4_IB_QPT_TUN_SMI:
1741 case MLX4_IB_QPT_PROXY_GSI:
1742 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1743 MLX4_QP_ST_UD : -1);
1744 default: return -1;
225c7b1f
RD		 1745 }
1746}
1747
65adfa91 1748static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1749 int attr_mask)
1750{
1751 u8 dest_rd_atomic;
1752 u32 access_flags;
1753 u32 hw_access_flags = 0;
1754
1755 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1756 dest_rd_atomic = attr->max_dest_rd_atomic;
1757 else
1758 dest_rd_atomic = qp->resp_depth;
1759
1760 if (attr_mask & IB_QP_ACCESS_FLAGS)
1761 access_flags = attr->qp_access_flags;
1762 else
1763 access_flags = qp->atomic_rd_en;
1764
1765 if (!dest_rd_atomic)
1766 access_flags &= IB_ACCESS_REMOTE_WRITE;
1767
1768 if (access_flags & IB_ACCESS_REMOTE_READ)
1769 hw_access_flags |= MLX4_QP_BIT_RRE;
1770 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1771 hw_access_flags |= MLX4_QP_BIT_RAE;
1772 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1773 hw_access_flags |= MLX4_QP_BIT_RWE;
1774
1775 return cpu_to_be32(hw_access_flags);
1776}
1777
65adfa91 1778static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1779 int attr_mask)
1780{
1781 if (attr_mask & IB_QP_PKEY_INDEX)
1782 sqp->pkey_index = attr->pkey_index;
1783 if (attr_mask & IB_QP_QKEY)
1784 sqp->qkey = attr->qkey;
1785 if (attr_mask & IB_QP_SQ_PSN)
1786 sqp->send_psn = attr->sq_psn;
1787}
1788
1789static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1790{
1791 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1792}
1793
90898850
DC		 1794static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1795 const struct rdma_ah_attr *ah,
297e0dad 1796 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1797 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1798{
4c3eb3ca 1799 int vidx;
297e0dad 1800 int smac_index;
2f5bb473 1801 int err;
297e0dad 1802
d8966fcd
DC		 1803 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1804 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1805 if (rdma_ah_get_static_rate(ah)) {
1806 path->static_rate = rdma_ah_get_static_rate(ah) +
1807 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1808 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1809 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1810 --path->static_rate;
1811 } else
1812 path->static_rate = 0;
225c7b1f 1813
d8966fcd
DC		 1814 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1815 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1816 int real_sgid_index =
1817 mlx4_ib_gid_index_to_real_index(dev, port,
1818 grh->sgid_index);
5070cd22
MS		 1819
1820 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1821 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1822 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1823 return -1;
1824 }
1825
1826 path->grh_mylmc |= 1 << 7;
5070cd22 1827 path->mgid_index = real_sgid_index;
d8966fcd 1828 path->hop_limit = grh->hop_limit;
225c7b1f 1829 path->tclass_flowlabel =
d8966fcd
DC		 1830 cpu_to_be32((grh->traffic_class << 20) |
1831 (grh->flow_label));
1832 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1833 }
1834
44c58487 1835 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1836 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1837 return -1;
1838
2f5bb473 1839 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1840 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1841
297e0dad 1842 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1843 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1844 if (smac_info->vid < 0x1000) {
1845 /* both valid vlan ids */
1846 if (smac_info->vid != vlan_tag) {
1847 /* different VIDs. unreg old and reg new */
1848 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1849 if (err)
1850 return err;
1851 smac_info->candidate_vid = vlan_tag;
1852 smac_info->candidate_vlan_index = vidx;
1853 smac_info->candidate_vlan_port = port;
1854 smac_info->update_vid = 1;
1855 path->vlan_index = vidx;
1856 } else {
1857 path->vlan_index = smac_info->vlan_index;
1858 }
1859 } else {
1860 /* no current vlan tag in qp */
1861 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1862 if (err)
1863 return err;
1864 smac_info->candidate_vid = vlan_tag;
1865 smac_info->candidate_vlan_index = vidx;
1866 smac_info->candidate_vlan_port = port;
1867 smac_info->update_vid = 1;
1868 path->vlan_index = vidx;
1869 }
297e0dad 1870 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1871 path->fl = 1 << 6;
1872 } else {
1873 /* have current vlan tag. unregister it at modify-qp success */
1874 if (smac_info->vid < 0x1000) {
1875 smac_info->candidate_vid = 0xFFFF;
1876 smac_info->update_vid = 1;
1877 }
4c3eb3ca 1878 }
2f5bb473
JM		 1879
1880 /* get smac_index for RoCE use.
1881 * If no smac was yet assigned, register one.
1882 * If one was already assigned, but the new mac differs,
1883 * unregister the old one and register the new one.
1884 */
25476b02
JM		 1885 if ((!smac_info->smac && !smac_info->smac_port) ||
1886 smac_info->smac != smac) {
2f5bb473
JM		 1887 /* register candidate now, unreg if needed, after success */
1888 smac_index = mlx4_register_mac(dev->dev, port, smac);
1889 if (smac_index >= 0) {
1890 smac_info->candidate_smac_index = smac_index;
1891 smac_info->candidate_smac = smac;
1892 smac_info->candidate_smac_port = port;
1893 } else {
1894 return -EINVAL;
1895 }
1896 } else {
1897 smac_index = smac_info->smac_index;
1898 }
44c58487 1899 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1900 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1901 /* put MAC table smac index for IBoE */
1902 path->grh_mylmc = (u8) (smac_index) | 0x80;
1903 } else {
4c3eb3ca 1904 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1905 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1906 }
fa417f7b 1907
225c7b1f
RD		 1908 return 0;
1909}
1910
297e0dad
MS		 1911static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1912 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1913 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1914 struct mlx4_qp_path *path, u8 port,
1915 u16 vlan_id, u8 *smac)
297e0dad
MS		 1916{
1917 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1918 mlx4_mac_to_u64(smac),
1919 vlan_id,
2f5bb473 1920 path, &mqp->pri, port);
297e0dad
MS		 1921}
1922
1923static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1924 const struct ib_qp_attr *qp,
1925 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1926 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1927 struct mlx4_qp_path *path, u8 port)
1928{
1929 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1930 0,
1931 0xffff,
2f5bb473 1932 path, &mqp->alt, port);
297e0dad
MS		 1933}
1934
fa417f7b
EC		 1935static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1936{
1937 struct mlx4_ib_gid_entry *ge, *tmp;
1938
1939 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1940 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1941 ge->added = 1;
1942 ge->port = qp->port;
1943 }
1944 }
1945}
1946
dbf727de
MB		 1947static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1948 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1949 struct mlx4_qp_context *context)
1950{
2f5bb473
JM		 1951 u64 u64_mac;
1952 int smac_index;
1953
3e0629cb 1954 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1955
1956 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1957 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1958 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1959 if (smac_index >= 0) {
1960 qp->pri.candidate_smac_index = smac_index;
1961 qp->pri.candidate_smac = u64_mac;
1962 qp->pri.candidate_smac_port = qp->port;
1963 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1964 } else {
1965 return -ENOENT;
1966 }
1967 }
1968 return 0;
1969}
1970
7b59f0f9
EBE		 1971static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1972{
1973 struct counter_index *new_counter_index;
1974 int err;
1975 u32 tmp_idx;
1976
1977 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1978 IB_LINK_LAYER_ETHERNET ||
1979 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1980 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1981 return 0;
1982
f3301870 1983 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1984 if (err)
1985 return err;
1986
1987 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1988 if (!new_counter_index) {
1989 mlx4_counter_free(dev->dev, tmp_idx);
1990 return -ENOMEM;
1991 }
1992
1993 new_counter_index->index = tmp_idx;
1994 new_counter_index->allocated = 1;
1995 qp->counter_index = new_counter_index;
1996
1997 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1998 list_add_tail(&new_counter_index->list,
1999 &dev->counters_table[qp->port - 1].counters_list);
2000 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2001
2002 return 0;
2003}
2004
3b5daf28
MS		 2005enum {
2006 MLX4_QPC_ROCE_MODE_1 = 0,
2007 MLX4_QPC_ROCE_MODE_2 = 2,
2008 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2009};
2010
2011static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2012{
2013 switch (gid_type) {
2014 case IB_GID_TYPE_ROCE:
2015 return MLX4_QPC_ROCE_MODE_1;
2016 case IB_GID_TYPE_ROCE_UDP_ENCAP:
2017 return MLX4_QPC_ROCE_MODE_2;
2018 default:
2019 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2020 }
2021}
2022
3078f5f1
GL		 2023/*
2024 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2025 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2026 */
2027static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2028{
fba02e6c 2029 int err = 0;
3078f5f1 2030 int i;
3078f5f1
GL		 2031
2032 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2033 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2034 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2035
2036 mutex_lock(&wq->mutex);
2037
2038 /* Mlx4_ib restrictions:
2039 * WQ's is associated to a port according to the RSS QP it is
2040 * associates to.
2041 * In case the WQ is associated to a different port by another
2042 * RSS QP, return a failure.
2043 */
2044 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2045 err = -EINVAL;
2046 mutex_unlock(&wq->mutex);
2047 break;
2048 }
2049 wq->port = port_num;
2050 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2051 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2052 if (err) {
2053 mutex_unlock(&wq->mutex);
2054 break;
2055 }
2056 }
2057 wq->rss_usecnt++;
2058
2059 mutex_unlock(&wq->mutex);
2060 }
2061
2062 if (i && err) {
2063 int j;
2064
2065 for (j = (i - 1); j >= 0; j--) {
2066 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2067 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2068
2069 mutex_lock(&wq->mutex);
2070
2071 if ((wq->rss_usecnt == 1) &&
2072 (ibwq->state == IB_WQS_RDY))
2073 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2074 pr_warn("failed to reverse WQN=0x%06x\n",
2075 ibwq->wq_num);
2076 wq->rss_usecnt--;
2077
2078 mutex_unlock(&wq->mutex);
2079 }
2080 }
2081
2082 return err;
2083}
2084
2085static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2086{
2087 int i;
2088
2089 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2090 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2091 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2092
2093 mutex_lock(&wq->mutex);
2094
2095 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2096 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2097 pr_warn("failed to reverse WQN=%x\n",
2098 ibwq->wq_num);
2099 wq->rss_usecnt--;
2100
2101 mutex_unlock(&wq->mutex);
2102 }
2103}
2104
2105static void fill_qp_rss_context(struct mlx4_qp_context *context,
2106 struct mlx4_ib_qp *qp)
2107{
2108 struct mlx4_rss_context *rss_context;
2109
2110 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2111 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2112
2113 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2114 rss_context->default_qpn =
2115 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2116 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2117 rss_context->base_qpn_udp = rss_context->default_qpn;
2118 rss_context->flags = qp->rss_ctx->flags;
2119 /* Currently support just toeplitz */
2120 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2121
2122 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2123 MLX4_EN_RSS_KEY_SIZE);
2124}
2125
400b1ebc 2126static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91
MT		 2127 const struct ib_qp_attr *attr, int attr_mask,
2128 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f 2129{
400b1ebc
GL		 2130 struct ib_uobject *ibuobject;
2131 struct ib_srq *ibsrq;
3078f5f1 2132 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2133 enum ib_qp_type qp_type;
2134 struct mlx4_ib_dev *dev;
2135 struct mlx4_ib_qp *qp;
0a1405da
SH		 2136 struct mlx4_ib_pd *pd;
2137 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 2138 struct mlx4_qp_context *context;
2139 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2140 int sqd_event;
c1c98501 2141 int steer_qp = 0;
225c7b1f 2142 int err = -EINVAL;
3ba8e31d 2143 int counter_index;
225c7b1f 2144
400b1ebc
GL		 2145 if (src_type == MLX4_IB_RWQ_SRC) {
2146 struct ib_wq *ibwq;
2147
3078f5f1
GL		 2148 ibwq = (struct ib_wq *)src;
2149 ibuobject = ibwq->uobject;
2150 ibsrq = NULL;
2151 rwq_ind_tbl = NULL;
2152 qp_type = IB_QPT_RAW_PACKET;
2153 qp = to_mqp((struct ib_qp *)ibwq);
2154 dev = to_mdev(ibwq->device);
2155 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2156 } else {
2157 struct ib_qp *ibqp;
2158
3078f5f1
GL		 2159 ibqp = (struct ib_qp *)src;
2160 ibuobject = ibqp->uobject;
2161 ibsrq = ibqp->srq;
2162 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2163 qp_type = ibqp->qp_type;
2164 qp = to_mqp(ibqp);
2165 dev = to_mdev(ibqp->device);
2166 pd = get_pd(qp);
400b1ebc
GL		 2167 }
2168
3dec4878
JM		 2169 /* APM is not supported under RoCE */
2170 if (attr_mask & IB_QP_ALT_PATH &&
2171 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2172 IB_LINK_LAYER_ETHERNET)
2173 return -ENOTSUPP;
2174
225c7b1f
RD		 2175 context = kzalloc(sizeof *context, GFP_KERNEL);
2176 if (!context)
2177 return -ENOMEM;
2178
225c7b1f 2179 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2180 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f 2181
3078f5f1
GL		 2182 if (rwq_ind_tbl) {
2183 fill_qp_rss_context(context, qp);
2184 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2185 }
2186
225c7b1f
RD		 2187 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2188 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2189 else {
2190 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2191 switch (attr->path_mig_state) {
2192 case IB_MIG_MIGRATED:
2193 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2194 break;
2195 case IB_MIG_REARM:
2196 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2197 break;
2198 case IB_MIG_ARMED:
2199 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2200 break;
2201 }
2202 }
2203
ea30b966
MG		 2204 if (qp->inl_recv_sz)
2205 context->param3 |= cpu_to_be32(1 << 25);
2206
400b1ebc 2207 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2208 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2209 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2210 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2211 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2212 if (qp->flags & MLX4_IB_QP_LSO)
2213 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2214 ilog2(dev->dev->caps.max_gso_sz);
2215 else
6e0d733d 2216 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 2217 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2218 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2219 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2220 attr->path_mtu);
f5b40431 2221 goto out;
225c7b1f 2222 }
d1f2cd89
EC		 2223 context->mtu_msgmax = (attr->path_mtu << 5) |
2224 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2225 }
2226
3078f5f1
GL		 2227 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2228 if (qp->rq.wqe_cnt)
2229 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2230 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2231 }
225c7b1f 2232
0e6e7416
RD		 2233 if (qp->sq.wqe_cnt)
2234 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2235 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2236
7b59f0f9
EBE		 2237 if (new_state == IB_QPS_RESET && qp->counter_index)
2238 mlx4_ib_free_qp_counter(dev, qp);
2239
0a1405da 2240 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2241 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2242 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2243 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2244 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2245 }
0e6e7416 2246
400b1ebc 2247 if (ibuobject)
85743f1e
HN		 2248 context->usr_page = cpu_to_be32(
2249 mlx4_to_hw_uar_index(dev->dev,
400b1ebc
GL		 2250 to_mucontext(ibuobject->context)
2251 ->uar.index));
225c7b1f 2252 else
85743f1e
HN		 2253 context->usr_page = cpu_to_be32(
2254 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2255
2256 if (attr_mask & IB_QP_DEST_QPN)
2257 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2258
2259 if (attr_mask & IB_QP_PORT) {
2260 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2261 !(attr_mask & IB_QP_AV)) {
2262 mlx4_set_sched(&context->pri_path, attr->port_num);
2263 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2264 }
2265 }
2266
cfcde11c 2267 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2268 err = create_qp_lb_counter(dev, qp);
2269 if (err)
2270 goto out;
2271
3ba8e31d
EBE		 2272 counter_index =
2273 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2274 if (qp->counter_index)
2275 counter_index = qp->counter_index->index;
2276
3ba8e31d
EBE		 2277 if (counter_index != -1) {
2278 context->pri_path.counter_index = counter_index;
cfcde11c 2279 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2280 if (qp->counter_index) {
2281 context->pri_path.fl |=
2282 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2283 context->pri_path.vlan_control |=
2284 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2285 }
cfcde11c 2286 } else
47d8417f
EBE		 2287 context->pri_path.counter_index =
2288 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2289
2290 if (qp->flags & MLX4_IB_QP_NETIF) {
2291 mlx4_ib_steer_qp_reg(dev, qp, 1);
2292 steer_qp = 1;
2293 }
e1b866c6 2294
400b1ebc 2295 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2296 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2297 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2298 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2299
2300 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2301 }
cfcde11c
OG		 2302 }
2303
225c7b1f 2304 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2305 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2306 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2307 context->pri_path.pkey_index = attr->pkey_index;
2308 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2309 }
2310
225c7b1f 2311 if (attr_mask & IB_QP_AV) {
400b1ebc 2312 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de
MB		 2313 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2314 union ib_gid gid;
bf08e884 2315 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
dbf727de
MB		 2316 u16 vlan = 0xffff;
2317 u8 smac[ETH_ALEN];
2318 int status = 0;
d8966fcd
DC		 2319 int is_eth =
2320 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2321 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2322
d8966fcd
DC		 2323 if (is_eth) {
2324 int index =
2325 rdma_ah_read_grh(&attr->ah_attr)->sgid_index;
dbf727de 2326
400b1ebc 2327 status = ib_get_cached_gid(&dev->ib_dev, port_num,
dbf727de
MB		 2328 index, &gid, &gid_attr);
2329 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
2330 status = -ENOENT;
2331 if (!status && gid_attr.ndev) {
2332 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
2333 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
2334 dev_put(gid_attr.ndev);
2335 }
2336 }
2337 if (status)
2338 goto out;
2339
2f5bb473 2340 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2341 port_num, vlan, smac))
225c7b1f 2342 goto out;
225c7b1f
RD		 2343
2344 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2345 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2346
2347 if (is_eth &&
2348 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2349 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
2350
2351 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2352 err = -EINVAL;
2353 goto out;
2354 }
2355 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2356 }
2357
225c7b1f
RD		 2358 }
2359
2360 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2361 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2362 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2363 }
2364
2365 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2366 if (attr->alt_port_num == 0 ||
2367 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2368 goto out;
225c7b1f 2369
5ae2a7a8
RD		 2370 if (attr->alt_pkey_index >=
2371 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2372 goto out;
5ae2a7a8 2373
2f5bb473
JM		 2374 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2375 &context->alt_path,
297e0dad 2376 attr->alt_port_num))
f5b40431 2377 goto out;
225c7b1f
RD		 2378
2379 context->alt_path.pkey_index = attr->alt_pkey_index;
2380 context->alt_path.ackto = attr->alt_timeout << 3;
2381 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2382 }
2383
3078f5f1
GL		 2384 context->pd = cpu_to_be32(pd->pdn);
2385
2386 if (!rwq_ind_tbl) {
2387 get_cqs(qp, src_type, &send_cq, &recv_cq);
2388 } else { /* Set dummy CQs to be compatible with HV and PRM */
2389 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2390 recv_cq = send_cq;
2391 }
0a1405da
SH		 2392 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2393 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2394 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 2395
95d04f07 2396 /* Set "fast registration enabled" for all kernel QPs */
400b1ebc 2397 if (!ibuobject)
95d04f07
RD		 2398 context->params1 |= cpu_to_be32(1 << 11);
2399
57f01b53
JM		 2400 if (attr_mask & IB_QP_RNR_RETRY) {
2401 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2402 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2403 }
2404
225c7b1f
RD		 2405 if (attr_mask & IB_QP_RETRY_CNT) {
2406 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2407 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2408 }
2409
2410 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2411 if (attr->max_rd_atomic)
2412 context->params1 |=
2413 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2414 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2415 }
2416
2417 if (attr_mask & IB_QP_SQ_PSN)
2418 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2419
225c7b1f
RD		 2420 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2421 if (attr->max_dest_rd_atomic)
2422 context->params2 |=
2423 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2424 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2425 }
2426
2427 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2428 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2429 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2430 }
2431
400b1ebc 2432 if (ibsrq)
225c7b1f
RD		 2433 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2434
2435 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2436 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2437 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2438 }
2439 if (attr_mask & IB_QP_RQ_PSN)
2440 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2441
1ffeb2eb 2442 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2443 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2444 if (qp->mlx4_ib_qp_type &
2445 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2446 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2447 else {
2448 if (mlx4_is_mfunc(dev->dev) &&
2449 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2450 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2451 MLX4_RESERVED_QKEY_BASE) {
2452 pr_err("Cannot use reserved QKEY"
2453 " 0x%x (range 0xffff0000..0xffffffff"
2454 " is reserved)\n", attr->qkey);
2455 err = -EINVAL;
2456 goto out;
2457 }
2458 context->qkey = cpu_to_be32(attr->qkey);
2459 }
225c7b1f
RD		 2460 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2461 }
2462
400b1ebc
GL		 2463 if (ibsrq)
2464 context->srqn = cpu_to_be32(1 << 24 |
2465 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2466
400b1ebc
GL		 2467 if (qp->rq.wqe_cnt &&
2468 cur_state == IB_QPS_RESET &&
2469 new_state == IB_QPS_INIT)
225c7b1f
RD		 2470 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2471
2472 if (cur_state == IB_QPS_INIT &&
2473 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2474 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2475 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2476 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2477 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2478 qp->mlx4_ib_qp_type &
2479 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2480 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2481 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2482 context->pri_path.fl = 0x80;
2483 } else {
2484 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2485 context->pri_path.fl = 0x80;
225c7b1f 2486 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2487 }
2f5bb473
JM		 2488 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2489 IB_LINK_LAYER_ETHERNET) {
2490 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2491 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2492 context->pri_path.feup = 1 << 7; /* don't fsm */
2493 /* handle smac_index */
2494 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2495 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2496 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2497 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2498 if (err) {
2499 err = -EINVAL;
2500 goto out;
2501 }
9433c188
MB		 2502 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2503 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2504 }
2505 }
225c7b1f
RD		 2506 }
2507
400b1ebc 2508 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2509 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2510 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2511 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2512 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 2513 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 2514 context->srqn = cpu_to_be32(7 << 28);
2515 }
2516 }
3528f696 2517
400b1ebc 2518 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2519 int is_eth = rdma_port_get_link_layer(
2520 &dev->ib_dev, qp->port) ==
2521 IB_LINK_LAYER_ETHERNET;
2522 if (is_eth) {
2523 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2524 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2525 }
2526 }
2527
225c7b1f
RD		 2528 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2529 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2530 sqd_event = 1;
2531 else
2532 sqd_event = 0;
2533
400b1ebc
GL		 2534 if (!ibuobject &&
2535 cur_state == IB_QPS_RESET &&
2536 new_state == IB_QPS_INIT)
3b5daf28 2537 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2538
c0be5fb5
EC		 2539 /*
2540 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2541 * ownership bits of the send queue are set and the SQ
2542 * headroom is stamped so that the hardware doesn't start
2543 * processing stale work requests.
c0be5fb5 2544 */
400b1ebc
GL		 2545 if (!ibuobject &&
2546 cur_state == IB_QPS_RESET &&
2547 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2548 struct mlx4_wqe_ctrl_seg *ctrl;
2549 int i;
2550
0e6e7416 2551 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2552 ctrl = get_send_wqe(qp, i);
2553 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553 2554 if (qp->sq_max_wqes_per_wr == 1)
224e92e0
BB		 2555 ctrl->qpn_vlan.fence_size =
2556 1 << (qp->sq.wqe_shift - 4);
0e6e7416 2557
ea54b10c 2558 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 2559 }
2560 }
2561
225c7b1f
RD		 2562 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2563 to_mlx4_state(new_state), context, optpar,
2564 sqd_event, &qp->mqp);
2565 if (err)
2566 goto out;
2567
2568 qp->state = new_state;
2569
2570 if (attr_mask & IB_QP_ACCESS_FLAGS)
2571 qp->atomic_rd_en = attr->qp_access_flags;
2572 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2573 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2574 if (attr_mask & IB_QP_PORT) {
225c7b1f 2575 qp->port = attr->port_num;
fa417f7b
EC		 2576 update_mcg_macs(dev, qp);
2577 }
225c7b1f
RD		 2578 if (attr_mask & IB_QP_ALT_PATH)
2579 qp->alt_port = attr->alt_port_num;
2580
2581 if (is_sqp(dev, qp))
2582 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2583
2584 /*
2585 * If we moved QP0 to RTR, bring the IB link up; if we moved
2586 * QP0 to RESET or ERROR, bring the link back down.
2587 */
2588 if (is_qp0(dev, qp)) {
2589 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2590 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2591 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2592 qp->port);
225c7b1f
RD		 2593
2594 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2595 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2596 mlx4_CLOSE_PORT(dev->dev, qp->port);
2597 }
2598
2599 /*
2600 * If we moved a kernel QP to RESET, clean up all old CQ
2601 * entries and reinitialize the QP.
2602 */
2f5bb473 2603 if (new_state == IB_QPS_RESET) {
400b1ebc 2604 if (!ibuobject) {
2f5bb473 2605 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2606 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2607 if (send_cq != recv_cq)
2608 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2609
2610 qp->rq.head = 0;
2611 qp->rq.tail = 0;
2612 qp->sq.head = 0;
2613 qp->sq.tail = 0;
2614 qp->sq_next_wqe = 0;
2615 if (qp->rq.wqe_cnt)
2616 *qp->db.db = 0;
225c7b1f 2617
2f5bb473
JM		 2618 if (qp->flags & MLX4_IB_QP_NETIF)
2619 mlx4_ib_steer_qp_reg(dev, qp, 0);
2620 }
25476b02 2621 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2622 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2623 qp->pri.smac = 0;
25476b02 2624 qp->pri.smac_port = 0;
2f5bb473
JM		 2625 }
2626 if (qp->alt.smac) {
2627 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2628 qp->alt.smac = 0;
2629 }
2630 if (qp->pri.vid < 0x1000) {
2631 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2632 qp->pri.vid = 0xFFFF;
2633 qp->pri.candidate_vid = 0xFFFF;
2634 qp->pri.update_vid = 0;
2635 }
c1c98501 2636
2f5bb473
JM		 2637 if (qp->alt.vid < 0x1000) {
2638 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2639 qp->alt.vid = 0xFFFF;
2640 qp->alt.candidate_vid = 0xFFFF;
2641 qp->alt.update_vid = 0;
2642 }
225c7b1f 2643 }
225c7b1f 2644out:
7b59f0f9
EBE		 2645 if (err && qp->counter_index)
2646 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2647 if (err && steer_qp)
2648 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2649 kfree(context);
25476b02
JM		 2650 if (qp->pri.candidate_smac ||
2651 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2652 if (err) {
2653 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2654 } else {
25476b02 2655 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2656 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2657 qp->pri.smac = qp->pri.candidate_smac;
2658 qp->pri.smac_index = qp->pri.candidate_smac_index;
2659 qp->pri.smac_port = qp->pri.candidate_smac_port;
2660 }
2661 qp->pri.candidate_smac = 0;
2662 qp->pri.candidate_smac_index = 0;
2663 qp->pri.candidate_smac_port = 0;
2664 }
2665 if (qp->alt.candidate_smac) {
2666 if (err) {
2667 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2668 } else {
2669 if (qp->alt.smac)
2670 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2671 qp->alt.smac = qp->alt.candidate_smac;
2672 qp->alt.smac_index = qp->alt.candidate_smac_index;
2673 qp->alt.smac_port = qp->alt.candidate_smac_port;
2674 }
2675 qp->alt.candidate_smac = 0;
2676 qp->alt.candidate_smac_index = 0;
2677 qp->alt.candidate_smac_port = 0;
2678 }
2679
2680 if (qp->pri.update_vid) {
2681 if (err) {
2682 if (qp->pri.candidate_vid < 0x1000)
2683 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2684 qp->pri.candidate_vid);
2685 } else {
2686 if (qp->pri.vid < 0x1000)
2687 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2688 qp->pri.vid);
2689 qp->pri.vid = qp->pri.candidate_vid;
2690 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2691 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2692 }
2693 qp->pri.candidate_vid = 0xFFFF;
2694 qp->pri.update_vid = 0;
2695 }
2696
2697 if (qp->alt.update_vid) {
2698 if (err) {
2699 if (qp->alt.candidate_vid < 0x1000)
2700 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2701 qp->alt.candidate_vid);
2702 } else {
2703 if (qp->alt.vid < 0x1000)
2704 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2705 qp->alt.vid);
2706 qp->alt.vid = qp->alt.candidate_vid;
2707 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2708 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2709 }
2710 qp->alt.candidate_vid = 0xFFFF;
2711 qp->alt.update_vid = 0;
2712 }
2713
225c7b1f
RD		 2714 return err;
2715}
2716
3078f5f1
GL		 2717enum {
2718 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2719 IB_QP_PORT),
2720};
2721
e1b866c6
MS		 2722static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2723 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2724{
2725 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2726 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2727 enum ib_qp_state cur_state, new_state;
2728 int err = -EINVAL;
297e0dad 2729 int ll;
65adfa91
MT		 2730 mutex_lock(&qp->mutex);
2731
2732 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2733 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2734
297e0dad
MS		 2735 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2736 ll = IB_LINK_LAYER_UNSPECIFIED;
2737 } else {
2738 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2739 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2740 }
dd5f03be
MB		 2741
2742 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2743 attr_mask, ll)) {
b1d8eb5a
JM		 2744 pr_debug("qpn 0x%x: invalid attribute mask specified "
2745 "for transition %d to %d. qp_type %d,"
2746 " attr_mask 0x%x\n",
2747 ibqp->qp_num, cur_state, new_state,
2748 ibqp->qp_type, attr_mask);
65adfa91 2749 goto out;
b1d8eb5a 2750 }
65adfa91 2751
3078f5f1
GL		 2752 if (ibqp->rwq_ind_tbl) {
2753 if (!(((cur_state == IB_QPS_RESET) &&
2754 (new_state == IB_QPS_INIT)) ||
2755 ((cur_state == IB_QPS_INIT) &&
2756 (new_state == IB_QPS_RTR)))) {
2757 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2758 ibqp->qp_num, cur_state, new_state);
2759
2760 err = -EOPNOTSUPP;
2761 goto out;
2762 }
2763
2764 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2765 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2766 ibqp->qp_num, attr_mask, cur_state, new_state);
2767
2768 err = -EOPNOTSUPP;
2769 goto out;
2770 }
2771 }
2772
c6215745
MS		 2773 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2774 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2775 if ((ibqp->qp_type == IB_QPT_RC) ||
2776 (ibqp->qp_type == IB_QPT_UD) ||
2777 (ibqp->qp_type == IB_QPT_UC) ||
2778 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2779 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2780 attr->port_num = mlx4_ib_bond_next_port(dev);
2781 }
2782 } else {
2783 /* no sense in changing port_num
2784 * when ports are bonded */
2785 attr_mask &= ~IB_QP_PORT;
2786 }
2787 }
2788
65adfa91 2789 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2790 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2791 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2792 "for transition %d to %d. qp_type %d\n",
2793 ibqp->qp_num, attr->port_num, cur_state,
2794 new_state, ibqp->qp_type);
65adfa91
MT		 2795 goto out;
2796 }
2797
3987a2d3
OG		 2798 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2799 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2800 IB_LINK_LAYER_ETHERNET))
2801 goto out;
2802
5ae2a7a8
RD		 2803 if (attr_mask & IB_QP_PKEY_INDEX) {
2804 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2805 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2806 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2807 "for transition %d to %d. qp_type %d\n",
2808 ibqp->qp_num, attr->pkey_index, cur_state,
2809 new_state, ibqp->qp_type);
5ae2a7a8 2810 goto out;
b1d8eb5a 2811 }
5ae2a7a8
RD		 2812 }
2813
65adfa91
MT		 2814 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2815 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2816 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2817 "Transition %d to %d. qp_type %d\n",
2818 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2819 new_state, ibqp->qp_type);
65adfa91
MT		 2820 goto out;
2821 }
2822
2823 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2824 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2825 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2826 "Transition %d to %d. qp_type %d\n",
2827 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2828 new_state, ibqp->qp_type);
65adfa91
MT		 2829 goto out;
2830 }
2831
2832 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2833 err = 0;
2834 goto out;
2835 }
2836
3078f5f1
GL		 2837 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2838 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2839 if (err)
2840 goto out;
2841 }
2842
400b1ebc
GL		 2843 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2844 cur_state, new_state);
65adfa91 2845
3078f5f1
GL		 2846 if (ibqp->rwq_ind_tbl && err)
2847 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2848
c6215745
MS		 2849 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2850 attr->port_num = 1;
2851
65adfa91
MT		 2852out:
2853 mutex_unlock(&qp->mutex);
2854 return err;
2855}
2856
e1b866c6
MS		 2857int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2858 int attr_mask, struct ib_udata *udata)
2859{
2860 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2861 int ret;
2862
2863 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2864
2865 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2866 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2867 int err = 0;
2868
2869 if (sqp->roce_v2_gsi)
2870 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2871 if (err)
2872 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2873 err);
2874 }
2875 return ret;
2876}
2877
99ec41d0
JM		 2878static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2879{
2880 int i;
2881 for (i = 0; i < dev->caps.num_ports; i++) {
2882 if (qpn == dev->caps.qp0_proxy[i] ||
2883 qpn == dev->caps.qp0_tunnel[i]) {
2884 *qkey = dev->caps.qp0_qkey[i];
2885 return 0;
2886 }
2887 }
2888 return -EINVAL;
2889}
2890
1ffeb2eb 2891static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2892 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2893 void *wqe, unsigned *mlx_seg_len)
2894{
2895 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2896 struct ib_device *ib_dev = &mdev->ib_dev;
2897 struct mlx4_wqe_mlx_seg *mlx = wqe;
2898 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2899 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2900 u16 pkey;
2901 u32 qkey;
2902 int send_size;
2903 int header_size;
2904 int spc;
2905 int i;
2906
e622f2f4 2907 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2908 return -EINVAL;
2909
2910 send_size = 0;
2911
e622f2f4
CH		 2912 for (i = 0; i < wr->wr.num_sge; ++i)
2913 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2914
2915 /* for proxy-qp0 sends, need to add in size of tunnel header */
2916 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2917 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2918 send_size += sizeof (struct mlx4_ib_tunnel_header);
2919
25f40220 2920 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2921
2922 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2923 sqp->ud_header.lrh.service_level =
2924 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2925 sqp->ud_header.lrh.destination_lid =
2926 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2927 sqp->ud_header.lrh.source_lid =
2928 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2929 }
2930
2931 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2932
2933 /* force loopback */
2934 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2935 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2936
2937 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2938 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2939 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2940 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2941 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2942 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2943 else
2944 sqp->ud_header.bth.destination_qpn =
47605df9 2945 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2946
2947 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2948 if (mlx4_is_master(mdev->dev)) {
2949 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2950 return -EINVAL;
2951 } else {
2952 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2953 return -EINVAL;
2954 }
1ffeb2eb
JM		 2955 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2956 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2957
2958 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2959 sqp->ud_header.immediate_present = 0;
2960
2961 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2962
2963 /*
2964 * Inline data segments may not cross a 64 byte boundary. If
2965 * our UD header is bigger than the space available up to the
2966 * next 64 byte boundary in the WQE, use two inline data
2967 * segments to hold the UD header.
2968 */
2969 spc = MLX4_INLINE_ALIGN -
2970 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2971 if (header_size <= spc) {
2972 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2973 memcpy(inl + 1, sqp->header_buf, header_size);
2974 i = 1;
2975 } else {
2976 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2977 memcpy(inl + 1, sqp->header_buf, spc);
2978
2979 inl = (void *) (inl + 1) + spc;
2980 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2981 /*
2982 * Need a barrier here to make sure all the data is
2983 * visible before the byte_count field is set.
2984 * Otherwise the HCA prefetcher could grab the 64-byte
2985 * chunk with this inline segment and get a valid (!=
2986 * 0xffffffff) byte count but stale data, and end up
2987 * generating a packet with bad headers.
2988 *
2989 * The first inline segment's byte_count field doesn't
2990 * need a barrier, because it comes after a
2991 * control/MLX segment and therefore is at an offset
2992 * of 16 mod 64.
2993 */
2994 wmb();
2995 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2996 i = 2;
2997 }
2998
2999 *mlx_seg_len =
3000 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3001 return 0;
3002}
3003
fd10ed8e
JM		 3004static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3005{
3006 union sl2vl_tbl_to_u64 tmp_vltab;
3007 u8 vl;
3008
3009 if (sl > 15)
3010 return 0xf;
3011 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3012 vl = tmp_vltab.sl8[sl >> 1];
3013 if (sl & 1)
3014 vl &= 0x0f;
3015 else
3016 vl >>= 4;
3017 return vl;
3018}
3019
a748d60d
TB		 3020static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3021 int index, union ib_gid *gid,
3022 enum ib_gid_type *gid_type)
3023{
3024 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3025 struct mlx4_port_gid_table *port_gid_table;
3026 unsigned long flags;
3027
3028 port_gid_table = &iboe->gids[port_num - 1];
3029 spin_lock_irqsave(&iboe->lock, flags);
3030 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3031 *gid_type = port_gid_table->gids[index].gid_type;
3032 spin_unlock_irqrestore(&iboe->lock, flags);
3033 if (!memcmp(gid, &zgid, sizeof(*gid)))
3034 return -ENOENT;
3035
3036 return 0;
3037}
3038
3ef967a4 3039#define MLX4_ROCEV2_QP1_SPORT 0xC000
e622f2f4 3040static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 3041 void *wqe, unsigned *mlx_seg_len)
225c7b1f 3042{
a478868a 3043 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 3044 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 3045 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 3046 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 3047 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 3048 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 3049 union ib_gid sgid;
225c7b1f
RD		 3050 u16 pkey;
3051 int send_size;
3052 int header_size;
e61ef241 3053 int spc;
225c7b1f 3054 int i;
1ffeb2eb 3055 int err = 0;
57d88cff 3056 u16 vlan = 0xffff;
a29bec12
RD		 3057 bool is_eth;
3058 bool is_vlan = false;
3059 bool is_grh;
3ef967a4
MS		 3060 bool is_udp = false;
3061 int ip_version = 0;
225c7b1f
RD		 3062
3063 send_size = 0;
e622f2f4
CH		 3064 for (i = 0; i < wr->wr.num_sge; ++i)
3065 send_size += wr->wr.sg_list[i].length;
225c7b1f 3066
fa417f7b
EC		 3067 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3068 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3069 if (is_eth) {
a748d60d 3070 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3071 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3072 /* When multi-function is enabled, the ib_core gid
3073 * indexes don't necessarily match the hw ones, so
3074 * we must use our own cache */
6ee51a4e
JM		 3075 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3076 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3077 ah->av.ib.gid_index, &sgid.raw[0]);
3078 if (err)
3079 return err;
1ffeb2eb 3080 } else {
a748d60d
TB		 3081 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3082 ah->av.ib.gid_index,
3083 &sgid, &gid_type);
3ef967a4 3084 if (!err) {
a748d60d 3085 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3086 if (is_udp) {
3087 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3088 ip_version = 4;
3089 else
3090 ip_version = 6;
3091 is_grh = false;
3092 }
3093 } else {
1ffeb2eb 3094 return err;
3ef967a4 3095 }
1ffeb2eb 3096 }
0e9855db 3097 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 3098 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3099 is_vlan = 1;
3100 }
4c3eb3ca 3101 }
25f40220 3102 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3103 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3104 if (err)
3105 return err;
fa417f7b
EC		 3106
3107 if (!is_eth) {
3108 sqp->ud_header.lrh.service_level =
3109 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3110 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3111 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3112 }
225c7b1f 3113
3ef967a4 3114 if (is_grh || (ip_version == 6)) {
225c7b1f 3115 sqp->ud_header.grh.traffic_class =
fa417f7b 3116 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3117 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3118 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3119 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3120 if (is_eth) {
6ee51a4e 3121 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3122 } else {
3123 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3124 /* When multi-function is enabled, the ib_core gid
3125 * indexes don't necessarily match the hw ones, so
3126 * we must use our own cache
3127 */
3128 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3129 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3130 demux[sqp->qp.port - 1].
3131 subnet_prefix)));
baa0be70
JM		 3132 sqp->ud_header.grh.source_gid.global.interface_id =
3133 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3134 guid_cache[ah->av.ib.gid_index];
3135 } else {
3136 ib_get_cached_gid(ib_dev,
3137 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3138 ah->av.ib.gid_index,
3139 &sqp->ud_header.grh.source_gid, NULL);
3140 }
6ee51a4e 3141 }
225c7b1f 3142 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3143 ah->av.ib.dgid, 16);
225c7b1f
RD		 3144 }
3145
3ef967a4
MS		 3146 if (ip_version == 4) {
3147 sqp->ud_header.ip4.tos =
3148 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3149 sqp->ud_header.ip4.id = 0;
3150 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3151 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3152
3153 memcpy(&sqp->ud_header.ip4.saddr,
3154 sgid.raw + 12, 4);
3155 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3156 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3157 }
3158
3159 if (is_udp) {
3160 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3161 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3162 sqp->ud_header.udp.csum = 0;
3163 }
3164
225c7b1f 3165 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3166
3167 if (!is_eth) {
3168 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3169 (sqp->ud_header.lrh.destination_lid ==
3170 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3171 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3172 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3173 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3174 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3175 }
225c7b1f 3176
e622f2f4 3177 switch (wr->wr.opcode) {
225c7b1f
RD		 3178 case IB_WR_SEND:
3179 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3180 sqp->ud_header.immediate_present = 0;
3181 break;
3182 case IB_WR_SEND_WITH_IMM:
3183 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3184 sqp->ud_header.immediate_present = 1;
e622f2f4 3185 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3186 break;
3187 default:
3188 return -EINVAL;
3189 }
3190
fa417f7b 3191 if (is_eth) {
6ee51a4e 3192 struct in6_addr in6;
3ef967a4 3193 u16 ether_type;
c0c1d3d7
OD		 3194 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3195
69ae5439 3196 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3197 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3198
c0c1d3d7 3199 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3200
1049f138 3201 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3202 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3203 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3204 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3205 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3206
3e0629cb 3207
fa417f7b
EC		 3208 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3209 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3210 if (!is_vlan) {
3ef967a4 3211 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3212 } else {
3ef967a4 3213 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3214 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3215 }
fa417f7b 3216 } else {
fd10ed8e
JM		 3217 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3218 sl_to_vl(to_mdev(ib_dev),
3219 sqp->ud_header.lrh.service_level,
3220 sqp->qp.port);
3221 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3222 return -EINVAL;
fa417f7b
EC		 3223 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3224 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3225 }
e622f2f4 3226 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 3227 if (!sqp->qp.ibqp.qp_num)
3228 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3229 else
e622f2f4 3230 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 3231 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3232 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3233 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3234 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3235 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3236 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3237
3238 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3239
3240 if (0) {
987c8f8f 3241 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3242 for (i = 0; i < header_size / 4; ++i) {
3243 if (i % 8 == 0)
987c8f8f
SP		 3244 pr_err(" [%02x] ", i * 4);
3245 pr_cont(" %08x",
3246 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3247 if ((i + 1) % 8 == 0)
987c8f8f 3248 pr_cont("\n");
225c7b1f 3249 }
987c8f8f 3250 pr_err("\n");
225c7b1f
RD		 3251 }
3252
e61ef241
RD		 3253 /*
3254 * Inline data segments may not cross a 64 byte boundary. If
3255 * our UD header is bigger than the space available up to the
3256 * next 64 byte boundary in the WQE, use two inline data
3257 * segments to hold the UD header.
3258 */
3259 spc = MLX4_INLINE_ALIGN -
3260 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3261 if (header_size <= spc) {
3262 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3263 memcpy(inl + 1, sqp->header_buf, header_size);
3264 i = 1;
3265 } else {
3266 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3267 memcpy(inl + 1, sqp->header_buf, spc);
3268
3269 inl = (void *) (inl + 1) + spc;
3270 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3271 /*
3272 * Need a barrier here to make sure all the data is
3273 * visible before the byte_count field is set.
3274 * Otherwise the HCA prefetcher could grab the 64-byte
3275 * chunk with this inline segment and get a valid (!=
3276 * 0xffffffff) byte count but stale data, and end up
3277 * generating a packet with bad headers.
3278 *
3279 * The first inline segment's byte_count field doesn't
3280 * need a barrier, because it comes after a
3281 * control/MLX segment and therefore is at an offset
3282 * of 16 mod 64.
3283 */
3284 wmb();
3285 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3286 i = 2;
3287 }
225c7b1f 3288
f438000f
RD		 3289 *mlx_seg_len =
3290 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3291 return 0;
225c7b1f
RD		 3292}
3293
3294static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3295{
3296 unsigned cur;
3297 struct mlx4_ib_cq *cq;
3298
3299 cur = wq->head - wq->tail;
0e6e7416 3300 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3301 return 0;
3302
3303 cq = to_mcq(ib_cq);
3304 spin_lock(&cq->lock);
3305 cur = wq->head - wq->tail;
3306 spin_unlock(&cq->lock);
3307
0e6e7416 3308 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3309}
3310
95d04f07
RD		 3311static __be32 convert_access(int acc)
3312{
6ff63e19
SM		 3313 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3314 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3315 (acc & IB_ACCESS_REMOTE_WRITE ?
3316 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3317 (acc & IB_ACCESS_REMOTE_READ ?
3318 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3319 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3320 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3321}
3322
1b2cd0fc
SG		 3323static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3324 struct ib_reg_wr *wr)
3325{
3326 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3327
3328 fseg->flags = convert_access(wr->access);
3329 fseg->mem_key = cpu_to_be32(wr->key);
3330 fseg->buf_list = cpu_to_be64(mr->page_map);
3331 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3332 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3333 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3334 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3335 fseg->reserved[0] = 0;
3336 fseg->reserved[1] = 0;
3337}
3338
95d04f07
RD		 3339static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3340{
aee38fad
SM		 3341 memset(iseg, 0, sizeof(*iseg));
3342 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3343}
3344
0fbfa6a9
RD		 3345static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3346 u64 remote_addr, u32 rkey)
3347{
3348 rseg->raddr = cpu_to_be64(remote_addr);
3349 rseg->rkey = cpu_to_be32(rkey);
3350 rseg->reserved = 0;
3351}
3352
e622f2f4
CH		 3353static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3354 struct ib_atomic_wr *wr)
0fbfa6a9 3355{
e622f2f4
CH		 3356 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3357 aseg->swap_add = cpu_to_be64(wr->swap);
3358 aseg->compare = cpu_to_be64(wr->compare_add);
3359 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3360 aseg->swap_add = cpu_to_be64(wr->compare_add);
3361 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3362 } else {
e622f2f4 3363 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3364 aseg->compare = 0;
3365 }
3366
3367}
3368
6fa8f719 3369static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 3370 struct ib_atomic_wr *wr)
6fa8f719 3371{
e622f2f4
CH		 3372 aseg->swap_add = cpu_to_be64(wr->swap);
3373 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3374 aseg->compare = cpu_to_be64(wr->compare_add);
3375 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3376}
3377
0fbfa6a9 3378static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 3379 struct ib_ud_wr *wr)
0fbfa6a9 3380{
e622f2f4
CH		 3381 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3382 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3383 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3384 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3385 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3386}
3387
1ffeb2eb
JM		 3388static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3389 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 3390 struct ib_ud_wr *wr,
97982f5a 3391 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3392{
e622f2f4 3393 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3394 struct mlx4_av sqp_av = {0};
3395 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3396
3397 /* force loopback */
3398 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3399 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3400 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3401 cpu_to_be32(0xf0000000);
3402
3403 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 3404 if (qpt == MLX4_IB_QPT_PROXY_GSI)
3405 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
3406 else
3407 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 3408 /* Use QKEY from the QP context, which is set by master */
3409 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3410}
3411
e622f2f4 3412static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 3413{
3414 struct mlx4_wqe_inline_seg *inl = wqe;
3415 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3416 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3417 int spc;
3418 int i;
3419
3420 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3421 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3422 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3423 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3424 memcpy(hdr.mac, ah->av.eth.mac, 6);
3425 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3426
3427 spc = MLX4_INLINE_ALIGN -
3428 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3429 if (sizeof (hdr) <= spc) {
3430 memcpy(inl + 1, &hdr, sizeof (hdr));
3431 wmb();
3432 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3433 i = 1;
3434 } else {
3435 memcpy(inl + 1, &hdr, spc);
3436 wmb();
3437 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3438
3439 inl = (void *) (inl + 1) + spc;
3440 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3441 wmb();
3442 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3443 i = 2;
3444 }
3445
3446 *mlx_seg_len =
3447 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3448}
3449
6e694ea3
JM		 3450static void set_mlx_icrc_seg(void *dseg)
3451{
3452 u32 *t = dseg;
3453 struct mlx4_wqe_inline_seg *iseg = dseg;
3454
3455 t[1] = 0;
3456
3457 /*
3458 * Need a barrier here before writing the byte_count field to
3459 * make sure that all the data is visible before the
3460 * byte_count field is set. Otherwise, if the segment begins
3461 * a new cacheline, the HCA prefetcher could grab the 64-byte
3462 * chunk and get a valid (!= * 0xffffffff) byte count but
3463 * stale data, and end up sending the wrong data.
3464 */
3465 wmb();
3466
3467 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3468}
3469
3470static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3471{
d420d9e3
RD		 3472 dseg->lkey = cpu_to_be32(sg->lkey);
3473 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3474
3475 /*
3476 * Need a barrier here before writing the byte_count field to
3477 * make sure that all the data is visible before the
3478 * byte_count field is set. Otherwise, if the segment begins
3479 * a new cacheline, the HCA prefetcher could grab the 64-byte
3480 * chunk and get a valid (!= * 0xffffffff) byte count but
3481 * stale data, and end up sending the wrong data.
3482 */
3483 wmb();
3484
3485 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3486}
3487
2242fa4f
RD		 3488static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3489{
3490 dseg->byte_count = cpu_to_be32(sg->length);
3491 dseg->lkey = cpu_to_be32(sg->lkey);
3492 dseg->addr = cpu_to_be64(sg->addr);
3493}
3494
e622f2f4 3495static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 3496 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 3497 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3498{
e622f2f4 3499 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3500
417608c2
EC		 3501 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3502 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3503
3504 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3505 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3506 return -EINVAL;
3507
e622f2f4 3508 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3509
e622f2f4 3510 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3511 *lso_seg_len = halign;
3512 return 0;
3513}
3514
95d04f07
RD		 3515static __be32 send_ieth(struct ib_send_wr *wr)
3516{
3517 switch (wr->opcode) {
3518 case IB_WR_SEND_WITH_IMM:
3519 case IB_WR_RDMA_WRITE_WITH_IMM:
3520 return wr->ex.imm_data;
3521
3522 case IB_WR_SEND_WITH_INV:
3523 return cpu_to_be32(wr->ex.invalidate_rkey);
3524
3525 default:
3526 return 0;
3527 }
3528}
3529
1ffeb2eb
JM		 3530static void add_zero_len_inline(void *wqe)
3531{
3532 struct mlx4_wqe_inline_seg *inl = wqe;
3533 memset(wqe, 0, 16);
3534 inl->byte_count = cpu_to_be32(1 << 31);
3535}
3536
225c7b1f
RD		 3537int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3538 struct ib_send_wr **bad_wr)
3539{
3540 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3541 void *wqe;
3542 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3543 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3544 unsigned long flags;
3545 int nreq;
3546 int err = 0;
ea54b10c
JM		 3547 unsigned ind;
3548 int uninitialized_var(stamp);
3549 int uninitialized_var(size);
a3d8e159 3550 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 3551 __be32 dummy;
3552 __be32 *lso_wqe;
3553 __be32 uninitialized_var(lso_hdr_sz);
417608c2 3554 __be32 blh;
225c7b1f 3555 int i;
35f05dab 3556 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3557
e1b866c6
MS		 3558 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3559 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3560
3561 if (sqp->roce_v2_gsi) {
3562 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3563 enum ib_gid_type gid_type;
e1b866c6
MS		 3564 union ib_gid gid;
3565
a748d60d
TB		 3566 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3567 ah->av.ib.gid_index,
3568 &gid, &gid_type))
3569 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3570 to_mqp(sqp->roce_v2_gsi) : qp;
3571 else
e1b866c6
MS		 3572 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3573 ah->av.ib.gid_index);
e1b866c6
MS		 3574 }
3575 }
3576
96db0e03 3577 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 3578 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3579 err = -EIO;
3580 *bad_wr = wr;
3581 nreq = 0;
3582 goto out;
3583 }
225c7b1f 3584
ea54b10c 3585 ind = qp->sq_next_wqe;
225c7b1f
RD		 3586
3587 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3588 lso_wqe = &dummy;
417608c2 3589 blh = 0;
0fd7e1d8 3590
225c7b1f
RD		 3591 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3592 err = -ENOMEM;
3593 *bad_wr = wr;
3594 goto out;
3595 }
3596
3597 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3598 err = -EINVAL;
3599 *bad_wr = wr;
3600 goto out;
3601 }
3602
0e6e7416 3603 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3604 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3605
3606 ctrl->srcrb_flags =
3607 (wr->send_flags & IB_SEND_SIGNALED ?
3608 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3609 (wr->send_flags & IB_SEND_SOLICITED ?
3610 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3611 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3612 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3613 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3614 qp->sq_signal_bits;
3615
95d04f07 3616 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3617
3618 wqe += sizeof *ctrl;
3619 size = sizeof *ctrl / 16;
3620
1ffeb2eb
JM		 3621 switch (qp->mlx4_ib_qp_type) {
3622 case MLX4_IB_QPT_RC:
3623 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3624 switch (wr->opcode) {
3625 case IB_WR_ATOMIC_CMP_AND_SWP:
3626 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3627 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3628 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3629 atomic_wr(wr)->rkey);
225c7b1f
RD		 3630 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3631
e622f2f4 3632 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3633 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3634
225c7b1f
RD		 3635 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3636 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3637
3638 break;
3639
3640 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3641 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3642 atomic_wr(wr)->rkey);
6fa8f719
VS		 3643 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3644
e622f2f4 3645 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3646 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3647
3648 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3649 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3650
3651 break;
3652
3653 case IB_WR_RDMA_READ:
3654 case IB_WR_RDMA_WRITE:
3655 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3656 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3657 rdma_wr(wr)->rkey);
225c7b1f
RD		 3658 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3659 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3660 break;
95d04f07
RD		 3661
3662 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3663 ctrl->srcrb_flags |=
3664 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3665 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3666 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3667 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3668 break;
3669
1b2cd0fc
SG		 3670 case IB_WR_REG_MR:
3671 ctrl->srcrb_flags |=
3672 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3673 set_reg_seg(wqe, reg_wr(wr));
3674 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3675 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3676 break;
3677
225c7b1f
RD		 3678 default:
3679 /* No extra segments required for sends */
3680 break;
3681 }
3682 break;
3683
1ffeb2eb 3684 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3685 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3686 ctrl, &seglen);
1ffeb2eb
JM		 3687 if (unlikely(err)) {
3688 *bad_wr = wr;
3689 goto out;
3690 }
3691 wqe += seglen;
3692 size += seglen / 16;
3693 break;
3694 case MLX4_IB_QPT_TUN_SMI:
3695 case MLX4_IB_QPT_TUN_GSI:
3696 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3697 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3698 /* set the forced-loopback bit in the data seg av */
3699 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3700 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3701 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3702 break;
3703 case MLX4_IB_QPT_UD:
e622f2f4 3704 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3705 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3706 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3707
3708 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3709 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3710 &lso_hdr_sz, &blh);
b832be1e
EC		 3711 if (unlikely(err)) {
3712 *bad_wr = wr;
3713 goto out;
3714 }
0fd7e1d8 3715 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3716 wqe += seglen;
3717 size += seglen / 16;
3718 }
225c7b1f
RD		 3719 break;
3720
1ffeb2eb 3721 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3722 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3723 ctrl, &seglen);
1ffeb2eb
JM		 3724 if (unlikely(err)) {
3725 *bad_wr = wr;
3726 goto out;
3727 }
3728 wqe += seglen;
3729 size += seglen / 16;
3730 /* to start tunnel header on a cache-line boundary */
3731 add_zero_len_inline(wqe);
3732 wqe += 16;
3733 size++;
e622f2f4 3734 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3735 wqe += seglen;
3736 size += seglen / 16;
3737 break;
3738 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3739 case MLX4_IB_QPT_PROXY_GSI:
3740 /* If we are tunneling special qps, this is a UD qp.
3741 * In this case we first add a UD segment targeting
3742 * the tunnel qp, and then add a header with address
3743 * information */
e622f2f4
CH		 3744 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3745 ud_wr(wr),
97982f5a 3746 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3747 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3748 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3749 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3750 wqe += seglen;
3751 size += seglen / 16;
3752 break;
3753
3754 case MLX4_IB_QPT_SMI:
3755 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3756 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3757 &seglen);
f438000f 3758 if (unlikely(err)) {
225c7b1f
RD		 3759 *bad_wr = wr;
3760 goto out;
3761 }
f438000f
RD		 3762 wqe += seglen;
3763 size += seglen / 16;
225c7b1f
RD		 3764 break;
3765
3766 default:
3767 break;
3768 }
3769
6e694ea3
JM		 3770 /*
3771 * Write data segments in reverse order, so as to
3772 * overwrite cacheline stamp last within each
3773 * cacheline. This avoids issues with WQE
3774 * prefetching.
3775 */
225c7b1f 3776
6e694ea3
JM		 3777 dseg = wqe;
3778 dseg += wr->num_sge - 1;
3779 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3780
3781 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3782 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3783 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3784 qp->mlx4_ib_qp_type &
3785 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3786 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3787 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3788 }
3789
6e694ea3
JM		 3790 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3791 set_data_seg(dseg, wr->sg_list + i);
3792
0fd7e1d8
RD		 3793 /*
3794 * Possibly overwrite stamping in cacheline with LSO
3795 * segment only after making sure all data segments
3796 * are written.
3797 */
3798 wmb();
3799 *lso_wqe = lso_hdr_sz;
3800
224e92e0
BB		 3801 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3802 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3803
3804 /*
3805 * Make sure descriptor is fully written before
3806 * setting ownership bit (because HW can start
3807 * executing as soon as we do).
3808 */
3809 wmb();
3810
59b0ed12 3811 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3812 *bad_wr = wr;
225c7b1f
RD		 3813 err = -EINVAL;
3814 goto out;
3815 }
3816
3817 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3818 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3819
ea54b10c
JM		 3820 stamp = ind + qp->sq_spare_wqes;
3821 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3822
0e6e7416
RD		 3823 /*
3824 * We can improve latency by not stamping the last
3825 * send queue WQE until after ringing the doorbell, so
3826 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3827 *
3828 * Same optimization applies to padding with NOP wqe
3829 * in case of WQE shrinking (used to prevent wrap-around
3830 * in the middle of WR).
0e6e7416 3831 */
ea54b10c
JM		 3832 if (wr->next) {
3833 stamp_send_wqe(qp, stamp, size * 16);
3834 ind = pad_wraparound(qp, ind);
3835 }
225c7b1f
RD		 3836 }
3837
3838out:
3839 if (likely(nreq)) {
3840 qp->sq.head += nreq;
3841
3842 /*
3843 * Make sure that descriptors are written before
3844 * doorbell record.
3845 */
3846 wmb();
3847
3848 writel(qp->doorbell_qpn,
3849 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3850
3851 /*
3852 * Make sure doorbells don't leak out of SQ spinlock
3853 * and reach the HCA out of order.
3854 */
3855 mmiowb();
0e6e7416 3856
ea54b10c
JM		 3857 stamp_send_wqe(qp, stamp, size * 16);
3858
3859 ind = pad_wraparound(qp, ind);
3860 qp->sq_next_wqe = ind;
225c7b1f
RD		 3861 }
3862
96db0e03 3863 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3864
3865 return err;
3866}
3867
3868int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3869 struct ib_recv_wr **bad_wr)
3870{
3871 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3872 struct mlx4_wqe_data_seg *scat;
3873 unsigned long flags;
3874 int err = 0;
3875 int nreq;
3876 int ind;
1ffeb2eb 3877 int max_gs;
225c7b1f 3878 int i;
35f05dab 3879 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3880
1ffeb2eb 3881 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3882 spin_lock_irqsave(&qp->rq.lock, flags);
3883
35f05dab
YH		 3884 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3885 err = -EIO;
3886 *bad_wr = wr;
3887 nreq = 0;
3888 goto out;
3889 }
3890
0e6e7416 3891 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3892
3893 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3894 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3895 err = -ENOMEM;
3896 *bad_wr = wr;
3897 goto out;
3898 }
3899
3900 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3901 err = -EINVAL;
3902 *bad_wr = wr;
3903 goto out;
3904 }
3905
3906 scat = get_recv_wqe(qp, ind);
3907
1ffeb2eb
JM		 3908 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3909 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3910 ib_dma_sync_single_for_device(ibqp->device,
3911 qp->sqp_proxy_rcv[ind].map,
3912 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3913 DMA_FROM_DEVICE);
3914 scat->byte_count =
3915 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3916 /* use dma lkey from upper layer entry */
3917 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3918 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3919 scat++;
3920 max_gs--;
3921 }
3922
2242fa4f
RD		 3923 for (i = 0; i < wr->num_sge; ++i)
3924 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3925
1ffeb2eb 3926 if (i < max_gs) {
225c7b1f
RD		 3927 scat[i].byte_count = 0;
3928 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3929 scat[i].addr = 0;
3930 }
3931
3932 qp->rq.wrid[ind] = wr->wr_id;
3933
0e6e7416 3934 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3935 }
3936
3937out:
3938 if (likely(nreq)) {
3939 qp->rq.head += nreq;
3940
3941 /*
3942 * Make sure that descriptors are written before
3943 * doorbell record.
3944 */
3945 wmb();
3946
3947 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3948 }
3949
3950 spin_unlock_irqrestore(&qp->rq.lock, flags);
3951
3952 return err;
3953}
6a775e2b
JM		 3954
3955static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3956{
3957 switch (mlx4_state) {
3958 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3959 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3960 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3961 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3962 case MLX4_QP_STATE_SQ_DRAINING:
3963 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3964 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3965 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3966 default: return -1;
3967 }
3968}
3969
3970static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3971{
3972 switch (mlx4_mig_state) {
3973 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3974 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3975 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3976 default: return -1;
3977 }
3978}
3979
3980static int to_ib_qp_access_flags(int mlx4_flags)
3981{
3982 int ib_flags = 0;
3983
3984 if (mlx4_flags & MLX4_QP_BIT_RRE)
3985 ib_flags |= IB_ACCESS_REMOTE_READ;
3986 if (mlx4_flags & MLX4_QP_BIT_RWE)
3987 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3988 if (mlx4_flags & MLX4_QP_BIT_RAE)
3989 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3990
3991 return ib_flags;
3992}
3993
71d53ab4 3994static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3995 struct rdma_ah_attr *ah_attr,
71d53ab4 3996 struct mlx4_qp_path *path)
6a775e2b 3997{
4c3eb3ca 3998 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3999 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 4000
d8966fcd 4001 memset(ah_attr, 0, sizeof(*ah_attr));
44c58487 4002 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
d8966fcd 4003 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b
JM		 4004 return;
4005
44c58487 4006 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 4007 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4008 ((path->sched_queue & 4) << 1));
4c3eb3ca 4009 else
d8966fcd 4010 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 4011 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 4012
d8966fcd
DC		 4013 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4014 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4015 rdma_ah_set_static_rate(ah_attr,
4016 path->static_rate ? path->static_rate - 5 : 0);
4017 if (path->grh_mylmc & (1 << 7)) {
4018 rdma_ah_set_grh(ah_attr, NULL,
4019 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4020 path->mgid_index,
4021 path->hop_limit,
4022 (be32_to_cpu(path->tclass_flowlabel)
4023 >> 20) & 0xff);
4024 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 4025 }
4026}
4027
4028int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4029 struct ib_qp_init_attr *qp_init_attr)
4030{
4031 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4032 struct mlx4_ib_qp *qp = to_mqp(ibqp);
4033 struct mlx4_qp_context context;
4034 int mlx4_state;
0df67030
DB		 4035 int err = 0;
4036
3078f5f1
GL		 4037 if (ibqp->rwq_ind_tbl)
4038 return -EOPNOTSUPP;
4039
0df67030 4040 mutex_lock(&qp->mutex);
6a775e2b
JM		 4041
4042 if (qp->state == IB_QPS_RESET) {
4043 qp_attr->qp_state = IB_QPS_RESET;
4044 goto done;
4045 }
4046
4047 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 4048 if (err) {
4049 err = -EINVAL;
4050 goto out;
4051 }
6a775e2b
JM		 4052
4053 mlx4_state = be32_to_cpu(context.flags) >> 28;
4054
0df67030
DB		 4055 qp->state = to_ib_qp_state(mlx4_state);
4056 qp_attr->qp_state = qp->state;
6a775e2b
JM		 4057 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4058 qp_attr->path_mig_state =
4059 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4060 qp_attr->qkey = be32_to_cpu(context.qkey);
4061 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4062 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4063 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4064 qp_attr->qp_access_flags =
4065 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4066
4067 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 4068 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4069 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4070 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4071 qp_attr->alt_port_num =
4072 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4073 }
4074
4075 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4076 if (qp_attr->qp_state == IB_QPS_INIT)
4077 qp_attr->port_num = qp->port;
4078 else
4079 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4080
4081 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4082 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4083
4084 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4085
4086 qp_attr->max_dest_rd_atomic =
4087 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4088 qp_attr->min_rnr_timer =
4089 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4090 qp_attr->timeout = context.pri_path.ackto >> 3;
4091 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4092 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4093 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4094
4095done:
4096 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4097 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4098 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4099
6a775e2b 4100 if (!ibqp->uobject) {
7f5eb9bb
RD		 4101 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4102 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4103 } else {
4104 qp_attr->cap.max_send_wr = 0;
4105 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4106 }
4107
7f5eb9bb
RD		 4108 /*
4109 * We don't support inline sends for kernel QPs (yet), and we
4110 * don't know what userspace's value should be.
4111 */
4112 qp_attr->cap.max_inline_data = 0;
4113
4114 qp_init_attr->cap = qp_attr->cap;
4115
521e575b
RL		 4116 qp_init_attr->create_flags = 0;
4117 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4118 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4119
4120 if (qp->flags & MLX4_IB_QP_LSO)
4121 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4122
c1c98501
MB		 4123 if (qp->flags & MLX4_IB_QP_NETIF)
4124 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4125
46db567d
DB		 4126 qp_init_attr->sq_sig_type =
4127 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4128 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4129
0df67030
DB		 4130out:
4131 mutex_unlock(&qp->mutex);
4132 return err;
6a775e2b
JM		 4133}
4134
400b1ebc
GL		 4135struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4136 struct ib_wq_init_attr *init_attr,
4137 struct ib_udata *udata)
4138{
4139 struct mlx4_ib_dev *dev;
4140 struct ib_qp_init_attr ib_qp_init_attr;
4141 struct mlx4_ib_qp *qp;
4142 struct mlx4_ib_create_wq ucmd;
4143 int err, required_cmd_sz;
4144
4145 if (!(udata && pd->uobject))
4146 return ERR_PTR(-EINVAL);
4147
078b3573
GL		 4148 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4149 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4150 if (udata->inlen < required_cmd_sz) {
4151 pr_debug("invalid inlen\n");
4152 return ERR_PTR(-EINVAL);
4153 }
4154
4155 if (udata->inlen > sizeof(ucmd) &&
4156 !ib_is_udata_cleared(udata, sizeof(ucmd),
4157 udata->inlen - sizeof(ucmd))) {
4158 pr_debug("inlen is not supported\n");
4159 return ERR_PTR(-EOPNOTSUPP);
4160 }
4161
4162 if (udata->outlen)
4163 return ERR_PTR(-EOPNOTSUPP);
4164
4165 dev = to_mdev(pd->device);
4166
4167 if (init_attr->wq_type != IB_WQT_RQ) {
4168 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4169 return ERR_PTR(-EOPNOTSUPP);
4170 }
4171
4172 if (init_attr->create_flags) {
4173 pr_debug("unsupported create_flags %u\n",
4174 init_attr->create_flags);
4175 return ERR_PTR(-EOPNOTSUPP);
4176 }
4177
4178 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4179 if (!qp)
4180 return ERR_PTR(-ENOMEM);
4181
4182 qp->pri.vid = 0xFFFF;
4183 qp->alt.vid = 0xFFFF;
4184
4185 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4186 ib_qp_init_attr.qp_context = init_attr->wq_context;
4187 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4188 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4189 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4190 ib_qp_init_attr.recv_cq = init_attr->cq;
4191 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4192
4193 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4194 udata, 0, &qp);
4195 if (err) {
4196 kfree(qp);
4197 return ERR_PTR(err);
4198 }
4199
4200 qp->ibwq.event_handler = init_attr->event_handler;
4201 qp->ibwq.wq_num = qp->mqp.qpn;
4202 qp->ibwq.state = IB_WQS_RESET;
4203
4204 return &qp->ibwq;
4205}
4206
4207static int ib_wq2qp_state(enum ib_wq_state state)
4208{
4209 switch (state) {
4210 case IB_WQS_RESET:
4211 return IB_QPS_RESET;
4212 case IB_WQS_RDY:
4213 return IB_QPS_RTR;
4214 default:
4215 return IB_QPS_ERR;
4216 }
4217}
4218
4219static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4220{
4221 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4222 enum ib_qp_state qp_cur_state;
4223 enum ib_qp_state qp_new_state;
4224 int attr_mask;
4225 int err;
4226
4227 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4228 * the WQ logic state.
4229 */
4230 qp_cur_state = qp->state;
4231 qp_new_state = ib_wq2qp_state(new_state);
4232
4233 if (ib_wq2qp_state(new_state) == qp_cur_state)
4234 return 0;
4235
4236 if (new_state == IB_WQS_RDY) {
4237 struct ib_qp_attr attr = {};
4238
4239 attr.port_num = qp->port;
4240 attr_mask = IB_QP_PORT;
4241
4242 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4243 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4244 if (err) {
4245 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4246 ibwq->wq_num);
4247 return err;
4248 }
4249
4250 qp_cur_state = IB_QPS_INIT;
4251 }
4252
4253 attr_mask = 0;
4254 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4255 qp_cur_state, qp_new_state);
4256
4257 if (err && (qp_cur_state == IB_QPS_INIT)) {
4258 qp_new_state = IB_QPS_RESET;
4259 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4260 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4261 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4262 ibwq->wq_num);
4263 qp_new_state = IB_QPS_INIT;
4264 }
4265 }
4266
4267 qp->state = qp_new_state;
4268
4269 return err;
4270}
4271
4272int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4273 u32 wq_attr_mask, struct ib_udata *udata)
4274{
4275 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4276 struct mlx4_ib_modify_wq ucmd = {};
4277 size_t required_cmd_sz;
4278 enum ib_wq_state cur_state, new_state;
4279 int err = 0;
4280
4281 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4282 sizeof(ucmd.reserved);
4283 if (udata->inlen < required_cmd_sz)
4284 return -EINVAL;
4285
4286 if (udata->inlen > sizeof(ucmd) &&
4287 !ib_is_udata_cleared(udata, sizeof(ucmd),
4288 udata->inlen - sizeof(ucmd)))
4289 return -EOPNOTSUPP;
4290
4291 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4292 return -EFAULT;
4293
4294 if (ucmd.comp_mask || ucmd.reserved)
4295 return -EOPNOTSUPP;
4296
4297 if (wq_attr_mask & IB_WQ_FLAGS)
4298 return -EOPNOTSUPP;
4299
4300 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4301 ibwq->state;
4302 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4303
4304 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4305 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4306 return -EINVAL;
4307
4308 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4309 return -EINVAL;
4310
4311 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4312 return -EINVAL;
4313
3078f5f1
GL		 4314 /* Need to protect against the parent RSS which also may modify WQ
4315 * state.
4316 */
4317 mutex_lock(&qp->mutex);
4318
400b1ebc
GL		 4319 /* Can update HW state only if a RSS QP has already associated to this
4320 * WQ, so we can apply its port on the WQ.
4321 */
4322 if (qp->rss_usecnt)
4323 err = _mlx4_ib_modify_wq(ibwq, new_state);
4324
4325 if (!err)
4326 ibwq->state = new_state;
4327
3078f5f1
GL		 4328 mutex_unlock(&qp->mutex);
4329
400b1ebc
GL		 4330 return err;
4331}
4332
4333int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4334{
4335 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4336 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4337
4338 if (qp->counter_index)
4339 mlx4_ib_free_qp_counter(dev, qp);
4340
4341 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4342
4343 kfree(qp);
4344
4345 return 0;
4346}
b8d46ca0
GL		 4347
4348struct ib_rwq_ind_table
4349*mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4350 struct ib_rwq_ind_table_init_attr *init_attr,
4351 struct ib_udata *udata)
4352{
4353 struct ib_rwq_ind_table *rwq_ind_table;
4354 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4355 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4356 unsigned int base_wqn;
4357 size_t min_resp_len;
4358 int i;
4359 int err;
4360
4361 if (udata->inlen > 0 &&
4362 !ib_is_udata_cleared(udata, 0,
4363 udata->inlen))
4364 return ERR_PTR(-EOPNOTSUPP);
4365
4366 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4367 if (udata->outlen && udata->outlen < min_resp_len)
4368 return ERR_PTR(-EINVAL);
4369
4370 if (ind_tbl_size >
4371 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4372 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4373 ind_tbl_size,
4374 device->attrs.rss_caps.max_rwq_indirection_table_size);
4375 return ERR_PTR(-EINVAL);
4376 }
4377
4378 base_wqn = init_attr->ind_tbl[0]->wq_num;
4379
4380 if (base_wqn % ind_tbl_size) {
4381 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4382 base_wqn);
4383 return ERR_PTR(-EINVAL);
4384 }
4385
4386 for (i = 1; i < ind_tbl_size; i++) {
4387 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4388 pr_debug("indirection table's WQNs aren't consecutive\n");
4389 return ERR_PTR(-EINVAL);
4390 }
4391 }
4392
4393 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4394 if (!rwq_ind_table)
4395 return ERR_PTR(-ENOMEM);
4396
4397 if (udata->outlen) {
4398 resp.response_length = offsetof(typeof(resp), response_length) +
4399 sizeof(resp.response_length);
4400 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4401 if (err)
4402 goto err;
4403 }
4404
4405 return rwq_ind_table;
4406
4407err:
4408 kfree(rwq_ind_table);
4409 return ERR_PTR(err);
4410}
4411
4412int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4413{
4414 kfree(ib_rwq_ind_tbl);
4415 return 0;
4416}
Linux 6.x block layer and io_uring tree(s)