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RDMA/restrack: Resource-tracker should not use uobject pointers
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
225c7b1f 44
2f48485d 45#include <linux/mlx4/driver.h>
225c7b1f
RD		 46#include <linux/mlx4/qp.h>
47
48#include "mlx4_ib.h"
9ce28a20 49#include <rdma/mlx4-abi.h>
225c7b1f 50
35f05dab
YH		 51static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
3078f5f1 55static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
35f05dab 56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
79struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 86 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 117};
118
400b1ebc
GL		 119enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122};
123
225c7b1f
RD		 124static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125{
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127}
128
1ffeb2eb
JM		 129static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130{
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
47605df9
JM		 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 137}
138
225c7b1f
RD		 139static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140{
47605df9
JM		 141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
e1b866c6
MS		 160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 164}
165
1ffeb2eb 166/* used for INIT/CLOSE port logic */
225c7b1f
RD		 167static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168{
47605df9
JM		 169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
225c7b1f
RD		 188}
189
190static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191{
1c69fc2a 192 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 193}
194
195static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198}
199
200static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201{
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203}
204
0e6e7416
RD		 205/*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
f95ccffc
JM		 207 * first four bytes of every 64 byte chunk with 0xffffffff, except for
208 * the very first chunk of the WQE.
0e6e7416 209 */
f95ccffc 210static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
0e6e7416 211{
d2ae16d5 212 __be32 *wqe;
0e6e7416 213 int i;
ea54b10c 214 int s;
ea54b10c 215 void *buf;
ea54b10c 216 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 217
f95ccffc
JM		 218 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
219 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
220 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
221 for (i = 64; i < s; i += 64) {
222 wqe = buf + i;
223 *wqe = cpu_to_be32(0xffffffff);
ea54b10c 224 }
0e6e7416
RD		 225}
226
225c7b1f
RD		 227static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
228{
229 struct ib_event event;
230 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
231
232 if (type == MLX4_EVENT_TYPE_PATH_MIG)
233 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
234
235 if (ibqp->event_handler) {
236 event.device = ibqp->device;
237 event.element.qp = ibqp;
238 switch (type) {
239 case MLX4_EVENT_TYPE_PATH_MIG:
240 event.event = IB_EVENT_PATH_MIG;
241 break;
242 case MLX4_EVENT_TYPE_COMM_EST:
243 event.event = IB_EVENT_COMM_EST;
244 break;
245 case MLX4_EVENT_TYPE_SQ_DRAINED:
246 event.event = IB_EVENT_SQ_DRAINED;
247 break;
248 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
249 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
250 break;
251 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
252 event.event = IB_EVENT_QP_FATAL;
253 break;
254 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
255 event.event = IB_EVENT_PATH_MIG_ERR;
256 break;
257 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
258 event.event = IB_EVENT_QP_REQ_ERR;
259 break;
260 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
261 event.event = IB_EVENT_QP_ACCESS_ERR;
262 break;
263 default:
987c8f8f 264 pr_warn("Unexpected event type %d "
225c7b1f
RD		 265 "on QP %06x\n", type, qp->qpn);
266 return;
267 }
268
269 ibqp->event_handler(&event, ibqp->qp_context);
270 }
271}
272
400b1ebc
GL		 273static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
274{
275 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
276 type, qp->qpn);
277}
278
1ffeb2eb 279static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 280{
281 /*
282 * UD WQEs must have a datagram segment.
283 * RC and UC WQEs might have a remote address segment.
284 * MLX WQEs need two extra inline data segments (for the UD
285 * header and space for the ICRC).
286 */
287 switch (type) {
1ffeb2eb 288 case MLX4_IB_QPT_UD:
225c7b1f 289 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 290 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 291 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 292 case MLX4_IB_QPT_PROXY_SMI_OWNER:
293 case MLX4_IB_QPT_PROXY_SMI:
294 case MLX4_IB_QPT_PROXY_GSI:
295 return sizeof (struct mlx4_wqe_ctrl_seg) +
296 sizeof (struct mlx4_wqe_datagram_seg) + 64;
297 case MLX4_IB_QPT_TUN_SMI_OWNER:
298 case MLX4_IB_QPT_TUN_GSI:
299 return sizeof (struct mlx4_wqe_ctrl_seg) +
300 sizeof (struct mlx4_wqe_datagram_seg);
301
302 case MLX4_IB_QPT_UC:
225c7b1f
RD		 303 return sizeof (struct mlx4_wqe_ctrl_seg) +
304 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 305 case MLX4_IB_QPT_RC:
225c7b1f 306 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 307 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 308 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 309 case MLX4_IB_QPT_SMI:
310 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 311 return sizeof (struct mlx4_wqe_ctrl_seg) +
312 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 313 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
314 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 315 sizeof (struct mlx4_wqe_inline_seg),
316 sizeof (struct mlx4_wqe_data_seg)) +
317 ALIGN(4 +
318 sizeof (struct mlx4_wqe_inline_seg),
319 sizeof (struct mlx4_wqe_data_seg));
320 default:
321 return sizeof (struct mlx4_wqe_ctrl_seg);
322 }
323}
324
2446304d 325static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
ea30b966
MG		 326 int is_user, int has_rq, struct mlx4_ib_qp *qp,
327 u32 inl_recv_sz)
225c7b1f 328{
2446304d 329 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 330 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
331 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 332 return -EINVAL;
333
0a1405da 334 if (!has_rq) {
ea30b966 335 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 336 return -EINVAL;
2446304d 337
0e6e7416 338 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 339 } else {
ea30b966
MG		 340 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
341 sizeof(struct mlx4_wqe_data_seg);
342 u32 wqe_size;
343
a4cd7ed8 344 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 345 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
346 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 347 return -EINVAL;
348
0e6e7416 349 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 350 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 351 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
352 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 353 }
2446304d 354
fc2d0044
SG		 355 /* leave userspace return values as they were, so as not to break ABI */
356 if (is_user) {
357 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
358 cap->max_recv_sge = qp->rq.max_gs;
359 } else {
360 cap->max_recv_wr = qp->rq.max_post =
361 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
362 cap->max_recv_sge = min(qp->rq.max_gs,
363 min(dev->dev->caps.max_sq_sg,
364 dev->dev->caps.max_rq_sg));
365 }
2446304d
EC		 366
367 return 0;
368}
369
370static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
f95ccffc 371 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 372{
ea54b10c
JM		 373 int s;
374
2446304d 375 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 376 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
377 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 378 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 379 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
380 return -EINVAL;
381
382 /*
383 * For MLX transport we need 2 extra S/G entries:
384 * one for the header and one for the checksum at the end
385 */
1ffeb2eb
JM		 386 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
387 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 388 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
389 return -EINVAL;
390
ea54b10c
JM		 391 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
392 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 393 send_wqe_overhead(type, qp->flags);
225c7b1f 394
cd155c1c
RD		 395 if (s > dev->dev->caps.max_sq_desc_sz)
396 return -EINVAL;
397
f95ccffc
JM		 398 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
399
0e6e7416 400 /*
f95ccffc
JM		 401 * We need to leave 2 KB + 1 WR of headroom in the SQ to
402 * allow HW to prefetch.
0e6e7416 403 */
350b4c8a 404 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
f95ccffc
JM		 405 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
406 qp->sq_spare_wqes);
407
408 qp->sq.max_gs =
409 (min(dev->dev->caps.max_sq_desc_sz,
410 (1 << qp->sq.wqe_shift)) -
411 send_wqe_overhead(type, qp->flags)) /
b832be1e 412 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 413
414 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
415 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 416 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
417 qp->rq.offset = 0;
0e6e7416 418 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 419 } else {
0e6e7416 420 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 421 qp->sq.offset = 0;
422 }
423
ea54b10c 424 cap->max_send_wr = qp->sq.max_post =
f95ccffc 425 qp->sq.wqe_cnt - qp->sq_spare_wqes;
cd155c1c
RD		 426 cap->max_send_sge = min(qp->sq.max_gs,
427 min(dev->dev->caps.max_sq_sg,
428 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 429 /* We don't support inline sends for kernel QPs (yet) */
430 cap->max_inline_data = 0;
225c7b1f
RD		 431
432 return 0;
433}
434
83904132
JM		 435static int set_user_sq_size(struct mlx4_ib_dev *dev,
436 struct mlx4_ib_qp *qp,
2446304d
EC		 437 struct mlx4_ib_create_qp *ucmd)
438{
83904132
JM		 439 /* Sanity check SQ size before proceeding */
440 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
441 ucmd->log_sq_stride >
442 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
443 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
444 return -EINVAL;
445
0e6e7416 446 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 447 qp->sq.wqe_shift = ucmd->log_sq_stride;
448
0e6e7416
RD		 449 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
450 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 451
452 return 0;
453}
454
1ffeb2eb
JM		 455static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
456{
457 int i;
458
459 qp->sqp_proxy_rcv =
6da2ec56
KC		 460 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
461 GFP_KERNEL);
1ffeb2eb
JM		 462 if (!qp->sqp_proxy_rcv)
463 return -ENOMEM;
464 for (i = 0; i < qp->rq.wqe_cnt; i++) {
465 qp->sqp_proxy_rcv[i].addr =
466 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
467 GFP_KERNEL);
468 if (!qp->sqp_proxy_rcv[i].addr)
469 goto err;
470 qp->sqp_proxy_rcv[i].map =
471 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
472 sizeof (struct mlx4_ib_proxy_sqp_hdr),
473 DMA_FROM_DEVICE);
cc47d369
SO		 474 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
475 kfree(qp->sqp_proxy_rcv[i].addr);
476 goto err;
477 }
1ffeb2eb
JM		 478 }
479 return 0;
480
481err:
482 while (i > 0) {
483 --i;
484 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
485 sizeof (struct mlx4_ib_proxy_sqp_hdr),
486 DMA_FROM_DEVICE);
487 kfree(qp->sqp_proxy_rcv[i].addr);
488 }
489 kfree(qp->sqp_proxy_rcv);
490 qp->sqp_proxy_rcv = NULL;
491 return -ENOMEM;
492}
493
494static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
495{
496 int i;
497
498 for (i = 0; i < qp->rq.wqe_cnt; i++) {
499 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
500 sizeof (struct mlx4_ib_proxy_sqp_hdr),
501 DMA_FROM_DEVICE);
502 kfree(qp->sqp_proxy_rcv[i].addr);
503 }
504 kfree(qp->sqp_proxy_rcv);
505}
506
0a1405da
SH		 507static int qp_has_rq(struct ib_qp_init_attr *attr)
508{
509 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
510 return 0;
511
512 return !attr->srq;
513}
514
99ec41d0
JM		 515static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
516{
517 int i;
518 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 519 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
520 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 521 }
522 return 0;
523}
524
7b59f0f9
EBE		 525static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
526 struct mlx4_ib_qp *qp)
527{
528 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
529 mlx4_counter_free(dev->dev, qp->counter_index->index);
530 list_del(&qp->counter_index->list);
531 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
532
533 kfree(qp->counter_index);
534 qp->counter_index = NULL;
535}
536
3078f5f1
GL		 537static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
538 struct ib_qp_init_attr *init_attr,
539 struct mlx4_ib_create_qp_rss *ucmd)
540{
541 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
542 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
543
544 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
545 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
546 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
547 MLX4_EN_RSS_KEY_SIZE);
548 } else {
549 pr_debug("RX Hash function is not supported\n");
550 return (-EOPNOTSUPP);
551 }
552
4d02ebd9
GL		 553 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
554 MLX4_IB_RX_HASH_DST_IPV4 |
555 MLX4_IB_RX_HASH_SRC_IPV6 |
556 MLX4_IB_RX_HASH_DST_IPV6 |
557 MLX4_IB_RX_HASH_SRC_PORT_TCP |
558 MLX4_IB_RX_HASH_DST_PORT_TCP |
559 MLX4_IB_RX_HASH_SRC_PORT_UDP |
4f9ca2d8
LR		 560 MLX4_IB_RX_HASH_DST_PORT_UDP |
561 MLX4_IB_RX_HASH_INNER)) {
4d02ebd9
GL		 562 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
563 ucmd->rx_hash_fields_mask);
564 return (-EOPNOTSUPP);
565 }
566
3078f5f1
GL		 567 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
568 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
569 rss_ctx->flags = MLX4_RSS_IPV4;
570 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
571 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
572 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
573 return (-EOPNOTSUPP);
574 }
575
576 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
577 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
578 rss_ctx->flags |= MLX4_RSS_IPV6;
579 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
580 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
581 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
582 return (-EOPNOTSUPP);
583 }
584
585 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
586 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
587 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
588 pr_debug("RX Hash fields_mask for UDP is not supported\n");
589 return (-EOPNOTSUPP);
590 }
591
4d02ebd9 592 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 593 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 594 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 595 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 596 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 597 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
598 return (-EOPNOTSUPP);
599 }
600 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
601 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
602 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
603 return (-EOPNOTSUPP);
604 }
605
606 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
607 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 608 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 609 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 610 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 611 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 612 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 613 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
614 return (-EOPNOTSUPP);
615 }
3078f5f1
GL		 616 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
617 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
618 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
619 return (-EOPNOTSUPP);
620 }
621
07d84f7b
GL		 622 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
623 if (dev->dev->caps.tunnel_offload_mode ==
624 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
625 /*
626 * Hash according to inner headers if exist, otherwise
627 * according to outer headers.
628 */
629 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
630 } else {
631 pr_debug("RSS Hash for inner headers isn't supported\n");
632 return (-EOPNOTSUPP);
633 }
634 }
635
3078f5f1
GL		 636 return 0;
637}
638
d7c0557a 639static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 640 struct ib_qp_init_attr *init_attr,
641 struct mlx4_ib_create_qp_rss *ucmd,
642 struct mlx4_ib_qp *qp)
643{
644 int qpn;
645 int err;
646
647 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
648
649 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
650 if (err)
651 return err;
652
653 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
654 if (err)
655 goto err_qpn;
656
657 mutex_init(&qp->mutex);
658
659 INIT_LIST_HEAD(&qp->gid_list);
660 INIT_LIST_HEAD(&qp->steering_rules);
661
c3f1ee29 662 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 663 qp->state = IB_QPS_RESET;
664
665 /* Set dummy send resources to be compatible with HV and PRM */
666 qp->sq_no_prefetch = 1;
667 qp->sq.wqe_cnt = 1;
668 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
669 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
670 qp->mtt = (to_mqp(
671 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
672
673 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
674 if (!qp->rss_ctx) {
675 err = -ENOMEM;
676 goto err_qp_alloc;
677 }
678
679 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
680 if (err)
681 goto err;
682
683 return 0;
684
685err:
686 kfree(qp->rss_ctx);
687
688err_qp_alloc:
689 mlx4_qp_remove(dev->dev, &qp->mqp);
690 mlx4_qp_free(dev->dev, &qp->mqp);
691
692err_qpn:
693 mlx4_qp_release_range(dev->dev, qpn, 1);
694 return err;
695}
696
697static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
698 struct ib_qp_init_attr *init_attr,
699 struct ib_udata *udata)
700{
701 struct mlx4_ib_qp *qp;
702 struct mlx4_ib_create_qp_rss ucmd = {};
703 size_t required_cmd_sz;
704 int err;
705
706 if (!udata) {
707 pr_debug("RSS QP with NULL udata\n");
708 return ERR_PTR(-EINVAL);
709 }
710
711 if (udata->outlen)
712 return ERR_PTR(-EOPNOTSUPP);
713
714 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
715 sizeof(ucmd.reserved1);
716 if (udata->inlen < required_cmd_sz) {
717 pr_debug("invalid inlen\n");
718 return ERR_PTR(-EINVAL);
719 }
720
721 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
722 pr_debug("copy failed\n");
723 return ERR_PTR(-EFAULT);
724 }
725
f9bfea99
GL		 726 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
727 return ERR_PTR(-EOPNOTSUPP);
728
3078f5f1
GL		 729 if (ucmd.comp_mask || ucmd.reserved1)
730 return ERR_PTR(-EOPNOTSUPP);
731
732 if (udata->inlen > sizeof(ucmd) &&
733 !ib_is_udata_cleared(udata, sizeof(ucmd),
734 udata->inlen - sizeof(ucmd))) {
735 pr_debug("inlen is not supported\n");
736 return ERR_PTR(-EOPNOTSUPP);
737 }
738
739 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
740 pr_debug("RSS QP with unsupported QP type %d\n",
741 init_attr->qp_type);
742 return ERR_PTR(-EOPNOTSUPP);
743 }
744
745 if (init_attr->create_flags) {
746 pr_debug("RSS QP doesn't support create flags\n");
747 return ERR_PTR(-EOPNOTSUPP);
748 }
749
750 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
751 pr_debug("RSS QP with unsupported send attributes\n");
752 return ERR_PTR(-EOPNOTSUPP);
753 }
754
755 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
756 if (!qp)
757 return ERR_PTR(-ENOMEM);
758
759 qp->pri.vid = 0xFFFF;
760 qp->alt.vid = 0xFFFF;
761
d7c0557a 762 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
3078f5f1
GL		 763 if (err) {
764 kfree(qp);
765 return ERR_PTR(err);
766 }
767
768 qp->ibqp.qp_num = qp->mqp.qpn;
769
770 return &qp->ibqp;
771}
772
400b1ebc
GL		 773/*
774 * This function allocates a WQN from a range which is consecutive and aligned
775 * to its size. In case the range is full, then it creates a new range and
776 * allocates WQN from it. The new range will be used for following allocations.
777 */
778static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
779 struct mlx4_ib_qp *qp, int range_size, int *wqn)
780{
781 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
782 struct mlx4_wqn_range *range;
783 int err = 0;
784
785 mutex_lock(&context->wqn_ranges_mutex);
786
787 range = list_first_entry_or_null(&context->wqn_ranges_list,
788 struct mlx4_wqn_range, list);
789
790 if (!range || (range->refcount == range->size) || range->dirty) {
791 range = kzalloc(sizeof(*range), GFP_KERNEL);
792 if (!range) {
793 err = -ENOMEM;
794 goto out;
795 }
796
797 err = mlx4_qp_reserve_range(dev->dev, range_size,
798 range_size, &range->base_wqn, 0,
799 qp->mqp.usage);
800 if (err) {
801 kfree(range);
802 goto out;
803 }
804
805 range->size = range_size;
806 list_add(&range->list, &context->wqn_ranges_list);
807 } else if (range_size != 1) {
808 /*
809 * Requesting a new range (>1) when last range is still open, is
810 * not valid.
811 */
812 err = -EINVAL;
813 goto out;
814 }
815
816 qp->wqn_range = range;
817
818 *wqn = range->base_wqn + range->refcount;
819
820 range->refcount++;
821
822out:
823 mutex_unlock(&context->wqn_ranges_mutex);
824
825 return err;
826}
827
828static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
829 struct mlx4_ib_qp *qp, bool dirty_release)
830{
831 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
832 struct mlx4_wqn_range *range;
833
834 mutex_lock(&context->wqn_ranges_mutex);
835
836 range = qp->wqn_range;
837
838 range->refcount--;
839 if (!range->refcount) {
840 mlx4_qp_release_range(dev->dev, range->base_wqn,
841 range->size);
842 list_del(&range->list);
843 kfree(range);
844 } else if (dirty_release) {
845 /*
846 * A range which one of its WQNs is destroyed, won't be able to be
847 * reused for further WQN allocations.
848 * The next created WQ will allocate a new range.
849 */
850 range->dirty = 1;
851 }
852
853 mutex_unlock(&context->wqn_ranges_mutex);
854}
855
225c7b1f 856static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
400b1ebc 857 enum mlx4_ib_source_type src,
225c7b1f 858 struct ib_qp_init_attr *init_attr,
8900b894
LR		 859 struct ib_udata *udata, int sqpn,
860 struct mlx4_ib_qp **caller_qp)
225c7b1f 861{
a3cdcbfa 862 int qpn;
225c7b1f 863 int err;
b42dde47 864 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 865 struct mlx4_ib_qp *qp;
866 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 867 struct mlx4_ib_cq *mcq;
868 unsigned long flags;
400b1ebc 869 int range_size = 0;
1ffeb2eb
JM		 870
871 /* When tunneling special qps, we use a plain UD qp */
872 if (sqpn) {
873 if (mlx4_is_mfunc(dev->dev) &&
874 (!mlx4_is_master(dev->dev) ||
875 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
876 if (init_attr->qp_type == IB_QPT_GSI)
877 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 878 else {
879 if (mlx4_is_master(dev->dev) ||
880 qp0_enabled_vf(dev->dev, sqpn))
881 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
882 else
883 qp_type = MLX4_IB_QPT_PROXY_SMI;
884 }
1ffeb2eb
JM		 885 }
886 qpn = sqpn;
887 /* add extra sg entry for tunneling */
888 init_attr->cap.max_recv_sge++;
889 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
890 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
891 container_of(init_attr,
892 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
893 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
894 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
895 !mlx4_is_master(dev->dev))
896 return -EINVAL;
897 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
898 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 899 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
900 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
901 tnl_init->port))
1ffeb2eb
JM		 902 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
903 else
904 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 905 /* we are definitely in the PPF here, since we are creating
906 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
907 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
908 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 909 sqpn = qpn;
910 }
911
912 if (!*caller_qp) {
913 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
914 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
915 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 916 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 917 if (!sqp)
918 return -ENOMEM;
919 qp = &sqp->qp;
2f5bb473
JM		 920 qp->pri.vid = 0xFFFF;
921 qp->alt.vid = 0xFFFF;
1ffeb2eb 922 } else {
8900b894 923 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 924 if (!qp)
925 return -ENOMEM;
2f5bb473
JM		 926 qp->pri.vid = 0xFFFF;
927 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 928 }
929 } else
930 qp = *caller_qp;
931
932 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 933
934 mutex_init(&qp->mutex);
935 spin_lock_init(&qp->sq.lock);
936 spin_lock_init(&qp->rq.lock);
fa417f7b 937 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 938 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 939
940 qp->state = IB_QPS_RESET;
ea54b10c
JM		 941 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
942 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 943
225c7b1f
RD		 944
945 if (pd->uobject) {
400b1ebc
GL		 946 union {
947 struct mlx4_ib_create_qp qp;
948 struct mlx4_ib_create_wq wq;
949 } ucmd;
950 size_t copy_len;
ed8637d3
GL		 951 int shift;
952 int n;
400b1ebc
GL		 953
954 copy_len = (src == MLX4_IB_QP_SRC) ?
955 sizeof(struct mlx4_ib_create_qp) :
956 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
225c7b1f 957
400b1ebc 958 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 959 err = -EFAULT;
960 goto err;
961 }
962
400b1ebc 963 if (src == MLX4_IB_RWQ_SRC) {
078b3573
GL		 964 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
965 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
400b1ebc
GL		 966 pr_debug("user command isn't supported\n");
967 err = -EOPNOTSUPP;
968 goto err;
969 }
ea30b966 970
400b1ebc
GL		 971 if (ucmd.wq.log_range_size >
972 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
973 pr_debug("WQN range size must be equal or smaller than %d\n",
974 dev->dev->caps.max_rss_tbl_sz);
975 err = -EOPNOTSUPP;
976 goto err;
977 }
978 range_size = 1 << ucmd.wq.log_range_size;
979 } else {
980 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
981 }
0e6e7416 982
6d06c9aa
GL		 983 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
984 if (!(dev->dev->caps.flags &
985 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
986 pr_debug("scatter FCS is unsupported\n");
987 err = -EOPNOTSUPP;
988 goto err;
989 }
990
991 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
992 }
993
400b1ebc
GL		 994 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
995 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 996 if (err)
997 goto err;
998
400b1ebc
GL		 999 if (src == MLX4_IB_QP_SRC) {
1000 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1001
1002 err = set_user_sq_size(dev, qp,
1003 (struct mlx4_ib_create_qp *)
1004 &ucmd);
1005 if (err)
1006 goto err;
1007 } else {
1008 qp->sq_no_prefetch = 1;
1009 qp->sq.wqe_cnt = 1;
1010 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1011 /* Allocated buffer expects to have at least that SQ
1012 * size.
1013 */
1014 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1015 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1016 }
1017
1018 qp->umem = ib_umem_get(pd->uobject->context,
1019 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1020 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
225c7b1f
RD		 1021 if (IS_ERR(qp->umem)) {
1022 err = PTR_ERR(qp->umem);
1023 goto err;
1024 }
1025
ed8637d3
GL		 1026 n = ib_umem_page_count(qp->umem);
1027 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1028 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1029
225c7b1f
RD		 1030 if (err)
1031 goto err_buf;
1032
1033 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1034 if (err)
1035 goto err_mtt;
1036
0a1405da 1037 if (qp_has_rq(init_attr)) {
02d89b87 1038 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
400b1ebc
GL		 1039 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1040 ucmd.wq.db_addr, &qp->db);
02d89b87
RD		 1041 if (err)
1042 goto err_mtt;
1043 }
f3301870 1044 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1045 } else {
ea30b966
MG		 1046 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1047 qp_has_rq(init_attr), qp, 0);
1048 if (err)
1049 goto err;
1050
0e6e7416
RD		 1051 qp->sq_no_prefetch = 0;
1052
b832be1e
EC		 1053 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1054 qp->flags |= MLX4_IB_QP_LSO;
1055
c1c98501
MB		 1056 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1057 if (dev->steering_support ==
1058 MLX4_STEERING_MODE_DEVICE_MANAGED)
1059 qp->flags |= MLX4_IB_QP_NETIF;
1060 else
1061 goto err;
1062 }
1063
f95ccffc 1064 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 1065 if (err)
1066 goto err;
1067
0a1405da 1068 if (qp_has_rq(init_attr)) {
8900b894 1069 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1070 if (err)
1071 goto err;
225c7b1f 1072
02d89b87
RD		 1073 *qp->db.db = 0;
1074 }
225c7b1f 1075
f95ccffc 1076 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
8900b894 1077 &qp->buf)) {
f95ccffc
JM		 1078 err = -ENOMEM;
1079 goto err_db;
225c7b1f
RD		 1080 }
1081
1082 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1083 &qp->mtt);
1084 if (err)
1085 goto err_buf;
1086
8900b894 1087 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1088 if (err)
1089 goto err_mtt;
1090
e9105cde
LD		 1091 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1092 sizeof(u64), GFP_KERNEL);
1093 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1094 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1095 if (!qp->sq.wrid || !qp->rq.wrid) {
1096 err = -ENOMEM;
1097 goto err_wrid;
1098 }
f3301870 1099 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1100 }
1101
a3cdcbfa 1102 if (sqpn) {
1ffeb2eb
JM		 1103 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1104 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1105 if (alloc_proxy_bufs(pd->device, qp)) {
1106 err = -ENOMEM;
1107 goto err_wrid;
1108 }
1109 }
400b1ebc
GL		 1110 } else if (src == MLX4_IB_RWQ_SRC) {
1111 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1112 range_size, &qpn);
1113 if (err)
1114 goto err_wrid;
a3cdcbfa 1115 } else {
ddae0349
EE		 1116 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1117 * otherwise, the WQE BlueFlame setup flow wrongly causes
1118 * VLAN insertion. */
3987a2d3 1119 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1120 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1121 (init_attr->cap.max_send_wr ?
1122 MLX4_RESERVE_ETH_BF_QP : 0) |
1123 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1124 MLX4_RESERVE_A0_QP : 0),
1125 qp->mqp.usage);
3987a2d3 1126 else
c1c98501
MB		 1127 if (qp->flags & MLX4_IB_QP_NETIF)
1128 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1129 else
1130 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1131 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1132 if (err)
1ffeb2eb 1133 goto err_proxy;
a3cdcbfa
YP		 1134 }
1135
fbfb6625
EBE		 1136 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1137 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1138
8900b894 1139 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1140 if (err)
a3cdcbfa 1141 goto err_qpn;
225c7b1f 1142
0a1405da
SH		 1143 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1144 qp->mqp.qpn |= (1 << 23);
1145
225c7b1f
RD		 1146 /*
1147 * Hardware wants QPN written in big-endian order (after
1148 * shifting) for send doorbell. Precompute this value to save
1149 * a little bit when posting sends.
1150 */
1151 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1152
400b1ebc
GL		 1153 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1154 mlx4_ib_wq_event;
1155
1ffeb2eb
JM		 1156 if (!*caller_qp)
1157 *caller_qp = qp;
35f05dab
YH		 1158
1159 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1160 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1161 to_mcq(init_attr->recv_cq));
1162 /* Maintain device to QPs access, needed for further handling
1163 * via reset flow
1164 */
1165 list_add_tail(&qp->qps_list, &dev->qp_list);
1166 /* Maintain CQ to QPs access, needed for further handling
1167 * via reset flow
1168 */
1169 mcq = to_mcq(init_attr->send_cq);
1170 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1171 mcq = to_mcq(init_attr->recv_cq);
1172 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1173 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1174 to_mcq(init_attr->recv_cq));
1175 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1176 return 0;
1177
a3cdcbfa 1178err_qpn:
c1c98501
MB		 1179 if (!sqpn) {
1180 if (qp->flags & MLX4_IB_QP_NETIF)
1181 mlx4_ib_steer_qp_free(dev, qpn, 1);
400b1ebc
GL		 1182 else if (src == MLX4_IB_RWQ_SRC)
1183 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1184 qp, 0);
c1c98501
MB		 1185 else
1186 mlx4_qp_release_range(dev->dev, qpn, 1);
1187 }
1ffeb2eb
JM		 1188err_proxy:
1189 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1190 free_proxy_bufs(pd->device, qp);
225c7b1f 1191err_wrid:
23f1b384 1192 if (pd->uobject) {
0a1405da
SH		 1193 if (qp_has_rq(init_attr))
1194 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 1195 } else {
0ef2f05c
WW		 1196 kvfree(qp->sq.wrid);
1197 kvfree(qp->rq.wrid);
225c7b1f
RD		 1198 }
1199
1200err_mtt:
1201 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1202
1203err_buf:
1204 if (pd->uobject)
1205 ib_umem_release(qp->umem);
1206 else
1207 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1208
1209err_db:
0a1405da 1210 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 1211 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1212
1213err:
2dd8e44c 1214 if (!sqp && !*caller_qp)
1ffeb2eb 1215 kfree(qp);
2dd8e44c
YS		 1216 kfree(sqp);
1217
225c7b1f
RD		 1218 return err;
1219}
1220
1221static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1222{
1223 switch (state) {
1224 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1225 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1226 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1227 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1228 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1229 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1230 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1231 default: return -1;
1232 }
1233}
1234
1235static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1236 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1237{
338a8fad 1238 if (send_cq == recv_cq) {
35f05dab 1239 spin_lock(&send_cq->lock);
338a8fad
RD		 1240 __acquire(&recv_cq->lock);
1241 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1242 spin_lock(&send_cq->lock);
225c7b1f
RD		 1243 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1244 } else {
35f05dab 1245 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1246 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1247 }
1248}
1249
1250static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1251 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1252{
338a8fad
RD		 1253 if (send_cq == recv_cq) {
1254 __release(&recv_cq->lock);
35f05dab 1255 spin_unlock(&send_cq->lock);
338a8fad 1256 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1257 spin_unlock(&recv_cq->lock);
35f05dab 1258 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1259 } else {
1260 spin_unlock(&send_cq->lock);
35f05dab 1261 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1262 }
1263}
1264
fa417f7b
EC		 1265static void del_gid_entries(struct mlx4_ib_qp *qp)
1266{
1267 struct mlx4_ib_gid_entry *ge, *tmp;
1268
1269 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1270 list_del(&ge->list);
1271 kfree(ge);
1272 }
1273}
1274
0a1405da
SH		 1275static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1276{
1277 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1278 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1279 else
1280 return to_mpd(qp->ibqp.pd);
1281}
1282
400b1ebc 1283static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1284 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1285{
1286 switch (qp->ibqp.qp_type) {
1287 case IB_QPT_XRC_TGT:
1288 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1289 *recv_cq = *send_cq;
1290 break;
1291 case IB_QPT_XRC_INI:
1292 *send_cq = to_mcq(qp->ibqp.send_cq);
1293 *recv_cq = *send_cq;
1294 break;
1295 default:
400b1ebc
GL		 1296 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1297 to_mcq(qp->ibwq.cq);
1298 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1299 *recv_cq;
0a1405da
SH		 1300 break;
1301 }
1302}
1303
3078f5f1
GL		 1304static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1305{
1306 if (qp->state != IB_QPS_RESET) {
1307 int i;
1308
1309 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1310 i++) {
1311 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1312 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1313
1314 mutex_lock(&wq->mutex);
1315
1316 wq->rss_usecnt--;
1317
1318 mutex_unlock(&wq->mutex);
1319 }
1320
1321 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1322 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1323 pr_warn("modify QP %06x to RESET failed.\n",
1324 qp->mqp.qpn);
1325 }
1326
1327 mlx4_qp_remove(dev->dev, &qp->mqp);
1328 mlx4_qp_free(dev->dev, &qp->mqp);
1329 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1330 del_gid_entries(qp);
1331 kfree(qp->rss_ctx);
1332}
1333
225c7b1f 1334static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
400b1ebc 1335 enum mlx4_ib_source_type src, int is_user)
225c7b1f
RD		 1336{
1337 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1338 unsigned long flags;
225c7b1f 1339
2f5bb473 1340 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1341 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1342 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1343 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1344 qp->mqp.qpn);
25476b02 1345 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1346 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1347 qp->pri.smac = 0;
25476b02 1348 qp->pri.smac_port = 0;
2f5bb473
JM		 1349 }
1350 if (qp->alt.smac) {
1351 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1352 qp->alt.smac = 0;
1353 }
1354 if (qp->pri.vid < 0x1000) {
1355 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1356 qp->pri.vid = 0xFFFF;
1357 qp->pri.candidate_vid = 0xFFFF;
1358 qp->pri.update_vid = 0;
1359 }
1360 if (qp->alt.vid < 0x1000) {
1361 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1362 qp->alt.vid = 0xFFFF;
1363 qp->alt.candidate_vid = 0xFFFF;
1364 qp->alt.update_vid = 0;
1365 }
1366 }
225c7b1f 1367
400b1ebc 1368 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1369
35f05dab 1370 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1371 mlx4_ib_lock_cqs(send_cq, recv_cq);
1372
35f05dab
YH		 1373 /* del from lists under both locks above to protect reset flow paths */
1374 list_del(&qp->qps_list);
1375 list_del(&qp->cq_send_list);
1376 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1377 if (!is_user) {
1378 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1379 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1380 if (send_cq != recv_cq)
1381 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1382 }
1383
1384 mlx4_qp_remove(dev->dev, &qp->mqp);
1385
1386 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1387 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1388
1389 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1390
c1c98501
MB		 1391 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1392 if (qp->flags & MLX4_IB_QP_NETIF)
1393 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc
GL		 1394 else if (src == MLX4_IB_RWQ_SRC)
1395 mlx4_ib_release_wqn(to_mucontext(
1396 qp->ibwq.uobject->context), qp, 1);
c1c98501
MB		 1397 else
1398 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1399 }
a3cdcbfa 1400
225c7b1f
RD		 1401 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1402
1403 if (is_user) {
400b1ebc
GL		 1404 if (qp->rq.wqe_cnt) {
1405 struct mlx4_ib_ucontext *mcontext = !src ?
1406 to_mucontext(qp->ibqp.uobject->context) :
1407 to_mucontext(qp->ibwq.uobject->context);
1408 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1409 }
225c7b1f
RD		 1410 ib_umem_release(qp->umem);
1411 } else {
0ef2f05c
WW		 1412 kvfree(qp->sq.wrid);
1413 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1414 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1415 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1416 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1417 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1418 if (qp->rq.wqe_cnt)
6296883c 1419 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1420 }
fa417f7b
EC		 1421
1422 del_gid_entries(qp);
225c7b1f
RD		 1423}
1424
47605df9
JM		 1425static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1426{
1427 /* Native or PPF */
1428 if (!mlx4_is_mfunc(dev->dev) ||
1429 (mlx4_is_master(dev->dev) &&
1430 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1431 return dev->dev->phys_caps.base_sqpn +
1432 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1433 attr->port_num - 1;
1434 }
1435 /* PF or VF -- creating proxies */
1436 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1437 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1438 else
c73c8b1e 1439 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1440}
1441
e1b866c6
MS		 1442static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1443 struct ib_qp_init_attr *init_attr,
1444 struct ib_udata *udata)
225c7b1f 1445{
1ffeb2eb 1446 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1447 int err;
fbfb6625 1448 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1449 u16 xrcdn = 0;
225c7b1f 1450
3078f5f1
GL		 1451 if (init_attr->rwq_ind_tbl)
1452 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1453
521e575b 1454 /*
1ffeb2eb
JM		 1455 * We only support LSO, vendor flag1, and multicast loopback blocking,
1456 * and only for kernel UD QPs.
521e575b 1457 */
1ffeb2eb
JM		 1458 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1459 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1460 MLX4_IB_SRIOV_TUNNEL_QP |
1461 MLX4_IB_SRIOV_SQP |
40f2287b 1462 MLX4_IB_QP_NETIF |
8900b894 1463 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1464 return ERR_PTR(-EINVAL);
521e575b 1465
c1c98501
MB		 1466 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1467 if (init_attr->qp_type != IB_QPT_UD)
1468 return ERR_PTR(-EINVAL);
1469 }
1470
e1b866c6
MS		 1471 if (init_attr->create_flags) {
1472 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1473 return ERR_PTR(-EINVAL);
1474
1475 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1476 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1477 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1478 init_attr->qp_type != IB_QPT_UD) ||
1479 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1480 init_attr->qp_type > IB_QPT_GSI) ||
1481 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1482 init_attr->qp_type != IB_QPT_GSI))
1483 return ERR_PTR(-EINVAL);
1484 }
b846f25a 1485
225c7b1f 1486 switch (init_attr->qp_type) {
0a1405da
SH		 1487 case IB_QPT_XRC_TGT:
1488 pd = to_mxrcd(init_attr->xrcd)->pd;
1489 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1490 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1491 /* fall through */
1492 case IB_QPT_XRC_INI:
1493 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1494 return ERR_PTR(-ENOSYS);
1495 init_attr->recv_cq = init_attr->send_cq;
1496 /* fall through */
225c7b1f
RD		 1497 case IB_QPT_RC:
1498 case IB_QPT_UC:
3987a2d3 1499 case IB_QPT_RAW_PACKET:
8900b894 1500 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1501 if (!qp)
1502 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1503 qp->pri.vid = 0xFFFF;
1504 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1505 /* fall through */
1506 case IB_QPT_UD:
1507 {
400b1ebc
GL		 1508 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1509 init_attr, udata, 0, &qp);
5b420d9c
DB		 1510 if (err) {
1511 kfree(qp);
225c7b1f 1512 return ERR_PTR(err);
5b420d9c 1513 }
225c7b1f
RD		 1514
1515 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1516 qp->xrcdn = xrcdn;
225c7b1f
RD		 1517
1518 break;
1519 }
1520 case IB_QPT_SMI:
1521 case IB_QPT_GSI:
1522 {
e1b866c6
MS		 1523 int sqpn;
1524
225c7b1f 1525 /* Userspace is not allowed to create special QPs: */
0a1405da 1526 if (udata)
225c7b1f 1527 return ERR_PTR(-EINVAL);
e1b866c6 1528 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1529 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1530 1, 1, &sqpn, 0,
1531 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1532
1533 if (res)
1534 return ERR_PTR(res);
1535 } else {
1536 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1537 }
225c7b1f 1538
400b1ebc
GL		 1539 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1540 init_attr, udata, sqpn, &qp);
1ffeb2eb 1541 if (err)
225c7b1f 1542 return ERR_PTR(err);
225c7b1f
RD		 1543
1544 qp->port = init_attr->port_num;
e1b866c6
MS		 1545 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1546 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1547 break;
1548 }
1549 default:
1550 /* Don't support raw QPs */
1551 return ERR_PTR(-EINVAL);
1552 }
1553
1554 return &qp->ibqp;
1555}
1556
e1b866c6
MS		 1557struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1558 struct ib_qp_init_attr *init_attr,
1559 struct ib_udata *udata) {
1560 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1561 struct ib_qp *ibqp;
1562 struct mlx4_ib_dev *dev = to_mdev(device);
1563
1564 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1565
1566 if (!IS_ERR(ibqp) &&
1567 (init_attr->qp_type == IB_QPT_GSI) &&
1568 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1569 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1570 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1571
1572 if (is_eth &&
1573 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1574 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1575 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1576
1577 if (IS_ERR(sqp->roce_v2_gsi)) {
1578 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1579 sqp->roce_v2_gsi = NULL;
1580 } else {
1581 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1582 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1583 }
1584
1585 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1586 }
1587 }
1588 return ibqp;
1589}
1590
1591static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1592{
1593 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1594 struct mlx4_ib_qp *mqp = to_mqp(qp);
1595
1596 if (is_qp0(dev, mqp))
1597 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1598
c482af64
JM		 1599 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1600 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1601 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1602 dev->qp1_proxy[mqp->port - 1] = NULL;
1603 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1604 }
1605
7b59f0f9
EBE		 1606 if (mqp->counter_index)
1607 mlx4_ib_free_qp_counter(dev, mqp);
1608
3078f5f1
GL		 1609 if (qp->rwq_ind_tbl) {
1610 destroy_qp_rss(dev, mqp);
1611 } else {
1612 struct mlx4_ib_pd *pd;
1613
1614 pd = get_pd(mqp);
1615 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1616 }
225c7b1f
RD		 1617
1618 if (is_sqp(dev, mqp))
1619 kfree(to_msqp(mqp));
1620 else
1621 kfree(mqp);
1622
1623 return 0;
1624}
1625
e1b866c6
MS		 1626int mlx4_ib_destroy_qp(struct ib_qp *qp)
1627{
1628 struct mlx4_ib_qp *mqp = to_mqp(qp);
1629
1630 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1631 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1632
1633 if (sqp->roce_v2_gsi)
1634 ib_destroy_qp(sqp->roce_v2_gsi);
1635 }
1636
1637 return _mlx4_ib_destroy_qp(qp);
1638}
1639
1ffeb2eb 1640static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1641{
1642 switch (type) {
1ffeb2eb
JM		 1643 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1644 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1645 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1646 case MLX4_IB_QPT_XRC_INI:
1647 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1648 case MLX4_IB_QPT_SMI:
1649 case MLX4_IB_QPT_GSI:
1650 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1651
1652 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1653 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1654 MLX4_QP_ST_MLX : -1);
1655 case MLX4_IB_QPT_PROXY_SMI:
1656 case MLX4_IB_QPT_TUN_SMI:
1657 case MLX4_IB_QPT_PROXY_GSI:
1658 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1659 MLX4_QP_ST_UD : -1);
1660 default: return -1;
225c7b1f
RD		 1661 }
1662}
1663
65adfa91 1664static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1665 int attr_mask)
1666{
1667 u8 dest_rd_atomic;
1668 u32 access_flags;
1669 u32 hw_access_flags = 0;
1670
1671 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1672 dest_rd_atomic = attr->max_dest_rd_atomic;
1673 else
1674 dest_rd_atomic = qp->resp_depth;
1675
1676 if (attr_mask & IB_QP_ACCESS_FLAGS)
1677 access_flags = attr->qp_access_flags;
1678 else
1679 access_flags = qp->atomic_rd_en;
1680
1681 if (!dest_rd_atomic)
1682 access_flags &= IB_ACCESS_REMOTE_WRITE;
1683
1684 if (access_flags & IB_ACCESS_REMOTE_READ)
1685 hw_access_flags |= MLX4_QP_BIT_RRE;
1686 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1687 hw_access_flags |= MLX4_QP_BIT_RAE;
1688 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1689 hw_access_flags |= MLX4_QP_BIT_RWE;
1690
1691 return cpu_to_be32(hw_access_flags);
1692}
1693
65adfa91 1694static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1695 int attr_mask)
1696{
1697 if (attr_mask & IB_QP_PKEY_INDEX)
1698 sqp->pkey_index = attr->pkey_index;
1699 if (attr_mask & IB_QP_QKEY)
1700 sqp->qkey = attr->qkey;
1701 if (attr_mask & IB_QP_SQ_PSN)
1702 sqp->send_psn = attr->sq_psn;
1703}
1704
1705static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1706{
1707 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1708}
1709
90898850
DC		 1710static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1711 const struct rdma_ah_attr *ah,
297e0dad 1712 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1713 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1714{
4c3eb3ca 1715 int vidx;
297e0dad 1716 int smac_index;
2f5bb473 1717 int err;
297e0dad 1718
d8966fcd
DC		 1719 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1720 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1721 if (rdma_ah_get_static_rate(ah)) {
1722 path->static_rate = rdma_ah_get_static_rate(ah) +
1723 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1724 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1725 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1726 --path->static_rate;
1727 } else
1728 path->static_rate = 0;
225c7b1f 1729
d8966fcd
DC		 1730 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1731 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1732 int real_sgid_index =
7492052a 1733 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
5070cd22 1734
54a6d63f
DC		 1735 if (real_sgid_index < 0)
1736 return real_sgid_index;
5070cd22 1737 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1738 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1739 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1740 return -1;
1741 }
1742
1743 path->grh_mylmc |= 1 << 7;
5070cd22 1744 path->mgid_index = real_sgid_index;
d8966fcd 1745 path->hop_limit = grh->hop_limit;
225c7b1f 1746 path->tclass_flowlabel =
d8966fcd
DC		 1747 cpu_to_be32((grh->traffic_class << 20) |
1748 (grh->flow_label));
1749 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1750 }
1751
44c58487 1752 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1753 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1754 return -1;
1755
2f5bb473 1756 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1757 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1758
297e0dad 1759 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1760 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1761 if (smac_info->vid < 0x1000) {
1762 /* both valid vlan ids */
1763 if (smac_info->vid != vlan_tag) {
1764 /* different VIDs. unreg old and reg new */
1765 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1766 if (err)
1767 return err;
1768 smac_info->candidate_vid = vlan_tag;
1769 smac_info->candidate_vlan_index = vidx;
1770 smac_info->candidate_vlan_port = port;
1771 smac_info->update_vid = 1;
1772 path->vlan_index = vidx;
1773 } else {
1774 path->vlan_index = smac_info->vlan_index;
1775 }
1776 } else {
1777 /* no current vlan tag in qp */
1778 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1779 if (err)
1780 return err;
1781 smac_info->candidate_vid = vlan_tag;
1782 smac_info->candidate_vlan_index = vidx;
1783 smac_info->candidate_vlan_port = port;
1784 smac_info->update_vid = 1;
1785 path->vlan_index = vidx;
1786 }
297e0dad 1787 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1788 path->fl = 1 << 6;
1789 } else {
1790 /* have current vlan tag. unregister it at modify-qp success */
1791 if (smac_info->vid < 0x1000) {
1792 smac_info->candidate_vid = 0xFFFF;
1793 smac_info->update_vid = 1;
1794 }
4c3eb3ca 1795 }
2f5bb473
JM		 1796
1797 /* get smac_index for RoCE use.
1798 * If no smac was yet assigned, register one.
1799 * If one was already assigned, but the new mac differs,
1800 * unregister the old one and register the new one.
1801 */
25476b02
JM		 1802 if ((!smac_info->smac && !smac_info->smac_port) ||
1803 smac_info->smac != smac) {
2f5bb473
JM		 1804 /* register candidate now, unreg if needed, after success */
1805 smac_index = mlx4_register_mac(dev->dev, port, smac);
1806 if (smac_index >= 0) {
1807 smac_info->candidate_smac_index = smac_index;
1808 smac_info->candidate_smac = smac;
1809 smac_info->candidate_smac_port = port;
1810 } else {
1811 return -EINVAL;
1812 }
1813 } else {
1814 smac_index = smac_info->smac_index;
1815 }
44c58487 1816 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1817 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1818 /* put MAC table smac index for IBoE */
1819 path->grh_mylmc = (u8) (smac_index) | 0x80;
1820 } else {
4c3eb3ca 1821 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1822 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1823 }
fa417f7b 1824
225c7b1f
RD		 1825 return 0;
1826}
1827
297e0dad
MS		 1828static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1829 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1830 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1831 struct mlx4_qp_path *path, u8 port,
1832 u16 vlan_id, u8 *smac)
297e0dad
MS		 1833{
1834 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1835 mlx4_mac_to_u64(smac),
1836 vlan_id,
2f5bb473 1837 path, &mqp->pri, port);
297e0dad
MS		 1838}
1839
1840static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1841 const struct ib_qp_attr *qp,
1842 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1843 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1844 struct mlx4_qp_path *path, u8 port)
1845{
1846 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1847 0,
1848 0xffff,
2f5bb473 1849 path, &mqp->alt, port);
297e0dad
MS		 1850}
1851
fa417f7b
EC		 1852static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1853{
1854 struct mlx4_ib_gid_entry *ge, *tmp;
1855
1856 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1857 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1858 ge->added = 1;
1859 ge->port = qp->port;
1860 }
1861 }
1862}
1863
dbf727de
MB		 1864static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1865 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1866 struct mlx4_qp_context *context)
1867{
2f5bb473
JM		 1868 u64 u64_mac;
1869 int smac_index;
1870
3e0629cb 1871 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1872
1873 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1874 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1875 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1876 if (smac_index >= 0) {
1877 qp->pri.candidate_smac_index = smac_index;
1878 qp->pri.candidate_smac = u64_mac;
1879 qp->pri.candidate_smac_port = qp->port;
1880 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1881 } else {
1882 return -ENOENT;
1883 }
1884 }
1885 return 0;
1886}
1887
7b59f0f9
EBE		 1888static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1889{
1890 struct counter_index *new_counter_index;
1891 int err;
1892 u32 tmp_idx;
1893
1894 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1895 IB_LINK_LAYER_ETHERNET ||
1896 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1897 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1898 return 0;
1899
f3301870 1900 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1901 if (err)
1902 return err;
1903
1904 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1905 if (!new_counter_index) {
1906 mlx4_counter_free(dev->dev, tmp_idx);
1907 return -ENOMEM;
1908 }
1909
1910 new_counter_index->index = tmp_idx;
1911 new_counter_index->allocated = 1;
1912 qp->counter_index = new_counter_index;
1913
1914 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1915 list_add_tail(&new_counter_index->list,
1916 &dev->counters_table[qp->port - 1].counters_list);
1917 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1918
1919 return 0;
1920}
1921
3b5daf28
MS		 1922enum {
1923 MLX4_QPC_ROCE_MODE_1 = 0,
1924 MLX4_QPC_ROCE_MODE_2 = 2,
1925 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1926};
1927
1928static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1929{
1930 switch (gid_type) {
1931 case IB_GID_TYPE_ROCE:
1932 return MLX4_QPC_ROCE_MODE_1;
1933 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1934 return MLX4_QPC_ROCE_MODE_2;
1935 default:
1936 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1937 }
1938}
1939
3078f5f1
GL		 1940/*
1941 * Go over all RSS QP's childes (WQs) and apply their HW state according to
1942 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
1943 */
1944static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
1945{
fba02e6c 1946 int err = 0;
3078f5f1 1947 int i;
3078f5f1
GL		 1948
1949 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
1950 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
1951 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1952
1953 mutex_lock(&wq->mutex);
1954
1955 /* Mlx4_ib restrictions:
1956 * WQ's is associated to a port according to the RSS QP it is
1957 * associates to.
1958 * In case the WQ is associated to a different port by another
1959 * RSS QP, return a failure.
1960 */
1961 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
1962 err = -EINVAL;
1963 mutex_unlock(&wq->mutex);
1964 break;
1965 }
1966 wq->port = port_num;
1967 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
1968 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
1969 if (err) {
1970 mutex_unlock(&wq->mutex);
1971 break;
1972 }
1973 }
1974 wq->rss_usecnt++;
1975
1976 mutex_unlock(&wq->mutex);
1977 }
1978
1979 if (i && err) {
1980 int j;
1981
1982 for (j = (i - 1); j >= 0; j--) {
1983 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
1984 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1985
1986 mutex_lock(&wq->mutex);
1987
1988 if ((wq->rss_usecnt == 1) &&
1989 (ibwq->state == IB_WQS_RDY))
1990 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
1991 pr_warn("failed to reverse WQN=0x%06x\n",
1992 ibwq->wq_num);
1993 wq->rss_usecnt--;
1994
1995 mutex_unlock(&wq->mutex);
1996 }
1997 }
1998
1999 return err;
2000}
2001
2002static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2003{
2004 int i;
2005
2006 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2007 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2008 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2009
2010 mutex_lock(&wq->mutex);
2011
2012 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2013 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2014 pr_warn("failed to reverse WQN=%x\n",
2015 ibwq->wq_num);
2016 wq->rss_usecnt--;
2017
2018 mutex_unlock(&wq->mutex);
2019 }
2020}
2021
2022static void fill_qp_rss_context(struct mlx4_qp_context *context,
2023 struct mlx4_ib_qp *qp)
2024{
2025 struct mlx4_rss_context *rss_context;
2026
2027 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2028 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2029
2030 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2031 rss_context->default_qpn =
2032 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2033 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2034 rss_context->base_qpn_udp = rss_context->default_qpn;
2035 rss_context->flags = qp->rss_ctx->flags;
2036 /* Currently support just toeplitz */
2037 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2038
2039 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2040 MLX4_EN_RSS_KEY_SIZE);
2041}
2042
400b1ebc 2043static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91
MT		 2044 const struct ib_qp_attr *attr, int attr_mask,
2045 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f 2046{
400b1ebc
GL		 2047 struct ib_uobject *ibuobject;
2048 struct ib_srq *ibsrq;
47ec3866 2049 const struct ib_gid_attr *gid_attr = NULL;
3078f5f1 2050 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2051 enum ib_qp_type qp_type;
2052 struct mlx4_ib_dev *dev;
2053 struct mlx4_ib_qp *qp;
0a1405da
SH		 2054 struct mlx4_ib_pd *pd;
2055 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 2056 struct mlx4_qp_context *context;
2057 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2058 int sqd_event;
c1c98501 2059 int steer_qp = 0;
225c7b1f 2060 int err = -EINVAL;
3ba8e31d 2061 int counter_index;
225c7b1f 2062
400b1ebc
GL		 2063 if (src_type == MLX4_IB_RWQ_SRC) {
2064 struct ib_wq *ibwq;
2065
3078f5f1
GL		 2066 ibwq = (struct ib_wq *)src;
2067 ibuobject = ibwq->uobject;
2068 ibsrq = NULL;
2069 rwq_ind_tbl = NULL;
2070 qp_type = IB_QPT_RAW_PACKET;
2071 qp = to_mqp((struct ib_qp *)ibwq);
2072 dev = to_mdev(ibwq->device);
2073 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2074 } else {
2075 struct ib_qp *ibqp;
2076
3078f5f1
GL		 2077 ibqp = (struct ib_qp *)src;
2078 ibuobject = ibqp->uobject;
2079 ibsrq = ibqp->srq;
2080 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2081 qp_type = ibqp->qp_type;
2082 qp = to_mqp(ibqp);
2083 dev = to_mdev(ibqp->device);
2084 pd = get_pd(qp);
400b1ebc
GL		 2085 }
2086
3dec4878
JM		 2087 /* APM is not supported under RoCE */
2088 if (attr_mask & IB_QP_ALT_PATH &&
2089 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2090 IB_LINK_LAYER_ETHERNET)
2091 return -ENOTSUPP;
2092
225c7b1f
RD		 2093 context = kzalloc(sizeof *context, GFP_KERNEL);
2094 if (!context)
2095 return -ENOMEM;
2096
225c7b1f 2097 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2098 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2099
2100 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2101 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2102 else {
2103 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2104 switch (attr->path_mig_state) {
2105 case IB_MIG_MIGRATED:
2106 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2107 break;
2108 case IB_MIG_REARM:
2109 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2110 break;
2111 case IB_MIG_ARMED:
2112 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2113 break;
2114 }
2115 }
2116
ea30b966
MG		 2117 if (qp->inl_recv_sz)
2118 context->param3 |= cpu_to_be32(1 << 25);
2119
6d06c9aa
GL		 2120 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2121 context->param3 |= cpu_to_be32(1 << 29);
2122
400b1ebc 2123 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2124 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2125 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2126 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2127 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2128 if (qp->flags & MLX4_IB_QP_LSO)
2129 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2130 ilog2(dev->dev->caps.max_gso_sz);
2131 else
5f22a1d8 2132 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2133 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2134 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2135 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2136 attr->path_mtu);
f5b40431 2137 goto out;
225c7b1f 2138 }
d1f2cd89
EC		 2139 context->mtu_msgmax = (attr->path_mtu << 5) |
2140 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2141 }
2142
3078f5f1
GL		 2143 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2144 if (qp->rq.wqe_cnt)
2145 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2146 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2147 }
225c7b1f 2148
0e6e7416
RD		 2149 if (qp->sq.wqe_cnt)
2150 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2151 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2152
7b59f0f9
EBE		 2153 if (new_state == IB_QPS_RESET && qp->counter_index)
2154 mlx4_ib_free_qp_counter(dev, qp);
2155
0a1405da 2156 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2157 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2158 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2159 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2160 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2161 }
0e6e7416 2162
400b1ebc 2163 if (ibuobject)
85743f1e
HN		 2164 context->usr_page = cpu_to_be32(
2165 mlx4_to_hw_uar_index(dev->dev,
400b1ebc
GL		 2166 to_mucontext(ibuobject->context)
2167 ->uar.index));
225c7b1f 2168 else
85743f1e
HN		 2169 context->usr_page = cpu_to_be32(
2170 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2171
2172 if (attr_mask & IB_QP_DEST_QPN)
2173 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2174
2175 if (attr_mask & IB_QP_PORT) {
2176 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2177 !(attr_mask & IB_QP_AV)) {
2178 mlx4_set_sched(&context->pri_path, attr->port_num);
2179 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2180 }
2181 }
2182
cfcde11c 2183 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2184 err = create_qp_lb_counter(dev, qp);
2185 if (err)
2186 goto out;
2187
3ba8e31d
EBE		 2188 counter_index =
2189 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2190 if (qp->counter_index)
2191 counter_index = qp->counter_index->index;
2192
3ba8e31d
EBE		 2193 if (counter_index != -1) {
2194 context->pri_path.counter_index = counter_index;
cfcde11c 2195 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2196 if (qp->counter_index) {
2197 context->pri_path.fl |=
2198 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2199 context->pri_path.vlan_control |=
2200 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2201 }
cfcde11c 2202 } else
47d8417f
EBE		 2203 context->pri_path.counter_index =
2204 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2205
2206 if (qp->flags & MLX4_IB_QP_NETIF) {
2207 mlx4_ib_steer_qp_reg(dev, qp, 1);
2208 steer_qp = 1;
2209 }
e1b866c6 2210
400b1ebc 2211 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2212 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2213 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2214 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2215
2216 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2217 }
cfcde11c
OG		 2218 }
2219
225c7b1f 2220 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2221 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2222 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2223 context->pri_path.pkey_index = attr->pkey_index;
2224 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2225 }
2226
225c7b1f 2227 if (attr_mask & IB_QP_AV) {
400b1ebc 2228 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de 2229 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
dbf727de
MB		 2230 u16 vlan = 0xffff;
2231 u8 smac[ETH_ALEN];
d8966fcd
DC		 2232 int is_eth =
2233 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2234 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2235
d8966fcd 2236 if (is_eth) {
47ec3866
PP		 2237 gid_attr = attr->ah_attr.grh.sgid_attr;
2238 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
2239 memcpy(smac, gid_attr->ndev->dev_addr, ETH_ALEN);
dbf727de 2240 }
dbf727de 2241
2f5bb473 2242 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2243 port_num, vlan, smac))
225c7b1f 2244 goto out;
225c7b1f
RD		 2245
2246 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2247 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2248
2249 if (is_eth &&
2250 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
47ec3866 2251 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
3b5daf28
MS		 2252
2253 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2254 err = -EINVAL;
2255 goto out;
2256 }
2257 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2258 }
2259
225c7b1f
RD		 2260 }
2261
2262 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2263 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2264 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2265 }
2266
2267 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2268 if (attr->alt_port_num == 0 ||
2269 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2270 goto out;
225c7b1f 2271
5ae2a7a8
RD		 2272 if (attr->alt_pkey_index >=
2273 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2274 goto out;
5ae2a7a8 2275
2f5bb473
JM		 2276 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2277 &context->alt_path,
297e0dad 2278 attr->alt_port_num))
f5b40431 2279 goto out;
225c7b1f
RD		 2280
2281 context->alt_path.pkey_index = attr->alt_pkey_index;
2282 context->alt_path.ackto = attr->alt_timeout << 3;
2283 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2284 }
2285
3078f5f1
GL		 2286 context->pd = cpu_to_be32(pd->pdn);
2287
2288 if (!rwq_ind_tbl) {
108809a0 2289 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2290 get_cqs(qp, src_type, &send_cq, &recv_cq);
2291 } else { /* Set dummy CQs to be compatible with HV and PRM */
2292 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2293 recv_cq = send_cq;
2294 }
0a1405da
SH		 2295 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2296 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2297
95d04f07 2298 /* Set "fast registration enabled" for all kernel QPs */
400b1ebc 2299 if (!ibuobject)
95d04f07
RD		 2300 context->params1 |= cpu_to_be32(1 << 11);
2301
57f01b53
JM		 2302 if (attr_mask & IB_QP_RNR_RETRY) {
2303 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2304 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2305 }
2306
225c7b1f
RD		 2307 if (attr_mask & IB_QP_RETRY_CNT) {
2308 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2309 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2310 }
2311
2312 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2313 if (attr->max_rd_atomic)
2314 context->params1 |=
2315 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2316 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2317 }
2318
2319 if (attr_mask & IB_QP_SQ_PSN)
2320 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2321
225c7b1f
RD		 2322 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2323 if (attr->max_dest_rd_atomic)
2324 context->params2 |=
2325 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2326 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2327 }
2328
2329 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2330 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2331 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2332 }
2333
400b1ebc 2334 if (ibsrq)
225c7b1f
RD		 2335 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2336
2337 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2338 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2339 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2340 }
2341 if (attr_mask & IB_QP_RQ_PSN)
2342 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2343
1ffeb2eb 2344 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2345 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2346 if (qp->mlx4_ib_qp_type &
2347 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2348 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2349 else {
2350 if (mlx4_is_mfunc(dev->dev) &&
2351 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2352 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2353 MLX4_RESERVED_QKEY_BASE) {
2354 pr_err("Cannot use reserved QKEY"
2355 " 0x%x (range 0xffff0000..0xffffffff"
2356 " is reserved)\n", attr->qkey);
2357 err = -EINVAL;
2358 goto out;
2359 }
2360 context->qkey = cpu_to_be32(attr->qkey);
2361 }
225c7b1f
RD		 2362 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2363 }
2364
400b1ebc
GL		 2365 if (ibsrq)
2366 context->srqn = cpu_to_be32(1 << 24 |
2367 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2368
400b1ebc
GL		 2369 if (qp->rq.wqe_cnt &&
2370 cur_state == IB_QPS_RESET &&
2371 new_state == IB_QPS_INIT)
225c7b1f
RD		 2372 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2373
2374 if (cur_state == IB_QPS_INIT &&
2375 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2376 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2377 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2378 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2379 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2380 qp->mlx4_ib_qp_type &
2381 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2382 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2383 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2384 context->pri_path.fl = 0x80;
2385 } else {
2386 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2387 context->pri_path.fl = 0x80;
225c7b1f 2388 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2389 }
2f5bb473
JM		 2390 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2391 IB_LINK_LAYER_ETHERNET) {
2392 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2393 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2394 context->pri_path.feup = 1 << 7; /* don't fsm */
2395 /* handle smac_index */
2396 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2397 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2398 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2399 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2400 if (err) {
2401 err = -EINVAL;
2402 goto out;
2403 }
9433c188
MB		 2404 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2405 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2406 }
2407 }
225c7b1f
RD		 2408 }
2409
400b1ebc 2410 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2411 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2412 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2413 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2414 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2415 if (!rwq_ind_tbl)
d2fce8a9
OG		 2416 context->srqn = cpu_to_be32(7 << 28);
2417 }
2418 }
3528f696 2419
400b1ebc 2420 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2421 int is_eth = rdma_port_get_link_layer(
2422 &dev->ib_dev, qp->port) ==
2423 IB_LINK_LAYER_ETHERNET;
2424 if (is_eth) {
2425 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2426 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2427 }
2428 }
2429
225c7b1f
RD		 2430 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2431 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2432 sqd_event = 1;
2433 else
2434 sqd_event = 0;
2435
400b1ebc
GL		 2436 if (!ibuobject &&
2437 cur_state == IB_QPS_RESET &&
2438 new_state == IB_QPS_INIT)
3b5daf28 2439 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2440
c0be5fb5
EC		 2441 /*
2442 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2443 * ownership bits of the send queue are set and the SQ
2444 * headroom is stamped so that the hardware doesn't start
2445 * processing stale work requests.
c0be5fb5 2446 */
400b1ebc
GL		 2447 if (!ibuobject &&
2448 cur_state == IB_QPS_RESET &&
2449 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2450 struct mlx4_wqe_ctrl_seg *ctrl;
2451 int i;
2452
0e6e7416 2453 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2454 ctrl = get_send_wqe(qp, i);
2455 ctrl->owner_opcode = cpu_to_be32(1 << 31);
f95ccffc
JM		 2456 ctrl->qpn_vlan.fence_size =
2457 1 << (qp->sq.wqe_shift - 4);
2458 stamp_send_wqe(qp, i);
c0be5fb5
EC		 2459 }
2460 }
2461
108809a0
GL		 2462 if (rwq_ind_tbl &&
2463 cur_state == IB_QPS_RESET &&
2464 new_state == IB_QPS_INIT) {
2465 fill_qp_rss_context(context, qp);
2466 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2467 }
2468
225c7b1f
RD		 2469 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2470 to_mlx4_state(new_state), context, optpar,
2471 sqd_event, &qp->mqp);
2472 if (err)
2473 goto out;
2474
2475 qp->state = new_state;
2476
2477 if (attr_mask & IB_QP_ACCESS_FLAGS)
2478 qp->atomic_rd_en = attr->qp_access_flags;
2479 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2480 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2481 if (attr_mask & IB_QP_PORT) {
225c7b1f 2482 qp->port = attr->port_num;
fa417f7b
EC		 2483 update_mcg_macs(dev, qp);
2484 }
225c7b1f
RD		 2485 if (attr_mask & IB_QP_ALT_PATH)
2486 qp->alt_port = attr->alt_port_num;
2487
2488 if (is_sqp(dev, qp))
2489 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2490
2491 /*
2492 * If we moved QP0 to RTR, bring the IB link up; if we moved
2493 * QP0 to RESET or ERROR, bring the link back down.
2494 */
2495 if (is_qp0(dev, qp)) {
2496 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2497 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2498 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2499 qp->port);
225c7b1f
RD		 2500
2501 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2502 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2503 mlx4_CLOSE_PORT(dev->dev, qp->port);
2504 }
2505
2506 /*
2507 * If we moved a kernel QP to RESET, clean up all old CQ
2508 * entries and reinitialize the QP.
2509 */
2f5bb473 2510 if (new_state == IB_QPS_RESET) {
400b1ebc 2511 if (!ibuobject) {
2f5bb473 2512 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2513 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2514 if (send_cq != recv_cq)
2515 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2516
2517 qp->rq.head = 0;
2518 qp->rq.tail = 0;
2519 qp->sq.head = 0;
2520 qp->sq.tail = 0;
2521 qp->sq_next_wqe = 0;
2522 if (qp->rq.wqe_cnt)
2523 *qp->db.db = 0;
225c7b1f 2524
2f5bb473
JM		 2525 if (qp->flags & MLX4_IB_QP_NETIF)
2526 mlx4_ib_steer_qp_reg(dev, qp, 0);
2527 }
25476b02 2528 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2529 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2530 qp->pri.smac = 0;
25476b02 2531 qp->pri.smac_port = 0;
2f5bb473
JM		 2532 }
2533 if (qp->alt.smac) {
2534 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2535 qp->alt.smac = 0;
2536 }
2537 if (qp->pri.vid < 0x1000) {
2538 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2539 qp->pri.vid = 0xFFFF;
2540 qp->pri.candidate_vid = 0xFFFF;
2541 qp->pri.update_vid = 0;
2542 }
c1c98501 2543
2f5bb473
JM		 2544 if (qp->alt.vid < 0x1000) {
2545 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2546 qp->alt.vid = 0xFFFF;
2547 qp->alt.candidate_vid = 0xFFFF;
2548 qp->alt.update_vid = 0;
2549 }
225c7b1f 2550 }
225c7b1f 2551out:
7b59f0f9
EBE		 2552 if (err && qp->counter_index)
2553 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2554 if (err && steer_qp)
2555 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2556 kfree(context);
25476b02
JM		 2557 if (qp->pri.candidate_smac ||
2558 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2559 if (err) {
2560 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2561 } else {
25476b02 2562 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2563 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2564 qp->pri.smac = qp->pri.candidate_smac;
2565 qp->pri.smac_index = qp->pri.candidate_smac_index;
2566 qp->pri.smac_port = qp->pri.candidate_smac_port;
2567 }
2568 qp->pri.candidate_smac = 0;
2569 qp->pri.candidate_smac_index = 0;
2570 qp->pri.candidate_smac_port = 0;
2571 }
2572 if (qp->alt.candidate_smac) {
2573 if (err) {
2574 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2575 } else {
2576 if (qp->alt.smac)
2577 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2578 qp->alt.smac = qp->alt.candidate_smac;
2579 qp->alt.smac_index = qp->alt.candidate_smac_index;
2580 qp->alt.smac_port = qp->alt.candidate_smac_port;
2581 }
2582 qp->alt.candidate_smac = 0;
2583 qp->alt.candidate_smac_index = 0;
2584 qp->alt.candidate_smac_port = 0;
2585 }
2586
2587 if (qp->pri.update_vid) {
2588 if (err) {
2589 if (qp->pri.candidate_vid < 0x1000)
2590 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2591 qp->pri.candidate_vid);
2592 } else {
2593 if (qp->pri.vid < 0x1000)
2594 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2595 qp->pri.vid);
2596 qp->pri.vid = qp->pri.candidate_vid;
2597 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2598 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2599 }
2600 qp->pri.candidate_vid = 0xFFFF;
2601 qp->pri.update_vid = 0;
2602 }
2603
2604 if (qp->alt.update_vid) {
2605 if (err) {
2606 if (qp->alt.candidate_vid < 0x1000)
2607 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2608 qp->alt.candidate_vid);
2609 } else {
2610 if (qp->alt.vid < 0x1000)
2611 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2612 qp->alt.vid);
2613 qp->alt.vid = qp->alt.candidate_vid;
2614 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2615 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2616 }
2617 qp->alt.candidate_vid = 0xFFFF;
2618 qp->alt.update_vid = 0;
2619 }
2620
225c7b1f
RD		 2621 return err;
2622}
2623
3078f5f1
GL		 2624enum {
2625 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2626 IB_QP_PORT),
2627};
2628
e1b866c6
MS		 2629static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2630 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2631{
2632 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2633 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2634 enum ib_qp_state cur_state, new_state;
2635 int err = -EINVAL;
65adfa91
MT		 2636 mutex_lock(&qp->mutex);
2637
2638 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2639 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2640
dd5f03be 2641 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
d31131bb 2642 attr_mask)) {
b1d8eb5a
JM		 2643 pr_debug("qpn 0x%x: invalid attribute mask specified "
2644 "for transition %d to %d. qp_type %d,"
2645 " attr_mask 0x%x\n",
2646 ibqp->qp_num, cur_state, new_state,
2647 ibqp->qp_type, attr_mask);
65adfa91 2648 goto out;
b1d8eb5a 2649 }
65adfa91 2650
3078f5f1
GL		 2651 if (ibqp->rwq_ind_tbl) {
2652 if (!(((cur_state == IB_QPS_RESET) &&
2653 (new_state == IB_QPS_INIT)) ||
2654 ((cur_state == IB_QPS_INIT) &&
2655 (new_state == IB_QPS_RTR)))) {
2656 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2657 ibqp->qp_num, cur_state, new_state);
2658
2659 err = -EOPNOTSUPP;
2660 goto out;
2661 }
2662
2663 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2664 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2665 ibqp->qp_num, attr_mask, cur_state, new_state);
2666
2667 err = -EOPNOTSUPP;
2668 goto out;
2669 }
2670 }
2671
c6215745
MS		 2672 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2673 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2674 if ((ibqp->qp_type == IB_QPT_RC) ||
2675 (ibqp->qp_type == IB_QPT_UD) ||
2676 (ibqp->qp_type == IB_QPT_UC) ||
2677 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2678 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2679 attr->port_num = mlx4_ib_bond_next_port(dev);
2680 }
2681 } else {
2682 /* no sense in changing port_num
2683 * when ports are bonded */
2684 attr_mask &= ~IB_QP_PORT;
2685 }
2686 }
2687
65adfa91 2688 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2689 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2690 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2691 "for transition %d to %d. qp_type %d\n",
2692 ibqp->qp_num, attr->port_num, cur_state,
2693 new_state, ibqp->qp_type);
65adfa91
MT		 2694 goto out;
2695 }
2696
3987a2d3
OG		 2697 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2698 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2699 IB_LINK_LAYER_ETHERNET))
2700 goto out;
2701
5ae2a7a8
RD		 2702 if (attr_mask & IB_QP_PKEY_INDEX) {
2703 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2704 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2705 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2706 "for transition %d to %d. qp_type %d\n",
2707 ibqp->qp_num, attr->pkey_index, cur_state,
2708 new_state, ibqp->qp_type);
5ae2a7a8 2709 goto out;
b1d8eb5a 2710 }
5ae2a7a8
RD		 2711 }
2712
65adfa91
MT		 2713 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2714 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2715 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2716 "Transition %d to %d. qp_type %d\n",
2717 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2718 new_state, ibqp->qp_type);
65adfa91
MT		 2719 goto out;
2720 }
2721
2722 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2723 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2724 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2725 "Transition %d to %d. qp_type %d\n",
2726 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2727 new_state, ibqp->qp_type);
65adfa91
MT		 2728 goto out;
2729 }
2730
2731 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2732 err = 0;
2733 goto out;
2734 }
2735
3078f5f1
GL		 2736 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2737 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2738 if (err)
2739 goto out;
2740 }
2741
400b1ebc
GL		 2742 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2743 cur_state, new_state);
65adfa91 2744
3078f5f1
GL		 2745 if (ibqp->rwq_ind_tbl && err)
2746 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2747
c6215745
MS		 2748 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2749 attr->port_num = 1;
2750
65adfa91
MT		 2751out:
2752 mutex_unlock(&qp->mutex);
2753 return err;
2754}
2755
e1b866c6
MS		 2756int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2757 int attr_mask, struct ib_udata *udata)
2758{
2759 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2760 int ret;
2761
2762 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2763
2764 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2765 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2766 int err = 0;
2767
2768 if (sqp->roce_v2_gsi)
2769 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2770 if (err)
2771 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2772 err);
2773 }
2774 return ret;
2775}
2776
99ec41d0
JM		 2777static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2778{
2779 int i;
2780 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2781 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2782 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2783 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2784 return 0;
2785 }
2786 }
2787 return -EINVAL;
2788}
2789
1ffeb2eb 2790static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
f696bf6d 2791 const struct ib_ud_wr *wr,
1ffeb2eb
JM		 2792 void *wqe, unsigned *mlx_seg_len)
2793{
2794 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2795 struct ib_device *ib_dev = &mdev->ib_dev;
2796 struct mlx4_wqe_mlx_seg *mlx = wqe;
2797 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2798 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2799 u16 pkey;
2800 u32 qkey;
2801 int send_size;
2802 int header_size;
2803 int spc;
2804 int i;
2805
e622f2f4 2806 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2807 return -EINVAL;
2808
2809 send_size = 0;
2810
e622f2f4
CH		 2811 for (i = 0; i < wr->wr.num_sge; ++i)
2812 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2813
2814 /* for proxy-qp0 sends, need to add in size of tunnel header */
2815 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2816 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2817 send_size += sizeof (struct mlx4_ib_tunnel_header);
2818
25f40220 2819 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2820
2821 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2822 sqp->ud_header.lrh.service_level =
2823 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2824 sqp->ud_header.lrh.destination_lid =
2825 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2826 sqp->ud_header.lrh.source_lid =
2827 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2828 }
2829
2830 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2831
2832 /* force loopback */
2833 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2834 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2835
2836 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2837 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2838 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2839 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2840 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2841 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2842 else
2843 sqp->ud_header.bth.destination_qpn =
c73c8b1e 2844 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
1ffeb2eb
JM		 2845
2846 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2847 if (mlx4_is_master(mdev->dev)) {
2848 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2849 return -EINVAL;
2850 } else {
2851 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2852 return -EINVAL;
2853 }
1ffeb2eb
JM		 2854 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2855 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2856
2857 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2858 sqp->ud_header.immediate_present = 0;
2859
2860 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2861
2862 /*
2863 * Inline data segments may not cross a 64 byte boundary. If
2864 * our UD header is bigger than the space available up to the
2865 * next 64 byte boundary in the WQE, use two inline data
2866 * segments to hold the UD header.
2867 */
2868 spc = MLX4_INLINE_ALIGN -
2869 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2870 if (header_size <= spc) {
2871 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2872 memcpy(inl + 1, sqp->header_buf, header_size);
2873 i = 1;
2874 } else {
2875 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2876 memcpy(inl + 1, sqp->header_buf, spc);
2877
2878 inl = (void *) (inl + 1) + spc;
2879 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2880 /*
2881 * Need a barrier here to make sure all the data is
2882 * visible before the byte_count field is set.
2883 * Otherwise the HCA prefetcher could grab the 64-byte
2884 * chunk with this inline segment and get a valid (!=
2885 * 0xffffffff) byte count but stale data, and end up
2886 * generating a packet with bad headers.
2887 *
2888 * The first inline segment's byte_count field doesn't
2889 * need a barrier, because it comes after a
2890 * control/MLX segment and therefore is at an offset
2891 * of 16 mod 64.
2892 */
2893 wmb();
2894 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2895 i = 2;
2896 }
2897
2898 *mlx_seg_len =
2899 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2900 return 0;
2901}
2902
fd10ed8e
JM		 2903static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2904{
2905 union sl2vl_tbl_to_u64 tmp_vltab;
2906 u8 vl;
2907
2908 if (sl > 15)
2909 return 0xf;
2910 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2911 vl = tmp_vltab.sl8[sl >> 1];
2912 if (sl & 1)
2913 vl &= 0x0f;
2914 else
2915 vl >>= 4;
2916 return vl;
2917}
2918
a748d60d
TB		 2919static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2920 int index, union ib_gid *gid,
2921 enum ib_gid_type *gid_type)
2922{
2923 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2924 struct mlx4_port_gid_table *port_gid_table;
2925 unsigned long flags;
2926
2927 port_gid_table = &iboe->gids[port_num - 1];
2928 spin_lock_irqsave(&iboe->lock, flags);
2929 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2930 *gid_type = port_gid_table->gids[index].gid_type;
2931 spin_unlock_irqrestore(&iboe->lock, flags);
25e62655 2932 if (rdma_is_zero_gid(gid))
a748d60d
TB		 2933 return -ENOENT;
2934
2935 return 0;
2936}
2937
3ef967a4 2938#define MLX4_ROCEV2_QP1_SPORT 0xC000
f696bf6d 2939static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr,
f438000f 2940 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2941{
a478868a 2942 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 2943 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 2944 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2945 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2946 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2947 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2948 union ib_gid sgid;
225c7b1f
RD		 2949 u16 pkey;
2950 int send_size;
2951 int header_size;
e61ef241 2952 int spc;
225c7b1f 2953 int i;
1ffeb2eb 2954 int err = 0;
57d88cff 2955 u16 vlan = 0xffff;
a29bec12
RD		 2956 bool is_eth;
2957 bool is_vlan = false;
2958 bool is_grh;
3ef967a4
MS		 2959 bool is_udp = false;
2960 int ip_version = 0;
225c7b1f
RD		 2961
2962 send_size = 0;
e622f2f4
CH		 2963 for (i = 0; i < wr->wr.num_sge; ++i)
2964 send_size += wr->wr.sg_list[i].length;
225c7b1f 2965
fa417f7b
EC		 2966 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2967 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2968 if (is_eth) {
a748d60d 2969 enum ib_gid_type gid_type;
1ffeb2eb
JM		 2970 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2971 /* When multi-function is enabled, the ib_core gid
2972 * indexes don't necessarily match the hw ones, so
2973 * we must use our own cache */
6ee51a4e
JM		 2974 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2975 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2976 ah->av.ib.gid_index, &sgid.raw[0]);
2977 if (err)
2978 return err;
1ffeb2eb 2979 } else {
a748d60d
TB		 2980 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
2981 ah->av.ib.gid_index,
2982 &sgid, &gid_type);
3ef967a4 2983 if (!err) {
a748d60d 2984 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 2985 if (is_udp) {
2986 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2987 ip_version = 4;
2988 else
2989 ip_version = 6;
2990 is_grh = false;
2991 }
2992 } else {
1ffeb2eb 2993 return err;
3ef967a4 2994 }
1ffeb2eb 2995 }
0e9855db 2996 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2997 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2998 is_vlan = 1;
2999 }
4c3eb3ca 3000 }
25f40220 3001 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3002 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3003 if (err)
3004 return err;
fa417f7b
EC		 3005
3006 if (!is_eth) {
3007 sqp->ud_header.lrh.service_level =
3008 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3009 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3010 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3011 }
225c7b1f 3012
3ef967a4 3013 if (is_grh || (ip_version == 6)) {
225c7b1f 3014 sqp->ud_header.grh.traffic_class =
fa417f7b 3015 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3016 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3017 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3018 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3019 if (is_eth) {
6ee51a4e 3020 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3021 } else {
3022 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3023 /* When multi-function is enabled, the ib_core gid
3024 * indexes don't necessarily match the hw ones, so
3025 * we must use our own cache
3026 */
3027 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3028 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3029 demux[sqp->qp.port - 1].
3030 subnet_prefix)));
baa0be70
JM		 3031 sqp->ud_header.grh.source_gid.global.interface_id =
3032 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3033 guid_cache[ah->av.ib.gid_index];
3034 } else {
89af969a
PP		 3035 sqp->ud_header.grh.source_gid =
3036 ah->ibah.sgid_attr->gid;
baa0be70 3037 }
6ee51a4e 3038 }
225c7b1f 3039 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3040 ah->av.ib.dgid, 16);
225c7b1f
RD		 3041 }
3042
3ef967a4
MS		 3043 if (ip_version == 4) {
3044 sqp->ud_header.ip4.tos =
3045 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3046 sqp->ud_header.ip4.id = 0;
3047 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3048 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3049
3050 memcpy(&sqp->ud_header.ip4.saddr,
3051 sgid.raw + 12, 4);
3052 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3053 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3054 }
3055
3056 if (is_udp) {
3057 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3058 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3059 sqp->ud_header.udp.csum = 0;
3060 }
3061
225c7b1f 3062 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3063
3064 if (!is_eth) {
3065 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3066 (sqp->ud_header.lrh.destination_lid ==
3067 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3068 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3069 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3070 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3071 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3072 }
225c7b1f 3073
e622f2f4 3074 switch (wr->wr.opcode) {
225c7b1f
RD		 3075 case IB_WR_SEND:
3076 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3077 sqp->ud_header.immediate_present = 0;
3078 break;
3079 case IB_WR_SEND_WITH_IMM:
3080 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3081 sqp->ud_header.immediate_present = 1;
e622f2f4 3082 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3083 break;
3084 default:
3085 return -EINVAL;
3086 }
3087
fa417f7b 3088 if (is_eth) {
6ee51a4e 3089 struct in6_addr in6;
3ef967a4 3090 u16 ether_type;
c0c1d3d7
OD		 3091 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3092
69ae5439 3093 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3094 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3095
c0c1d3d7 3096 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3097
1049f138 3098 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3099 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3100 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3101 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3102 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3103
3e0629cb 3104
fa417f7b
EC		 3105 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3106 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3107 if (!is_vlan) {
3ef967a4 3108 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3109 } else {
3ef967a4 3110 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3111 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3112 }
fa417f7b 3113 } else {
fd10ed8e
JM		 3114 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3115 sl_to_vl(to_mdev(ib_dev),
3116 sqp->ud_header.lrh.service_level,
3117 sqp->qp.port);
3118 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3119 return -EINVAL;
fa417f7b
EC		 3120 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3121 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3122 }
e622f2f4 3123 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 3124 if (!sqp->qp.ibqp.qp_num)
3125 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3126 else
e622f2f4 3127 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 3128 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3129 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3130 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3131 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3132 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3133 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3134
3135 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3136
3137 if (0) {
987c8f8f 3138 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3139 for (i = 0; i < header_size / 4; ++i) {
3140 if (i % 8 == 0)
987c8f8f
SP		 3141 pr_err(" [%02x] ", i * 4);
3142 pr_cont(" %08x",
3143 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3144 if ((i + 1) % 8 == 0)
987c8f8f 3145 pr_cont("\n");
225c7b1f 3146 }
987c8f8f 3147 pr_err("\n");
225c7b1f
RD		 3148 }
3149
e61ef241
RD		 3150 /*
3151 * Inline data segments may not cross a 64 byte boundary. If
3152 * our UD header is bigger than the space available up to the
3153 * next 64 byte boundary in the WQE, use two inline data
3154 * segments to hold the UD header.
3155 */
3156 spc = MLX4_INLINE_ALIGN -
3157 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3158 if (header_size <= spc) {
3159 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3160 memcpy(inl + 1, sqp->header_buf, header_size);
3161 i = 1;
3162 } else {
3163 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3164 memcpy(inl + 1, sqp->header_buf, spc);
3165
3166 inl = (void *) (inl + 1) + spc;
3167 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3168 /*
3169 * Need a barrier here to make sure all the data is
3170 * visible before the byte_count field is set.
3171 * Otherwise the HCA prefetcher could grab the 64-byte
3172 * chunk with this inline segment and get a valid (!=
3173 * 0xffffffff) byte count but stale data, and end up
3174 * generating a packet with bad headers.
3175 *
3176 * The first inline segment's byte_count field doesn't
3177 * need a barrier, because it comes after a
3178 * control/MLX segment and therefore is at an offset
3179 * of 16 mod 64.
3180 */
3181 wmb();
3182 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3183 i = 2;
3184 }
225c7b1f 3185
f438000f
RD		 3186 *mlx_seg_len =
3187 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3188 return 0;
225c7b1f
RD		 3189}
3190
3191static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3192{
3193 unsigned cur;
3194 struct mlx4_ib_cq *cq;
3195
3196 cur = wq->head - wq->tail;
0e6e7416 3197 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3198 return 0;
3199
3200 cq = to_mcq(ib_cq);
3201 spin_lock(&cq->lock);
3202 cur = wq->head - wq->tail;
3203 spin_unlock(&cq->lock);
3204
0e6e7416 3205 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3206}
3207
95d04f07
RD		 3208static __be32 convert_access(int acc)
3209{
6ff63e19
SM		 3210 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3211 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3212 (acc & IB_ACCESS_REMOTE_WRITE ?
3213 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3214 (acc & IB_ACCESS_REMOTE_READ ?
3215 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3216 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3217 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3218}
3219
1b2cd0fc 3220static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
f696bf6d 3221 const struct ib_reg_wr *wr)
1b2cd0fc
SG		 3222{
3223 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3224
3225 fseg->flags = convert_access(wr->access);
3226 fseg->mem_key = cpu_to_be32(wr->key);
3227 fseg->buf_list = cpu_to_be64(mr->page_map);
3228 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3229 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3230 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3231 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3232 fseg->reserved[0] = 0;
3233 fseg->reserved[1] = 0;
3234}
3235
95d04f07
RD		 3236static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3237{
aee38fad
SM		 3238 memset(iseg, 0, sizeof(*iseg));
3239 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3240}
3241
0fbfa6a9
RD		 3242static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3243 u64 remote_addr, u32 rkey)
3244{
3245 rseg->raddr = cpu_to_be64(remote_addr);
3246 rseg->rkey = cpu_to_be32(rkey);
3247 rseg->reserved = 0;
3248}
3249
e622f2f4 3250static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
f696bf6d 3251 const struct ib_atomic_wr *wr)
0fbfa6a9 3252{
e622f2f4
CH		 3253 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3254 aseg->swap_add = cpu_to_be64(wr->swap);
3255 aseg->compare = cpu_to_be64(wr->compare_add);
3256 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3257 aseg->swap_add = cpu_to_be64(wr->compare_add);
3258 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3259 } else {
e622f2f4 3260 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3261 aseg->compare = 0;
3262 }
3263
3264}
3265
6fa8f719 3266static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
f696bf6d 3267 const struct ib_atomic_wr *wr)
6fa8f719 3268{
e622f2f4
CH		 3269 aseg->swap_add = cpu_to_be64(wr->swap);
3270 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3271 aseg->compare = cpu_to_be64(wr->compare_add);
3272 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3273}
3274
0fbfa6a9 3275static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3276 const struct ib_ud_wr *wr)
0fbfa6a9 3277{
e622f2f4
CH		 3278 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3279 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3280 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3281 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3282 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3283}
3284
1ffeb2eb
JM		 3285static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3286 struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3287 const struct ib_ud_wr *wr,
97982f5a 3288 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3289{
e622f2f4 3290 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3291 struct mlx4_av sqp_av = {0};
3292 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3293
3294 /* force loopback */
3295 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3296 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3297 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3298 cpu_to_be32(0xf0000000);
3299
3300 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3301 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3302 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3303 else
c73c8b1e 3304 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3305 /* Use QKEY from the QP context, which is set by master */
3306 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3307}
3308
f696bf6d
BVA		 3309static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3310 unsigned *mlx_seg_len)
1ffeb2eb
JM		 3311{
3312 struct mlx4_wqe_inline_seg *inl = wqe;
3313 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3314 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3315 int spc;
3316 int i;
3317
3318 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3319 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3320 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3321 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3322 memcpy(hdr.mac, ah->av.eth.mac, 6);
3323 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3324
3325 spc = MLX4_INLINE_ALIGN -
3326 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3327 if (sizeof (hdr) <= spc) {
3328 memcpy(inl + 1, &hdr, sizeof (hdr));
3329 wmb();
3330 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3331 i = 1;
3332 } else {
3333 memcpy(inl + 1, &hdr, spc);
3334 wmb();
3335 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3336
3337 inl = (void *) (inl + 1) + spc;
3338 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3339 wmb();
3340 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3341 i = 2;
3342 }
3343
3344 *mlx_seg_len =
3345 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3346}
3347
6e694ea3
JM		 3348static void set_mlx_icrc_seg(void *dseg)
3349{
3350 u32 *t = dseg;
3351 struct mlx4_wqe_inline_seg *iseg = dseg;
3352
3353 t[1] = 0;
3354
3355 /*
3356 * Need a barrier here before writing the byte_count field to
3357 * make sure that all the data is visible before the
3358 * byte_count field is set. Otherwise, if the segment begins
3359 * a new cacheline, the HCA prefetcher could grab the 64-byte
3360 * chunk and get a valid (!= * 0xffffffff) byte count but
3361 * stale data, and end up sending the wrong data.
3362 */
3363 wmb();
3364
3365 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3366}
3367
3368static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3369{
d420d9e3
RD		 3370 dseg->lkey = cpu_to_be32(sg->lkey);
3371 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3372
3373 /*
3374 * Need a barrier here before writing the byte_count field to
3375 * make sure that all the data is visible before the
3376 * byte_count field is set. Otherwise, if the segment begins
3377 * a new cacheline, the HCA prefetcher could grab the 64-byte
3378 * chunk and get a valid (!= * 0xffffffff) byte count but
3379 * stale data, and end up sending the wrong data.
3380 */
3381 wmb();
3382
3383 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3384}
3385
2242fa4f
RD		 3386static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3387{
3388 dseg->byte_count = cpu_to_be32(sg->length);
3389 dseg->lkey = cpu_to_be32(sg->lkey);
3390 dseg->addr = cpu_to_be64(sg->addr);
3391}
3392
f696bf6d
BVA		 3393static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3394 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3395 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3396{
e622f2f4 3397 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3398
417608c2
EC		 3399 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3400 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3401
3402 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3403 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3404 return -EINVAL;
3405
e622f2f4 3406 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3407
e622f2f4 3408 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3409 *lso_seg_len = halign;
3410 return 0;
3411}
3412
f696bf6d 3413static __be32 send_ieth(const struct ib_send_wr *wr)
95d04f07
RD		 3414{
3415 switch (wr->opcode) {
3416 case IB_WR_SEND_WITH_IMM:
3417 case IB_WR_RDMA_WRITE_WITH_IMM:
3418 return wr->ex.imm_data;
3419
3420 case IB_WR_SEND_WITH_INV:
3421 return cpu_to_be32(wr->ex.invalidate_rkey);
3422
3423 default:
3424 return 0;
3425 }
3426}
3427
1ffeb2eb
JM		 3428static void add_zero_len_inline(void *wqe)
3429{
3430 struct mlx4_wqe_inline_seg *inl = wqe;
3431 memset(wqe, 0, 16);
3432 inl->byte_count = cpu_to_be32(1 << 31);
3433}
3434
d34ac5cd
BVA		 3435static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3436 const struct ib_send_wr **bad_wr, bool drain)
225c7b1f
RD		 3437{
3438 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3439 void *wqe;
3440 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3441 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3442 unsigned long flags;
3443 int nreq;
3444 int err = 0;
ea54b10c 3445 unsigned ind;
ea54b10c 3446 int uninitialized_var(size);
a3d8e159 3447 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 3448 __be32 dummy;
3449 __be32 *lso_wqe;
3450 __be32 uninitialized_var(lso_hdr_sz);
417608c2 3451 __be32 blh;
225c7b1f 3452 int i;
35f05dab 3453 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3454
e1b866c6
MS		 3455 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3456 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3457
3458 if (sqp->roce_v2_gsi) {
3459 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3460 enum ib_gid_type gid_type;
e1b866c6
MS		 3461 union ib_gid gid;
3462
a748d60d
TB		 3463 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3464 ah->av.ib.gid_index,
3465 &gid, &gid_type))
3466 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3467 to_mqp(sqp->roce_v2_gsi) : qp;
3468 else
e1b866c6
MS		 3469 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3470 ah->av.ib.gid_index);
e1b866c6
MS		 3471 }
3472 }
3473
96db0e03 3474 spin_lock_irqsave(&qp->sq.lock, flags);
1975acd9
YH		 3475 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3476 !drain) {
35f05dab
YH		 3477 err = -EIO;
3478 *bad_wr = wr;
3479 nreq = 0;
3480 goto out;
3481 }
225c7b1f 3482
ea54b10c 3483 ind = qp->sq_next_wqe;
225c7b1f
RD		 3484
3485 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3486 lso_wqe = &dummy;
417608c2 3487 blh = 0;
0fd7e1d8 3488
225c7b1f
RD		 3489 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3490 err = -ENOMEM;
3491 *bad_wr = wr;
3492 goto out;
3493 }
3494
3495 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3496 err = -EINVAL;
3497 *bad_wr = wr;
3498 goto out;
3499 }
3500
0e6e7416 3501 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3502 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3503
3504 ctrl->srcrb_flags =
3505 (wr->send_flags & IB_SEND_SIGNALED ?
3506 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3507 (wr->send_flags & IB_SEND_SOLICITED ?
3508 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3509 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3510 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3511 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3512 qp->sq_signal_bits;
3513
95d04f07 3514 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3515
3516 wqe += sizeof *ctrl;
3517 size = sizeof *ctrl / 16;
3518
1ffeb2eb
JM		 3519 switch (qp->mlx4_ib_qp_type) {
3520 case MLX4_IB_QPT_RC:
3521 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3522 switch (wr->opcode) {
3523 case IB_WR_ATOMIC_CMP_AND_SWP:
3524 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3525 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3526 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3527 atomic_wr(wr)->rkey);
225c7b1f
RD		 3528 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3529
e622f2f4 3530 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3531 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3532
225c7b1f
RD		 3533 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3534 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3535
3536 break;
3537
3538 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3539 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3540 atomic_wr(wr)->rkey);
6fa8f719
VS		 3541 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3542
e622f2f4 3543 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3544 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3545
3546 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3547 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3548
3549 break;
3550
3551 case IB_WR_RDMA_READ:
3552 case IB_WR_RDMA_WRITE:
3553 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3554 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3555 rdma_wr(wr)->rkey);
225c7b1f
RD		 3556 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3557 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3558 break;
95d04f07
RD		 3559
3560 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3561 ctrl->srcrb_flags |=
3562 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3563 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3564 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3565 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3566 break;
3567
1b2cd0fc
SG		 3568 case IB_WR_REG_MR:
3569 ctrl->srcrb_flags |=
3570 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3571 set_reg_seg(wqe, reg_wr(wr));
3572 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3573 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3574 break;
3575
225c7b1f
RD		 3576 default:
3577 /* No extra segments required for sends */
3578 break;
3579 }
3580 break;
3581
1ffeb2eb 3582 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3583 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3584 ctrl, &seglen);
1ffeb2eb
JM		 3585 if (unlikely(err)) {
3586 *bad_wr = wr;
3587 goto out;
3588 }
3589 wqe += seglen;
3590 size += seglen / 16;
3591 break;
3592 case MLX4_IB_QPT_TUN_SMI:
3593 case MLX4_IB_QPT_TUN_GSI:
3594 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3595 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3596 /* set the forced-loopback bit in the data seg av */
3597 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3598 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3599 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3600 break;
3601 case MLX4_IB_QPT_UD:
e622f2f4 3602 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3603 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3604 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3605
3606 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3607 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3608 &lso_hdr_sz, &blh);
b832be1e
EC		 3609 if (unlikely(err)) {
3610 *bad_wr = wr;
3611 goto out;
3612 }
0fd7e1d8 3613 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3614 wqe += seglen;
3615 size += seglen / 16;
3616 }
225c7b1f
RD		 3617 break;
3618
1ffeb2eb 3619 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3620 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3621 ctrl, &seglen);
1ffeb2eb
JM		 3622 if (unlikely(err)) {
3623 *bad_wr = wr;
3624 goto out;
3625 }
3626 wqe += seglen;
3627 size += seglen / 16;
3628 /* to start tunnel header on a cache-line boundary */
3629 add_zero_len_inline(wqe);
3630 wqe += 16;
3631 size++;
e622f2f4 3632 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3633 wqe += seglen;
3634 size += seglen / 16;
3635 break;
3636 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3637 case MLX4_IB_QPT_PROXY_GSI:
3638 /* If we are tunneling special qps, this is a UD qp.
3639 * In this case we first add a UD segment targeting
3640 * the tunnel qp, and then add a header with address
3641 * information */
e622f2f4
CH		 3642 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3643 ud_wr(wr),
97982f5a 3644 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3645 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3646 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3647 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3648 wqe += seglen;
3649 size += seglen / 16;
3650 break;
3651
3652 case MLX4_IB_QPT_SMI:
3653 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3654 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3655 &seglen);
f438000f 3656 if (unlikely(err)) {
225c7b1f
RD		 3657 *bad_wr = wr;
3658 goto out;
3659 }
f438000f
RD		 3660 wqe += seglen;
3661 size += seglen / 16;
225c7b1f
RD		 3662 break;
3663
3664 default:
3665 break;
3666 }
3667
6e694ea3
JM		 3668 /*
3669 * Write data segments in reverse order, so as to
3670 * overwrite cacheline stamp last within each
3671 * cacheline. This avoids issues with WQE
3672 * prefetching.
3673 */
225c7b1f 3674
6e694ea3
JM		 3675 dseg = wqe;
3676 dseg += wr->num_sge - 1;
3677 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3678
3679 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3680 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3681 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3682 qp->mlx4_ib_qp_type &
3683 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3684 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3685 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3686 }
3687
6e694ea3
JM		 3688 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3689 set_data_seg(dseg, wr->sg_list + i);
3690
0fd7e1d8
RD		 3691 /*
3692 * Possibly overwrite stamping in cacheline with LSO
3693 * segment only after making sure all data segments
3694 * are written.
3695 */
3696 wmb();
3697 *lso_wqe = lso_hdr_sz;
3698
224e92e0
BB		 3699 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3700 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3701
3702 /*
3703 * Make sure descriptor is fully written before
3704 * setting ownership bit (because HW can start
3705 * executing as soon as we do).
3706 */
3707 wmb();
3708
59b0ed12 3709 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3710 *bad_wr = wr;
225c7b1f
RD		 3711 err = -EINVAL;
3712 goto out;
3713 }
3714
3715 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3716 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416
RD		 3717
3718 /*
3719 * We can improve latency by not stamping the last
3720 * send queue WQE until after ringing the doorbell, so
3721 * only stamp here if there are still more WQEs to post.
3722 */
f95ccffc
JM		 3723 if (wr->next)
3724 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3725 ind++;
225c7b1f
RD		 3726 }
3727
3728out:
3729 if (likely(nreq)) {
3730 qp->sq.head += nreq;
3731
3732 /*
3733 * Make sure that descriptors are written before
3734 * doorbell record.
3735 */
3736 wmb();
3737
97d82a48
SK		 3738 writel_relaxed(qp->doorbell_qpn,
3739 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
225c7b1f
RD		 3740
3741 /*
3742 * Make sure doorbells don't leak out of SQ spinlock
3743 * and reach the HCA out of order.
3744 */
3745 mmiowb();
0e6e7416 3746
f95ccffc 3747 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
ea54b10c 3748
ea54b10c 3749 qp->sq_next_wqe = ind;
225c7b1f
RD		 3750 }
3751
96db0e03 3752 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3753
3754 return err;
3755}
3756
d34ac5cd
BVA		 3757int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3758 const struct ib_send_wr **bad_wr)
1975acd9
YH		 3759{
3760 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3761}
3762
d34ac5cd
BVA		 3763static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3764 const struct ib_recv_wr **bad_wr, bool drain)
225c7b1f
RD		 3765{
3766 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3767 struct mlx4_wqe_data_seg *scat;
3768 unsigned long flags;
3769 int err = 0;
3770 int nreq;
3771 int ind;
1ffeb2eb 3772 int max_gs;
225c7b1f 3773 int i;
35f05dab 3774 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3775
1ffeb2eb 3776 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3777 spin_lock_irqsave(&qp->rq.lock, flags);
3778
1975acd9
YH		 3779 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3780 !drain) {
35f05dab
YH		 3781 err = -EIO;
3782 *bad_wr = wr;
3783 nreq = 0;
3784 goto out;
3785 }
3786
0e6e7416 3787 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3788
3789 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3790 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3791 err = -ENOMEM;
3792 *bad_wr = wr;
3793 goto out;
3794 }
3795
3796 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3797 err = -EINVAL;
3798 *bad_wr = wr;
3799 goto out;
3800 }
3801
3802 scat = get_recv_wqe(qp, ind);
3803
1ffeb2eb
JM		 3804 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3805 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3806 ib_dma_sync_single_for_device(ibqp->device,
3807 qp->sqp_proxy_rcv[ind].map,
3808 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3809 DMA_FROM_DEVICE);
3810 scat->byte_count =
3811 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3812 /* use dma lkey from upper layer entry */
3813 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3814 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3815 scat++;
3816 max_gs--;
3817 }
3818
2242fa4f
RD		 3819 for (i = 0; i < wr->num_sge; ++i)
3820 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3821
1ffeb2eb 3822 if (i < max_gs) {
225c7b1f
RD		 3823 scat[i].byte_count = 0;
3824 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3825 scat[i].addr = 0;
3826 }
3827
3828 qp->rq.wrid[ind] = wr->wr_id;
3829
0e6e7416 3830 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3831 }
3832
3833out:
3834 if (likely(nreq)) {
3835 qp->rq.head += nreq;
3836
3837 /*
3838 * Make sure that descriptors are written before
3839 * doorbell record.
3840 */
3841 wmb();
3842
3843 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3844 }
3845
3846 spin_unlock_irqrestore(&qp->rq.lock, flags);
3847
3848 return err;
3849}
6a775e2b 3850
d34ac5cd
BVA		 3851int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3852 const struct ib_recv_wr **bad_wr)
1975acd9
YH		 3853{
3854 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3855}
3856
6a775e2b
JM		 3857static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3858{
3859 switch (mlx4_state) {
3860 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3861 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3862 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3863 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3864 case MLX4_QP_STATE_SQ_DRAINING:
3865 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3866 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3867 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3868 default: return -1;
3869 }
3870}
3871
3872static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3873{
3874 switch (mlx4_mig_state) {
3875 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3876 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3877 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3878 default: return -1;
3879 }
3880}
3881
3882static int to_ib_qp_access_flags(int mlx4_flags)
3883{
3884 int ib_flags = 0;
3885
3886 if (mlx4_flags & MLX4_QP_BIT_RRE)
3887 ib_flags |= IB_ACCESS_REMOTE_READ;
3888 if (mlx4_flags & MLX4_QP_BIT_RWE)
3889 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3890 if (mlx4_flags & MLX4_QP_BIT_RAE)
3891 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3892
3893 return ib_flags;
3894}
3895
71d53ab4 3896static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3897 struct rdma_ah_attr *ah_attr,
71d53ab4 3898 struct mlx4_qp_path *path)
6a775e2b 3899{
4c3eb3ca 3900 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3901 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 3902
d8966fcd 3903 memset(ah_attr, 0, sizeof(*ah_attr));
d8966fcd 3904 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b 3905 return;
f1228867 3906 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
6a775e2b 3907
44c58487 3908 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 3909 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3910 ((path->sched_queue & 4) << 1));
4c3eb3ca 3911 else
d8966fcd 3912 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 3913 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 3914
d8966fcd
DC		 3915 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3916 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3917 rdma_ah_set_static_rate(ah_attr,
3918 path->static_rate ? path->static_rate - 5 : 0);
3919 if (path->grh_mylmc & (1 << 7)) {
3920 rdma_ah_set_grh(ah_attr, NULL,
3921 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3922 path->mgid_index,
3923 path->hop_limit,
3924 (be32_to_cpu(path->tclass_flowlabel)
3925 >> 20) & 0xff);
3926 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 3927 }
3928}
3929
3930int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3931 struct ib_qp_init_attr *qp_init_attr)
3932{
3933 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3934 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3935 struct mlx4_qp_context context;
3936 int mlx4_state;
0df67030
DB		 3937 int err = 0;
3938
3078f5f1
GL		 3939 if (ibqp->rwq_ind_tbl)
3940 return -EOPNOTSUPP;
3941
0df67030 3942 mutex_lock(&qp->mutex);
6a775e2b
JM		 3943
3944 if (qp->state == IB_QPS_RESET) {
3945 qp_attr->qp_state = IB_QPS_RESET;
3946 goto done;
3947 }
3948
3949 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3950 if (err) {
3951 err = -EINVAL;
3952 goto out;
3953 }
6a775e2b
JM		 3954
3955 mlx4_state = be32_to_cpu(context.flags) >> 28;
3956
0df67030
DB		 3957 qp->state = to_ib_qp_state(mlx4_state);
3958 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3959 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3960 qp_attr->path_mig_state =
3961 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3962 qp_attr->qkey = be32_to_cpu(context.qkey);
3963 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3964 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3965 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3966 qp_attr->qp_access_flags =
3967 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3968
3969 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 3970 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3971 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 3972 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 3973 qp_attr->alt_port_num =
3974 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 3975 }
3976
3977 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3978 if (qp_attr->qp_state == IB_QPS_INIT)
3979 qp_attr->port_num = qp->port;
3980 else
3981 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3982
3983 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3984 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3985
3986 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3987
3988 qp_attr->max_dest_rd_atomic =
3989 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3990 qp_attr->min_rnr_timer =
3991 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3992 qp_attr->timeout = context.pri_path.ackto >> 3;
3993 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3994 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3995 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3996
3997done:
3998 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3999 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4000 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4001
6a775e2b 4002 if (!ibqp->uobject) {
7f5eb9bb
RD		 4003 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4004 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4005 } else {
4006 qp_attr->cap.max_send_wr = 0;
4007 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4008 }
4009
7f5eb9bb
RD		 4010 /*
4011 * We don't support inline sends for kernel QPs (yet), and we
4012 * don't know what userspace's value should be.
4013 */
4014 qp_attr->cap.max_inline_data = 0;
4015
4016 qp_init_attr->cap = qp_attr->cap;
4017
521e575b
RL		 4018 qp_init_attr->create_flags = 0;
4019 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4020 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4021
4022 if (qp->flags & MLX4_IB_QP_LSO)
4023 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4024
c1c98501
MB		 4025 if (qp->flags & MLX4_IB_QP_NETIF)
4026 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4027
46db567d
DB		 4028 qp_init_attr->sq_sig_type =
4029 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4030 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4031
0df67030
DB		 4032out:
4033 mutex_unlock(&qp->mutex);
4034 return err;
6a775e2b
JM		 4035}
4036
400b1ebc
GL		 4037struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4038 struct ib_wq_init_attr *init_attr,
4039 struct ib_udata *udata)
4040{
4041 struct mlx4_ib_dev *dev;
4042 struct ib_qp_init_attr ib_qp_init_attr;
4043 struct mlx4_ib_qp *qp;
4044 struct mlx4_ib_create_wq ucmd;
4045 int err, required_cmd_sz;
4046
4047 if (!(udata && pd->uobject))
4048 return ERR_PTR(-EINVAL);
4049
078b3573
GL		 4050 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4051 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4052 if (udata->inlen < required_cmd_sz) {
4053 pr_debug("invalid inlen\n");
4054 return ERR_PTR(-EINVAL);
4055 }
4056
4057 if (udata->inlen > sizeof(ucmd) &&
4058 !ib_is_udata_cleared(udata, sizeof(ucmd),
4059 udata->inlen - sizeof(ucmd))) {
4060 pr_debug("inlen is not supported\n");
4061 return ERR_PTR(-EOPNOTSUPP);
4062 }
4063
4064 if (udata->outlen)
4065 return ERR_PTR(-EOPNOTSUPP);
4066
4067 dev = to_mdev(pd->device);
4068
4069 if (init_attr->wq_type != IB_WQT_RQ) {
4070 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4071 return ERR_PTR(-EOPNOTSUPP);
4072 }
4073
6d06c9aa 4074 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) {
400b1ebc
GL		 4075 pr_debug("unsupported create_flags %u\n",
4076 init_attr->create_flags);
4077 return ERR_PTR(-EOPNOTSUPP);
4078 }
4079
4080 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4081 if (!qp)
4082 return ERR_PTR(-ENOMEM);
4083
4084 qp->pri.vid = 0xFFFF;
4085 qp->alt.vid = 0xFFFF;
4086
4087 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4088 ib_qp_init_attr.qp_context = init_attr->wq_context;
4089 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4090 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4091 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4092 ib_qp_init_attr.recv_cq = init_attr->cq;
4093 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4094
6d06c9aa
GL		 4095 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4096 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4097
400b1ebc
GL		 4098 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4099 udata, 0, &qp);
4100 if (err) {
4101 kfree(qp);
4102 return ERR_PTR(err);
4103 }
4104
4105 qp->ibwq.event_handler = init_attr->event_handler;
4106 qp->ibwq.wq_num = qp->mqp.qpn;
4107 qp->ibwq.state = IB_WQS_RESET;
4108
4109 return &qp->ibwq;
4110}
4111
4112static int ib_wq2qp_state(enum ib_wq_state state)
4113{
4114 switch (state) {
4115 case IB_WQS_RESET:
4116 return IB_QPS_RESET;
4117 case IB_WQS_RDY:
4118 return IB_QPS_RTR;
4119 default:
4120 return IB_QPS_ERR;
4121 }
4122}
4123
4124static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4125{
4126 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4127 enum ib_qp_state qp_cur_state;
4128 enum ib_qp_state qp_new_state;
4129 int attr_mask;
4130 int err;
4131
4132 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4133 * the WQ logic state.
4134 */
4135 qp_cur_state = qp->state;
4136 qp_new_state = ib_wq2qp_state(new_state);
4137
4138 if (ib_wq2qp_state(new_state) == qp_cur_state)
4139 return 0;
4140
4141 if (new_state == IB_WQS_RDY) {
4142 struct ib_qp_attr attr = {};
4143
4144 attr.port_num = qp->port;
4145 attr_mask = IB_QP_PORT;
4146
4147 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4148 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4149 if (err) {
4150 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4151 ibwq->wq_num);
4152 return err;
4153 }
4154
4155 qp_cur_state = IB_QPS_INIT;
4156 }
4157
4158 attr_mask = 0;
4159 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4160 qp_cur_state, qp_new_state);
4161
4162 if (err && (qp_cur_state == IB_QPS_INIT)) {
4163 qp_new_state = IB_QPS_RESET;
4164 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4165 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4166 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4167 ibwq->wq_num);
4168 qp_new_state = IB_QPS_INIT;
4169 }
4170 }
4171
4172 qp->state = qp_new_state;
4173
4174 return err;
4175}
4176
4177int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4178 u32 wq_attr_mask, struct ib_udata *udata)
4179{
4180 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4181 struct mlx4_ib_modify_wq ucmd = {};
4182 size_t required_cmd_sz;
4183 enum ib_wq_state cur_state, new_state;
4184 int err = 0;
4185
4186 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4187 sizeof(ucmd.reserved);
4188 if (udata->inlen < required_cmd_sz)
4189 return -EINVAL;
4190
4191 if (udata->inlen > sizeof(ucmd) &&
4192 !ib_is_udata_cleared(udata, sizeof(ucmd),
4193 udata->inlen - sizeof(ucmd)))
4194 return -EOPNOTSUPP;
4195
4196 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4197 return -EFAULT;
4198
4199 if (ucmd.comp_mask || ucmd.reserved)
4200 return -EOPNOTSUPP;
4201
4202 if (wq_attr_mask & IB_WQ_FLAGS)
4203 return -EOPNOTSUPP;
4204
4205 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4206 ibwq->state;
4207 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4208
4209 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4210 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4211 return -EINVAL;
4212
4213 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4214 return -EINVAL;
4215
4216 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4217 return -EINVAL;
4218
3078f5f1
GL		 4219 /* Need to protect against the parent RSS which also may modify WQ
4220 * state.
4221 */
4222 mutex_lock(&qp->mutex);
4223
400b1ebc
GL		 4224 /* Can update HW state only if a RSS QP has already associated to this
4225 * WQ, so we can apply its port on the WQ.
4226 */
4227 if (qp->rss_usecnt)
4228 err = _mlx4_ib_modify_wq(ibwq, new_state);
4229
4230 if (!err)
4231 ibwq->state = new_state;
4232
3078f5f1
GL		 4233 mutex_unlock(&qp->mutex);
4234
400b1ebc
GL		 4235 return err;
4236}
4237
4238int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4239{
4240 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4241 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4242
4243 if (qp->counter_index)
4244 mlx4_ib_free_qp_counter(dev, qp);
4245
4246 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4247
4248 kfree(qp);
4249
4250 return 0;
4251}
b8d46ca0
GL		 4252
4253struct ib_rwq_ind_table
4254*mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4255 struct ib_rwq_ind_table_init_attr *init_attr,
4256 struct ib_udata *udata)
4257{
4258 struct ib_rwq_ind_table *rwq_ind_table;
4259 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4260 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4261 unsigned int base_wqn;
4262 size_t min_resp_len;
4263 int i;
4264 int err;
4265
4266 if (udata->inlen > 0 &&
4267 !ib_is_udata_cleared(udata, 0,
4268 udata->inlen))
4269 return ERR_PTR(-EOPNOTSUPP);
4270
4271 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4272 if (udata->outlen && udata->outlen < min_resp_len)
4273 return ERR_PTR(-EINVAL);
4274
4275 if (ind_tbl_size >
4276 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4277 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4278 ind_tbl_size,
4279 device->attrs.rss_caps.max_rwq_indirection_table_size);
4280 return ERR_PTR(-EINVAL);
4281 }
4282
4283 base_wqn = init_attr->ind_tbl[0]->wq_num;
4284
4285 if (base_wqn % ind_tbl_size) {
4286 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4287 base_wqn);
4288 return ERR_PTR(-EINVAL);
4289 }
4290
4291 for (i = 1; i < ind_tbl_size; i++) {
4292 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4293 pr_debug("indirection table's WQNs aren't consecutive\n");
4294 return ERR_PTR(-EINVAL);
4295 }
4296 }
4297
4298 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4299 if (!rwq_ind_table)
4300 return ERR_PTR(-ENOMEM);
4301
4302 if (udata->outlen) {
4303 resp.response_length = offsetof(typeof(resp), response_length) +
4304 sizeof(resp.response_length);
4305 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4306 if (err)
4307 goto err;
4308 }
4309
4310 return rwq_ind_table;
4311
4312err:
4313 kfree(rwq_ind_table);
4314 return ERR_PTR(err);
4315}
4316
4317int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4318{
4319 kfree(ib_rwq_ind_tbl);
4320 return 0;
4321}
1975acd9
YH		 4322
4323struct mlx4_ib_drain_cqe {
4324 struct ib_cqe cqe;
4325 struct completion done;
4326};
4327
4328static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4329{
4330 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4331 struct mlx4_ib_drain_cqe,
4332 cqe);
4333
4334 complete(&cqe->done);
4335}
4336
4337/* This function returns only once the drained WR was completed */
4338static void handle_drain_completion(struct ib_cq *cq,
4339 struct mlx4_ib_drain_cqe *sdrain,
4340 struct mlx4_ib_dev *dev)
4341{
4342 struct mlx4_dev *mdev = dev->dev;
4343
4344 if (cq->poll_ctx == IB_POLL_DIRECT) {
4345 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4346 ib_process_cq_direct(cq, -1);
4347 return;
4348 }
4349
4350 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4351 struct mlx4_ib_cq *mcq = to_mcq(cq);
4352 bool triggered = false;
4353 unsigned long flags;
4354
4355 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4356 /* Make sure that the CQ handler won't run if wasn't run yet */
4357 if (!mcq->mcq.reset_notify_added)
4358 mcq->mcq.reset_notify_added = 1;
4359 else
4360 triggered = true;
4361 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4362
4363 if (triggered) {
4364 /* Wait for any scheduled/running task to be ended */
4365 switch (cq->poll_ctx) {
4366 case IB_POLL_SOFTIRQ:
4367 irq_poll_disable(&cq->iop);
4368 irq_poll_enable(&cq->iop);
4369 break;
4370 case IB_POLL_WORKQUEUE:
4371 cancel_work_sync(&cq->work);
4372 break;
4373 default:
4374 WARN_ON_ONCE(1);
4375 }
4376 }
4377
4378 /* Run the CQ handler - this makes sure that the drain WR will
4379 * be processed if wasn't processed yet.
4380 */
4381 mcq->mcq.comp(&mcq->mcq);
4382 }
4383
4384 wait_for_completion(&sdrain->done);
4385}
4386
4387void mlx4_ib_drain_sq(struct ib_qp *qp)
4388{
4389 struct ib_cq *cq = qp->send_cq;
4390 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4391 struct mlx4_ib_drain_cqe sdrain;
d34ac5cd 4392 const struct ib_send_wr *bad_swr;
1975acd9
YH		 4393 struct ib_rdma_wr swr = {
4394 .wr = {
4395 .next = NULL,
4396 { .wr_cqe = &sdrain.cqe, },
4397 .opcode = IB_WR_RDMA_WRITE,
4398 },
4399 };
4400 int ret;
4401 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4402 struct mlx4_dev *mdev = dev->dev;
4403
4404 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4405 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4406 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4407 return;
4408 }
4409
4410 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4411 init_completion(&sdrain.done);
4412
4413 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4414 if (ret) {
4415 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4416 return;
4417 }
4418
4419 handle_drain_completion(cq, &sdrain, dev);
4420}
4421
4422void mlx4_ib_drain_rq(struct ib_qp *qp)
4423{
4424 struct ib_cq *cq = qp->recv_cq;
4425 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4426 struct mlx4_ib_drain_cqe rdrain;
d34ac5cd
BVA		 4427 struct ib_recv_wr rwr = {};
4428 const struct ib_recv_wr *bad_rwr;
1975acd9
YH		 4429 int ret;
4430 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4431 struct mlx4_dev *mdev = dev->dev;
4432
4433 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4434 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4435 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4436 return;
4437 }
4438
4439 rwr.wr_cqe = &rdrain.cqe;
4440 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4441 init_completion(&rdrain.done);
4442
4443 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4444 if (ret) {
4445 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4446 return;
4447 }
4448
4449 handle_drain_completion(cq, &rdrain, dev);
4450}
Linux 6.x block layer and io_uring tree(s)