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Merge branch 'from-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
225c7b1f 44
2f48485d 45#include <linux/mlx4/driver.h>
225c7b1f
RD		 46#include <linux/mlx4/qp.h>
47
48#include "mlx4_ib.h"
9ce28a20 49#include <rdma/mlx4-abi.h>
225c7b1f 50
35f05dab
YH		 51static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
3078f5f1 55static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
35f05dab 56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
79struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 86 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 117};
118
400b1ebc
GL		 119enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122};
123
225c7b1f
RD		 124static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125{
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127}
128
1ffeb2eb
JM		 129static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130{
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
47605df9
JM		 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 137}
138
225c7b1f
RD		 139static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140{
47605df9
JM		 141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
e1b866c6
MS		 160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 164}
165
1ffeb2eb 166/* used for INIT/CLOSE port logic */
225c7b1f
RD		 167static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168{
47605df9
JM		 169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
225c7b1f
RD		 188}
189
190static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191{
1c69fc2a 192 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 193}
194
195static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198}
199
200static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201{
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203}
204
0e6e7416
RD		 205/*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 207 * first four bytes of every 64 byte chunk with
208 * 0x7FFFFFF | (invalid_ownership_value << 31).
209 *
210 * When the max work request size is less than or equal to the WQE
211 * basic block size, as an optimization, we can stamp all WQEs with
212 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 213 */
ea54b10c 214static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 215{
d2ae16d5 216 __be32 *wqe;
0e6e7416 217 int i;
ea54b10c
JM		 218 int s;
219 int ind;
220 void *buf;
221 __be32 stamp;
9670e553 222 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 223
ea54b10c 224 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 225 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 226 for (i = 0; i < s; i += 64) {
227 ind = (i >> qp->sq.wqe_shift) + n;
228 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
229 cpu_to_be32(0xffffffff);
230 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
231 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
232 *wqe = stamp;
233 }
234 } else {
9670e553 235 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
224e92e0 236 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
ea54b10c
JM		 237 for (i = 64; i < s; i += 64) {
238 wqe = buf + i;
d2ae16d5 239 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 240 }
241 }
242}
243
244static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
245{
246 struct mlx4_wqe_ctrl_seg *ctrl;
247 struct mlx4_wqe_inline_seg *inl;
248 void *wqe;
249 int s;
250
251 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
252 s = sizeof(struct mlx4_wqe_ctrl_seg);
253
254 if (qp->ibqp.qp_type == IB_QPT_UD) {
255 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
256 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
257 memset(dgram, 0, sizeof *dgram);
258 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
259 s += sizeof(struct mlx4_wqe_datagram_seg);
260 }
261
262 /* Pad the remainder of the WQE with an inline data segment. */
263 if (size > s) {
264 inl = wqe + s;
265 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
266 }
267 ctrl->srcrb_flags = 0;
224e92e0 268 ctrl->qpn_vlan.fence_size = size / 16;
ea54b10c
JM		 269 /*
270 * Make sure descriptor is fully written before setting ownership bit
271 * (because HW can start executing as soon as we do).
272 */
273 wmb();
274
275 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
276 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 277
ea54b10c
JM		 278 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
279}
280
281/* Post NOP WQE to prevent wrap-around in the middle of WR */
282static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
283{
284 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
285 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
286 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
287 ind += s;
288 }
289 return ind;
0e6e7416
RD		 290}
291
225c7b1f
RD		 292static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
293{
294 struct ib_event event;
295 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
296
297 if (type == MLX4_EVENT_TYPE_PATH_MIG)
298 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
299
300 if (ibqp->event_handler) {
301 event.device = ibqp->device;
302 event.element.qp = ibqp;
303 switch (type) {
304 case MLX4_EVENT_TYPE_PATH_MIG:
305 event.event = IB_EVENT_PATH_MIG;
306 break;
307 case MLX4_EVENT_TYPE_COMM_EST:
308 event.event = IB_EVENT_COMM_EST;
309 break;
310 case MLX4_EVENT_TYPE_SQ_DRAINED:
311 event.event = IB_EVENT_SQ_DRAINED;
312 break;
313 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
314 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
315 break;
316 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
317 event.event = IB_EVENT_QP_FATAL;
318 break;
319 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
320 event.event = IB_EVENT_PATH_MIG_ERR;
321 break;
322 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
323 event.event = IB_EVENT_QP_REQ_ERR;
324 break;
325 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
326 event.event = IB_EVENT_QP_ACCESS_ERR;
327 break;
328 default:
987c8f8f 329 pr_warn("Unexpected event type %d "
225c7b1f
RD		 330 "on QP %06x\n", type, qp->qpn);
331 return;
332 }
333
334 ibqp->event_handler(&event, ibqp->qp_context);
335 }
336}
337
400b1ebc
GL		 338static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
339{
340 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
341 type, qp->qpn);
342}
343
1ffeb2eb 344static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 345{
346 /*
347 * UD WQEs must have a datagram segment.
348 * RC and UC WQEs might have a remote address segment.
349 * MLX WQEs need two extra inline data segments (for the UD
350 * header and space for the ICRC).
351 */
352 switch (type) {
1ffeb2eb 353 case MLX4_IB_QPT_UD:
225c7b1f 354 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 355 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 356 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 357 case MLX4_IB_QPT_PROXY_SMI_OWNER:
358 case MLX4_IB_QPT_PROXY_SMI:
359 case MLX4_IB_QPT_PROXY_GSI:
360 return sizeof (struct mlx4_wqe_ctrl_seg) +
361 sizeof (struct mlx4_wqe_datagram_seg) + 64;
362 case MLX4_IB_QPT_TUN_SMI_OWNER:
363 case MLX4_IB_QPT_TUN_GSI:
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_datagram_seg);
366
367 case MLX4_IB_QPT_UC:
225c7b1f
RD		 368 return sizeof (struct mlx4_wqe_ctrl_seg) +
369 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 370 case MLX4_IB_QPT_RC:
225c7b1f 371 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 372 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 373 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 374 case MLX4_IB_QPT_SMI:
375 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 376 return sizeof (struct mlx4_wqe_ctrl_seg) +
377 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 378 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
379 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 380 sizeof (struct mlx4_wqe_inline_seg),
381 sizeof (struct mlx4_wqe_data_seg)) +
382 ALIGN(4 +
383 sizeof (struct mlx4_wqe_inline_seg),
384 sizeof (struct mlx4_wqe_data_seg));
385 default:
386 return sizeof (struct mlx4_wqe_ctrl_seg);
387 }
388}
389
2446304d 390static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
ea30b966
MG		 391 int is_user, int has_rq, struct mlx4_ib_qp *qp,
392 u32 inl_recv_sz)
225c7b1f 393{
2446304d 394 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 395 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
396 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 397 return -EINVAL;
398
0a1405da 399 if (!has_rq) {
ea30b966 400 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 401 return -EINVAL;
2446304d 402
0e6e7416 403 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 404 } else {
ea30b966
MG		 405 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
406 sizeof(struct mlx4_wqe_data_seg);
407 u32 wqe_size;
408
a4cd7ed8 409 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 410 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
411 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 412 return -EINVAL;
413
0e6e7416 414 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 415 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 416 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
417 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 418 }
2446304d 419
fc2d0044
SG		 420 /* leave userspace return values as they were, so as not to break ABI */
421 if (is_user) {
422 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
423 cap->max_recv_sge = qp->rq.max_gs;
424 } else {
425 cap->max_recv_wr = qp->rq.max_post =
426 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
427 cap->max_recv_sge = min(qp->rq.max_gs,
428 min(dev->dev->caps.max_sq_sg,
429 dev->dev->caps.max_rq_sg));
430 }
2446304d
EC		 431
432 return 0;
433}
434
435static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
73898db0
HA		 436 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
437 bool shrink_wqe)
2446304d 438{
ea54b10c
JM		 439 int s;
440
2446304d 441 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 442 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
443 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 444 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 445 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
446 return -EINVAL;
447
448 /*
449 * For MLX transport we need 2 extra S/G entries:
450 * one for the header and one for the checksum at the end
451 */
1ffeb2eb
JM		 452 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
453 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 454 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
455 return -EINVAL;
456
ea54b10c
JM		 457 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
458 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 459 send_wqe_overhead(type, qp->flags);
225c7b1f 460
cd155c1c
RD		 461 if (s > dev->dev->caps.max_sq_desc_sz)
462 return -EINVAL;
463
0e6e7416 464 /*
ea54b10c
JM		 465 * Hermon supports shrinking WQEs, such that a single work
466 * request can include multiple units of 1 << wqe_shift. This
467 * way, work requests can differ in size, and do not have to
468 * be a power of 2 in size, saving memory and speeding up send
469 * WR posting. Unfortunately, if we do this then the
470 * wqe_index field in CQEs can't be used to look up the WR ID
471 * anymore, so we do this only if selective signaling is off.
472 *
473 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 474 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 475 * constant-sized WRs to make sure a WR is always fully within
476 * a single page-sized chunk.
477 *
478 * Finally, we use NOP work requests to pad the end of the
479 * work queue, to avoid wrap-around in the middle of WR. We
480 * set NEC bit to avoid getting completions with error for
481 * these NOP WRs, but since NEC is only supported starting
482 * with firmware 2.2.232, we use constant-sized WRs for older
483 * firmware.
484 *
485 * And, since MLX QPs only support SEND, we use constant-sized
486 * WRs in this case.
487 *
488 * We look for the smallest value of wqe_shift such that the
489 * resulting number of wqes does not exceed device
490 * capabilities.
491 *
492 * We set WQE size to at least 64 bytes, this way stamping
493 * invalidates each WQE.
0e6e7416 494 */
73898db0 495 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
ea54b10c 496 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 497 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
498 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
499 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 500 qp->sq.wqe_shift = ilog2(64);
501 else
502 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
503
504 for (;;) {
ea54b10c
JM		 505 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
506
507 /*
508 * We need to leave 2 KB + 1 WR of headroom in the SQ to
509 * allow HW to prefetch.
510 */
511 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
512 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
513 qp->sq_max_wqes_per_wr +
514 qp->sq_spare_wqes);
515
516 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
517 break;
518
519 if (qp->sq_max_wqes_per_wr <= 1)
520 return -EINVAL;
521
522 ++qp->sq.wqe_shift;
523 }
524
cd155c1c
RD		 525 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
526 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 527 send_wqe_overhead(type, qp->flags)) /
528 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 529
530 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
531 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 532 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
533 qp->rq.offset = 0;
0e6e7416 534 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 535 } else {
0e6e7416 536 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 537 qp->sq.offset = 0;
538 }
539
ea54b10c
JM		 540 cap->max_send_wr = qp->sq.max_post =
541 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 542 cap->max_send_sge = min(qp->sq.max_gs,
543 min(dev->dev->caps.max_sq_sg,
544 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 545 /* We don't support inline sends for kernel QPs (yet) */
546 cap->max_inline_data = 0;
225c7b1f
RD		 547
548 return 0;
549}
550
83904132
JM		 551static int set_user_sq_size(struct mlx4_ib_dev *dev,
552 struct mlx4_ib_qp *qp,
2446304d
EC		 553 struct mlx4_ib_create_qp *ucmd)
554{
83904132
JM		 555 /* Sanity check SQ size before proceeding */
556 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
557 ucmd->log_sq_stride >
558 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
559 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
560 return -EINVAL;
561
0e6e7416 562 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 563 qp->sq.wqe_shift = ucmd->log_sq_stride;
564
0e6e7416
RD		 565 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
566 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 567
568 return 0;
569}
570
1ffeb2eb
JM		 571static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
572{
573 int i;
574
575 qp->sqp_proxy_rcv =
576 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
577 GFP_KERNEL);
578 if (!qp->sqp_proxy_rcv)
579 return -ENOMEM;
580 for (i = 0; i < qp->rq.wqe_cnt; i++) {
581 qp->sqp_proxy_rcv[i].addr =
582 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
583 GFP_KERNEL);
584 if (!qp->sqp_proxy_rcv[i].addr)
585 goto err;
586 qp->sqp_proxy_rcv[i].map =
587 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
588 sizeof (struct mlx4_ib_proxy_sqp_hdr),
589 DMA_FROM_DEVICE);
cc47d369
SO		 590 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
591 kfree(qp->sqp_proxy_rcv[i].addr);
592 goto err;
593 }
1ffeb2eb
JM		 594 }
595 return 0;
596
597err:
598 while (i > 0) {
599 --i;
600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
601 sizeof (struct mlx4_ib_proxy_sqp_hdr),
602 DMA_FROM_DEVICE);
603 kfree(qp->sqp_proxy_rcv[i].addr);
604 }
605 kfree(qp->sqp_proxy_rcv);
606 qp->sqp_proxy_rcv = NULL;
607 return -ENOMEM;
608}
609
610static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
611{
612 int i;
613
614 for (i = 0; i < qp->rq.wqe_cnt; i++) {
615 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
616 sizeof (struct mlx4_ib_proxy_sqp_hdr),
617 DMA_FROM_DEVICE);
618 kfree(qp->sqp_proxy_rcv[i].addr);
619 }
620 kfree(qp->sqp_proxy_rcv);
621}
622
0a1405da
SH		 623static int qp_has_rq(struct ib_qp_init_attr *attr)
624{
625 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
626 return 0;
627
628 return !attr->srq;
629}
630
99ec41d0
JM		 631static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
632{
633 int i;
634 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 635 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
636 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 637 }
638 return 0;
639}
640
7b59f0f9
EBE		 641static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
642 struct mlx4_ib_qp *qp)
643{
644 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
645 mlx4_counter_free(dev->dev, qp->counter_index->index);
646 list_del(&qp->counter_index->list);
647 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
648
649 kfree(qp->counter_index);
650 qp->counter_index = NULL;
651}
652
3078f5f1
GL		 653static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
654 struct ib_qp_init_attr *init_attr,
655 struct mlx4_ib_create_qp_rss *ucmd)
656{
657 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
658 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
659
660 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
661 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
662 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
663 MLX4_EN_RSS_KEY_SIZE);
664 } else {
665 pr_debug("RX Hash function is not supported\n");
666 return (-EOPNOTSUPP);
667 }
668
4d02ebd9
GL		 669 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
670 MLX4_IB_RX_HASH_DST_IPV4 |
671 MLX4_IB_RX_HASH_SRC_IPV6 |
672 MLX4_IB_RX_HASH_DST_IPV6 |
673 MLX4_IB_RX_HASH_SRC_PORT_TCP |
674 MLX4_IB_RX_HASH_DST_PORT_TCP |
675 MLX4_IB_RX_HASH_SRC_PORT_UDP |
676 MLX4_IB_RX_HASH_DST_PORT_UDP)) {
677 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
678 ucmd->rx_hash_fields_mask);
679 return (-EOPNOTSUPP);
680 }
681
3078f5f1
GL		 682 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
683 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
684 rss_ctx->flags = MLX4_RSS_IPV4;
685 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
686 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
687 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
688 return (-EOPNOTSUPP);
689 }
690
691 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
692 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
693 rss_ctx->flags |= MLX4_RSS_IPV6;
694 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
695 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
696 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
697 return (-EOPNOTSUPP);
698 }
699
700 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
701 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
702 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
703 pr_debug("RX Hash fields_mask for UDP is not supported\n");
704 return (-EOPNOTSUPP);
705 }
706
4d02ebd9 707 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 708 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 709 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 710 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 711 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 712 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
713 return (-EOPNOTSUPP);
714 }
715 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
716 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
717 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
718 return (-EOPNOTSUPP);
719 }
720
721 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
722 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 723 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 724 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 725 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 726 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 727 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 728 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
729 return (-EOPNOTSUPP);
730 }
3078f5f1
GL		 731 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
732 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
733 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
734 return (-EOPNOTSUPP);
735 }
736
737 return 0;
738}
739
d7c0557a 740static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 741 struct ib_qp_init_attr *init_attr,
742 struct mlx4_ib_create_qp_rss *ucmd,
743 struct mlx4_ib_qp *qp)
744{
745 int qpn;
746 int err;
747
748 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
749
750 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
751 if (err)
752 return err;
753
754 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
755 if (err)
756 goto err_qpn;
757
758 mutex_init(&qp->mutex);
759
760 INIT_LIST_HEAD(&qp->gid_list);
761 INIT_LIST_HEAD(&qp->steering_rules);
762
c3f1ee29 763 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 764 qp->state = IB_QPS_RESET;
765
766 /* Set dummy send resources to be compatible with HV and PRM */
767 qp->sq_no_prefetch = 1;
768 qp->sq.wqe_cnt = 1;
769 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
770 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
771 qp->mtt = (to_mqp(
772 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
773
774 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
775 if (!qp->rss_ctx) {
776 err = -ENOMEM;
777 goto err_qp_alloc;
778 }
779
780 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
781 if (err)
782 goto err;
783
784 return 0;
785
786err:
787 kfree(qp->rss_ctx);
788
789err_qp_alloc:
790 mlx4_qp_remove(dev->dev, &qp->mqp);
791 mlx4_qp_free(dev->dev, &qp->mqp);
792
793err_qpn:
794 mlx4_qp_release_range(dev->dev, qpn, 1);
795 return err;
796}
797
798static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
799 struct ib_qp_init_attr *init_attr,
800 struct ib_udata *udata)
801{
802 struct mlx4_ib_qp *qp;
803 struct mlx4_ib_create_qp_rss ucmd = {};
804 size_t required_cmd_sz;
805 int err;
806
807 if (!udata) {
808 pr_debug("RSS QP with NULL udata\n");
809 return ERR_PTR(-EINVAL);
810 }
811
812 if (udata->outlen)
813 return ERR_PTR(-EOPNOTSUPP);
814
815 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
816 sizeof(ucmd.reserved1);
817 if (udata->inlen < required_cmd_sz) {
818 pr_debug("invalid inlen\n");
819 return ERR_PTR(-EINVAL);
820 }
821
822 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
823 pr_debug("copy failed\n");
824 return ERR_PTR(-EFAULT);
825 }
826
f9bfea99
GL		 827 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
828 return ERR_PTR(-EOPNOTSUPP);
829
3078f5f1
GL		 830 if (ucmd.comp_mask || ucmd.reserved1)
831 return ERR_PTR(-EOPNOTSUPP);
832
833 if (udata->inlen > sizeof(ucmd) &&
834 !ib_is_udata_cleared(udata, sizeof(ucmd),
835 udata->inlen - sizeof(ucmd))) {
836 pr_debug("inlen is not supported\n");
837 return ERR_PTR(-EOPNOTSUPP);
838 }
839
840 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
841 pr_debug("RSS QP with unsupported QP type %d\n",
842 init_attr->qp_type);
843 return ERR_PTR(-EOPNOTSUPP);
844 }
845
846 if (init_attr->create_flags) {
847 pr_debug("RSS QP doesn't support create flags\n");
848 return ERR_PTR(-EOPNOTSUPP);
849 }
850
851 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
852 pr_debug("RSS QP with unsupported send attributes\n");
853 return ERR_PTR(-EOPNOTSUPP);
854 }
855
856 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
857 if (!qp)
858 return ERR_PTR(-ENOMEM);
859
860 qp->pri.vid = 0xFFFF;
861 qp->alt.vid = 0xFFFF;
862
d7c0557a 863 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
3078f5f1
GL		 864 if (err) {
865 kfree(qp);
866 return ERR_PTR(err);
867 }
868
869 qp->ibqp.qp_num = qp->mqp.qpn;
870
871 return &qp->ibqp;
872}
873
400b1ebc
GL		 874/*
875 * This function allocates a WQN from a range which is consecutive and aligned
876 * to its size. In case the range is full, then it creates a new range and
877 * allocates WQN from it. The new range will be used for following allocations.
878 */
879static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
880 struct mlx4_ib_qp *qp, int range_size, int *wqn)
881{
882 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
883 struct mlx4_wqn_range *range;
884 int err = 0;
885
886 mutex_lock(&context->wqn_ranges_mutex);
887
888 range = list_first_entry_or_null(&context->wqn_ranges_list,
889 struct mlx4_wqn_range, list);
890
891 if (!range || (range->refcount == range->size) || range->dirty) {
892 range = kzalloc(sizeof(*range), GFP_KERNEL);
893 if (!range) {
894 err = -ENOMEM;
895 goto out;
896 }
897
898 err = mlx4_qp_reserve_range(dev->dev, range_size,
899 range_size, &range->base_wqn, 0,
900 qp->mqp.usage);
901 if (err) {
902 kfree(range);
903 goto out;
904 }
905
906 range->size = range_size;
907 list_add(&range->list, &context->wqn_ranges_list);
908 } else if (range_size != 1) {
909 /*
910 * Requesting a new range (>1) when last range is still open, is
911 * not valid.
912 */
913 err = -EINVAL;
914 goto out;
915 }
916
917 qp->wqn_range = range;
918
919 *wqn = range->base_wqn + range->refcount;
920
921 range->refcount++;
922
923out:
924 mutex_unlock(&context->wqn_ranges_mutex);
925
926 return err;
927}
928
929static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
930 struct mlx4_ib_qp *qp, bool dirty_release)
931{
932 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
933 struct mlx4_wqn_range *range;
934
935 mutex_lock(&context->wqn_ranges_mutex);
936
937 range = qp->wqn_range;
938
939 range->refcount--;
940 if (!range->refcount) {
941 mlx4_qp_release_range(dev->dev, range->base_wqn,
942 range->size);
943 list_del(&range->list);
944 kfree(range);
945 } else if (dirty_release) {
946 /*
947 * A range which one of its WQNs is destroyed, won't be able to be
948 * reused for further WQN allocations.
949 * The next created WQ will allocate a new range.
950 */
951 range->dirty = 1;
952 }
953
954 mutex_unlock(&context->wqn_ranges_mutex);
955}
956
225c7b1f 957static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
400b1ebc 958 enum mlx4_ib_source_type src,
225c7b1f 959 struct ib_qp_init_attr *init_attr,
8900b894
LR		 960 struct ib_udata *udata, int sqpn,
961 struct mlx4_ib_qp **caller_qp)
225c7b1f 962{
a3cdcbfa 963 int qpn;
225c7b1f 964 int err;
73898db0 965 struct ib_qp_cap backup_cap;
b42dde47 966 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 967 struct mlx4_ib_qp *qp;
968 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 969 struct mlx4_ib_cq *mcq;
970 unsigned long flags;
400b1ebc 971 int range_size = 0;
1ffeb2eb
JM		 972
973 /* When tunneling special qps, we use a plain UD qp */
974 if (sqpn) {
975 if (mlx4_is_mfunc(dev->dev) &&
976 (!mlx4_is_master(dev->dev) ||
977 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
978 if (init_attr->qp_type == IB_QPT_GSI)
979 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 980 else {
981 if (mlx4_is_master(dev->dev) ||
982 qp0_enabled_vf(dev->dev, sqpn))
983 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
984 else
985 qp_type = MLX4_IB_QPT_PROXY_SMI;
986 }
1ffeb2eb
JM		 987 }
988 qpn = sqpn;
989 /* add extra sg entry for tunneling */
990 init_attr->cap.max_recv_sge++;
991 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
992 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
993 container_of(init_attr,
994 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
995 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
996 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
997 !mlx4_is_master(dev->dev))
998 return -EINVAL;
999 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1000 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 1001 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1002 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1003 tnl_init->port))
1ffeb2eb
JM		 1004 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1005 else
1006 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 1007 /* we are definitely in the PPF here, since we are creating
1008 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1009 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1010 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 1011 sqpn = qpn;
1012 }
1013
1014 if (!*caller_qp) {
1015 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1016 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1017 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 1018 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 1019 if (!sqp)
1020 return -ENOMEM;
1021 qp = &sqp->qp;
2f5bb473
JM		 1022 qp->pri.vid = 0xFFFF;
1023 qp->alt.vid = 0xFFFF;
1ffeb2eb 1024 } else {
8900b894 1025 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 1026 if (!qp)
1027 return -ENOMEM;
2f5bb473
JM		 1028 qp->pri.vid = 0xFFFF;
1029 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1030 }
1031 } else
1032 qp = *caller_qp;
1033
1034 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 1035
1036 mutex_init(&qp->mutex);
1037 spin_lock_init(&qp->sq.lock);
1038 spin_lock_init(&qp->rq.lock);
fa417f7b 1039 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1040 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 1041
1042 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1043 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1044 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1045
225c7b1f
RD		 1046
1047 if (pd->uobject) {
400b1ebc
GL		 1048 union {
1049 struct mlx4_ib_create_qp qp;
1050 struct mlx4_ib_create_wq wq;
1051 } ucmd;
1052 size_t copy_len;
ed8637d3
GL		 1053 int shift;
1054 int n;
400b1ebc
GL		 1055
1056 copy_len = (src == MLX4_IB_QP_SRC) ?
1057 sizeof(struct mlx4_ib_create_qp) :
1058 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
225c7b1f 1059
400b1ebc 1060 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1061 err = -EFAULT;
1062 goto err;
1063 }
1064
400b1ebc 1065 if (src == MLX4_IB_RWQ_SRC) {
078b3573
GL		 1066 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
1067 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
400b1ebc
GL		 1068 pr_debug("user command isn't supported\n");
1069 err = -EOPNOTSUPP;
1070 goto err;
1071 }
ea30b966 1072
400b1ebc
GL		 1073 if (ucmd.wq.log_range_size >
1074 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1075 pr_debug("WQN range size must be equal or smaller than %d\n",
1076 dev->dev->caps.max_rss_tbl_sz);
1077 err = -EOPNOTSUPP;
1078 goto err;
1079 }
1080 range_size = 1 << ucmd.wq.log_range_size;
1081 } else {
1082 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1083 }
0e6e7416 1084
400b1ebc
GL		 1085 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1086 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1087 if (err)
1088 goto err;
1089
400b1ebc
GL		 1090 if (src == MLX4_IB_QP_SRC) {
1091 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1092
1093 err = set_user_sq_size(dev, qp,
1094 (struct mlx4_ib_create_qp *)
1095 &ucmd);
1096 if (err)
1097 goto err;
1098 } else {
1099 qp->sq_no_prefetch = 1;
1100 qp->sq.wqe_cnt = 1;
1101 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1102 /* Allocated buffer expects to have at least that SQ
1103 * size.
1104 */
1105 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1106 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1107 }
1108
1109 qp->umem = ib_umem_get(pd->uobject->context,
1110 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1111 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
225c7b1f
RD		 1112 if (IS_ERR(qp->umem)) {
1113 err = PTR_ERR(qp->umem);
1114 goto err;
1115 }
1116
ed8637d3
GL		 1117 n = ib_umem_page_count(qp->umem);
1118 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1119 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1120
225c7b1f
RD		 1121 if (err)
1122 goto err_buf;
1123
1124 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1125 if (err)
1126 goto err_mtt;
1127
0a1405da 1128 if (qp_has_rq(init_attr)) {
02d89b87 1129 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
400b1ebc
GL		 1130 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1131 ucmd.wq.db_addr, &qp->db);
02d89b87
RD		 1132 if (err)
1133 goto err_mtt;
1134 }
f3301870 1135 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1136 } else {
ea30b966
MG		 1137 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1138 qp_has_rq(init_attr), qp, 0);
1139 if (err)
1140 goto err;
1141
0e6e7416
RD		 1142 qp->sq_no_prefetch = 0;
1143
b832be1e
EC		 1144 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1145 qp->flags |= MLX4_IB_QP_LSO;
1146
c1c98501
MB		 1147 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1148 if (dev->steering_support ==
1149 MLX4_STEERING_MODE_DEVICE_MANAGED)
1150 qp->flags |= MLX4_IB_QP_NETIF;
1151 else
1152 goto err;
1153 }
1154
73898db0
HA		 1155 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1156 err = set_kernel_sq_size(dev, &init_attr->cap,
1157 qp_type, qp, true);
2446304d
EC		 1158 if (err)
1159 goto err;
1160
0a1405da 1161 if (qp_has_rq(init_attr)) {
8900b894 1162 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1163 if (err)
1164 goto err;
225c7b1f 1165
02d89b87
RD		 1166 *qp->db.db = 0;
1167 }
225c7b1f 1168
73898db0 1169 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
8900b894 1170 &qp->buf)) {
73898db0
HA		 1171 memcpy(&init_attr->cap, &backup_cap,
1172 sizeof(backup_cap));
1173 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1174 qp, false);
1175 if (err)
1176 goto err_db;
1177
1178 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
8900b894 1179 PAGE_SIZE * 2, &qp->buf)) {
73898db0
HA		 1180 err = -ENOMEM;
1181 goto err_db;
1182 }
225c7b1f
RD		 1183 }
1184
1185 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1186 &qp->mtt);
1187 if (err)
1188 goto err_buf;
1189
8900b894 1190 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1191 if (err)
1192 goto err_mtt;
1193
e9105cde
LD		 1194 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1195 sizeof(u64), GFP_KERNEL);
1196 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1197 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1198 if (!qp->sq.wrid || !qp->rq.wrid) {
1199 err = -ENOMEM;
1200 goto err_wrid;
1201 }
f3301870 1202 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1203 }
1204
a3cdcbfa 1205 if (sqpn) {
1ffeb2eb
JM		 1206 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1207 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1208 if (alloc_proxy_bufs(pd->device, qp)) {
1209 err = -ENOMEM;
1210 goto err_wrid;
1211 }
1212 }
400b1ebc
GL		 1213 } else if (src == MLX4_IB_RWQ_SRC) {
1214 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1215 range_size, &qpn);
1216 if (err)
1217 goto err_wrid;
a3cdcbfa 1218 } else {
ddae0349
EE		 1219 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1220 * otherwise, the WQE BlueFlame setup flow wrongly causes
1221 * VLAN insertion. */
3987a2d3 1222 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1223 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1224 (init_attr->cap.max_send_wr ?
1225 MLX4_RESERVE_ETH_BF_QP : 0) |
1226 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1227 MLX4_RESERVE_A0_QP : 0),
1228 qp->mqp.usage);
3987a2d3 1229 else
c1c98501
MB		 1230 if (qp->flags & MLX4_IB_QP_NETIF)
1231 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1232 else
1233 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1234 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1235 if (err)
1ffeb2eb 1236 goto err_proxy;
a3cdcbfa
YP		 1237 }
1238
fbfb6625
EBE		 1239 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1240 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1241
8900b894 1242 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1243 if (err)
a3cdcbfa 1244 goto err_qpn;
225c7b1f 1245
0a1405da
SH		 1246 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1247 qp->mqp.qpn |= (1 << 23);
1248
225c7b1f
RD		 1249 /*
1250 * Hardware wants QPN written in big-endian order (after
1251 * shifting) for send doorbell. Precompute this value to save
1252 * a little bit when posting sends.
1253 */
1254 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1255
400b1ebc
GL		 1256 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1257 mlx4_ib_wq_event;
1258
1ffeb2eb
JM		 1259 if (!*caller_qp)
1260 *caller_qp = qp;
35f05dab
YH		 1261
1262 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1263 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1264 to_mcq(init_attr->recv_cq));
1265 /* Maintain device to QPs access, needed for further handling
1266 * via reset flow
1267 */
1268 list_add_tail(&qp->qps_list, &dev->qp_list);
1269 /* Maintain CQ to QPs access, needed for further handling
1270 * via reset flow
1271 */
1272 mcq = to_mcq(init_attr->send_cq);
1273 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1274 mcq = to_mcq(init_attr->recv_cq);
1275 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1276 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1277 to_mcq(init_attr->recv_cq));
1278 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1279 return 0;
1280
a3cdcbfa 1281err_qpn:
c1c98501
MB		 1282 if (!sqpn) {
1283 if (qp->flags & MLX4_IB_QP_NETIF)
1284 mlx4_ib_steer_qp_free(dev, qpn, 1);
400b1ebc
GL		 1285 else if (src == MLX4_IB_RWQ_SRC)
1286 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1287 qp, 0);
c1c98501
MB		 1288 else
1289 mlx4_qp_release_range(dev->dev, qpn, 1);
1290 }
1ffeb2eb
JM		 1291err_proxy:
1292 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1293 free_proxy_bufs(pd->device, qp);
225c7b1f 1294err_wrid:
23f1b384 1295 if (pd->uobject) {
0a1405da
SH		 1296 if (qp_has_rq(init_attr))
1297 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 1298 } else {
0ef2f05c
WW		 1299 kvfree(qp->sq.wrid);
1300 kvfree(qp->rq.wrid);
225c7b1f
RD		 1301 }
1302
1303err_mtt:
1304 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1305
1306err_buf:
1307 if (pd->uobject)
1308 ib_umem_release(qp->umem);
1309 else
1310 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1311
1312err_db:
0a1405da 1313 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 1314 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1315
1316err:
b42dde47
BVA		 1317 if (sqp)
1318 kfree(sqp);
1319 else if (!*caller_qp)
1ffeb2eb 1320 kfree(qp);
225c7b1f
RD		 1321 return err;
1322}
1323
1324static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1325{
1326 switch (state) {
1327 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1328 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1329 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1330 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1331 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1332 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1333 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1334 default: return -1;
1335 }
1336}
1337
1338static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1339 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1340{
338a8fad 1341 if (send_cq == recv_cq) {
35f05dab 1342 spin_lock(&send_cq->lock);
338a8fad
RD		 1343 __acquire(&recv_cq->lock);
1344 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1345 spin_lock(&send_cq->lock);
225c7b1f
RD		 1346 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1347 } else {
35f05dab 1348 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1349 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1350 }
1351}
1352
1353static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1354 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1355{
338a8fad
RD		 1356 if (send_cq == recv_cq) {
1357 __release(&recv_cq->lock);
35f05dab 1358 spin_unlock(&send_cq->lock);
338a8fad 1359 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1360 spin_unlock(&recv_cq->lock);
35f05dab 1361 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1362 } else {
1363 spin_unlock(&send_cq->lock);
35f05dab 1364 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1365 }
1366}
1367
fa417f7b
EC		 1368static void del_gid_entries(struct mlx4_ib_qp *qp)
1369{
1370 struct mlx4_ib_gid_entry *ge, *tmp;
1371
1372 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1373 list_del(&ge->list);
1374 kfree(ge);
1375 }
1376}
1377
0a1405da
SH		 1378static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1379{
1380 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1381 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1382 else
1383 return to_mpd(qp->ibqp.pd);
1384}
1385
400b1ebc 1386static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1387 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1388{
1389 switch (qp->ibqp.qp_type) {
1390 case IB_QPT_XRC_TGT:
1391 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1392 *recv_cq = *send_cq;
1393 break;
1394 case IB_QPT_XRC_INI:
1395 *send_cq = to_mcq(qp->ibqp.send_cq);
1396 *recv_cq = *send_cq;
1397 break;
1398 default:
400b1ebc
GL		 1399 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1400 to_mcq(qp->ibwq.cq);
1401 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1402 *recv_cq;
0a1405da
SH		 1403 break;
1404 }
1405}
1406
3078f5f1
GL		 1407static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1408{
1409 if (qp->state != IB_QPS_RESET) {
1410 int i;
1411
1412 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1413 i++) {
1414 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1415 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1416
1417 mutex_lock(&wq->mutex);
1418
1419 wq->rss_usecnt--;
1420
1421 mutex_unlock(&wq->mutex);
1422 }
1423
1424 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1425 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1426 pr_warn("modify QP %06x to RESET failed.\n",
1427 qp->mqp.qpn);
1428 }
1429
1430 mlx4_qp_remove(dev->dev, &qp->mqp);
1431 mlx4_qp_free(dev->dev, &qp->mqp);
1432 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1433 del_gid_entries(qp);
1434 kfree(qp->rss_ctx);
1435}
1436
225c7b1f 1437static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
400b1ebc 1438 enum mlx4_ib_source_type src, int is_user)
225c7b1f
RD		 1439{
1440 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1441 unsigned long flags;
225c7b1f 1442
2f5bb473 1443 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1444 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1445 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1446 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1447 qp->mqp.qpn);
25476b02 1448 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1449 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1450 qp->pri.smac = 0;
25476b02 1451 qp->pri.smac_port = 0;
2f5bb473
JM		 1452 }
1453 if (qp->alt.smac) {
1454 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1455 qp->alt.smac = 0;
1456 }
1457 if (qp->pri.vid < 0x1000) {
1458 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1459 qp->pri.vid = 0xFFFF;
1460 qp->pri.candidate_vid = 0xFFFF;
1461 qp->pri.update_vid = 0;
1462 }
1463 if (qp->alt.vid < 0x1000) {
1464 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1465 qp->alt.vid = 0xFFFF;
1466 qp->alt.candidate_vid = 0xFFFF;
1467 qp->alt.update_vid = 0;
1468 }
1469 }
225c7b1f 1470
400b1ebc 1471 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1472
35f05dab 1473 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1474 mlx4_ib_lock_cqs(send_cq, recv_cq);
1475
35f05dab
YH		 1476 /* del from lists under both locks above to protect reset flow paths */
1477 list_del(&qp->qps_list);
1478 list_del(&qp->cq_send_list);
1479 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1480 if (!is_user) {
1481 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1482 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1483 if (send_cq != recv_cq)
1484 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1485 }
1486
1487 mlx4_qp_remove(dev->dev, &qp->mqp);
1488
1489 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1490 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1491
1492 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1493
c1c98501
MB		 1494 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1495 if (qp->flags & MLX4_IB_QP_NETIF)
1496 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc
GL		 1497 else if (src == MLX4_IB_RWQ_SRC)
1498 mlx4_ib_release_wqn(to_mucontext(
1499 qp->ibwq.uobject->context), qp, 1);
c1c98501
MB		 1500 else
1501 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1502 }
a3cdcbfa 1503
225c7b1f
RD		 1504 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1505
1506 if (is_user) {
400b1ebc
GL		 1507 if (qp->rq.wqe_cnt) {
1508 struct mlx4_ib_ucontext *mcontext = !src ?
1509 to_mucontext(qp->ibqp.uobject->context) :
1510 to_mucontext(qp->ibwq.uobject->context);
1511 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1512 }
225c7b1f
RD		 1513 ib_umem_release(qp->umem);
1514 } else {
0ef2f05c
WW		 1515 kvfree(qp->sq.wrid);
1516 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1517 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1518 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1519 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1520 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1521 if (qp->rq.wqe_cnt)
6296883c 1522 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1523 }
fa417f7b
EC		 1524
1525 del_gid_entries(qp);
225c7b1f
RD		 1526}
1527
47605df9
JM		 1528static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1529{
1530 /* Native or PPF */
1531 if (!mlx4_is_mfunc(dev->dev) ||
1532 (mlx4_is_master(dev->dev) &&
1533 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1534 return dev->dev->phys_caps.base_sqpn +
1535 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1536 attr->port_num - 1;
1537 }
1538 /* PF or VF -- creating proxies */
1539 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1540 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1541 else
c73c8b1e 1542 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1543}
1544
e1b866c6
MS		 1545static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1546 struct ib_qp_init_attr *init_attr,
1547 struct ib_udata *udata)
225c7b1f 1548{
1ffeb2eb 1549 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1550 int err;
fbfb6625 1551 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1552 u16 xrcdn = 0;
225c7b1f 1553
3078f5f1
GL		 1554 if (init_attr->rwq_ind_tbl)
1555 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1556
521e575b 1557 /*
1ffeb2eb
JM		 1558 * We only support LSO, vendor flag1, and multicast loopback blocking,
1559 * and only for kernel UD QPs.
521e575b 1560 */
1ffeb2eb
JM		 1561 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1562 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1563 MLX4_IB_SRIOV_TUNNEL_QP |
1564 MLX4_IB_SRIOV_SQP |
40f2287b 1565 MLX4_IB_QP_NETIF |
8900b894 1566 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1567 return ERR_PTR(-EINVAL);
521e575b 1568
c1c98501
MB		 1569 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1570 if (init_attr->qp_type != IB_QPT_UD)
1571 return ERR_PTR(-EINVAL);
1572 }
1573
e1b866c6
MS		 1574 if (init_attr->create_flags) {
1575 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1576 return ERR_PTR(-EINVAL);
1577
1578 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1579 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1580 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1581 init_attr->qp_type != IB_QPT_UD) ||
1582 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1583 init_attr->qp_type > IB_QPT_GSI) ||
1584 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1585 init_attr->qp_type != IB_QPT_GSI))
1586 return ERR_PTR(-EINVAL);
1587 }
b846f25a 1588
225c7b1f 1589 switch (init_attr->qp_type) {
0a1405da
SH		 1590 case IB_QPT_XRC_TGT:
1591 pd = to_mxrcd(init_attr->xrcd)->pd;
1592 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1593 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1594 /* fall through */
1595 case IB_QPT_XRC_INI:
1596 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1597 return ERR_PTR(-ENOSYS);
1598 init_attr->recv_cq = init_attr->send_cq;
1599 /* fall through */
225c7b1f
RD		 1600 case IB_QPT_RC:
1601 case IB_QPT_UC:
3987a2d3 1602 case IB_QPT_RAW_PACKET:
8900b894 1603 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1604 if (!qp)
1605 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1606 qp->pri.vid = 0xFFFF;
1607 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1608 /* fall through */
1609 case IB_QPT_UD:
1610 {
400b1ebc
GL		 1611 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1612 init_attr, udata, 0, &qp);
5b420d9c
DB		 1613 if (err) {
1614 kfree(qp);
225c7b1f 1615 return ERR_PTR(err);
5b420d9c 1616 }
225c7b1f
RD		 1617
1618 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1619 qp->xrcdn = xrcdn;
225c7b1f
RD		 1620
1621 break;
1622 }
1623 case IB_QPT_SMI:
1624 case IB_QPT_GSI:
1625 {
e1b866c6
MS		 1626 int sqpn;
1627
225c7b1f 1628 /* Userspace is not allowed to create special QPs: */
0a1405da 1629 if (udata)
225c7b1f 1630 return ERR_PTR(-EINVAL);
e1b866c6 1631 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1632 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1633 1, 1, &sqpn, 0,
1634 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1635
1636 if (res)
1637 return ERR_PTR(res);
1638 } else {
1639 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1640 }
225c7b1f 1641
400b1ebc
GL		 1642 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1643 init_attr, udata, sqpn, &qp);
1ffeb2eb 1644 if (err)
225c7b1f 1645 return ERR_PTR(err);
225c7b1f
RD		 1646
1647 qp->port = init_attr->port_num;
e1b866c6
MS		 1648 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1649 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1650 break;
1651 }
1652 default:
1653 /* Don't support raw QPs */
1654 return ERR_PTR(-EINVAL);
1655 }
1656
1657 return &qp->ibqp;
1658}
1659
e1b866c6
MS		 1660struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1661 struct ib_qp_init_attr *init_attr,
1662 struct ib_udata *udata) {
1663 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1664 struct ib_qp *ibqp;
1665 struct mlx4_ib_dev *dev = to_mdev(device);
1666
1667 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1668
1669 if (!IS_ERR(ibqp) &&
1670 (init_attr->qp_type == IB_QPT_GSI) &&
1671 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1672 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1673 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1674
1675 if (is_eth &&
1676 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1677 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1678 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1679
1680 if (IS_ERR(sqp->roce_v2_gsi)) {
1681 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1682 sqp->roce_v2_gsi = NULL;
1683 } else {
1684 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1685 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1686 }
1687
1688 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1689 }
1690 }
1691 return ibqp;
1692}
1693
1694static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1695{
1696 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1697 struct mlx4_ib_qp *mqp = to_mqp(qp);
1698
1699 if (is_qp0(dev, mqp))
1700 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1701
c482af64
JM		 1702 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1703 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1704 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1705 dev->qp1_proxy[mqp->port - 1] = NULL;
1706 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1707 }
1708
7b59f0f9
EBE		 1709 if (mqp->counter_index)
1710 mlx4_ib_free_qp_counter(dev, mqp);
1711
3078f5f1
GL		 1712 if (qp->rwq_ind_tbl) {
1713 destroy_qp_rss(dev, mqp);
1714 } else {
1715 struct mlx4_ib_pd *pd;
1716
1717 pd = get_pd(mqp);
1718 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1719 }
225c7b1f
RD		 1720
1721 if (is_sqp(dev, mqp))
1722 kfree(to_msqp(mqp));
1723 else
1724 kfree(mqp);
1725
1726 return 0;
1727}
1728
e1b866c6
MS		 1729int mlx4_ib_destroy_qp(struct ib_qp *qp)
1730{
1731 struct mlx4_ib_qp *mqp = to_mqp(qp);
1732
1733 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1734 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1735
1736 if (sqp->roce_v2_gsi)
1737 ib_destroy_qp(sqp->roce_v2_gsi);
1738 }
1739
1740 return _mlx4_ib_destroy_qp(qp);
1741}
1742
1ffeb2eb 1743static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1744{
1745 switch (type) {
1ffeb2eb
JM		 1746 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1747 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1748 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1749 case MLX4_IB_QPT_XRC_INI:
1750 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1751 case MLX4_IB_QPT_SMI:
1752 case MLX4_IB_QPT_GSI:
1753 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1754
1755 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1756 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1757 MLX4_QP_ST_MLX : -1);
1758 case MLX4_IB_QPT_PROXY_SMI:
1759 case MLX4_IB_QPT_TUN_SMI:
1760 case MLX4_IB_QPT_PROXY_GSI:
1761 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1762 MLX4_QP_ST_UD : -1);
1763 default: return -1;
225c7b1f
RD		 1764 }
1765}
1766
65adfa91 1767static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1768 int attr_mask)
1769{
1770 u8 dest_rd_atomic;
1771 u32 access_flags;
1772 u32 hw_access_flags = 0;
1773
1774 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1775 dest_rd_atomic = attr->max_dest_rd_atomic;
1776 else
1777 dest_rd_atomic = qp->resp_depth;
1778
1779 if (attr_mask & IB_QP_ACCESS_FLAGS)
1780 access_flags = attr->qp_access_flags;
1781 else
1782 access_flags = qp->atomic_rd_en;
1783
1784 if (!dest_rd_atomic)
1785 access_flags &= IB_ACCESS_REMOTE_WRITE;
1786
1787 if (access_flags & IB_ACCESS_REMOTE_READ)
1788 hw_access_flags |= MLX4_QP_BIT_RRE;
1789 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1790 hw_access_flags |= MLX4_QP_BIT_RAE;
1791 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1792 hw_access_flags |= MLX4_QP_BIT_RWE;
1793
1794 return cpu_to_be32(hw_access_flags);
1795}
1796
65adfa91 1797static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1798 int attr_mask)
1799{
1800 if (attr_mask & IB_QP_PKEY_INDEX)
1801 sqp->pkey_index = attr->pkey_index;
1802 if (attr_mask & IB_QP_QKEY)
1803 sqp->qkey = attr->qkey;
1804 if (attr_mask & IB_QP_SQ_PSN)
1805 sqp->send_psn = attr->sq_psn;
1806}
1807
1808static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1809{
1810 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1811}
1812
90898850
DC		 1813static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1814 const struct rdma_ah_attr *ah,
297e0dad 1815 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1816 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1817{
4c3eb3ca 1818 int vidx;
297e0dad 1819 int smac_index;
2f5bb473 1820 int err;
297e0dad 1821
d8966fcd
DC		 1822 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1823 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1824 if (rdma_ah_get_static_rate(ah)) {
1825 path->static_rate = rdma_ah_get_static_rate(ah) +
1826 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1827 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1828 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1829 --path->static_rate;
1830 } else
1831 path->static_rate = 0;
225c7b1f 1832
d8966fcd
DC		 1833 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1834 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1835 int real_sgid_index =
1836 mlx4_ib_gid_index_to_real_index(dev, port,
1837 grh->sgid_index);
5070cd22 1838
54a6d63f
DC		 1839 if (real_sgid_index < 0)
1840 return real_sgid_index;
5070cd22 1841 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1842 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1843 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1844 return -1;
1845 }
1846
1847 path->grh_mylmc |= 1 << 7;
5070cd22 1848 path->mgid_index = real_sgid_index;
d8966fcd 1849 path->hop_limit = grh->hop_limit;
225c7b1f 1850 path->tclass_flowlabel =
d8966fcd
DC		 1851 cpu_to_be32((grh->traffic_class << 20) |
1852 (grh->flow_label));
1853 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1854 }
1855
44c58487 1856 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1857 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1858 return -1;
1859
2f5bb473 1860 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1861 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1862
297e0dad 1863 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1864 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1865 if (smac_info->vid < 0x1000) {
1866 /* both valid vlan ids */
1867 if (smac_info->vid != vlan_tag) {
1868 /* different VIDs. unreg old and reg new */
1869 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1870 if (err)
1871 return err;
1872 smac_info->candidate_vid = vlan_tag;
1873 smac_info->candidate_vlan_index = vidx;
1874 smac_info->candidate_vlan_port = port;
1875 smac_info->update_vid = 1;
1876 path->vlan_index = vidx;
1877 } else {
1878 path->vlan_index = smac_info->vlan_index;
1879 }
1880 } else {
1881 /* no current vlan tag in qp */
1882 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1883 if (err)
1884 return err;
1885 smac_info->candidate_vid = vlan_tag;
1886 smac_info->candidate_vlan_index = vidx;
1887 smac_info->candidate_vlan_port = port;
1888 smac_info->update_vid = 1;
1889 path->vlan_index = vidx;
1890 }
297e0dad 1891 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1892 path->fl = 1 << 6;
1893 } else {
1894 /* have current vlan tag. unregister it at modify-qp success */
1895 if (smac_info->vid < 0x1000) {
1896 smac_info->candidate_vid = 0xFFFF;
1897 smac_info->update_vid = 1;
1898 }
4c3eb3ca 1899 }
2f5bb473
JM		 1900
1901 /* get smac_index for RoCE use.
1902 * If no smac was yet assigned, register one.
1903 * If one was already assigned, but the new mac differs,
1904 * unregister the old one and register the new one.
1905 */
25476b02
JM		 1906 if ((!smac_info->smac && !smac_info->smac_port) ||
1907 smac_info->smac != smac) {
2f5bb473
JM		 1908 /* register candidate now, unreg if needed, after success */
1909 smac_index = mlx4_register_mac(dev->dev, port, smac);
1910 if (smac_index >= 0) {
1911 smac_info->candidate_smac_index = smac_index;
1912 smac_info->candidate_smac = smac;
1913 smac_info->candidate_smac_port = port;
1914 } else {
1915 return -EINVAL;
1916 }
1917 } else {
1918 smac_index = smac_info->smac_index;
1919 }
44c58487 1920 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1921 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1922 /* put MAC table smac index for IBoE */
1923 path->grh_mylmc = (u8) (smac_index) | 0x80;
1924 } else {
4c3eb3ca 1925 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1926 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1927 }
fa417f7b 1928
225c7b1f
RD		 1929 return 0;
1930}
1931
297e0dad
MS		 1932static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1933 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1934 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1935 struct mlx4_qp_path *path, u8 port,
1936 u16 vlan_id, u8 *smac)
297e0dad
MS		 1937{
1938 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1939 mlx4_mac_to_u64(smac),
1940 vlan_id,
2f5bb473 1941 path, &mqp->pri, port);
297e0dad
MS		 1942}
1943
1944static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1945 const struct ib_qp_attr *qp,
1946 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1947 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1948 struct mlx4_qp_path *path, u8 port)
1949{
1950 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1951 0,
1952 0xffff,
2f5bb473 1953 path, &mqp->alt, port);
297e0dad
MS		 1954}
1955
fa417f7b
EC		 1956static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1957{
1958 struct mlx4_ib_gid_entry *ge, *tmp;
1959
1960 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1961 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1962 ge->added = 1;
1963 ge->port = qp->port;
1964 }
1965 }
1966}
1967
dbf727de
MB		 1968static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1969 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1970 struct mlx4_qp_context *context)
1971{
2f5bb473
JM		 1972 u64 u64_mac;
1973 int smac_index;
1974
3e0629cb 1975 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1976
1977 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1978 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1979 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1980 if (smac_index >= 0) {
1981 qp->pri.candidate_smac_index = smac_index;
1982 qp->pri.candidate_smac = u64_mac;
1983 qp->pri.candidate_smac_port = qp->port;
1984 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1985 } else {
1986 return -ENOENT;
1987 }
1988 }
1989 return 0;
1990}
1991
7b59f0f9
EBE		 1992static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1993{
1994 struct counter_index *new_counter_index;
1995 int err;
1996 u32 tmp_idx;
1997
1998 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1999 IB_LINK_LAYER_ETHERNET ||
2000 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
2001 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
2002 return 0;
2003
f3301870 2004 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 2005 if (err)
2006 return err;
2007
2008 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
2009 if (!new_counter_index) {
2010 mlx4_counter_free(dev->dev, tmp_idx);
2011 return -ENOMEM;
2012 }
2013
2014 new_counter_index->index = tmp_idx;
2015 new_counter_index->allocated = 1;
2016 qp->counter_index = new_counter_index;
2017
2018 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
2019 list_add_tail(&new_counter_index->list,
2020 &dev->counters_table[qp->port - 1].counters_list);
2021 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2022
2023 return 0;
2024}
2025
3b5daf28
MS		 2026enum {
2027 MLX4_QPC_ROCE_MODE_1 = 0,
2028 MLX4_QPC_ROCE_MODE_2 = 2,
2029 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2030};
2031
2032static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2033{
2034 switch (gid_type) {
2035 case IB_GID_TYPE_ROCE:
2036 return MLX4_QPC_ROCE_MODE_1;
2037 case IB_GID_TYPE_ROCE_UDP_ENCAP:
2038 return MLX4_QPC_ROCE_MODE_2;
2039 default:
2040 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2041 }
2042}
2043
3078f5f1
GL		 2044/*
2045 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2046 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2047 */
2048static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2049{
fba02e6c 2050 int err = 0;
3078f5f1 2051 int i;
3078f5f1
GL		 2052
2053 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2054 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2055 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2056
2057 mutex_lock(&wq->mutex);
2058
2059 /* Mlx4_ib restrictions:
2060 * WQ's is associated to a port according to the RSS QP it is
2061 * associates to.
2062 * In case the WQ is associated to a different port by another
2063 * RSS QP, return a failure.
2064 */
2065 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2066 err = -EINVAL;
2067 mutex_unlock(&wq->mutex);
2068 break;
2069 }
2070 wq->port = port_num;
2071 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2072 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2073 if (err) {
2074 mutex_unlock(&wq->mutex);
2075 break;
2076 }
2077 }
2078 wq->rss_usecnt++;
2079
2080 mutex_unlock(&wq->mutex);
2081 }
2082
2083 if (i && err) {
2084 int j;
2085
2086 for (j = (i - 1); j >= 0; j--) {
2087 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2088 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2089
2090 mutex_lock(&wq->mutex);
2091
2092 if ((wq->rss_usecnt == 1) &&
2093 (ibwq->state == IB_WQS_RDY))
2094 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2095 pr_warn("failed to reverse WQN=0x%06x\n",
2096 ibwq->wq_num);
2097 wq->rss_usecnt--;
2098
2099 mutex_unlock(&wq->mutex);
2100 }
2101 }
2102
2103 return err;
2104}
2105
2106static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2107{
2108 int i;
2109
2110 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2111 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2112 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2113
2114 mutex_lock(&wq->mutex);
2115
2116 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2117 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2118 pr_warn("failed to reverse WQN=%x\n",
2119 ibwq->wq_num);
2120 wq->rss_usecnt--;
2121
2122 mutex_unlock(&wq->mutex);
2123 }
2124}
2125
2126static void fill_qp_rss_context(struct mlx4_qp_context *context,
2127 struct mlx4_ib_qp *qp)
2128{
2129 struct mlx4_rss_context *rss_context;
2130
2131 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2132 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2133
2134 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2135 rss_context->default_qpn =
2136 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2137 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2138 rss_context->base_qpn_udp = rss_context->default_qpn;
2139 rss_context->flags = qp->rss_ctx->flags;
2140 /* Currently support just toeplitz */
2141 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2142
2143 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2144 MLX4_EN_RSS_KEY_SIZE);
2145}
2146
400b1ebc 2147static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91
MT		 2148 const struct ib_qp_attr *attr, int attr_mask,
2149 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f 2150{
400b1ebc
GL		 2151 struct ib_uobject *ibuobject;
2152 struct ib_srq *ibsrq;
3078f5f1 2153 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2154 enum ib_qp_type qp_type;
2155 struct mlx4_ib_dev *dev;
2156 struct mlx4_ib_qp *qp;
0a1405da
SH		 2157 struct mlx4_ib_pd *pd;
2158 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 2159 struct mlx4_qp_context *context;
2160 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2161 int sqd_event;
c1c98501 2162 int steer_qp = 0;
225c7b1f 2163 int err = -EINVAL;
3ba8e31d 2164 int counter_index;
225c7b1f 2165
400b1ebc
GL		 2166 if (src_type == MLX4_IB_RWQ_SRC) {
2167 struct ib_wq *ibwq;
2168
3078f5f1
GL		 2169 ibwq = (struct ib_wq *)src;
2170 ibuobject = ibwq->uobject;
2171 ibsrq = NULL;
2172 rwq_ind_tbl = NULL;
2173 qp_type = IB_QPT_RAW_PACKET;
2174 qp = to_mqp((struct ib_qp *)ibwq);
2175 dev = to_mdev(ibwq->device);
2176 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2177 } else {
2178 struct ib_qp *ibqp;
2179
3078f5f1
GL		 2180 ibqp = (struct ib_qp *)src;
2181 ibuobject = ibqp->uobject;
2182 ibsrq = ibqp->srq;
2183 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2184 qp_type = ibqp->qp_type;
2185 qp = to_mqp(ibqp);
2186 dev = to_mdev(ibqp->device);
2187 pd = get_pd(qp);
400b1ebc
GL		 2188 }
2189
3dec4878
JM		 2190 /* APM is not supported under RoCE */
2191 if (attr_mask & IB_QP_ALT_PATH &&
2192 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2193 IB_LINK_LAYER_ETHERNET)
2194 return -ENOTSUPP;
2195
225c7b1f
RD		 2196 context = kzalloc(sizeof *context, GFP_KERNEL);
2197 if (!context)
2198 return -ENOMEM;
2199
225c7b1f 2200 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2201 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2202
2203 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2204 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2205 else {
2206 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2207 switch (attr->path_mig_state) {
2208 case IB_MIG_MIGRATED:
2209 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2210 break;
2211 case IB_MIG_REARM:
2212 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2213 break;
2214 case IB_MIG_ARMED:
2215 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2216 break;
2217 }
2218 }
2219
ea30b966
MG		 2220 if (qp->inl_recv_sz)
2221 context->param3 |= cpu_to_be32(1 << 25);
2222
400b1ebc 2223 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2224 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2225 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2226 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2227 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2228 if (qp->flags & MLX4_IB_QP_LSO)
2229 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2230 ilog2(dev->dev->caps.max_gso_sz);
2231 else
5f22a1d8 2232 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2233 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2234 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2235 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2236 attr->path_mtu);
f5b40431 2237 goto out;
225c7b1f 2238 }
d1f2cd89
EC		 2239 context->mtu_msgmax = (attr->path_mtu << 5) |
2240 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2241 }
2242
3078f5f1
GL		 2243 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2244 if (qp->rq.wqe_cnt)
2245 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2246 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2247 }
225c7b1f 2248
0e6e7416
RD		 2249 if (qp->sq.wqe_cnt)
2250 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2251 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2252
7b59f0f9
EBE		 2253 if (new_state == IB_QPS_RESET && qp->counter_index)
2254 mlx4_ib_free_qp_counter(dev, qp);
2255
0a1405da 2256 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2257 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2258 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2259 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2260 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2261 }
0e6e7416 2262
400b1ebc 2263 if (ibuobject)
85743f1e
HN		 2264 context->usr_page = cpu_to_be32(
2265 mlx4_to_hw_uar_index(dev->dev,
400b1ebc
GL		 2266 to_mucontext(ibuobject->context)
2267 ->uar.index));
225c7b1f 2268 else
85743f1e
HN		 2269 context->usr_page = cpu_to_be32(
2270 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2271
2272 if (attr_mask & IB_QP_DEST_QPN)
2273 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2274
2275 if (attr_mask & IB_QP_PORT) {
2276 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2277 !(attr_mask & IB_QP_AV)) {
2278 mlx4_set_sched(&context->pri_path, attr->port_num);
2279 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2280 }
2281 }
2282
cfcde11c 2283 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2284 err = create_qp_lb_counter(dev, qp);
2285 if (err)
2286 goto out;
2287
3ba8e31d
EBE		 2288 counter_index =
2289 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2290 if (qp->counter_index)
2291 counter_index = qp->counter_index->index;
2292
3ba8e31d
EBE		 2293 if (counter_index != -1) {
2294 context->pri_path.counter_index = counter_index;
cfcde11c 2295 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2296 if (qp->counter_index) {
2297 context->pri_path.fl |=
2298 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2299 context->pri_path.vlan_control |=
2300 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2301 }
cfcde11c 2302 } else
47d8417f
EBE		 2303 context->pri_path.counter_index =
2304 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2305
2306 if (qp->flags & MLX4_IB_QP_NETIF) {
2307 mlx4_ib_steer_qp_reg(dev, qp, 1);
2308 steer_qp = 1;
2309 }
e1b866c6 2310
400b1ebc 2311 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2312 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2313 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2314 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2315
2316 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2317 }
cfcde11c
OG		 2318 }
2319
225c7b1f 2320 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2321 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2322 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2323 context->pri_path.pkey_index = attr->pkey_index;
2324 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2325 }
2326
225c7b1f 2327 if (attr_mask & IB_QP_AV) {
400b1ebc 2328 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de
MB		 2329 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2330 union ib_gid gid;
bf08e884 2331 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
dbf727de
MB		 2332 u16 vlan = 0xffff;
2333 u8 smac[ETH_ALEN];
2334 int status = 0;
d8966fcd
DC		 2335 int is_eth =
2336 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2337 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2338
d8966fcd
DC		 2339 if (is_eth) {
2340 int index =
2341 rdma_ah_read_grh(&attr->ah_attr)->sgid_index;
dbf727de 2342
400b1ebc 2343 status = ib_get_cached_gid(&dev->ib_dev, port_num,
dbf727de
MB		 2344 index, &gid, &gid_attr);
2345 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
2346 status = -ENOENT;
2347 if (!status && gid_attr.ndev) {
2348 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
2349 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
2350 dev_put(gid_attr.ndev);
2351 }
2352 }
2353 if (status)
2354 goto out;
2355
2f5bb473 2356 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2357 port_num, vlan, smac))
225c7b1f 2358 goto out;
225c7b1f
RD		 2359
2360 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2361 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2362
2363 if (is_eth &&
2364 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2365 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
2366
2367 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2368 err = -EINVAL;
2369 goto out;
2370 }
2371 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2372 }
2373
225c7b1f
RD		 2374 }
2375
2376 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2377 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2378 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2379 }
2380
2381 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2382 if (attr->alt_port_num == 0 ||
2383 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2384 goto out;
225c7b1f 2385
5ae2a7a8
RD		 2386 if (attr->alt_pkey_index >=
2387 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2388 goto out;
5ae2a7a8 2389
2f5bb473
JM		 2390 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2391 &context->alt_path,
297e0dad 2392 attr->alt_port_num))
f5b40431 2393 goto out;
225c7b1f
RD		 2394
2395 context->alt_path.pkey_index = attr->alt_pkey_index;
2396 context->alt_path.ackto = attr->alt_timeout << 3;
2397 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2398 }
2399
3078f5f1
GL		 2400 context->pd = cpu_to_be32(pd->pdn);
2401
2402 if (!rwq_ind_tbl) {
108809a0 2403 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2404 get_cqs(qp, src_type, &send_cq, &recv_cq);
2405 } else { /* Set dummy CQs to be compatible with HV and PRM */
2406 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2407 recv_cq = send_cq;
2408 }
0a1405da
SH		 2409 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2410 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2411
95d04f07 2412 /* Set "fast registration enabled" for all kernel QPs */
400b1ebc 2413 if (!ibuobject)
95d04f07
RD		 2414 context->params1 |= cpu_to_be32(1 << 11);
2415
57f01b53
JM		 2416 if (attr_mask & IB_QP_RNR_RETRY) {
2417 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2418 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2419 }
2420
225c7b1f
RD		 2421 if (attr_mask & IB_QP_RETRY_CNT) {
2422 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2423 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2424 }
2425
2426 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2427 if (attr->max_rd_atomic)
2428 context->params1 |=
2429 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2430 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2431 }
2432
2433 if (attr_mask & IB_QP_SQ_PSN)
2434 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2435
225c7b1f
RD		 2436 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2437 if (attr->max_dest_rd_atomic)
2438 context->params2 |=
2439 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2440 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2441 }
2442
2443 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2444 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2445 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2446 }
2447
400b1ebc 2448 if (ibsrq)
225c7b1f
RD		 2449 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2450
2451 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2452 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2453 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2454 }
2455 if (attr_mask & IB_QP_RQ_PSN)
2456 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2457
1ffeb2eb 2458 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2459 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2460 if (qp->mlx4_ib_qp_type &
2461 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2462 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2463 else {
2464 if (mlx4_is_mfunc(dev->dev) &&
2465 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2466 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2467 MLX4_RESERVED_QKEY_BASE) {
2468 pr_err("Cannot use reserved QKEY"
2469 " 0x%x (range 0xffff0000..0xffffffff"
2470 " is reserved)\n", attr->qkey);
2471 err = -EINVAL;
2472 goto out;
2473 }
2474 context->qkey = cpu_to_be32(attr->qkey);
2475 }
225c7b1f
RD		 2476 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2477 }
2478
400b1ebc
GL		 2479 if (ibsrq)
2480 context->srqn = cpu_to_be32(1 << 24 |
2481 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2482
400b1ebc
GL		 2483 if (qp->rq.wqe_cnt &&
2484 cur_state == IB_QPS_RESET &&
2485 new_state == IB_QPS_INIT)
225c7b1f
RD		 2486 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2487
2488 if (cur_state == IB_QPS_INIT &&
2489 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2490 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2491 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2492 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2493 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2494 qp->mlx4_ib_qp_type &
2495 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2496 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2497 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2498 context->pri_path.fl = 0x80;
2499 } else {
2500 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2501 context->pri_path.fl = 0x80;
225c7b1f 2502 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2503 }
2f5bb473
JM		 2504 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2505 IB_LINK_LAYER_ETHERNET) {
2506 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2507 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2508 context->pri_path.feup = 1 << 7; /* don't fsm */
2509 /* handle smac_index */
2510 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2511 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2512 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2513 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2514 if (err) {
2515 err = -EINVAL;
2516 goto out;
2517 }
9433c188
MB		 2518 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2519 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2520 }
2521 }
225c7b1f
RD		 2522 }
2523
400b1ebc 2524 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2525 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2526 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2527 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2528 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2529 if (!rwq_ind_tbl)
d2fce8a9
OG		 2530 context->srqn = cpu_to_be32(7 << 28);
2531 }
2532 }
3528f696 2533
400b1ebc 2534 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2535 int is_eth = rdma_port_get_link_layer(
2536 &dev->ib_dev, qp->port) ==
2537 IB_LINK_LAYER_ETHERNET;
2538 if (is_eth) {
2539 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2540 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2541 }
2542 }
2543
225c7b1f
RD		 2544 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2545 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2546 sqd_event = 1;
2547 else
2548 sqd_event = 0;
2549
400b1ebc
GL		 2550 if (!ibuobject &&
2551 cur_state == IB_QPS_RESET &&
2552 new_state == IB_QPS_INIT)
3b5daf28 2553 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2554
c0be5fb5
EC		 2555 /*
2556 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2557 * ownership bits of the send queue are set and the SQ
2558 * headroom is stamped so that the hardware doesn't start
2559 * processing stale work requests.
c0be5fb5 2560 */
400b1ebc
GL		 2561 if (!ibuobject &&
2562 cur_state == IB_QPS_RESET &&
2563 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2564 struct mlx4_wqe_ctrl_seg *ctrl;
2565 int i;
2566
0e6e7416 2567 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2568 ctrl = get_send_wqe(qp, i);
2569 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553 2570 if (qp->sq_max_wqes_per_wr == 1)
224e92e0
BB		 2571 ctrl->qpn_vlan.fence_size =
2572 1 << (qp->sq.wqe_shift - 4);
0e6e7416 2573
ea54b10c 2574 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 2575 }
2576 }
2577
108809a0
GL		 2578 if (rwq_ind_tbl &&
2579 cur_state == IB_QPS_RESET &&
2580 new_state == IB_QPS_INIT) {
2581 fill_qp_rss_context(context, qp);
2582 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2583 }
2584
225c7b1f
RD		 2585 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2586 to_mlx4_state(new_state), context, optpar,
2587 sqd_event, &qp->mqp);
2588 if (err)
2589 goto out;
2590
2591 qp->state = new_state;
2592
2593 if (attr_mask & IB_QP_ACCESS_FLAGS)
2594 qp->atomic_rd_en = attr->qp_access_flags;
2595 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2596 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2597 if (attr_mask & IB_QP_PORT) {
225c7b1f 2598 qp->port = attr->port_num;
fa417f7b
EC		 2599 update_mcg_macs(dev, qp);
2600 }
225c7b1f
RD		 2601 if (attr_mask & IB_QP_ALT_PATH)
2602 qp->alt_port = attr->alt_port_num;
2603
2604 if (is_sqp(dev, qp))
2605 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2606
2607 /*
2608 * If we moved QP0 to RTR, bring the IB link up; if we moved
2609 * QP0 to RESET or ERROR, bring the link back down.
2610 */
2611 if (is_qp0(dev, qp)) {
2612 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2613 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2614 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2615 qp->port);
225c7b1f
RD		 2616
2617 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2618 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2619 mlx4_CLOSE_PORT(dev->dev, qp->port);
2620 }
2621
2622 /*
2623 * If we moved a kernel QP to RESET, clean up all old CQ
2624 * entries and reinitialize the QP.
2625 */
2f5bb473 2626 if (new_state == IB_QPS_RESET) {
400b1ebc 2627 if (!ibuobject) {
2f5bb473 2628 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2629 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2630 if (send_cq != recv_cq)
2631 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2632
2633 qp->rq.head = 0;
2634 qp->rq.tail = 0;
2635 qp->sq.head = 0;
2636 qp->sq.tail = 0;
2637 qp->sq_next_wqe = 0;
2638 if (qp->rq.wqe_cnt)
2639 *qp->db.db = 0;
225c7b1f 2640
2f5bb473
JM		 2641 if (qp->flags & MLX4_IB_QP_NETIF)
2642 mlx4_ib_steer_qp_reg(dev, qp, 0);
2643 }
25476b02 2644 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2645 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2646 qp->pri.smac = 0;
25476b02 2647 qp->pri.smac_port = 0;
2f5bb473
JM		 2648 }
2649 if (qp->alt.smac) {
2650 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2651 qp->alt.smac = 0;
2652 }
2653 if (qp->pri.vid < 0x1000) {
2654 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2655 qp->pri.vid = 0xFFFF;
2656 qp->pri.candidate_vid = 0xFFFF;
2657 qp->pri.update_vid = 0;
2658 }
c1c98501 2659
2f5bb473
JM		 2660 if (qp->alt.vid < 0x1000) {
2661 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2662 qp->alt.vid = 0xFFFF;
2663 qp->alt.candidate_vid = 0xFFFF;
2664 qp->alt.update_vid = 0;
2665 }
225c7b1f 2666 }
225c7b1f 2667out:
7b59f0f9
EBE		 2668 if (err && qp->counter_index)
2669 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2670 if (err && steer_qp)
2671 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2672 kfree(context);
25476b02
JM		 2673 if (qp->pri.candidate_smac ||
2674 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2675 if (err) {
2676 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2677 } else {
25476b02 2678 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2679 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2680 qp->pri.smac = qp->pri.candidate_smac;
2681 qp->pri.smac_index = qp->pri.candidate_smac_index;
2682 qp->pri.smac_port = qp->pri.candidate_smac_port;
2683 }
2684 qp->pri.candidate_smac = 0;
2685 qp->pri.candidate_smac_index = 0;
2686 qp->pri.candidate_smac_port = 0;
2687 }
2688 if (qp->alt.candidate_smac) {
2689 if (err) {
2690 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2691 } else {
2692 if (qp->alt.smac)
2693 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2694 qp->alt.smac = qp->alt.candidate_smac;
2695 qp->alt.smac_index = qp->alt.candidate_smac_index;
2696 qp->alt.smac_port = qp->alt.candidate_smac_port;
2697 }
2698 qp->alt.candidate_smac = 0;
2699 qp->alt.candidate_smac_index = 0;
2700 qp->alt.candidate_smac_port = 0;
2701 }
2702
2703 if (qp->pri.update_vid) {
2704 if (err) {
2705 if (qp->pri.candidate_vid < 0x1000)
2706 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2707 qp->pri.candidate_vid);
2708 } else {
2709 if (qp->pri.vid < 0x1000)
2710 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2711 qp->pri.vid);
2712 qp->pri.vid = qp->pri.candidate_vid;
2713 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2714 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2715 }
2716 qp->pri.candidate_vid = 0xFFFF;
2717 qp->pri.update_vid = 0;
2718 }
2719
2720 if (qp->alt.update_vid) {
2721 if (err) {
2722 if (qp->alt.candidate_vid < 0x1000)
2723 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2724 qp->alt.candidate_vid);
2725 } else {
2726 if (qp->alt.vid < 0x1000)
2727 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2728 qp->alt.vid);
2729 qp->alt.vid = qp->alt.candidate_vid;
2730 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2731 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2732 }
2733 qp->alt.candidate_vid = 0xFFFF;
2734 qp->alt.update_vid = 0;
2735 }
2736
225c7b1f
RD		 2737 return err;
2738}
2739
3078f5f1
GL		 2740enum {
2741 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2742 IB_QP_PORT),
2743};
2744
e1b866c6
MS		 2745static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2746 int attr_mask, struct ib_udata *udata)
65adfa91 2747{
17bf1ad2 2748 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
65adfa91
MT		 2749 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2750 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2751 enum ib_qp_state cur_state, new_state;
2752 int err = -EINVAL;
65adfa91
MT		 2753 mutex_lock(&qp->mutex);
2754
2755 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2756 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2757
17bf1ad2 2758 if (cur_state != new_state || cur_state != IB_QPS_RESET) {
297e0dad
MS		 2759 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2760 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2761 }
dd5f03be
MB		 2762
2763 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2764 attr_mask, ll)) {
b1d8eb5a
JM		 2765 pr_debug("qpn 0x%x: invalid attribute mask specified "
2766 "for transition %d to %d. qp_type %d,"
2767 " attr_mask 0x%x\n",
2768 ibqp->qp_num, cur_state, new_state,
2769 ibqp->qp_type, attr_mask);
65adfa91 2770 goto out;
b1d8eb5a 2771 }
65adfa91 2772
3078f5f1
GL		 2773 if (ibqp->rwq_ind_tbl) {
2774 if (!(((cur_state == IB_QPS_RESET) &&
2775 (new_state == IB_QPS_INIT)) ||
2776 ((cur_state == IB_QPS_INIT) &&
2777 (new_state == IB_QPS_RTR)))) {
2778 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2779 ibqp->qp_num, cur_state, new_state);
2780
2781 err = -EOPNOTSUPP;
2782 goto out;
2783 }
2784
2785 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2786 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2787 ibqp->qp_num, attr_mask, cur_state, new_state);
2788
2789 err = -EOPNOTSUPP;
2790 goto out;
2791 }
2792 }
2793
c6215745
MS		 2794 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2795 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2796 if ((ibqp->qp_type == IB_QPT_RC) ||
2797 (ibqp->qp_type == IB_QPT_UD) ||
2798 (ibqp->qp_type == IB_QPT_UC) ||
2799 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2800 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2801 attr->port_num = mlx4_ib_bond_next_port(dev);
2802 }
2803 } else {
2804 /* no sense in changing port_num
2805 * when ports are bonded */
2806 attr_mask &= ~IB_QP_PORT;
2807 }
2808 }
2809
65adfa91 2810 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2811 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2812 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2813 "for transition %d to %d. qp_type %d\n",
2814 ibqp->qp_num, attr->port_num, cur_state,
2815 new_state, ibqp->qp_type);
65adfa91
MT		 2816 goto out;
2817 }
2818
3987a2d3
OG		 2819 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2820 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2821 IB_LINK_LAYER_ETHERNET))
2822 goto out;
2823
5ae2a7a8
RD		 2824 if (attr_mask & IB_QP_PKEY_INDEX) {
2825 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2826 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2827 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2828 "for transition %d to %d. qp_type %d\n",
2829 ibqp->qp_num, attr->pkey_index, cur_state,
2830 new_state, ibqp->qp_type);
5ae2a7a8 2831 goto out;
b1d8eb5a 2832 }
5ae2a7a8
RD		 2833 }
2834
65adfa91
MT		 2835 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2836 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2837 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2838 "Transition %d to %d. qp_type %d\n",
2839 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2840 new_state, ibqp->qp_type);
65adfa91
MT		 2841 goto out;
2842 }
2843
2844 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2845 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2846 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2847 "Transition %d to %d. qp_type %d\n",
2848 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2849 new_state, ibqp->qp_type);
65adfa91
MT		 2850 goto out;
2851 }
2852
2853 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2854 err = 0;
2855 goto out;
2856 }
2857
3078f5f1
GL		 2858 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2859 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2860 if (err)
2861 goto out;
2862 }
2863
400b1ebc
GL		 2864 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2865 cur_state, new_state);
65adfa91 2866
3078f5f1
GL		 2867 if (ibqp->rwq_ind_tbl && err)
2868 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2869
c6215745
MS		 2870 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2871 attr->port_num = 1;
2872
65adfa91
MT		 2873out:
2874 mutex_unlock(&qp->mutex);
2875 return err;
2876}
2877
e1b866c6
MS		 2878int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2879 int attr_mask, struct ib_udata *udata)
2880{
2881 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2882 int ret;
2883
2884 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2885
2886 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2887 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2888 int err = 0;
2889
2890 if (sqp->roce_v2_gsi)
2891 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2892 if (err)
2893 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2894 err);
2895 }
2896 return ret;
2897}
2898
99ec41d0
JM		 2899static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2900{
2901 int i;
2902 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2903 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2904 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2905 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2906 return 0;
2907 }
2908 }
2909 return -EINVAL;
2910}
2911
1ffeb2eb 2912static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2913 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2914 void *wqe, unsigned *mlx_seg_len)
2915{
2916 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2917 struct ib_device *ib_dev = &mdev->ib_dev;
2918 struct mlx4_wqe_mlx_seg *mlx = wqe;
2919 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2920 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2921 u16 pkey;
2922 u32 qkey;
2923 int send_size;
2924 int header_size;
2925 int spc;
2926 int i;
2927
e622f2f4 2928 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2929 return -EINVAL;
2930
2931 send_size = 0;
2932
e622f2f4
CH		 2933 for (i = 0; i < wr->wr.num_sge; ++i)
2934 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2935
2936 /* for proxy-qp0 sends, need to add in size of tunnel header */
2937 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2938 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2939 send_size += sizeof (struct mlx4_ib_tunnel_header);
2940
25f40220 2941 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2942
2943 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2944 sqp->ud_header.lrh.service_level =
2945 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2946 sqp->ud_header.lrh.destination_lid =
2947 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2948 sqp->ud_header.lrh.source_lid =
2949 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2950 }
2951
2952 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2953
2954 /* force loopback */
2955 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2956 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2957
2958 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2959 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2960 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2961 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2962 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2963 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2964 else
2965 sqp->ud_header.bth.destination_qpn =
c73c8b1e 2966 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
1ffeb2eb
JM		 2967
2968 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2969 if (mlx4_is_master(mdev->dev)) {
2970 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2971 return -EINVAL;
2972 } else {
2973 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2974 return -EINVAL;
2975 }
1ffeb2eb
JM		 2976 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2977 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2978
2979 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2980 sqp->ud_header.immediate_present = 0;
2981
2982 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2983
2984 /*
2985 * Inline data segments may not cross a 64 byte boundary. If
2986 * our UD header is bigger than the space available up to the
2987 * next 64 byte boundary in the WQE, use two inline data
2988 * segments to hold the UD header.
2989 */
2990 spc = MLX4_INLINE_ALIGN -
2991 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2992 if (header_size <= spc) {
2993 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2994 memcpy(inl + 1, sqp->header_buf, header_size);
2995 i = 1;
2996 } else {
2997 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2998 memcpy(inl + 1, sqp->header_buf, spc);
2999
3000 inl = (void *) (inl + 1) + spc;
3001 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3002 /*
3003 * Need a barrier here to make sure all the data is
3004 * visible before the byte_count field is set.
3005 * Otherwise the HCA prefetcher could grab the 64-byte
3006 * chunk with this inline segment and get a valid (!=
3007 * 0xffffffff) byte count but stale data, and end up
3008 * generating a packet with bad headers.
3009 *
3010 * The first inline segment's byte_count field doesn't
3011 * need a barrier, because it comes after a
3012 * control/MLX segment and therefore is at an offset
3013 * of 16 mod 64.
3014 */
3015 wmb();
3016 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3017 i = 2;
3018 }
3019
3020 *mlx_seg_len =
3021 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3022 return 0;
3023}
3024
fd10ed8e
JM		 3025static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3026{
3027 union sl2vl_tbl_to_u64 tmp_vltab;
3028 u8 vl;
3029
3030 if (sl > 15)
3031 return 0xf;
3032 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3033 vl = tmp_vltab.sl8[sl >> 1];
3034 if (sl & 1)
3035 vl &= 0x0f;
3036 else
3037 vl >>= 4;
3038 return vl;
3039}
3040
a748d60d
TB		 3041static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3042 int index, union ib_gid *gid,
3043 enum ib_gid_type *gid_type)
3044{
3045 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3046 struct mlx4_port_gid_table *port_gid_table;
3047 unsigned long flags;
3048
3049 port_gid_table = &iboe->gids[port_num - 1];
3050 spin_lock_irqsave(&iboe->lock, flags);
3051 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3052 *gid_type = port_gid_table->gids[index].gid_type;
3053 spin_unlock_irqrestore(&iboe->lock, flags);
3054 if (!memcmp(gid, &zgid, sizeof(*gid)))
3055 return -ENOENT;
3056
3057 return 0;
3058}
3059
3ef967a4 3060#define MLX4_ROCEV2_QP1_SPORT 0xC000
e622f2f4 3061static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 3062 void *wqe, unsigned *mlx_seg_len)
225c7b1f 3063{
a478868a 3064 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 3065 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 3066 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 3067 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 3068 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 3069 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 3070 union ib_gid sgid;
225c7b1f
RD		 3071 u16 pkey;
3072 int send_size;
3073 int header_size;
e61ef241 3074 int spc;
225c7b1f 3075 int i;
1ffeb2eb 3076 int err = 0;
57d88cff 3077 u16 vlan = 0xffff;
a29bec12
RD		 3078 bool is_eth;
3079 bool is_vlan = false;
3080 bool is_grh;
3ef967a4
MS		 3081 bool is_udp = false;
3082 int ip_version = 0;
225c7b1f
RD		 3083
3084 send_size = 0;
e622f2f4
CH		 3085 for (i = 0; i < wr->wr.num_sge; ++i)
3086 send_size += wr->wr.sg_list[i].length;
225c7b1f 3087
fa417f7b
EC		 3088 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3089 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3090 if (is_eth) {
a748d60d 3091 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3092 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3093 /* When multi-function is enabled, the ib_core gid
3094 * indexes don't necessarily match the hw ones, so
3095 * we must use our own cache */
6ee51a4e
JM		 3096 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3097 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3098 ah->av.ib.gid_index, &sgid.raw[0]);
3099 if (err)
3100 return err;
1ffeb2eb 3101 } else {
a748d60d
TB		 3102 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3103 ah->av.ib.gid_index,
3104 &sgid, &gid_type);
3ef967a4 3105 if (!err) {
a748d60d 3106 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3107 if (is_udp) {
3108 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3109 ip_version = 4;
3110 else
3111 ip_version = 6;
3112 is_grh = false;
3113 }
3114 } else {
1ffeb2eb 3115 return err;
3ef967a4 3116 }
1ffeb2eb 3117 }
0e9855db 3118 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 3119 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3120 is_vlan = 1;
3121 }
4c3eb3ca 3122 }
25f40220 3123 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3124 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3125 if (err)
3126 return err;
fa417f7b
EC		 3127
3128 if (!is_eth) {
3129 sqp->ud_header.lrh.service_level =
3130 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3131 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3132 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3133 }
225c7b1f 3134
3ef967a4 3135 if (is_grh || (ip_version == 6)) {
225c7b1f 3136 sqp->ud_header.grh.traffic_class =
fa417f7b 3137 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3138 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3139 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3140 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3141 if (is_eth) {
6ee51a4e 3142 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3143 } else {
3144 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3145 /* When multi-function is enabled, the ib_core gid
3146 * indexes don't necessarily match the hw ones, so
3147 * we must use our own cache
3148 */
3149 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3150 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3151 demux[sqp->qp.port - 1].
3152 subnet_prefix)));
baa0be70
JM		 3153 sqp->ud_header.grh.source_gid.global.interface_id =
3154 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3155 guid_cache[ah->av.ib.gid_index];
3156 } else {
3157 ib_get_cached_gid(ib_dev,
3158 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3159 ah->av.ib.gid_index,
3160 &sqp->ud_header.grh.source_gid, NULL);
3161 }
6ee51a4e 3162 }
225c7b1f 3163 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3164 ah->av.ib.dgid, 16);
225c7b1f
RD		 3165 }
3166
3ef967a4
MS		 3167 if (ip_version == 4) {
3168 sqp->ud_header.ip4.tos =
3169 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3170 sqp->ud_header.ip4.id = 0;
3171 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3172 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3173
3174 memcpy(&sqp->ud_header.ip4.saddr,
3175 sgid.raw + 12, 4);
3176 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3177 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3178 }
3179
3180 if (is_udp) {
3181 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3182 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3183 sqp->ud_header.udp.csum = 0;
3184 }
3185
225c7b1f 3186 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3187
3188 if (!is_eth) {
3189 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3190 (sqp->ud_header.lrh.destination_lid ==
3191 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3192 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3193 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3194 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3195 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3196 }
225c7b1f 3197
e622f2f4 3198 switch (wr->wr.opcode) {
225c7b1f
RD		 3199 case IB_WR_SEND:
3200 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3201 sqp->ud_header.immediate_present = 0;
3202 break;
3203 case IB_WR_SEND_WITH_IMM:
3204 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3205 sqp->ud_header.immediate_present = 1;
e622f2f4 3206 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3207 break;
3208 default:
3209 return -EINVAL;
3210 }
3211
fa417f7b 3212 if (is_eth) {
6ee51a4e 3213 struct in6_addr in6;
3ef967a4 3214 u16 ether_type;
c0c1d3d7
OD		 3215 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3216
69ae5439 3217 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3218 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3219
c0c1d3d7 3220 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3221
1049f138 3222 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3223 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3224 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3225 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3226 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3227
3e0629cb 3228
fa417f7b
EC		 3229 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3230 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3231 if (!is_vlan) {
3ef967a4 3232 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3233 } else {
3ef967a4 3234 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3235 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3236 }
fa417f7b 3237 } else {
fd10ed8e
JM		 3238 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3239 sl_to_vl(to_mdev(ib_dev),
3240 sqp->ud_header.lrh.service_level,
3241 sqp->qp.port);
3242 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3243 return -EINVAL;
fa417f7b
EC		 3244 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3245 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3246 }
e622f2f4 3247 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 3248 if (!sqp->qp.ibqp.qp_num)
3249 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3250 else
e622f2f4 3251 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 3252 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3253 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3254 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3255 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3256 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3257 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3258
3259 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3260
3261 if (0) {
987c8f8f 3262 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3263 for (i = 0; i < header_size / 4; ++i) {
3264 if (i % 8 == 0)
987c8f8f
SP		 3265 pr_err(" [%02x] ", i * 4);
3266 pr_cont(" %08x",
3267 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3268 if ((i + 1) % 8 == 0)
987c8f8f 3269 pr_cont("\n");
225c7b1f 3270 }
987c8f8f 3271 pr_err("\n");
225c7b1f
RD		 3272 }
3273
e61ef241
RD		 3274 /*
3275 * Inline data segments may not cross a 64 byte boundary. If
3276 * our UD header is bigger than the space available up to the
3277 * next 64 byte boundary in the WQE, use two inline data
3278 * segments to hold the UD header.
3279 */
3280 spc = MLX4_INLINE_ALIGN -
3281 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3282 if (header_size <= spc) {
3283 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3284 memcpy(inl + 1, sqp->header_buf, header_size);
3285 i = 1;
3286 } else {
3287 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3288 memcpy(inl + 1, sqp->header_buf, spc);
3289
3290 inl = (void *) (inl + 1) + spc;
3291 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3292 /*
3293 * Need a barrier here to make sure all the data is
3294 * visible before the byte_count field is set.
3295 * Otherwise the HCA prefetcher could grab the 64-byte
3296 * chunk with this inline segment and get a valid (!=
3297 * 0xffffffff) byte count but stale data, and end up
3298 * generating a packet with bad headers.
3299 *
3300 * The first inline segment's byte_count field doesn't
3301 * need a barrier, because it comes after a
3302 * control/MLX segment and therefore is at an offset
3303 * of 16 mod 64.
3304 */
3305 wmb();
3306 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3307 i = 2;
3308 }
225c7b1f 3309
f438000f
RD		 3310 *mlx_seg_len =
3311 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3312 return 0;
225c7b1f
RD		 3313}
3314
3315static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3316{
3317 unsigned cur;
3318 struct mlx4_ib_cq *cq;
3319
3320 cur = wq->head - wq->tail;
0e6e7416 3321 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3322 return 0;
3323
3324 cq = to_mcq(ib_cq);
3325 spin_lock(&cq->lock);
3326 cur = wq->head - wq->tail;
3327 spin_unlock(&cq->lock);
3328
0e6e7416 3329 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3330}
3331
95d04f07
RD		 3332static __be32 convert_access(int acc)
3333{
6ff63e19
SM		 3334 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3335 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3336 (acc & IB_ACCESS_REMOTE_WRITE ?
3337 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3338 (acc & IB_ACCESS_REMOTE_READ ?
3339 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3340 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3341 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3342}
3343
1b2cd0fc
SG		 3344static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3345 struct ib_reg_wr *wr)
3346{
3347 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3348
3349 fseg->flags = convert_access(wr->access);
3350 fseg->mem_key = cpu_to_be32(wr->key);
3351 fseg->buf_list = cpu_to_be64(mr->page_map);
3352 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3353 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3354 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3355 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3356 fseg->reserved[0] = 0;
3357 fseg->reserved[1] = 0;
3358}
3359
95d04f07
RD		 3360static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3361{
aee38fad
SM		 3362 memset(iseg, 0, sizeof(*iseg));
3363 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3364}
3365
0fbfa6a9
RD		 3366static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3367 u64 remote_addr, u32 rkey)
3368{
3369 rseg->raddr = cpu_to_be64(remote_addr);
3370 rseg->rkey = cpu_to_be32(rkey);
3371 rseg->reserved = 0;
3372}
3373
e622f2f4
CH		 3374static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3375 struct ib_atomic_wr *wr)
0fbfa6a9 3376{
e622f2f4
CH		 3377 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3378 aseg->swap_add = cpu_to_be64(wr->swap);
3379 aseg->compare = cpu_to_be64(wr->compare_add);
3380 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3381 aseg->swap_add = cpu_to_be64(wr->compare_add);
3382 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3383 } else {
e622f2f4 3384 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3385 aseg->compare = 0;
3386 }
3387
3388}
3389
6fa8f719 3390static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 3391 struct ib_atomic_wr *wr)
6fa8f719 3392{
e622f2f4
CH		 3393 aseg->swap_add = cpu_to_be64(wr->swap);
3394 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3395 aseg->compare = cpu_to_be64(wr->compare_add);
3396 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3397}
3398
0fbfa6a9 3399static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 3400 struct ib_ud_wr *wr)
0fbfa6a9 3401{
e622f2f4
CH		 3402 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3403 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3404 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3405 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3406 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3407}
3408
1ffeb2eb
JM		 3409static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3410 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 3411 struct ib_ud_wr *wr,
97982f5a 3412 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3413{
e622f2f4 3414 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3415 struct mlx4_av sqp_av = {0};
3416 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3417
3418 /* force loopback */
3419 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3420 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3421 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3422 cpu_to_be32(0xf0000000);
3423
3424 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3425 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3426 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3427 else
c73c8b1e 3428 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3429 /* Use QKEY from the QP context, which is set by master */
3430 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3431}
3432
e622f2f4 3433static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 3434{
3435 struct mlx4_wqe_inline_seg *inl = wqe;
3436 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3437 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3438 int spc;
3439 int i;
3440
3441 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3442 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3443 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3444 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3445 memcpy(hdr.mac, ah->av.eth.mac, 6);
3446 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3447
3448 spc = MLX4_INLINE_ALIGN -
3449 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3450 if (sizeof (hdr) <= spc) {
3451 memcpy(inl + 1, &hdr, sizeof (hdr));
3452 wmb();
3453 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3454 i = 1;
3455 } else {
3456 memcpy(inl + 1, &hdr, spc);
3457 wmb();
3458 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3459
3460 inl = (void *) (inl + 1) + spc;
3461 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3462 wmb();
3463 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3464 i = 2;
3465 }
3466
3467 *mlx_seg_len =
3468 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3469}
3470
6e694ea3
JM		 3471static void set_mlx_icrc_seg(void *dseg)
3472{
3473 u32 *t = dseg;
3474 struct mlx4_wqe_inline_seg *iseg = dseg;
3475
3476 t[1] = 0;
3477
3478 /*
3479 * Need a barrier here before writing the byte_count field to
3480 * make sure that all the data is visible before the
3481 * byte_count field is set. Otherwise, if the segment begins
3482 * a new cacheline, the HCA prefetcher could grab the 64-byte
3483 * chunk and get a valid (!= * 0xffffffff) byte count but
3484 * stale data, and end up sending the wrong data.
3485 */
3486 wmb();
3487
3488 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3489}
3490
3491static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3492{
d420d9e3
RD		 3493 dseg->lkey = cpu_to_be32(sg->lkey);
3494 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3495
3496 /*
3497 * Need a barrier here before writing the byte_count field to
3498 * make sure that all the data is visible before the
3499 * byte_count field is set. Otherwise, if the segment begins
3500 * a new cacheline, the HCA prefetcher could grab the 64-byte
3501 * chunk and get a valid (!= * 0xffffffff) byte count but
3502 * stale data, and end up sending the wrong data.
3503 */
3504 wmb();
3505
3506 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3507}
3508
2242fa4f
RD		 3509static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3510{
3511 dseg->byte_count = cpu_to_be32(sg->length);
3512 dseg->lkey = cpu_to_be32(sg->lkey);
3513 dseg->addr = cpu_to_be64(sg->addr);
3514}
3515
e622f2f4 3516static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 3517 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 3518 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3519{
e622f2f4 3520 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3521
417608c2
EC		 3522 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3523 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3524
3525 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3526 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3527 return -EINVAL;
3528
e622f2f4 3529 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3530
e622f2f4 3531 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3532 *lso_seg_len = halign;
3533 return 0;
3534}
3535
95d04f07
RD		 3536static __be32 send_ieth(struct ib_send_wr *wr)
3537{
3538 switch (wr->opcode) {
3539 case IB_WR_SEND_WITH_IMM:
3540 case IB_WR_RDMA_WRITE_WITH_IMM:
3541 return wr->ex.imm_data;
3542
3543 case IB_WR_SEND_WITH_INV:
3544 return cpu_to_be32(wr->ex.invalidate_rkey);
3545
3546 default:
3547 return 0;
3548 }
3549}
3550
1ffeb2eb
JM		 3551static void add_zero_len_inline(void *wqe)
3552{
3553 struct mlx4_wqe_inline_seg *inl = wqe;
3554 memset(wqe, 0, 16);
3555 inl->byte_count = cpu_to_be32(1 << 31);
3556}
3557
225c7b1f
RD		 3558int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3559 struct ib_send_wr **bad_wr)
3560{
3561 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3562 void *wqe;
3563 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3564 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3565 unsigned long flags;
3566 int nreq;
3567 int err = 0;
ea54b10c
JM		 3568 unsigned ind;
3569 int uninitialized_var(stamp);
3570 int uninitialized_var(size);
a3d8e159 3571 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 3572 __be32 dummy;
3573 __be32 *lso_wqe;
3574 __be32 uninitialized_var(lso_hdr_sz);
417608c2 3575 __be32 blh;
225c7b1f 3576 int i;
35f05dab 3577 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3578
e1b866c6
MS		 3579 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3580 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3581
3582 if (sqp->roce_v2_gsi) {
3583 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3584 enum ib_gid_type gid_type;
e1b866c6
MS		 3585 union ib_gid gid;
3586
a748d60d
TB		 3587 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3588 ah->av.ib.gid_index,
3589 &gid, &gid_type))
3590 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3591 to_mqp(sqp->roce_v2_gsi) : qp;
3592 else
e1b866c6
MS		 3593 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3594 ah->av.ib.gid_index);
e1b866c6
MS		 3595 }
3596 }
3597
96db0e03 3598 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 3599 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3600 err = -EIO;
3601 *bad_wr = wr;
3602 nreq = 0;
3603 goto out;
3604 }
225c7b1f 3605
ea54b10c 3606 ind = qp->sq_next_wqe;
225c7b1f
RD		 3607
3608 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3609 lso_wqe = &dummy;
417608c2 3610 blh = 0;
0fd7e1d8 3611
225c7b1f
RD		 3612 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3613 err = -ENOMEM;
3614 *bad_wr = wr;
3615 goto out;
3616 }
3617
3618 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3619 err = -EINVAL;
3620 *bad_wr = wr;
3621 goto out;
3622 }
3623
0e6e7416 3624 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3625 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3626
3627 ctrl->srcrb_flags =
3628 (wr->send_flags & IB_SEND_SIGNALED ?
3629 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3630 (wr->send_flags & IB_SEND_SOLICITED ?
3631 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3632 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3633 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3634 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3635 qp->sq_signal_bits;
3636
95d04f07 3637 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3638
3639 wqe += sizeof *ctrl;
3640 size = sizeof *ctrl / 16;
3641
1ffeb2eb
JM		 3642 switch (qp->mlx4_ib_qp_type) {
3643 case MLX4_IB_QPT_RC:
3644 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3645 switch (wr->opcode) {
3646 case IB_WR_ATOMIC_CMP_AND_SWP:
3647 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3648 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3649 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3650 atomic_wr(wr)->rkey);
225c7b1f
RD		 3651 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3652
e622f2f4 3653 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3654 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3655
225c7b1f
RD		 3656 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3657 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3658
3659 break;
3660
3661 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3662 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3663 atomic_wr(wr)->rkey);
6fa8f719
VS		 3664 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3665
e622f2f4 3666 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3667 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3668
3669 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3670 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3671
3672 break;
3673
3674 case IB_WR_RDMA_READ:
3675 case IB_WR_RDMA_WRITE:
3676 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3677 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3678 rdma_wr(wr)->rkey);
225c7b1f
RD		 3679 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3680 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3681 break;
95d04f07
RD		 3682
3683 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3684 ctrl->srcrb_flags |=
3685 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3686 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3687 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3688 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3689 break;
3690
1b2cd0fc
SG		 3691 case IB_WR_REG_MR:
3692 ctrl->srcrb_flags |=
3693 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3694 set_reg_seg(wqe, reg_wr(wr));
3695 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3696 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3697 break;
3698
225c7b1f
RD		 3699 default:
3700 /* No extra segments required for sends */
3701 break;
3702 }
3703 break;
3704
1ffeb2eb 3705 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3706 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3707 ctrl, &seglen);
1ffeb2eb
JM		 3708 if (unlikely(err)) {
3709 *bad_wr = wr;
3710 goto out;
3711 }
3712 wqe += seglen;
3713 size += seglen / 16;
3714 break;
3715 case MLX4_IB_QPT_TUN_SMI:
3716 case MLX4_IB_QPT_TUN_GSI:
3717 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3718 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3719 /* set the forced-loopback bit in the data seg av */
3720 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3721 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3722 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3723 break;
3724 case MLX4_IB_QPT_UD:
e622f2f4 3725 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3726 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3727 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3728
3729 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3730 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3731 &lso_hdr_sz, &blh);
b832be1e
EC		 3732 if (unlikely(err)) {
3733 *bad_wr = wr;
3734 goto out;
3735 }
0fd7e1d8 3736 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3737 wqe += seglen;
3738 size += seglen / 16;
3739 }
225c7b1f
RD		 3740 break;
3741
1ffeb2eb 3742 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3743 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3744 ctrl, &seglen);
1ffeb2eb
JM		 3745 if (unlikely(err)) {
3746 *bad_wr = wr;
3747 goto out;
3748 }
3749 wqe += seglen;
3750 size += seglen / 16;
3751 /* to start tunnel header on a cache-line boundary */
3752 add_zero_len_inline(wqe);
3753 wqe += 16;
3754 size++;
e622f2f4 3755 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3756 wqe += seglen;
3757 size += seglen / 16;
3758 break;
3759 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3760 case MLX4_IB_QPT_PROXY_GSI:
3761 /* If we are tunneling special qps, this is a UD qp.
3762 * In this case we first add a UD segment targeting
3763 * the tunnel qp, and then add a header with address
3764 * information */
e622f2f4
CH		 3765 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3766 ud_wr(wr),
97982f5a 3767 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3768 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3769 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3770 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3771 wqe += seglen;
3772 size += seglen / 16;
3773 break;
3774
3775 case MLX4_IB_QPT_SMI:
3776 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3777 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3778 &seglen);
f438000f 3779 if (unlikely(err)) {
225c7b1f
RD		 3780 *bad_wr = wr;
3781 goto out;
3782 }
f438000f
RD		 3783 wqe += seglen;
3784 size += seglen / 16;
225c7b1f
RD		 3785 break;
3786
3787 default:
3788 break;
3789 }
3790
6e694ea3
JM		 3791 /*
3792 * Write data segments in reverse order, so as to
3793 * overwrite cacheline stamp last within each
3794 * cacheline. This avoids issues with WQE
3795 * prefetching.
3796 */
225c7b1f 3797
6e694ea3
JM		 3798 dseg = wqe;
3799 dseg += wr->num_sge - 1;
3800 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3801
3802 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3803 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3804 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3805 qp->mlx4_ib_qp_type &
3806 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3807 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3808 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3809 }
3810
6e694ea3
JM		 3811 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3812 set_data_seg(dseg, wr->sg_list + i);
3813
0fd7e1d8
RD		 3814 /*
3815 * Possibly overwrite stamping in cacheline with LSO
3816 * segment only after making sure all data segments
3817 * are written.
3818 */
3819 wmb();
3820 *lso_wqe = lso_hdr_sz;
3821
224e92e0
BB		 3822 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3823 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3824
3825 /*
3826 * Make sure descriptor is fully written before
3827 * setting ownership bit (because HW can start
3828 * executing as soon as we do).
3829 */
3830 wmb();
3831
59b0ed12 3832 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3833 *bad_wr = wr;
225c7b1f
RD		 3834 err = -EINVAL;
3835 goto out;
3836 }
3837
3838 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3839 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3840
ea54b10c
JM		 3841 stamp = ind + qp->sq_spare_wqes;
3842 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3843
0e6e7416
RD		 3844 /*
3845 * We can improve latency by not stamping the last
3846 * send queue WQE until after ringing the doorbell, so
3847 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3848 *
3849 * Same optimization applies to padding with NOP wqe
3850 * in case of WQE shrinking (used to prevent wrap-around
3851 * in the middle of WR).
0e6e7416 3852 */
ea54b10c
JM		 3853 if (wr->next) {
3854 stamp_send_wqe(qp, stamp, size * 16);
3855 ind = pad_wraparound(qp, ind);
3856 }
225c7b1f
RD		 3857 }
3858
3859out:
3860 if (likely(nreq)) {
3861 qp->sq.head += nreq;
3862
3863 /*
3864 * Make sure that descriptors are written before
3865 * doorbell record.
3866 */
3867 wmb();
3868
3869 writel(qp->doorbell_qpn,
3870 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3871
3872 /*
3873 * Make sure doorbells don't leak out of SQ spinlock
3874 * and reach the HCA out of order.
3875 */
3876 mmiowb();
0e6e7416 3877
ea54b10c
JM		 3878 stamp_send_wqe(qp, stamp, size * 16);
3879
3880 ind = pad_wraparound(qp, ind);
3881 qp->sq_next_wqe = ind;
225c7b1f
RD		 3882 }
3883
96db0e03 3884 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3885
3886 return err;
3887}
3888
3889int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3890 struct ib_recv_wr **bad_wr)
3891{
3892 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3893 struct mlx4_wqe_data_seg *scat;
3894 unsigned long flags;
3895 int err = 0;
3896 int nreq;
3897 int ind;
1ffeb2eb 3898 int max_gs;
225c7b1f 3899 int i;
35f05dab 3900 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3901
1ffeb2eb 3902 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3903 spin_lock_irqsave(&qp->rq.lock, flags);
3904
35f05dab
YH		 3905 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3906 err = -EIO;
3907 *bad_wr = wr;
3908 nreq = 0;
3909 goto out;
3910 }
3911
0e6e7416 3912 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3913
3914 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3915 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3916 err = -ENOMEM;
3917 *bad_wr = wr;
3918 goto out;
3919 }
3920
3921 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3922 err = -EINVAL;
3923 *bad_wr = wr;
3924 goto out;
3925 }
3926
3927 scat = get_recv_wqe(qp, ind);
3928
1ffeb2eb
JM		 3929 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3930 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3931 ib_dma_sync_single_for_device(ibqp->device,
3932 qp->sqp_proxy_rcv[ind].map,
3933 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3934 DMA_FROM_DEVICE);
3935 scat->byte_count =
3936 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3937 /* use dma lkey from upper layer entry */
3938 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3939 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3940 scat++;
3941 max_gs--;
3942 }
3943
2242fa4f
RD		 3944 for (i = 0; i < wr->num_sge; ++i)
3945 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3946
1ffeb2eb 3947 if (i < max_gs) {
225c7b1f
RD		 3948 scat[i].byte_count = 0;
3949 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3950 scat[i].addr = 0;
3951 }
3952
3953 qp->rq.wrid[ind] = wr->wr_id;
3954
0e6e7416 3955 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3956 }
3957
3958out:
3959 if (likely(nreq)) {
3960 qp->rq.head += nreq;
3961
3962 /*
3963 * Make sure that descriptors are written before
3964 * doorbell record.
3965 */
3966 wmb();
3967
3968 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3969 }
3970
3971 spin_unlock_irqrestore(&qp->rq.lock, flags);
3972
3973 return err;
3974}
6a775e2b
JM		 3975
3976static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3977{
3978 switch (mlx4_state) {
3979 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3980 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3981 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3982 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3983 case MLX4_QP_STATE_SQ_DRAINING:
3984 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3985 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3986 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3987 default: return -1;
3988 }
3989}
3990
3991static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3992{
3993 switch (mlx4_mig_state) {
3994 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3995 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3996 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3997 default: return -1;
3998 }
3999}
4000
4001static int to_ib_qp_access_flags(int mlx4_flags)
4002{
4003 int ib_flags = 0;
4004
4005 if (mlx4_flags & MLX4_QP_BIT_RRE)
4006 ib_flags |= IB_ACCESS_REMOTE_READ;
4007 if (mlx4_flags & MLX4_QP_BIT_RWE)
4008 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4009 if (mlx4_flags & MLX4_QP_BIT_RAE)
4010 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4011
4012 return ib_flags;
4013}
4014
71d53ab4 4015static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 4016 struct rdma_ah_attr *ah_attr,
71d53ab4 4017 struct mlx4_qp_path *path)
6a775e2b 4018{
4c3eb3ca 4019 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 4020 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 4021
d8966fcd 4022 memset(ah_attr, 0, sizeof(*ah_attr));
44c58487 4023 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
d8966fcd 4024 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b
JM		 4025 return;
4026
44c58487 4027 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 4028 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4029 ((path->sched_queue & 4) << 1));
4c3eb3ca 4030 else
d8966fcd 4031 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 4032 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 4033
d8966fcd
DC		 4034 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4035 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4036 rdma_ah_set_static_rate(ah_attr,
4037 path->static_rate ? path->static_rate - 5 : 0);
4038 if (path->grh_mylmc & (1 << 7)) {
4039 rdma_ah_set_grh(ah_attr, NULL,
4040 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4041 path->mgid_index,
4042 path->hop_limit,
4043 (be32_to_cpu(path->tclass_flowlabel)
4044 >> 20) & 0xff);
4045 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 4046 }
4047}
4048
4049int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4050 struct ib_qp_init_attr *qp_init_attr)
4051{
4052 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4053 struct mlx4_ib_qp *qp = to_mqp(ibqp);
4054 struct mlx4_qp_context context;
4055 int mlx4_state;
0df67030
DB		 4056 int err = 0;
4057
3078f5f1
GL		 4058 if (ibqp->rwq_ind_tbl)
4059 return -EOPNOTSUPP;
4060
0df67030 4061 mutex_lock(&qp->mutex);
6a775e2b
JM		 4062
4063 if (qp->state == IB_QPS_RESET) {
4064 qp_attr->qp_state = IB_QPS_RESET;
4065 goto done;
4066 }
4067
4068 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 4069 if (err) {
4070 err = -EINVAL;
4071 goto out;
4072 }
6a775e2b
JM		 4073
4074 mlx4_state = be32_to_cpu(context.flags) >> 28;
4075
0df67030
DB		 4076 qp->state = to_ib_qp_state(mlx4_state);
4077 qp_attr->qp_state = qp->state;
6a775e2b
JM		 4078 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4079 qp_attr->path_mig_state =
4080 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4081 qp_attr->qkey = be32_to_cpu(context.qkey);
4082 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4083 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4084 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4085 qp_attr->qp_access_flags =
4086 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4087
4088 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 4089 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4090 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4091 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4092 qp_attr->alt_port_num =
4093 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4094 }
4095
4096 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4097 if (qp_attr->qp_state == IB_QPS_INIT)
4098 qp_attr->port_num = qp->port;
4099 else
4100 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4101
4102 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4103 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4104
4105 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4106
4107 qp_attr->max_dest_rd_atomic =
4108 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4109 qp_attr->min_rnr_timer =
4110 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4111 qp_attr->timeout = context.pri_path.ackto >> 3;
4112 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4113 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4114 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4115
4116done:
4117 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4118 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4119 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4120
6a775e2b 4121 if (!ibqp->uobject) {
7f5eb9bb
RD		 4122 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4123 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4124 } else {
4125 qp_attr->cap.max_send_wr = 0;
4126 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4127 }
4128
7f5eb9bb
RD		 4129 /*
4130 * We don't support inline sends for kernel QPs (yet), and we
4131 * don't know what userspace's value should be.
4132 */
4133 qp_attr->cap.max_inline_data = 0;
4134
4135 qp_init_attr->cap = qp_attr->cap;
4136
521e575b
RL		 4137 qp_init_attr->create_flags = 0;
4138 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4139 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4140
4141 if (qp->flags & MLX4_IB_QP_LSO)
4142 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4143
c1c98501
MB		 4144 if (qp->flags & MLX4_IB_QP_NETIF)
4145 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4146
46db567d
DB		 4147 qp_init_attr->sq_sig_type =
4148 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4149 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4150
0df67030
DB		 4151out:
4152 mutex_unlock(&qp->mutex);
4153 return err;
6a775e2b
JM		 4154}
4155
400b1ebc
GL		 4156struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4157 struct ib_wq_init_attr *init_attr,
4158 struct ib_udata *udata)
4159{
4160 struct mlx4_ib_dev *dev;
4161 struct ib_qp_init_attr ib_qp_init_attr;
4162 struct mlx4_ib_qp *qp;
4163 struct mlx4_ib_create_wq ucmd;
4164 int err, required_cmd_sz;
4165
4166 if (!(udata && pd->uobject))
4167 return ERR_PTR(-EINVAL);
4168
078b3573
GL		 4169 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4170 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4171 if (udata->inlen < required_cmd_sz) {
4172 pr_debug("invalid inlen\n");
4173 return ERR_PTR(-EINVAL);
4174 }
4175
4176 if (udata->inlen > sizeof(ucmd) &&
4177 !ib_is_udata_cleared(udata, sizeof(ucmd),
4178 udata->inlen - sizeof(ucmd))) {
4179 pr_debug("inlen is not supported\n");
4180 return ERR_PTR(-EOPNOTSUPP);
4181 }
4182
4183 if (udata->outlen)
4184 return ERR_PTR(-EOPNOTSUPP);
4185
4186 dev = to_mdev(pd->device);
4187
4188 if (init_attr->wq_type != IB_WQT_RQ) {
4189 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4190 return ERR_PTR(-EOPNOTSUPP);
4191 }
4192
4193 if (init_attr->create_flags) {
4194 pr_debug("unsupported create_flags %u\n",
4195 init_attr->create_flags);
4196 return ERR_PTR(-EOPNOTSUPP);
4197 }
4198
4199 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4200 if (!qp)
4201 return ERR_PTR(-ENOMEM);
4202
4203 qp->pri.vid = 0xFFFF;
4204 qp->alt.vid = 0xFFFF;
4205
4206 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4207 ib_qp_init_attr.qp_context = init_attr->wq_context;
4208 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4209 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4210 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4211 ib_qp_init_attr.recv_cq = init_attr->cq;
4212 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4213
4214 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4215 udata, 0, &qp);
4216 if (err) {
4217 kfree(qp);
4218 return ERR_PTR(err);
4219 }
4220
4221 qp->ibwq.event_handler = init_attr->event_handler;
4222 qp->ibwq.wq_num = qp->mqp.qpn;
4223 qp->ibwq.state = IB_WQS_RESET;
4224
4225 return &qp->ibwq;
4226}
4227
4228static int ib_wq2qp_state(enum ib_wq_state state)
4229{
4230 switch (state) {
4231 case IB_WQS_RESET:
4232 return IB_QPS_RESET;
4233 case IB_WQS_RDY:
4234 return IB_QPS_RTR;
4235 default:
4236 return IB_QPS_ERR;
4237 }
4238}
4239
4240static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4241{
4242 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4243 enum ib_qp_state qp_cur_state;
4244 enum ib_qp_state qp_new_state;
4245 int attr_mask;
4246 int err;
4247
4248 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4249 * the WQ logic state.
4250 */
4251 qp_cur_state = qp->state;
4252 qp_new_state = ib_wq2qp_state(new_state);
4253
4254 if (ib_wq2qp_state(new_state) == qp_cur_state)
4255 return 0;
4256
4257 if (new_state == IB_WQS_RDY) {
4258 struct ib_qp_attr attr = {};
4259
4260 attr.port_num = qp->port;
4261 attr_mask = IB_QP_PORT;
4262
4263 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4264 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4265 if (err) {
4266 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4267 ibwq->wq_num);
4268 return err;
4269 }
4270
4271 qp_cur_state = IB_QPS_INIT;
4272 }
4273
4274 attr_mask = 0;
4275 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4276 qp_cur_state, qp_new_state);
4277
4278 if (err && (qp_cur_state == IB_QPS_INIT)) {
4279 qp_new_state = IB_QPS_RESET;
4280 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4281 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4282 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4283 ibwq->wq_num);
4284 qp_new_state = IB_QPS_INIT;
4285 }
4286 }
4287
4288 qp->state = qp_new_state;
4289
4290 return err;
4291}
4292
4293int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4294 u32 wq_attr_mask, struct ib_udata *udata)
4295{
4296 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4297 struct mlx4_ib_modify_wq ucmd = {};
4298 size_t required_cmd_sz;
4299 enum ib_wq_state cur_state, new_state;
4300 int err = 0;
4301
4302 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4303 sizeof(ucmd.reserved);
4304 if (udata->inlen < required_cmd_sz)
4305 return -EINVAL;
4306
4307 if (udata->inlen > sizeof(ucmd) &&
4308 !ib_is_udata_cleared(udata, sizeof(ucmd),
4309 udata->inlen - sizeof(ucmd)))
4310 return -EOPNOTSUPP;
4311
4312 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4313 return -EFAULT;
4314
4315 if (ucmd.comp_mask || ucmd.reserved)
4316 return -EOPNOTSUPP;
4317
4318 if (wq_attr_mask & IB_WQ_FLAGS)
4319 return -EOPNOTSUPP;
4320
4321 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4322 ibwq->state;
4323 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4324
4325 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4326 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4327 return -EINVAL;
4328
4329 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4330 return -EINVAL;
4331
4332 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4333 return -EINVAL;
4334
3078f5f1
GL		 4335 /* Need to protect against the parent RSS which also may modify WQ
4336 * state.
4337 */
4338 mutex_lock(&qp->mutex);
4339
400b1ebc
GL		 4340 /* Can update HW state only if a RSS QP has already associated to this
4341 * WQ, so we can apply its port on the WQ.
4342 */
4343 if (qp->rss_usecnt)
4344 err = _mlx4_ib_modify_wq(ibwq, new_state);
4345
4346 if (!err)
4347 ibwq->state = new_state;
4348
3078f5f1
GL		 4349 mutex_unlock(&qp->mutex);
4350
400b1ebc
GL		 4351 return err;
4352}
4353
4354int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4355{
4356 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4357 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4358
4359 if (qp->counter_index)
4360 mlx4_ib_free_qp_counter(dev, qp);
4361
4362 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4363
4364 kfree(qp);
4365
4366 return 0;
4367}
b8d46ca0
GL		 4368
4369struct ib_rwq_ind_table
4370*mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4371 struct ib_rwq_ind_table_init_attr *init_attr,
4372 struct ib_udata *udata)
4373{
4374 struct ib_rwq_ind_table *rwq_ind_table;
4375 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4376 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4377 unsigned int base_wqn;
4378 size_t min_resp_len;
4379 int i;
4380 int err;
4381
4382 if (udata->inlen > 0 &&
4383 !ib_is_udata_cleared(udata, 0,
4384 udata->inlen))
4385 return ERR_PTR(-EOPNOTSUPP);
4386
4387 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4388 if (udata->outlen && udata->outlen < min_resp_len)
4389 return ERR_PTR(-EINVAL);
4390
4391 if (ind_tbl_size >
4392 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4393 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4394 ind_tbl_size,
4395 device->attrs.rss_caps.max_rwq_indirection_table_size);
4396 return ERR_PTR(-EINVAL);
4397 }
4398
4399 base_wqn = init_attr->ind_tbl[0]->wq_num;
4400
4401 if (base_wqn % ind_tbl_size) {
4402 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4403 base_wqn);
4404 return ERR_PTR(-EINVAL);
4405 }
4406
4407 for (i = 1; i < ind_tbl_size; i++) {
4408 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4409 pr_debug("indirection table's WQNs aren't consecutive\n");
4410 return ERR_PTR(-EINVAL);
4411 }
4412 }
4413
4414 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4415 if (!rwq_ind_table)
4416 return ERR_PTR(-ENOMEM);
4417
4418 if (udata->outlen) {
4419 resp.response_length = offsetof(typeof(resp), response_length) +
4420 sizeof(resp.response_length);
4421 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4422 if (err)
4423 goto err;
4424 }
4425
4426 return rwq_ind_table;
4427
4428err:
4429 kfree(rwq_ind_table);
4430 return ERR_PTR(err);
4431}
4432
4433int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4434{
4435 kfree(ib_rwq_ind_tbl);
4436 return 0;
4437}
Linux 6.x block layer and io_uring tree(s)