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IB/verbs: Add helper function rdma_udata_to_drv_context
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
225c7b1f 44
2f48485d 45#include <linux/mlx4/driver.h>
225c7b1f
RD		 46#include <linux/mlx4/qp.h>
47
48#include "mlx4_ib.h"
9ce28a20 49#include <rdma/mlx4-abi.h>
225c7b1f 50
35f05dab
YH		 51static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
3078f5f1 55static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
35f05dab 56
225c7b1f
RD		 57enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59};
60
61enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 66};
67
68enum {
69 /*
fa417f7b 70 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
225c7b1f 74 */
4c3eb3ca 75 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 76 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 77};
78
79struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
e1b866c6 86 struct ib_qp *roce_v2_gsi;
225c7b1f
RD		 87};
88
83904132 89enum {
417608c2
EC		 90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 92};
93
3987a2d3
OG		 94enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97};
98
297e0dad
MS		 99#ifndef ETH_ALEN
100#define ETH_ALEN 6
101#endif
297e0dad 102
225c7b1f 103static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 117};
118
400b1ebc
GL		 119enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122};
123
225c7b1f
RD		 124static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125{
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127}
128
1ffeb2eb
JM		 129static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130{
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
47605df9
JM		 134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 137}
138
225c7b1f
RD		 139static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140{
47605df9
JM		 141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
e1b866c6
MS		 160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 164}
165
1ffeb2eb 166/* used for INIT/CLOSE port logic */
225c7b1f
RD		 167static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168{
47605df9
JM		 169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
225c7b1f
RD		 188}
189
190static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191{
1c69fc2a 192 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 193}
194
195static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196{
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198}
199
200static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201{
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203}
204
0e6e7416
RD		 205/*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
f95ccffc
JM		 207 * first four bytes of every 64 byte chunk with 0xffffffff, except for
208 * the very first chunk of the WQE.
0e6e7416 209 */
f95ccffc 210static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
0e6e7416 211{
d2ae16d5 212 __be32 *wqe;
0e6e7416 213 int i;
ea54b10c 214 int s;
ea54b10c 215 void *buf;
ea54b10c 216 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 217
f95ccffc
JM		 218 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
219 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
220 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
221 for (i = 64; i < s; i += 64) {
222 wqe = buf + i;
223 *wqe = cpu_to_be32(0xffffffff);
ea54b10c 224 }
0e6e7416
RD		 225}
226
225c7b1f
RD		 227static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
228{
229 struct ib_event event;
230 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
231
232 if (type == MLX4_EVENT_TYPE_PATH_MIG)
233 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
234
235 if (ibqp->event_handler) {
236 event.device = ibqp->device;
237 event.element.qp = ibqp;
238 switch (type) {
239 case MLX4_EVENT_TYPE_PATH_MIG:
240 event.event = IB_EVENT_PATH_MIG;
241 break;
242 case MLX4_EVENT_TYPE_COMM_EST:
243 event.event = IB_EVENT_COMM_EST;
244 break;
245 case MLX4_EVENT_TYPE_SQ_DRAINED:
246 event.event = IB_EVENT_SQ_DRAINED;
247 break;
248 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
249 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
250 break;
251 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
252 event.event = IB_EVENT_QP_FATAL;
253 break;
254 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
255 event.event = IB_EVENT_PATH_MIG_ERR;
256 break;
257 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
258 event.event = IB_EVENT_QP_REQ_ERR;
259 break;
260 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
261 event.event = IB_EVENT_QP_ACCESS_ERR;
262 break;
263 default:
987c8f8f 264 pr_warn("Unexpected event type %d "
225c7b1f
RD		 265 "on QP %06x\n", type, qp->qpn);
266 return;
267 }
268
269 ibqp->event_handler(&event, ibqp->qp_context);
270 }
271}
272
400b1ebc
GL		 273static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
274{
275 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
276 type, qp->qpn);
277}
278
1ffeb2eb 279static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 280{
281 /*
282 * UD WQEs must have a datagram segment.
283 * RC and UC WQEs might have a remote address segment.
284 * MLX WQEs need two extra inline data segments (for the UD
285 * header and space for the ICRC).
286 */
287 switch (type) {
1ffeb2eb 288 case MLX4_IB_QPT_UD:
225c7b1f 289 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 290 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 291 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 292 case MLX4_IB_QPT_PROXY_SMI_OWNER:
293 case MLX4_IB_QPT_PROXY_SMI:
294 case MLX4_IB_QPT_PROXY_GSI:
295 return sizeof (struct mlx4_wqe_ctrl_seg) +
296 sizeof (struct mlx4_wqe_datagram_seg) + 64;
297 case MLX4_IB_QPT_TUN_SMI_OWNER:
298 case MLX4_IB_QPT_TUN_GSI:
299 return sizeof (struct mlx4_wqe_ctrl_seg) +
300 sizeof (struct mlx4_wqe_datagram_seg);
301
302 case MLX4_IB_QPT_UC:
225c7b1f
RD		 303 return sizeof (struct mlx4_wqe_ctrl_seg) +
304 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 305 case MLX4_IB_QPT_RC:
225c7b1f 306 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 307 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 308 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 309 case MLX4_IB_QPT_SMI:
310 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 311 return sizeof (struct mlx4_wqe_ctrl_seg) +
312 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 313 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
314 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 315 sizeof (struct mlx4_wqe_inline_seg),
316 sizeof (struct mlx4_wqe_data_seg)) +
317 ALIGN(4 +
318 sizeof (struct mlx4_wqe_inline_seg),
319 sizeof (struct mlx4_wqe_data_seg));
320 default:
321 return sizeof (struct mlx4_wqe_ctrl_seg);
322 }
323}
324
2446304d 325static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
e00b64f7 326 bool is_user, int has_rq, struct mlx4_ib_qp *qp,
ea30b966 327 u32 inl_recv_sz)
225c7b1f 328{
2446304d 329 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 330 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
331 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 332 return -EINVAL;
333
0a1405da 334 if (!has_rq) {
ea30b966 335 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 336 return -EINVAL;
2446304d 337
0e6e7416 338 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 339 } else {
ea30b966
MG		 340 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
341 sizeof(struct mlx4_wqe_data_seg);
342 u32 wqe_size;
343
a4cd7ed8 344 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 345 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
346 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 347 return -EINVAL;
348
0e6e7416 349 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 350 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 351 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
352 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 353 }
2446304d 354
fc2d0044
SG		 355 /* leave userspace return values as they were, so as not to break ABI */
356 if (is_user) {
357 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
358 cap->max_recv_sge = qp->rq.max_gs;
359 } else {
360 cap->max_recv_wr = qp->rq.max_post =
361 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
362 cap->max_recv_sge = min(qp->rq.max_gs,
363 min(dev->dev->caps.max_sq_sg,
364 dev->dev->caps.max_rq_sg));
365 }
2446304d
EC		 366
367 return 0;
368}
369
370static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
f95ccffc 371 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 372{
ea54b10c
JM		 373 int s;
374
2446304d 375 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 376 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
377 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 378 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 379 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
380 return -EINVAL;
381
382 /*
383 * For MLX transport we need 2 extra S/G entries:
384 * one for the header and one for the checksum at the end
385 */
1ffeb2eb
JM		 386 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
387 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 388 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
389 return -EINVAL;
390
ea54b10c
JM		 391 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
392 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 393 send_wqe_overhead(type, qp->flags);
225c7b1f 394
cd155c1c
RD		 395 if (s > dev->dev->caps.max_sq_desc_sz)
396 return -EINVAL;
397
f95ccffc
JM		 398 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
399
0e6e7416 400 /*
f95ccffc
JM		 401 * We need to leave 2 KB + 1 WR of headroom in the SQ to
402 * allow HW to prefetch.
0e6e7416 403 */
350b4c8a 404 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
f95ccffc
JM		 405 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
406 qp->sq_spare_wqes);
407
408 qp->sq.max_gs =
409 (min(dev->dev->caps.max_sq_desc_sz,
410 (1 << qp->sq.wqe_shift)) -
411 send_wqe_overhead(type, qp->flags)) /
b832be1e 412 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 413
414 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
415 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 416 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
417 qp->rq.offset = 0;
0e6e7416 418 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 419 } else {
0e6e7416 420 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 421 qp->sq.offset = 0;
422 }
423
ea54b10c 424 cap->max_send_wr = qp->sq.max_post =
f95ccffc 425 qp->sq.wqe_cnt - qp->sq_spare_wqes;
cd155c1c
RD		 426 cap->max_send_sge = min(qp->sq.max_gs,
427 min(dev->dev->caps.max_sq_sg,
428 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 429 /* We don't support inline sends for kernel QPs (yet) */
430 cap->max_inline_data = 0;
225c7b1f
RD		 431
432 return 0;
433}
434
83904132
JM		 435static int set_user_sq_size(struct mlx4_ib_dev *dev,
436 struct mlx4_ib_qp *qp,
2446304d
EC		 437 struct mlx4_ib_create_qp *ucmd)
438{
83904132
JM		 439 /* Sanity check SQ size before proceeding */
440 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
441 ucmd->log_sq_stride >
442 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
443 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
444 return -EINVAL;
445
0e6e7416 446 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 447 qp->sq.wqe_shift = ucmd->log_sq_stride;
448
0e6e7416
RD		 449 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
450 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 451
452 return 0;
453}
454
1ffeb2eb
JM		 455static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
456{
457 int i;
458
459 qp->sqp_proxy_rcv =
6da2ec56
KC		 460 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
461 GFP_KERNEL);
1ffeb2eb
JM		 462 if (!qp->sqp_proxy_rcv)
463 return -ENOMEM;
464 for (i = 0; i < qp->rq.wqe_cnt; i++) {
465 qp->sqp_proxy_rcv[i].addr =
466 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
467 GFP_KERNEL);
468 if (!qp->sqp_proxy_rcv[i].addr)
469 goto err;
470 qp->sqp_proxy_rcv[i].map =
471 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
472 sizeof (struct mlx4_ib_proxy_sqp_hdr),
473 DMA_FROM_DEVICE);
cc47d369
SO		 474 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
475 kfree(qp->sqp_proxy_rcv[i].addr);
476 goto err;
477 }
1ffeb2eb
JM		 478 }
479 return 0;
480
481err:
482 while (i > 0) {
483 --i;
484 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
485 sizeof (struct mlx4_ib_proxy_sqp_hdr),
486 DMA_FROM_DEVICE);
487 kfree(qp->sqp_proxy_rcv[i].addr);
488 }
489 kfree(qp->sqp_proxy_rcv);
490 qp->sqp_proxy_rcv = NULL;
491 return -ENOMEM;
492}
493
494static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
495{
496 int i;
497
498 for (i = 0; i < qp->rq.wqe_cnt; i++) {
499 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
500 sizeof (struct mlx4_ib_proxy_sqp_hdr),
501 DMA_FROM_DEVICE);
502 kfree(qp->sqp_proxy_rcv[i].addr);
503 }
504 kfree(qp->sqp_proxy_rcv);
505}
506
0a1405da
SH		 507static int qp_has_rq(struct ib_qp_init_attr *attr)
508{
509 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
510 return 0;
511
512 return !attr->srq;
513}
514
99ec41d0
JM		 515static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
516{
517 int i;
518 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 519 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
520 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 521 }
522 return 0;
523}
524
7b59f0f9
EBE		 525static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
526 struct mlx4_ib_qp *qp)
527{
528 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
529 mlx4_counter_free(dev->dev, qp->counter_index->index);
530 list_del(&qp->counter_index->list);
531 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
532
533 kfree(qp->counter_index);
534 qp->counter_index = NULL;
535}
536
3078f5f1
GL		 537static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
538 struct ib_qp_init_attr *init_attr,
539 struct mlx4_ib_create_qp_rss *ucmd)
540{
541 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
542 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
543
544 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
545 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
546 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
547 MLX4_EN_RSS_KEY_SIZE);
548 } else {
549 pr_debug("RX Hash function is not supported\n");
550 return (-EOPNOTSUPP);
551 }
552
4d02ebd9
GL		 553 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
554 MLX4_IB_RX_HASH_DST_IPV4 |
555 MLX4_IB_RX_HASH_SRC_IPV6 |
556 MLX4_IB_RX_HASH_DST_IPV6 |
557 MLX4_IB_RX_HASH_SRC_PORT_TCP |
558 MLX4_IB_RX_HASH_DST_PORT_TCP |
559 MLX4_IB_RX_HASH_SRC_PORT_UDP |
4f9ca2d8
LR		 560 MLX4_IB_RX_HASH_DST_PORT_UDP |
561 MLX4_IB_RX_HASH_INNER)) {
4d02ebd9
GL		 562 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
563 ucmd->rx_hash_fields_mask);
564 return (-EOPNOTSUPP);
565 }
566
3078f5f1
GL		 567 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
568 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
569 rss_ctx->flags = MLX4_RSS_IPV4;
570 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
571 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
572 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
573 return (-EOPNOTSUPP);
574 }
575
576 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
577 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
578 rss_ctx->flags |= MLX4_RSS_IPV6;
579 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
580 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
581 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
582 return (-EOPNOTSUPP);
583 }
584
585 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
586 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
587 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
588 pr_debug("RX Hash fields_mask for UDP is not supported\n");
589 return (-EOPNOTSUPP);
590 }
591
4d02ebd9 592 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 593 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 594 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 595 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 596 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 597 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
598 return (-EOPNOTSUPP);
599 }
600 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
601 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
602 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
603 return (-EOPNOTSUPP);
604 }
605
606 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
607 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 608 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 609 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 610 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 611 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 612 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 613 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
614 return (-EOPNOTSUPP);
615 }
3078f5f1
GL		 616 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
617 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
618 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
619 return (-EOPNOTSUPP);
620 }
621
07d84f7b
GL		 622 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
623 if (dev->dev->caps.tunnel_offload_mode ==
624 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
625 /*
626 * Hash according to inner headers if exist, otherwise
627 * according to outer headers.
628 */
629 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
630 } else {
631 pr_debug("RSS Hash for inner headers isn't supported\n");
632 return (-EOPNOTSUPP);
633 }
634 }
635
3078f5f1
GL		 636 return 0;
637}
638
d7c0557a 639static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 640 struct ib_qp_init_attr *init_attr,
641 struct mlx4_ib_create_qp_rss *ucmd,
642 struct mlx4_ib_qp *qp)
643{
644 int qpn;
645 int err;
646
647 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
648
649 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
650 if (err)
651 return err;
652
653 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
654 if (err)
655 goto err_qpn;
656
657 mutex_init(&qp->mutex);
658
659 INIT_LIST_HEAD(&qp->gid_list);
660 INIT_LIST_HEAD(&qp->steering_rules);
661
c3f1ee29 662 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 663 qp->state = IB_QPS_RESET;
664
665 /* Set dummy send resources to be compatible with HV and PRM */
666 qp->sq_no_prefetch = 1;
667 qp->sq.wqe_cnt = 1;
668 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
669 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
670 qp->mtt = (to_mqp(
671 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
672
673 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
674 if (!qp->rss_ctx) {
675 err = -ENOMEM;
676 goto err_qp_alloc;
677 }
678
679 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
680 if (err)
681 goto err;
682
683 return 0;
684
685err:
686 kfree(qp->rss_ctx);
687
688err_qp_alloc:
689 mlx4_qp_remove(dev->dev, &qp->mqp);
690 mlx4_qp_free(dev->dev, &qp->mqp);
691
692err_qpn:
693 mlx4_qp_release_range(dev->dev, qpn, 1);
694 return err;
695}
696
697static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
698 struct ib_qp_init_attr *init_attr,
699 struct ib_udata *udata)
700{
701 struct mlx4_ib_qp *qp;
702 struct mlx4_ib_create_qp_rss ucmd = {};
703 size_t required_cmd_sz;
704 int err;
705
706 if (!udata) {
707 pr_debug("RSS QP with NULL udata\n");
708 return ERR_PTR(-EINVAL);
709 }
710
711 if (udata->outlen)
712 return ERR_PTR(-EOPNOTSUPP);
713
714 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
715 sizeof(ucmd.reserved1);
716 if (udata->inlen < required_cmd_sz) {
717 pr_debug("invalid inlen\n");
718 return ERR_PTR(-EINVAL);
719 }
720
721 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
722 pr_debug("copy failed\n");
723 return ERR_PTR(-EFAULT);
724 }
725
f9bfea99
GL		 726 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
727 return ERR_PTR(-EOPNOTSUPP);
728
3078f5f1
GL		 729 if (ucmd.comp_mask || ucmd.reserved1)
730 return ERR_PTR(-EOPNOTSUPP);
731
732 if (udata->inlen > sizeof(ucmd) &&
733 !ib_is_udata_cleared(udata, sizeof(ucmd),
734 udata->inlen - sizeof(ucmd))) {
735 pr_debug("inlen is not supported\n");
736 return ERR_PTR(-EOPNOTSUPP);
737 }
738
739 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
740 pr_debug("RSS QP with unsupported QP type %d\n",
741 init_attr->qp_type);
742 return ERR_PTR(-EOPNOTSUPP);
743 }
744
745 if (init_attr->create_flags) {
746 pr_debug("RSS QP doesn't support create flags\n");
747 return ERR_PTR(-EOPNOTSUPP);
748 }
749
750 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
751 pr_debug("RSS QP with unsupported send attributes\n");
752 return ERR_PTR(-EOPNOTSUPP);
753 }
754
755 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
756 if (!qp)
757 return ERR_PTR(-ENOMEM);
758
759 qp->pri.vid = 0xFFFF;
760 qp->alt.vid = 0xFFFF;
761
d7c0557a 762 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
3078f5f1
GL		 763 if (err) {
764 kfree(qp);
765 return ERR_PTR(err);
766 }
767
768 qp->ibqp.qp_num = qp->mqp.qpn;
769
770 return &qp->ibqp;
771}
772
400b1ebc
GL		 773/*
774 * This function allocates a WQN from a range which is consecutive and aligned
775 * to its size. In case the range is full, then it creates a new range and
776 * allocates WQN from it. The new range will be used for following allocations.
777 */
778static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
779 struct mlx4_ib_qp *qp, int range_size, int *wqn)
780{
781 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
782 struct mlx4_wqn_range *range;
783 int err = 0;
784
785 mutex_lock(&context->wqn_ranges_mutex);
786
787 range = list_first_entry_or_null(&context->wqn_ranges_list,
788 struct mlx4_wqn_range, list);
789
790 if (!range || (range->refcount == range->size) || range->dirty) {
791 range = kzalloc(sizeof(*range), GFP_KERNEL);
792 if (!range) {
793 err = -ENOMEM;
794 goto out;
795 }
796
797 err = mlx4_qp_reserve_range(dev->dev, range_size,
798 range_size, &range->base_wqn, 0,
799 qp->mqp.usage);
800 if (err) {
801 kfree(range);
802 goto out;
803 }
804
805 range->size = range_size;
806 list_add(&range->list, &context->wqn_ranges_list);
807 } else if (range_size != 1) {
808 /*
809 * Requesting a new range (>1) when last range is still open, is
810 * not valid.
811 */
812 err = -EINVAL;
813 goto out;
814 }
815
816 qp->wqn_range = range;
817
818 *wqn = range->base_wqn + range->refcount;
819
820 range->refcount++;
821
822out:
823 mutex_unlock(&context->wqn_ranges_mutex);
824
825 return err;
826}
827
828static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
829 struct mlx4_ib_qp *qp, bool dirty_release)
830{
831 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
832 struct mlx4_wqn_range *range;
833
834 mutex_lock(&context->wqn_ranges_mutex);
835
836 range = qp->wqn_range;
837
838 range->refcount--;
839 if (!range->refcount) {
840 mlx4_qp_release_range(dev->dev, range->base_wqn,
841 range->size);
842 list_del(&range->list);
843 kfree(range);
844 } else if (dirty_release) {
845 /*
846 * A range which one of its WQNs is destroyed, won't be able to be
847 * reused for further WQN allocations.
848 * The next created WQ will allocate a new range.
849 */
850 range->dirty = 1;
851 }
852
853 mutex_unlock(&context->wqn_ranges_mutex);
854}
855
225c7b1f 856static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
400b1ebc 857 enum mlx4_ib_source_type src,
225c7b1f 858 struct ib_qp_init_attr *init_attr,
8900b894
LR		 859 struct ib_udata *udata, int sqpn,
860 struct mlx4_ib_qp **caller_qp)
225c7b1f 861{
a3cdcbfa 862 int qpn;
225c7b1f 863 int err;
b42dde47 864 struct mlx4_ib_sqp *sqp = NULL;
1ffeb2eb
JM		 865 struct mlx4_ib_qp *qp;
866 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 867 struct mlx4_ib_cq *mcq;
868 unsigned long flags;
400b1ebc 869 int range_size = 0;
1ffeb2eb
JM		 870
871 /* When tunneling special qps, we use a plain UD qp */
872 if (sqpn) {
873 if (mlx4_is_mfunc(dev->dev) &&
874 (!mlx4_is_master(dev->dev) ||
875 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
876 if (init_attr->qp_type == IB_QPT_GSI)
877 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 878 else {
879 if (mlx4_is_master(dev->dev) ||
880 qp0_enabled_vf(dev->dev, sqpn))
881 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
882 else
883 qp_type = MLX4_IB_QPT_PROXY_SMI;
884 }
1ffeb2eb
JM		 885 }
886 qpn = sqpn;
887 /* add extra sg entry for tunneling */
888 init_attr->cap.max_recv_sge++;
889 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
890 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
891 container_of(init_attr,
892 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
893 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
894 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
895 !mlx4_is_master(dev->dev))
896 return -EINVAL;
897 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
898 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 899 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
900 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
901 tnl_init->port))
1ffeb2eb
JM		 902 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
903 else
904 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 905 /* we are definitely in the PPF here, since we are creating
906 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
907 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
908 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 909 sqpn = qpn;
910 }
911
912 if (!*caller_qp) {
913 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
914 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
915 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
8900b894 916 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1ffeb2eb
JM		 917 if (!sqp)
918 return -ENOMEM;
919 qp = &sqp->qp;
2f5bb473
JM		 920 qp->pri.vid = 0xFFFF;
921 qp->alt.vid = 0xFFFF;
1ffeb2eb 922 } else {
8900b894 923 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1ffeb2eb
JM		 924 if (!qp)
925 return -ENOMEM;
2f5bb473
JM		 926 qp->pri.vid = 0xFFFF;
927 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 928 }
929 } else
930 qp = *caller_qp;
931
932 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 933
934 mutex_init(&qp->mutex);
935 spin_lock_init(&qp->sq.lock);
936 spin_lock_init(&qp->rq.lock);
fa417f7b 937 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 938 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 939
940 qp->state = IB_QPS_RESET;
ea54b10c
JM		 941 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
942 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 943
225c7b1f 944
e00b64f7 945 if (udata) {
400b1ebc
GL		 946 union {
947 struct mlx4_ib_create_qp qp;
948 struct mlx4_ib_create_wq wq;
949 } ucmd;
950 size_t copy_len;
ed8637d3
GL		 951 int shift;
952 int n;
400b1ebc
GL		 953
954 copy_len = (src == MLX4_IB_QP_SRC) ?
955 sizeof(struct mlx4_ib_create_qp) :
956 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
225c7b1f 957
400b1ebc 958 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 959 err = -EFAULT;
960 goto err;
961 }
962
400b1ebc 963 if (src == MLX4_IB_RWQ_SRC) {
078b3573
GL		 964 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
965 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
400b1ebc
GL		 966 pr_debug("user command isn't supported\n");
967 err = -EOPNOTSUPP;
968 goto err;
969 }
ea30b966 970
400b1ebc
GL		 971 if (ucmd.wq.log_range_size >
972 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
973 pr_debug("WQN range size must be equal or smaller than %d\n",
974 dev->dev->caps.max_rss_tbl_sz);
975 err = -EOPNOTSUPP;
976 goto err;
977 }
978 range_size = 1 << ucmd.wq.log_range_size;
979 } else {
980 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
981 }
0e6e7416 982
6d06c9aa
GL		 983 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
984 if (!(dev->dev->caps.flags &
985 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
986 pr_debug("scatter FCS is unsupported\n");
987 err = -EOPNOTSUPP;
988 goto err;
989 }
990
991 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
992 }
993
e00b64f7 994 err = set_rq_size(dev, &init_attr->cap, udata,
400b1ebc 995 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 996 if (err)
997 goto err;
998
400b1ebc
GL		 999 if (src == MLX4_IB_QP_SRC) {
1000 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1001
1002 err = set_user_sq_size(dev, qp,
1003 (struct mlx4_ib_create_qp *)
1004 &ucmd);
1005 if (err)
1006 goto err;
1007 } else {
1008 qp->sq_no_prefetch = 1;
1009 qp->sq.wqe_cnt = 1;
1010 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1011 /* Allocated buffer expects to have at least that SQ
1012 * size.
1013 */
1014 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1015 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1016 }
1017
b0ea0fa5
JG		 1018 qp->umem =
1019 ib_umem_get(udata,
1020 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1021 ucmd.wq.buf_addr,
1022 qp->buf_size, 0, 0);
225c7b1f
RD		 1023 if (IS_ERR(qp->umem)) {
1024 err = PTR_ERR(qp->umem);
1025 goto err;
1026 }
1027
ed8637d3
GL		 1028 n = ib_umem_page_count(qp->umem);
1029 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1030 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1031
225c7b1f
RD		 1032 if (err)
1033 goto err_buf;
1034
1035 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1036 if (err)
1037 goto err_mtt;
1038
0a1405da 1039 if (qp_has_rq(init_attr)) {
b0ea0fa5
JG		 1040 err = mlx4_ib_db_map_user(
1041 to_mucontext(pd->uobject->context), udata,
400b1ebc 1042 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
b0ea0fa5
JG		 1043 ucmd.wq.db_addr,
1044 &qp->db);
02d89b87
RD		 1045 if (err)
1046 goto err_mtt;
1047 }
f3301870 1048 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1049 } else {
e00b64f7 1050 err = set_rq_size(dev, &init_attr->cap, udata,
ea30b966
MG		 1051 qp_has_rq(init_attr), qp, 0);
1052 if (err)
1053 goto err;
1054
0e6e7416
RD		 1055 qp->sq_no_prefetch = 0;
1056
b832be1e
EC		 1057 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1058 qp->flags |= MLX4_IB_QP_LSO;
1059
c1c98501
MB		 1060 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1061 if (dev->steering_support ==
1062 MLX4_STEERING_MODE_DEVICE_MANAGED)
1063 qp->flags |= MLX4_IB_QP_NETIF;
1064 else
1065 goto err;
1066 }
1067
f95ccffc 1068 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 1069 if (err)
1070 goto err;
1071
0a1405da 1072 if (qp_has_rq(init_attr)) {
8900b894 1073 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1074 if (err)
1075 goto err;
225c7b1f 1076
02d89b87
RD		 1077 *qp->db.db = 0;
1078 }
225c7b1f 1079
f95ccffc 1080 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
8900b894 1081 &qp->buf)) {
f95ccffc
JM		 1082 err = -ENOMEM;
1083 goto err_db;
225c7b1f
RD		 1084 }
1085
1086 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1087 &qp->mtt);
1088 if (err)
1089 goto err_buf;
1090
8900b894 1091 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1092 if (err)
1093 goto err_mtt;
1094
e9105cde
LD		 1095 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1096 sizeof(u64), GFP_KERNEL);
1097 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1098 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1099 if (!qp->sq.wrid || !qp->rq.wrid) {
1100 err = -ENOMEM;
1101 goto err_wrid;
1102 }
f3301870 1103 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1104 }
1105
a3cdcbfa 1106 if (sqpn) {
1ffeb2eb
JM		 1107 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1108 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1109 if (alloc_proxy_bufs(pd->device, qp)) {
1110 err = -ENOMEM;
1111 goto err_wrid;
1112 }
1113 }
400b1ebc
GL		 1114 } else if (src == MLX4_IB_RWQ_SRC) {
1115 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1116 range_size, &qpn);
1117 if (err)
1118 goto err_wrid;
a3cdcbfa 1119 } else {
ddae0349
EE		 1120 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1121 * otherwise, the WQE BlueFlame setup flow wrongly causes
1122 * VLAN insertion. */
3987a2d3 1123 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1124 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1125 (init_attr->cap.max_send_wr ?
1126 MLX4_RESERVE_ETH_BF_QP : 0) |
1127 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1128 MLX4_RESERVE_A0_QP : 0),
1129 qp->mqp.usage);
3987a2d3 1130 else
c1c98501
MB		 1131 if (qp->flags & MLX4_IB_QP_NETIF)
1132 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1133 else
1134 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1135 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1136 if (err)
1ffeb2eb 1137 goto err_proxy;
a3cdcbfa
YP		 1138 }
1139
fbfb6625
EBE		 1140 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1141 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1142
8900b894 1143 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1144 if (err)
a3cdcbfa 1145 goto err_qpn;
225c7b1f 1146
0a1405da
SH		 1147 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1148 qp->mqp.qpn |= (1 << 23);
1149
225c7b1f
RD		 1150 /*
1151 * Hardware wants QPN written in big-endian order (after
1152 * shifting) for send doorbell. Precompute this value to save
1153 * a little bit when posting sends.
1154 */
1155 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1156
400b1ebc
GL		 1157 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1158 mlx4_ib_wq_event;
1159
1ffeb2eb
JM		 1160 if (!*caller_qp)
1161 *caller_qp = qp;
35f05dab
YH		 1162
1163 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1164 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1165 to_mcq(init_attr->recv_cq));
1166 /* Maintain device to QPs access, needed for further handling
1167 * via reset flow
1168 */
1169 list_add_tail(&qp->qps_list, &dev->qp_list);
1170 /* Maintain CQ to QPs access, needed for further handling
1171 * via reset flow
1172 */
1173 mcq = to_mcq(init_attr->send_cq);
1174 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1175 mcq = to_mcq(init_attr->recv_cq);
1176 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1177 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1178 to_mcq(init_attr->recv_cq));
1179 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1180 return 0;
1181
a3cdcbfa 1182err_qpn:
c1c98501
MB		 1183 if (!sqpn) {
1184 if (qp->flags & MLX4_IB_QP_NETIF)
1185 mlx4_ib_steer_qp_free(dev, qpn, 1);
400b1ebc
GL		 1186 else if (src == MLX4_IB_RWQ_SRC)
1187 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1188 qp, 0);
c1c98501
MB		 1189 else
1190 mlx4_qp_release_range(dev->dev, qpn, 1);
1191 }
1ffeb2eb
JM		 1192err_proxy:
1193 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1194 free_proxy_bufs(pd->device, qp);
225c7b1f 1195err_wrid:
e00b64f7 1196 if (udata) {
0a1405da
SH		 1197 if (qp_has_rq(init_attr))
1198 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 1199 } else {
0ef2f05c
WW		 1200 kvfree(qp->sq.wrid);
1201 kvfree(qp->rq.wrid);
225c7b1f
RD		 1202 }
1203
1204err_mtt:
1205 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1206
1207err_buf:
e00b64f7 1208 if (qp->umem)
225c7b1f
RD		 1209 ib_umem_release(qp->umem);
1210 else
1211 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1212
1213err_db:
e00b64f7 1214 if (!udata && qp_has_rq(init_attr))
6296883c 1215 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1216
1217err:
2dd8e44c 1218 if (!sqp && !*caller_qp)
1ffeb2eb 1219 kfree(qp);
2dd8e44c
YS		 1220 kfree(sqp);
1221
225c7b1f
RD		 1222 return err;
1223}
1224
1225static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1226{
1227 switch (state) {
1228 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1229 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1230 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1231 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1232 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1233 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1234 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1235 default: return -1;
1236 }
1237}
1238
1239static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1240 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1241{
338a8fad 1242 if (send_cq == recv_cq) {
35f05dab 1243 spin_lock(&send_cq->lock);
338a8fad
RD		 1244 __acquire(&recv_cq->lock);
1245 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1246 spin_lock(&send_cq->lock);
225c7b1f
RD		 1247 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1248 } else {
35f05dab 1249 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1250 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1251 }
1252}
1253
1254static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1255 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1256{
338a8fad
RD		 1257 if (send_cq == recv_cq) {
1258 __release(&recv_cq->lock);
35f05dab 1259 spin_unlock(&send_cq->lock);
338a8fad 1260 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1261 spin_unlock(&recv_cq->lock);
35f05dab 1262 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1263 } else {
1264 spin_unlock(&send_cq->lock);
35f05dab 1265 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1266 }
1267}
1268
fa417f7b
EC		 1269static void del_gid_entries(struct mlx4_ib_qp *qp)
1270{
1271 struct mlx4_ib_gid_entry *ge, *tmp;
1272
1273 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1274 list_del(&ge->list);
1275 kfree(ge);
1276 }
1277}
1278
0a1405da
SH		 1279static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1280{
1281 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1282 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1283 else
1284 return to_mpd(qp->ibqp.pd);
1285}
1286
400b1ebc 1287static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1288 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1289{
1290 switch (qp->ibqp.qp_type) {
1291 case IB_QPT_XRC_TGT:
1292 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1293 *recv_cq = *send_cq;
1294 break;
1295 case IB_QPT_XRC_INI:
1296 *send_cq = to_mcq(qp->ibqp.send_cq);
1297 *recv_cq = *send_cq;
1298 break;
1299 default:
400b1ebc
GL		 1300 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1301 to_mcq(qp->ibwq.cq);
1302 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1303 *recv_cq;
0a1405da
SH		 1304 break;
1305 }
1306}
1307
3078f5f1
GL		 1308static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1309{
1310 if (qp->state != IB_QPS_RESET) {
1311 int i;
1312
1313 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1314 i++) {
1315 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1316 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1317
1318 mutex_lock(&wq->mutex);
1319
1320 wq->rss_usecnt--;
1321
1322 mutex_unlock(&wq->mutex);
1323 }
1324
1325 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1326 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1327 pr_warn("modify QP %06x to RESET failed.\n",
1328 qp->mqp.qpn);
1329 }
1330
1331 mlx4_qp_remove(dev->dev, &qp->mqp);
1332 mlx4_qp_free(dev->dev, &qp->mqp);
1333 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1334 del_gid_entries(qp);
1335 kfree(qp->rss_ctx);
1336}
1337
225c7b1f 1338static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
e00b64f7 1339 enum mlx4_ib_source_type src, bool is_user)
225c7b1f
RD		 1340{
1341 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1342 unsigned long flags;
225c7b1f 1343
2f5bb473 1344 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1345 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1346 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1347 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1348 qp->mqp.qpn);
25476b02 1349 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1350 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1351 qp->pri.smac = 0;
25476b02 1352 qp->pri.smac_port = 0;
2f5bb473
JM		 1353 }
1354 if (qp->alt.smac) {
1355 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1356 qp->alt.smac = 0;
1357 }
1358 if (qp->pri.vid < 0x1000) {
1359 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1360 qp->pri.vid = 0xFFFF;
1361 qp->pri.candidate_vid = 0xFFFF;
1362 qp->pri.update_vid = 0;
1363 }
1364 if (qp->alt.vid < 0x1000) {
1365 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1366 qp->alt.vid = 0xFFFF;
1367 qp->alt.candidate_vid = 0xFFFF;
1368 qp->alt.update_vid = 0;
1369 }
1370 }
225c7b1f 1371
400b1ebc 1372 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1373
35f05dab 1374 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1375 mlx4_ib_lock_cqs(send_cq, recv_cq);
1376
35f05dab
YH		 1377 /* del from lists under both locks above to protect reset flow paths */
1378 list_del(&qp->qps_list);
1379 list_del(&qp->cq_send_list);
1380 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1381 if (!is_user) {
1382 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1383 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1384 if (send_cq != recv_cq)
1385 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1386 }
1387
1388 mlx4_qp_remove(dev->dev, &qp->mqp);
1389
1390 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1391 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1392
1393 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1394
c1c98501
MB		 1395 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1396 if (qp->flags & MLX4_IB_QP_NETIF)
1397 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc
GL		 1398 else if (src == MLX4_IB_RWQ_SRC)
1399 mlx4_ib_release_wqn(to_mucontext(
1400 qp->ibwq.uobject->context), qp, 1);
c1c98501
MB		 1401 else
1402 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1403 }
a3cdcbfa 1404
225c7b1f
RD		 1405 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1406
1407 if (is_user) {
400b1ebc
GL		 1408 if (qp->rq.wqe_cnt) {
1409 struct mlx4_ib_ucontext *mcontext = !src ?
1410 to_mucontext(qp->ibqp.uobject->context) :
1411 to_mucontext(qp->ibwq.uobject->context);
1412 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1413 }
225c7b1f
RD		 1414 ib_umem_release(qp->umem);
1415 } else {
0ef2f05c
WW		 1416 kvfree(qp->sq.wrid);
1417 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1418 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1419 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1420 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1421 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1422 if (qp->rq.wqe_cnt)
6296883c 1423 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1424 }
fa417f7b
EC		 1425
1426 del_gid_entries(qp);
225c7b1f
RD		 1427}
1428
47605df9
JM		 1429static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1430{
1431 /* Native or PPF */
1432 if (!mlx4_is_mfunc(dev->dev) ||
1433 (mlx4_is_master(dev->dev) &&
1434 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1435 return dev->dev->phys_caps.base_sqpn +
1436 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1437 attr->port_num - 1;
1438 }
1439 /* PF or VF -- creating proxies */
1440 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1441 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1442 else
c73c8b1e 1443 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1444}
1445
e1b866c6
MS		 1446static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1447 struct ib_qp_init_attr *init_attr,
1448 struct ib_udata *udata)
225c7b1f 1449{
1ffeb2eb 1450 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1451 int err;
fbfb6625 1452 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1453 u16 xrcdn = 0;
225c7b1f 1454
3078f5f1
GL		 1455 if (init_attr->rwq_ind_tbl)
1456 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1457
521e575b 1458 /*
1ffeb2eb
JM		 1459 * We only support LSO, vendor flag1, and multicast loopback blocking,
1460 * and only for kernel UD QPs.
521e575b 1461 */
1ffeb2eb
JM		 1462 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1463 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1464 MLX4_IB_SRIOV_TUNNEL_QP |
1465 MLX4_IB_SRIOV_SQP |
40f2287b 1466 MLX4_IB_QP_NETIF |
8900b894 1467 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
b832be1e 1468 return ERR_PTR(-EINVAL);
521e575b 1469
c1c98501
MB		 1470 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1471 if (init_attr->qp_type != IB_QPT_UD)
1472 return ERR_PTR(-EINVAL);
1473 }
1474
e1b866c6
MS		 1475 if (init_attr->create_flags) {
1476 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1477 return ERR_PTR(-EINVAL);
1478
1479 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1480 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1481 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1482 init_attr->qp_type != IB_QPT_UD) ||
1483 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1484 init_attr->qp_type > IB_QPT_GSI) ||
1485 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1486 init_attr->qp_type != IB_QPT_GSI))
1487 return ERR_PTR(-EINVAL);
1488 }
b846f25a 1489
225c7b1f 1490 switch (init_attr->qp_type) {
0a1405da
SH		 1491 case IB_QPT_XRC_TGT:
1492 pd = to_mxrcd(init_attr->xrcd)->pd;
1493 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1494 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1495 /* fall through */
1496 case IB_QPT_XRC_INI:
1497 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1498 return ERR_PTR(-ENOSYS);
1499 init_attr->recv_cq = init_attr->send_cq;
1500 /* fall through */
225c7b1f
RD		 1501 case IB_QPT_RC:
1502 case IB_QPT_UC:
3987a2d3 1503 case IB_QPT_RAW_PACKET:
8900b894 1504 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
225c7b1f
RD		 1505 if (!qp)
1506 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1507 qp->pri.vid = 0xFFFF;
1508 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1509 /* fall through */
1510 case IB_QPT_UD:
1511 {
400b1ebc
GL		 1512 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1513 init_attr, udata, 0, &qp);
5b420d9c
DB		 1514 if (err) {
1515 kfree(qp);
225c7b1f 1516 return ERR_PTR(err);
5b420d9c 1517 }
225c7b1f
RD		 1518
1519 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1520 qp->xrcdn = xrcdn;
225c7b1f
RD		 1521
1522 break;
1523 }
1524 case IB_QPT_SMI:
1525 case IB_QPT_GSI:
1526 {
e1b866c6
MS		 1527 int sqpn;
1528
225c7b1f 1529 /* Userspace is not allowed to create special QPs: */
0a1405da 1530 if (udata)
225c7b1f 1531 return ERR_PTR(-EINVAL);
e1b866c6 1532 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1533 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1534 1, 1, &sqpn, 0,
1535 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1536
1537 if (res)
1538 return ERR_PTR(res);
1539 } else {
1540 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1541 }
225c7b1f 1542
400b1ebc
GL		 1543 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1544 init_attr, udata, sqpn, &qp);
1ffeb2eb 1545 if (err)
225c7b1f 1546 return ERR_PTR(err);
225c7b1f
RD		 1547
1548 qp->port = init_attr->port_num;
e1b866c6
MS		 1549 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1550 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1551 break;
1552 }
1553 default:
1554 /* Don't support raw QPs */
1555 return ERR_PTR(-EINVAL);
1556 }
1557
1558 return &qp->ibqp;
1559}
1560
e1b866c6
MS		 1561struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1562 struct ib_qp_init_attr *init_attr,
1563 struct ib_udata *udata) {
1564 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1565 struct ib_qp *ibqp;
1566 struct mlx4_ib_dev *dev = to_mdev(device);
1567
1568 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1569
1570 if (!IS_ERR(ibqp) &&
1571 (init_attr->qp_type == IB_QPT_GSI) &&
1572 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1573 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1574 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1575
1576 if (is_eth &&
1577 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1578 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1579 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1580
1581 if (IS_ERR(sqp->roce_v2_gsi)) {
1582 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1583 sqp->roce_v2_gsi = NULL;
1584 } else {
1585 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1586 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1587 }
1588
1589 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1590 }
1591 }
1592 return ibqp;
1593}
1594
1595static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
225c7b1f
RD		 1596{
1597 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1598 struct mlx4_ib_qp *mqp = to_mqp(qp);
1599
1600 if (is_qp0(dev, mqp))
1601 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1602
c482af64
JM		 1603 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1604 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1605 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1606 dev->qp1_proxy[mqp->port - 1] = NULL;
1607 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1608 }
1609
7b59f0f9
EBE		 1610 if (mqp->counter_index)
1611 mlx4_ib_free_qp_counter(dev, mqp);
1612
3078f5f1
GL		 1613 if (qp->rwq_ind_tbl) {
1614 destroy_qp_rss(dev, mqp);
1615 } else {
e00b64f7 1616 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, qp->uobject);
3078f5f1 1617 }
225c7b1f
RD		 1618
1619 if (is_sqp(dev, mqp))
1620 kfree(to_msqp(mqp));
1621 else
1622 kfree(mqp);
1623
1624 return 0;
1625}
1626
e1b866c6
MS		 1627int mlx4_ib_destroy_qp(struct ib_qp *qp)
1628{
1629 struct mlx4_ib_qp *mqp = to_mqp(qp);
1630
1631 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1632 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1633
1634 if (sqp->roce_v2_gsi)
1635 ib_destroy_qp(sqp->roce_v2_gsi);
1636 }
1637
1638 return _mlx4_ib_destroy_qp(qp);
1639}
1640
1ffeb2eb 1641static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1642{
1643 switch (type) {
1ffeb2eb
JM		 1644 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1645 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1646 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1647 case MLX4_IB_QPT_XRC_INI:
1648 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1649 case MLX4_IB_QPT_SMI:
1650 case MLX4_IB_QPT_GSI:
1651 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1652
1653 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1654 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1655 MLX4_QP_ST_MLX : -1);
1656 case MLX4_IB_QPT_PROXY_SMI:
1657 case MLX4_IB_QPT_TUN_SMI:
1658 case MLX4_IB_QPT_PROXY_GSI:
1659 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1660 MLX4_QP_ST_UD : -1);
1661 default: return -1;
225c7b1f
RD		 1662 }
1663}
1664
65adfa91 1665static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1666 int attr_mask)
1667{
1668 u8 dest_rd_atomic;
1669 u32 access_flags;
1670 u32 hw_access_flags = 0;
1671
1672 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1673 dest_rd_atomic = attr->max_dest_rd_atomic;
1674 else
1675 dest_rd_atomic = qp->resp_depth;
1676
1677 if (attr_mask & IB_QP_ACCESS_FLAGS)
1678 access_flags = attr->qp_access_flags;
1679 else
1680 access_flags = qp->atomic_rd_en;
1681
1682 if (!dest_rd_atomic)
1683 access_flags &= IB_ACCESS_REMOTE_WRITE;
1684
1685 if (access_flags & IB_ACCESS_REMOTE_READ)
1686 hw_access_flags |= MLX4_QP_BIT_RRE;
1687 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1688 hw_access_flags |= MLX4_QP_BIT_RAE;
1689 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1690 hw_access_flags |= MLX4_QP_BIT_RWE;
1691
1692 return cpu_to_be32(hw_access_flags);
1693}
1694
65adfa91 1695static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1696 int attr_mask)
1697{
1698 if (attr_mask & IB_QP_PKEY_INDEX)
1699 sqp->pkey_index = attr->pkey_index;
1700 if (attr_mask & IB_QP_QKEY)
1701 sqp->qkey = attr->qkey;
1702 if (attr_mask & IB_QP_SQ_PSN)
1703 sqp->send_psn = attr->sq_psn;
1704}
1705
1706static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1707{
1708 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1709}
1710
90898850
DC		 1711static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1712 const struct rdma_ah_attr *ah,
297e0dad 1713 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1714 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1715{
4c3eb3ca 1716 int vidx;
297e0dad 1717 int smac_index;
2f5bb473 1718 int err;
297e0dad 1719
d8966fcd
DC		 1720 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1721 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1722 if (rdma_ah_get_static_rate(ah)) {
1723 path->static_rate = rdma_ah_get_static_rate(ah) +
1724 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1725 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1726 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1727 --path->static_rate;
1728 } else
1729 path->static_rate = 0;
225c7b1f 1730
d8966fcd
DC		 1731 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1732 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1733 int real_sgid_index =
7492052a 1734 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
5070cd22 1735
54a6d63f
DC		 1736 if (real_sgid_index < 0)
1737 return real_sgid_index;
5070cd22 1738 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1739 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1740 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1741 return -1;
1742 }
1743
1744 path->grh_mylmc |= 1 << 7;
5070cd22 1745 path->mgid_index = real_sgid_index;
d8966fcd 1746 path->hop_limit = grh->hop_limit;
225c7b1f 1747 path->tclass_flowlabel =
d8966fcd
DC		 1748 cpu_to_be32((grh->traffic_class << 20) |
1749 (grh->flow_label));
1750 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1751 }
1752
44c58487 1753 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1754 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1755 return -1;
1756
2f5bb473 1757 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1758 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1759
297e0dad 1760 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1761 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1762 if (smac_info->vid < 0x1000) {
1763 /* both valid vlan ids */
1764 if (smac_info->vid != vlan_tag) {
1765 /* different VIDs. unreg old and reg new */
1766 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1767 if (err)
1768 return err;
1769 smac_info->candidate_vid = vlan_tag;
1770 smac_info->candidate_vlan_index = vidx;
1771 smac_info->candidate_vlan_port = port;
1772 smac_info->update_vid = 1;
1773 path->vlan_index = vidx;
1774 } else {
1775 path->vlan_index = smac_info->vlan_index;
1776 }
1777 } else {
1778 /* no current vlan tag in qp */
1779 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1780 if (err)
1781 return err;
1782 smac_info->candidate_vid = vlan_tag;
1783 smac_info->candidate_vlan_index = vidx;
1784 smac_info->candidate_vlan_port = port;
1785 smac_info->update_vid = 1;
1786 path->vlan_index = vidx;
1787 }
297e0dad 1788 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1789 path->fl = 1 << 6;
1790 } else {
1791 /* have current vlan tag. unregister it at modify-qp success */
1792 if (smac_info->vid < 0x1000) {
1793 smac_info->candidate_vid = 0xFFFF;
1794 smac_info->update_vid = 1;
1795 }
4c3eb3ca 1796 }
2f5bb473
JM		 1797
1798 /* get smac_index for RoCE use.
1799 * If no smac was yet assigned, register one.
1800 * If one was already assigned, but the new mac differs,
1801 * unregister the old one and register the new one.
1802 */
25476b02
JM		 1803 if ((!smac_info->smac && !smac_info->smac_port) ||
1804 smac_info->smac != smac) {
2f5bb473
JM		 1805 /* register candidate now, unreg if needed, after success */
1806 smac_index = mlx4_register_mac(dev->dev, port, smac);
1807 if (smac_index >= 0) {
1808 smac_info->candidate_smac_index = smac_index;
1809 smac_info->candidate_smac = smac;
1810 smac_info->candidate_smac_port = port;
1811 } else {
1812 return -EINVAL;
1813 }
1814 } else {
1815 smac_index = smac_info->smac_index;
1816 }
44c58487 1817 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1818 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1819 /* put MAC table smac index for IBoE */
1820 path->grh_mylmc = (u8) (smac_index) | 0x80;
1821 } else {
4c3eb3ca 1822 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1823 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1824 }
fa417f7b 1825
225c7b1f
RD		 1826 return 0;
1827}
1828
297e0dad
MS		 1829static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1830 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1831 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1832 struct mlx4_qp_path *path, u8 port,
1833 u16 vlan_id, u8 *smac)
297e0dad
MS		 1834{
1835 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1836 mlx4_mac_to_u64(smac),
1837 vlan_id,
2f5bb473 1838 path, &mqp->pri, port);
297e0dad
MS		 1839}
1840
1841static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1842 const struct ib_qp_attr *qp,
1843 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1844 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1845 struct mlx4_qp_path *path, u8 port)
1846{
1847 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1848 0,
1849 0xffff,
2f5bb473 1850 path, &mqp->alt, port);
297e0dad
MS		 1851}
1852
fa417f7b
EC		 1853static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1854{
1855 struct mlx4_ib_gid_entry *ge, *tmp;
1856
1857 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1858 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1859 ge->added = 1;
1860 ge->port = qp->port;
1861 }
1862 }
1863}
1864
dbf727de
MB		 1865static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1866 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1867 struct mlx4_qp_context *context)
1868{
2f5bb473
JM		 1869 u64 u64_mac;
1870 int smac_index;
1871
3e0629cb 1872 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1873
1874 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1875 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1876 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1877 if (smac_index >= 0) {
1878 qp->pri.candidate_smac_index = smac_index;
1879 qp->pri.candidate_smac = u64_mac;
1880 qp->pri.candidate_smac_port = qp->port;
1881 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1882 } else {
1883 return -ENOENT;
1884 }
1885 }
1886 return 0;
1887}
1888
7b59f0f9
EBE		 1889static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1890{
1891 struct counter_index *new_counter_index;
1892 int err;
1893 u32 tmp_idx;
1894
1895 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1896 IB_LINK_LAYER_ETHERNET ||
1897 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1898 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1899 return 0;
1900
f3301870 1901 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1902 if (err)
1903 return err;
1904
1905 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1906 if (!new_counter_index) {
1907 mlx4_counter_free(dev->dev, tmp_idx);
1908 return -ENOMEM;
1909 }
1910
1911 new_counter_index->index = tmp_idx;
1912 new_counter_index->allocated = 1;
1913 qp->counter_index = new_counter_index;
1914
1915 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1916 list_add_tail(&new_counter_index->list,
1917 &dev->counters_table[qp->port - 1].counters_list);
1918 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1919
1920 return 0;
1921}
1922
3b5daf28
MS		 1923enum {
1924 MLX4_QPC_ROCE_MODE_1 = 0,
1925 MLX4_QPC_ROCE_MODE_2 = 2,
1926 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1927};
1928
1929static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1930{
1931 switch (gid_type) {
1932 case IB_GID_TYPE_ROCE:
1933 return MLX4_QPC_ROCE_MODE_1;
1934 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1935 return MLX4_QPC_ROCE_MODE_2;
1936 default:
1937 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1938 }
1939}
1940
3078f5f1
GL		 1941/*
1942 * Go over all RSS QP's childes (WQs) and apply their HW state according to
1943 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
1944 */
1945static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
1946{
fba02e6c 1947 int err = 0;
3078f5f1 1948 int i;
3078f5f1
GL		 1949
1950 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
1951 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
1952 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1953
1954 mutex_lock(&wq->mutex);
1955
1956 /* Mlx4_ib restrictions:
1957 * WQ's is associated to a port according to the RSS QP it is
1958 * associates to.
1959 * In case the WQ is associated to a different port by another
1960 * RSS QP, return a failure.
1961 */
1962 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
1963 err = -EINVAL;
1964 mutex_unlock(&wq->mutex);
1965 break;
1966 }
1967 wq->port = port_num;
1968 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
1969 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
1970 if (err) {
1971 mutex_unlock(&wq->mutex);
1972 break;
1973 }
1974 }
1975 wq->rss_usecnt++;
1976
1977 mutex_unlock(&wq->mutex);
1978 }
1979
1980 if (i && err) {
1981 int j;
1982
1983 for (j = (i - 1); j >= 0; j--) {
1984 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
1985 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1986
1987 mutex_lock(&wq->mutex);
1988
1989 if ((wq->rss_usecnt == 1) &&
1990 (ibwq->state == IB_WQS_RDY))
1991 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
1992 pr_warn("failed to reverse WQN=0x%06x\n",
1993 ibwq->wq_num);
1994 wq->rss_usecnt--;
1995
1996 mutex_unlock(&wq->mutex);
1997 }
1998 }
1999
2000 return err;
2001}
2002
2003static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2004{
2005 int i;
2006
2007 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2008 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2009 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2010
2011 mutex_lock(&wq->mutex);
2012
2013 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2014 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2015 pr_warn("failed to reverse WQN=%x\n",
2016 ibwq->wq_num);
2017 wq->rss_usecnt--;
2018
2019 mutex_unlock(&wq->mutex);
2020 }
2021}
2022
2023static void fill_qp_rss_context(struct mlx4_qp_context *context,
2024 struct mlx4_ib_qp *qp)
2025{
2026 struct mlx4_rss_context *rss_context;
2027
2028 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2029 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2030
2031 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2032 rss_context->default_qpn =
2033 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2034 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2035 rss_context->base_qpn_udp = rss_context->default_qpn;
2036 rss_context->flags = qp->rss_ctx->flags;
2037 /* Currently support just toeplitz */
2038 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2039
2040 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2041 MLX4_EN_RSS_KEY_SIZE);
2042}
2043
400b1ebc 2044static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91
MT		 2045 const struct ib_qp_attr *attr, int attr_mask,
2046 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f 2047{
400b1ebc
GL		 2048 struct ib_uobject *ibuobject;
2049 struct ib_srq *ibsrq;
47ec3866 2050 const struct ib_gid_attr *gid_attr = NULL;
3078f5f1 2051 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2052 enum ib_qp_type qp_type;
2053 struct mlx4_ib_dev *dev;
2054 struct mlx4_ib_qp *qp;
0a1405da
SH		 2055 struct mlx4_ib_pd *pd;
2056 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 2057 struct mlx4_qp_context *context;
2058 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2059 int sqd_event;
c1c98501 2060 int steer_qp = 0;
225c7b1f 2061 int err = -EINVAL;
3ba8e31d 2062 int counter_index;
225c7b1f 2063
400b1ebc
GL		 2064 if (src_type == MLX4_IB_RWQ_SRC) {
2065 struct ib_wq *ibwq;
2066
3078f5f1
GL		 2067 ibwq = (struct ib_wq *)src;
2068 ibuobject = ibwq->uobject;
2069 ibsrq = NULL;
2070 rwq_ind_tbl = NULL;
2071 qp_type = IB_QPT_RAW_PACKET;
2072 qp = to_mqp((struct ib_qp *)ibwq);
2073 dev = to_mdev(ibwq->device);
2074 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2075 } else {
2076 struct ib_qp *ibqp;
2077
3078f5f1
GL		 2078 ibqp = (struct ib_qp *)src;
2079 ibuobject = ibqp->uobject;
2080 ibsrq = ibqp->srq;
2081 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2082 qp_type = ibqp->qp_type;
2083 qp = to_mqp(ibqp);
2084 dev = to_mdev(ibqp->device);
2085 pd = get_pd(qp);
400b1ebc
GL		 2086 }
2087
3dec4878
JM		 2088 /* APM is not supported under RoCE */
2089 if (attr_mask & IB_QP_ALT_PATH &&
2090 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2091 IB_LINK_LAYER_ETHERNET)
2092 return -ENOTSUPP;
2093
225c7b1f
RD		 2094 context = kzalloc(sizeof *context, GFP_KERNEL);
2095 if (!context)
2096 return -ENOMEM;
2097
225c7b1f 2098 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2099 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2100
2101 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2102 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2103 else {
2104 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2105 switch (attr->path_mig_state) {
2106 case IB_MIG_MIGRATED:
2107 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2108 break;
2109 case IB_MIG_REARM:
2110 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2111 break;
2112 case IB_MIG_ARMED:
2113 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2114 break;
2115 }
2116 }
2117
ea30b966
MG		 2118 if (qp->inl_recv_sz)
2119 context->param3 |= cpu_to_be32(1 << 25);
2120
6d06c9aa
GL		 2121 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2122 context->param3 |= cpu_to_be32(1 << 29);
2123
400b1ebc 2124 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2125 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2126 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2127 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2128 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2129 if (qp->flags & MLX4_IB_QP_LSO)
2130 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2131 ilog2(dev->dev->caps.max_gso_sz);
2132 else
5f22a1d8 2133 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2134 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2135 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2136 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2137 attr->path_mtu);
f5b40431 2138 goto out;
225c7b1f 2139 }
d1f2cd89
EC		 2140 context->mtu_msgmax = (attr->path_mtu << 5) |
2141 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2142 }
2143
3078f5f1
GL		 2144 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2145 if (qp->rq.wqe_cnt)
2146 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2147 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2148 }
225c7b1f 2149
0e6e7416
RD		 2150 if (qp->sq.wqe_cnt)
2151 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2152 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2153
7b59f0f9
EBE		 2154 if (new_state == IB_QPS_RESET && qp->counter_index)
2155 mlx4_ib_free_qp_counter(dev, qp);
2156
0a1405da 2157 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2158 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2159 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2160 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2161 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2162 }
0e6e7416 2163
400b1ebc 2164 if (ibuobject)
85743f1e
HN		 2165 context->usr_page = cpu_to_be32(
2166 mlx4_to_hw_uar_index(dev->dev,
400b1ebc
GL		 2167 to_mucontext(ibuobject->context)
2168 ->uar.index));
225c7b1f 2169 else
85743f1e
HN		 2170 context->usr_page = cpu_to_be32(
2171 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2172
2173 if (attr_mask & IB_QP_DEST_QPN)
2174 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2175
2176 if (attr_mask & IB_QP_PORT) {
2177 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2178 !(attr_mask & IB_QP_AV)) {
2179 mlx4_set_sched(&context->pri_path, attr->port_num);
2180 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2181 }
2182 }
2183
cfcde11c 2184 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2185 err = create_qp_lb_counter(dev, qp);
2186 if (err)
2187 goto out;
2188
3ba8e31d
EBE		 2189 counter_index =
2190 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2191 if (qp->counter_index)
2192 counter_index = qp->counter_index->index;
2193
3ba8e31d
EBE		 2194 if (counter_index != -1) {
2195 context->pri_path.counter_index = counter_index;
cfcde11c 2196 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2197 if (qp->counter_index) {
2198 context->pri_path.fl |=
2199 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2200 context->pri_path.vlan_control |=
2201 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2202 }
cfcde11c 2203 } else
47d8417f
EBE		 2204 context->pri_path.counter_index =
2205 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2206
2207 if (qp->flags & MLX4_IB_QP_NETIF) {
2208 mlx4_ib_steer_qp_reg(dev, qp, 1);
2209 steer_qp = 1;
2210 }
e1b866c6 2211
400b1ebc 2212 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2213 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2214 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2215 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2216
2217 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2218 }
cfcde11c
OG		 2219 }
2220
225c7b1f 2221 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2222 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2223 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2224 context->pri_path.pkey_index = attr->pkey_index;
2225 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2226 }
2227
225c7b1f 2228 if (attr_mask & IB_QP_AV) {
400b1ebc 2229 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de 2230 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
dbf727de
MB		 2231 u16 vlan = 0xffff;
2232 u8 smac[ETH_ALEN];
d8966fcd
DC		 2233 int is_eth =
2234 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2235 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2236
d8966fcd 2237 if (is_eth) {
47ec3866
PP		 2238 gid_attr = attr->ah_attr.grh.sgid_attr;
2239 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
2240 memcpy(smac, gid_attr->ndev->dev_addr, ETH_ALEN);
dbf727de 2241 }
dbf727de 2242
2f5bb473 2243 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2244 port_num, vlan, smac))
225c7b1f 2245 goto out;
225c7b1f
RD		 2246
2247 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2248 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2249
2250 if (is_eth &&
2251 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
47ec3866 2252 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
3b5daf28
MS		 2253
2254 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2255 err = -EINVAL;
2256 goto out;
2257 }
2258 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2259 }
2260
225c7b1f
RD		 2261 }
2262
2263 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2264 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2265 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2266 }
2267
2268 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2269 if (attr->alt_port_num == 0 ||
2270 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2271 goto out;
225c7b1f 2272
5ae2a7a8
RD		 2273 if (attr->alt_pkey_index >=
2274 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2275 goto out;
5ae2a7a8 2276
2f5bb473
JM		 2277 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2278 &context->alt_path,
297e0dad 2279 attr->alt_port_num))
f5b40431 2280 goto out;
225c7b1f
RD		 2281
2282 context->alt_path.pkey_index = attr->alt_pkey_index;
2283 context->alt_path.ackto = attr->alt_timeout << 3;
2284 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2285 }
2286
3078f5f1
GL		 2287 context->pd = cpu_to_be32(pd->pdn);
2288
2289 if (!rwq_ind_tbl) {
108809a0 2290 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2291 get_cqs(qp, src_type, &send_cq, &recv_cq);
2292 } else { /* Set dummy CQs to be compatible with HV and PRM */
2293 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2294 recv_cq = send_cq;
2295 }
0a1405da
SH		 2296 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2297 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2298
95d04f07 2299 /* Set "fast registration enabled" for all kernel QPs */
400b1ebc 2300 if (!ibuobject)
95d04f07
RD		 2301 context->params1 |= cpu_to_be32(1 << 11);
2302
57f01b53
JM		 2303 if (attr_mask & IB_QP_RNR_RETRY) {
2304 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2305 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2306 }
2307
225c7b1f
RD		 2308 if (attr_mask & IB_QP_RETRY_CNT) {
2309 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2310 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2311 }
2312
2313 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2314 if (attr->max_rd_atomic)
2315 context->params1 |=
2316 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2317 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2318 }
2319
2320 if (attr_mask & IB_QP_SQ_PSN)
2321 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2322
225c7b1f
RD		 2323 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2324 if (attr->max_dest_rd_atomic)
2325 context->params2 |=
2326 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2327 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2328 }
2329
2330 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2331 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2332 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2333 }
2334
400b1ebc 2335 if (ibsrq)
225c7b1f
RD		 2336 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2337
2338 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2339 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2340 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2341 }
2342 if (attr_mask & IB_QP_RQ_PSN)
2343 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2344
1ffeb2eb 2345 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2346 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2347 if (qp->mlx4_ib_qp_type &
2348 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2349 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2350 else {
2351 if (mlx4_is_mfunc(dev->dev) &&
2352 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2353 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2354 MLX4_RESERVED_QKEY_BASE) {
2355 pr_err("Cannot use reserved QKEY"
2356 " 0x%x (range 0xffff0000..0xffffffff"
2357 " is reserved)\n", attr->qkey);
2358 err = -EINVAL;
2359 goto out;
2360 }
2361 context->qkey = cpu_to_be32(attr->qkey);
2362 }
225c7b1f
RD		 2363 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2364 }
2365
400b1ebc
GL		 2366 if (ibsrq)
2367 context->srqn = cpu_to_be32(1 << 24 |
2368 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2369
400b1ebc
GL		 2370 if (qp->rq.wqe_cnt &&
2371 cur_state == IB_QPS_RESET &&
2372 new_state == IB_QPS_INIT)
225c7b1f
RD		 2373 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2374
2375 if (cur_state == IB_QPS_INIT &&
2376 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2377 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2378 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2379 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2380 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2381 qp->mlx4_ib_qp_type &
2382 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2383 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2384 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2385 context->pri_path.fl = 0x80;
2386 } else {
2387 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2388 context->pri_path.fl = 0x80;
225c7b1f 2389 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2390 }
2f5bb473
JM		 2391 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2392 IB_LINK_LAYER_ETHERNET) {
2393 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2394 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2395 context->pri_path.feup = 1 << 7; /* don't fsm */
2396 /* handle smac_index */
2397 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2398 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2399 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2400 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2401 if (err) {
2402 err = -EINVAL;
2403 goto out;
2404 }
9433c188
MB		 2405 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2406 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2407 }
2408 }
225c7b1f
RD		 2409 }
2410
400b1ebc 2411 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2412 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2413 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2414 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2415 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2416 if (!rwq_ind_tbl)
d2fce8a9
OG		 2417 context->srqn = cpu_to_be32(7 << 28);
2418 }
2419 }
3528f696 2420
400b1ebc 2421 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2422 int is_eth = rdma_port_get_link_layer(
2423 &dev->ib_dev, qp->port) ==
2424 IB_LINK_LAYER_ETHERNET;
2425 if (is_eth) {
2426 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2427 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2428 }
2429 }
2430
225c7b1f
RD		 2431 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2432 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2433 sqd_event = 1;
2434 else
2435 sqd_event = 0;
2436
400b1ebc
GL		 2437 if (!ibuobject &&
2438 cur_state == IB_QPS_RESET &&
2439 new_state == IB_QPS_INIT)
3b5daf28 2440 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2441
c0be5fb5
EC		 2442 /*
2443 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2444 * ownership bits of the send queue are set and the SQ
2445 * headroom is stamped so that the hardware doesn't start
2446 * processing stale work requests.
c0be5fb5 2447 */
400b1ebc
GL		 2448 if (!ibuobject &&
2449 cur_state == IB_QPS_RESET &&
2450 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2451 struct mlx4_wqe_ctrl_seg *ctrl;
2452 int i;
2453
0e6e7416 2454 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2455 ctrl = get_send_wqe(qp, i);
2456 ctrl->owner_opcode = cpu_to_be32(1 << 31);
f95ccffc
JM		 2457 ctrl->qpn_vlan.fence_size =
2458 1 << (qp->sq.wqe_shift - 4);
2459 stamp_send_wqe(qp, i);
c0be5fb5
EC		 2460 }
2461 }
2462
108809a0
GL		 2463 if (rwq_ind_tbl &&
2464 cur_state == IB_QPS_RESET &&
2465 new_state == IB_QPS_INIT) {
2466 fill_qp_rss_context(context, qp);
2467 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2468 }
2469
225c7b1f
RD		 2470 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2471 to_mlx4_state(new_state), context, optpar,
2472 sqd_event, &qp->mqp);
2473 if (err)
2474 goto out;
2475
2476 qp->state = new_state;
2477
2478 if (attr_mask & IB_QP_ACCESS_FLAGS)
2479 qp->atomic_rd_en = attr->qp_access_flags;
2480 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2481 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2482 if (attr_mask & IB_QP_PORT) {
225c7b1f 2483 qp->port = attr->port_num;
fa417f7b
EC		 2484 update_mcg_macs(dev, qp);
2485 }
225c7b1f
RD		 2486 if (attr_mask & IB_QP_ALT_PATH)
2487 qp->alt_port = attr->alt_port_num;
2488
2489 if (is_sqp(dev, qp))
2490 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2491
2492 /*
2493 * If we moved QP0 to RTR, bring the IB link up; if we moved
2494 * QP0 to RESET or ERROR, bring the link back down.
2495 */
2496 if (is_qp0(dev, qp)) {
2497 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2498 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2499 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2500 qp->port);
225c7b1f
RD		 2501
2502 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2503 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2504 mlx4_CLOSE_PORT(dev->dev, qp->port);
2505 }
2506
2507 /*
2508 * If we moved a kernel QP to RESET, clean up all old CQ
2509 * entries and reinitialize the QP.
2510 */
2f5bb473 2511 if (new_state == IB_QPS_RESET) {
400b1ebc 2512 if (!ibuobject) {
2f5bb473 2513 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2514 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2515 if (send_cq != recv_cq)
2516 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2517
2518 qp->rq.head = 0;
2519 qp->rq.tail = 0;
2520 qp->sq.head = 0;
2521 qp->sq.tail = 0;
2522 qp->sq_next_wqe = 0;
2523 if (qp->rq.wqe_cnt)
2524 *qp->db.db = 0;
225c7b1f 2525
2f5bb473
JM		 2526 if (qp->flags & MLX4_IB_QP_NETIF)
2527 mlx4_ib_steer_qp_reg(dev, qp, 0);
2528 }
25476b02 2529 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2530 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2531 qp->pri.smac = 0;
25476b02 2532 qp->pri.smac_port = 0;
2f5bb473
JM		 2533 }
2534 if (qp->alt.smac) {
2535 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2536 qp->alt.smac = 0;
2537 }
2538 if (qp->pri.vid < 0x1000) {
2539 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2540 qp->pri.vid = 0xFFFF;
2541 qp->pri.candidate_vid = 0xFFFF;
2542 qp->pri.update_vid = 0;
2543 }
c1c98501 2544
2f5bb473
JM		 2545 if (qp->alt.vid < 0x1000) {
2546 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2547 qp->alt.vid = 0xFFFF;
2548 qp->alt.candidate_vid = 0xFFFF;
2549 qp->alt.update_vid = 0;
2550 }
225c7b1f 2551 }
225c7b1f 2552out:
7b59f0f9
EBE		 2553 if (err && qp->counter_index)
2554 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2555 if (err && steer_qp)
2556 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2557 kfree(context);
25476b02
JM		 2558 if (qp->pri.candidate_smac ||
2559 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2560 if (err) {
2561 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2562 } else {
25476b02 2563 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2564 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2565 qp->pri.smac = qp->pri.candidate_smac;
2566 qp->pri.smac_index = qp->pri.candidate_smac_index;
2567 qp->pri.smac_port = qp->pri.candidate_smac_port;
2568 }
2569 qp->pri.candidate_smac = 0;
2570 qp->pri.candidate_smac_index = 0;
2571 qp->pri.candidate_smac_port = 0;
2572 }
2573 if (qp->alt.candidate_smac) {
2574 if (err) {
2575 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2576 } else {
2577 if (qp->alt.smac)
2578 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2579 qp->alt.smac = qp->alt.candidate_smac;
2580 qp->alt.smac_index = qp->alt.candidate_smac_index;
2581 qp->alt.smac_port = qp->alt.candidate_smac_port;
2582 }
2583 qp->alt.candidate_smac = 0;
2584 qp->alt.candidate_smac_index = 0;
2585 qp->alt.candidate_smac_port = 0;
2586 }
2587
2588 if (qp->pri.update_vid) {
2589 if (err) {
2590 if (qp->pri.candidate_vid < 0x1000)
2591 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2592 qp->pri.candidate_vid);
2593 } else {
2594 if (qp->pri.vid < 0x1000)
2595 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2596 qp->pri.vid);
2597 qp->pri.vid = qp->pri.candidate_vid;
2598 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2599 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2600 }
2601 qp->pri.candidate_vid = 0xFFFF;
2602 qp->pri.update_vid = 0;
2603 }
2604
2605 if (qp->alt.update_vid) {
2606 if (err) {
2607 if (qp->alt.candidate_vid < 0x1000)
2608 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2609 qp->alt.candidate_vid);
2610 } else {
2611 if (qp->alt.vid < 0x1000)
2612 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2613 qp->alt.vid);
2614 qp->alt.vid = qp->alt.candidate_vid;
2615 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2616 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2617 }
2618 qp->alt.candidate_vid = 0xFFFF;
2619 qp->alt.update_vid = 0;
2620 }
2621
225c7b1f
RD		 2622 return err;
2623}
2624
3078f5f1
GL		 2625enum {
2626 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2627 IB_QP_PORT),
2628};
2629
e1b866c6
MS		 2630static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2631 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2632{
2633 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2634 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2635 enum ib_qp_state cur_state, new_state;
2636 int err = -EINVAL;
65adfa91
MT		 2637 mutex_lock(&qp->mutex);
2638
2639 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2640 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2641
dd5f03be 2642 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
d31131bb 2643 attr_mask)) {
b1d8eb5a
JM		 2644 pr_debug("qpn 0x%x: invalid attribute mask specified "
2645 "for transition %d to %d. qp_type %d,"
2646 " attr_mask 0x%x\n",
2647 ibqp->qp_num, cur_state, new_state,
2648 ibqp->qp_type, attr_mask);
65adfa91 2649 goto out;
b1d8eb5a 2650 }
65adfa91 2651
3078f5f1
GL		 2652 if (ibqp->rwq_ind_tbl) {
2653 if (!(((cur_state == IB_QPS_RESET) &&
2654 (new_state == IB_QPS_INIT)) ||
2655 ((cur_state == IB_QPS_INIT) &&
2656 (new_state == IB_QPS_RTR)))) {
2657 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2658 ibqp->qp_num, cur_state, new_state);
2659
2660 err = -EOPNOTSUPP;
2661 goto out;
2662 }
2663
2664 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2665 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2666 ibqp->qp_num, attr_mask, cur_state, new_state);
2667
2668 err = -EOPNOTSUPP;
2669 goto out;
2670 }
2671 }
2672
c6215745
MS		 2673 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2674 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2675 if ((ibqp->qp_type == IB_QPT_RC) ||
2676 (ibqp->qp_type == IB_QPT_UD) ||
2677 (ibqp->qp_type == IB_QPT_UC) ||
2678 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2679 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2680 attr->port_num = mlx4_ib_bond_next_port(dev);
2681 }
2682 } else {
2683 /* no sense in changing port_num
2684 * when ports are bonded */
2685 attr_mask &= ~IB_QP_PORT;
2686 }
2687 }
2688
65adfa91 2689 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2690 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2691 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2692 "for transition %d to %d. qp_type %d\n",
2693 ibqp->qp_num, attr->port_num, cur_state,
2694 new_state, ibqp->qp_type);
65adfa91
MT		 2695 goto out;
2696 }
2697
3987a2d3
OG		 2698 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2699 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2700 IB_LINK_LAYER_ETHERNET))
2701 goto out;
2702
5ae2a7a8
RD		 2703 if (attr_mask & IB_QP_PKEY_INDEX) {
2704 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2705 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2706 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2707 "for transition %d to %d. qp_type %d\n",
2708 ibqp->qp_num, attr->pkey_index, cur_state,
2709 new_state, ibqp->qp_type);
5ae2a7a8 2710 goto out;
b1d8eb5a 2711 }
5ae2a7a8
RD		 2712 }
2713
65adfa91
MT		 2714 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2715 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2716 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2717 "Transition %d to %d. qp_type %d\n",
2718 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2719 new_state, ibqp->qp_type);
65adfa91
MT		 2720 goto out;
2721 }
2722
2723 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2724 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2725 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2726 "Transition %d to %d. qp_type %d\n",
2727 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2728 new_state, ibqp->qp_type);
65adfa91
MT		 2729 goto out;
2730 }
2731
2732 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2733 err = 0;
2734 goto out;
2735 }
2736
3078f5f1
GL		 2737 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2738 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2739 if (err)
2740 goto out;
2741 }
2742
400b1ebc
GL		 2743 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2744 cur_state, new_state);
65adfa91 2745
3078f5f1
GL		 2746 if (ibqp->rwq_ind_tbl && err)
2747 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2748
c6215745
MS		 2749 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2750 attr->port_num = 1;
2751
65adfa91
MT		 2752out:
2753 mutex_unlock(&qp->mutex);
2754 return err;
2755}
2756
e1b866c6
MS		 2757int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2758 int attr_mask, struct ib_udata *udata)
2759{
2760 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2761 int ret;
2762
2763 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2764
2765 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2766 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2767 int err = 0;
2768
2769 if (sqp->roce_v2_gsi)
2770 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2771 if (err)
2772 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2773 err);
2774 }
2775 return ret;
2776}
2777
99ec41d0
JM		 2778static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2779{
2780 int i;
2781 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2782 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2783 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2784 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2785 return 0;
2786 }
2787 }
2788 return -EINVAL;
2789}
2790
1ffeb2eb 2791static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
f696bf6d 2792 const struct ib_ud_wr *wr,
1ffeb2eb
JM		 2793 void *wqe, unsigned *mlx_seg_len)
2794{
2795 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2796 struct ib_device *ib_dev = &mdev->ib_dev;
2797 struct mlx4_wqe_mlx_seg *mlx = wqe;
2798 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2799 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2800 u16 pkey;
2801 u32 qkey;
2802 int send_size;
2803 int header_size;
2804 int spc;
2805 int i;
2806
e622f2f4 2807 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2808 return -EINVAL;
2809
2810 send_size = 0;
2811
e622f2f4
CH		 2812 for (i = 0; i < wr->wr.num_sge; ++i)
2813 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2814
2815 /* for proxy-qp0 sends, need to add in size of tunnel header */
2816 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2817 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2818 send_size += sizeof (struct mlx4_ib_tunnel_header);
2819
25f40220 2820 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2821
2822 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2823 sqp->ud_header.lrh.service_level =
2824 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2825 sqp->ud_header.lrh.destination_lid =
2826 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2827 sqp->ud_header.lrh.source_lid =
2828 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2829 }
2830
2831 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2832
2833 /* force loopback */
2834 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2835 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2836
2837 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2838 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2839 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2840 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2841 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2842 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2843 else
2844 sqp->ud_header.bth.destination_qpn =
c73c8b1e 2845 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
1ffeb2eb
JM		 2846
2847 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2848 if (mlx4_is_master(mdev->dev)) {
2849 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2850 return -EINVAL;
2851 } else {
2852 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2853 return -EINVAL;
2854 }
1ffeb2eb
JM		 2855 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2856 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2857
2858 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2859 sqp->ud_header.immediate_present = 0;
2860
2861 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2862
2863 /*
2864 * Inline data segments may not cross a 64 byte boundary. If
2865 * our UD header is bigger than the space available up to the
2866 * next 64 byte boundary in the WQE, use two inline data
2867 * segments to hold the UD header.
2868 */
2869 spc = MLX4_INLINE_ALIGN -
2870 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2871 if (header_size <= spc) {
2872 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2873 memcpy(inl + 1, sqp->header_buf, header_size);
2874 i = 1;
2875 } else {
2876 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2877 memcpy(inl + 1, sqp->header_buf, spc);
2878
2879 inl = (void *) (inl + 1) + spc;
2880 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2881 /*
2882 * Need a barrier here to make sure all the data is
2883 * visible before the byte_count field is set.
2884 * Otherwise the HCA prefetcher could grab the 64-byte
2885 * chunk with this inline segment and get a valid (!=
2886 * 0xffffffff) byte count but stale data, and end up
2887 * generating a packet with bad headers.
2888 *
2889 * The first inline segment's byte_count field doesn't
2890 * need a barrier, because it comes after a
2891 * control/MLX segment and therefore is at an offset
2892 * of 16 mod 64.
2893 */
2894 wmb();
2895 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2896 i = 2;
2897 }
2898
2899 *mlx_seg_len =
2900 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2901 return 0;
2902}
2903
fd10ed8e
JM		 2904static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2905{
2906 union sl2vl_tbl_to_u64 tmp_vltab;
2907 u8 vl;
2908
2909 if (sl > 15)
2910 return 0xf;
2911 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2912 vl = tmp_vltab.sl8[sl >> 1];
2913 if (sl & 1)
2914 vl &= 0x0f;
2915 else
2916 vl >>= 4;
2917 return vl;
2918}
2919
a748d60d
TB		 2920static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2921 int index, union ib_gid *gid,
2922 enum ib_gid_type *gid_type)
2923{
2924 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2925 struct mlx4_port_gid_table *port_gid_table;
2926 unsigned long flags;
2927
2928 port_gid_table = &iboe->gids[port_num - 1];
2929 spin_lock_irqsave(&iboe->lock, flags);
2930 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2931 *gid_type = port_gid_table->gids[index].gid_type;
2932 spin_unlock_irqrestore(&iboe->lock, flags);
25e62655 2933 if (rdma_is_zero_gid(gid))
a748d60d
TB		 2934 return -ENOENT;
2935
2936 return 0;
2937}
2938
3ef967a4 2939#define MLX4_ROCEV2_QP1_SPORT 0xC000
f696bf6d 2940static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr,
f438000f 2941 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2942{
a478868a 2943 struct ib_device *ib_dev = sqp->qp.ibqp.device;
a748d60d 2944 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 2945 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2946 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2947 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2948 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2949 union ib_gid sgid;
225c7b1f
RD		 2950 u16 pkey;
2951 int send_size;
2952 int header_size;
e61ef241 2953 int spc;
225c7b1f 2954 int i;
1ffeb2eb 2955 int err = 0;
57d88cff 2956 u16 vlan = 0xffff;
a29bec12
RD		 2957 bool is_eth;
2958 bool is_vlan = false;
2959 bool is_grh;
3ef967a4
MS		 2960 bool is_udp = false;
2961 int ip_version = 0;
225c7b1f
RD		 2962
2963 send_size = 0;
e622f2f4
CH		 2964 for (i = 0; i < wr->wr.num_sge; ++i)
2965 send_size += wr->wr.sg_list[i].length;
225c7b1f 2966
fa417f7b
EC		 2967 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2968 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2969 if (is_eth) {
a748d60d 2970 enum ib_gid_type gid_type;
1ffeb2eb
JM		 2971 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2972 /* When multi-function is enabled, the ib_core gid
2973 * indexes don't necessarily match the hw ones, so
2974 * we must use our own cache */
6ee51a4e
JM		 2975 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2976 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2977 ah->av.ib.gid_index, &sgid.raw[0]);
2978 if (err)
2979 return err;
1ffeb2eb 2980 } else {
a748d60d
TB		 2981 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
2982 ah->av.ib.gid_index,
2983 &sgid, &gid_type);
3ef967a4 2984 if (!err) {
a748d60d 2985 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 2986 if (is_udp) {
2987 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2988 ip_version = 4;
2989 else
2990 ip_version = 6;
2991 is_grh = false;
2992 }
2993 } else {
1ffeb2eb 2994 return err;
3ef967a4 2995 }
1ffeb2eb 2996 }
0e9855db 2997 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2998 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2999 is_vlan = 1;
3000 }
4c3eb3ca 3001 }
25f40220 3002 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3003 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3004 if (err)
3005 return err;
fa417f7b
EC		 3006
3007 if (!is_eth) {
3008 sqp->ud_header.lrh.service_level =
3009 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3010 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3011 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3012 }
225c7b1f 3013
3ef967a4 3014 if (is_grh || (ip_version == 6)) {
225c7b1f 3015 sqp->ud_header.grh.traffic_class =
fa417f7b 3016 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3017 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3018 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3019 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3020 if (is_eth) {
6ee51a4e 3021 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3022 } else {
3023 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3024 /* When multi-function is enabled, the ib_core gid
3025 * indexes don't necessarily match the hw ones, so
3026 * we must use our own cache
3027 */
3028 sqp->ud_header.grh.source_gid.global.subnet_prefix =
8ec07bf8
JM		 3029 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3030 demux[sqp->qp.port - 1].
3031 subnet_prefix)));
baa0be70
JM		 3032 sqp->ud_header.grh.source_gid.global.interface_id =
3033 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3034 guid_cache[ah->av.ib.gid_index];
3035 } else {
89af969a
PP		 3036 sqp->ud_header.grh.source_gid =
3037 ah->ibah.sgid_attr->gid;
baa0be70 3038 }
6ee51a4e 3039 }
225c7b1f 3040 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3041 ah->av.ib.dgid, 16);
225c7b1f
RD		 3042 }
3043
3ef967a4
MS		 3044 if (ip_version == 4) {
3045 sqp->ud_header.ip4.tos =
3046 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3047 sqp->ud_header.ip4.id = 0;
3048 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3049 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3050
3051 memcpy(&sqp->ud_header.ip4.saddr,
3052 sgid.raw + 12, 4);
3053 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3054 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3055 }
3056
3057 if (is_udp) {
3058 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3059 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3060 sqp->ud_header.udp.csum = 0;
3061 }
3062
225c7b1f 3063 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3064
3065 if (!is_eth) {
3066 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3067 (sqp->ud_header.lrh.destination_lid ==
3068 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3069 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3070 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3071 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3072 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3073 }
225c7b1f 3074
e622f2f4 3075 switch (wr->wr.opcode) {
225c7b1f
RD		 3076 case IB_WR_SEND:
3077 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3078 sqp->ud_header.immediate_present = 0;
3079 break;
3080 case IB_WR_SEND_WITH_IMM:
3081 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3082 sqp->ud_header.immediate_present = 1;
e622f2f4 3083 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3084 break;
3085 default:
3086 return -EINVAL;
3087 }
3088
fa417f7b 3089 if (is_eth) {
6ee51a4e 3090 struct in6_addr in6;
3ef967a4 3091 u16 ether_type;
c0c1d3d7
OD		 3092 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3093
69ae5439 3094 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3095 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3096
c0c1d3d7 3097 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3098
1049f138 3099 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3100 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3101 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3102 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3103 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3104
3e0629cb 3105
fa417f7b
EC		 3106 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3107 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3108 if (!is_vlan) {
3ef967a4 3109 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3110 } else {
3ef967a4 3111 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3112 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3113 }
fa417f7b 3114 } else {
fd10ed8e
JM		 3115 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3116 sl_to_vl(to_mdev(ib_dev),
3117 sqp->ud_header.lrh.service_level,
3118 sqp->qp.port);
3119 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3120 return -EINVAL;
fa417f7b
EC		 3121 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3122 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3123 }
e622f2f4 3124 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 3125 if (!sqp->qp.ibqp.qp_num)
3126 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3127 else
e622f2f4 3128 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 3129 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3130 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3131 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3132 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3133 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 3134 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3135
3136 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3137
3138 if (0) {
987c8f8f 3139 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3140 for (i = 0; i < header_size / 4; ++i) {
3141 if (i % 8 == 0)
987c8f8f
SP		 3142 pr_err(" [%02x] ", i * 4);
3143 pr_cont(" %08x",
3144 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3145 if ((i + 1) % 8 == 0)
987c8f8f 3146 pr_cont("\n");
225c7b1f 3147 }
987c8f8f 3148 pr_err("\n");
225c7b1f
RD		 3149 }
3150
e61ef241
RD		 3151 /*
3152 * Inline data segments may not cross a 64 byte boundary. If
3153 * our UD header is bigger than the space available up to the
3154 * next 64 byte boundary in the WQE, use two inline data
3155 * segments to hold the UD header.
3156 */
3157 spc = MLX4_INLINE_ALIGN -
3158 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3159 if (header_size <= spc) {
3160 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3161 memcpy(inl + 1, sqp->header_buf, header_size);
3162 i = 1;
3163 } else {
3164 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3165 memcpy(inl + 1, sqp->header_buf, spc);
3166
3167 inl = (void *) (inl + 1) + spc;
3168 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3169 /*
3170 * Need a barrier here to make sure all the data is
3171 * visible before the byte_count field is set.
3172 * Otherwise the HCA prefetcher could grab the 64-byte
3173 * chunk with this inline segment and get a valid (!=
3174 * 0xffffffff) byte count but stale data, and end up
3175 * generating a packet with bad headers.
3176 *
3177 * The first inline segment's byte_count field doesn't
3178 * need a barrier, because it comes after a
3179 * control/MLX segment and therefore is at an offset
3180 * of 16 mod 64.
3181 */
3182 wmb();
3183 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3184 i = 2;
3185 }
225c7b1f 3186
f438000f
RD		 3187 *mlx_seg_len =
3188 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3189 return 0;
225c7b1f
RD		 3190}
3191
3192static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3193{
3194 unsigned cur;
3195 struct mlx4_ib_cq *cq;
3196
3197 cur = wq->head - wq->tail;
0e6e7416 3198 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3199 return 0;
3200
3201 cq = to_mcq(ib_cq);
3202 spin_lock(&cq->lock);
3203 cur = wq->head - wq->tail;
3204 spin_unlock(&cq->lock);
3205
0e6e7416 3206 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3207}
3208
95d04f07
RD		 3209static __be32 convert_access(int acc)
3210{
6ff63e19
SM		 3211 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3212 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3213 (acc & IB_ACCESS_REMOTE_WRITE ?
3214 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3215 (acc & IB_ACCESS_REMOTE_READ ?
3216 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3217 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3218 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3219}
3220
1b2cd0fc 3221static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
f696bf6d 3222 const struct ib_reg_wr *wr)
1b2cd0fc
SG		 3223{
3224 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3225
3226 fseg->flags = convert_access(wr->access);
3227 fseg->mem_key = cpu_to_be32(wr->key);
3228 fseg->buf_list = cpu_to_be64(mr->page_map);
3229 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3230 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3231 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3232 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3233 fseg->reserved[0] = 0;
3234 fseg->reserved[1] = 0;
3235}
3236
95d04f07
RD		 3237static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3238{
aee38fad
SM		 3239 memset(iseg, 0, sizeof(*iseg));
3240 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3241}
3242
0fbfa6a9
RD		 3243static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3244 u64 remote_addr, u32 rkey)
3245{
3246 rseg->raddr = cpu_to_be64(remote_addr);
3247 rseg->rkey = cpu_to_be32(rkey);
3248 rseg->reserved = 0;
3249}
3250
e622f2f4 3251static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
f696bf6d 3252 const struct ib_atomic_wr *wr)
0fbfa6a9 3253{
e622f2f4
CH		 3254 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3255 aseg->swap_add = cpu_to_be64(wr->swap);
3256 aseg->compare = cpu_to_be64(wr->compare_add);
3257 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3258 aseg->swap_add = cpu_to_be64(wr->compare_add);
3259 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3260 } else {
e622f2f4 3261 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3262 aseg->compare = 0;
3263 }
3264
3265}
3266
6fa8f719 3267static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
f696bf6d 3268 const struct ib_atomic_wr *wr)
6fa8f719 3269{
e622f2f4
CH		 3270 aseg->swap_add = cpu_to_be64(wr->swap);
3271 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3272 aseg->compare = cpu_to_be64(wr->compare_add);
3273 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3274}
3275
0fbfa6a9 3276static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3277 const struct ib_ud_wr *wr)
0fbfa6a9 3278{
e622f2f4
CH		 3279 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3280 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3281 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3282 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3283 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3284}
3285
1ffeb2eb
JM		 3286static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3287 struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3288 const struct ib_ud_wr *wr,
97982f5a 3289 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3290{
e622f2f4 3291 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3292 struct mlx4_av sqp_av = {0};
3293 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3294
3295 /* force loopback */
3296 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3297 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3298 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3299 cpu_to_be32(0xf0000000);
3300
3301 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3302 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3303 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3304 else
c73c8b1e 3305 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3306 /* Use QKEY from the QP context, which is set by master */
3307 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3308}
3309
f696bf6d
BVA		 3310static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3311 unsigned *mlx_seg_len)
1ffeb2eb
JM		 3312{
3313 struct mlx4_wqe_inline_seg *inl = wqe;
3314 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3315 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3316 int spc;
3317 int i;
3318
3319 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3320 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3321 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3322 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3323 memcpy(hdr.mac, ah->av.eth.mac, 6);
3324 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3325
3326 spc = MLX4_INLINE_ALIGN -
3327 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3328 if (sizeof (hdr) <= spc) {
3329 memcpy(inl + 1, &hdr, sizeof (hdr));
3330 wmb();
3331 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3332 i = 1;
3333 } else {
3334 memcpy(inl + 1, &hdr, spc);
3335 wmb();
3336 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3337
3338 inl = (void *) (inl + 1) + spc;
3339 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3340 wmb();
3341 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3342 i = 2;
3343 }
3344
3345 *mlx_seg_len =
3346 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3347}
3348
6e694ea3
JM		 3349static void set_mlx_icrc_seg(void *dseg)
3350{
3351 u32 *t = dseg;
3352 struct mlx4_wqe_inline_seg *iseg = dseg;
3353
3354 t[1] = 0;
3355
3356 /*
3357 * Need a barrier here before writing the byte_count field to
3358 * make sure that all the data is visible before the
3359 * byte_count field is set. Otherwise, if the segment begins
3360 * a new cacheline, the HCA prefetcher could grab the 64-byte
3361 * chunk and get a valid (!= * 0xffffffff) byte count but
3362 * stale data, and end up sending the wrong data.
3363 */
3364 wmb();
3365
3366 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3367}
3368
3369static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3370{
d420d9e3
RD		 3371 dseg->lkey = cpu_to_be32(sg->lkey);
3372 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3373
3374 /*
3375 * Need a barrier here before writing the byte_count field to
3376 * make sure that all the data is visible before the
3377 * byte_count field is set. Otherwise, if the segment begins
3378 * a new cacheline, the HCA prefetcher could grab the 64-byte
3379 * chunk and get a valid (!= * 0xffffffff) byte count but
3380 * stale data, and end up sending the wrong data.
3381 */
3382 wmb();
3383
3384 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3385}
3386
2242fa4f
RD		 3387static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3388{
3389 dseg->byte_count = cpu_to_be32(sg->length);
3390 dseg->lkey = cpu_to_be32(sg->lkey);
3391 dseg->addr = cpu_to_be64(sg->addr);
3392}
3393
f696bf6d
BVA		 3394static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3395 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3396 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3397{
e622f2f4 3398 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3399
417608c2
EC		 3400 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3401 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3402
3403 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3404 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3405 return -EINVAL;
3406
e622f2f4 3407 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3408
e622f2f4 3409 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3410 *lso_seg_len = halign;
3411 return 0;
3412}
3413
f696bf6d 3414static __be32 send_ieth(const struct ib_send_wr *wr)
95d04f07
RD		 3415{
3416 switch (wr->opcode) {
3417 case IB_WR_SEND_WITH_IMM:
3418 case IB_WR_RDMA_WRITE_WITH_IMM:
3419 return wr->ex.imm_data;
3420
3421 case IB_WR_SEND_WITH_INV:
3422 return cpu_to_be32(wr->ex.invalidate_rkey);
3423
3424 default:
3425 return 0;
3426 }
3427}
3428
1ffeb2eb
JM		 3429static void add_zero_len_inline(void *wqe)
3430{
3431 struct mlx4_wqe_inline_seg *inl = wqe;
3432 memset(wqe, 0, 16);
3433 inl->byte_count = cpu_to_be32(1 << 31);
3434}
3435
d34ac5cd
BVA		 3436static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3437 const struct ib_send_wr **bad_wr, bool drain)
225c7b1f
RD		 3438{
3439 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3440 void *wqe;
3441 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3442 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3443 unsigned long flags;
3444 int nreq;
3445 int err = 0;
ea54b10c 3446 unsigned ind;
ea54b10c 3447 int uninitialized_var(size);
a3d8e159 3448 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 3449 __be32 dummy;
3450 __be32 *lso_wqe;
3451 __be32 uninitialized_var(lso_hdr_sz);
417608c2 3452 __be32 blh;
225c7b1f 3453 int i;
35f05dab 3454 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3455
e1b866c6
MS		 3456 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3457 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3458
3459 if (sqp->roce_v2_gsi) {
3460 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3461 enum ib_gid_type gid_type;
e1b866c6
MS		 3462 union ib_gid gid;
3463
a748d60d
TB		 3464 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3465 ah->av.ib.gid_index,
3466 &gid, &gid_type))
3467 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3468 to_mqp(sqp->roce_v2_gsi) : qp;
3469 else
e1b866c6
MS		 3470 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3471 ah->av.ib.gid_index);
e1b866c6
MS		 3472 }
3473 }
3474
96db0e03 3475 spin_lock_irqsave(&qp->sq.lock, flags);
1975acd9
YH		 3476 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3477 !drain) {
35f05dab
YH		 3478 err = -EIO;
3479 *bad_wr = wr;
3480 nreq = 0;
3481 goto out;
3482 }
225c7b1f 3483
ea54b10c 3484 ind = qp->sq_next_wqe;
225c7b1f
RD		 3485
3486 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3487 lso_wqe = &dummy;
417608c2 3488 blh = 0;
0fd7e1d8 3489
225c7b1f
RD		 3490 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3491 err = -ENOMEM;
3492 *bad_wr = wr;
3493 goto out;
3494 }
3495
3496 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3497 err = -EINVAL;
3498 *bad_wr = wr;
3499 goto out;
3500 }
3501
0e6e7416 3502 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3503 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3504
3505 ctrl->srcrb_flags =
3506 (wr->send_flags & IB_SEND_SIGNALED ?
3507 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3508 (wr->send_flags & IB_SEND_SOLICITED ?
3509 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3510 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3511 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3512 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3513 qp->sq_signal_bits;
3514
95d04f07 3515 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3516
3517 wqe += sizeof *ctrl;
3518 size = sizeof *ctrl / 16;
3519
1ffeb2eb
JM		 3520 switch (qp->mlx4_ib_qp_type) {
3521 case MLX4_IB_QPT_RC:
3522 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3523 switch (wr->opcode) {
3524 case IB_WR_ATOMIC_CMP_AND_SWP:
3525 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3526 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3527 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3528 atomic_wr(wr)->rkey);
225c7b1f
RD		 3529 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3530
e622f2f4 3531 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3532 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3533
225c7b1f
RD		 3534 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3535 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3536
3537 break;
3538
3539 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3540 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3541 atomic_wr(wr)->rkey);
6fa8f719
VS		 3542 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3543
e622f2f4 3544 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3545 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3546
3547 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3548 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3549
3550 break;
3551
3552 case IB_WR_RDMA_READ:
3553 case IB_WR_RDMA_WRITE:
3554 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3555 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3556 rdma_wr(wr)->rkey);
225c7b1f
RD		 3557 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3558 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3559 break;
95d04f07
RD		 3560
3561 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3562 ctrl->srcrb_flags |=
3563 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3564 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3565 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3566 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3567 break;
3568
1b2cd0fc
SG		 3569 case IB_WR_REG_MR:
3570 ctrl->srcrb_flags |=
3571 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3572 set_reg_seg(wqe, reg_wr(wr));
3573 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3574 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3575 break;
3576
225c7b1f
RD		 3577 default:
3578 /* No extra segments required for sends */
3579 break;
3580 }
3581 break;
3582
1ffeb2eb 3583 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 3584 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3585 ctrl, &seglen);
1ffeb2eb
JM		 3586 if (unlikely(err)) {
3587 *bad_wr = wr;
3588 goto out;
3589 }
3590 wqe += seglen;
3591 size += seglen / 16;
3592 break;
3593 case MLX4_IB_QPT_TUN_SMI:
3594 case MLX4_IB_QPT_TUN_GSI:
3595 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3596 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3597 /* set the forced-loopback bit in the data seg av */
3598 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3599 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3600 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3601 break;
3602 case MLX4_IB_QPT_UD:
e622f2f4 3603 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3604 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3605 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3606
3607 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3608 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3609 &lso_hdr_sz, &blh);
b832be1e
EC		 3610 if (unlikely(err)) {
3611 *bad_wr = wr;
3612 goto out;
3613 }
0fd7e1d8 3614 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3615 wqe += seglen;
3616 size += seglen / 16;
3617 }
225c7b1f
RD		 3618 break;
3619
1ffeb2eb 3620 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 3621 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3622 ctrl, &seglen);
1ffeb2eb
JM		 3623 if (unlikely(err)) {
3624 *bad_wr = wr;
3625 goto out;
3626 }
3627 wqe += seglen;
3628 size += seglen / 16;
3629 /* to start tunnel header on a cache-line boundary */
3630 add_zero_len_inline(wqe);
3631 wqe += 16;
3632 size++;
e622f2f4 3633 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3634 wqe += seglen;
3635 size += seglen / 16;
3636 break;
3637 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3638 case MLX4_IB_QPT_PROXY_GSI:
3639 /* If we are tunneling special qps, this is a UD qp.
3640 * In this case we first add a UD segment targeting
3641 * the tunnel qp, and then add a header with address
3642 * information */
e622f2f4
CH		 3643 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3644 ud_wr(wr),
97982f5a 3645 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3646 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3647 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3648 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3649 wqe += seglen;
3650 size += seglen / 16;
3651 break;
3652
3653 case MLX4_IB_QPT_SMI:
3654 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 3655 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3656 &seglen);
f438000f 3657 if (unlikely(err)) {
225c7b1f
RD		 3658 *bad_wr = wr;
3659 goto out;
3660 }
f438000f
RD		 3661 wqe += seglen;
3662 size += seglen / 16;
225c7b1f
RD		 3663 break;
3664
3665 default:
3666 break;
3667 }
3668
6e694ea3
JM		 3669 /*
3670 * Write data segments in reverse order, so as to
3671 * overwrite cacheline stamp last within each
3672 * cacheline. This avoids issues with WQE
3673 * prefetching.
3674 */
225c7b1f 3675
6e694ea3
JM		 3676 dseg = wqe;
3677 dseg += wr->num_sge - 1;
3678 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3679
3680 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3681 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3682 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3683 qp->mlx4_ib_qp_type &
3684 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3685 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3686 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3687 }
3688
6e694ea3
JM		 3689 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3690 set_data_seg(dseg, wr->sg_list + i);
3691
0fd7e1d8
RD		 3692 /*
3693 * Possibly overwrite stamping in cacheline with LSO
3694 * segment only after making sure all data segments
3695 * are written.
3696 */
3697 wmb();
3698 *lso_wqe = lso_hdr_sz;
3699
224e92e0
BB		 3700 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3701 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3702
3703 /*
3704 * Make sure descriptor is fully written before
3705 * setting ownership bit (because HW can start
3706 * executing as soon as we do).
3707 */
3708 wmb();
3709
59b0ed12 3710 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3711 *bad_wr = wr;
225c7b1f
RD		 3712 err = -EINVAL;
3713 goto out;
3714 }
3715
3716 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3717 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416
RD		 3718
3719 /*
3720 * We can improve latency by not stamping the last
3721 * send queue WQE until after ringing the doorbell, so
3722 * only stamp here if there are still more WQEs to post.
3723 */
f95ccffc
JM		 3724 if (wr->next)
3725 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3726 ind++;
225c7b1f
RD		 3727 }
3728
3729out:
3730 if (likely(nreq)) {
3731 qp->sq.head += nreq;
3732
3733 /*
3734 * Make sure that descriptors are written before
3735 * doorbell record.
3736 */
3737 wmb();
3738
97d82a48
SK		 3739 writel_relaxed(qp->doorbell_qpn,
3740 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
225c7b1f
RD		 3741
3742 /*
3743 * Make sure doorbells don't leak out of SQ spinlock
3744 * and reach the HCA out of order.
3745 */
3746 mmiowb();
0e6e7416 3747
f95ccffc 3748 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
ea54b10c 3749
ea54b10c 3750 qp->sq_next_wqe = ind;
225c7b1f
RD		 3751 }
3752
96db0e03 3753 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3754
3755 return err;
3756}
3757
d34ac5cd
BVA		 3758int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3759 const struct ib_send_wr **bad_wr)
1975acd9
YH		 3760{
3761 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3762}
3763
d34ac5cd
BVA		 3764static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3765 const struct ib_recv_wr **bad_wr, bool drain)
225c7b1f
RD		 3766{
3767 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3768 struct mlx4_wqe_data_seg *scat;
3769 unsigned long flags;
3770 int err = 0;
3771 int nreq;
3772 int ind;
1ffeb2eb 3773 int max_gs;
225c7b1f 3774 int i;
35f05dab 3775 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3776
1ffeb2eb 3777 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3778 spin_lock_irqsave(&qp->rq.lock, flags);
3779
1975acd9
YH		 3780 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3781 !drain) {
35f05dab
YH		 3782 err = -EIO;
3783 *bad_wr = wr;
3784 nreq = 0;
3785 goto out;
3786 }
3787
0e6e7416 3788 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3789
3790 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3791 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3792 err = -ENOMEM;
3793 *bad_wr = wr;
3794 goto out;
3795 }
3796
3797 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3798 err = -EINVAL;
3799 *bad_wr = wr;
3800 goto out;
3801 }
3802
3803 scat = get_recv_wqe(qp, ind);
3804
1ffeb2eb
JM		 3805 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3806 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3807 ib_dma_sync_single_for_device(ibqp->device,
3808 qp->sqp_proxy_rcv[ind].map,
3809 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3810 DMA_FROM_DEVICE);
3811 scat->byte_count =
3812 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3813 /* use dma lkey from upper layer entry */
3814 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3815 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3816 scat++;
3817 max_gs--;
3818 }
3819
2242fa4f
RD		 3820 for (i = 0; i < wr->num_sge; ++i)
3821 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3822
1ffeb2eb 3823 if (i < max_gs) {
225c7b1f
RD		 3824 scat[i].byte_count = 0;
3825 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3826 scat[i].addr = 0;
3827 }
3828
3829 qp->rq.wrid[ind] = wr->wr_id;
3830
0e6e7416 3831 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3832 }
3833
3834out:
3835 if (likely(nreq)) {
3836 qp->rq.head += nreq;
3837
3838 /*
3839 * Make sure that descriptors are written before
3840 * doorbell record.
3841 */
3842 wmb();
3843
3844 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3845 }
3846
3847 spin_unlock_irqrestore(&qp->rq.lock, flags);
3848
3849 return err;
3850}
6a775e2b 3851
d34ac5cd
BVA		 3852int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3853 const struct ib_recv_wr **bad_wr)
1975acd9
YH		 3854{
3855 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3856}
3857
6a775e2b
JM		 3858static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3859{
3860 switch (mlx4_state) {
3861 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3862 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3863 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3864 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3865 case MLX4_QP_STATE_SQ_DRAINING:
3866 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3867 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3868 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3869 default: return -1;
3870 }
3871}
3872
3873static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3874{
3875 switch (mlx4_mig_state) {
3876 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3877 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3878 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3879 default: return -1;
3880 }
3881}
3882
3883static int to_ib_qp_access_flags(int mlx4_flags)
3884{
3885 int ib_flags = 0;
3886
3887 if (mlx4_flags & MLX4_QP_BIT_RRE)
3888 ib_flags |= IB_ACCESS_REMOTE_READ;
3889 if (mlx4_flags & MLX4_QP_BIT_RWE)
3890 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3891 if (mlx4_flags & MLX4_QP_BIT_RAE)
3892 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3893
3894 return ib_flags;
3895}
3896
71d53ab4 3897static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3898 struct rdma_ah_attr *ah_attr,
71d53ab4 3899 struct mlx4_qp_path *path)
6a775e2b 3900{
4c3eb3ca 3901 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3902 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 3903
d8966fcd 3904 memset(ah_attr, 0, sizeof(*ah_attr));
d8966fcd 3905 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b 3906 return;
f1228867 3907 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
6a775e2b 3908
44c58487 3909 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 3910 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3911 ((path->sched_queue & 4) << 1));
4c3eb3ca 3912 else
d8966fcd 3913 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 3914 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 3915
d8966fcd
DC		 3916 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3917 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3918 rdma_ah_set_static_rate(ah_attr,
3919 path->static_rate ? path->static_rate - 5 : 0);
3920 if (path->grh_mylmc & (1 << 7)) {
3921 rdma_ah_set_grh(ah_attr, NULL,
3922 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3923 path->mgid_index,
3924 path->hop_limit,
3925 (be32_to_cpu(path->tclass_flowlabel)
3926 >> 20) & 0xff);
3927 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 3928 }
3929}
3930
3931int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3932 struct ib_qp_init_attr *qp_init_attr)
3933{
3934 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3935 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3936 struct mlx4_qp_context context;
3937 int mlx4_state;
0df67030
DB		 3938 int err = 0;
3939
3078f5f1
GL		 3940 if (ibqp->rwq_ind_tbl)
3941 return -EOPNOTSUPP;
3942
0df67030 3943 mutex_lock(&qp->mutex);
6a775e2b
JM		 3944
3945 if (qp->state == IB_QPS_RESET) {
3946 qp_attr->qp_state = IB_QPS_RESET;
3947 goto done;
3948 }
3949
3950 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3951 if (err) {
3952 err = -EINVAL;
3953 goto out;
3954 }
6a775e2b
JM		 3955
3956 mlx4_state = be32_to_cpu(context.flags) >> 28;
3957
0df67030
DB		 3958 qp->state = to_ib_qp_state(mlx4_state);
3959 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3960 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3961 qp_attr->path_mig_state =
3962 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3963 qp_attr->qkey = be32_to_cpu(context.qkey);
3964 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3965 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3966 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3967 qp_attr->qp_access_flags =
3968 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3969
3970 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 3971 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3972 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 3973 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 3974 qp_attr->alt_port_num =
3975 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 3976 }
3977
3978 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3979 if (qp_attr->qp_state == IB_QPS_INIT)
3980 qp_attr->port_num = qp->port;
3981 else
3982 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3983
3984 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3985 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3986
3987 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3988
3989 qp_attr->max_dest_rd_atomic =
3990 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3991 qp_attr->min_rnr_timer =
3992 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3993 qp_attr->timeout = context.pri_path.ackto >> 3;
3994 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3995 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3996 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3997
3998done:
3999 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4000 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4001 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4002
6a775e2b 4003 if (!ibqp->uobject) {
7f5eb9bb
RD		 4004 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4005 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4006 } else {
4007 qp_attr->cap.max_send_wr = 0;
4008 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4009 }
4010
7f5eb9bb
RD		 4011 /*
4012 * We don't support inline sends for kernel QPs (yet), and we
4013 * don't know what userspace's value should be.
4014 */
4015 qp_attr->cap.max_inline_data = 0;
4016
4017 qp_init_attr->cap = qp_attr->cap;
4018
521e575b
RL		 4019 qp_init_attr->create_flags = 0;
4020 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4021 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4022
4023 if (qp->flags & MLX4_IB_QP_LSO)
4024 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4025
c1c98501
MB		 4026 if (qp->flags & MLX4_IB_QP_NETIF)
4027 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4028
46db567d
DB		 4029 qp_init_attr->sq_sig_type =
4030 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4031 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4032
0df67030
DB		 4033out:
4034 mutex_unlock(&qp->mutex);
4035 return err;
6a775e2b
JM		 4036}
4037
400b1ebc
GL		 4038struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4039 struct ib_wq_init_attr *init_attr,
4040 struct ib_udata *udata)
4041{
4042 struct mlx4_ib_dev *dev;
4043 struct ib_qp_init_attr ib_qp_init_attr;
4044 struct mlx4_ib_qp *qp;
4045 struct mlx4_ib_create_wq ucmd;
4046 int err, required_cmd_sz;
4047
e00b64f7 4048 if (!udata)
400b1ebc
GL		 4049 return ERR_PTR(-EINVAL);
4050
078b3573
GL		 4051 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4052 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4053 if (udata->inlen < required_cmd_sz) {
4054 pr_debug("invalid inlen\n");
4055 return ERR_PTR(-EINVAL);
4056 }
4057
4058 if (udata->inlen > sizeof(ucmd) &&
4059 !ib_is_udata_cleared(udata, sizeof(ucmd),
4060 udata->inlen - sizeof(ucmd))) {
4061 pr_debug("inlen is not supported\n");
4062 return ERR_PTR(-EOPNOTSUPP);
4063 }
4064
4065 if (udata->outlen)
4066 return ERR_PTR(-EOPNOTSUPP);
4067
4068 dev = to_mdev(pd->device);
4069
4070 if (init_attr->wq_type != IB_WQT_RQ) {
4071 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4072 return ERR_PTR(-EOPNOTSUPP);
4073 }
4074
6d06c9aa 4075 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) {
400b1ebc
GL		 4076 pr_debug("unsupported create_flags %u\n",
4077 init_attr->create_flags);
4078 return ERR_PTR(-EOPNOTSUPP);
4079 }
4080
4081 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4082 if (!qp)
4083 return ERR_PTR(-ENOMEM);
4084
4085 qp->pri.vid = 0xFFFF;
4086 qp->alt.vid = 0xFFFF;
4087
4088 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4089 ib_qp_init_attr.qp_context = init_attr->wq_context;
4090 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4091 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4092 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4093 ib_qp_init_attr.recv_cq = init_attr->cq;
4094 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4095
6d06c9aa
GL		 4096 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4097 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4098
400b1ebc
GL		 4099 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4100 udata, 0, &qp);
4101 if (err) {
4102 kfree(qp);
4103 return ERR_PTR(err);
4104 }
4105
4106 qp->ibwq.event_handler = init_attr->event_handler;
4107 qp->ibwq.wq_num = qp->mqp.qpn;
4108 qp->ibwq.state = IB_WQS_RESET;
4109
4110 return &qp->ibwq;
4111}
4112
4113static int ib_wq2qp_state(enum ib_wq_state state)
4114{
4115 switch (state) {
4116 case IB_WQS_RESET:
4117 return IB_QPS_RESET;
4118 case IB_WQS_RDY:
4119 return IB_QPS_RTR;
4120 default:
4121 return IB_QPS_ERR;
4122 }
4123}
4124
4125static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4126{
4127 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4128 enum ib_qp_state qp_cur_state;
4129 enum ib_qp_state qp_new_state;
4130 int attr_mask;
4131 int err;
4132
4133 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4134 * the WQ logic state.
4135 */
4136 qp_cur_state = qp->state;
4137 qp_new_state = ib_wq2qp_state(new_state);
4138
4139 if (ib_wq2qp_state(new_state) == qp_cur_state)
4140 return 0;
4141
4142 if (new_state == IB_WQS_RDY) {
4143 struct ib_qp_attr attr = {};
4144
4145 attr.port_num = qp->port;
4146 attr_mask = IB_QP_PORT;
4147
4148 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4149 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4150 if (err) {
4151 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4152 ibwq->wq_num);
4153 return err;
4154 }
4155
4156 qp_cur_state = IB_QPS_INIT;
4157 }
4158
4159 attr_mask = 0;
4160 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4161 qp_cur_state, qp_new_state);
4162
4163 if (err && (qp_cur_state == IB_QPS_INIT)) {
4164 qp_new_state = IB_QPS_RESET;
4165 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4166 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4167 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4168 ibwq->wq_num);
4169 qp_new_state = IB_QPS_INIT;
4170 }
4171 }
4172
4173 qp->state = qp_new_state;
4174
4175 return err;
4176}
4177
4178int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4179 u32 wq_attr_mask, struct ib_udata *udata)
4180{
4181 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4182 struct mlx4_ib_modify_wq ucmd = {};
4183 size_t required_cmd_sz;
4184 enum ib_wq_state cur_state, new_state;
4185 int err = 0;
4186
4187 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4188 sizeof(ucmd.reserved);
4189 if (udata->inlen < required_cmd_sz)
4190 return -EINVAL;
4191
4192 if (udata->inlen > sizeof(ucmd) &&
4193 !ib_is_udata_cleared(udata, sizeof(ucmd),
4194 udata->inlen - sizeof(ucmd)))
4195 return -EOPNOTSUPP;
4196
4197 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4198 return -EFAULT;
4199
4200 if (ucmd.comp_mask || ucmd.reserved)
4201 return -EOPNOTSUPP;
4202
4203 if (wq_attr_mask & IB_WQ_FLAGS)
4204 return -EOPNOTSUPP;
4205
4206 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4207 ibwq->state;
4208 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4209
4210 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4211 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4212 return -EINVAL;
4213
4214 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4215 return -EINVAL;
4216
4217 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4218 return -EINVAL;
4219
3078f5f1
GL		 4220 /* Need to protect against the parent RSS which also may modify WQ
4221 * state.
4222 */
4223 mutex_lock(&qp->mutex);
4224
400b1ebc
GL		 4225 /* Can update HW state only if a RSS QP has already associated to this
4226 * WQ, so we can apply its port on the WQ.
4227 */
4228 if (qp->rss_usecnt)
4229 err = _mlx4_ib_modify_wq(ibwq, new_state);
4230
4231 if (!err)
4232 ibwq->state = new_state;
4233
3078f5f1
GL		 4234 mutex_unlock(&qp->mutex);
4235
400b1ebc
GL		 4236 return err;
4237}
4238
4239int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4240{
4241 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4242 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4243
4244 if (qp->counter_index)
4245 mlx4_ib_free_qp_counter(dev, qp);
4246
4247 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4248
4249 kfree(qp);
4250
4251 return 0;
4252}
b8d46ca0
GL		 4253
4254struct ib_rwq_ind_table
4255*mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4256 struct ib_rwq_ind_table_init_attr *init_attr,
4257 struct ib_udata *udata)
4258{
4259 struct ib_rwq_ind_table *rwq_ind_table;
4260 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4261 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4262 unsigned int base_wqn;
4263 size_t min_resp_len;
4264 int i;
4265 int err;
4266
4267 if (udata->inlen > 0 &&
4268 !ib_is_udata_cleared(udata, 0,
4269 udata->inlen))
4270 return ERR_PTR(-EOPNOTSUPP);
4271
4272 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4273 if (udata->outlen && udata->outlen < min_resp_len)
4274 return ERR_PTR(-EINVAL);
4275
4276 if (ind_tbl_size >
4277 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4278 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4279 ind_tbl_size,
4280 device->attrs.rss_caps.max_rwq_indirection_table_size);
4281 return ERR_PTR(-EINVAL);
4282 }
4283
4284 base_wqn = init_attr->ind_tbl[0]->wq_num;
4285
4286 if (base_wqn % ind_tbl_size) {
4287 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4288 base_wqn);
4289 return ERR_PTR(-EINVAL);
4290 }
4291
4292 for (i = 1; i < ind_tbl_size; i++) {
4293 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4294 pr_debug("indirection table's WQNs aren't consecutive\n");
4295 return ERR_PTR(-EINVAL);
4296 }
4297 }
4298
4299 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4300 if (!rwq_ind_table)
4301 return ERR_PTR(-ENOMEM);
4302
4303 if (udata->outlen) {
4304 resp.response_length = offsetof(typeof(resp), response_length) +
4305 sizeof(resp.response_length);
4306 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4307 if (err)
4308 goto err;
4309 }
4310
4311 return rwq_ind_table;
4312
4313err:
4314 kfree(rwq_ind_table);
4315 return ERR_PTR(err);
4316}
4317
4318int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4319{
4320 kfree(ib_rwq_ind_tbl);
4321 return 0;
4322}
1975acd9
YH		 4323
4324struct mlx4_ib_drain_cqe {
4325 struct ib_cqe cqe;
4326 struct completion done;
4327};
4328
4329static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4330{
4331 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4332 struct mlx4_ib_drain_cqe,
4333 cqe);
4334
4335 complete(&cqe->done);
4336}
4337
4338/* This function returns only once the drained WR was completed */
4339static void handle_drain_completion(struct ib_cq *cq,
4340 struct mlx4_ib_drain_cqe *sdrain,
4341 struct mlx4_ib_dev *dev)
4342{
4343 struct mlx4_dev *mdev = dev->dev;
4344
4345 if (cq->poll_ctx == IB_POLL_DIRECT) {
4346 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4347 ib_process_cq_direct(cq, -1);
4348 return;
4349 }
4350
4351 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4352 struct mlx4_ib_cq *mcq = to_mcq(cq);
4353 bool triggered = false;
4354 unsigned long flags;
4355
4356 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4357 /* Make sure that the CQ handler won't run if wasn't run yet */
4358 if (!mcq->mcq.reset_notify_added)
4359 mcq->mcq.reset_notify_added = 1;
4360 else
4361 triggered = true;
4362 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4363
4364 if (triggered) {
4365 /* Wait for any scheduled/running task to be ended */
4366 switch (cq->poll_ctx) {
4367 case IB_POLL_SOFTIRQ:
4368 irq_poll_disable(&cq->iop);
4369 irq_poll_enable(&cq->iop);
4370 break;
4371 case IB_POLL_WORKQUEUE:
4372 cancel_work_sync(&cq->work);
4373 break;
4374 default:
4375 WARN_ON_ONCE(1);
4376 }
4377 }
4378
4379 /* Run the CQ handler - this makes sure that the drain WR will
4380 * be processed if wasn't processed yet.
4381 */
4382 mcq->mcq.comp(&mcq->mcq);
4383 }
4384
4385 wait_for_completion(&sdrain->done);
4386}
4387
4388void mlx4_ib_drain_sq(struct ib_qp *qp)
4389{
4390 struct ib_cq *cq = qp->send_cq;
4391 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4392 struct mlx4_ib_drain_cqe sdrain;
d34ac5cd 4393 const struct ib_send_wr *bad_swr;
1975acd9
YH		 4394 struct ib_rdma_wr swr = {
4395 .wr = {
4396 .next = NULL,
4397 { .wr_cqe = &sdrain.cqe, },
4398 .opcode = IB_WR_RDMA_WRITE,
4399 },
4400 };
4401 int ret;
4402 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4403 struct mlx4_dev *mdev = dev->dev;
4404
4405 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4406 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4407 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4408 return;
4409 }
4410
4411 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4412 init_completion(&sdrain.done);
4413
4414 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4415 if (ret) {
4416 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4417 return;
4418 }
4419
4420 handle_drain_completion(cq, &sdrain, dev);
4421}
4422
4423void mlx4_ib_drain_rq(struct ib_qp *qp)
4424{
4425 struct ib_cq *cq = qp->recv_cq;
4426 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4427 struct mlx4_ib_drain_cqe rdrain;
d34ac5cd
BVA		 4428 struct ib_recv_wr rwr = {};
4429 const struct ib_recv_wr *bad_rwr;
1975acd9
YH		 4430 int ret;
4431 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4432 struct mlx4_dev *mdev = dev->dev;
4433
4434 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4435 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4436 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4437 return;
4438 }
4439
4440 rwr.wr_cqe = &rdrain.cqe;
4441 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4442 init_completion(&rdrain.done);
4443
4444 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4445 if (ret) {
4446 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4447 return;
4448 }
4449
4450 handle_drain_completion(cq, &rdrain, dev);
4451}
Linux 6.x block layer and io_uring tree(s)