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IB/mlx4: Enable RoCE v2 when the IB device is added
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
5a0e3ad6 36#include <linux/slab.h>
fa417f7b 37#include <linux/netdevice.h>
0ef2f05c 38#include <linux/vmalloc.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
225c7b1f 44
2f48485d 45#include <linux/mlx4/driver.h>
225c7b1f
RD		 46#include <linux/mlx4/qp.h>
47
48#include "mlx4_ib.h"
49#include "user.h"
50
35f05dab
YH		 51static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
55
225c7b1f
RD		 56enum {
57 MLX4_IB_ACK_REQ_FREQ = 8,
58};
59
60enum {
61 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 62 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
63 MLX4_IB_LINK_TYPE_IB = 0,
64 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 65};
66
67enum {
68 /*
fa417f7b 69 * Largest possible UD header: send with GRH and immediate
4c3eb3ca
EC		 70 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
71 * tag. (LRH would only use 8 bytes, so Ethernet is the
72 * biggest case)
225c7b1f 73 */
4c3eb3ca 74 MLX4_IB_UD_HEADER_SIZE = 82,
417608c2 75 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 76};
77
fa417f7b
EC		 78enum {
79 MLX4_IB_IBOE_ETHERTYPE = 0x8915
80};
81
225c7b1f
RD		 82struct mlx4_ib_sqp {
83 struct mlx4_ib_qp qp;
84 int pkey_index;
85 u32 qkey;
86 u32 send_psn;
87 struct ib_ud_header ud_header;
88 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
89};
90
83904132 91enum {
417608c2
EC		 92 MLX4_IB_MIN_SQ_STRIDE = 6,
93 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 94};
95
3987a2d3
OG		 96enum {
97 MLX4_RAW_QP_MTU = 7,
98 MLX4_RAW_QP_MSGMAX = 31,
99};
100
297e0dad
MS		 101#ifndef ETH_ALEN
102#define ETH_ALEN 6
103#endif
297e0dad 104
225c7b1f 105static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 106 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
107 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
108 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
109 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
110 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
111 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
112 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
113 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
114 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
115 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 116 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 117 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
118 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 119};
120
121static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
122{
123 return container_of(mqp, struct mlx4_ib_sqp, qp);
124}
125
1ffeb2eb
JM		 126static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
127{
128 if (!mlx4_is_master(dev->dev))
129 return 0;
130
47605df9
JM		 131 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
132 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
133 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 134}
135
225c7b1f
RD		 136static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
137{
47605df9
JM		 138 int proxy_sqp = 0;
139 int real_sqp = 0;
140 int i;
141 /* PPF or Native -- real SQP */
142 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
143 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
144 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
145 if (real_sqp)
146 return 1;
147 /* VF or PF -- proxy SQP */
148 if (mlx4_is_mfunc(dev->dev)) {
149 for (i = 0; i < dev->dev->caps.num_ports; i++) {
150 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
151 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
152 proxy_sqp = 1;
153 break;
154 }
155 }
156 }
157 return proxy_sqp;
225c7b1f
RD		 158}
159
1ffeb2eb 160/* used for INIT/CLOSE port logic */
225c7b1f
RD		 161static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
162{
47605df9
JM		 163 int proxy_qp0 = 0;
164 int real_qp0 = 0;
165 int i;
166 /* PPF or Native -- real QP0 */
167 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
168 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
169 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
170 if (real_qp0)
171 return 1;
172 /* VF or PF -- proxy QP0 */
173 if (mlx4_is_mfunc(dev->dev)) {
174 for (i = 0; i < dev->dev->caps.num_ports; i++) {
175 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
176 proxy_qp0 = 1;
177 break;
178 }
179 }
180 }
181 return proxy_qp0;
225c7b1f
RD		 182}
183
184static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
185{
1c69fc2a 186 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 187}
188
189static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
190{
191 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
192}
193
194static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
195{
196 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
197}
198
0e6e7416
RD		 199/*
200 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 201 * first four bytes of every 64 byte chunk with
202 * 0x7FFFFFF | (invalid_ownership_value << 31).
203 *
204 * When the max work request size is less than or equal to the WQE
205 * basic block size, as an optimization, we can stamp all WQEs with
206 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 207 */
ea54b10c 208static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 209{
d2ae16d5 210 __be32 *wqe;
0e6e7416 211 int i;
ea54b10c
JM		 212 int s;
213 int ind;
214 void *buf;
215 __be32 stamp;
9670e553 216 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 217
ea54b10c 218 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 219 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 220 for (i = 0; i < s; i += 64) {
221 ind = (i >> qp->sq.wqe_shift) + n;
222 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
223 cpu_to_be32(0xffffffff);
224 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
225 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
226 *wqe = stamp;
227 }
228 } else {
9670e553
EC		 229 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
230 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 231 for (i = 64; i < s; i += 64) {
232 wqe = buf + i;
d2ae16d5 233 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 234 }
235 }
236}
237
238static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
239{
240 struct mlx4_wqe_ctrl_seg *ctrl;
241 struct mlx4_wqe_inline_seg *inl;
242 void *wqe;
243 int s;
244
245 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
246 s = sizeof(struct mlx4_wqe_ctrl_seg);
247
248 if (qp->ibqp.qp_type == IB_QPT_UD) {
249 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
250 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
251 memset(dgram, 0, sizeof *dgram);
252 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
253 s += sizeof(struct mlx4_wqe_datagram_seg);
254 }
255
256 /* Pad the remainder of the WQE with an inline data segment. */
257 if (size > s) {
258 inl = wqe + s;
259 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
260 }
261 ctrl->srcrb_flags = 0;
262 ctrl->fence_size = size / 16;
263 /*
264 * Make sure descriptor is fully written before setting ownership bit
265 * (because HW can start executing as soon as we do).
266 */
267 wmb();
268
269 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
270 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 271
ea54b10c
JM		 272 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
273}
274
275/* Post NOP WQE to prevent wrap-around in the middle of WR */
276static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
277{
278 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
279 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
280 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
281 ind += s;
282 }
283 return ind;
0e6e7416
RD		 284}
285
225c7b1f
RD		 286static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
287{
288 struct ib_event event;
289 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
290
291 if (type == MLX4_EVENT_TYPE_PATH_MIG)
292 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
293
294 if (ibqp->event_handler) {
295 event.device = ibqp->device;
296 event.element.qp = ibqp;
297 switch (type) {
298 case MLX4_EVENT_TYPE_PATH_MIG:
299 event.event = IB_EVENT_PATH_MIG;
300 break;
301 case MLX4_EVENT_TYPE_COMM_EST:
302 event.event = IB_EVENT_COMM_EST;
303 break;
304 case MLX4_EVENT_TYPE_SQ_DRAINED:
305 event.event = IB_EVENT_SQ_DRAINED;
306 break;
307 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
308 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
309 break;
310 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
311 event.event = IB_EVENT_QP_FATAL;
312 break;
313 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
314 event.event = IB_EVENT_PATH_MIG_ERR;
315 break;
316 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
317 event.event = IB_EVENT_QP_REQ_ERR;
318 break;
319 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
320 event.event = IB_EVENT_QP_ACCESS_ERR;
321 break;
322 default:
987c8f8f 323 pr_warn("Unexpected event type %d "
225c7b1f
RD		 324 "on QP %06x\n", type, qp->qpn);
325 return;
326 }
327
328 ibqp->event_handler(&event, ibqp->qp_context);
329 }
330}
331
1ffeb2eb 332static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 333{
334 /*
335 * UD WQEs must have a datagram segment.
336 * RC and UC WQEs might have a remote address segment.
337 * MLX WQEs need two extra inline data segments (for the UD
338 * header and space for the ICRC).
339 */
340 switch (type) {
1ffeb2eb 341 case MLX4_IB_QPT_UD:
225c7b1f 342 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 343 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 344 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 345 case MLX4_IB_QPT_PROXY_SMI_OWNER:
346 case MLX4_IB_QPT_PROXY_SMI:
347 case MLX4_IB_QPT_PROXY_GSI:
348 return sizeof (struct mlx4_wqe_ctrl_seg) +
349 sizeof (struct mlx4_wqe_datagram_seg) + 64;
350 case MLX4_IB_QPT_TUN_SMI_OWNER:
351 case MLX4_IB_QPT_TUN_GSI:
352 return sizeof (struct mlx4_wqe_ctrl_seg) +
353 sizeof (struct mlx4_wqe_datagram_seg);
354
355 case MLX4_IB_QPT_UC:
225c7b1f
RD		 356 return sizeof (struct mlx4_wqe_ctrl_seg) +
357 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 358 case MLX4_IB_QPT_RC:
225c7b1f
RD		 359 return sizeof (struct mlx4_wqe_ctrl_seg) +
360 sizeof (struct mlx4_wqe_atomic_seg) +
361 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 362 case MLX4_IB_QPT_SMI:
363 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 366 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
367 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 368 sizeof (struct mlx4_wqe_inline_seg),
369 sizeof (struct mlx4_wqe_data_seg)) +
370 ALIGN(4 +
371 sizeof (struct mlx4_wqe_inline_seg),
372 sizeof (struct mlx4_wqe_data_seg));
373 default:
374 return sizeof (struct mlx4_wqe_ctrl_seg);
375 }
376}
377
2446304d 378static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
0a1405da 379 int is_user, int has_rq, struct mlx4_ib_qp *qp)
225c7b1f 380{
2446304d 381 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 382 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
383 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 384 return -EINVAL;
385
0a1405da 386 if (!has_rq) {
a4cd7ed8
RD		 387 if (cap->max_recv_wr)
388 return -EINVAL;
2446304d 389
0e6e7416 390 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 391 } else {
392 /* HW requires >= 1 RQ entry with >= 1 gather entry */
393 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
394 return -EINVAL;
395
0e6e7416 396 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 397 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 398 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
399 }
2446304d 400
fc2d0044
SG		 401 /* leave userspace return values as they were, so as not to break ABI */
402 if (is_user) {
403 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
404 cap->max_recv_sge = qp->rq.max_gs;
405 } else {
406 cap->max_recv_wr = qp->rq.max_post =
407 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
408 cap->max_recv_sge = min(qp->rq.max_gs,
409 min(dev->dev->caps.max_sq_sg,
410 dev->dev->caps.max_rq_sg));
411 }
2446304d
EC		 412
413 return 0;
414}
415
416static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
1ffeb2eb 417 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 418{
ea54b10c
JM		 419 int s;
420
2446304d 421 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 422 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
423 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 424 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 425 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
426 return -EINVAL;
427
428 /*
429 * For MLX transport we need 2 extra S/G entries:
430 * one for the header and one for the checksum at the end
431 */
1ffeb2eb
JM		 432 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
433 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 434 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
435 return -EINVAL;
436
ea54b10c
JM		 437 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
438 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 439 send_wqe_overhead(type, qp->flags);
225c7b1f 440
cd155c1c
RD		 441 if (s > dev->dev->caps.max_sq_desc_sz)
442 return -EINVAL;
443
0e6e7416 444 /*
ea54b10c
JM		 445 * Hermon supports shrinking WQEs, such that a single work
446 * request can include multiple units of 1 << wqe_shift. This
447 * way, work requests can differ in size, and do not have to
448 * be a power of 2 in size, saving memory and speeding up send
449 * WR posting. Unfortunately, if we do this then the
450 * wqe_index field in CQEs can't be used to look up the WR ID
451 * anymore, so we do this only if selective signaling is off.
452 *
453 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 454 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 455 * constant-sized WRs to make sure a WR is always fully within
456 * a single page-sized chunk.
457 *
458 * Finally, we use NOP work requests to pad the end of the
459 * work queue, to avoid wrap-around in the middle of WR. We
460 * set NEC bit to avoid getting completions with error for
461 * these NOP WRs, but since NEC is only supported starting
462 * with firmware 2.2.232, we use constant-sized WRs for older
463 * firmware.
464 *
465 * And, since MLX QPs only support SEND, we use constant-sized
466 * WRs in this case.
467 *
468 * We look for the smallest value of wqe_shift such that the
469 * resulting number of wqes does not exceed device
470 * capabilities.
471 *
472 * We set WQE size to at least 64 bytes, this way stamping
473 * invalidates each WQE.
0e6e7416 474 */
ea54b10c
JM		 475 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
476 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
1ffeb2eb
JM		 477 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
478 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
479 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
ea54b10c
JM		 480 qp->sq.wqe_shift = ilog2(64);
481 else
482 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
483
484 for (;;) {
ea54b10c
JM		 485 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
486
487 /*
488 * We need to leave 2 KB + 1 WR of headroom in the SQ to
489 * allow HW to prefetch.
490 */
491 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
492 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
493 qp->sq_max_wqes_per_wr +
494 qp->sq_spare_wqes);
495
496 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
497 break;
498
499 if (qp->sq_max_wqes_per_wr <= 1)
500 return -EINVAL;
501
502 ++qp->sq.wqe_shift;
503 }
504
cd155c1c
RD		 505 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
506 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 507 send_wqe_overhead(type, qp->flags)) /
508 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 509
510 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
511 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 512 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
513 qp->rq.offset = 0;
0e6e7416 514 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 515 } else {
0e6e7416 516 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 517 qp->sq.offset = 0;
518 }
519
ea54b10c
JM		 520 cap->max_send_wr = qp->sq.max_post =
521 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 522 cap->max_send_sge = min(qp->sq.max_gs,
523 min(dev->dev->caps.max_sq_sg,
524 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 525 /* We don't support inline sends for kernel QPs (yet) */
526 cap->max_inline_data = 0;
225c7b1f
RD		 527
528 return 0;
529}
530
83904132
JM		 531static int set_user_sq_size(struct mlx4_ib_dev *dev,
532 struct mlx4_ib_qp *qp,
2446304d
EC		 533 struct mlx4_ib_create_qp *ucmd)
534{
83904132
JM		 535 /* Sanity check SQ size before proceeding */
536 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
537 ucmd->log_sq_stride >
538 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
539 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
540 return -EINVAL;
541
0e6e7416 542 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 543 qp->sq.wqe_shift = ucmd->log_sq_stride;
544
0e6e7416
RD		 545 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
546 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 547
548 return 0;
549}
550
1ffeb2eb
JM		 551static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
552{
553 int i;
554
555 qp->sqp_proxy_rcv =
556 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
557 GFP_KERNEL);
558 if (!qp->sqp_proxy_rcv)
559 return -ENOMEM;
560 for (i = 0; i < qp->rq.wqe_cnt; i++) {
561 qp->sqp_proxy_rcv[i].addr =
562 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
563 GFP_KERNEL);
564 if (!qp->sqp_proxy_rcv[i].addr)
565 goto err;
566 qp->sqp_proxy_rcv[i].map =
567 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
568 sizeof (struct mlx4_ib_proxy_sqp_hdr),
569 DMA_FROM_DEVICE);
cc47d369
SO		 570 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
571 kfree(qp->sqp_proxy_rcv[i].addr);
572 goto err;
573 }
1ffeb2eb
JM		 574 }
575 return 0;
576
577err:
578 while (i > 0) {
579 --i;
580 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
581 sizeof (struct mlx4_ib_proxy_sqp_hdr),
582 DMA_FROM_DEVICE);
583 kfree(qp->sqp_proxy_rcv[i].addr);
584 }
585 kfree(qp->sqp_proxy_rcv);
586 qp->sqp_proxy_rcv = NULL;
587 return -ENOMEM;
588}
589
590static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
591{
592 int i;
593
594 for (i = 0; i < qp->rq.wqe_cnt; i++) {
595 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
596 sizeof (struct mlx4_ib_proxy_sqp_hdr),
597 DMA_FROM_DEVICE);
598 kfree(qp->sqp_proxy_rcv[i].addr);
599 }
600 kfree(qp->sqp_proxy_rcv);
601}
602
0a1405da
SH		 603static int qp_has_rq(struct ib_qp_init_attr *attr)
604{
605 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
606 return 0;
607
608 return !attr->srq;
609}
610
99ec41d0
JM		 611static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
612{
613 int i;
614 for (i = 0; i < dev->caps.num_ports; i++) {
615 if (qpn == dev->caps.qp0_proxy[i])
616 return !!dev->caps.qp0_qkey[i];
617 }
618 return 0;
619}
620
7b59f0f9
EBE		 621static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
622 struct mlx4_ib_qp *qp)
623{
624 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
625 mlx4_counter_free(dev->dev, qp->counter_index->index);
626 list_del(&qp->counter_index->list);
627 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
628
629 kfree(qp->counter_index);
630 qp->counter_index = NULL;
631}
632
225c7b1f
RD		 633static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
634 struct ib_qp_init_attr *init_attr,
40f2287b
JK		 635 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
636 gfp_t gfp)
225c7b1f 637{
a3cdcbfa 638 int qpn;
225c7b1f 639 int err;
1ffeb2eb
JM		 640 struct mlx4_ib_sqp *sqp;
641 struct mlx4_ib_qp *qp;
642 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 643 struct mlx4_ib_cq *mcq;
644 unsigned long flags;
1ffeb2eb
JM		 645
646 /* When tunneling special qps, we use a plain UD qp */
647 if (sqpn) {
648 if (mlx4_is_mfunc(dev->dev) &&
649 (!mlx4_is_master(dev->dev) ||
650 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
651 if (init_attr->qp_type == IB_QPT_GSI)
652 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 653 else {
654 if (mlx4_is_master(dev->dev) ||
655 qp0_enabled_vf(dev->dev, sqpn))
656 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
657 else
658 qp_type = MLX4_IB_QPT_PROXY_SMI;
659 }
1ffeb2eb
JM		 660 }
661 qpn = sqpn;
662 /* add extra sg entry for tunneling */
663 init_attr->cap.max_recv_sge++;
664 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
665 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
666 container_of(init_attr,
667 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
668 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
669 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
670 !mlx4_is_master(dev->dev))
671 return -EINVAL;
672 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
673 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 674 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
675 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
676 tnl_init->port))
1ffeb2eb
JM		 677 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
678 else
679 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 680 /* we are definitely in the PPF here, since we are creating
681 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
682 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
683 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 684 sqpn = qpn;
685 }
686
687 if (!*caller_qp) {
688 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
689 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
690 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6fcd8d0d 691 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
1ffeb2eb
JM		 692 if (!sqp)
693 return -ENOMEM;
694 qp = &sqp->qp;
2f5bb473
JM		 695 qp->pri.vid = 0xFFFF;
696 qp->alt.vid = 0xFFFF;
1ffeb2eb 697 } else {
6fcd8d0d 698 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
1ffeb2eb
JM		 699 if (!qp)
700 return -ENOMEM;
2f5bb473
JM		 701 qp->pri.vid = 0xFFFF;
702 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 703 }
704 } else
705 qp = *caller_qp;
706
707 qp->mlx4_ib_qp_type = qp_type;
225c7b1f
RD		 708
709 mutex_init(&qp->mutex);
710 spin_lock_init(&qp->sq.lock);
711 spin_lock_init(&qp->rq.lock);
fa417f7b 712 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 713 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f
RD		 714
715 qp->state = IB_QPS_RESET;
ea54b10c
JM		 716 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
717 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 718
0a1405da 719 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
225c7b1f
RD		 720 if (err)
721 goto err;
722
723 if (pd->uobject) {
724 struct mlx4_ib_create_qp ucmd;
725
726 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
727 err = -EFAULT;
728 goto err;
729 }
730
0e6e7416
RD		 731 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
732
83904132 733 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 734 if (err)
735 goto err;
736
225c7b1f 737 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 738 qp->buf_size, 0, 0);
225c7b1f
RD		 739 if (IS_ERR(qp->umem)) {
740 err = PTR_ERR(qp->umem);
741 goto err;
742 }
743
744 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
745 ilog2(qp->umem->page_size), &qp->mtt);
746 if (err)
747 goto err_buf;
748
749 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
750 if (err)
751 goto err_mtt;
752
0a1405da 753 if (qp_has_rq(init_attr)) {
02d89b87
RD		 754 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
755 ucmd.db_addr, &qp->db);
756 if (err)
757 goto err_mtt;
758 }
225c7b1f 759 } else {
0e6e7416
RD		 760 qp->sq_no_prefetch = 0;
761
b832be1e
EC		 762 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
763 qp->flags |= MLX4_IB_QP_LSO;
764
c1c98501
MB		 765 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
766 if (dev->steering_support ==
767 MLX4_STEERING_MODE_DEVICE_MANAGED)
768 qp->flags |= MLX4_IB_QP_NETIF;
769 else
770 goto err;
771 }
772
1ffeb2eb 773 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 774 if (err)
775 goto err;
776
0a1405da 777 if (qp_has_rq(init_attr)) {
40f2287b 778 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
02d89b87
RD		 779 if (err)
780 goto err;
225c7b1f 781
02d89b87
RD		 782 *qp->db.db = 0;
783 }
225c7b1f 784
40f2287b 785 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
225c7b1f
RD		 786 err = -ENOMEM;
787 goto err_db;
788 }
789
790 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
791 &qp->mtt);
792 if (err)
793 goto err_buf;
794
40f2287b 795 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
225c7b1f
RD		 796 if (err)
797 goto err_mtt;
798
ee370950 799 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
9afc60dc 800 gfp | __GFP_NOWARN);
0ef2f05c
WW		 801 if (!qp->sq.wrid)
802 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
803 gfp, PAGE_KERNEL);
ee370950 804 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
9afc60dc 805 gfp | __GFP_NOWARN);
0ef2f05c
WW		 806 if (!qp->rq.wrid)
807 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
808 gfp, PAGE_KERNEL);
225c7b1f
RD		 809 if (!qp->sq.wrid || !qp->rq.wrid) {
810 err = -ENOMEM;
811 goto err_wrid;
812 }
225c7b1f
RD		 813 }
814
a3cdcbfa 815 if (sqpn) {
1ffeb2eb
JM		 816 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
817 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
818 if (alloc_proxy_bufs(pd->device, qp)) {
819 err = -ENOMEM;
820 goto err_wrid;
821 }
822 }
a3cdcbfa 823 } else {
ddae0349
EE		 824 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
825 * otherwise, the WQE BlueFlame setup flow wrongly causes
826 * VLAN insertion. */
3987a2d3 827 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 828 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 829 (init_attr->cap.max_send_wr ?
830 MLX4_RESERVE_ETH_BF_QP : 0) |
831 (init_attr->cap.max_recv_wr ?
832 MLX4_RESERVE_A0_QP : 0));
3987a2d3 833 else
c1c98501
MB		 834 if (qp->flags & MLX4_IB_QP_NETIF)
835 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
836 else
837 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
ddae0349 838 &qpn, 0);
a3cdcbfa 839 if (err)
1ffeb2eb 840 goto err_proxy;
a3cdcbfa
YP		 841 }
842
fbfb6625
EBE		 843 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
844 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
845
40f2287b 846 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
225c7b1f 847 if (err)
a3cdcbfa 848 goto err_qpn;
225c7b1f 849
0a1405da
SH		 850 if (init_attr->qp_type == IB_QPT_XRC_TGT)
851 qp->mqp.qpn |= (1 << 23);
852
225c7b1f
RD		 853 /*
854 * Hardware wants QPN written in big-endian order (after
855 * shifting) for send doorbell. Precompute this value to save
856 * a little bit when posting sends.
857 */
858 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
859
225c7b1f 860 qp->mqp.event = mlx4_ib_qp_event;
1ffeb2eb
JM		 861 if (!*caller_qp)
862 *caller_qp = qp;
35f05dab
YH		 863
864 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
865 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
866 to_mcq(init_attr->recv_cq));
867 /* Maintain device to QPs access, needed for further handling
868 * via reset flow
869 */
870 list_add_tail(&qp->qps_list, &dev->qp_list);
871 /* Maintain CQ to QPs access, needed for further handling
872 * via reset flow
873 */
874 mcq = to_mcq(init_attr->send_cq);
875 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
876 mcq = to_mcq(init_attr->recv_cq);
877 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
878 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
879 to_mcq(init_attr->recv_cq));
880 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 881 return 0;
882
a3cdcbfa 883err_qpn:
c1c98501
MB		 884 if (!sqpn) {
885 if (qp->flags & MLX4_IB_QP_NETIF)
886 mlx4_ib_steer_qp_free(dev, qpn, 1);
887 else
888 mlx4_qp_release_range(dev->dev, qpn, 1);
889 }
1ffeb2eb
JM		 890err_proxy:
891 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
892 free_proxy_bufs(pd->device, qp);
225c7b1f 893err_wrid:
23f1b384 894 if (pd->uobject) {
0a1405da
SH		 895 if (qp_has_rq(init_attr))
896 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
23f1b384 897 } else {
0ef2f05c
WW		 898 kvfree(qp->sq.wrid);
899 kvfree(qp->rq.wrid);
225c7b1f
RD		 900 }
901
902err_mtt:
903 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
904
905err_buf:
906 if (pd->uobject)
907 ib_umem_release(qp->umem);
908 else
909 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
910
911err_db:
0a1405da 912 if (!pd->uobject && qp_has_rq(init_attr))
6296883c 913 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 914
915err:
1ffeb2eb
JM		 916 if (!*caller_qp)
917 kfree(qp);
225c7b1f
RD		 918 return err;
919}
920
921static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
922{
923 switch (state) {
924 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
925 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
926 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
927 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
928 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
929 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
930 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
931 default: return -1;
932 }
933}
934
935static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 936 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 937{
338a8fad 938 if (send_cq == recv_cq) {
35f05dab 939 spin_lock(&send_cq->lock);
338a8fad
RD		 940 __acquire(&recv_cq->lock);
941 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 942 spin_lock(&send_cq->lock);
225c7b1f
RD		 943 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
944 } else {
35f05dab 945 spin_lock(&recv_cq->lock);
225c7b1f
RD		 946 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
947 }
948}
949
950static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 951 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 952{
338a8fad
RD		 953 if (send_cq == recv_cq) {
954 __release(&recv_cq->lock);
35f05dab 955 spin_unlock(&send_cq->lock);
338a8fad 956 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 957 spin_unlock(&recv_cq->lock);
35f05dab 958 spin_unlock(&send_cq->lock);
225c7b1f
RD		 959 } else {
960 spin_unlock(&send_cq->lock);
35f05dab 961 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 962 }
963}
964
fa417f7b
EC		 965static void del_gid_entries(struct mlx4_ib_qp *qp)
966{
967 struct mlx4_ib_gid_entry *ge, *tmp;
968
969 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
970 list_del(&ge->list);
971 kfree(ge);
972 }
973}
974
0a1405da
SH		 975static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
976{
977 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
978 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
979 else
980 return to_mpd(qp->ibqp.pd);
981}
982
983static void get_cqs(struct mlx4_ib_qp *qp,
984 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
985{
986 switch (qp->ibqp.qp_type) {
987 case IB_QPT_XRC_TGT:
988 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
989 *recv_cq = *send_cq;
990 break;
991 case IB_QPT_XRC_INI:
992 *send_cq = to_mcq(qp->ibqp.send_cq);
993 *recv_cq = *send_cq;
994 break;
995 default:
996 *send_cq = to_mcq(qp->ibqp.send_cq);
997 *recv_cq = to_mcq(qp->ibqp.recv_cq);
998 break;
999 }
1000}
1001
225c7b1f
RD		 1002static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1003 int is_user)
1004{
1005 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1006 unsigned long flags;
225c7b1f 1007
2f5bb473 1008 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1009 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1010 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1011 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1012 qp->mqp.qpn);
25476b02 1013 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1014 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1015 qp->pri.smac = 0;
25476b02 1016 qp->pri.smac_port = 0;
2f5bb473
JM		 1017 }
1018 if (qp->alt.smac) {
1019 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1020 qp->alt.smac = 0;
1021 }
1022 if (qp->pri.vid < 0x1000) {
1023 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1024 qp->pri.vid = 0xFFFF;
1025 qp->pri.candidate_vid = 0xFFFF;
1026 qp->pri.update_vid = 0;
1027 }
1028 if (qp->alt.vid < 0x1000) {
1029 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1030 qp->alt.vid = 0xFFFF;
1031 qp->alt.candidate_vid = 0xFFFF;
1032 qp->alt.update_vid = 0;
1033 }
1034 }
225c7b1f 1035
0a1405da 1036 get_cqs(qp, &send_cq, &recv_cq);
225c7b1f 1037
35f05dab 1038 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1039 mlx4_ib_lock_cqs(send_cq, recv_cq);
1040
35f05dab
YH		 1041 /* del from lists under both locks above to protect reset flow paths */
1042 list_del(&qp->qps_list);
1043 list_del(&qp->cq_send_list);
1044 list_del(&qp->cq_recv_list);
225c7b1f
RD		 1045 if (!is_user) {
1046 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1047 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1048 if (send_cq != recv_cq)
1049 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1050 }
1051
1052 mlx4_qp_remove(dev->dev, &qp->mqp);
1053
1054 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1055 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1056
1057 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1058
c1c98501
MB		 1059 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1060 if (qp->flags & MLX4_IB_QP_NETIF)
1061 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1062 else
1063 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1064 }
a3cdcbfa 1065
225c7b1f
RD		 1066 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1067
1068 if (is_user) {
0a1405da 1069 if (qp->rq.wqe_cnt)
02d89b87
RD		 1070 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1071 &qp->db);
225c7b1f
RD		 1072 ib_umem_release(qp->umem);
1073 } else {
0ef2f05c
WW		 1074 kvfree(qp->sq.wrid);
1075 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1076 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1077 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1078 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1079 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1080 if (qp->rq.wqe_cnt)
6296883c 1081 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1082 }
fa417f7b
EC		 1083
1084 del_gid_entries(qp);
225c7b1f
RD		 1085}
1086
47605df9
JM		 1087static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1088{
1089 /* Native or PPF */
1090 if (!mlx4_is_mfunc(dev->dev) ||
1091 (mlx4_is_master(dev->dev) &&
1092 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1093 return dev->dev->phys_caps.base_sqpn +
1094 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1095 attr->port_num - 1;
1096 }
1097 /* PF or VF -- creating proxies */
1098 if (attr->qp_type == IB_QPT_SMI)
1099 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1100 else
1101 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1102}
1103
225c7b1f
RD		 1104struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1105 struct ib_qp_init_attr *init_attr,
1106 struct ib_udata *udata)
1107{
1ffeb2eb 1108 struct mlx4_ib_qp *qp = NULL;
225c7b1f 1109 int err;
fbfb6625 1110 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1111 u16 xrcdn = 0;
40f2287b 1112 gfp_t gfp;
225c7b1f 1113
40f2287b
JK		 1114 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1115 GFP_NOIO : GFP_KERNEL;
521e575b 1116 /*
1ffeb2eb
JM		 1117 * We only support LSO, vendor flag1, and multicast loopback blocking,
1118 * and only for kernel UD QPs.
521e575b 1119 */
1ffeb2eb
JM		 1120 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1121 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1122 MLX4_IB_SRIOV_TUNNEL_QP |
1123 MLX4_IB_SRIOV_SQP |
40f2287b
JK		 1124 MLX4_IB_QP_NETIF |
1125 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
b832be1e 1126 return ERR_PTR(-EINVAL);
521e575b 1127
c1c98501
MB		 1128 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1129 if (init_attr->qp_type != IB_QPT_UD)
1130 return ERR_PTR(-EINVAL);
1131 }
1132
521e575b 1133 if (init_attr->create_flags &&
fbfb6625
EBE		 1134 ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1135 ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1136 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1137 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1ffeb2eb
JM		 1138 init_attr->qp_type != IB_QPT_UD) ||
1139 ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1140 init_attr->qp_type > IB_QPT_GSI)))
b846f25a
EC		 1141 return ERR_PTR(-EINVAL);
1142
225c7b1f 1143 switch (init_attr->qp_type) {
0a1405da
SH		 1144 case IB_QPT_XRC_TGT:
1145 pd = to_mxrcd(init_attr->xrcd)->pd;
1146 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1147 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1148 /* fall through */
1149 case IB_QPT_XRC_INI:
1150 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1151 return ERR_PTR(-ENOSYS);
1152 init_attr->recv_cq = init_attr->send_cq;
1153 /* fall through */
225c7b1f
RD		 1154 case IB_QPT_RC:
1155 case IB_QPT_UC:
3987a2d3 1156 case IB_QPT_RAW_PACKET:
40f2287b 1157 qp = kzalloc(sizeof *qp, gfp);
225c7b1f
RD		 1158 if (!qp)
1159 return ERR_PTR(-ENOMEM);
2f5bb473
JM		 1160 qp->pri.vid = 0xFFFF;
1161 qp->alt.vid = 0xFFFF;
1ffeb2eb
JM		 1162 /* fall through */
1163 case IB_QPT_UD:
1164 {
1165 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
40f2287b 1166 udata, 0, &qp, gfp);
1ffeb2eb 1167 if (err)
225c7b1f 1168 return ERR_PTR(err);
225c7b1f
RD		 1169
1170 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1171 qp->xrcdn = xrcdn;
225c7b1f
RD		 1172
1173 break;
1174 }
1175 case IB_QPT_SMI:
1176 case IB_QPT_GSI:
1177 {
1178 /* Userspace is not allowed to create special QPs: */
0a1405da 1179 if (udata)
225c7b1f
RD		 1180 return ERR_PTR(-EINVAL);
1181
0a1405da 1182 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
47605df9 1183 get_sqp_num(to_mdev(pd->device), init_attr),
40f2287b 1184 &qp, gfp);
1ffeb2eb 1185 if (err)
225c7b1f 1186 return ERR_PTR(err);
225c7b1f
RD		 1187
1188 qp->port = init_attr->port_num;
1189 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1190
1191 break;
1192 }
1193 default:
1194 /* Don't support raw QPs */
1195 return ERR_PTR(-EINVAL);
1196 }
1197
1198 return &qp->ibqp;
1199}
1200
1201int mlx4_ib_destroy_qp(struct ib_qp *qp)
1202{
1203 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1204 struct mlx4_ib_qp *mqp = to_mqp(qp);
0a1405da 1205 struct mlx4_ib_pd *pd;
225c7b1f
RD		 1206
1207 if (is_qp0(dev, mqp))
1208 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1209
9433c188
MB		 1210 if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1211 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1212 dev->qp1_proxy[mqp->port - 1] = NULL;
1213 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1214 }
1215
7b59f0f9
EBE		 1216 if (mqp->counter_index)
1217 mlx4_ib_free_qp_counter(dev, mqp);
1218
0a1405da
SH		 1219 pd = get_pd(mqp);
1220 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
225c7b1f
RD		 1221
1222 if (is_sqp(dev, mqp))
1223 kfree(to_msqp(mqp));
1224 else
1225 kfree(mqp);
1226
1227 return 0;
1228}
1229
1ffeb2eb 1230static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1231{
1232 switch (type) {
1ffeb2eb
JM		 1233 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1234 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1235 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1236 case MLX4_IB_QPT_XRC_INI:
1237 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1238 case MLX4_IB_QPT_SMI:
1239 case MLX4_IB_QPT_GSI:
1240 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1241
1242 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1243 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1244 MLX4_QP_ST_MLX : -1);
1245 case MLX4_IB_QPT_PROXY_SMI:
1246 case MLX4_IB_QPT_TUN_SMI:
1247 case MLX4_IB_QPT_PROXY_GSI:
1248 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1249 MLX4_QP_ST_UD : -1);
1250 default: return -1;
225c7b1f
RD		 1251 }
1252}
1253
65adfa91 1254static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1255 int attr_mask)
1256{
1257 u8 dest_rd_atomic;
1258 u32 access_flags;
1259 u32 hw_access_flags = 0;
1260
1261 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1262 dest_rd_atomic = attr->max_dest_rd_atomic;
1263 else
1264 dest_rd_atomic = qp->resp_depth;
1265
1266 if (attr_mask & IB_QP_ACCESS_FLAGS)
1267 access_flags = attr->qp_access_flags;
1268 else
1269 access_flags = qp->atomic_rd_en;
1270
1271 if (!dest_rd_atomic)
1272 access_flags &= IB_ACCESS_REMOTE_WRITE;
1273
1274 if (access_flags & IB_ACCESS_REMOTE_READ)
1275 hw_access_flags |= MLX4_QP_BIT_RRE;
1276 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1277 hw_access_flags |= MLX4_QP_BIT_RAE;
1278 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1279 hw_access_flags |= MLX4_QP_BIT_RWE;
1280
1281 return cpu_to_be32(hw_access_flags);
1282}
1283
65adfa91 1284static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1285 int attr_mask)
1286{
1287 if (attr_mask & IB_QP_PKEY_INDEX)
1288 sqp->pkey_index = attr->pkey_index;
1289 if (attr_mask & IB_QP_QKEY)
1290 sqp->qkey = attr->qkey;
1291 if (attr_mask & IB_QP_SQ_PSN)
1292 sqp->send_psn = attr->sq_psn;
1293}
1294
1295static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1296{
1297 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1298}
1299
297e0dad
MS		 1300static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1301 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1302 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1303{
fa417f7b
EC		 1304 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1305 IB_LINK_LAYER_ETHERNET;
4c3eb3ca 1306 int vidx;
297e0dad 1307 int smac_index;
2f5bb473 1308 int err;
297e0dad 1309
fa417f7b 1310
225c7b1f
RD		 1311 path->grh_mylmc = ah->src_path_bits & 0x7f;
1312 path->rlid = cpu_to_be16(ah->dlid);
1313 if (ah->static_rate) {
1314 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1315 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1316 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1317 --path->static_rate;
1318 } else
1319 path->static_rate = 0;
225c7b1f
RD		 1320
1321 if (ah->ah_flags & IB_AH_GRH) {
5070cd22
MS		 1322 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1323 port,
1324 ah->grh.sgid_index);
1325
1326 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1327 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1328 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1329 return -1;
1330 }
1331
1332 path->grh_mylmc |= 1 << 7;
5070cd22 1333 path->mgid_index = real_sgid_index;
225c7b1f
RD		 1334 path->hop_limit = ah->grh.hop_limit;
1335 path->tclass_flowlabel =
1336 cpu_to_be32((ah->grh.traffic_class << 20) |
1337 (ah->grh.flow_label));
1338 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1339 }
1340
fa417f7b
EC		 1341 if (is_eth) {
1342 if (!(ah->ah_flags & IB_AH_GRH))
1343 return -1;
1344
2f5bb473
JM		 1345 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1346 ((port - 1) << 6) | ((ah->sl & 7) << 3);
4c3eb3ca 1347
297e0dad 1348 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1349 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1350 if (smac_info->vid < 0x1000) {
1351 /* both valid vlan ids */
1352 if (smac_info->vid != vlan_tag) {
1353 /* different VIDs. unreg old and reg new */
1354 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1355 if (err)
1356 return err;
1357 smac_info->candidate_vid = vlan_tag;
1358 smac_info->candidate_vlan_index = vidx;
1359 smac_info->candidate_vlan_port = port;
1360 smac_info->update_vid = 1;
1361 path->vlan_index = vidx;
1362 } else {
1363 path->vlan_index = smac_info->vlan_index;
1364 }
1365 } else {
1366 /* no current vlan tag in qp */
1367 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1368 if (err)
1369 return err;
1370 smac_info->candidate_vid = vlan_tag;
1371 smac_info->candidate_vlan_index = vidx;
1372 smac_info->candidate_vlan_port = port;
1373 smac_info->update_vid = 1;
1374 path->vlan_index = vidx;
1375 }
297e0dad 1376 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1377 path->fl = 1 << 6;
1378 } else {
1379 /* have current vlan tag. unregister it at modify-qp success */
1380 if (smac_info->vid < 0x1000) {
1381 smac_info->candidate_vid = 0xFFFF;
1382 smac_info->update_vid = 1;
1383 }
4c3eb3ca 1384 }
2f5bb473
JM		 1385
1386 /* get smac_index for RoCE use.
1387 * If no smac was yet assigned, register one.
1388 * If one was already assigned, but the new mac differs,
1389 * unregister the old one and register the new one.
1390 */
25476b02
JM		 1391 if ((!smac_info->smac && !smac_info->smac_port) ||
1392 smac_info->smac != smac) {
2f5bb473
JM		 1393 /* register candidate now, unreg if needed, after success */
1394 smac_index = mlx4_register_mac(dev->dev, port, smac);
1395 if (smac_index >= 0) {
1396 smac_info->candidate_smac_index = smac_index;
1397 smac_info->candidate_smac = smac;
1398 smac_info->candidate_smac_port = port;
1399 } else {
1400 return -EINVAL;
1401 }
1402 } else {
1403 smac_index = smac_info->smac_index;
1404 }
1405
1406 memcpy(path->dmac, ah->dmac, 6);
1407 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1408 /* put MAC table smac index for IBoE */
1409 path->grh_mylmc = (u8) (smac_index) | 0x80;
1410 } else {
4c3eb3ca
EC		 1411 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1412 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
2f5bb473 1413 }
fa417f7b 1414
225c7b1f
RD		 1415 return 0;
1416}
1417
297e0dad
MS		 1418static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1419 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1420 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1421 struct mlx4_qp_path *path, u8 port,
1422 u16 vlan_id, u8 *smac)
297e0dad
MS		 1423{
1424 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1425 mlx4_mac_to_u64(smac),
1426 vlan_id,
2f5bb473 1427 path, &mqp->pri, port);
297e0dad
MS		 1428}
1429
1430static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1431 const struct ib_qp_attr *qp,
1432 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1433 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1434 struct mlx4_qp_path *path, u8 port)
1435{
1436 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1437 0,
1438 0xffff,
2f5bb473 1439 path, &mqp->alt, port);
297e0dad
MS		 1440}
1441
fa417f7b
EC		 1442static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1443{
1444 struct mlx4_ib_gid_entry *ge, *tmp;
1445
1446 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1447 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1448 ge->added = 1;
1449 ge->port = qp->port;
1450 }
1451 }
1452}
1453
dbf727de
MB		 1454static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1455 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1456 struct mlx4_qp_context *context)
1457{
2f5bb473
JM		 1458 u64 u64_mac;
1459 int smac_index;
1460
3e0629cb 1461 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1462
1463 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1464 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1465 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1466 if (smac_index >= 0) {
1467 qp->pri.candidate_smac_index = smac_index;
1468 qp->pri.candidate_smac = u64_mac;
1469 qp->pri.candidate_smac_port = qp->port;
1470 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1471 } else {
1472 return -ENOENT;
1473 }
1474 }
1475 return 0;
1476}
1477
7b59f0f9
EBE		 1478static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1479{
1480 struct counter_index *new_counter_index;
1481 int err;
1482 u32 tmp_idx;
1483
1484 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1485 IB_LINK_LAYER_ETHERNET ||
1486 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1487 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1488 return 0;
1489
1490 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1491 if (err)
1492 return err;
1493
1494 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1495 if (!new_counter_index) {
1496 mlx4_counter_free(dev->dev, tmp_idx);
1497 return -ENOMEM;
1498 }
1499
1500 new_counter_index->index = tmp_idx;
1501 new_counter_index->allocated = 1;
1502 qp->counter_index = new_counter_index;
1503
1504 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1505 list_add_tail(&new_counter_index->list,
1506 &dev->counters_table[qp->port - 1].counters_list);
1507 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1508
1509 return 0;
1510}
1511
3b5daf28
MS		 1512enum {
1513 MLX4_QPC_ROCE_MODE_1 = 0,
1514 MLX4_QPC_ROCE_MODE_2 = 2,
1515 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1516};
1517
1518static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1519{
1520 switch (gid_type) {
1521 case IB_GID_TYPE_ROCE:
1522 return MLX4_QPC_ROCE_MODE_1;
1523 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1524 return MLX4_QPC_ROCE_MODE_2;
1525 default:
1526 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1527 }
1528}
1529
65adfa91
MT		 1530static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1531 const struct ib_qp_attr *attr, int attr_mask,
1532 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 1533{
1534 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1535 struct mlx4_ib_qp *qp = to_mqp(ibqp);
0a1405da
SH		 1536 struct mlx4_ib_pd *pd;
1537 struct mlx4_ib_cq *send_cq, *recv_cq;
225c7b1f
RD		 1538 struct mlx4_qp_context *context;
1539 enum mlx4_qp_optpar optpar = 0;
225c7b1f 1540 int sqd_event;
c1c98501 1541 int steer_qp = 0;
225c7b1f 1542 int err = -EINVAL;
3ba8e31d 1543 int counter_index;
225c7b1f 1544
3dec4878
JM		 1545 /* APM is not supported under RoCE */
1546 if (attr_mask & IB_QP_ALT_PATH &&
1547 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1548 IB_LINK_LAYER_ETHERNET)
1549 return -ENOTSUPP;
1550
225c7b1f
RD		 1551 context = kzalloc(sizeof *context, GFP_KERNEL);
1552 if (!context)
1553 return -ENOMEM;
1554
225c7b1f 1555 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 1556 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 1557
1558 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1559 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1560 else {
1561 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1562 switch (attr->path_mig_state) {
1563 case IB_MIG_MIGRATED:
1564 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1565 break;
1566 case IB_MIG_REARM:
1567 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1568 break;
1569 case IB_MIG_ARMED:
1570 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1571 break;
1572 }
1573 }
1574
b832be1e 1575 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 1576 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
3987a2d3
OG		 1577 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1578 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
b832be1e
EC		 1579 else if (ibqp->qp_type == IB_QPT_UD) {
1580 if (qp->flags & MLX4_IB_QP_LSO)
1581 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1582 ilog2(dev->dev->caps.max_gso_sz);
1583 else
6e0d733d 1584 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 1585 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 1586 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 1587 pr_err("path MTU (%u) is invalid\n",
225c7b1f 1588 attr->path_mtu);
f5b40431 1589 goto out;
225c7b1f 1590 }
d1f2cd89
EC		 1591 context->mtu_msgmax = (attr->path_mtu << 5) |
1592 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 1593 }
1594
0e6e7416
RD		 1595 if (qp->rq.wqe_cnt)
1596 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 1597 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1598
0e6e7416
RD		 1599 if (qp->sq.wqe_cnt)
1600 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 1601 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1602
7b59f0f9
EBE		 1603 if (new_state == IB_QPS_RESET && qp->counter_index)
1604 mlx4_ib_free_qp_counter(dev, qp);
1605
0a1405da 1606 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 1607 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 1608 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
02d7ef6f
DB		 1609 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1610 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 1611 }
0e6e7416 1612
225c7b1f
RD		 1613 if (qp->ibqp.uobject)
1614 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1615 else
1616 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1617
1618 if (attr_mask & IB_QP_DEST_QPN)
1619 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1620
1621 if (attr_mask & IB_QP_PORT) {
1622 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1623 !(attr_mask & IB_QP_AV)) {
1624 mlx4_set_sched(&context->pri_path, attr->port_num);
1625 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1626 }
1627 }
1628
cfcde11c 1629 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 1630 err = create_qp_lb_counter(dev, qp);
1631 if (err)
1632 goto out;
1633
3ba8e31d
EBE		 1634 counter_index =
1635 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 1636 if (qp->counter_index)
1637 counter_index = qp->counter_index->index;
1638
3ba8e31d
EBE		 1639 if (counter_index != -1) {
1640 context->pri_path.counter_index = counter_index;
cfcde11c 1641 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 1642 if (qp->counter_index) {
1643 context->pri_path.fl |=
1644 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1645 context->pri_path.vlan_control |=
1646 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1647 }
cfcde11c 1648 } else
47d8417f
EBE		 1649 context->pri_path.counter_index =
1650 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 1651
1652 if (qp->flags & MLX4_IB_QP_NETIF) {
1653 mlx4_ib_steer_qp_reg(dev, qp, 1);
1654 steer_qp = 1;
1655 }
cfcde11c
OG		 1656 }
1657
225c7b1f 1658 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 1659 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1660 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 1661 context->pri_path.pkey_index = attr->pkey_index;
1662 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1663 }
1664
225c7b1f 1665 if (attr_mask & IB_QP_AV) {
dbf727de
MB		 1666 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1667 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1668 union ib_gid gid;
1669 struct ib_gid_attr gid_attr;
1670 u16 vlan = 0xffff;
1671 u8 smac[ETH_ALEN];
1672 int status = 0;
3b5daf28
MS		 1673 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1674 attr->ah_attr.ah_flags & IB_AH_GRH;
dbf727de 1675
3b5daf28 1676 if (is_eth) {
dbf727de
MB		 1677 int index = attr->ah_attr.grh.sgid_index;
1678
1679 status = ib_get_cached_gid(ibqp->device, port_num,
1680 index, &gid, &gid_attr);
1681 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1682 status = -ENOENT;
1683 if (!status && gid_attr.ndev) {
1684 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1685 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1686 dev_put(gid_attr.ndev);
1687 }
1688 }
1689 if (status)
1690 goto out;
1691
2f5bb473 1692 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 1693 port_num, vlan, smac))
225c7b1f 1694 goto out;
225c7b1f
RD		 1695
1696 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1697 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 1698
1699 if (is_eth &&
1700 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1701 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1702
1703 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1704 err = -EINVAL;
1705 goto out;
1706 }
1707 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1708 }
1709
225c7b1f
RD		 1710 }
1711
1712 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 1713 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 1714 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1715 }
1716
1717 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 1718 if (attr->alt_port_num == 0 ||
1719 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 1720 goto out;
225c7b1f 1721
5ae2a7a8
RD		 1722 if (attr->alt_pkey_index >=
1723 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 1724 goto out;
5ae2a7a8 1725
2f5bb473
JM		 1726 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1727 &context->alt_path,
297e0dad 1728 attr->alt_port_num))
f5b40431 1729 goto out;
225c7b1f
RD		 1730
1731 context->alt_path.pkey_index = attr->alt_pkey_index;
1732 context->alt_path.ackto = attr->alt_timeout << 3;
1733 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1734 }
1735
0a1405da
SH		 1736 pd = get_pd(qp);
1737 get_cqs(qp, &send_cq, &recv_cq);
1738 context->pd = cpu_to_be32(pd->pdn);
1739 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1740 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1741 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1742
95d04f07
RD		 1743 /* Set "fast registration enabled" for all kernel QPs */
1744 if (!qp->ibqp.uobject)
1745 context->params1 |= cpu_to_be32(1 << 11);
1746
57f01b53
JM		 1747 if (attr_mask & IB_QP_RNR_RETRY) {
1748 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1749 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1750 }
1751
225c7b1f
RD		 1752 if (attr_mask & IB_QP_RETRY_CNT) {
1753 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1754 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1755 }
1756
1757 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1758 if (attr->max_rd_atomic)
1759 context->params1 |=
1760 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1761 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1762 }
1763
1764 if (attr_mask & IB_QP_SQ_PSN)
1765 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1766
225c7b1f
RD		 1767 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1768 if (attr->max_dest_rd_atomic)
1769 context->params2 |=
1770 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1771 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1772 }
1773
1774 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1775 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1776 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1777 }
1778
1779 if (ibqp->srq)
1780 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1781
1782 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1783 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1784 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1785 }
1786 if (attr_mask & IB_QP_RQ_PSN)
1787 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1788
1ffeb2eb 1789 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 1790 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 1791 if (qp->mlx4_ib_qp_type &
1792 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1793 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1794 else {
1795 if (mlx4_is_mfunc(dev->dev) &&
1796 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1797 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1798 MLX4_RESERVED_QKEY_BASE) {
1799 pr_err("Cannot use reserved QKEY"
1800 " 0x%x (range 0xffff0000..0xffffffff"
1801 " is reserved)\n", attr->qkey);
1802 err = -EINVAL;
1803 goto out;
1804 }
1805 context->qkey = cpu_to_be32(attr->qkey);
1806 }
225c7b1f
RD		 1807 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1808 }
1809
1810 if (ibqp->srq)
1811 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1812
0a1405da 1813 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1814 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1815
1816 if (cur_state == IB_QPS_INIT &&
1817 new_state == IB_QPS_RTR &&
1818 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
3987a2d3
OG		 1819 ibqp->qp_type == IB_QPT_UD ||
1820 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 1821 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 1822 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1823 qp->mlx4_ib_qp_type &
1824 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 1825 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 1826 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1827 context->pri_path.fl = 0x80;
1828 } else {
1829 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1830 context->pri_path.fl = 0x80;
225c7b1f 1831 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 1832 }
2f5bb473
JM		 1833 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1834 IB_LINK_LAYER_ETHERNET) {
1835 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1836 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1837 context->pri_path.feup = 1 << 7; /* don't fsm */
1838 /* handle smac_index */
1839 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1840 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1841 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 1842 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 1843 if (err) {
1844 err = -EINVAL;
1845 goto out;
1846 }
9433c188
MB		 1847 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1848 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 1849 }
1850 }
225c7b1f
RD		 1851 }
1852
d2fce8a9 1853 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 1854 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1855 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 1856 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1857 /* set QP to receive both tunneled & non-tunneled packets */
8e1a03b6 1858 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
d2fce8a9
OG		 1859 context->srqn = cpu_to_be32(7 << 28);
1860 }
1861 }
3528f696 1862
297e0dad
MS		 1863 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1864 int is_eth = rdma_port_get_link_layer(
1865 &dev->ib_dev, qp->port) ==
1866 IB_LINK_LAYER_ETHERNET;
1867 if (is_eth) {
1868 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1869 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1870 }
1871 }
1872
1873
225c7b1f
RD		 1874 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1875 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1876 sqd_event = 1;
1877 else
1878 sqd_event = 0;
1879
d57f5f72 1880 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3b5daf28 1881 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 1882
c0be5fb5
EC		 1883 /*
1884 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1885 * ownership bits of the send queue are set and the SQ
1886 * headroom is stamped so that the hardware doesn't start
1887 * processing stale work requests.
c0be5fb5
EC		 1888 */
1889 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1890 struct mlx4_wqe_ctrl_seg *ctrl;
1891 int i;
1892
0e6e7416 1893 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1894 ctrl = get_send_wqe(qp, i);
1895 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1896 if (qp->sq_max_wqes_per_wr == 1)
1897 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1898
ea54b10c 1899 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1900 }
1901 }
1902
225c7b1f
RD		 1903 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1904 to_mlx4_state(new_state), context, optpar,
1905 sqd_event, &qp->mqp);
1906 if (err)
1907 goto out;
1908
1909 qp->state = new_state;
1910
1911 if (attr_mask & IB_QP_ACCESS_FLAGS)
1912 qp->atomic_rd_en = attr->qp_access_flags;
1913 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1914 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 1915 if (attr_mask & IB_QP_PORT) {
225c7b1f 1916 qp->port = attr->port_num;
fa417f7b
EC		 1917 update_mcg_macs(dev, qp);
1918 }
225c7b1f
RD		 1919 if (attr_mask & IB_QP_ALT_PATH)
1920 qp->alt_port = attr->alt_port_num;
1921
1922 if (is_sqp(dev, qp))
1923 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1924
1925 /*
1926 * If we moved QP0 to RTR, bring the IB link up; if we moved
1927 * QP0 to RESET or ERROR, bring the link back down.
1928 */
1929 if (is_qp0(dev, qp)) {
1930 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 1931 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 1932 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 1933 qp->port);
225c7b1f
RD		 1934
1935 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1936 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1937 mlx4_CLOSE_PORT(dev->dev, qp->port);
1938 }
1939
1940 /*
1941 * If we moved a kernel QP to RESET, clean up all old CQ
1942 * entries and reinitialize the QP.
1943 */
2f5bb473
JM		 1944 if (new_state == IB_QPS_RESET) {
1945 if (!ibqp->uobject) {
1946 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1947 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1948 if (send_cq != recv_cq)
1949 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1950
1951 qp->rq.head = 0;
1952 qp->rq.tail = 0;
1953 qp->sq.head = 0;
1954 qp->sq.tail = 0;
1955 qp->sq_next_wqe = 0;
1956 if (qp->rq.wqe_cnt)
1957 *qp->db.db = 0;
225c7b1f 1958
2f5bb473
JM		 1959 if (qp->flags & MLX4_IB_QP_NETIF)
1960 mlx4_ib_steer_qp_reg(dev, qp, 0);
1961 }
25476b02 1962 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1963 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1964 qp->pri.smac = 0;
25476b02 1965 qp->pri.smac_port = 0;
2f5bb473
JM		 1966 }
1967 if (qp->alt.smac) {
1968 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1969 qp->alt.smac = 0;
1970 }
1971 if (qp->pri.vid < 0x1000) {
1972 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1973 qp->pri.vid = 0xFFFF;
1974 qp->pri.candidate_vid = 0xFFFF;
1975 qp->pri.update_vid = 0;
1976 }
c1c98501 1977
2f5bb473
JM		 1978 if (qp->alt.vid < 0x1000) {
1979 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1980 qp->alt.vid = 0xFFFF;
1981 qp->alt.candidate_vid = 0xFFFF;
1982 qp->alt.update_vid = 0;
1983 }
225c7b1f 1984 }
225c7b1f 1985out:
7b59f0f9
EBE		 1986 if (err && qp->counter_index)
1987 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 1988 if (err && steer_qp)
1989 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 1990 kfree(context);
25476b02
JM		 1991 if (qp->pri.candidate_smac ||
1992 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 1993 if (err) {
1994 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1995 } else {
25476b02 1996 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 1997 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1998 qp->pri.smac = qp->pri.candidate_smac;
1999 qp->pri.smac_index = qp->pri.candidate_smac_index;
2000 qp->pri.smac_port = qp->pri.candidate_smac_port;
2001 }
2002 qp->pri.candidate_smac = 0;
2003 qp->pri.candidate_smac_index = 0;
2004 qp->pri.candidate_smac_port = 0;
2005 }
2006 if (qp->alt.candidate_smac) {
2007 if (err) {
2008 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2009 } else {
2010 if (qp->alt.smac)
2011 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2012 qp->alt.smac = qp->alt.candidate_smac;
2013 qp->alt.smac_index = qp->alt.candidate_smac_index;
2014 qp->alt.smac_port = qp->alt.candidate_smac_port;
2015 }
2016 qp->alt.candidate_smac = 0;
2017 qp->alt.candidate_smac_index = 0;
2018 qp->alt.candidate_smac_port = 0;
2019 }
2020
2021 if (qp->pri.update_vid) {
2022 if (err) {
2023 if (qp->pri.candidate_vid < 0x1000)
2024 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2025 qp->pri.candidate_vid);
2026 } else {
2027 if (qp->pri.vid < 0x1000)
2028 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2029 qp->pri.vid);
2030 qp->pri.vid = qp->pri.candidate_vid;
2031 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2032 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2033 }
2034 qp->pri.candidate_vid = 0xFFFF;
2035 qp->pri.update_vid = 0;
2036 }
2037
2038 if (qp->alt.update_vid) {
2039 if (err) {
2040 if (qp->alt.candidate_vid < 0x1000)
2041 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2042 qp->alt.candidate_vid);
2043 } else {
2044 if (qp->alt.vid < 0x1000)
2045 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2046 qp->alt.vid);
2047 qp->alt.vid = qp->alt.candidate_vid;
2048 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2049 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2050 }
2051 qp->alt.candidate_vid = 0xFFFF;
2052 qp->alt.update_vid = 0;
2053 }
2054
225c7b1f
RD		 2055 return err;
2056}
2057
65adfa91
MT		 2058int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2059 int attr_mask, struct ib_udata *udata)
2060{
2061 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2062 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2063 enum ib_qp_state cur_state, new_state;
2064 int err = -EINVAL;
297e0dad 2065 int ll;
65adfa91
MT		 2066 mutex_lock(&qp->mutex);
2067
2068 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2069 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2070
297e0dad
MS		 2071 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2072 ll = IB_LINK_LAYER_UNSPECIFIED;
2073 } else {
2074 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2075 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2076 }
dd5f03be
MB		 2077
2078 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
297e0dad 2079 attr_mask, ll)) {
b1d8eb5a
JM		 2080 pr_debug("qpn 0x%x: invalid attribute mask specified "
2081 "for transition %d to %d. qp_type %d,"
2082 " attr_mask 0x%x\n",
2083 ibqp->qp_num, cur_state, new_state,
2084 ibqp->qp_type, attr_mask);
65adfa91 2085 goto out;
b1d8eb5a 2086 }
65adfa91 2087
c6215745
MS		 2088 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2089 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2090 if ((ibqp->qp_type == IB_QPT_RC) ||
2091 (ibqp->qp_type == IB_QPT_UD) ||
2092 (ibqp->qp_type == IB_QPT_UC) ||
2093 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2094 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2095 attr->port_num = mlx4_ib_bond_next_port(dev);
2096 }
2097 } else {
2098 /* no sense in changing port_num
2099 * when ports are bonded */
2100 attr_mask &= ~IB_QP_PORT;
2101 }
2102 }
2103
65adfa91 2104 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2105 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2106 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2107 "for transition %d to %d. qp_type %d\n",
2108 ibqp->qp_num, attr->port_num, cur_state,
2109 new_state, ibqp->qp_type);
65adfa91
MT		 2110 goto out;
2111 }
2112
3987a2d3
OG		 2113 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2114 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2115 IB_LINK_LAYER_ETHERNET))
2116 goto out;
2117
5ae2a7a8
RD		 2118 if (attr_mask & IB_QP_PKEY_INDEX) {
2119 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2120 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2121 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2122 "for transition %d to %d. qp_type %d\n",
2123 ibqp->qp_num, attr->pkey_index, cur_state,
2124 new_state, ibqp->qp_type);
5ae2a7a8 2125 goto out;
b1d8eb5a 2126 }
5ae2a7a8
RD		 2127 }
2128
65adfa91
MT		 2129 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2130 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2131 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2132 "Transition %d to %d. qp_type %d\n",
2133 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2134 new_state, ibqp->qp_type);
65adfa91
MT		 2135 goto out;
2136 }
2137
2138 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2139 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2140 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2141 "Transition %d to %d. qp_type %d\n",
2142 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2143 new_state, ibqp->qp_type);
65adfa91
MT		 2144 goto out;
2145 }
2146
2147 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2148 err = 0;
2149 goto out;
2150 }
2151
65adfa91
MT		 2152 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2153
c6215745
MS		 2154 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2155 attr->port_num = 1;
2156
65adfa91
MT		 2157out:
2158 mutex_unlock(&qp->mutex);
2159 return err;
2160}
2161
99ec41d0
JM		 2162static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2163{
2164 int i;
2165 for (i = 0; i < dev->caps.num_ports; i++) {
2166 if (qpn == dev->caps.qp0_proxy[i] ||
2167 qpn == dev->caps.qp0_tunnel[i]) {
2168 *qkey = dev->caps.qp0_qkey[i];
2169 return 0;
2170 }
2171 }
2172 return -EINVAL;
2173}
2174
1ffeb2eb 2175static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
e622f2f4 2176 struct ib_ud_wr *wr,
1ffeb2eb
JM		 2177 void *wqe, unsigned *mlx_seg_len)
2178{
2179 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2180 struct ib_device *ib_dev = &mdev->ib_dev;
2181 struct mlx4_wqe_mlx_seg *mlx = wqe;
2182 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2183 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2184 u16 pkey;
2185 u32 qkey;
2186 int send_size;
2187 int header_size;
2188 int spc;
2189 int i;
2190
e622f2f4 2191 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2192 return -EINVAL;
2193
2194 send_size = 0;
2195
e622f2f4
CH		 2196 for (i = 0; i < wr->wr.num_sge; ++i)
2197 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2198
2199 /* for proxy-qp0 sends, need to add in size of tunnel header */
2200 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2201 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2202 send_size += sizeof (struct mlx4_ib_tunnel_header);
2203
25f40220 2204 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb
JM		 2205
2206 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2207 sqp->ud_header.lrh.service_level =
2208 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2209 sqp->ud_header.lrh.destination_lid =
2210 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2211 sqp->ud_header.lrh.source_lid =
2212 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2213 }
2214
2215 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2216
2217 /* force loopback */
2218 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2219 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2220
2221 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2222 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1ffeb2eb
JM		 2223 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2224 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2225 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2226 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2227 else
2228 sqp->ud_header.bth.destination_qpn =
47605df9 2229 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1ffeb2eb
JM		 2230
2231 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0
JM		 2232 if (mlx4_is_master(mdev->dev)) {
2233 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2234 return -EINVAL;
2235 } else {
2236 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2237 return -EINVAL;
2238 }
1ffeb2eb
JM		 2239 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2240 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2241
2242 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2243 sqp->ud_header.immediate_present = 0;
2244
2245 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2246
2247 /*
2248 * Inline data segments may not cross a 64 byte boundary. If
2249 * our UD header is bigger than the space available up to the
2250 * next 64 byte boundary in the WQE, use two inline data
2251 * segments to hold the UD header.
2252 */
2253 spc = MLX4_INLINE_ALIGN -
2254 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2255 if (header_size <= spc) {
2256 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2257 memcpy(inl + 1, sqp->header_buf, header_size);
2258 i = 1;
2259 } else {
2260 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2261 memcpy(inl + 1, sqp->header_buf, spc);
2262
2263 inl = (void *) (inl + 1) + spc;
2264 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2265 /*
2266 * Need a barrier here to make sure all the data is
2267 * visible before the byte_count field is set.
2268 * Otherwise the HCA prefetcher could grab the 64-byte
2269 * chunk with this inline segment and get a valid (!=
2270 * 0xffffffff) byte count but stale data, and end up
2271 * generating a packet with bad headers.
2272 *
2273 * The first inline segment's byte_count field doesn't
2274 * need a barrier, because it comes after a
2275 * control/MLX segment and therefore is at an offset
2276 * of 16 mod 64.
2277 */
2278 wmb();
2279 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2280 i = 2;
2281 }
2282
2283 *mlx_seg_len =
2284 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2285 return 0;
2286}
2287
e622f2f4 2288static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
f438000f 2289 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2290{
a478868a 2291 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f 2292 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2293 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2294 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2295 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2296 union ib_gid sgid;
225c7b1f
RD		 2297 u16 pkey;
2298 int send_size;
2299 int header_size;
e61ef241 2300 int spc;
225c7b1f 2301 int i;
1ffeb2eb 2302 int err = 0;
57d88cff 2303 u16 vlan = 0xffff;
a29bec12
RD		 2304 bool is_eth;
2305 bool is_vlan = false;
2306 bool is_grh;
225c7b1f
RD		 2307
2308 send_size = 0;
e622f2f4
CH		 2309 for (i = 0; i < wr->wr.num_sge; ++i)
2310 send_size += wr->wr.sg_list[i].length;
225c7b1f 2311
fa417f7b
EC		 2312 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2313 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 2314 if (is_eth) {
1ffeb2eb
JM		 2315 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2316 /* When multi-function is enabled, the ib_core gid
2317 * indexes don't necessarily match the hw ones, so
2318 * we must use our own cache */
6ee51a4e
JM		 2319 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2320 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2321 ah->av.ib.gid_index, &sgid.raw[0]);
2322 if (err)
2323 return err;
1ffeb2eb
JM		 2324 } else {
2325 err = ib_get_cached_gid(ib_dev,
2326 be32_to_cpu(ah->av.ib.port_pd) >> 24,
55ee3ab2
MB		 2327 ah->av.ib.gid_index, &sgid,
2328 NULL);
dbf727de
MB		 2329 if (!err && !memcmp(&sgid, &zgid, sizeof(sgid)))
2330 err = -ENOENT;
1ffeb2eb
JM		 2331 if (err)
2332 return err;
2333 }
2334
0e9855db 2335 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad
MS		 2336 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2337 is_vlan = 1;
2338 }
4c3eb3ca 2339 }
25f40220
MS		 2340 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
2341 0, 0, 0, &sqp->ud_header);
2342 if (err)
2343 return err;
fa417f7b
EC		 2344
2345 if (!is_eth) {
2346 sqp->ud_header.lrh.service_level =
2347 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2348 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2349 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2350 }
225c7b1f 2351
fa417f7b 2352 if (is_grh) {
225c7b1f 2353 sqp->ud_header.grh.traffic_class =
fa417f7b 2354 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 2355 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 2356 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2357 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
6ee51a4e
JM		 2358 if (is_eth)
2359 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2360 else {
1ffeb2eb
JM		 2361 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2362 /* When multi-function is enabled, the ib_core gid
2363 * indexes don't necessarily match the hw ones, so
2364 * we must use our own cache */
2365 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2366 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2367 subnet_prefix;
2368 sqp->ud_header.grh.source_gid.global.interface_id =
2369 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2370 guid_cache[ah->av.ib.gid_index];
2371 } else
2372 ib_get_cached_gid(ib_dev,
2373 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2374 ah->av.ib.gid_index,
55ee3ab2 2375 &sqp->ud_header.grh.source_gid, NULL);
6ee51a4e 2376 }
225c7b1f 2377 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 2378 ah->av.ib.dgid, 16);
225c7b1f
RD		 2379 }
2380
2381 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 2382
2383 if (!is_eth) {
2384 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2385 (sqp->ud_header.lrh.destination_lid ==
2386 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2387 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 2388 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2389 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 2390 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2391 }
225c7b1f 2392
e622f2f4 2393 switch (wr->wr.opcode) {
225c7b1f
RD		 2394 case IB_WR_SEND:
2395 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2396 sqp->ud_header.immediate_present = 0;
2397 break;
2398 case IB_WR_SEND_WITH_IMM:
2399 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2400 sqp->ud_header.immediate_present = 1;
e622f2f4 2401 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 2402 break;
2403 default:
2404 return -EINVAL;
2405 }
2406
fa417f7b 2407 if (is_eth) {
6ee51a4e 2408 struct in6_addr in6;
c0c1d3d7
OD		 2409 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2410
2411 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 2412
1049f138 2413 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 2414 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 2415 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2416 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2417 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 2418
3e0629cb 2419
fa417f7b
EC		 2420 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2421 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca
EC		 2422 if (!is_vlan) {
2423 sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2424 } else {
4c3eb3ca 2425 sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
4c3eb3ca
EC		 2426 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2427 }
fa417f7b
EC		 2428 } else {
2429 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
2430 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2431 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2432 }
e622f2f4 2433 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
225c7b1f
RD		 2434 if (!sqp->qp.ibqp.qp_num)
2435 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2436 else
e622f2f4 2437 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
225c7b1f 2438 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 2439 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 2440 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 2441 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2442 sqp->qkey : wr->remote_qkey);
225c7b1f
RD		 2443 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2444
2445 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2446
2447 if (0) {
987c8f8f 2448 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 2449 for (i = 0; i < header_size / 4; ++i) {
2450 if (i % 8 == 0)
987c8f8f
SP		 2451 pr_err(" [%02x] ", i * 4);
2452 pr_cont(" %08x",
2453 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 2454 if ((i + 1) % 8 == 0)
987c8f8f 2455 pr_cont("\n");
225c7b1f 2456 }
987c8f8f 2457 pr_err("\n");
225c7b1f
RD		 2458 }
2459
e61ef241
RD		 2460 /*
2461 * Inline data segments may not cross a 64 byte boundary. If
2462 * our UD header is bigger than the space available up to the
2463 * next 64 byte boundary in the WQE, use two inline data
2464 * segments to hold the UD header.
2465 */
2466 spc = MLX4_INLINE_ALIGN -
2467 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2468 if (header_size <= spc) {
2469 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2470 memcpy(inl + 1, sqp->header_buf, header_size);
2471 i = 1;
2472 } else {
2473 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2474 memcpy(inl + 1, sqp->header_buf, spc);
2475
2476 inl = (void *) (inl + 1) + spc;
2477 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2478 /*
2479 * Need a barrier here to make sure all the data is
2480 * visible before the byte_count field is set.
2481 * Otherwise the HCA prefetcher could grab the 64-byte
2482 * chunk with this inline segment and get a valid (!=
2483 * 0xffffffff) byte count but stale data, and end up
2484 * generating a packet with bad headers.
2485 *
2486 * The first inline segment's byte_count field doesn't
2487 * need a barrier, because it comes after a
2488 * control/MLX segment and therefore is at an offset
2489 * of 16 mod 64.
2490 */
2491 wmb();
2492 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2493 i = 2;
2494 }
225c7b1f 2495
f438000f
RD		 2496 *mlx_seg_len =
2497 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2498 return 0;
225c7b1f
RD		 2499}
2500
2501static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2502{
2503 unsigned cur;
2504 struct mlx4_ib_cq *cq;
2505
2506 cur = wq->head - wq->tail;
0e6e7416 2507 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 2508 return 0;
2509
2510 cq = to_mcq(ib_cq);
2511 spin_lock(&cq->lock);
2512 cur = wq->head - wq->tail;
2513 spin_unlock(&cq->lock);
2514
0e6e7416 2515 return cur + nreq >= wq->max_post;
225c7b1f
RD		 2516}
2517
95d04f07
RD		 2518static __be32 convert_access(int acc)
2519{
6ff63e19
SM		 2520 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2521 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2522 (acc & IB_ACCESS_REMOTE_WRITE ?
2523 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2524 (acc & IB_ACCESS_REMOTE_READ ?
2525 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 2526 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2527 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2528}
2529
1b2cd0fc
SG		 2530static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2531 struct ib_reg_wr *wr)
2532{
2533 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2534
2535 fseg->flags = convert_access(wr->access);
2536 fseg->mem_key = cpu_to_be32(wr->key);
2537 fseg->buf_list = cpu_to_be64(mr->page_map);
2538 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2539 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2540 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2541 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2542 fseg->reserved[0] = 0;
2543 fseg->reserved[1] = 0;
2544}
2545
95d04f07
RD		 2546static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2547{
aee38fad
SM		 2548 memset(iseg, 0, sizeof(*iseg));
2549 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 2550}
2551
0fbfa6a9
RD		 2552static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2553 u64 remote_addr, u32 rkey)
2554{
2555 rseg->raddr = cpu_to_be64(remote_addr);
2556 rseg->rkey = cpu_to_be32(rkey);
2557 rseg->reserved = 0;
2558}
2559
e622f2f4
CH		 2560static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2561 struct ib_atomic_wr *wr)
0fbfa6a9 2562{
e622f2f4
CH		 2563 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2564 aseg->swap_add = cpu_to_be64(wr->swap);
2565 aseg->compare = cpu_to_be64(wr->compare_add);
2566 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2567 aseg->swap_add = cpu_to_be64(wr->compare_add);
2568 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 2569 } else {
e622f2f4 2570 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 2571 aseg->compare = 0;
2572 }
2573
2574}
2575
6fa8f719 2576static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
e622f2f4 2577 struct ib_atomic_wr *wr)
6fa8f719 2578{
e622f2f4
CH		 2579 aseg->swap_add = cpu_to_be64(wr->swap);
2580 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2581 aseg->compare = cpu_to_be64(wr->compare_add);
2582 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 2583}
2584
0fbfa6a9 2585static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2586 struct ib_ud_wr *wr)
0fbfa6a9 2587{
e622f2f4
CH		 2588 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2589 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2590 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2591 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2592 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 2593}
2594
1ffeb2eb
JM		 2595static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2596 struct mlx4_wqe_datagram_seg *dseg,
e622f2f4 2597 struct ib_ud_wr *wr,
97982f5a 2598 enum mlx4_ib_qp_type qpt)
1ffeb2eb 2599{
e622f2f4 2600 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 2601 struct mlx4_av sqp_av = {0};
2602 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2603
2604 /* force loopback */
2605 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2606 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2607 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2608 cpu_to_be32(0xf0000000);
2609
2610 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a
JM		 2611 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2612 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2613 else
2614 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
47605df9
JM		 2615 /* Use QKEY from the QP context, which is set by master */
2616 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 2617}
2618
e622f2f4 2619static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
1ffeb2eb
JM		 2620{
2621 struct mlx4_wqe_inline_seg *inl = wqe;
2622 struct mlx4_ib_tunnel_header hdr;
e622f2f4 2623 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2624 int spc;
2625 int i;
2626
2627 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 2628 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2629 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2630 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 2631 memcpy(hdr.mac, ah->av.eth.mac, 6);
2632 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 2633
2634 spc = MLX4_INLINE_ALIGN -
2635 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2636 if (sizeof (hdr) <= spc) {
2637 memcpy(inl + 1, &hdr, sizeof (hdr));
2638 wmb();
2639 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2640 i = 1;
2641 } else {
2642 memcpy(inl + 1, &hdr, spc);
2643 wmb();
2644 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2645
2646 inl = (void *) (inl + 1) + spc;
2647 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2648 wmb();
2649 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2650 i = 2;
2651 }
2652
2653 *mlx_seg_len =
2654 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2655}
2656
6e694ea3
JM		 2657static void set_mlx_icrc_seg(void *dseg)
2658{
2659 u32 *t = dseg;
2660 struct mlx4_wqe_inline_seg *iseg = dseg;
2661
2662 t[1] = 0;
2663
2664 /*
2665 * Need a barrier here before writing the byte_count field to
2666 * make sure that all the data is visible before the
2667 * byte_count field is set. Otherwise, if the segment begins
2668 * a new cacheline, the HCA prefetcher could grab the 64-byte
2669 * chunk and get a valid (!= * 0xffffffff) byte count but
2670 * stale data, and end up sending the wrong data.
2671 */
2672 wmb();
2673
2674 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2675}
2676
2677static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 2678{
d420d9e3
RD		 2679 dseg->lkey = cpu_to_be32(sg->lkey);
2680 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 2681
2682 /*
2683 * Need a barrier here before writing the byte_count field to
2684 * make sure that all the data is visible before the
2685 * byte_count field is set. Otherwise, if the segment begins
2686 * a new cacheline, the HCA prefetcher could grab the 64-byte
2687 * chunk and get a valid (!= * 0xffffffff) byte count but
2688 * stale data, and end up sending the wrong data.
2689 */
2690 wmb();
2691
2692 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 2693}
2694
2242fa4f
RD		 2695static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2696{
2697 dseg->byte_count = cpu_to_be32(sg->length);
2698 dseg->lkey = cpu_to_be32(sg->lkey);
2699 dseg->addr = cpu_to_be64(sg->addr);
2700}
2701
e622f2f4 2702static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
0fd7e1d8 2703 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 2704 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 2705{
e622f2f4 2706 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 2707
417608c2
EC		 2708 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2709 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 2710
2711 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 2712 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 2713 return -EINVAL;
2714
e622f2f4 2715 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 2716
e622f2f4 2717 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 2718 *lso_seg_len = halign;
2719 return 0;
2720}
2721
95d04f07
RD		 2722static __be32 send_ieth(struct ib_send_wr *wr)
2723{
2724 switch (wr->opcode) {
2725 case IB_WR_SEND_WITH_IMM:
2726 case IB_WR_RDMA_WRITE_WITH_IMM:
2727 return wr->ex.imm_data;
2728
2729 case IB_WR_SEND_WITH_INV:
2730 return cpu_to_be32(wr->ex.invalidate_rkey);
2731
2732 default:
2733 return 0;
2734 }
2735}
2736
1ffeb2eb
JM		 2737static void add_zero_len_inline(void *wqe)
2738{
2739 struct mlx4_wqe_inline_seg *inl = wqe;
2740 memset(wqe, 0, 16);
2741 inl->byte_count = cpu_to_be32(1 << 31);
2742}
2743
225c7b1f
RD		 2744int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2745 struct ib_send_wr **bad_wr)
2746{
2747 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2748 void *wqe;
2749 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 2750 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 2751 unsigned long flags;
2752 int nreq;
2753 int err = 0;
ea54b10c
JM		 2754 unsigned ind;
2755 int uninitialized_var(stamp);
2756 int uninitialized_var(size);
a3d8e159 2757 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 2758 __be32 dummy;
2759 __be32 *lso_wqe;
2760 __be32 uninitialized_var(lso_hdr_sz);
417608c2 2761 __be32 blh;
225c7b1f 2762 int i;
35f05dab 2763 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 2764
96db0e03 2765 spin_lock_irqsave(&qp->sq.lock, flags);
35f05dab
YH		 2766 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2767 err = -EIO;
2768 *bad_wr = wr;
2769 nreq = 0;
2770 goto out;
2771 }
225c7b1f 2772
ea54b10c 2773 ind = qp->sq_next_wqe;
225c7b1f
RD		 2774
2775 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 2776 lso_wqe = &dummy;
417608c2 2777 blh = 0;
0fd7e1d8 2778
225c7b1f
RD		 2779 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2780 err = -ENOMEM;
2781 *bad_wr = wr;
2782 goto out;
2783 }
2784
2785 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2786 err = -EINVAL;
2787 *bad_wr = wr;
2788 goto out;
2789 }
2790
0e6e7416 2791 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 2792 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 2793
2794 ctrl->srcrb_flags =
2795 (wr->send_flags & IB_SEND_SIGNALED ?
2796 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2797 (wr->send_flags & IB_SEND_SOLICITED ?
2798 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 2799 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2800 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2801 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 2802 qp->sq_signal_bits;
2803
95d04f07 2804 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 2805
2806 wqe += sizeof *ctrl;
2807 size = sizeof *ctrl / 16;
2808
1ffeb2eb
JM		 2809 switch (qp->mlx4_ib_qp_type) {
2810 case MLX4_IB_QPT_RC:
2811 case MLX4_IB_QPT_UC:
225c7b1f
RD		 2812 switch (wr->opcode) {
2813 case IB_WR_ATOMIC_CMP_AND_SWP:
2814 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 2815 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 2816 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2817 atomic_wr(wr)->rkey);
225c7b1f
RD		 2818 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2819
e622f2f4 2820 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 2821 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 2822
225c7b1f
RD		 2823 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2824 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 2825
2826 break;
2827
2828 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 2829 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2830 atomic_wr(wr)->rkey);
6fa8f719
VS		 2831 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2832
e622f2f4 2833 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 2834 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
2835
2836 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2837 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 2838
2839 break;
2840
2841 case IB_WR_RDMA_READ:
2842 case IB_WR_RDMA_WRITE:
2843 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 2844 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2845 rdma_wr(wr)->rkey);
225c7b1f
RD		 2846 wqe += sizeof (struct mlx4_wqe_raddr_seg);
2847 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 2848 break;
95d04f07
RD		 2849
2850 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 2851 ctrl->srcrb_flags |=
2852 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 2853 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2854 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
2855 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2856 break;
2857
1b2cd0fc
SG		 2858 case IB_WR_REG_MR:
2859 ctrl->srcrb_flags |=
2860 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2861 set_reg_seg(wqe, reg_wr(wr));
2862 wqe += sizeof(struct mlx4_wqe_fmr_seg);
2863 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2864 break;
2865
225c7b1f
RD		 2866 default:
2867 /* No extra segments required for sends */
2868 break;
2869 }
2870 break;
2871
1ffeb2eb 2872 case MLX4_IB_QPT_TUN_SMI_OWNER:
e622f2f4
CH		 2873 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2874 ctrl, &seglen);
1ffeb2eb
JM		 2875 if (unlikely(err)) {
2876 *bad_wr = wr;
2877 goto out;
2878 }
2879 wqe += seglen;
2880 size += seglen / 16;
2881 break;
2882 case MLX4_IB_QPT_TUN_SMI:
2883 case MLX4_IB_QPT_TUN_GSI:
2884 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 2885 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 2886 /* set the forced-loopback bit in the data seg av */
2887 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2888 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2889 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2890 break;
2891 case MLX4_IB_QPT_UD:
e622f2f4 2892 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 2893 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2894 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 2895
2896 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 2897 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2898 &lso_hdr_sz, &blh);
b832be1e
EC		 2899 if (unlikely(err)) {
2900 *bad_wr = wr;
2901 goto out;
2902 }
0fd7e1d8 2903 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 2904 wqe += seglen;
2905 size += seglen / 16;
2906 }
225c7b1f
RD		 2907 break;
2908
1ffeb2eb 2909 case MLX4_IB_QPT_PROXY_SMI_OWNER:
e622f2f4
CH		 2910 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2911 ctrl, &seglen);
1ffeb2eb
JM		 2912 if (unlikely(err)) {
2913 *bad_wr = wr;
2914 goto out;
2915 }
2916 wqe += seglen;
2917 size += seglen / 16;
2918 /* to start tunnel header on a cache-line boundary */
2919 add_zero_len_inline(wqe);
2920 wqe += 16;
2921 size++;
e622f2f4 2922 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2923 wqe += seglen;
2924 size += seglen / 16;
2925 break;
2926 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 2927 case MLX4_IB_QPT_PROXY_GSI:
2928 /* If we are tunneling special qps, this is a UD qp.
2929 * In this case we first add a UD segment targeting
2930 * the tunnel qp, and then add a header with address
2931 * information */
e622f2f4
CH		 2932 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2933 ud_wr(wr),
97982f5a 2934 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 2935 wqe += sizeof (struct mlx4_wqe_datagram_seg);
2936 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 2937 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 2938 wqe += seglen;
2939 size += seglen / 16;
2940 break;
2941
2942 case MLX4_IB_QPT_SMI:
2943 case MLX4_IB_QPT_GSI:
e622f2f4
CH		 2944 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2945 &seglen);
f438000f 2946 if (unlikely(err)) {
225c7b1f
RD		 2947 *bad_wr = wr;
2948 goto out;
2949 }
f438000f
RD		 2950 wqe += seglen;
2951 size += seglen / 16;
225c7b1f
RD		 2952 break;
2953
2954 default:
2955 break;
2956 }
2957
6e694ea3
JM		 2958 /*
2959 * Write data segments in reverse order, so as to
2960 * overwrite cacheline stamp last within each
2961 * cacheline. This avoids issues with WQE
2962 * prefetching.
2963 */
225c7b1f 2964
6e694ea3
JM		 2965 dseg = wqe;
2966 dseg += wr->num_sge - 1;
2967 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 2968
2969 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 2970 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2971 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2972 qp->mlx4_ib_qp_type &
2973 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 2974 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 2975 size += sizeof (struct mlx4_wqe_data_seg) / 16;
2976 }
2977
6e694ea3
JM		 2978 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2979 set_data_seg(dseg, wr->sg_list + i);
2980
0fd7e1d8
RD		 2981 /*
2982 * Possibly overwrite stamping in cacheline with LSO
2983 * segment only after making sure all data segments
2984 * are written.
2985 */
2986 wmb();
2987 *lso_wqe = lso_hdr_sz;
2988
225c7b1f
RD		 2989 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2990 MLX4_WQE_CTRL_FENCE : 0) | size;
2991
2992 /*
2993 * Make sure descriptor is fully written before
2994 * setting ownership bit (because HW can start
2995 * executing as soon as we do).
2996 */
2997 wmb();
2998
59b0ed12 2999 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3000 *bad_wr = wr;
225c7b1f
RD		 3001 err = -EINVAL;
3002 goto out;
3003 }
3004
3005 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3006 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 3007
ea54b10c
JM		 3008 stamp = ind + qp->sq_spare_wqes;
3009 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3010
0e6e7416
RD		 3011 /*
3012 * We can improve latency by not stamping the last
3013 * send queue WQE until after ringing the doorbell, so
3014 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 3015 *
3016 * Same optimization applies to padding with NOP wqe
3017 * in case of WQE shrinking (used to prevent wrap-around
3018 * in the middle of WR).
0e6e7416 3019 */
ea54b10c
JM		 3020 if (wr->next) {
3021 stamp_send_wqe(qp, stamp, size * 16);
3022 ind = pad_wraparound(qp, ind);
3023 }
225c7b1f
RD		 3024 }
3025
3026out:
3027 if (likely(nreq)) {
3028 qp->sq.head += nreq;
3029
3030 /*
3031 * Make sure that descriptors are written before
3032 * doorbell record.
3033 */
3034 wmb();
3035
3036 writel(qp->doorbell_qpn,
3037 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3038
3039 /*
3040 * Make sure doorbells don't leak out of SQ spinlock
3041 * and reach the HCA out of order.
3042 */
3043 mmiowb();
0e6e7416 3044
ea54b10c
JM		 3045 stamp_send_wqe(qp, stamp, size * 16);
3046
3047 ind = pad_wraparound(qp, ind);
3048 qp->sq_next_wqe = ind;
225c7b1f
RD		 3049 }
3050
96db0e03 3051 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3052
3053 return err;
3054}
3055
3056int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3057 struct ib_recv_wr **bad_wr)
3058{
3059 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3060 struct mlx4_wqe_data_seg *scat;
3061 unsigned long flags;
3062 int err = 0;
3063 int nreq;
3064 int ind;
1ffeb2eb 3065 int max_gs;
225c7b1f 3066 int i;
35f05dab 3067 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3068
1ffeb2eb 3069 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3070 spin_lock_irqsave(&qp->rq.lock, flags);
3071
35f05dab
YH		 3072 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3073 err = -EIO;
3074 *bad_wr = wr;
3075 nreq = 0;
3076 goto out;
3077 }
3078
0e6e7416 3079 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3080
3081 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3082 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3083 err = -ENOMEM;
3084 *bad_wr = wr;
3085 goto out;
3086 }
3087
3088 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3089 err = -EINVAL;
3090 *bad_wr = wr;
3091 goto out;
3092 }
3093
3094 scat = get_recv_wqe(qp, ind);
3095
1ffeb2eb
JM		 3096 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3097 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3098 ib_dma_sync_single_for_device(ibqp->device,
3099 qp->sqp_proxy_rcv[ind].map,
3100 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3101 DMA_FROM_DEVICE);
3102 scat->byte_count =
3103 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3104 /* use dma lkey from upper layer entry */
3105 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3106 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3107 scat++;
3108 max_gs--;
3109 }
3110
2242fa4f
RD		 3111 for (i = 0; i < wr->num_sge; ++i)
3112 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3113
1ffeb2eb 3114 if (i < max_gs) {
225c7b1f
RD		 3115 scat[i].byte_count = 0;
3116 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3117 scat[i].addr = 0;
3118 }
3119
3120 qp->rq.wrid[ind] = wr->wr_id;
3121
0e6e7416 3122 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3123 }
3124
3125out:
3126 if (likely(nreq)) {
3127 qp->rq.head += nreq;
3128
3129 /*
3130 * Make sure that descriptors are written before
3131 * doorbell record.
3132 */
3133 wmb();
3134
3135 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3136 }
3137
3138 spin_unlock_irqrestore(&qp->rq.lock, flags);
3139
3140 return err;
3141}
6a775e2b
JM		 3142
3143static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3144{
3145 switch (mlx4_state) {
3146 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3147 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3148 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3149 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3150 case MLX4_QP_STATE_SQ_DRAINING:
3151 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3152 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3153 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3154 default: return -1;
3155 }
3156}
3157
3158static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3159{
3160 switch (mlx4_mig_state) {
3161 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3162 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3163 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3164 default: return -1;
3165 }
3166}
3167
3168static int to_ib_qp_access_flags(int mlx4_flags)
3169{
3170 int ib_flags = 0;
3171
3172 if (mlx4_flags & MLX4_QP_BIT_RRE)
3173 ib_flags |= IB_ACCESS_REMOTE_READ;
3174 if (mlx4_flags & MLX4_QP_BIT_RWE)
3175 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3176 if (mlx4_flags & MLX4_QP_BIT_RAE)
3177 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3178
3179 return ib_flags;
3180}
3181
4c3eb3ca 3182static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
6a775e2b
JM		 3183 struct mlx4_qp_path *path)
3184{
4c3eb3ca
EC		 3185 struct mlx4_dev *dev = ibdev->dev;
3186 int is_eth;
3187
8fcea95a 3188 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 3189 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3190
3191 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3192 return;
3193
4c3eb3ca
EC		 3194 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3195 IB_LINK_LAYER_ETHERNET;
3196 if (is_eth)
3197 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3198 ((path->sched_queue & 4) << 1);
3199 else
3200 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3201
6a775e2b 3202 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
6a775e2b
JM		 3203 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3204 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3205 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3206 if (ib_ah_attr->ah_flags) {
3207 ib_ah_attr->grh.sgid_index = path->mgid_index;
3208 ib_ah_attr->grh.hop_limit = path->hop_limit;
3209 ib_ah_attr->grh.traffic_class =
3210 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3211 ib_ah_attr->grh.flow_label =
586bb586 3212 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 3213 memcpy(ib_ah_attr->grh.dgid.raw,
3214 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3215 }
3216}
3217
3218int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3219 struct ib_qp_init_attr *qp_init_attr)
3220{
3221 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3222 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3223 struct mlx4_qp_context context;
3224 int mlx4_state;
0df67030
DB		 3225 int err = 0;
3226
3227 mutex_lock(&qp->mutex);
6a775e2b
JM		 3228
3229 if (qp->state == IB_QPS_RESET) {
3230 qp_attr->qp_state = IB_QPS_RESET;
3231 goto done;
3232 }
3233
3234 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3235 if (err) {
3236 err = -EINVAL;
3237 goto out;
3238 }
6a775e2b
JM		 3239
3240 mlx4_state = be32_to_cpu(context.flags) >> 28;
3241
0df67030
DB		 3242 qp->state = to_ib_qp_state(mlx4_state);
3243 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3244 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3245 qp_attr->path_mig_state =
3246 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3247 qp_attr->qkey = be32_to_cpu(context.qkey);
3248 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3249 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3250 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3251 qp_attr->qp_access_flags =
3252 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3253
3254 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4c3eb3ca
EC		 3255 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3256 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b
JM		 3257 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3258 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3259 }
3260
3261 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 3262 if (qp_attr->qp_state == IB_QPS_INIT)
3263 qp_attr->port_num = qp->port;
3264 else
3265 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 3266
3267 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3268 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3269
3270 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3271
3272 qp_attr->max_dest_rd_atomic =
3273 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3274 qp_attr->min_rnr_timer =
3275 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3276 qp_attr->timeout = context.pri_path.ackto >> 3;
3277 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3278 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3279 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3280
3281done:
3282 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 3283 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3284 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3285
6a775e2b 3286 if (!ibqp->uobject) {
7f5eb9bb
RD		 3287 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3288 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3289 } else {
3290 qp_attr->cap.max_send_wr = 0;
3291 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 3292 }
3293
7f5eb9bb
RD		 3294 /*
3295 * We don't support inline sends for kernel QPs (yet), and we
3296 * don't know what userspace's value should be.
3297 */
3298 qp_attr->cap.max_inline_data = 0;
3299
3300 qp_init_attr->cap = qp_attr->cap;
3301
521e575b
RL		 3302 qp_init_attr->create_flags = 0;
3303 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3304 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3305
3306 if (qp->flags & MLX4_IB_QP_LSO)
3307 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3308
c1c98501
MB		 3309 if (qp->flags & MLX4_IB_QP_NETIF)
3310 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3311
46db567d
DB		 3312 qp_init_attr->sq_sig_type =
3313 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3314 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3315
0df67030
DB		 3316out:
3317 mutex_unlock(&qp->mutex);
3318 return err;
6a775e2b
JM		 3319}
3320
Linux 6.x block layer and io_uring tree(s)