projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RDMA: Check srq_type during create_srq
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
89944450 44#include <rdma/uverbs_ioctl.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
9ce28a20 50#include <rdma/mlx4-abi.h>
225c7b1f 51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
89944450
SR		 56static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
57 struct ib_udata *udata);
35f05dab 58
225c7b1f
RD		 59enum {
60 MLX4_IB_ACK_REQ_FREQ = 8,
61};
62
63enum {
64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
66 MLX4_IB_LINK_TYPE_IB = 0,
67 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 68};
69
83904132 70enum {
417608c2
EC		 71 MLX4_IB_MIN_SQ_STRIDE = 6,
72 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 73};
74
3987a2d3
OG		 75enum {
76 MLX4_RAW_QP_MTU = 7,
77 MLX4_RAW_QP_MSGMAX = 31,
78};
79
297e0dad
MS		 80#ifndef ETH_ALEN
81#define ETH_ALEN 6
82#endif
297e0dad 83
225c7b1f 84static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 85 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
86 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
87 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
88 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
89 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
90 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
91 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
92 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
93 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
94 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 95 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 96 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
97 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 98};
99
400b1ebc
GL		 100enum mlx4_ib_source_type {
101 MLX4_IB_QP_SRC = 0,
102 MLX4_IB_RWQ_SRC = 1,
103};
104
1ffeb2eb
JM		 105static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
106{
107 if (!mlx4_is_master(dev->dev))
108 return 0;
109
47605df9
JM		 110 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
111 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
112 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 113}
114
225c7b1f
RD		 115static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
116{
47605df9
JM		 117 int proxy_sqp = 0;
118 int real_sqp = 0;
119 int i;
120 /* PPF or Native -- real SQP */
121 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
122 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
123 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
124 if (real_sqp)
125 return 1;
126 /* VF or PF -- proxy SQP */
127 if (mlx4_is_mfunc(dev->dev)) {
128 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 129 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
130 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 131 proxy_sqp = 1;
132 break;
133 }
134 }
135 }
e1b866c6
MS		 136 if (proxy_sqp)
137 return 1;
138
139 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 140}
141
1ffeb2eb 142/* used for INIT/CLOSE port logic */
225c7b1f
RD		 143static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
144{
47605df9
JM		 145 int proxy_qp0 = 0;
146 int real_qp0 = 0;
147 int i;
148 /* PPF or Native -- real QP0 */
149 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
150 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
151 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
152 if (real_qp0)
153 return 1;
154 /* VF or PF -- proxy QP0 */
155 if (mlx4_is_mfunc(dev->dev)) {
156 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 157 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 158 proxy_qp0 = 1;
159 break;
160 }
161 }
162 }
163 return proxy_qp0;
225c7b1f
RD		 164}
165
166static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
167{
1c69fc2a 168 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 169}
170
171static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
172{
173 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
174}
175
176static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
177{
178 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
179}
180
0e6e7416
RD		 181/*
182 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
f95ccffc
JM		 183 * first four bytes of every 64 byte chunk with 0xffffffff, except for
184 * the very first chunk of the WQE.
0e6e7416 185 */
f95ccffc 186static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
0e6e7416 187{
d2ae16d5 188 __be32 *wqe;
0e6e7416 189 int i;
ea54b10c 190 int s;
ea54b10c 191 void *buf;
ea54b10c 192 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 193
f95ccffc
JM		 194 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
195 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
196 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
197 for (i = 64; i < s; i += 64) {
198 wqe = buf + i;
199 *wqe = cpu_to_be32(0xffffffff);
ea54b10c 200 }
0e6e7416
RD		 201}
202
225c7b1f
RD		 203static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
204{
205 struct ib_event event;
206 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
207
208 if (type == MLX4_EVENT_TYPE_PATH_MIG)
209 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
210
211 if (ibqp->event_handler) {
212 event.device = ibqp->device;
213 event.element.qp = ibqp;
214 switch (type) {
215 case MLX4_EVENT_TYPE_PATH_MIG:
216 event.event = IB_EVENT_PATH_MIG;
217 break;
218 case MLX4_EVENT_TYPE_COMM_EST:
219 event.event = IB_EVENT_COMM_EST;
220 break;
221 case MLX4_EVENT_TYPE_SQ_DRAINED:
222 event.event = IB_EVENT_SQ_DRAINED;
223 break;
224 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
225 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
226 break;
227 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
228 event.event = IB_EVENT_QP_FATAL;
229 break;
230 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
231 event.event = IB_EVENT_PATH_MIG_ERR;
232 break;
233 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
234 event.event = IB_EVENT_QP_REQ_ERR;
235 break;
236 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
237 event.event = IB_EVENT_QP_ACCESS_ERR;
238 break;
239 default:
987c8f8f 240 pr_warn("Unexpected event type %d "
225c7b1f
RD		 241 "on QP %06x\n", type, qp->qpn);
242 return;
243 }
244
245 ibqp->event_handler(&event, ibqp->qp_context);
246 }
247}
248
400b1ebc
GL		 249static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
250{
251 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
252 type, qp->qpn);
253}
254
1ffeb2eb 255static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 256{
257 /*
258 * UD WQEs must have a datagram segment.
259 * RC and UC WQEs might have a remote address segment.
260 * MLX WQEs need two extra inline data segments (for the UD
261 * header and space for the ICRC).
262 */
263 switch (type) {
1ffeb2eb 264 case MLX4_IB_QPT_UD:
225c7b1f 265 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 266 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 267 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 268 case MLX4_IB_QPT_PROXY_SMI_OWNER:
269 case MLX4_IB_QPT_PROXY_SMI:
270 case MLX4_IB_QPT_PROXY_GSI:
271 return sizeof (struct mlx4_wqe_ctrl_seg) +
272 sizeof (struct mlx4_wqe_datagram_seg) + 64;
273 case MLX4_IB_QPT_TUN_SMI_OWNER:
274 case MLX4_IB_QPT_TUN_GSI:
275 return sizeof (struct mlx4_wqe_ctrl_seg) +
276 sizeof (struct mlx4_wqe_datagram_seg);
277
278 case MLX4_IB_QPT_UC:
225c7b1f
RD		 279 return sizeof (struct mlx4_wqe_ctrl_seg) +
280 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 281 case MLX4_IB_QPT_RC:
225c7b1f 282 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 283 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 284 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 285 case MLX4_IB_QPT_SMI:
286 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 287 return sizeof (struct mlx4_wqe_ctrl_seg) +
288 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 289 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
290 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 291 sizeof (struct mlx4_wqe_inline_seg),
292 sizeof (struct mlx4_wqe_data_seg)) +
293 ALIGN(4 +
294 sizeof (struct mlx4_wqe_inline_seg),
295 sizeof (struct mlx4_wqe_data_seg));
296 default:
297 return sizeof (struct mlx4_wqe_ctrl_seg);
298 }
299}
300
2446304d 301static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
913df8c3 302 bool is_user, bool has_rq, struct mlx4_ib_qp *qp,
ea30b966 303 u32 inl_recv_sz)
225c7b1f 304{
2446304d 305 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 306 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
307 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 308 return -EINVAL;
309
0a1405da 310 if (!has_rq) {
ea30b966 311 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 312 return -EINVAL;
2446304d 313
0e6e7416 314 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 315 } else {
ea30b966
MG		 316 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
317 sizeof(struct mlx4_wqe_data_seg);
318 u32 wqe_size;
319
a4cd7ed8 320 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 321 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
322 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 323 return -EINVAL;
324
0e6e7416 325 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 326 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 327 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
328 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 329 }
2446304d 330
fc2d0044
SG		 331 /* leave userspace return values as they were, so as not to break ABI */
332 if (is_user) {
333 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
334 cap->max_recv_sge = qp->rq.max_gs;
335 } else {
336 cap->max_recv_wr = qp->rq.max_post =
337 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
338 cap->max_recv_sge = min(qp->rq.max_gs,
339 min(dev->dev->caps.max_sq_sg,
340 dev->dev->caps.max_rq_sg));
341 }
2446304d
EC		 342
343 return 0;
344}
345
346static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
f95ccffc 347 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 348{
ea54b10c
JM		 349 int s;
350
2446304d 351 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 352 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
353 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 354 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 355 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
356 return -EINVAL;
357
358 /*
359 * For MLX transport we need 2 extra S/G entries:
360 * one for the header and one for the checksum at the end
361 */
1ffeb2eb
JM		 362 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
363 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 364 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
365 return -EINVAL;
366
ea54b10c
JM		 367 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
368 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 369 send_wqe_overhead(type, qp->flags);
225c7b1f 370
cd155c1c
RD		 371 if (s > dev->dev->caps.max_sq_desc_sz)
372 return -EINVAL;
373
f95ccffc
JM		 374 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
375
0e6e7416 376 /*
f95ccffc
JM		 377 * We need to leave 2 KB + 1 WR of headroom in the SQ to
378 * allow HW to prefetch.
0e6e7416 379 */
350b4c8a 380 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
f95ccffc
JM		 381 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
382 qp->sq_spare_wqes);
383
384 qp->sq.max_gs =
385 (min(dev->dev->caps.max_sq_desc_sz,
386 (1 << qp->sq.wqe_shift)) -
387 send_wqe_overhead(type, qp->flags)) /
b832be1e 388 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 389
390 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
391 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 392 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
393 qp->rq.offset = 0;
0e6e7416 394 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 395 } else {
0e6e7416 396 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 397 qp->sq.offset = 0;
398 }
399
ea54b10c 400 cap->max_send_wr = qp->sq.max_post =
f95ccffc 401 qp->sq.wqe_cnt - qp->sq_spare_wqes;
cd155c1c
RD		 402 cap->max_send_sge = min(qp->sq.max_gs,
403 min(dev->dev->caps.max_sq_sg,
404 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 405 /* We don't support inline sends for kernel QPs (yet) */
406 cap->max_inline_data = 0;
225c7b1f
RD		 407
408 return 0;
409}
410
83904132
JM		 411static int set_user_sq_size(struct mlx4_ib_dev *dev,
412 struct mlx4_ib_qp *qp,
2446304d
EC		 413 struct mlx4_ib_create_qp *ucmd)
414{
83904132
JM		 415 /* Sanity check SQ size before proceeding */
416 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
417 ucmd->log_sq_stride >
418 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
419 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
420 return -EINVAL;
421
0e6e7416 422 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 423 qp->sq.wqe_shift = ucmd->log_sq_stride;
424
0e6e7416
RD		 425 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
426 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 427
428 return 0;
429}
430
1ffeb2eb
JM		 431static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
432{
433 int i;
434
435 qp->sqp_proxy_rcv =
6da2ec56
KC		 436 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
437 GFP_KERNEL);
1ffeb2eb
JM		 438 if (!qp->sqp_proxy_rcv)
439 return -ENOMEM;
440 for (i = 0; i < qp->rq.wqe_cnt; i++) {
441 qp->sqp_proxy_rcv[i].addr =
442 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
443 GFP_KERNEL);
444 if (!qp->sqp_proxy_rcv[i].addr)
445 goto err;
446 qp->sqp_proxy_rcv[i].map =
447 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
448 sizeof (struct mlx4_ib_proxy_sqp_hdr),
449 DMA_FROM_DEVICE);
cc47d369
SO		 450 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
451 kfree(qp->sqp_proxy_rcv[i].addr);
452 goto err;
453 }
1ffeb2eb
JM		 454 }
455 return 0;
456
457err:
458 while (i > 0) {
459 --i;
460 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
461 sizeof (struct mlx4_ib_proxy_sqp_hdr),
462 DMA_FROM_DEVICE);
463 kfree(qp->sqp_proxy_rcv[i].addr);
464 }
465 kfree(qp->sqp_proxy_rcv);
466 qp->sqp_proxy_rcv = NULL;
467 return -ENOMEM;
468}
469
470static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
471{
472 int i;
473
474 for (i = 0; i < qp->rq.wqe_cnt; i++) {
475 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
476 sizeof (struct mlx4_ib_proxy_sqp_hdr),
477 DMA_FROM_DEVICE);
478 kfree(qp->sqp_proxy_rcv[i].addr);
479 }
480 kfree(qp->sqp_proxy_rcv);
481}
482
913df8c3 483static bool qp_has_rq(struct ib_qp_init_attr *attr)
0a1405da
SH		 484{
485 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
913df8c3 486 return false;
0a1405da
SH		 487
488 return !attr->srq;
489}
490
99ec41d0
JM		 491static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
492{
493 int i;
494 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 495 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
496 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 497 }
498 return 0;
499}
500
7b59f0f9
EBE		 501static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
502 struct mlx4_ib_qp *qp)
503{
504 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
505 mlx4_counter_free(dev->dev, qp->counter_index->index);
506 list_del(&qp->counter_index->list);
507 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
508
509 kfree(qp->counter_index);
510 qp->counter_index = NULL;
511}
512
3078f5f1
GL		 513static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
514 struct ib_qp_init_attr *init_attr,
515 struct mlx4_ib_create_qp_rss *ucmd)
516{
517 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
518 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
519
520 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
521 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
522 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
523 MLX4_EN_RSS_KEY_SIZE);
524 } else {
525 pr_debug("RX Hash function is not supported\n");
526 return (-EOPNOTSUPP);
527 }
528
4d02ebd9
GL		 529 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
530 MLX4_IB_RX_HASH_DST_IPV4 |
531 MLX4_IB_RX_HASH_SRC_IPV6 |
532 MLX4_IB_RX_HASH_DST_IPV6 |
533 MLX4_IB_RX_HASH_SRC_PORT_TCP |
534 MLX4_IB_RX_HASH_DST_PORT_TCP |
535 MLX4_IB_RX_HASH_SRC_PORT_UDP |
4f9ca2d8
LR		 536 MLX4_IB_RX_HASH_DST_PORT_UDP |
537 MLX4_IB_RX_HASH_INNER)) {
4d02ebd9
GL		 538 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
539 ucmd->rx_hash_fields_mask);
540 return (-EOPNOTSUPP);
541 }
542
3078f5f1
GL		 543 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
544 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
545 rss_ctx->flags = MLX4_RSS_IPV4;
546 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
547 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
548 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
549 return (-EOPNOTSUPP);
550 }
551
552 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
553 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
554 rss_ctx->flags |= MLX4_RSS_IPV6;
555 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
556 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
557 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
558 return (-EOPNOTSUPP);
559 }
560
561 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
562 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
563 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
564 pr_debug("RX Hash fields_mask for UDP is not supported\n");
565 return (-EOPNOTSUPP);
566 }
567
4d02ebd9 568 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 569 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 570 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 571 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 572 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 573 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
574 return (-EOPNOTSUPP);
575 }
576 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
577 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
578 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
579 return (-EOPNOTSUPP);
580 }
581
582 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
583 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 584 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 585 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 586 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 587 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 588 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 589 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
590 return (-EOPNOTSUPP);
591 }
3078f5f1
GL		 592 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
593 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
594 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
595 return (-EOPNOTSUPP);
596 }
597
07d84f7b
GL		 598 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
599 if (dev->dev->caps.tunnel_offload_mode ==
600 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
601 /*
602 * Hash according to inner headers if exist, otherwise
603 * according to outer headers.
604 */
605 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
606 } else {
607 pr_debug("RSS Hash for inner headers isn't supported\n");
608 return (-EOPNOTSUPP);
609 }
610 }
611
3078f5f1
GL		 612 return 0;
613}
614
d7c0557a 615static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 616 struct ib_qp_init_attr *init_attr,
617 struct mlx4_ib_create_qp_rss *ucmd,
618 struct mlx4_ib_qp *qp)
619{
620 int qpn;
621 int err;
622
623 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
624
625 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
626 if (err)
627 return err;
628
629 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
630 if (err)
631 goto err_qpn;
632
3078f5f1
GL		 633 INIT_LIST_HEAD(&qp->gid_list);
634 INIT_LIST_HEAD(&qp->steering_rules);
635
c3f1ee29 636 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 637 qp->state = IB_QPS_RESET;
638
639 /* Set dummy send resources to be compatible with HV and PRM */
640 qp->sq_no_prefetch = 1;
641 qp->sq.wqe_cnt = 1;
642 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
643 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
644 qp->mtt = (to_mqp(
645 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
646
647 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
648 if (!qp->rss_ctx) {
649 err = -ENOMEM;
650 goto err_qp_alloc;
651 }
652
653 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
654 if (err)
655 goto err;
656
657 return 0;
658
659err:
660 kfree(qp->rss_ctx);
661
662err_qp_alloc:
663 mlx4_qp_remove(dev->dev, &qp->mqp);
664 mlx4_qp_free(dev->dev, &qp->mqp);
665
666err_qpn:
667 mlx4_qp_release_range(dev->dev, qpn, 1);
668 return err;
669}
670
8fd3cd2a
LR		 671static int _mlx4_ib_create_qp_rss(struct ib_pd *pd, struct mlx4_ib_qp *qp,
672 struct ib_qp_init_attr *init_attr,
673 struct ib_udata *udata)
3078f5f1 674{
3078f5f1
GL		 675 struct mlx4_ib_create_qp_rss ucmd = {};
676 size_t required_cmd_sz;
677 int err;
678
679 if (!udata) {
680 pr_debug("RSS QP with NULL udata\n");
8fd3cd2a 681 return -EINVAL;
3078f5f1
GL		 682 }
683
684 if (udata->outlen)
8fd3cd2a 685 return -EOPNOTSUPP;
3078f5f1
GL		 686
687 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
688 sizeof(ucmd.reserved1);
689 if (udata->inlen < required_cmd_sz) {
690 pr_debug("invalid inlen\n");
8fd3cd2a 691 return -EINVAL;
3078f5f1
GL		 692 }
693
694 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
695 pr_debug("copy failed\n");
8fd3cd2a 696 return -EFAULT;
3078f5f1
GL		 697 }
698
f9bfea99 699 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
8fd3cd2a 700 return -EOPNOTSUPP;
f9bfea99 701
3078f5f1 702 if (ucmd.comp_mask || ucmd.reserved1)
8fd3cd2a 703 return -EOPNOTSUPP;
3078f5f1
GL		 704
705 if (udata->inlen > sizeof(ucmd) &&
706 !ib_is_udata_cleared(udata, sizeof(ucmd),
707 udata->inlen - sizeof(ucmd))) {
708 pr_debug("inlen is not supported\n");
8fd3cd2a 709 return -EOPNOTSUPP;
3078f5f1
GL		 710 }
711
712 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
713 pr_debug("RSS QP with unsupported QP type %d\n",
714 init_attr->qp_type);
8fd3cd2a 715 return -EOPNOTSUPP;
3078f5f1
GL		 716 }
717
718 if (init_attr->create_flags) {
719 pr_debug("RSS QP doesn't support create flags\n");
8fd3cd2a 720 return -EOPNOTSUPP;
3078f5f1
GL		 721 }
722
723 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
724 pr_debug("RSS QP with unsupported send attributes\n");
8fd3cd2a 725 return -EOPNOTSUPP;
3078f5f1
GL		 726 }
727
3078f5f1
GL		 728 qp->pri.vid = 0xFFFF;
729 qp->alt.vid = 0xFFFF;
730
d7c0557a 731 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
8fd3cd2a
LR		 732 if (err)
733 return err;
3078f5f1
GL		 734
735 qp->ibqp.qp_num = qp->mqp.qpn;
8fd3cd2a 736 return 0;
3078f5f1
GL		 737}
738
400b1ebc
GL		 739/*
740 * This function allocates a WQN from a range which is consecutive and aligned
741 * to its size. In case the range is full, then it creates a new range and
742 * allocates WQN from it. The new range will be used for following allocations.
743 */
744static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
745 struct mlx4_ib_qp *qp, int range_size, int *wqn)
746{
747 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
748 struct mlx4_wqn_range *range;
749 int err = 0;
750
751 mutex_lock(&context->wqn_ranges_mutex);
752
753 range = list_first_entry_or_null(&context->wqn_ranges_list,
754 struct mlx4_wqn_range, list);
755
756 if (!range || (range->refcount == range->size) || range->dirty) {
757 range = kzalloc(sizeof(*range), GFP_KERNEL);
758 if (!range) {
759 err = -ENOMEM;
760 goto out;
761 }
762
763 err = mlx4_qp_reserve_range(dev->dev, range_size,
764 range_size, &range->base_wqn, 0,
765 qp->mqp.usage);
766 if (err) {
767 kfree(range);
768 goto out;
769 }
770
771 range->size = range_size;
772 list_add(&range->list, &context->wqn_ranges_list);
773 } else if (range_size != 1) {
774 /*
775 * Requesting a new range (>1) when last range is still open, is
776 * not valid.
777 */
778 err = -EINVAL;
779 goto out;
780 }
781
782 qp->wqn_range = range;
783
784 *wqn = range->base_wqn + range->refcount;
785
786 range->refcount++;
787
788out:
789 mutex_unlock(&context->wqn_ranges_mutex);
790
791 return err;
792}
793
794static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
795 struct mlx4_ib_qp *qp, bool dirty_release)
796{
797 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
798 struct mlx4_wqn_range *range;
799
800 mutex_lock(&context->wqn_ranges_mutex);
801
802 range = qp->wqn_range;
803
804 range->refcount--;
805 if (!range->refcount) {
806 mlx4_qp_release_range(dev->dev, range->base_wqn,
807 range->size);
808 list_del(&range->list);
809 kfree(range);
810 } else if (dirty_release) {
811 /*
812 * A range which one of its WQNs is destroyed, won't be able to be
813 * reused for further WQN allocations.
814 * The next created WQ will allocate a new range.
815 */
cf368beb 816 range->dirty = true;
400b1ebc
GL		 817 }
818
819 mutex_unlock(&context->wqn_ranges_mutex);
820}
821
089b645d
LR		 822static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
823 struct ib_udata *udata, struct mlx4_ib_qp *qp)
824{
825 struct mlx4_ib_dev *dev = to_mdev(pd->device);
826 int qpn;
827 int err;
828 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
829 udata, struct mlx4_ib_ucontext, ibucontext);
830 struct mlx4_ib_cq *mcq;
831 unsigned long flags;
832 int range_size;
833 struct mlx4_ib_create_wq wq;
834 size_t copy_len;
835 int shift;
836 int n;
837
838 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
839
089b645d
LR		 840 spin_lock_init(&qp->sq.lock);
841 spin_lock_init(&qp->rq.lock);
842 INIT_LIST_HEAD(&qp->gid_list);
843 INIT_LIST_HEAD(&qp->steering_rules);
844
845 qp->state = IB_QPS_RESET;
846
847 copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
848
849 if (ib_copy_from_udata(&wq, udata, copy_len)) {
850 err = -EFAULT;
851 goto err;
852 }
853
854 if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] ||
855 wq.reserved[2]) {
856 pr_debug("user command isn't supported\n");
857 err = -EOPNOTSUPP;
858 goto err;
859 }
860
861 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) {
862 pr_debug("WQN range size must be equal or smaller than %d\n",
863 dev->dev->caps.max_rss_tbl_sz);
864 err = -EOPNOTSUPP;
865 goto err;
866 }
867 range_size = 1 << wq.log_range_size;
868
869 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS)
870 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
871
913df8c3 872 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz);
089b645d
LR		 873 if (err)
874 goto err;
875
876 qp->sq_no_prefetch = 1;
877 qp->sq.wqe_cnt = 1;
878 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
879 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
880 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
881
c320e527 882 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0);
089b645d
LR		 883 if (IS_ERR(qp->umem)) {
884 err = PTR_ERR(qp->umem);
885 goto err;
886 }
887
089b645d
LR		 888 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
889 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
890
891 if (err)
892 goto err_buf;
893
894 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
895 if (err)
896 goto err_mtt;
897
898 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db);
899 if (err)
900 goto err_mtt;
901 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
902
903 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn);
904 if (err)
905 goto err_wrid;
906
907 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
908 if (err)
909 goto err_qpn;
910
911 /*
912 * Hardware wants QPN written in big-endian order (after
913 * shifting) for send doorbell. Precompute this value to save
914 * a little bit when posting sends.
915 */
916 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
917
918 qp->mqp.event = mlx4_ib_wq_event;
919
920 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
921 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
922 to_mcq(init_attr->recv_cq));
923 /* Maintain device to QPs access, needed for further handling
924 * via reset flow
925 */
926 list_add_tail(&qp->qps_list, &dev->qp_list);
927 /* Maintain CQ to QPs access, needed for further handling
928 * via reset flow
929 */
930 mcq = to_mcq(init_attr->send_cq);
931 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
932 mcq = to_mcq(init_attr->recv_cq);
933 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
934 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
935 to_mcq(init_attr->recv_cq));
936 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
937 return 0;
938
939err_qpn:
940 mlx4_ib_release_wqn(context, qp, 0);
941err_wrid:
942 mlx4_ib_db_unmap_user(context, &qp->db);
943
944err_mtt:
945 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
946err_buf:
947 ib_umem_release(qp->umem);
948err:
949 return err;
950}
951
952static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
8900b894 953 struct ib_udata *udata, int sqpn,
8fd3cd2a 954 struct mlx4_ib_qp *qp)
225c7b1f 955{
089b645d 956 struct mlx4_ib_dev *dev = to_mdev(pd->device);
a3cdcbfa 957 int qpn;
225c7b1f 958 int err;
89944450
SR		 959 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
960 udata, struct mlx4_ib_ucontext, ibucontext);
1ffeb2eb 961 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 962 struct mlx4_ib_cq *mcq;
963 unsigned long flags;
1ffeb2eb
JM		 964
965 /* When tunneling special qps, we use a plain UD qp */
966 if (sqpn) {
967 if (mlx4_is_mfunc(dev->dev) &&
968 (!mlx4_is_master(dev->dev) ||
969 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
970 if (init_attr->qp_type == IB_QPT_GSI)
971 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 972 else {
973 if (mlx4_is_master(dev->dev) ||
974 qp0_enabled_vf(dev->dev, sqpn))
975 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
976 else
977 qp_type = MLX4_IB_QPT_PROXY_SMI;
978 }
1ffeb2eb
JM		 979 }
980 qpn = sqpn;
981 /* add extra sg entry for tunneling */
982 init_attr->cap.max_recv_sge++;
983 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
984 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
985 container_of(init_attr,
986 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
987 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
988 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
989 !mlx4_is_master(dev->dev))
990 return -EINVAL;
991 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
992 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 993 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
994 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
995 tnl_init->port))
1ffeb2eb
JM		 996 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
997 else
998 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 999 /* we are definitely in the PPF here, since we are creating
1000 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1001 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1002 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 1003 sqpn = qpn;
1004 }
1005
8fd3cd2a
LR		 1006 if (init_attr->qp_type == IB_QPT_SMI ||
1007 init_attr->qp_type == IB_QPT_GSI || qp_type == MLX4_IB_QPT_SMI ||
1008 qp_type == MLX4_IB_QPT_GSI ||
1009 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1010 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1011 qp->sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1012 if (!qp->sqp)
915ec7ed 1013 return -ENOMEM;
8fd3cd2a 1014 }
1ffeb2eb
JM		 1015
1016 qp->mlx4_ib_qp_type = qp_type;
225c7b1f 1017
225c7b1f
RD		 1018 spin_lock_init(&qp->sq.lock);
1019 spin_lock_init(&qp->rq.lock);
fa417f7b 1020 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1021 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f 1022
089b645d 1023 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1024 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1025 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1026
e00b64f7 1027 if (udata) {
089b645d 1028 struct mlx4_ib_create_qp ucmd;
400b1ebc 1029 size_t copy_len;
ed8637d3
GL		 1030 int shift;
1031 int n;
400b1ebc 1032
089b645d 1033 copy_len = sizeof(struct mlx4_ib_create_qp);
225c7b1f 1034
400b1ebc 1035 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1036 err = -EFAULT;
1037 goto err;
1038 }
1039
089b645d 1040 qp->inl_recv_sz = ucmd.inl_recv_sz;
0e6e7416 1041
6d06c9aa
GL		 1042 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1043 if (!(dev->dev->caps.flags &
1044 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1045 pr_debug("scatter FCS is unsupported\n");
1046 err = -EOPNOTSUPP;
1047 goto err;
1048 }
1049
1050 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1051 }
1052
e00b64f7 1053 err = set_rq_size(dev, &init_attr->cap, udata,
400b1ebc 1054 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1055 if (err)
1056 goto err;
1057
089b645d 1058 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
400b1ebc 1059
089b645d
LR		 1060 err = set_user_sq_size(dev, qp, &ucmd);
1061 if (err)
1062 goto err;
400b1ebc 1063
c320e527
MS		 1064 qp->umem =
1065 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0);
225c7b1f
RD		 1066 if (IS_ERR(qp->umem)) {
1067 err = PTR_ERR(qp->umem);
1068 goto err;
1069 }
1070
ed8637d3
GL		 1071 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1072 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1073
225c7b1f
RD		 1074 if (err)
1075 goto err_buf;
1076
1077 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1078 if (err)
1079 goto err_mtt;
1080
0a1405da 1081 if (qp_has_rq(init_attr)) {
089b645d 1082 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db);
02d89b87
RD		 1083 if (err)
1084 goto err_mtt;
1085 }
f3301870 1086 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1087 } else {
e00b64f7 1088 err = set_rq_size(dev, &init_attr->cap, udata,
ea30b966
MG		 1089 qp_has_rq(init_attr), qp, 0);
1090 if (err)
1091 goto err;
1092
0e6e7416
RD		 1093 qp->sq_no_prefetch = 0;
1094
b832be1e
EC		 1095 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1096 qp->flags |= MLX4_IB_QP_LSO;
1097
c1c98501
MB		 1098 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1099 if (dev->steering_support ==
1100 MLX4_STEERING_MODE_DEVICE_MANAGED)
1101 qp->flags |= MLX4_IB_QP_NETIF;
1102 else
1103 goto err;
1104 }
1105
f95ccffc 1106 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 1107 if (err)
1108 goto err;
1109
0a1405da 1110 if (qp_has_rq(init_attr)) {
8900b894 1111 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1112 if (err)
1113 goto err;
225c7b1f 1114
02d89b87
RD		 1115 *qp->db.db = 0;
1116 }
225c7b1f 1117
f95ccffc 1118 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
8900b894 1119 &qp->buf)) {
f95ccffc
JM		 1120 err = -ENOMEM;
1121 goto err_db;
225c7b1f
RD		 1122 }
1123
1124 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1125 &qp->mtt);
1126 if (err)
1127 goto err_buf;
1128
8900b894 1129 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1130 if (err)
1131 goto err_mtt;
1132
e9105cde
LD		 1133 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1134 sizeof(u64), GFP_KERNEL);
1135 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1136 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1137 if (!qp->sq.wrid || !qp->rq.wrid) {
1138 err = -ENOMEM;
1139 goto err_wrid;
1140 }
f3301870 1141 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1142 }
1143
a3cdcbfa 1144 if (sqpn) {
1ffeb2eb
JM		 1145 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1146 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1147 if (alloc_proxy_bufs(pd->device, qp)) {
1148 err = -ENOMEM;
1149 goto err_wrid;
1150 }
1151 }
a3cdcbfa 1152 } else {
ddae0349
EE		 1153 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1154 * otherwise, the WQE BlueFlame setup flow wrongly causes
1155 * VLAN insertion. */
3987a2d3 1156 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1157 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1158 (init_attr->cap.max_send_wr ?
1159 MLX4_RESERVE_ETH_BF_QP : 0) |
1160 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1161 MLX4_RESERVE_A0_QP : 0),
1162 qp->mqp.usage);
3987a2d3 1163 else
c1c98501
MB		 1164 if (qp->flags & MLX4_IB_QP_NETIF)
1165 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1166 else
1167 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1168 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1169 if (err)
1ffeb2eb 1170 goto err_proxy;
a3cdcbfa
YP		 1171 }
1172
fbfb6625
EBE		 1173 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1174 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1175
8900b894 1176 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1177 if (err)
a3cdcbfa 1178 goto err_qpn;
225c7b1f 1179
0a1405da
SH		 1180 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1181 qp->mqp.qpn |= (1 << 23);
1182
225c7b1f
RD		 1183 /*
1184 * Hardware wants QPN written in big-endian order (after
1185 * shifting) for send doorbell. Precompute this value to save
1186 * a little bit when posting sends.
1187 */
1188 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1189
089b645d 1190 qp->mqp.event = mlx4_ib_qp_event;
400b1ebc 1191
35f05dab
YH		 1192 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1193 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1194 to_mcq(init_attr->recv_cq));
1195 /* Maintain device to QPs access, needed for further handling
1196 * via reset flow
1197 */
1198 list_add_tail(&qp->qps_list, &dev->qp_list);
1199 /* Maintain CQ to QPs access, needed for further handling
1200 * via reset flow
1201 */
1202 mcq = to_mcq(init_attr->send_cq);
1203 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1204 mcq = to_mcq(init_attr->recv_cq);
1205 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1206 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1207 to_mcq(init_attr->recv_cq));
1208 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1209 return 0;
1210
a3cdcbfa 1211err_qpn:
c1c98501
MB		 1212 if (!sqpn) {
1213 if (qp->flags & MLX4_IB_QP_NETIF)
1214 mlx4_ib_steer_qp_free(dev, qpn, 1);
1215 else
1216 mlx4_qp_release_range(dev->dev, qpn, 1);
1217 }
1ffeb2eb
JM		 1218err_proxy:
1219 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1220 free_proxy_bufs(pd->device, qp);
225c7b1f 1221err_wrid:
e00b64f7 1222 if (udata) {
0a1405da 1223 if (qp_has_rq(init_attr))
89944450 1224 mlx4_ib_db_unmap_user(context, &qp->db);
23f1b384 1225 } else {
0ef2f05c
WW		 1226 kvfree(qp->sq.wrid);
1227 kvfree(qp->rq.wrid);
225c7b1f
RD		 1228 }
1229
1230err_mtt:
1231 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1232
1233err_buf:
836a0fbb 1234 if (!qp->umem)
225c7b1f 1235 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
836a0fbb 1236 ib_umem_release(qp->umem);
225c7b1f
RD		 1237
1238err_db:
e00b64f7 1239 if (!udata && qp_has_rq(init_attr))
6296883c 1240 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1241
1242err:
8fd3cd2a 1243 kfree(qp->sqp);
225c7b1f
RD		 1244 return err;
1245}
1246
1247static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1248{
1249 switch (state) {
1250 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1251 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1252 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1253 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1254 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1255 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1256 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1257 default: return -1;
1258 }
1259}
1260
1261static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1262 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1263{
338a8fad 1264 if (send_cq == recv_cq) {
35f05dab 1265 spin_lock(&send_cq->lock);
338a8fad
RD		 1266 __acquire(&recv_cq->lock);
1267 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1268 spin_lock(&send_cq->lock);
225c7b1f
RD		 1269 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1270 } else {
35f05dab 1271 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1272 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1273 }
1274}
1275
1276static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1277 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1278{
338a8fad
RD		 1279 if (send_cq == recv_cq) {
1280 __release(&recv_cq->lock);
35f05dab 1281 spin_unlock(&send_cq->lock);
338a8fad 1282 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1283 spin_unlock(&recv_cq->lock);
35f05dab 1284 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1285 } else {
1286 spin_unlock(&send_cq->lock);
35f05dab 1287 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1288 }
1289}
1290
fa417f7b
EC		 1291static void del_gid_entries(struct mlx4_ib_qp *qp)
1292{
1293 struct mlx4_ib_gid_entry *ge, *tmp;
1294
1295 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1296 list_del(&ge->list);
1297 kfree(ge);
1298 }
1299}
1300
0a1405da
SH		 1301static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1302{
1303 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1304 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1305 else
1306 return to_mpd(qp->ibqp.pd);
1307}
1308
400b1ebc 1309static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1310 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1311{
1312 switch (qp->ibqp.qp_type) {
1313 case IB_QPT_XRC_TGT:
1314 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1315 *recv_cq = *send_cq;
1316 break;
1317 case IB_QPT_XRC_INI:
1318 *send_cq = to_mcq(qp->ibqp.send_cq);
1319 *recv_cq = *send_cq;
1320 break;
1321 default:
400b1ebc
GL		 1322 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1323 to_mcq(qp->ibwq.cq);
1324 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1325 *recv_cq;
0a1405da
SH		 1326 break;
1327 }
1328}
1329
3078f5f1
GL		 1330static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1331{
1332 if (qp->state != IB_QPS_RESET) {
1333 int i;
1334
1335 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1336 i++) {
1337 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1338 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1339
1340 mutex_lock(&wq->mutex);
1341
1342 wq->rss_usecnt--;
1343
1344 mutex_unlock(&wq->mutex);
1345 }
1346
1347 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1348 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1349 pr_warn("modify QP %06x to RESET failed.\n",
1350 qp->mqp.qpn);
1351 }
1352
1353 mlx4_qp_remove(dev->dev, &qp->mqp);
1354 mlx4_qp_free(dev->dev, &qp->mqp);
1355 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1356 del_gid_entries(qp);
3078f5f1
GL		 1357}
1358
225c7b1f 1359static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
bdeacabd
SR		 1360 enum mlx4_ib_source_type src,
1361 struct ib_udata *udata)
225c7b1f
RD		 1362{
1363 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1364 unsigned long flags;
225c7b1f 1365
2f5bb473 1366 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1367 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1368 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1369 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1370 qp->mqp.qpn);
25476b02 1371 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1372 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1373 qp->pri.smac = 0;
25476b02 1374 qp->pri.smac_port = 0;
2f5bb473
JM		 1375 }
1376 if (qp->alt.smac) {
1377 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1378 qp->alt.smac = 0;
1379 }
1380 if (qp->pri.vid < 0x1000) {
1381 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1382 qp->pri.vid = 0xFFFF;
1383 qp->pri.candidate_vid = 0xFFFF;
1384 qp->pri.update_vid = 0;
1385 }
1386 if (qp->alt.vid < 0x1000) {
1387 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1388 qp->alt.vid = 0xFFFF;
1389 qp->alt.candidate_vid = 0xFFFF;
1390 qp->alt.update_vid = 0;
1391 }
1392 }
225c7b1f 1393
400b1ebc 1394 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1395
35f05dab 1396 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1397 mlx4_ib_lock_cqs(send_cq, recv_cq);
1398
35f05dab
YH		 1399 /* del from lists under both locks above to protect reset flow paths */
1400 list_del(&qp->qps_list);
1401 list_del(&qp->cq_send_list);
1402 list_del(&qp->cq_recv_list);
bdeacabd 1403 if (!udata) {
225c7b1f
RD		 1404 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1405 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1406 if (send_cq != recv_cq)
1407 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1408 }
1409
1410 mlx4_qp_remove(dev->dev, &qp->mqp);
1411
1412 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1413 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1414
1415 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1416
c1c98501
MB		 1417 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1418 if (qp->flags & MLX4_IB_QP_NETIF)
1419 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc 1420 else if (src == MLX4_IB_RWQ_SRC)
bdeacabd
SR		 1421 mlx4_ib_release_wqn(
1422 rdma_udata_to_drv_context(
1423 udata,
1424 struct mlx4_ib_ucontext,
1425 ibucontext),
1426 qp, 1);
c1c98501
MB		 1427 else
1428 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1429 }
a3cdcbfa 1430
225c7b1f
RD		 1431 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1432
bdeacabd 1433 if (udata) {
400b1ebc 1434 if (qp->rq.wqe_cnt) {
bdeacabd
SR		 1435 struct mlx4_ib_ucontext *mcontext =
1436 rdma_udata_to_drv_context(
1437 udata,
1438 struct mlx4_ib_ucontext,
1439 ibucontext);
1440
400b1ebc
GL		 1441 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1442 }
225c7b1f 1443 } else {
0ef2f05c
WW		 1444 kvfree(qp->sq.wrid);
1445 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1446 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1447 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1448 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1449 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1450 if (qp->rq.wqe_cnt)
6296883c 1451 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1452 }
836a0fbb 1453 ib_umem_release(qp->umem);
fa417f7b
EC		 1454
1455 del_gid_entries(qp);
225c7b1f
RD		 1456}
1457
47605df9
JM		 1458static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1459{
1460 /* Native or PPF */
1461 if (!mlx4_is_mfunc(dev->dev) ||
1462 (mlx4_is_master(dev->dev) &&
1463 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1464 return dev->dev->phys_caps.base_sqpn +
1465 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1466 attr->port_num - 1;
1467 }
1468 /* PF or VF -- creating proxies */
1469 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1470 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1471 else
c73c8b1e 1472 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1473}
1474
8fd3cd2a
LR		 1475static int _mlx4_ib_create_qp(struct ib_pd *pd, struct mlx4_ib_qp *qp,
1476 struct ib_qp_init_attr *init_attr,
1477 struct ib_udata *udata)
225c7b1f 1478{
225c7b1f 1479 int err;
fbfb6625 1480 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1481 u16 xrcdn = 0;
225c7b1f 1482
3078f5f1 1483 if (init_attr->rwq_ind_tbl)
8fd3cd2a 1484 return _mlx4_ib_create_qp_rss(pd, qp, init_attr, udata);
3078f5f1 1485
521e575b 1486 /*
1ffeb2eb
JM		 1487 * We only support LSO, vendor flag1, and multicast loopback blocking,
1488 * and only for kernel UD QPs.
521e575b 1489 */
1ffeb2eb
JM		 1490 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1491 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1492 MLX4_IB_SRIOV_TUNNEL_QP |
1493 MLX4_IB_SRIOV_SQP |
40f2287b 1494 MLX4_IB_QP_NETIF |
8900b894 1495 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
8fd3cd2a 1496 return -EINVAL;
521e575b 1497
c1c98501
MB		 1498 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1499 if (init_attr->qp_type != IB_QPT_UD)
8fd3cd2a 1500 return -EINVAL;
c1c98501
MB		 1501 }
1502
e1b866c6
MS		 1503 if (init_attr->create_flags) {
1504 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
8fd3cd2a 1505 return -EINVAL;
e1b866c6
MS		 1506
1507 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1508 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1509 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1510 init_attr->qp_type != IB_QPT_UD) ||
1511 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1512 init_attr->qp_type > IB_QPT_GSI) ||
1513 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1514 init_attr->qp_type != IB_QPT_GSI))
8fd3cd2a 1515 return -EINVAL;
e1b866c6 1516 }
b846f25a 1517
225c7b1f 1518 switch (init_attr->qp_type) {
0a1405da
SH		 1519 case IB_QPT_XRC_TGT:
1520 pd = to_mxrcd(init_attr->xrcd)->pd;
1521 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1522 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
df561f66 1523 fallthrough;
0a1405da
SH		 1524 case IB_QPT_XRC_INI:
1525 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
8fd3cd2a 1526 return -ENOSYS;
0a1405da 1527 init_attr->recv_cq = init_attr->send_cq;
df561f66 1528 fallthrough;
225c7b1f
RD		 1529 case IB_QPT_RC:
1530 case IB_QPT_UC:
3987a2d3 1531 case IB_QPT_RAW_PACKET:
8fd3cd2a 1532 case IB_QPT_UD:
2f5bb473
JM		 1533 qp->pri.vid = 0xFFFF;
1534 qp->alt.vid = 0xFFFF;
8fd3cd2a
LR		 1535 err = create_qp_common(pd, init_attr, udata, 0, qp);
1536 if (err)
1537 return err;
225c7b1f
RD		 1538
1539 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1540 qp->xrcdn = xrcdn;
225c7b1f 1541 break;
225c7b1f
RD		 1542 case IB_QPT_SMI:
1543 case IB_QPT_GSI:
1544 {
e1b866c6
MS		 1545 int sqpn;
1546
e1b866c6 1547 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1548 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1549 1, 1, &sqpn, 0,
1550 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1551
1552 if (res)
8fd3cd2a 1553 return res;
e1b866c6
MS		 1554 } else {
1555 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1556 }
225c7b1f 1557
8fd3cd2a
LR		 1558 qp->pri.vid = 0xFFFF;
1559 qp->alt.vid = 0xFFFF;
1560 err = create_qp_common(pd, init_attr, udata, sqpn, qp);
1ffeb2eb 1561 if (err)
8fd3cd2a 1562 return err;
225c7b1f
RD		 1563
1564 qp->port = init_attr->port_num;
e1b866c6
MS		 1565 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1566 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1567 break;
1568 }
1569 default:
1570 /* Don't support raw QPs */
8fd3cd2a 1571 return -EOPNOTSUPP;
225c7b1f 1572 }
8fd3cd2a 1573 return 0;
225c7b1f
RD		 1574}
1575
e1b866c6
MS		 1576struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1577 struct ib_qp_init_attr *init_attr,
1578 struct ib_udata *udata) {
1579 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
e1b866c6 1580 struct mlx4_ib_dev *dev = to_mdev(device);
8fd3cd2a
LR		 1581 struct mlx4_ib_qp *qp;
1582 int ret;
1583
1584 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1585 if (!qp)
1586 return ERR_PTR(-ENOMEM);
e1b866c6 1587
8fd3cd2a
LR		 1588 mutex_init(&qp->mutex);
1589 ret = _mlx4_ib_create_qp(pd, qp, init_attr, udata);
1590 if (ret) {
1591 kfree(qp);
1592 return ERR_PTR(ret);
1593 }
e1b866c6 1594
8fd3cd2a 1595 if (init_attr->qp_type == IB_QPT_GSI &&
e1b866c6 1596 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
915ec7ed 1597 struct mlx4_ib_sqp *sqp = qp->sqp;
e1b866c6
MS		 1598 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1599
1600 if (is_eth &&
1601 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1602 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1603 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1604
1605 if (IS_ERR(sqp->roce_v2_gsi)) {
1606 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1607 sqp->roce_v2_gsi = NULL;
1608 } else {
915ec7ed
LR		 1609 to_mqp(sqp->roce_v2_gsi)->flags |=
1610 MLX4_IB_ROCE_V2_GSI_QP;
e1b866c6
MS		 1611 }
1612
1613 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1614 }
1615 }
8fd3cd2a 1616 return &qp->ibqp;
e1b866c6
MS		 1617}
1618
bdeacabd 1619static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
225c7b1f
RD		 1620{
1621 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1622 struct mlx4_ib_qp *mqp = to_mqp(qp);
1623
1624 if (is_qp0(dev, mqp))
1625 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1626
c482af64
JM		 1627 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1628 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1629 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1630 dev->qp1_proxy[mqp->port - 1] = NULL;
1631 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1632 }
1633
7b59f0f9
EBE		 1634 if (mqp->counter_index)
1635 mlx4_ib_free_qp_counter(dev, mqp);
1636
3078f5f1
GL		 1637 if (qp->rwq_ind_tbl) {
1638 destroy_qp_rss(dev, mqp);
1639 } else {
bdeacabd 1640 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata);
3078f5f1 1641 }
225c7b1f 1642
8fd3cd2a 1643 kfree(mqp->sqp);
915ec7ed 1644 kfree(mqp);
225c7b1f
RD		 1645
1646 return 0;
1647}
1648
c4367a26 1649int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
e1b866c6
MS		 1650{
1651 struct mlx4_ib_qp *mqp = to_mqp(qp);
1652
1653 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
915ec7ed 1654 struct mlx4_ib_sqp *sqp = mqp->sqp;
e1b866c6
MS		 1655
1656 if (sqp->roce_v2_gsi)
1657 ib_destroy_qp(sqp->roce_v2_gsi);
1658 }
1659
bdeacabd 1660 return _mlx4_ib_destroy_qp(qp, udata);
e1b866c6
MS		 1661}
1662
1ffeb2eb 1663static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1664{
1665 switch (type) {
1ffeb2eb
JM		 1666 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1667 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1668 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1669 case MLX4_IB_QPT_XRC_INI:
1670 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1671 case MLX4_IB_QPT_SMI:
1672 case MLX4_IB_QPT_GSI:
1673 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1674
1675 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1676 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1677 MLX4_QP_ST_MLX : -1);
1678 case MLX4_IB_QPT_PROXY_SMI:
1679 case MLX4_IB_QPT_TUN_SMI:
1680 case MLX4_IB_QPT_PROXY_GSI:
1681 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1682 MLX4_QP_ST_UD : -1);
1683 default: return -1;
225c7b1f
RD		 1684 }
1685}
1686
65adfa91 1687static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1688 int attr_mask)
1689{
1690 u8 dest_rd_atomic;
1691 u32 access_flags;
1692 u32 hw_access_flags = 0;
1693
1694 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1695 dest_rd_atomic = attr->max_dest_rd_atomic;
1696 else
1697 dest_rd_atomic = qp->resp_depth;
1698
1699 if (attr_mask & IB_QP_ACCESS_FLAGS)
1700 access_flags = attr->qp_access_flags;
1701 else
1702 access_flags = qp->atomic_rd_en;
1703
1704 if (!dest_rd_atomic)
1705 access_flags &= IB_ACCESS_REMOTE_WRITE;
1706
1707 if (access_flags & IB_ACCESS_REMOTE_READ)
1708 hw_access_flags |= MLX4_QP_BIT_RRE;
1709 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1710 hw_access_flags |= MLX4_QP_BIT_RAE;
1711 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1712 hw_access_flags |= MLX4_QP_BIT_RWE;
1713
1714 return cpu_to_be32(hw_access_flags);
1715}
1716
65adfa91 1717static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1718 int attr_mask)
1719{
1720 if (attr_mask & IB_QP_PKEY_INDEX)
1721 sqp->pkey_index = attr->pkey_index;
1722 if (attr_mask & IB_QP_QKEY)
1723 sqp->qkey = attr->qkey;
1724 if (attr_mask & IB_QP_SQ_PSN)
1725 sqp->send_psn = attr->sq_psn;
1726}
1727
1728static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1729{
1730 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1731}
1732
90898850
DC		 1733static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1734 const struct rdma_ah_attr *ah,
297e0dad 1735 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1736 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1737{
4c3eb3ca 1738 int vidx;
297e0dad 1739 int smac_index;
2f5bb473 1740 int err;
297e0dad 1741
d8966fcd
DC		 1742 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1743 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1744 if (rdma_ah_get_static_rate(ah)) {
1745 path->static_rate = rdma_ah_get_static_rate(ah) +
1746 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1747 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1748 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1749 --path->static_rate;
1750 } else
1751 path->static_rate = 0;
225c7b1f 1752
d8966fcd
DC		 1753 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1754 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1755 int real_sgid_index =
7492052a 1756 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
5070cd22 1757
54a6d63f
DC		 1758 if (real_sgid_index < 0)
1759 return real_sgid_index;
5070cd22 1760 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1761 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1762 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1763 return -1;
1764 }
1765
1766 path->grh_mylmc |= 1 << 7;
5070cd22 1767 path->mgid_index = real_sgid_index;
d8966fcd 1768 path->hop_limit = grh->hop_limit;
225c7b1f 1769 path->tclass_flowlabel =
d8966fcd
DC		 1770 cpu_to_be32((grh->traffic_class << 20) |
1771 (grh->flow_label));
1772 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1773 }
1774
44c58487 1775 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1776 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1777 return -1;
1778
2f5bb473 1779 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1780 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1781
297e0dad 1782 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1783 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1784 if (smac_info->vid < 0x1000) {
1785 /* both valid vlan ids */
1786 if (smac_info->vid != vlan_tag) {
1787 /* different VIDs. unreg old and reg new */
1788 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1789 if (err)
1790 return err;
1791 smac_info->candidate_vid = vlan_tag;
1792 smac_info->candidate_vlan_index = vidx;
1793 smac_info->candidate_vlan_port = port;
1794 smac_info->update_vid = 1;
1795 path->vlan_index = vidx;
1796 } else {
1797 path->vlan_index = smac_info->vlan_index;
1798 }
1799 } else {
1800 /* no current vlan tag in qp */
1801 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1802 if (err)
1803 return err;
1804 smac_info->candidate_vid = vlan_tag;
1805 smac_info->candidate_vlan_index = vidx;
1806 smac_info->candidate_vlan_port = port;
1807 smac_info->update_vid = 1;
1808 path->vlan_index = vidx;
1809 }
297e0dad 1810 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1811 path->fl = 1 << 6;
1812 } else {
1813 /* have current vlan tag. unregister it at modify-qp success */
1814 if (smac_info->vid < 0x1000) {
1815 smac_info->candidate_vid = 0xFFFF;
1816 smac_info->update_vid = 1;
1817 }
4c3eb3ca 1818 }
2f5bb473
JM		 1819
1820 /* get smac_index for RoCE use.
1821 * If no smac was yet assigned, register one.
1822 * If one was already assigned, but the new mac differs,
1823 * unregister the old one and register the new one.
1824 */
25476b02
JM		 1825 if ((!smac_info->smac && !smac_info->smac_port) ||
1826 smac_info->smac != smac) {
2f5bb473
JM		 1827 /* register candidate now, unreg if needed, after success */
1828 smac_index = mlx4_register_mac(dev->dev, port, smac);
1829 if (smac_index >= 0) {
1830 smac_info->candidate_smac_index = smac_index;
1831 smac_info->candidate_smac = smac;
1832 smac_info->candidate_smac_port = port;
1833 } else {
1834 return -EINVAL;
1835 }
1836 } else {
1837 smac_index = smac_info->smac_index;
1838 }
44c58487 1839 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1840 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1841 /* put MAC table smac index for IBoE */
1842 path->grh_mylmc = (u8) (smac_index) | 0x80;
1843 } else {
4c3eb3ca 1844 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1845 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1846 }
fa417f7b 1847
225c7b1f
RD		 1848 return 0;
1849}
1850
297e0dad
MS		 1851static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1852 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1853 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1854 struct mlx4_qp_path *path, u8 port,
1855 u16 vlan_id, u8 *smac)
297e0dad
MS		 1856{
1857 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1858 mlx4_mac_to_u64(smac),
1859 vlan_id,
2f5bb473 1860 path, &mqp->pri, port);
297e0dad
MS		 1861}
1862
1863static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1864 const struct ib_qp_attr *qp,
1865 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1866 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1867 struct mlx4_qp_path *path, u8 port)
1868{
1869 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1870 0,
1871 0xffff,
2f5bb473 1872 path, &mqp->alt, port);
297e0dad
MS		 1873}
1874
fa417f7b
EC		 1875static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1876{
1877 struct mlx4_ib_gid_entry *ge, *tmp;
1878
1879 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1880 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1881 ge->added = 1;
1882 ge->port = qp->port;
1883 }
1884 }
1885}
1886
dbf727de
MB		 1887static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1888 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1889 struct mlx4_qp_context *context)
1890{
2f5bb473
JM		 1891 u64 u64_mac;
1892 int smac_index;
1893
3e0629cb 1894 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1895
1896 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1897 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1898 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1899 if (smac_index >= 0) {
1900 qp->pri.candidate_smac_index = smac_index;
1901 qp->pri.candidate_smac = u64_mac;
1902 qp->pri.candidate_smac_port = qp->port;
1903 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1904 } else {
1905 return -ENOENT;
1906 }
1907 }
1908 return 0;
1909}
1910
7b59f0f9
EBE		 1911static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1912{
1913 struct counter_index *new_counter_index;
1914 int err;
1915 u32 tmp_idx;
1916
1917 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1918 IB_LINK_LAYER_ETHERNET ||
1919 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1920 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1921 return 0;
1922
f3301870 1923 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1924 if (err)
1925 return err;
1926
1927 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1928 if (!new_counter_index) {
1929 mlx4_counter_free(dev->dev, tmp_idx);
1930 return -ENOMEM;
1931 }
1932
1933 new_counter_index->index = tmp_idx;
1934 new_counter_index->allocated = 1;
1935 qp->counter_index = new_counter_index;
1936
1937 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1938 list_add_tail(&new_counter_index->list,
1939 &dev->counters_table[qp->port - 1].counters_list);
1940 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1941
1942 return 0;
1943}
1944
3b5daf28
MS		 1945enum {
1946 MLX4_QPC_ROCE_MODE_1 = 0,
1947 MLX4_QPC_ROCE_MODE_2 = 2,
1948 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1949};
1950
1951static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1952{
1953 switch (gid_type) {
1954 case IB_GID_TYPE_ROCE:
1955 return MLX4_QPC_ROCE_MODE_1;
1956 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1957 return MLX4_QPC_ROCE_MODE_2;
1958 default:
1959 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1960 }
1961}
1962
3078f5f1
GL		 1963/*
1964 * Go over all RSS QP's childes (WQs) and apply their HW state according to
1965 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
1966 */
89944450
SR		 1967static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num,
1968 struct ib_udata *udata)
3078f5f1 1969{
fba02e6c 1970 int err = 0;
3078f5f1 1971 int i;
3078f5f1
GL		 1972
1973 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
1974 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
1975 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1976
1977 mutex_lock(&wq->mutex);
1978
1979 /* Mlx4_ib restrictions:
1980 * WQ's is associated to a port according to the RSS QP it is
1981 * associates to.
1982 * In case the WQ is associated to a different port by another
1983 * RSS QP, return a failure.
1984 */
1985 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
1986 err = -EINVAL;
1987 mutex_unlock(&wq->mutex);
1988 break;
1989 }
1990 wq->port = port_num;
1991 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
89944450 1992 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata);
3078f5f1
GL		 1993 if (err) {
1994 mutex_unlock(&wq->mutex);
1995 break;
1996 }
1997 }
1998 wq->rss_usecnt++;
1999
2000 mutex_unlock(&wq->mutex);
2001 }
2002
2003 if (i && err) {
2004 int j;
2005
2006 for (j = (i - 1); j >= 0; j--) {
2007 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2008 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2009
2010 mutex_lock(&wq->mutex);
2011
2012 if ((wq->rss_usecnt == 1) &&
2013 (ibwq->state == IB_WQS_RDY))
89944450
SR		 2014 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET,
2015 udata))
3078f5f1
GL		 2016 pr_warn("failed to reverse WQN=0x%06x\n",
2017 ibwq->wq_num);
2018 wq->rss_usecnt--;
2019
2020 mutex_unlock(&wq->mutex);
2021 }
2022 }
2023
2024 return err;
2025}
2026
89944450
SR		 2027static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl,
2028 struct ib_udata *udata)
3078f5f1
GL		 2029{
2030 int i;
2031
2032 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2033 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2034 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2035
2036 mutex_lock(&wq->mutex);
2037
2038 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
89944450 2039 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata))
3078f5f1
GL		 2040 pr_warn("failed to reverse WQN=%x\n",
2041 ibwq->wq_num);
2042 wq->rss_usecnt--;
2043
2044 mutex_unlock(&wq->mutex);
2045 }
2046}
2047
2048static void fill_qp_rss_context(struct mlx4_qp_context *context,
2049 struct mlx4_ib_qp *qp)
2050{
2051 struct mlx4_rss_context *rss_context;
2052
2053 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2054 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2055
2056 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2057 rss_context->default_qpn =
2058 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2059 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2060 rss_context->base_qpn_udp = rss_context->default_qpn;
2061 rss_context->flags = qp->rss_ctx->flags;
2062 /* Currently support just toeplitz */
2063 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2064
2065 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2066 MLX4_EN_RSS_KEY_SIZE);
2067}
2068
400b1ebc 2069static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91 2070 const struct ib_qp_attr *attr, int attr_mask,
89944450
SR		 2071 enum ib_qp_state cur_state,
2072 enum ib_qp_state new_state,
2073 struct ib_udata *udata)
225c7b1f 2074{
400b1ebc 2075 struct ib_srq *ibsrq;
47ec3866 2076 const struct ib_gid_attr *gid_attr = NULL;
3078f5f1 2077 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2078 enum ib_qp_type qp_type;
2079 struct mlx4_ib_dev *dev;
2080 struct mlx4_ib_qp *qp;
0a1405da
SH		 2081 struct mlx4_ib_pd *pd;
2082 struct mlx4_ib_cq *send_cq, *recv_cq;
89944450
SR		 2083 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2084 udata, struct mlx4_ib_ucontext, ibucontext);
225c7b1f
RD		 2085 struct mlx4_qp_context *context;
2086 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2087 int sqd_event;
c1c98501 2088 int steer_qp = 0;
225c7b1f 2089 int err = -EINVAL;
3ba8e31d 2090 int counter_index;
225c7b1f 2091
400b1ebc
GL		 2092 if (src_type == MLX4_IB_RWQ_SRC) {
2093 struct ib_wq *ibwq;
2094
3078f5f1 2095 ibwq = (struct ib_wq *)src;
3078f5f1
GL		 2096 ibsrq = NULL;
2097 rwq_ind_tbl = NULL;
2098 qp_type = IB_QPT_RAW_PACKET;
2099 qp = to_mqp((struct ib_qp *)ibwq);
2100 dev = to_mdev(ibwq->device);
2101 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2102 } else {
2103 struct ib_qp *ibqp;
2104
3078f5f1 2105 ibqp = (struct ib_qp *)src;
3078f5f1
GL		 2106 ibsrq = ibqp->srq;
2107 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2108 qp_type = ibqp->qp_type;
2109 qp = to_mqp(ibqp);
2110 dev = to_mdev(ibqp->device);
2111 pd = get_pd(qp);
400b1ebc
GL		 2112 }
2113
3dec4878
JM		 2114 /* APM is not supported under RoCE */
2115 if (attr_mask & IB_QP_ALT_PATH &&
2116 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2117 IB_LINK_LAYER_ETHERNET)
2118 return -ENOTSUPP;
2119
225c7b1f
RD		 2120 context = kzalloc(sizeof *context, GFP_KERNEL);
2121 if (!context)
2122 return -ENOMEM;
2123
225c7b1f 2124 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2125 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2126
2127 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2128 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2129 else {
2130 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2131 switch (attr->path_mig_state) {
2132 case IB_MIG_MIGRATED:
2133 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2134 break;
2135 case IB_MIG_REARM:
2136 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2137 break;
2138 case IB_MIG_ARMED:
2139 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2140 break;
2141 }
2142 }
2143
ea30b966
MG		 2144 if (qp->inl_recv_sz)
2145 context->param3 |= cpu_to_be32(1 << 25);
2146
6d06c9aa
GL		 2147 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2148 context->param3 |= cpu_to_be32(1 << 29);
2149
400b1ebc 2150 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2151 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2152 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2153 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2154 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2155 if (qp->flags & MLX4_IB_QP_LSO)
2156 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2157 ilog2(dev->dev->caps.max_gso_sz);
2158 else
5f22a1d8 2159 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2160 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2161 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2162 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2163 attr->path_mtu);
f5b40431 2164 goto out;
225c7b1f 2165 }
d1f2cd89
EC		 2166 context->mtu_msgmax = (attr->path_mtu << 5) |
2167 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2168 }
2169
3078f5f1
GL		 2170 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2171 if (qp->rq.wqe_cnt)
2172 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2173 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2174 }
225c7b1f 2175
0e6e7416
RD		 2176 if (qp->sq.wqe_cnt)
2177 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2178 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2179
7b59f0f9
EBE		 2180 if (new_state == IB_QPS_RESET && qp->counter_index)
2181 mlx4_ib_free_qp_counter(dev, qp);
2182
0a1405da 2183 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2184 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2185 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2186 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2187 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2188 }
0e6e7416 2189
89944450 2190 if (ucontext)
85743f1e 2191 context->usr_page = cpu_to_be32(
89944450 2192 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index));
225c7b1f 2193 else
85743f1e
HN		 2194 context->usr_page = cpu_to_be32(
2195 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2196
2197 if (attr_mask & IB_QP_DEST_QPN)
2198 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2199
2200 if (attr_mask & IB_QP_PORT) {
2201 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2202 !(attr_mask & IB_QP_AV)) {
2203 mlx4_set_sched(&context->pri_path, attr->port_num);
2204 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2205 }
2206 }
2207
cfcde11c 2208 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2209 err = create_qp_lb_counter(dev, qp);
2210 if (err)
2211 goto out;
2212
3ba8e31d
EBE		 2213 counter_index =
2214 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2215 if (qp->counter_index)
2216 counter_index = qp->counter_index->index;
2217
3ba8e31d
EBE		 2218 if (counter_index != -1) {
2219 context->pri_path.counter_index = counter_index;
cfcde11c 2220 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2221 if (qp->counter_index) {
2222 context->pri_path.fl |=
2223 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2224 context->pri_path.vlan_control |=
2225 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2226 }
cfcde11c 2227 } else
47d8417f
EBE		 2228 context->pri_path.counter_index =
2229 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2230
2231 if (qp->flags & MLX4_IB_QP_NETIF) {
2232 mlx4_ib_steer_qp_reg(dev, qp, 1);
2233 steer_qp = 1;
2234 }
e1b866c6 2235
400b1ebc 2236 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2237 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2238 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2239 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2240
2241 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2242 }
cfcde11c
OG		 2243 }
2244
225c7b1f 2245 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2246 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2247 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2248 context->pri_path.pkey_index = attr->pkey_index;
2249 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2250 }
2251
225c7b1f 2252 if (attr_mask & IB_QP_AV) {
400b1ebc 2253 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de 2254 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
dbf727de
MB		 2255 u16 vlan = 0xffff;
2256 u8 smac[ETH_ALEN];
d8966fcd
DC		 2257 int is_eth =
2258 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2259 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2260
d8966fcd 2261 if (is_eth) {
47ec3866 2262 gid_attr = attr->ah_attr.grh.sgid_attr;
a70c0739
PP		 2263 err = rdma_read_gid_l2_fields(gid_attr, &vlan,
2264 &smac[0]);
2265 if (err)
2266 goto out;
dbf727de 2267 }
dbf727de 2268
2f5bb473 2269 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2270 port_num, vlan, smac))
225c7b1f 2271 goto out;
225c7b1f
RD		 2272
2273 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2274 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2275
2276 if (is_eth &&
2277 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
47ec3866 2278 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
3b5daf28
MS		 2279
2280 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2281 err = -EINVAL;
2282 goto out;
2283 }
2284 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2285 }
2286
225c7b1f
RD		 2287 }
2288
2289 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2290 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2291 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2292 }
2293
2294 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2295 if (attr->alt_port_num == 0 ||
2296 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2297 goto out;
225c7b1f 2298
5ae2a7a8
RD		 2299 if (attr->alt_pkey_index >=
2300 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2301 goto out;
5ae2a7a8 2302
2f5bb473
JM		 2303 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2304 &context->alt_path,
297e0dad 2305 attr->alt_port_num))
f5b40431 2306 goto out;
225c7b1f
RD		 2307
2308 context->alt_path.pkey_index = attr->alt_pkey_index;
2309 context->alt_path.ackto = attr->alt_timeout << 3;
2310 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2311 }
2312
3078f5f1
GL		 2313 context->pd = cpu_to_be32(pd->pdn);
2314
2315 if (!rwq_ind_tbl) {
108809a0 2316 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2317 get_cqs(qp, src_type, &send_cq, &recv_cq);
2318 } else { /* Set dummy CQs to be compatible with HV and PRM */
2319 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2320 recv_cq = send_cq;
2321 }
0a1405da
SH		 2322 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2323 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2324
95d04f07 2325 /* Set "fast registration enabled" for all kernel QPs */
89944450 2326 if (!ucontext)
95d04f07
RD		 2327 context->params1 |= cpu_to_be32(1 << 11);
2328
57f01b53
JM		 2329 if (attr_mask & IB_QP_RNR_RETRY) {
2330 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2331 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2332 }
2333
225c7b1f
RD		 2334 if (attr_mask & IB_QP_RETRY_CNT) {
2335 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2336 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2337 }
2338
2339 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2340 if (attr->max_rd_atomic)
2341 context->params1 |=
2342 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2343 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2344 }
2345
2346 if (attr_mask & IB_QP_SQ_PSN)
2347 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2348
225c7b1f
RD		 2349 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2350 if (attr->max_dest_rd_atomic)
2351 context->params2 |=
2352 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2353 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2354 }
2355
2356 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2357 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2358 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2359 }
2360
400b1ebc 2361 if (ibsrq)
225c7b1f
RD		 2362 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2363
2364 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2365 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2366 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2367 }
2368 if (attr_mask & IB_QP_RQ_PSN)
2369 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2370
1ffeb2eb 2371 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2372 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2373 if (qp->mlx4_ib_qp_type &
2374 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2375 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2376 else {
2377 if (mlx4_is_mfunc(dev->dev) &&
2378 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2379 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2380 MLX4_RESERVED_QKEY_BASE) {
2381 pr_err("Cannot use reserved QKEY"
2382 " 0x%x (range 0xffff0000..0xffffffff"
2383 " is reserved)\n", attr->qkey);
2384 err = -EINVAL;
2385 goto out;
2386 }
2387 context->qkey = cpu_to_be32(attr->qkey);
2388 }
225c7b1f
RD		 2389 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2390 }
2391
400b1ebc
GL		 2392 if (ibsrq)
2393 context->srqn = cpu_to_be32(1 << 24 |
2394 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2395
400b1ebc
GL		 2396 if (qp->rq.wqe_cnt &&
2397 cur_state == IB_QPS_RESET &&
2398 new_state == IB_QPS_INIT)
225c7b1f
RD		 2399 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2400
2401 if (cur_state == IB_QPS_INIT &&
2402 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2403 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2404 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2405 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2406 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2407 qp->mlx4_ib_qp_type &
2408 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2409 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2410 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2411 context->pri_path.fl = 0x80;
2412 } else {
2413 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2414 context->pri_path.fl = 0x80;
225c7b1f 2415 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2416 }
2f5bb473
JM		 2417 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2418 IB_LINK_LAYER_ETHERNET) {
2419 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2420 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2421 context->pri_path.feup = 1 << 7; /* don't fsm */
2422 /* handle smac_index */
2423 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2424 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2425 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2426 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2427 if (err) {
2428 err = -EINVAL;
2429 goto out;
2430 }
9433c188
MB		 2431 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2432 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2433 }
2434 }
225c7b1f
RD		 2435 }
2436
400b1ebc 2437 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2438 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2439 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2440 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2441 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2442 if (!rwq_ind_tbl)
d2fce8a9
OG		 2443 context->srqn = cpu_to_be32(7 << 28);
2444 }
2445 }
3528f696 2446
400b1ebc 2447 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2448 int is_eth = rdma_port_get_link_layer(
2449 &dev->ib_dev, qp->port) ==
2450 IB_LINK_LAYER_ETHERNET;
2451 if (is_eth) {
2452 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2453 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2454 }
2455 }
2456
225c7b1f
RD		 2457 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2458 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2459 sqd_event = 1;
2460 else
2461 sqd_event = 0;
2462
89944450 2463 if (!ucontext &&
400b1ebc
GL		 2464 cur_state == IB_QPS_RESET &&
2465 new_state == IB_QPS_INIT)
3b5daf28 2466 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2467
c0be5fb5
EC		 2468 /*
2469 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2470 * ownership bits of the send queue are set and the SQ
2471 * headroom is stamped so that the hardware doesn't start
2472 * processing stale work requests.
c0be5fb5 2473 */
89944450 2474 if (!ucontext &&
400b1ebc
GL		 2475 cur_state == IB_QPS_RESET &&
2476 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2477 struct mlx4_wqe_ctrl_seg *ctrl;
2478 int i;
2479
0e6e7416 2480 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2481 ctrl = get_send_wqe(qp, i);
2482 ctrl->owner_opcode = cpu_to_be32(1 << 31);
f95ccffc
JM		 2483 ctrl->qpn_vlan.fence_size =
2484 1 << (qp->sq.wqe_shift - 4);
2485 stamp_send_wqe(qp, i);
c0be5fb5
EC		 2486 }
2487 }
2488
108809a0
GL		 2489 if (rwq_ind_tbl &&
2490 cur_state == IB_QPS_RESET &&
2491 new_state == IB_QPS_INIT) {
2492 fill_qp_rss_context(context, qp);
2493 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2494 }
2495
225c7b1f
RD		 2496 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2497 to_mlx4_state(new_state), context, optpar,
2498 sqd_event, &qp->mqp);
2499 if (err)
2500 goto out;
2501
2502 qp->state = new_state;
2503
2504 if (attr_mask & IB_QP_ACCESS_FLAGS)
2505 qp->atomic_rd_en = attr->qp_access_flags;
2506 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2507 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2508 if (attr_mask & IB_QP_PORT) {
225c7b1f 2509 qp->port = attr->port_num;
fa417f7b
EC		 2510 update_mcg_macs(dev, qp);
2511 }
225c7b1f
RD		 2512 if (attr_mask & IB_QP_ALT_PATH)
2513 qp->alt_port = attr->alt_port_num;
2514
2515 if (is_sqp(dev, qp))
915ec7ed 2516 store_sqp_attrs(qp->sqp, attr, attr_mask);
225c7b1f
RD		 2517
2518 /*
2519 * If we moved QP0 to RTR, bring the IB link up; if we moved
2520 * QP0 to RESET or ERROR, bring the link back down.
2521 */
2522 if (is_qp0(dev, qp)) {
2523 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2524 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2525 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2526 qp->port);
225c7b1f
RD		 2527
2528 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2529 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2530 mlx4_CLOSE_PORT(dev->dev, qp->port);
2531 }
2532
2533 /*
2534 * If we moved a kernel QP to RESET, clean up all old CQ
2535 * entries and reinitialize the QP.
2536 */
2f5bb473 2537 if (new_state == IB_QPS_RESET) {
89944450 2538 if (!ucontext) {
2f5bb473 2539 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2540 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2541 if (send_cq != recv_cq)
2542 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2543
2544 qp->rq.head = 0;
2545 qp->rq.tail = 0;
2546 qp->sq.head = 0;
2547 qp->sq.tail = 0;
2548 qp->sq_next_wqe = 0;
2549 if (qp->rq.wqe_cnt)
2550 *qp->db.db = 0;
225c7b1f 2551
2f5bb473
JM		 2552 if (qp->flags & MLX4_IB_QP_NETIF)
2553 mlx4_ib_steer_qp_reg(dev, qp, 0);
2554 }
25476b02 2555 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2556 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2557 qp->pri.smac = 0;
25476b02 2558 qp->pri.smac_port = 0;
2f5bb473
JM		 2559 }
2560 if (qp->alt.smac) {
2561 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2562 qp->alt.smac = 0;
2563 }
2564 if (qp->pri.vid < 0x1000) {
2565 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2566 qp->pri.vid = 0xFFFF;
2567 qp->pri.candidate_vid = 0xFFFF;
2568 qp->pri.update_vid = 0;
2569 }
c1c98501 2570
2f5bb473
JM		 2571 if (qp->alt.vid < 0x1000) {
2572 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2573 qp->alt.vid = 0xFFFF;
2574 qp->alt.candidate_vid = 0xFFFF;
2575 qp->alt.update_vid = 0;
2576 }
225c7b1f 2577 }
225c7b1f 2578out:
7b59f0f9
EBE		 2579 if (err && qp->counter_index)
2580 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2581 if (err && steer_qp)
2582 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2583 kfree(context);
25476b02
JM		 2584 if (qp->pri.candidate_smac ||
2585 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2586 if (err) {
2587 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2588 } else {
25476b02 2589 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2590 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2591 qp->pri.smac = qp->pri.candidate_smac;
2592 qp->pri.smac_index = qp->pri.candidate_smac_index;
2593 qp->pri.smac_port = qp->pri.candidate_smac_port;
2594 }
2595 qp->pri.candidate_smac = 0;
2596 qp->pri.candidate_smac_index = 0;
2597 qp->pri.candidate_smac_port = 0;
2598 }
2599 if (qp->alt.candidate_smac) {
2600 if (err) {
2601 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2602 } else {
2603 if (qp->alt.smac)
2604 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2605 qp->alt.smac = qp->alt.candidate_smac;
2606 qp->alt.smac_index = qp->alt.candidate_smac_index;
2607 qp->alt.smac_port = qp->alt.candidate_smac_port;
2608 }
2609 qp->alt.candidate_smac = 0;
2610 qp->alt.candidate_smac_index = 0;
2611 qp->alt.candidate_smac_port = 0;
2612 }
2613
2614 if (qp->pri.update_vid) {
2615 if (err) {
2616 if (qp->pri.candidate_vid < 0x1000)
2617 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2618 qp->pri.candidate_vid);
2619 } else {
2620 if (qp->pri.vid < 0x1000)
2621 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2622 qp->pri.vid);
2623 qp->pri.vid = qp->pri.candidate_vid;
2624 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2625 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2626 }
2627 qp->pri.candidate_vid = 0xFFFF;
2628 qp->pri.update_vid = 0;
2629 }
2630
2631 if (qp->alt.update_vid) {
2632 if (err) {
2633 if (qp->alt.candidate_vid < 0x1000)
2634 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2635 qp->alt.candidate_vid);
2636 } else {
2637 if (qp->alt.vid < 0x1000)
2638 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2639 qp->alt.vid);
2640 qp->alt.vid = qp->alt.candidate_vid;
2641 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2642 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2643 }
2644 qp->alt.candidate_vid = 0xFFFF;
2645 qp->alt.update_vid = 0;
2646 }
2647
225c7b1f
RD		 2648 return err;
2649}
2650
3078f5f1
GL		 2651enum {
2652 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2653 IB_QP_PORT),
2654};
2655
e1b866c6
MS		 2656static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2657 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2658{
2659 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2660 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2661 enum ib_qp_state cur_state, new_state;
2662 int err = -EINVAL;
65adfa91
MT		 2663 mutex_lock(&qp->mutex);
2664
2665 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2666 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2667
dd5f03be 2668 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
d31131bb 2669 attr_mask)) {
b1d8eb5a
JM		 2670 pr_debug("qpn 0x%x: invalid attribute mask specified "
2671 "for transition %d to %d. qp_type %d,"
2672 " attr_mask 0x%x\n",
2673 ibqp->qp_num, cur_state, new_state,
2674 ibqp->qp_type, attr_mask);
65adfa91 2675 goto out;
b1d8eb5a 2676 }
65adfa91 2677
3078f5f1
GL		 2678 if (ibqp->rwq_ind_tbl) {
2679 if (!(((cur_state == IB_QPS_RESET) &&
2680 (new_state == IB_QPS_INIT)) ||
2681 ((cur_state == IB_QPS_INIT) &&
2682 (new_state == IB_QPS_RTR)))) {
2683 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2684 ibqp->qp_num, cur_state, new_state);
2685
2686 err = -EOPNOTSUPP;
2687 goto out;
2688 }
2689
2690 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2691 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2692 ibqp->qp_num, attr_mask, cur_state, new_state);
2693
2694 err = -EOPNOTSUPP;
2695 goto out;
2696 }
2697 }
2698
c6215745
MS		 2699 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2700 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2701 if ((ibqp->qp_type == IB_QPT_RC) ||
2702 (ibqp->qp_type == IB_QPT_UD) ||
2703 (ibqp->qp_type == IB_QPT_UC) ||
2704 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2705 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2706 attr->port_num = mlx4_ib_bond_next_port(dev);
2707 }
2708 } else {
2709 /* no sense in changing port_num
2710 * when ports are bonded */
2711 attr_mask &= ~IB_QP_PORT;
2712 }
2713 }
2714
65adfa91 2715 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2716 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2717 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2718 "for transition %d to %d. qp_type %d\n",
2719 ibqp->qp_num, attr->port_num, cur_state,
2720 new_state, ibqp->qp_type);
65adfa91
MT		 2721 goto out;
2722 }
2723
3987a2d3
OG		 2724 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2725 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2726 IB_LINK_LAYER_ETHERNET))
2727 goto out;
2728
5ae2a7a8
RD		 2729 if (attr_mask & IB_QP_PKEY_INDEX) {
2730 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2731 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2732 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2733 "for transition %d to %d. qp_type %d\n",
2734 ibqp->qp_num, attr->pkey_index, cur_state,
2735 new_state, ibqp->qp_type);
5ae2a7a8 2736 goto out;
b1d8eb5a 2737 }
5ae2a7a8
RD		 2738 }
2739
65adfa91
MT		 2740 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2741 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2742 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2743 "Transition %d to %d. qp_type %d\n",
2744 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2745 new_state, ibqp->qp_type);
65adfa91
MT		 2746 goto out;
2747 }
2748
2749 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2750 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2751 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2752 "Transition %d to %d. qp_type %d\n",
2753 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2754 new_state, ibqp->qp_type);
65adfa91
MT		 2755 goto out;
2756 }
2757
2758 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2759 err = 0;
2760 goto out;
2761 }
2762
3078f5f1 2763 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
89944450
SR		 2764 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num,
2765 udata);
3078f5f1
GL		 2766 if (err)
2767 goto out;
2768 }
2769
400b1ebc 2770 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
89944450 2771 cur_state, new_state, udata);
65adfa91 2772
3078f5f1 2773 if (ibqp->rwq_ind_tbl && err)
89944450 2774 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata);
3078f5f1 2775
c6215745
MS		 2776 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2777 attr->port_num = 1;
2778
65adfa91
MT		 2779out:
2780 mutex_unlock(&qp->mutex);
2781 return err;
2782}
2783
e1b866c6
MS		 2784int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2785 int attr_mask, struct ib_udata *udata)
2786{
2787 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2788 int ret;
2789
2790 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2791
2792 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
915ec7ed 2793 struct mlx4_ib_sqp *sqp = mqp->sqp;
e1b866c6
MS		 2794 int err = 0;
2795
2796 if (sqp->roce_v2_gsi)
2797 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2798 if (err)
2799 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2800 err);
2801 }
2802 return ret;
2803}
2804
99ec41d0
JM		 2805static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2806{
2807 int i;
2808 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2809 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2810 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2811 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2812 return 0;
2813 }
2814 }
2815 return -EINVAL;
2816}
2817
915ec7ed 2818static int build_sriov_qp0_header(struct mlx4_ib_qp *qp,
f696bf6d 2819 const struct ib_ud_wr *wr,
1ffeb2eb
JM		 2820 void *wqe, unsigned *mlx_seg_len)
2821{
915ec7ed
LR		 2822 struct mlx4_ib_dev *mdev = to_mdev(qp->ibqp.device);
2823 struct mlx4_ib_sqp *sqp = qp->sqp;
2824 struct ib_device *ib_dev = qp->ibqp.device;
1ffeb2eb
JM		 2825 struct mlx4_wqe_mlx_seg *mlx = wqe;
2826 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2827 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2828 u16 pkey;
2829 u32 qkey;
2830 int send_size;
2831 int header_size;
2832 int spc;
6693ca95 2833 int err;
1ffeb2eb
JM		 2834 int i;
2835
e622f2f4 2836 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2837 return -EINVAL;
2838
2839 send_size = 0;
2840
e622f2f4
CH		 2841 for (i = 0; i < wr->wr.num_sge; ++i)
2842 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2843
2844 /* for proxy-qp0 sends, need to add in size of tunnel header */
2845 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
915ec7ed 2846 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1ffeb2eb
JM		 2847 send_size += sizeof (struct mlx4_ib_tunnel_header);
2848
25f40220 2849 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb 2850
915ec7ed 2851 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1ffeb2eb
JM		 2852 sqp->ud_header.lrh.service_level =
2853 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2854 sqp->ud_header.lrh.destination_lid =
2855 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2856 sqp->ud_header.lrh.source_lid =
2857 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2858 }
2859
2860 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2861
2862 /* force loopback */
2863 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2864 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2865
2866 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2867 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
915ec7ed 2868 err = ib_get_cached_pkey(ib_dev, qp->port, 0, &pkey);
6693ca95
JM		 2869 if (err)
2870 return err;
1ffeb2eb 2871 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
915ec7ed 2872 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2873 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2874 else
2875 sqp->ud_header.bth.destination_qpn =
915ec7ed 2876 cpu_to_be32(mdev->dev->caps.spec_qps[qp->port - 1].qp0_tunnel);
1ffeb2eb
JM		 2877
2878 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0 2879 if (mlx4_is_master(mdev->dev)) {
915ec7ed 2880 if (mlx4_get_parav_qkey(mdev->dev, qp->mqp.qpn, &qkey))
99ec41d0
JM		 2881 return -EINVAL;
2882 } else {
915ec7ed 2883 if (vf_get_qp0_qkey(mdev->dev, qp->mqp.qpn, &qkey))
99ec41d0
JM		 2884 return -EINVAL;
2885 }
1ffeb2eb 2886 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
915ec7ed 2887 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->mqp.qpn);
1ffeb2eb
JM		 2888
2889 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2890 sqp->ud_header.immediate_present = 0;
2891
2892 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2893
2894 /*
2895 * Inline data segments may not cross a 64 byte boundary. If
2896 * our UD header is bigger than the space available up to the
2897 * next 64 byte boundary in the WQE, use two inline data
2898 * segments to hold the UD header.
2899 */
2900 spc = MLX4_INLINE_ALIGN -
2901 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2902 if (header_size <= spc) {
2903 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2904 memcpy(inl + 1, sqp->header_buf, header_size);
2905 i = 1;
2906 } else {
2907 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2908 memcpy(inl + 1, sqp->header_buf, spc);
2909
2910 inl = (void *) (inl + 1) + spc;
2911 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2912 /*
2913 * Need a barrier here to make sure all the data is
2914 * visible before the byte_count field is set.
2915 * Otherwise the HCA prefetcher could grab the 64-byte
2916 * chunk with this inline segment and get a valid (!=
2917 * 0xffffffff) byte count but stale data, and end up
2918 * generating a packet with bad headers.
2919 *
2920 * The first inline segment's byte_count field doesn't
2921 * need a barrier, because it comes after a
2922 * control/MLX segment and therefore is at an offset
2923 * of 16 mod 64.
2924 */
2925 wmb();
2926 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2927 i = 2;
2928 }
2929
2930 *mlx_seg_len =
2931 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2932 return 0;
2933}
2934
fd10ed8e
JM		 2935static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2936{
2937 union sl2vl_tbl_to_u64 tmp_vltab;
2938 u8 vl;
2939
2940 if (sl > 15)
2941 return 0xf;
2942 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2943 vl = tmp_vltab.sl8[sl >> 1];
2944 if (sl & 1)
2945 vl &= 0x0f;
2946 else
2947 vl >>= 4;
2948 return vl;
2949}
2950
a748d60d
TB		 2951static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2952 int index, union ib_gid *gid,
2953 enum ib_gid_type *gid_type)
2954{
2955 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2956 struct mlx4_port_gid_table *port_gid_table;
2957 unsigned long flags;
2958
2959 port_gid_table = &iboe->gids[port_num - 1];
2960 spin_lock_irqsave(&iboe->lock, flags);
2961 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2962 *gid_type = port_gid_table->gids[index].gid_type;
2963 spin_unlock_irqrestore(&iboe->lock, flags);
25e62655 2964 if (rdma_is_zero_gid(gid))
a748d60d
TB		 2965 return -ENOENT;
2966
2967 return 0;
2968}
2969
3ef967a4 2970#define MLX4_ROCEV2_QP1_SPORT 0xC000
915ec7ed 2971static int build_mlx_header(struct mlx4_ib_qp *qp, const struct ib_ud_wr *wr,
f438000f 2972 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2973{
915ec7ed
LR		 2974 struct mlx4_ib_sqp *sqp = qp->sqp;
2975 struct ib_device *ib_dev = qp->ibqp.device;
a748d60d 2976 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 2977 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2978 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2979 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2980 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2981 union ib_gid sgid;
225c7b1f
RD		 2982 u16 pkey;
2983 int send_size;
2984 int header_size;
e61ef241 2985 int spc;
225c7b1f 2986 int i;
1ffeb2eb 2987 int err = 0;
57d88cff 2988 u16 vlan = 0xffff;
a29bec12
RD		 2989 bool is_eth;
2990 bool is_vlan = false;
2991 bool is_grh;
3ef967a4
MS		 2992 bool is_udp = false;
2993 int ip_version = 0;
225c7b1f
RD		 2994
2995 send_size = 0;
e622f2f4
CH		 2996 for (i = 0; i < wr->wr.num_sge; ++i)
2997 send_size += wr->wr.sg_list[i].length;
225c7b1f 2998
915ec7ed 2999 is_eth = rdma_port_get_link_layer(qp->ibqp.device, qp->port) == IB_LINK_LAYER_ETHERNET;
fa417f7b 3000 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3001 if (is_eth) {
a748d60d 3002 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3003 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3004 /* When multi-function is enabled, the ib_core gid
3005 * indexes don't necessarily match the hw ones, so
3006 * we must use our own cache */
6ee51a4e
JM		 3007 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3008 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3009 ah->av.ib.gid_index, &sgid.raw[0]);
3010 if (err)
3011 return err;
1ffeb2eb 3012 } else {
915ec7ed
LR		 3013 err = fill_gid_by_hw_index(ibdev, qp->port,
3014 ah->av.ib.gid_index, &sgid,
3015 &gid_type);
3ef967a4 3016 if (!err) {
a748d60d 3017 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3018 if (is_udp) {
3019 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3020 ip_version = 4;
3021 else
3022 ip_version = 6;
3023 is_grh = false;
3024 }
3025 } else {
1ffeb2eb 3026 return err;
3ef967a4 3027 }
1ffeb2eb 3028 }
0e9855db 3029 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad 3030 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
cf368beb 3031 is_vlan = true;
297e0dad 3032 }
4c3eb3ca 3033 }
25f40220 3034 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3035 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3036 if (err)
3037 return err;
fa417f7b
EC		 3038
3039 if (!is_eth) {
3040 sqp->ud_header.lrh.service_level =
3041 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3042 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3043 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3044 }
225c7b1f 3045
3ef967a4 3046 if (is_grh || (ip_version == 6)) {
225c7b1f 3047 sqp->ud_header.grh.traffic_class =
fa417f7b 3048 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3049 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3050 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3051 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3052 if (is_eth) {
6ee51a4e 3053 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3054 } else {
3055 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3056 /* When multi-function is enabled, the ib_core gid
3057 * indexes don't necessarily match the hw ones, so
3058 * we must use our own cache
3059 */
915ec7ed
LR		 3060 sqp->ud_header.grh.source_gid.global
3061 .subnet_prefix =
3062 cpu_to_be64(atomic64_read(
3063 &(to_mdev(ib_dev)
3064 ->sriov
3065 .demux[qp->port - 1]
3066 .subnet_prefix)));
3067 sqp->ud_header.grh.source_gid.global
3068 .interface_id =
3069 to_mdev(ib_dev)
3070 ->sriov.demux[qp->port - 1]
3071 .guid_cache[ah->av.ib.gid_index];
baa0be70 3072 } else {
89af969a
PP		 3073 sqp->ud_header.grh.source_gid =
3074 ah->ibah.sgid_attr->gid;
baa0be70 3075 }
6ee51a4e 3076 }
225c7b1f 3077 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3078 ah->av.ib.dgid, 16);
225c7b1f
RD		 3079 }
3080
3ef967a4
MS		 3081 if (ip_version == 4) {
3082 sqp->ud_header.ip4.tos =
3083 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3084 sqp->ud_header.ip4.id = 0;
3085 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3086 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3087
3088 memcpy(&sqp->ud_header.ip4.saddr,
3089 sgid.raw + 12, 4);
3090 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3091 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3092 }
3093
3094 if (is_udp) {
3095 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3096 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3097 sqp->ud_header.udp.csum = 0;
3098 }
3099
225c7b1f 3100 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3101
3102 if (!is_eth) {
915ec7ed
LR		 3103 mlx->flags |=
3104 cpu_to_be32((!qp->ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3105 (sqp->ud_header.lrh.destination_lid ==
3106 IB_LID_PERMISSIVE ?
3107 MLX4_WQE_MLX_SLR :
3108 0) |
3109 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3110 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3111 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3112 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3113 }
225c7b1f 3114
e622f2f4 3115 switch (wr->wr.opcode) {
225c7b1f
RD		 3116 case IB_WR_SEND:
3117 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3118 sqp->ud_header.immediate_present = 0;
3119 break;
3120 case IB_WR_SEND_WITH_IMM:
3121 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3122 sqp->ud_header.immediate_present = 1;
e622f2f4 3123 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3124 break;
3125 default:
3126 return -EINVAL;
3127 }
3128
fa417f7b 3129 if (is_eth) {
6ee51a4e 3130 struct in6_addr in6;
3ef967a4 3131 u16 ether_type;
c0c1d3d7
OD		 3132 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3133
69ae5439 3134 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3135 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3136
c0c1d3d7 3137 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3138
1049f138 3139 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
fa417f7b 3140 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
6ee51a4e
JM		 3141 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3142 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3143 memcpy(&in6, sgid.raw, sizeof(in6));
5ea8bbfc 3144
3e0629cb 3145
fa417f7b
EC		 3146 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3147 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3148 if (!is_vlan) {
3ef967a4 3149 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3150 } else {
3ef967a4 3151 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3152 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3153 }
fa417f7b 3154 } else {
915ec7ed
LR		 3155 sqp->ud_header.lrh.virtual_lane =
3156 !qp->ibqp.qp_num ?
3157 15 :
3158 sl_to_vl(to_mdev(ib_dev),
3159 sqp->ud_header.lrh.service_level,
3160 qp->port);
3161 if (qp->ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
fd10ed8e 3162 return -EINVAL;
fa417f7b
EC		 3163 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3164 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3165 }
e622f2f4 3166 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
915ec7ed
LR		 3167 if (!qp->ibqp.qp_num)
3168 err = ib_get_cached_pkey(ib_dev, qp->port, sqp->pkey_index,
6693ca95 3169 &pkey);
225c7b1f 3170 else
915ec7ed 3171 err = ib_get_cached_pkey(ib_dev, qp->port, wr->pkey_index,
6693ca95
JM		 3172 &pkey);
3173 if (err)
3174 return err;
3175
225c7b1f 3176 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3177 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3178 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3179 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3180 sqp->qkey : wr->remote_qkey);
915ec7ed 3181 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->ibqp.qp_num);
225c7b1f
RD		 3182
3183 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3184
3185 if (0) {
987c8f8f 3186 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3187 for (i = 0; i < header_size / 4; ++i) {
3188 if (i % 8 == 0)
987c8f8f
SP		 3189 pr_err(" [%02x] ", i * 4);
3190 pr_cont(" %08x",
3191 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3192 if ((i + 1) % 8 == 0)
987c8f8f 3193 pr_cont("\n");
225c7b1f 3194 }
987c8f8f 3195 pr_err("\n");
225c7b1f
RD		 3196 }
3197
e61ef241
RD		 3198 /*
3199 * Inline data segments may not cross a 64 byte boundary. If
3200 * our UD header is bigger than the space available up to the
3201 * next 64 byte boundary in the WQE, use two inline data
3202 * segments to hold the UD header.
3203 */
3204 spc = MLX4_INLINE_ALIGN -
3205 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3206 if (header_size <= spc) {
3207 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3208 memcpy(inl + 1, sqp->header_buf, header_size);
3209 i = 1;
3210 } else {
3211 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3212 memcpy(inl + 1, sqp->header_buf, spc);
3213
3214 inl = (void *) (inl + 1) + spc;
3215 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3216 /*
3217 * Need a barrier here to make sure all the data is
3218 * visible before the byte_count field is set.
3219 * Otherwise the HCA prefetcher could grab the 64-byte
3220 * chunk with this inline segment and get a valid (!=
3221 * 0xffffffff) byte count but stale data, and end up
3222 * generating a packet with bad headers.
3223 *
3224 * The first inline segment's byte_count field doesn't
3225 * need a barrier, because it comes after a
3226 * control/MLX segment and therefore is at an offset
3227 * of 16 mod 64.
3228 */
3229 wmb();
3230 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3231 i = 2;
3232 }
225c7b1f 3233
f438000f
RD		 3234 *mlx_seg_len =
3235 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3236 return 0;
225c7b1f
RD		 3237}
3238
3239static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3240{
3241 unsigned cur;
3242 struct mlx4_ib_cq *cq;
3243
3244 cur = wq->head - wq->tail;
0e6e7416 3245 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3246 return 0;
3247
3248 cq = to_mcq(ib_cq);
3249 spin_lock(&cq->lock);
3250 cur = wq->head - wq->tail;
3251 spin_unlock(&cq->lock);
3252
0e6e7416 3253 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3254}
3255
95d04f07
RD		 3256static __be32 convert_access(int acc)
3257{
6ff63e19
SM		 3258 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3259 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3260 (acc & IB_ACCESS_REMOTE_WRITE ?
3261 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3262 (acc & IB_ACCESS_REMOTE_READ ?
3263 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3264 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3265 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3266}
3267
1b2cd0fc 3268static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
f696bf6d 3269 const struct ib_reg_wr *wr)
1b2cd0fc
SG		 3270{
3271 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3272
3273 fseg->flags = convert_access(wr->access);
3274 fseg->mem_key = cpu_to_be32(wr->key);
3275 fseg->buf_list = cpu_to_be64(mr->page_map);
3276 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3277 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3278 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3279 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3280 fseg->reserved[0] = 0;
3281 fseg->reserved[1] = 0;
3282}
3283
95d04f07
RD		 3284static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3285{
aee38fad
SM		 3286 memset(iseg, 0, sizeof(*iseg));
3287 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3288}
3289
0fbfa6a9
RD		 3290static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3291 u64 remote_addr, u32 rkey)
3292{
3293 rseg->raddr = cpu_to_be64(remote_addr);
3294 rseg->rkey = cpu_to_be32(rkey);
3295 rseg->reserved = 0;
3296}
3297
e622f2f4 3298static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
f696bf6d 3299 const struct ib_atomic_wr *wr)
0fbfa6a9 3300{
e622f2f4
CH		 3301 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3302 aseg->swap_add = cpu_to_be64(wr->swap);
3303 aseg->compare = cpu_to_be64(wr->compare_add);
3304 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3305 aseg->swap_add = cpu_to_be64(wr->compare_add);
3306 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3307 } else {
e622f2f4 3308 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3309 aseg->compare = 0;
3310 }
3311
3312}
3313
6fa8f719 3314static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
f696bf6d 3315 const struct ib_atomic_wr *wr)
6fa8f719 3316{
e622f2f4
CH		 3317 aseg->swap_add = cpu_to_be64(wr->swap);
3318 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3319 aseg->compare = cpu_to_be64(wr->compare_add);
3320 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3321}
3322
0fbfa6a9 3323static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3324 const struct ib_ud_wr *wr)
0fbfa6a9 3325{
e622f2f4
CH		 3326 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3327 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3328 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3329 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3330 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3331}
3332
1ffeb2eb
JM		 3333static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3334 struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3335 const struct ib_ud_wr *wr,
97982f5a 3336 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3337{
e622f2f4 3338 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3339 struct mlx4_av sqp_av = {0};
3340 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3341
3342 /* force loopback */
3343 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3344 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3345 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3346 cpu_to_be32(0xf0000000);
3347
3348 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3349 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3350 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3351 else
c73c8b1e 3352 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3353 /* Use QKEY from the QP context, which is set by master */
3354 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3355}
3356
f696bf6d
BVA		 3357static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3358 unsigned *mlx_seg_len)
1ffeb2eb
JM		 3359{
3360 struct mlx4_wqe_inline_seg *inl = wqe;
3361 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3362 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3363 int spc;
3364 int i;
3365
3366 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3367 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3368 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3369 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3370 memcpy(hdr.mac, ah->av.eth.mac, 6);
3371 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3372
3373 spc = MLX4_INLINE_ALIGN -
3374 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3375 if (sizeof (hdr) <= spc) {
3376 memcpy(inl + 1, &hdr, sizeof (hdr));
3377 wmb();
3378 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3379 i = 1;
3380 } else {
3381 memcpy(inl + 1, &hdr, spc);
3382 wmb();
3383 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3384
3385 inl = (void *) (inl + 1) + spc;
3386 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3387 wmb();
3388 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3389 i = 2;
3390 }
3391
3392 *mlx_seg_len =
3393 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3394}
3395
6e694ea3
JM		 3396static void set_mlx_icrc_seg(void *dseg)
3397{
3398 u32 *t = dseg;
3399 struct mlx4_wqe_inline_seg *iseg = dseg;
3400
3401 t[1] = 0;
3402
3403 /*
3404 * Need a barrier here before writing the byte_count field to
3405 * make sure that all the data is visible before the
3406 * byte_count field is set. Otherwise, if the segment begins
3407 * a new cacheline, the HCA prefetcher could grab the 64-byte
3408 * chunk and get a valid (!= * 0xffffffff) byte count but
3409 * stale data, and end up sending the wrong data.
3410 */
3411 wmb();
3412
3413 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3414}
3415
3416static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3417{
d420d9e3
RD		 3418 dseg->lkey = cpu_to_be32(sg->lkey);
3419 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3420
3421 /*
3422 * Need a barrier here before writing the byte_count field to
3423 * make sure that all the data is visible before the
3424 * byte_count field is set. Otherwise, if the segment begins
3425 * a new cacheline, the HCA prefetcher could grab the 64-byte
3426 * chunk and get a valid (!= * 0xffffffff) byte count but
3427 * stale data, and end up sending the wrong data.
3428 */
3429 wmb();
3430
3431 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3432}
3433
2242fa4f
RD		 3434static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3435{
3436 dseg->byte_count = cpu_to_be32(sg->length);
3437 dseg->lkey = cpu_to_be32(sg->lkey);
3438 dseg->addr = cpu_to_be64(sg->addr);
3439}
3440
f696bf6d
BVA		 3441static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3442 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3443 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3444{
e622f2f4 3445 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3446
417608c2
EC		 3447 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3448 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3449
3450 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3451 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3452 return -EINVAL;
3453
e622f2f4 3454 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3455
e622f2f4 3456 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3457 *lso_seg_len = halign;
3458 return 0;
3459}
3460
f696bf6d 3461static __be32 send_ieth(const struct ib_send_wr *wr)
95d04f07
RD		 3462{
3463 switch (wr->opcode) {
3464 case IB_WR_SEND_WITH_IMM:
3465 case IB_WR_RDMA_WRITE_WITH_IMM:
3466 return wr->ex.imm_data;
3467
3468 case IB_WR_SEND_WITH_INV:
3469 return cpu_to_be32(wr->ex.invalidate_rkey);
3470
3471 default:
3472 return 0;
3473 }
3474}
3475
1ffeb2eb
JM		 3476static void add_zero_len_inline(void *wqe)
3477{
3478 struct mlx4_wqe_inline_seg *inl = wqe;
3479 memset(wqe, 0, 16);
3480 inl->byte_count = cpu_to_be32(1 << 31);
3481}
3482
d34ac5cd
BVA		 3483static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3484 const struct ib_send_wr **bad_wr, bool drain)
225c7b1f
RD		 3485{
3486 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3487 void *wqe;
3488 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3489 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3490 unsigned long flags;
3491 int nreq;
3492 int err = 0;
ea54b10c 3493 unsigned ind;
3f649ab7
KC		 3494 int size;
3495 unsigned seglen;
0fd7e1d8
RD		 3496 __be32 dummy;
3497 __be32 *lso_wqe;
3f649ab7 3498 __be32 lso_hdr_sz;
417608c2 3499 __be32 blh;
225c7b1f 3500 int i;
35f05dab 3501 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3502
e1b866c6 3503 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
915ec7ed 3504 struct mlx4_ib_sqp *sqp = qp->sqp;
e1b866c6
MS		 3505
3506 if (sqp->roce_v2_gsi) {
3507 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3508 enum ib_gid_type gid_type;
e1b866c6
MS		 3509 union ib_gid gid;
3510
915ec7ed 3511 if (!fill_gid_by_hw_index(mdev, qp->port,
a748d60d
TB		 3512 ah->av.ib.gid_index,
3513 &gid, &gid_type))
3514 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3515 to_mqp(sqp->roce_v2_gsi) : qp;
3516 else
e1b866c6
MS		 3517 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3518 ah->av.ib.gid_index);
e1b866c6
MS		 3519 }
3520 }
3521
96db0e03 3522 spin_lock_irqsave(&qp->sq.lock, flags);
1975acd9
YH		 3523 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3524 !drain) {
35f05dab
YH		 3525 err = -EIO;
3526 *bad_wr = wr;
3527 nreq = 0;
3528 goto out;
3529 }
225c7b1f 3530
ea54b10c 3531 ind = qp->sq_next_wqe;
225c7b1f
RD		 3532
3533 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3534 lso_wqe = &dummy;
417608c2 3535 blh = 0;
0fd7e1d8 3536
225c7b1f
RD		 3537 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3538 err = -ENOMEM;
3539 *bad_wr = wr;
3540 goto out;
3541 }
3542
3543 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3544 err = -EINVAL;
3545 *bad_wr = wr;
3546 goto out;
3547 }
3548
0e6e7416 3549 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3550 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3551
3552 ctrl->srcrb_flags =
3553 (wr->send_flags & IB_SEND_SIGNALED ?
3554 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3555 (wr->send_flags & IB_SEND_SOLICITED ?
3556 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3557 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3558 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3559 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3560 qp->sq_signal_bits;
3561
95d04f07 3562 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3563
3564 wqe += sizeof *ctrl;
3565 size = sizeof *ctrl / 16;
3566
1ffeb2eb
JM		 3567 switch (qp->mlx4_ib_qp_type) {
3568 case MLX4_IB_QPT_RC:
3569 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3570 switch (wr->opcode) {
3571 case IB_WR_ATOMIC_CMP_AND_SWP:
3572 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3573 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3574 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3575 atomic_wr(wr)->rkey);
225c7b1f
RD		 3576 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3577
e622f2f4 3578 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3579 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3580
225c7b1f
RD		 3581 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3582 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3583
3584 break;
3585
3586 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3587 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3588 atomic_wr(wr)->rkey);
6fa8f719
VS		 3589 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3590
e622f2f4 3591 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3592 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3593
3594 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3595 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3596
3597 break;
3598
3599 case IB_WR_RDMA_READ:
3600 case IB_WR_RDMA_WRITE:
3601 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3602 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3603 rdma_wr(wr)->rkey);
225c7b1f
RD		 3604 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3605 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3606 break;
95d04f07
RD		 3607
3608 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3609 ctrl->srcrb_flags |=
3610 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3611 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3612 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3613 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3614 break;
3615
1b2cd0fc
SG		 3616 case IB_WR_REG_MR:
3617 ctrl->srcrb_flags |=
3618 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3619 set_reg_seg(wqe, reg_wr(wr));
3620 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3621 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3622 break;
3623
225c7b1f
RD		 3624 default:
3625 /* No extra segments required for sends */
3626 break;
3627 }
3628 break;
3629
1ffeb2eb 3630 case MLX4_IB_QPT_TUN_SMI_OWNER:
915ec7ed
LR		 3631 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3632 &seglen);
1ffeb2eb
JM		 3633 if (unlikely(err)) {
3634 *bad_wr = wr;
3635 goto out;
3636 }
3637 wqe += seglen;
3638 size += seglen / 16;
3639 break;
3640 case MLX4_IB_QPT_TUN_SMI:
3641 case MLX4_IB_QPT_TUN_GSI:
3642 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3643 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3644 /* set the forced-loopback bit in the data seg av */
3645 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3646 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3647 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3648 break;
3649 case MLX4_IB_QPT_UD:
e622f2f4 3650 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3651 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3652 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3653
3654 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3655 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3656 &lso_hdr_sz, &blh);
b832be1e
EC		 3657 if (unlikely(err)) {
3658 *bad_wr = wr;
3659 goto out;
3660 }
0fd7e1d8 3661 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3662 wqe += seglen;
3663 size += seglen / 16;
3664 }
225c7b1f
RD		 3665 break;
3666
1ffeb2eb 3667 case MLX4_IB_QPT_PROXY_SMI_OWNER:
915ec7ed
LR		 3668 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3669 &seglen);
1ffeb2eb
JM		 3670 if (unlikely(err)) {
3671 *bad_wr = wr;
3672 goto out;
3673 }
3674 wqe += seglen;
3675 size += seglen / 16;
3676 /* to start tunnel header on a cache-line boundary */
3677 add_zero_len_inline(wqe);
3678 wqe += 16;
3679 size++;
e622f2f4 3680 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3681 wqe += seglen;
3682 size += seglen / 16;
3683 break;
3684 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3685 case MLX4_IB_QPT_PROXY_GSI:
3686 /* If we are tunneling special qps, this is a UD qp.
3687 * In this case we first add a UD segment targeting
3688 * the tunnel qp, and then add a header with address
3689 * information */
e622f2f4
CH		 3690 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3691 ud_wr(wr),
97982f5a 3692 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3693 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3694 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3695 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3696 wqe += seglen;
3697 size += seglen / 16;
3698 break;
3699
3700 case MLX4_IB_QPT_SMI:
3701 case MLX4_IB_QPT_GSI:
915ec7ed 3702 err = build_mlx_header(qp, ud_wr(wr), ctrl, &seglen);
f438000f 3703 if (unlikely(err)) {
225c7b1f
RD		 3704 *bad_wr = wr;
3705 goto out;
3706 }
f438000f
RD		 3707 wqe += seglen;
3708 size += seglen / 16;
225c7b1f
RD		 3709 break;
3710
3711 default:
3712 break;
3713 }
3714
6e694ea3
JM		 3715 /*
3716 * Write data segments in reverse order, so as to
3717 * overwrite cacheline stamp last within each
3718 * cacheline. This avoids issues with WQE
3719 * prefetching.
3720 */
225c7b1f 3721
6e694ea3
JM		 3722 dseg = wqe;
3723 dseg += wr->num_sge - 1;
3724 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3725
3726 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3727 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3728 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3729 qp->mlx4_ib_qp_type &
3730 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3731 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3732 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3733 }
3734
6e694ea3
JM		 3735 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3736 set_data_seg(dseg, wr->sg_list + i);
3737
0fd7e1d8
RD		 3738 /*
3739 * Possibly overwrite stamping in cacheline with LSO
3740 * segment only after making sure all data segments
3741 * are written.
3742 */
3743 wmb();
3744 *lso_wqe = lso_hdr_sz;
3745
224e92e0
BB		 3746 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3747 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3748
3749 /*
3750 * Make sure descriptor is fully written before
3751 * setting ownership bit (because HW can start
3752 * executing as soon as we do).
3753 */
3754 wmb();
3755
59b0ed12 3756 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3757 *bad_wr = wr;
225c7b1f
RD		 3758 err = -EINVAL;
3759 goto out;
3760 }
3761
3762 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3763 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416
RD		 3764
3765 /*
3766 * We can improve latency by not stamping the last
3767 * send queue WQE until after ringing the doorbell, so
3768 * only stamp here if there are still more WQEs to post.
3769 */
f95ccffc
JM		 3770 if (wr->next)
3771 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3772 ind++;
225c7b1f
RD		 3773 }
3774
3775out:
3776 if (likely(nreq)) {
3777 qp->sq.head += nreq;
3778
3779 /*
3780 * Make sure that descriptors are written before
3781 * doorbell record.
3782 */
3783 wmb();
3784
97d82a48
SK		 3785 writel_relaxed(qp->doorbell_qpn,
3786 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
225c7b1f 3787
f95ccffc 3788 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
ea54b10c 3789
ea54b10c 3790 qp->sq_next_wqe = ind;
225c7b1f
RD		 3791 }
3792
96db0e03 3793 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3794
3795 return err;
3796}
3797
d34ac5cd
BVA		 3798int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3799 const struct ib_send_wr **bad_wr)
1975acd9
YH		 3800{
3801 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3802}
3803
d34ac5cd
BVA		 3804static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3805 const struct ib_recv_wr **bad_wr, bool drain)
225c7b1f
RD		 3806{
3807 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3808 struct mlx4_wqe_data_seg *scat;
3809 unsigned long flags;
3810 int err = 0;
3811 int nreq;
3812 int ind;
1ffeb2eb 3813 int max_gs;
225c7b1f 3814 int i;
35f05dab 3815 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3816
1ffeb2eb 3817 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3818 spin_lock_irqsave(&qp->rq.lock, flags);
3819
1975acd9
YH		 3820 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3821 !drain) {
35f05dab
YH		 3822 err = -EIO;
3823 *bad_wr = wr;
3824 nreq = 0;
3825 goto out;
3826 }
3827
0e6e7416 3828 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3829
3830 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3831 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3832 err = -ENOMEM;
3833 *bad_wr = wr;
3834 goto out;
3835 }
3836
3837 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3838 err = -EINVAL;
3839 *bad_wr = wr;
3840 goto out;
3841 }
3842
3843 scat = get_recv_wqe(qp, ind);
3844
1ffeb2eb
JM		 3845 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3846 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3847 ib_dma_sync_single_for_device(ibqp->device,
3848 qp->sqp_proxy_rcv[ind].map,
3849 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3850 DMA_FROM_DEVICE);
3851 scat->byte_count =
3852 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3853 /* use dma lkey from upper layer entry */
3854 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3855 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3856 scat++;
3857 max_gs--;
3858 }
3859
2242fa4f
RD		 3860 for (i = 0; i < wr->num_sge; ++i)
3861 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3862
1ffeb2eb 3863 if (i < max_gs) {
225c7b1f
RD		 3864 scat[i].byte_count = 0;
3865 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3866 scat[i].addr = 0;
3867 }
3868
3869 qp->rq.wrid[ind] = wr->wr_id;
3870
0e6e7416 3871 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3872 }
3873
3874out:
3875 if (likely(nreq)) {
3876 qp->rq.head += nreq;
3877
3878 /*
3879 * Make sure that descriptors are written before
3880 * doorbell record.
3881 */
3882 wmb();
3883
3884 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3885 }
3886
3887 spin_unlock_irqrestore(&qp->rq.lock, flags);
3888
3889 return err;
3890}
6a775e2b 3891
d34ac5cd
BVA		 3892int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3893 const struct ib_recv_wr **bad_wr)
1975acd9
YH		 3894{
3895 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3896}
3897
6a775e2b
JM		 3898static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3899{
3900 switch (mlx4_state) {
3901 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3902 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3903 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3904 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3905 case MLX4_QP_STATE_SQ_DRAINING:
3906 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3907 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3908 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3909 default: return -1;
3910 }
3911}
3912
3913static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3914{
3915 switch (mlx4_mig_state) {
3916 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3917 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3918 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3919 default: return -1;
3920 }
3921}
3922
3923static int to_ib_qp_access_flags(int mlx4_flags)
3924{
3925 int ib_flags = 0;
3926
3927 if (mlx4_flags & MLX4_QP_BIT_RRE)
3928 ib_flags |= IB_ACCESS_REMOTE_READ;
3929 if (mlx4_flags & MLX4_QP_BIT_RWE)
3930 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3931 if (mlx4_flags & MLX4_QP_BIT_RAE)
3932 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3933
3934 return ib_flags;
3935}
3936
71d53ab4 3937static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3938 struct rdma_ah_attr *ah_attr,
71d53ab4 3939 struct mlx4_qp_path *path)
6a775e2b 3940{
4c3eb3ca 3941 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3942 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 3943
d8966fcd 3944 memset(ah_attr, 0, sizeof(*ah_attr));
d8966fcd 3945 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b 3946 return;
f1228867 3947 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
6a775e2b 3948
44c58487 3949 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 3950 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3951 ((path->sched_queue & 4) << 1));
4c3eb3ca 3952 else
d8966fcd 3953 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 3954 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 3955
d8966fcd
DC		 3956 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3957 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3958 rdma_ah_set_static_rate(ah_attr,
3959 path->static_rate ? path->static_rate - 5 : 0);
3960 if (path->grh_mylmc & (1 << 7)) {
3961 rdma_ah_set_grh(ah_attr, NULL,
3962 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3963 path->mgid_index,
3964 path->hop_limit,
3965 (be32_to_cpu(path->tclass_flowlabel)
3966 >> 20) & 0xff);
3967 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 3968 }
3969}
3970
3971int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3972 struct ib_qp_init_attr *qp_init_attr)
3973{
3974 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3975 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3976 struct mlx4_qp_context context;
3977 int mlx4_state;
0df67030
DB		 3978 int err = 0;
3979
3078f5f1
GL		 3980 if (ibqp->rwq_ind_tbl)
3981 return -EOPNOTSUPP;
3982
0df67030 3983 mutex_lock(&qp->mutex);
6a775e2b
JM		 3984
3985 if (qp->state == IB_QPS_RESET) {
3986 qp_attr->qp_state = IB_QPS_RESET;
3987 goto done;
3988 }
3989
3990 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3991 if (err) {
3992 err = -EINVAL;
3993 goto out;
3994 }
6a775e2b
JM		 3995
3996 mlx4_state = be32_to_cpu(context.flags) >> 28;
3997
0df67030
DB		 3998 qp->state = to_ib_qp_state(mlx4_state);
3999 qp_attr->qp_state = qp->state;
6a775e2b
JM		 4000 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4001 qp_attr->path_mig_state =
4002 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4003 qp_attr->qkey = be32_to_cpu(context.qkey);
4004 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4005 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4006 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4007 qp_attr->qp_access_flags =
4008 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4009
4010 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
71d53ab4
DC		 4011 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4012 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4013 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4014 qp_attr->alt_port_num =
4015 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4016 }
4017
4018 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4019 if (qp_attr->qp_state == IB_QPS_INIT)
4020 qp_attr->port_num = qp->port;
4021 else
4022 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4023
4024 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4025 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4026
4027 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4028
4029 qp_attr->max_dest_rd_atomic =
4030 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4031 qp_attr->min_rnr_timer =
4032 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4033 qp_attr->timeout = context.pri_path.ackto >> 3;
4034 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4035 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4036 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4037
4038done:
4039 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4040 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4041 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4042
6a775e2b 4043 if (!ibqp->uobject) {
7f5eb9bb
RD		 4044 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4045 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4046 } else {
4047 qp_attr->cap.max_send_wr = 0;
4048 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4049 }
4050
7f5eb9bb
RD		 4051 /*
4052 * We don't support inline sends for kernel QPs (yet), and we
4053 * don't know what userspace's value should be.
4054 */
4055 qp_attr->cap.max_inline_data = 0;
4056
4057 qp_init_attr->cap = qp_attr->cap;
4058
521e575b
RL		 4059 qp_init_attr->create_flags = 0;
4060 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4061 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4062
4063 if (qp->flags & MLX4_IB_QP_LSO)
4064 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4065
c1c98501
MB		 4066 if (qp->flags & MLX4_IB_QP_NETIF)
4067 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4068
46db567d
DB		 4069 qp_init_attr->sq_sig_type =
4070 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4071 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4072
0df67030
DB		 4073out:
4074 mutex_unlock(&qp->mutex);
4075 return err;
6a775e2b
JM		 4076}
4077
400b1ebc
GL		 4078struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4079 struct ib_wq_init_attr *init_attr,
4080 struct ib_udata *udata)
4081{
089b645d
LR		 4082 struct mlx4_dev *dev = to_mdev(pd->device)->dev;
4083 struct ib_qp_init_attr ib_qp_init_attr = {};
400b1ebc
GL		 4084 struct mlx4_ib_qp *qp;
4085 struct mlx4_ib_create_wq ucmd;
4086 int err, required_cmd_sz;
4087
e00b64f7 4088 if (!udata)
400b1ebc
GL		 4089 return ERR_PTR(-EINVAL);
4090
078b3573
GL		 4091 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4092 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4093 if (udata->inlen < required_cmd_sz) {
4094 pr_debug("invalid inlen\n");
4095 return ERR_PTR(-EINVAL);
4096 }
4097
4098 if (udata->inlen > sizeof(ucmd) &&
4099 !ib_is_udata_cleared(udata, sizeof(ucmd),
4100 udata->inlen - sizeof(ucmd))) {
4101 pr_debug("inlen is not supported\n");
4102 return ERR_PTR(-EOPNOTSUPP);
4103 }
4104
4105 if (udata->outlen)
4106 return ERR_PTR(-EOPNOTSUPP);
4107
400b1ebc
GL		 4108 if (init_attr->wq_type != IB_WQT_RQ) {
4109 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4110 return ERR_PTR(-EOPNOTSUPP);
4111 }
4112
089b645d
LR		 4113 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS ||
4114 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
400b1ebc
GL		 4115 pr_debug("unsupported create_flags %u\n",
4116 init_attr->create_flags);
4117 return ERR_PTR(-EOPNOTSUPP);
4118 }
4119
4120 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4121 if (!qp)
4122 return ERR_PTR(-ENOMEM);
4123
8fd3cd2a 4124 mutex_init(&qp->mutex);
400b1ebc
GL		 4125 qp->pri.vid = 0xFFFF;
4126 qp->alt.vid = 0xFFFF;
4127
400b1ebc
GL		 4128 ib_qp_init_attr.qp_context = init_attr->wq_context;
4129 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4130 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4131 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4132 ib_qp_init_attr.recv_cq = init_attr->cq;
4133 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4134
6d06c9aa
GL		 4135 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4136 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4137
089b645d 4138 err = create_rq(pd, &ib_qp_init_attr, udata, qp);
400b1ebc
GL		 4139 if (err) {
4140 kfree(qp);
4141 return ERR_PTR(err);
4142 }
4143
4144 qp->ibwq.event_handler = init_attr->event_handler;
4145 qp->ibwq.wq_num = qp->mqp.qpn;
4146 qp->ibwq.state = IB_WQS_RESET;
4147
4148 return &qp->ibwq;
4149}
4150
4151static int ib_wq2qp_state(enum ib_wq_state state)
4152{
4153 switch (state) {
4154 case IB_WQS_RESET:
4155 return IB_QPS_RESET;
4156 case IB_WQS_RDY:
4157 return IB_QPS_RTR;
4158 default:
4159 return IB_QPS_ERR;
4160 }
4161}
4162
89944450
SR		 4163static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
4164 struct ib_udata *udata)
400b1ebc
GL		 4165{
4166 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4167 enum ib_qp_state qp_cur_state;
4168 enum ib_qp_state qp_new_state;
4169 int attr_mask;
4170 int err;
4171
4172 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4173 * the WQ logic state.
4174 */
4175 qp_cur_state = qp->state;
4176 qp_new_state = ib_wq2qp_state(new_state);
4177
4178 if (ib_wq2qp_state(new_state) == qp_cur_state)
4179 return 0;
4180
4181 if (new_state == IB_WQS_RDY) {
4182 struct ib_qp_attr attr = {};
4183
4184 attr.port_num = qp->port;
4185 attr_mask = IB_QP_PORT;
4186
4187 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
89944450
SR		 4188 attr_mask, IB_QPS_RESET, IB_QPS_INIT,
4189 udata);
400b1ebc
GL		 4190 if (err) {
4191 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4192 ibwq->wq_num);
4193 return err;
4194 }
4195
4196 qp_cur_state = IB_QPS_INIT;
4197 }
4198
4199 attr_mask = 0;
4200 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
89944450 4201 qp_cur_state, qp_new_state, udata);
400b1ebc
GL		 4202
4203 if (err && (qp_cur_state == IB_QPS_INIT)) {
4204 qp_new_state = IB_QPS_RESET;
4205 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
89944450
SR		 4206 attr_mask, IB_QPS_INIT, IB_QPS_RESET,
4207 udata)) {
400b1ebc
GL		 4208 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4209 ibwq->wq_num);
4210 qp_new_state = IB_QPS_INIT;
4211 }
4212 }
4213
4214 qp->state = qp_new_state;
4215
4216 return err;
4217}
4218
4219int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4220 u32 wq_attr_mask, struct ib_udata *udata)
4221{
4222 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4223 struct mlx4_ib_modify_wq ucmd = {};
4224 size_t required_cmd_sz;
4225 enum ib_wq_state cur_state, new_state;
4226 int err = 0;
4227
4228 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4229 sizeof(ucmd.reserved);
4230 if (udata->inlen < required_cmd_sz)
4231 return -EINVAL;
4232
4233 if (udata->inlen > sizeof(ucmd) &&
4234 !ib_is_udata_cleared(udata, sizeof(ucmd),
4235 udata->inlen - sizeof(ucmd)))
4236 return -EOPNOTSUPP;
4237
4238 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4239 return -EFAULT;
4240
4241 if (ucmd.comp_mask || ucmd.reserved)
4242 return -EOPNOTSUPP;
4243
4244 if (wq_attr_mask & IB_WQ_FLAGS)
4245 return -EOPNOTSUPP;
4246
4247 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4248 ibwq->state;
4249 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4250
4251 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4252 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4253 return -EINVAL;
4254
4255 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4256 return -EINVAL;
4257
4258 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4259 return -EINVAL;
4260
3078f5f1
GL		 4261 /* Need to protect against the parent RSS which also may modify WQ
4262 * state.
4263 */
4264 mutex_lock(&qp->mutex);
4265
400b1ebc
GL		 4266 /* Can update HW state only if a RSS QP has already associated to this
4267 * WQ, so we can apply its port on the WQ.
4268 */
4269 if (qp->rss_usecnt)
89944450 4270 err = _mlx4_ib_modify_wq(ibwq, new_state, udata);
400b1ebc
GL		 4271
4272 if (!err)
4273 ibwq->state = new_state;
4274
3078f5f1
GL		 4275 mutex_unlock(&qp->mutex);
4276
400b1ebc
GL		 4277 return err;
4278}
4279
add53535 4280int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata)
400b1ebc
GL		 4281{
4282 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4283 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4284
4285 if (qp->counter_index)
4286 mlx4_ib_free_qp_counter(dev, qp);
4287
bdeacabd 4288 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata);
400b1ebc
GL		 4289
4290 kfree(qp);
add53535 4291 return 0;
400b1ebc 4292}
b8d46ca0 4293
c0a6b5ec
LR		 4294int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table,
4295 struct ib_rwq_ind_table_init_attr *init_attr,
4296 struct ib_udata *udata)
b8d46ca0 4297{
b8d46ca0
GL		 4298 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4299 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
c0a6b5ec 4300 struct ib_device *device = rwq_ind_table->device;
b8d46ca0
GL		 4301 unsigned int base_wqn;
4302 size_t min_resp_len;
c0a6b5ec 4303 int i, err = 0;
b8d46ca0
GL		 4304
4305 if (udata->inlen > 0 &&
4306 !ib_is_udata_cleared(udata, 0,
4307 udata->inlen))
c0a6b5ec 4308 return -EOPNOTSUPP;
b8d46ca0
GL		 4309
4310 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4311 if (udata->outlen && udata->outlen < min_resp_len)
c0a6b5ec 4312 return -EINVAL;
b8d46ca0
GL		 4313
4314 if (ind_tbl_size >
4315 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4316 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4317 ind_tbl_size,
4318 device->attrs.rss_caps.max_rwq_indirection_table_size);
c0a6b5ec 4319 return -EINVAL;
b8d46ca0
GL		 4320 }
4321
4322 base_wqn = init_attr->ind_tbl[0]->wq_num;
4323
4324 if (base_wqn % ind_tbl_size) {
4325 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4326 base_wqn);
c0a6b5ec 4327 return -EINVAL;
b8d46ca0
GL		 4328 }
4329
4330 for (i = 1; i < ind_tbl_size; i++) {
4331 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4332 pr_debug("indirection table's WQNs aren't consecutive\n");
c0a6b5ec 4333 return -EINVAL;
b8d46ca0
GL		 4334 }
4335 }
4336
b8d46ca0
GL		 4337 if (udata->outlen) {
4338 resp.response_length = offsetof(typeof(resp), response_length) +
4339 sizeof(resp.response_length);
4340 err = ib_copy_to_udata(udata, &resp, resp.response_length);
b8d46ca0
GL		 4341 }
4342
c0a6b5ec 4343 return err;
b8d46ca0 4344}
1975acd9
YH		 4345
4346struct mlx4_ib_drain_cqe {
4347 struct ib_cqe cqe;
4348 struct completion done;
4349};
4350
4351static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4352{
4353 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4354 struct mlx4_ib_drain_cqe,
4355 cqe);
4356
4357 complete(&cqe->done);
4358}
4359
4360/* This function returns only once the drained WR was completed */
4361static void handle_drain_completion(struct ib_cq *cq,
4362 struct mlx4_ib_drain_cqe *sdrain,
4363 struct mlx4_ib_dev *dev)
4364{
4365 struct mlx4_dev *mdev = dev->dev;
4366
4367 if (cq->poll_ctx == IB_POLL_DIRECT) {
4368 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4369 ib_process_cq_direct(cq, -1);
4370 return;
4371 }
4372
4373 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4374 struct mlx4_ib_cq *mcq = to_mcq(cq);
4375 bool triggered = false;
4376 unsigned long flags;
4377
4378 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4379 /* Make sure that the CQ handler won't run if wasn't run yet */
4380 if (!mcq->mcq.reset_notify_added)
4381 mcq->mcq.reset_notify_added = 1;
4382 else
4383 triggered = true;
4384 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4385
4386 if (triggered) {
4387 /* Wait for any scheduled/running task to be ended */
4388 switch (cq->poll_ctx) {
4389 case IB_POLL_SOFTIRQ:
4390 irq_poll_disable(&cq->iop);
4391 irq_poll_enable(&cq->iop);
4392 break;
4393 case IB_POLL_WORKQUEUE:
4394 cancel_work_sync(&cq->work);
4395 break;
4396 default:
4397 WARN_ON_ONCE(1);
4398 }
4399 }
4400
4401 /* Run the CQ handler - this makes sure that the drain WR will
4402 * be processed if wasn't processed yet.
4403 */
4404 mcq->mcq.comp(&mcq->mcq);
4405 }
4406
4407 wait_for_completion(&sdrain->done);
4408}
4409
4410void mlx4_ib_drain_sq(struct ib_qp *qp)
4411{
4412 struct ib_cq *cq = qp->send_cq;
4413 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4414 struct mlx4_ib_drain_cqe sdrain;
d34ac5cd 4415 const struct ib_send_wr *bad_swr;
1975acd9
YH		 4416 struct ib_rdma_wr swr = {
4417 .wr = {
4418 .next = NULL,
4419 { .wr_cqe = &sdrain.cqe, },
4420 .opcode = IB_WR_RDMA_WRITE,
4421 },
4422 };
4423 int ret;
4424 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4425 struct mlx4_dev *mdev = dev->dev;
4426
4427 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4428 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4429 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4430 return;
4431 }
4432
4433 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4434 init_completion(&sdrain.done);
4435
4436 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4437 if (ret) {
4438 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4439 return;
4440 }
4441
4442 handle_drain_completion(cq, &sdrain, dev);
4443}
4444
4445void mlx4_ib_drain_rq(struct ib_qp *qp)
4446{
4447 struct ib_cq *cq = qp->recv_cq;
4448 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4449 struct mlx4_ib_drain_cqe rdrain;
d34ac5cd
BVA		 4450 struct ib_recv_wr rwr = {};
4451 const struct ib_recv_wr *bad_rwr;
1975acd9
YH		 4452 int ret;
4453 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4454 struct mlx4_dev *mdev = dev->dev;
4455
4456 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4457 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4458 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4459 return;
4460 }
4461
4462 rwr.wr_cqe = &rdrain.cqe;
4463 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4464 init_completion(&rdrain.done);
4465
4466 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4467 if (ret) {
4468 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4469 return;
4470 }
4471
4472 handle_drain_completion(cq, &rdrain, dev);
4473}
Linux 6.x block layer and io_uring tree(s)