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RDMA: Globally allocate and release QP memory
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
1049f138 35#include <linux/etherdevice.h>
3ef967a4 36#include <net/ip.h>
5a0e3ad6 37#include <linux/slab.h>
fa417f7b 38#include <linux/netdevice.h>
ea54b10c 39
225c7b1f
RD		 40#include <rdma/ib_cache.h>
41#include <rdma/ib_pack.h>
4c3eb3ca 42#include <rdma/ib_addr.h>
1ffeb2eb 43#include <rdma/ib_mad.h>
89944450 44#include <rdma/uverbs_ioctl.h>
225c7b1f 45
2f48485d 46#include <linux/mlx4/driver.h>
225c7b1f
RD		 47#include <linux/mlx4/qp.h>
48
49#include "mlx4_ib.h"
9ce28a20 50#include <rdma/mlx4-abi.h>
225c7b1f 51
35f05dab
YH		 52static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
89944450
SR		 56static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
57 struct ib_udata *udata);
35f05dab 58
225c7b1f
RD		 59enum {
60 MLX4_IB_ACK_REQ_FREQ = 8,
61};
62
63enum {
64 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
fa417f7b
EC		 65 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
66 MLX4_IB_LINK_TYPE_IB = 0,
67 MLX4_IB_LINK_TYPE_ETH = 1
225c7b1f
RD		 68};
69
83904132 70enum {
417608c2
EC		 71 MLX4_IB_MIN_SQ_STRIDE = 6,
72 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 73};
74
3987a2d3
OG		 75enum {
76 MLX4_RAW_QP_MTU = 7,
77 MLX4_RAW_QP_MSGMAX = 31,
78};
79
297e0dad
MS		 80#ifndef ETH_ALEN
81#define ETH_ALEN 6
82#endif
297e0dad 83
225c7b1f 84static const __be32 mlx4_ib_opcode[] = {
6fa8f719
VS		 85 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
86 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
87 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
88 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
89 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
90 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
91 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
92 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
93 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
94 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
1b2cd0fc 95 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
6fa8f719
VS		 96 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
97 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
225c7b1f
RD		 98};
99
400b1ebc
GL		 100enum mlx4_ib_source_type {
101 MLX4_IB_QP_SRC = 0,
102 MLX4_IB_RWQ_SRC = 1,
103};
104
1ffeb2eb
JM		 105static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
106{
107 if (!mlx4_is_master(dev->dev))
108 return 0;
109
47605df9
JM		 110 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
111 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
112 8 * MLX4_MFUNC_MAX;
1ffeb2eb
JM		 113}
114
225c7b1f
RD		 115static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
116{
47605df9
JM		 117 int proxy_sqp = 0;
118 int real_sqp = 0;
119 int i;
120 /* PPF or Native -- real SQP */
121 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
122 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
123 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
124 if (real_sqp)
125 return 1;
126 /* VF or PF -- proxy SQP */
127 if (mlx4_is_mfunc(dev->dev)) {
128 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e
EBE		 129 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
130 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
47605df9
JM		 131 proxy_sqp = 1;
132 break;
133 }
134 }
135 }
e1b866c6
MS		 136 if (proxy_sqp)
137 return 1;
138
139 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
225c7b1f
RD		 140}
141
1ffeb2eb 142/* used for INIT/CLOSE port logic */
225c7b1f
RD		 143static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
144{
47605df9
JM		 145 int proxy_qp0 = 0;
146 int real_qp0 = 0;
147 int i;
148 /* PPF or Native -- real QP0 */
149 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
150 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
151 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
152 if (real_qp0)
153 return 1;
154 /* VF or PF -- proxy QP0 */
155 if (mlx4_is_mfunc(dev->dev)) {
156 for (i = 0; i < dev->dev->caps.num_ports; i++) {
c73c8b1e 157 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
47605df9
JM		 158 proxy_qp0 = 1;
159 break;
160 }
161 }
162 }
163 return proxy_qp0;
225c7b1f
RD		 164}
165
166static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
167{
1c69fc2a 168 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 169}
170
171static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
172{
173 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
174}
175
176static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
177{
178 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
179}
180
0e6e7416
RD		 181/*
182 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
f95ccffc
JM		 183 * first four bytes of every 64 byte chunk with 0xffffffff, except for
184 * the very first chunk of the WQE.
0e6e7416 185 */
f95ccffc 186static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
0e6e7416 187{
d2ae16d5 188 __be32 *wqe;
0e6e7416 189 int i;
ea54b10c 190 int s;
ea54b10c 191 void *buf;
ea54b10c 192 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 193
f95ccffc
JM		 194 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
195 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
196 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
197 for (i = 64; i < s; i += 64) {
198 wqe = buf + i;
199 *wqe = cpu_to_be32(0xffffffff);
ea54b10c 200 }
0e6e7416
RD		 201}
202
225c7b1f
RD		 203static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
204{
205 struct ib_event event;
206 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
207
208 if (type == MLX4_EVENT_TYPE_PATH_MIG)
209 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
210
211 if (ibqp->event_handler) {
212 event.device = ibqp->device;
213 event.element.qp = ibqp;
214 switch (type) {
215 case MLX4_EVENT_TYPE_PATH_MIG:
216 event.event = IB_EVENT_PATH_MIG;
217 break;
218 case MLX4_EVENT_TYPE_COMM_EST:
219 event.event = IB_EVENT_COMM_EST;
220 break;
221 case MLX4_EVENT_TYPE_SQ_DRAINED:
222 event.event = IB_EVENT_SQ_DRAINED;
223 break;
224 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
225 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
226 break;
227 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
228 event.event = IB_EVENT_QP_FATAL;
229 break;
230 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
231 event.event = IB_EVENT_PATH_MIG_ERR;
232 break;
233 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
234 event.event = IB_EVENT_QP_REQ_ERR;
235 break;
236 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
237 event.event = IB_EVENT_QP_ACCESS_ERR;
238 break;
239 default:
987c8f8f 240 pr_warn("Unexpected event type %d "
225c7b1f
RD		 241 "on QP %06x\n", type, qp->qpn);
242 return;
243 }
244
245 ibqp->event_handler(&event, ibqp->qp_context);
246 }
247}
248
400b1ebc
GL		 249static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
250{
251 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
252 type, qp->qpn);
253}
254
1ffeb2eb 255static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
225c7b1f
RD		 256{
257 /*
258 * UD WQEs must have a datagram segment.
259 * RC and UC WQEs might have a remote address segment.
260 * MLX WQEs need two extra inline data segments (for the UD
261 * header and space for the ICRC).
262 */
263 switch (type) {
1ffeb2eb 264 case MLX4_IB_QPT_UD:
225c7b1f 265 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 266 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 267 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
1ffeb2eb
JM		 268 case MLX4_IB_QPT_PROXY_SMI_OWNER:
269 case MLX4_IB_QPT_PROXY_SMI:
270 case MLX4_IB_QPT_PROXY_GSI:
271 return sizeof (struct mlx4_wqe_ctrl_seg) +
272 sizeof (struct mlx4_wqe_datagram_seg) + 64;
273 case MLX4_IB_QPT_TUN_SMI_OWNER:
274 case MLX4_IB_QPT_TUN_GSI:
275 return sizeof (struct mlx4_wqe_ctrl_seg) +
276 sizeof (struct mlx4_wqe_datagram_seg);
277
278 case MLX4_IB_QPT_UC:
225c7b1f
RD		 279 return sizeof (struct mlx4_wqe_ctrl_seg) +
280 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb 281 case MLX4_IB_QPT_RC:
225c7b1f 282 return sizeof (struct mlx4_wqe_ctrl_seg) +
f2940e2c 283 sizeof (struct mlx4_wqe_masked_atomic_seg) +
225c7b1f 284 sizeof (struct mlx4_wqe_raddr_seg);
1ffeb2eb
JM		 285 case MLX4_IB_QPT_SMI:
286 case MLX4_IB_QPT_GSI:
225c7b1f
RD		 287 return sizeof (struct mlx4_wqe_ctrl_seg) +
288 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 289 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
290 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 291 sizeof (struct mlx4_wqe_inline_seg),
292 sizeof (struct mlx4_wqe_data_seg)) +
293 ALIGN(4 +
294 sizeof (struct mlx4_wqe_inline_seg),
295 sizeof (struct mlx4_wqe_data_seg));
296 default:
297 return sizeof (struct mlx4_wqe_ctrl_seg);
298 }
299}
300
2446304d 301static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
913df8c3 302 bool is_user, bool has_rq, struct mlx4_ib_qp *qp,
ea30b966 303 u32 inl_recv_sz)
225c7b1f 304{
2446304d 305 /* Sanity check RQ size before proceeding */
fc2d0044
SG		 306 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
307 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
2446304d
EC		 308 return -EINVAL;
309
0a1405da 310 if (!has_rq) {
ea30b966 311 if (cap->max_recv_wr || inl_recv_sz)
a4cd7ed8 312 return -EINVAL;
2446304d 313
0e6e7416 314 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8 315 } else {
ea30b966
MG		 316 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
317 sizeof(struct mlx4_wqe_data_seg);
318 u32 wqe_size;
319
a4cd7ed8 320 /* HW requires >= 1 RQ entry with >= 1 gather entry */
ea30b966
MG		 321 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
322 inl_recv_sz > max_inl_recv_sz))
a4cd7ed8
RD		 323 return -EINVAL;
324
0e6e7416 325 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 326 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
ea30b966
MG		 327 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
328 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
a4cd7ed8 329 }
2446304d 330
fc2d0044
SG		 331 /* leave userspace return values as they were, so as not to break ABI */
332 if (is_user) {
333 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
334 cap->max_recv_sge = qp->rq.max_gs;
335 } else {
336 cap->max_recv_wr = qp->rq.max_post =
337 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
338 cap->max_recv_sge = min(qp->rq.max_gs,
339 min(dev->dev->caps.max_sq_sg,
340 dev->dev->caps.max_rq_sg));
341 }
2446304d
EC		 342
343 return 0;
344}
345
346static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
f95ccffc 347 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
2446304d 348{
ea54b10c
JM		 349 int s;
350
2446304d 351 /* Sanity check SQ size before proceeding */
fc2d0044
SG		 352 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
353 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
b832be1e 354 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 355 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
356 return -EINVAL;
357
358 /*
359 * For MLX transport we need 2 extra S/G entries:
360 * one for the header and one for the checksum at the end
361 */
1ffeb2eb
JM		 362 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
363 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
225c7b1f
RD		 364 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
365 return -EINVAL;
366
ea54b10c
JM		 367 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
368 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 369 send_wqe_overhead(type, qp->flags);
225c7b1f 370
cd155c1c
RD		 371 if (s > dev->dev->caps.max_sq_desc_sz)
372 return -EINVAL;
373
f95ccffc
JM		 374 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
375
0e6e7416 376 /*
f95ccffc
JM		 377 * We need to leave 2 KB + 1 WR of headroom in the SQ to
378 * allow HW to prefetch.
0e6e7416 379 */
350b4c8a 380 qp->sq_spare_wqes = MLX4_IB_SQ_HEADROOM(qp->sq.wqe_shift);
f95ccffc
JM		 381 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
382 qp->sq_spare_wqes);
383
384 qp->sq.max_gs =
385 (min(dev->dev->caps.max_sq_desc_sz,
386 (1 << qp->sq.wqe_shift)) -
387 send_wqe_overhead(type, qp->flags)) /
b832be1e 388 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 389
390 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
391 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 392 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
393 qp->rq.offset = 0;
0e6e7416 394 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 395 } else {
0e6e7416 396 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 397 qp->sq.offset = 0;
398 }
399
ea54b10c 400 cap->max_send_wr = qp->sq.max_post =
f95ccffc 401 qp->sq.wqe_cnt - qp->sq_spare_wqes;
cd155c1c
RD		 402 cap->max_send_sge = min(qp->sq.max_gs,
403 min(dev->dev->caps.max_sq_sg,
404 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 405 /* We don't support inline sends for kernel QPs (yet) */
406 cap->max_inline_data = 0;
225c7b1f
RD		 407
408 return 0;
409}
410
83904132
JM		 411static int set_user_sq_size(struct mlx4_ib_dev *dev,
412 struct mlx4_ib_qp *qp,
2446304d
EC		 413 struct mlx4_ib_create_qp *ucmd)
414{
83904132
JM		 415 /* Sanity check SQ size before proceeding */
416 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
417 ucmd->log_sq_stride >
418 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
419 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
420 return -EINVAL;
421
0e6e7416 422 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 423 qp->sq.wqe_shift = ucmd->log_sq_stride;
424
0e6e7416
RD		 425 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
426 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 427
428 return 0;
429}
430
1ffeb2eb
JM		 431static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
432{
433 int i;
434
435 qp->sqp_proxy_rcv =
6da2ec56
KC		 436 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
437 GFP_KERNEL);
1ffeb2eb
JM		 438 if (!qp->sqp_proxy_rcv)
439 return -ENOMEM;
440 for (i = 0; i < qp->rq.wqe_cnt; i++) {
441 qp->sqp_proxy_rcv[i].addr =
442 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
443 GFP_KERNEL);
444 if (!qp->sqp_proxy_rcv[i].addr)
445 goto err;
446 qp->sqp_proxy_rcv[i].map =
447 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
448 sizeof (struct mlx4_ib_proxy_sqp_hdr),
449 DMA_FROM_DEVICE);
cc47d369
SO		 450 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
451 kfree(qp->sqp_proxy_rcv[i].addr);
452 goto err;
453 }
1ffeb2eb
JM		 454 }
455 return 0;
456
457err:
458 while (i > 0) {
459 --i;
460 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
461 sizeof (struct mlx4_ib_proxy_sqp_hdr),
462 DMA_FROM_DEVICE);
463 kfree(qp->sqp_proxy_rcv[i].addr);
464 }
465 kfree(qp->sqp_proxy_rcv);
466 qp->sqp_proxy_rcv = NULL;
467 return -ENOMEM;
468}
469
470static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
471{
472 int i;
473
474 for (i = 0; i < qp->rq.wqe_cnt; i++) {
475 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
476 sizeof (struct mlx4_ib_proxy_sqp_hdr),
477 DMA_FROM_DEVICE);
478 kfree(qp->sqp_proxy_rcv[i].addr);
479 }
480 kfree(qp->sqp_proxy_rcv);
481}
482
913df8c3 483static bool qp_has_rq(struct ib_qp_init_attr *attr)
0a1405da
SH		 484{
485 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
913df8c3 486 return false;
0a1405da
SH		 487
488 return !attr->srq;
489}
490
99ec41d0
JM		 491static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
492{
493 int i;
494 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 495 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
496 return !!dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 497 }
498 return 0;
499}
500
7b59f0f9
EBE		 501static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
502 struct mlx4_ib_qp *qp)
503{
504 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
505 mlx4_counter_free(dev->dev, qp->counter_index->index);
506 list_del(&qp->counter_index->list);
507 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
508
509 kfree(qp->counter_index);
510 qp->counter_index = NULL;
511}
512
3078f5f1
GL		 513static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
514 struct ib_qp_init_attr *init_attr,
515 struct mlx4_ib_create_qp_rss *ucmd)
516{
517 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
518 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
519
520 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
521 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
522 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
523 MLX4_EN_RSS_KEY_SIZE);
524 } else {
525 pr_debug("RX Hash function is not supported\n");
526 return (-EOPNOTSUPP);
527 }
528
4d02ebd9
GL		 529 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
530 MLX4_IB_RX_HASH_DST_IPV4 |
531 MLX4_IB_RX_HASH_SRC_IPV6 |
532 MLX4_IB_RX_HASH_DST_IPV6 |
533 MLX4_IB_RX_HASH_SRC_PORT_TCP |
534 MLX4_IB_RX_HASH_DST_PORT_TCP |
535 MLX4_IB_RX_HASH_SRC_PORT_UDP |
4f9ca2d8
LR		 536 MLX4_IB_RX_HASH_DST_PORT_UDP |
537 MLX4_IB_RX_HASH_INNER)) {
4d02ebd9
GL		 538 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
539 ucmd->rx_hash_fields_mask);
540 return (-EOPNOTSUPP);
541 }
542
3078f5f1
GL		 543 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
544 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
545 rss_ctx->flags = MLX4_RSS_IPV4;
546 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
547 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
548 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
549 return (-EOPNOTSUPP);
550 }
551
552 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
553 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
554 rss_ctx->flags |= MLX4_RSS_IPV6;
555 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
556 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
557 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
558 return (-EOPNOTSUPP);
559 }
560
561 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
562 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
563 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
564 pr_debug("RX Hash fields_mask for UDP is not supported\n");
565 return (-EOPNOTSUPP);
566 }
567
4d02ebd9 568 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 569 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
4d02ebd9 570 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 571 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
4d02ebd9 572 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 573 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
574 return (-EOPNOTSUPP);
575 }
576 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
577 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
578 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
579 return (-EOPNOTSUPP);
580 }
581
582 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
583 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
4d02ebd9 584 if (rss_ctx->flags & MLX4_RSS_IPV4)
3078f5f1 585 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
4d02ebd9 586 if (rss_ctx->flags & MLX4_RSS_IPV6)
3078f5f1 587 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
4d02ebd9 588 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
3078f5f1
GL		 589 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
590 return (-EOPNOTSUPP);
591 }
3078f5f1
GL		 592 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
593 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
594 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
595 return (-EOPNOTSUPP);
596 }
597
07d84f7b
GL		 598 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
599 if (dev->dev->caps.tunnel_offload_mode ==
600 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
601 /*
602 * Hash according to inner headers if exist, otherwise
603 * according to outer headers.
604 */
605 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
606 } else {
607 pr_debug("RSS Hash for inner headers isn't supported\n");
608 return (-EOPNOTSUPP);
609 }
610 }
611
3078f5f1
GL		 612 return 0;
613}
614
d7c0557a 615static int create_qp_rss(struct mlx4_ib_dev *dev,
3078f5f1
GL		 616 struct ib_qp_init_attr *init_attr,
617 struct mlx4_ib_create_qp_rss *ucmd,
618 struct mlx4_ib_qp *qp)
619{
620 int qpn;
621 int err;
622
623 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
624
625 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
626 if (err)
627 return err;
628
629 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
630 if (err)
631 goto err_qpn;
632
3078f5f1
GL		 633 INIT_LIST_HEAD(&qp->gid_list);
634 INIT_LIST_HEAD(&qp->steering_rules);
635
c3f1ee29 636 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
3078f5f1
GL		 637 qp->state = IB_QPS_RESET;
638
639 /* Set dummy send resources to be compatible with HV and PRM */
640 qp->sq_no_prefetch = 1;
641 qp->sq.wqe_cnt = 1;
642 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
643 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
644 qp->mtt = (to_mqp(
645 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
646
647 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
648 if (!qp->rss_ctx) {
649 err = -ENOMEM;
650 goto err_qp_alloc;
651 }
652
653 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
654 if (err)
655 goto err;
656
657 return 0;
658
659err:
660 kfree(qp->rss_ctx);
661
662err_qp_alloc:
663 mlx4_qp_remove(dev->dev, &qp->mqp);
664 mlx4_qp_free(dev->dev, &qp->mqp);
665
666err_qpn:
667 mlx4_qp_release_range(dev->dev, qpn, 1);
668 return err;
669}
670
8fd3cd2a
LR		 671static int _mlx4_ib_create_qp_rss(struct ib_pd *pd, struct mlx4_ib_qp *qp,
672 struct ib_qp_init_attr *init_attr,
673 struct ib_udata *udata)
3078f5f1 674{
3078f5f1
GL		 675 struct mlx4_ib_create_qp_rss ucmd = {};
676 size_t required_cmd_sz;
677 int err;
678
679 if (!udata) {
680 pr_debug("RSS QP with NULL udata\n");
8fd3cd2a 681 return -EINVAL;
3078f5f1
GL		 682 }
683
684 if (udata->outlen)
8fd3cd2a 685 return -EOPNOTSUPP;
3078f5f1
GL		 686
687 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
688 sizeof(ucmd.reserved1);
689 if (udata->inlen < required_cmd_sz) {
690 pr_debug("invalid inlen\n");
8fd3cd2a 691 return -EINVAL;
3078f5f1
GL		 692 }
693
694 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
695 pr_debug("copy failed\n");
8fd3cd2a 696 return -EFAULT;
3078f5f1
GL		 697 }
698
f9bfea99 699 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
8fd3cd2a 700 return -EOPNOTSUPP;
f9bfea99 701
3078f5f1 702 if (ucmd.comp_mask || ucmd.reserved1)
8fd3cd2a 703 return -EOPNOTSUPP;
3078f5f1
GL		 704
705 if (udata->inlen > sizeof(ucmd) &&
706 !ib_is_udata_cleared(udata, sizeof(ucmd),
707 udata->inlen - sizeof(ucmd))) {
708 pr_debug("inlen is not supported\n");
8fd3cd2a 709 return -EOPNOTSUPP;
3078f5f1
GL		 710 }
711
712 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
713 pr_debug("RSS QP with unsupported QP type %d\n",
714 init_attr->qp_type);
8fd3cd2a 715 return -EOPNOTSUPP;
3078f5f1
GL		 716 }
717
718 if (init_attr->create_flags) {
719 pr_debug("RSS QP doesn't support create flags\n");
8fd3cd2a 720 return -EOPNOTSUPP;
3078f5f1
GL		 721 }
722
723 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
724 pr_debug("RSS QP with unsupported send attributes\n");
8fd3cd2a 725 return -EOPNOTSUPP;
3078f5f1
GL		 726 }
727
3078f5f1
GL		 728 qp->pri.vid = 0xFFFF;
729 qp->alt.vid = 0xFFFF;
730
d7c0557a 731 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
8fd3cd2a
LR		 732 if (err)
733 return err;
3078f5f1
GL		 734
735 qp->ibqp.qp_num = qp->mqp.qpn;
8fd3cd2a 736 return 0;
3078f5f1
GL		 737}
738
400b1ebc
GL		 739/*
740 * This function allocates a WQN from a range which is consecutive and aligned
741 * to its size. In case the range is full, then it creates a new range and
742 * allocates WQN from it. The new range will be used for following allocations.
743 */
744static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
745 struct mlx4_ib_qp *qp, int range_size, int *wqn)
746{
747 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
748 struct mlx4_wqn_range *range;
749 int err = 0;
750
751 mutex_lock(&context->wqn_ranges_mutex);
752
753 range = list_first_entry_or_null(&context->wqn_ranges_list,
754 struct mlx4_wqn_range, list);
755
756 if (!range || (range->refcount == range->size) || range->dirty) {
757 range = kzalloc(sizeof(*range), GFP_KERNEL);
758 if (!range) {
759 err = -ENOMEM;
760 goto out;
761 }
762
763 err = mlx4_qp_reserve_range(dev->dev, range_size,
764 range_size, &range->base_wqn, 0,
765 qp->mqp.usage);
766 if (err) {
767 kfree(range);
768 goto out;
769 }
770
771 range->size = range_size;
772 list_add(&range->list, &context->wqn_ranges_list);
773 } else if (range_size != 1) {
774 /*
775 * Requesting a new range (>1) when last range is still open, is
776 * not valid.
777 */
778 err = -EINVAL;
779 goto out;
780 }
781
782 qp->wqn_range = range;
783
784 *wqn = range->base_wqn + range->refcount;
785
786 range->refcount++;
787
788out:
789 mutex_unlock(&context->wqn_ranges_mutex);
790
791 return err;
792}
793
794static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
795 struct mlx4_ib_qp *qp, bool dirty_release)
796{
797 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
798 struct mlx4_wqn_range *range;
799
800 mutex_lock(&context->wqn_ranges_mutex);
801
802 range = qp->wqn_range;
803
804 range->refcount--;
805 if (!range->refcount) {
806 mlx4_qp_release_range(dev->dev, range->base_wqn,
807 range->size);
808 list_del(&range->list);
809 kfree(range);
810 } else if (dirty_release) {
811 /*
812 * A range which one of its WQNs is destroyed, won't be able to be
813 * reused for further WQN allocations.
814 * The next created WQ will allocate a new range.
815 */
cf368beb 816 range->dirty = true;
400b1ebc
GL		 817 }
818
819 mutex_unlock(&context->wqn_ranges_mutex);
820}
821
089b645d
LR		 822static int create_rq(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
823 struct ib_udata *udata, struct mlx4_ib_qp *qp)
824{
825 struct mlx4_ib_dev *dev = to_mdev(pd->device);
826 int qpn;
827 int err;
828 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
829 udata, struct mlx4_ib_ucontext, ibucontext);
830 struct mlx4_ib_cq *mcq;
831 unsigned long flags;
832 int range_size;
833 struct mlx4_ib_create_wq wq;
834 size_t copy_len;
835 int shift;
836 int n;
837
838 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
839
089b645d
LR		 840 spin_lock_init(&qp->sq.lock);
841 spin_lock_init(&qp->rq.lock);
842 INIT_LIST_HEAD(&qp->gid_list);
843 INIT_LIST_HEAD(&qp->steering_rules);
844
845 qp->state = IB_QPS_RESET;
846
847 copy_len = min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
848
849 if (ib_copy_from_udata(&wq, udata, copy_len)) {
850 err = -EFAULT;
851 goto err;
852 }
853
854 if (wq.comp_mask || wq.reserved[0] || wq.reserved[1] ||
855 wq.reserved[2]) {
856 pr_debug("user command isn't supported\n");
857 err = -EOPNOTSUPP;
858 goto err;
859 }
860
861 if (wq.log_range_size > ilog2(dev->dev->caps.max_rss_tbl_sz)) {
862 pr_debug("WQN range size must be equal or smaller than %d\n",
863 dev->dev->caps.max_rss_tbl_sz);
864 err = -EOPNOTSUPP;
865 goto err;
866 }
867 range_size = 1 << wq.log_range_size;
868
869 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS)
870 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
871
913df8c3 872 err = set_rq_size(dev, &init_attr->cap, true, true, qp, qp->inl_recv_sz);
089b645d
LR		 873 if (err)
874 goto err;
875
876 qp->sq_no_prefetch = 1;
877 qp->sq.wqe_cnt = 1;
878 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
879 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
880 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
881
c320e527 882 qp->umem = ib_umem_get(pd->device, wq.buf_addr, qp->buf_size, 0);
089b645d
LR		 883 if (IS_ERR(qp->umem)) {
884 err = PTR_ERR(qp->umem);
885 goto err;
886 }
887
089b645d
LR		 888 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
889 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
890
891 if (err)
892 goto err_buf;
893
894 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
895 if (err)
896 goto err_mtt;
897
898 err = mlx4_ib_db_map_user(udata, wq.db_addr, &qp->db);
899 if (err)
900 goto err_mtt;
901 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
902
903 err = mlx4_ib_alloc_wqn(context, qp, range_size, &qpn);
904 if (err)
905 goto err_wrid;
906
907 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
908 if (err)
909 goto err_qpn;
910
911 /*
912 * Hardware wants QPN written in big-endian order (after
913 * shifting) for send doorbell. Precompute this value to save
914 * a little bit when posting sends.
915 */
916 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
917
918 qp->mqp.event = mlx4_ib_wq_event;
919
920 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
921 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
922 to_mcq(init_attr->recv_cq));
923 /* Maintain device to QPs access, needed for further handling
924 * via reset flow
925 */
926 list_add_tail(&qp->qps_list, &dev->qp_list);
927 /* Maintain CQ to QPs access, needed for further handling
928 * via reset flow
929 */
930 mcq = to_mcq(init_attr->send_cq);
931 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
932 mcq = to_mcq(init_attr->recv_cq);
933 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
934 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
935 to_mcq(init_attr->recv_cq));
936 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
937 return 0;
938
939err_qpn:
940 mlx4_ib_release_wqn(context, qp, 0);
941err_wrid:
942 mlx4_ib_db_unmap_user(context, &qp->db);
943
944err_mtt:
945 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
946err_buf:
947 ib_umem_release(qp->umem);
948err:
949 return err;
950}
951
952static int create_qp_common(struct ib_pd *pd, struct ib_qp_init_attr *init_attr,
8900b894 953 struct ib_udata *udata, int sqpn,
8fd3cd2a 954 struct mlx4_ib_qp *qp)
225c7b1f 955{
089b645d 956 struct mlx4_ib_dev *dev = to_mdev(pd->device);
a3cdcbfa 957 int qpn;
225c7b1f 958 int err;
89944450
SR		 959 struct mlx4_ib_ucontext *context = rdma_udata_to_drv_context(
960 udata, struct mlx4_ib_ucontext, ibucontext);
1ffeb2eb 961 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
35f05dab
YH		 962 struct mlx4_ib_cq *mcq;
963 unsigned long flags;
1ffeb2eb
JM		 964
965 /* When tunneling special qps, we use a plain UD qp */
966 if (sqpn) {
967 if (mlx4_is_mfunc(dev->dev) &&
968 (!mlx4_is_master(dev->dev) ||
969 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
970 if (init_attr->qp_type == IB_QPT_GSI)
971 qp_type = MLX4_IB_QPT_PROXY_GSI;
99ec41d0
JM		 972 else {
973 if (mlx4_is_master(dev->dev) ||
974 qp0_enabled_vf(dev->dev, sqpn))
975 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
976 else
977 qp_type = MLX4_IB_QPT_PROXY_SMI;
978 }
1ffeb2eb
JM		 979 }
980 qpn = sqpn;
981 /* add extra sg entry for tunneling */
982 init_attr->cap.max_recv_sge++;
983 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
984 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
985 container_of(init_attr,
986 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
987 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
988 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
989 !mlx4_is_master(dev->dev))
990 return -EINVAL;
991 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
992 qp_type = MLX4_IB_QPT_TUN_GSI;
99ec41d0
JM		 993 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
994 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
995 tnl_init->port))
1ffeb2eb
JM		 996 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
997 else
998 qp_type = MLX4_IB_QPT_TUN_SMI;
47605df9
JM		 999 /* we are definitely in the PPF here, since we are creating
1000 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1001 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1002 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1ffeb2eb
JM		 1003 sqpn = qpn;
1004 }
1005
8fd3cd2a
LR		 1006 if (init_attr->qp_type == IB_QPT_SMI ||
1007 init_attr->qp_type == IB_QPT_GSI || qp_type == MLX4_IB_QPT_SMI ||
1008 qp_type == MLX4_IB_QPT_GSI ||
1009 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1010 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1011 qp->sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1012 if (!qp->sqp)
915ec7ed 1013 return -ENOMEM;
8fd3cd2a 1014 }
1ffeb2eb
JM		 1015
1016 qp->mlx4_ib_qp_type = qp_type;
225c7b1f 1017
225c7b1f
RD		 1018 spin_lock_init(&qp->sq.lock);
1019 spin_lock_init(&qp->rq.lock);
fa417f7b 1020 INIT_LIST_HEAD(&qp->gid_list);
0ff1fb65 1021 INIT_LIST_HEAD(&qp->steering_rules);
225c7b1f 1022
089b645d 1023 qp->state = IB_QPS_RESET;
ea54b10c
JM		 1024 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1025 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 1026
e00b64f7 1027 if (udata) {
089b645d 1028 struct mlx4_ib_create_qp ucmd;
400b1ebc 1029 size_t copy_len;
ed8637d3
GL		 1030 int shift;
1031 int n;
400b1ebc 1032
089b645d 1033 copy_len = sizeof(struct mlx4_ib_create_qp);
225c7b1f 1034
400b1ebc 1035 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
225c7b1f
RD		 1036 err = -EFAULT;
1037 goto err;
1038 }
1039
089b645d 1040 qp->inl_recv_sz = ucmd.inl_recv_sz;
0e6e7416 1041
6d06c9aa
GL		 1042 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1043 if (!(dev->dev->caps.flags &
1044 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
1045 pr_debug("scatter FCS is unsupported\n");
1046 err = -EOPNOTSUPP;
1047 goto err;
1048 }
1049
1050 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
1051 }
1052
e00b64f7 1053 err = set_rq_size(dev, &init_attr->cap, udata,
400b1ebc 1054 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
2446304d
EC		 1055 if (err)
1056 goto err;
1057
089b645d 1058 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
400b1ebc 1059
089b645d
LR		 1060 err = set_user_sq_size(dev, qp, &ucmd);
1061 if (err)
1062 goto err;
400b1ebc 1063
c320e527
MS		 1064 qp->umem =
1065 ib_umem_get(pd->device, ucmd.buf_addr, qp->buf_size, 0);
225c7b1f
RD		 1066 if (IS_ERR(qp->umem)) {
1067 err = PTR_ERR(qp->umem);
1068 goto err;
1069 }
1070
ed8637d3
GL		 1071 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1072 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1073
225c7b1f
RD		 1074 if (err)
1075 goto err_buf;
1076
1077 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1078 if (err)
1079 goto err_mtt;
1080
0a1405da 1081 if (qp_has_rq(init_attr)) {
089b645d 1082 err = mlx4_ib_db_map_user(udata, ucmd.db_addr, &qp->db);
02d89b87
RD		 1083 if (err)
1084 goto err_mtt;
1085 }
f3301870 1086 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
225c7b1f 1087 } else {
e00b64f7 1088 err = set_rq_size(dev, &init_attr->cap, udata,
ea30b966
MG		 1089 qp_has_rq(init_attr), qp, 0);
1090 if (err)
1091 goto err;
1092
0e6e7416
RD		 1093 qp->sq_no_prefetch = 0;
1094
b832be1e
EC		 1095 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1096 qp->flags |= MLX4_IB_QP_LSO;
1097
c1c98501
MB		 1098 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1099 if (dev->steering_support ==
1100 MLX4_STEERING_MODE_DEVICE_MANAGED)
1101 qp->flags |= MLX4_IB_QP_NETIF;
1102 else
1103 goto err;
1104 }
1105
f95ccffc 1106 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
2446304d
EC		 1107 if (err)
1108 goto err;
1109
0a1405da 1110 if (qp_has_rq(init_attr)) {
8900b894 1111 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 1112 if (err)
1113 goto err;
225c7b1f 1114
02d89b87
RD		 1115 *qp->db.db = 0;
1116 }
225c7b1f 1117
f95ccffc 1118 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
8900b894 1119 &qp->buf)) {
f95ccffc
JM		 1120 err = -ENOMEM;
1121 goto err_db;
225c7b1f
RD		 1122 }
1123
1124 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1125 &qp->mtt);
1126 if (err)
1127 goto err_buf;
1128
8900b894 1129 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
225c7b1f
RD		 1130 if (err)
1131 goto err_mtt;
1132
e9105cde
LD		 1133 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1134 sizeof(u64), GFP_KERNEL);
1135 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1136 sizeof(u64), GFP_KERNEL);
225c7b1f
RD		 1137 if (!qp->sq.wrid || !qp->rq.wrid) {
1138 err = -ENOMEM;
1139 goto err_wrid;
1140 }
f3301870 1141 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
225c7b1f
RD		 1142 }
1143
a3cdcbfa 1144 if (sqpn) {
1ffeb2eb
JM		 1145 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1146 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1147 if (alloc_proxy_bufs(pd->device, qp)) {
1148 err = -ENOMEM;
1149 goto err_wrid;
1150 }
1151 }
a3cdcbfa 1152 } else {
ddae0349
EE		 1153 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1154 * otherwise, the WQE BlueFlame setup flow wrongly causes
1155 * VLAN insertion. */
3987a2d3 1156 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
ddae0349 1157 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
d57febe1
MB		 1158 (init_attr->cap.max_send_wr ?
1159 MLX4_RESERVE_ETH_BF_QP : 0) |
1160 (init_attr->cap.max_recv_wr ?
f3301870
MS		 1161 MLX4_RESERVE_A0_QP : 0),
1162 qp->mqp.usage);
3987a2d3 1163 else
c1c98501
MB		 1164 if (qp->flags & MLX4_IB_QP_NETIF)
1165 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1166 else
1167 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
f3301870 1168 &qpn, 0, qp->mqp.usage);
a3cdcbfa 1169 if (err)
1ffeb2eb 1170 goto err_proxy;
a3cdcbfa
YP		 1171 }
1172
fbfb6625
EBE		 1173 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1174 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1175
8900b894 1176 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 1177 if (err)
a3cdcbfa 1178 goto err_qpn;
225c7b1f 1179
0a1405da
SH		 1180 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1181 qp->mqp.qpn |= (1 << 23);
1182
225c7b1f
RD		 1183 /*
1184 * Hardware wants QPN written in big-endian order (after
1185 * shifting) for send doorbell. Precompute this value to save
1186 * a little bit when posting sends.
1187 */
1188 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1189
089b645d 1190 qp->mqp.event = mlx4_ib_qp_event;
400b1ebc 1191
35f05dab
YH		 1192 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1193 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1194 to_mcq(init_attr->recv_cq));
1195 /* Maintain device to QPs access, needed for further handling
1196 * via reset flow
1197 */
1198 list_add_tail(&qp->qps_list, &dev->qp_list);
1199 /* Maintain CQ to QPs access, needed for further handling
1200 * via reset flow
1201 */
1202 mcq = to_mcq(init_attr->send_cq);
1203 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1204 mcq = to_mcq(init_attr->recv_cq);
1205 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1206 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1207 to_mcq(init_attr->recv_cq));
1208 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1209 return 0;
1210
a3cdcbfa 1211err_qpn:
c1c98501
MB		 1212 if (!sqpn) {
1213 if (qp->flags & MLX4_IB_QP_NETIF)
1214 mlx4_ib_steer_qp_free(dev, qpn, 1);
1215 else
1216 mlx4_qp_release_range(dev->dev, qpn, 1);
1217 }
1ffeb2eb
JM		 1218err_proxy:
1219 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1220 free_proxy_bufs(pd->device, qp);
225c7b1f 1221err_wrid:
e00b64f7 1222 if (udata) {
0a1405da 1223 if (qp_has_rq(init_attr))
89944450 1224 mlx4_ib_db_unmap_user(context, &qp->db);
23f1b384 1225 } else {
0ef2f05c
WW		 1226 kvfree(qp->sq.wrid);
1227 kvfree(qp->rq.wrid);
225c7b1f
RD		 1228 }
1229
1230err_mtt:
1231 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1232
1233err_buf:
836a0fbb 1234 if (!qp->umem)
225c7b1f 1235 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
836a0fbb 1236 ib_umem_release(qp->umem);
225c7b1f
RD		 1237
1238err_db:
e00b64f7 1239 if (!udata && qp_has_rq(init_attr))
6296883c 1240 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 1241
1242err:
8fd3cd2a 1243 kfree(qp->sqp);
225c7b1f
RD		 1244 return err;
1245}
1246
1247static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1248{
1249 switch (state) {
1250 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1251 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1252 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1253 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1254 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1255 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1256 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1257 default: return -1;
1258 }
1259}
1260
1261static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1262 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 1263{
338a8fad 1264 if (send_cq == recv_cq) {
35f05dab 1265 spin_lock(&send_cq->lock);
338a8fad
RD		 1266 __acquire(&recv_cq->lock);
1267 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
35f05dab 1268 spin_lock(&send_cq->lock);
225c7b1f
RD		 1269 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1270 } else {
35f05dab 1271 spin_lock(&recv_cq->lock);
225c7b1f
RD		 1272 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1273 }
1274}
1275
1276static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 1277 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 1278{
338a8fad
RD		 1279 if (send_cq == recv_cq) {
1280 __release(&recv_cq->lock);
35f05dab 1281 spin_unlock(&send_cq->lock);
338a8fad 1282 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f 1283 spin_unlock(&recv_cq->lock);
35f05dab 1284 spin_unlock(&send_cq->lock);
225c7b1f
RD		 1285 } else {
1286 spin_unlock(&send_cq->lock);
35f05dab 1287 spin_unlock(&recv_cq->lock);
225c7b1f
RD		 1288 }
1289}
1290
fa417f7b
EC		 1291static void del_gid_entries(struct mlx4_ib_qp *qp)
1292{
1293 struct mlx4_ib_gid_entry *ge, *tmp;
1294
1295 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1296 list_del(&ge->list);
1297 kfree(ge);
1298 }
1299}
1300
0a1405da
SH		 1301static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1302{
1303 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1304 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1305 else
1306 return to_mpd(qp->ibqp.pd);
1307}
1308
400b1ebc 1309static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
0a1405da
SH		 1310 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1311{
1312 switch (qp->ibqp.qp_type) {
1313 case IB_QPT_XRC_TGT:
1314 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1315 *recv_cq = *send_cq;
1316 break;
1317 case IB_QPT_XRC_INI:
1318 *send_cq = to_mcq(qp->ibqp.send_cq);
1319 *recv_cq = *send_cq;
1320 break;
1321 default:
400b1ebc
GL		 1322 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1323 to_mcq(qp->ibwq.cq);
1324 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1325 *recv_cq;
0a1405da
SH		 1326 break;
1327 }
1328}
1329
3078f5f1
GL		 1330static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1331{
1332 if (qp->state != IB_QPS_RESET) {
1333 int i;
1334
1335 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1336 i++) {
1337 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1338 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1339
1340 mutex_lock(&wq->mutex);
1341
1342 wq->rss_usecnt--;
1343
1344 mutex_unlock(&wq->mutex);
1345 }
1346
1347 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1348 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1349 pr_warn("modify QP %06x to RESET failed.\n",
1350 qp->mqp.qpn);
1351 }
1352
1353 mlx4_qp_remove(dev->dev, &qp->mqp);
1354 mlx4_qp_free(dev->dev, &qp->mqp);
1355 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1356 del_gid_entries(qp);
3078f5f1
GL		 1357}
1358
225c7b1f 1359static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
bdeacabd
SR		 1360 enum mlx4_ib_source_type src,
1361 struct ib_udata *udata)
225c7b1f
RD		 1362{
1363 struct mlx4_ib_cq *send_cq, *recv_cq;
35f05dab 1364 unsigned long flags;
225c7b1f 1365
2f5bb473 1366 if (qp->state != IB_QPS_RESET) {
225c7b1f
RD		 1367 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1368 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
987c8f8f 1369 pr_warn("modify QP %06x to RESET failed.\n",
225c7b1f 1370 qp->mqp.qpn);
25476b02 1371 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 1372 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1373 qp->pri.smac = 0;
25476b02 1374 qp->pri.smac_port = 0;
2f5bb473
JM		 1375 }
1376 if (qp->alt.smac) {
1377 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1378 qp->alt.smac = 0;
1379 }
1380 if (qp->pri.vid < 0x1000) {
1381 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1382 qp->pri.vid = 0xFFFF;
1383 qp->pri.candidate_vid = 0xFFFF;
1384 qp->pri.update_vid = 0;
1385 }
1386 if (qp->alt.vid < 0x1000) {
1387 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1388 qp->alt.vid = 0xFFFF;
1389 qp->alt.candidate_vid = 0xFFFF;
1390 qp->alt.update_vid = 0;
1391 }
1392 }
225c7b1f 1393
400b1ebc 1394 get_cqs(qp, src, &send_cq, &recv_cq);
225c7b1f 1395
35f05dab 1396 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1397 mlx4_ib_lock_cqs(send_cq, recv_cq);
1398
35f05dab
YH		 1399 /* del from lists under both locks above to protect reset flow paths */
1400 list_del(&qp->qps_list);
1401 list_del(&qp->cq_send_list);
1402 list_del(&qp->cq_recv_list);
bdeacabd 1403 if (!udata) {
225c7b1f
RD		 1404 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1405 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1406 if (send_cq != recv_cq)
1407 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1408 }
1409
1410 mlx4_qp_remove(dev->dev, &qp->mqp);
1411
1412 mlx4_ib_unlock_cqs(send_cq, recv_cq);
35f05dab 1413 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
225c7b1f
RD		 1414
1415 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa 1416
c1c98501
MB		 1417 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1418 if (qp->flags & MLX4_IB_QP_NETIF)
1419 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
400b1ebc 1420 else if (src == MLX4_IB_RWQ_SRC)
bdeacabd
SR		 1421 mlx4_ib_release_wqn(
1422 rdma_udata_to_drv_context(
1423 udata,
1424 struct mlx4_ib_ucontext,
1425 ibucontext),
1426 qp, 1);
c1c98501
MB		 1427 else
1428 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1429 }
a3cdcbfa 1430
225c7b1f
RD		 1431 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1432
bdeacabd 1433 if (udata) {
400b1ebc 1434 if (qp->rq.wqe_cnt) {
bdeacabd
SR		 1435 struct mlx4_ib_ucontext *mcontext =
1436 rdma_udata_to_drv_context(
1437 udata,
1438 struct mlx4_ib_ucontext,
1439 ibucontext);
1440
400b1ebc
GL		 1441 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1442 }
225c7b1f 1443 } else {
0ef2f05c
WW		 1444 kvfree(qp->sq.wrid);
1445 kvfree(qp->rq.wrid);
1ffeb2eb
JM		 1446 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1447 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1448 free_proxy_bufs(&dev->ib_dev, qp);
225c7b1f 1449 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
0a1405da 1450 if (qp->rq.wqe_cnt)
6296883c 1451 mlx4_db_free(dev->dev, &qp->db);
225c7b1f 1452 }
836a0fbb 1453 ib_umem_release(qp->umem);
fa417f7b
EC		 1454
1455 del_gid_entries(qp);
225c7b1f
RD		 1456}
1457
47605df9
JM		 1458static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1459{
1460 /* Native or PPF */
1461 if (!mlx4_is_mfunc(dev->dev) ||
1462 (mlx4_is_master(dev->dev) &&
1463 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1464 return dev->dev->phys_caps.base_sqpn +
1465 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1466 attr->port_num - 1;
1467 }
1468 /* PF or VF -- creating proxies */
1469 if (attr->qp_type == IB_QPT_SMI)
c73c8b1e 1470 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
47605df9 1471 else
c73c8b1e 1472 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
47605df9
JM		 1473}
1474
8fd3cd2a
LR		 1475static int _mlx4_ib_create_qp(struct ib_pd *pd, struct mlx4_ib_qp *qp,
1476 struct ib_qp_init_attr *init_attr,
1477 struct ib_udata *udata)
225c7b1f 1478{
225c7b1f 1479 int err;
fbfb6625 1480 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
0a1405da 1481 u16 xrcdn = 0;
225c7b1f 1482
3078f5f1 1483 if (init_attr->rwq_ind_tbl)
8fd3cd2a 1484 return _mlx4_ib_create_qp_rss(pd, qp, init_attr, udata);
3078f5f1 1485
521e575b 1486 /*
1ffeb2eb
JM		 1487 * We only support LSO, vendor flag1, and multicast loopback blocking,
1488 * and only for kernel UD QPs.
521e575b 1489 */
1ffeb2eb
JM		 1490 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1491 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
c1c98501
MB		 1492 MLX4_IB_SRIOV_TUNNEL_QP |
1493 MLX4_IB_SRIOV_SQP |
40f2287b 1494 MLX4_IB_QP_NETIF |
8900b894 1495 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1f11a761 1496 return -EOPNOTSUPP;
521e575b 1497
c1c98501
MB		 1498 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1499 if (init_attr->qp_type != IB_QPT_UD)
8fd3cd2a 1500 return -EINVAL;
c1c98501
MB		 1501 }
1502
e1b866c6
MS		 1503 if (init_attr->create_flags) {
1504 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
8fd3cd2a 1505 return -EINVAL;
e1b866c6
MS		 1506
1507 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
e1b866c6
MS		 1508 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1509 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1510 init_attr->qp_type != IB_QPT_UD) ||
1511 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1512 init_attr->qp_type > IB_QPT_GSI) ||
1513 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1514 init_attr->qp_type != IB_QPT_GSI))
8fd3cd2a 1515 return -EINVAL;
e1b866c6 1516 }
b846f25a 1517
225c7b1f 1518 switch (init_attr->qp_type) {
0a1405da
SH		 1519 case IB_QPT_XRC_TGT:
1520 pd = to_mxrcd(init_attr->xrcd)->pd;
1521 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1522 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
df561f66 1523 fallthrough;
0a1405da
SH		 1524 case IB_QPT_XRC_INI:
1525 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
8fd3cd2a 1526 return -ENOSYS;
0a1405da 1527 init_attr->recv_cq = init_attr->send_cq;
df561f66 1528 fallthrough;
225c7b1f
RD		 1529 case IB_QPT_RC:
1530 case IB_QPT_UC:
3987a2d3 1531 case IB_QPT_RAW_PACKET:
8fd3cd2a 1532 case IB_QPT_UD:
2f5bb473
JM		 1533 qp->pri.vid = 0xFFFF;
1534 qp->alt.vid = 0xFFFF;
8fd3cd2a
LR		 1535 err = create_qp_common(pd, init_attr, udata, 0, qp);
1536 if (err)
1537 return err;
225c7b1f
RD		 1538
1539 qp->ibqp.qp_num = qp->mqp.qpn;
0a1405da 1540 qp->xrcdn = xrcdn;
225c7b1f 1541 break;
225c7b1f
RD		 1542 case IB_QPT_SMI:
1543 case IB_QPT_GSI:
1544 {
e1b866c6
MS		 1545 int sqpn;
1546
e1b866c6 1547 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
f3301870
MS		 1548 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1549 1, 1, &sqpn, 0,
1550 MLX4_RES_USAGE_DRIVER);
e1b866c6
MS		 1551
1552 if (res)
8fd3cd2a 1553 return res;
e1b866c6
MS		 1554 } else {
1555 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1556 }
225c7b1f 1557
8fd3cd2a
LR		 1558 qp->pri.vid = 0xFFFF;
1559 qp->alt.vid = 0xFFFF;
1560 err = create_qp_common(pd, init_attr, udata, sqpn, qp);
1ffeb2eb 1561 if (err)
8fd3cd2a 1562 return err;
225c7b1f 1563
2b1f7470
LR		 1564 if (init_attr->create_flags &
1565 (MLX4_IB_SRIOV_SQP | MLX4_IB_SRIOV_TUNNEL_QP))
1566 /* Internal QP created with ib_create_qp */
1567 rdma_restrack_no_track(&qp->ibqp.res);
1568
225c7b1f 1569 qp->port = init_attr->port_num;
e1b866c6
MS		 1570 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1571 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
225c7b1f
RD		 1572 break;
1573 }
1574 default:
1575 /* Don't support raw QPs */
8fd3cd2a 1576 return -EOPNOTSUPP;
225c7b1f 1577 }
8fd3cd2a 1578 return 0;
225c7b1f
RD		 1579}
1580
514aee66
LR		 1581int mlx4_ib_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *init_attr,
1582 struct ib_udata *udata)
1583{
1584 struct ib_device *device = ibqp->device;
e1b866c6 1585 struct mlx4_ib_dev *dev = to_mdev(device);
514aee66
LR		 1586 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1587 struct ib_pd *pd = ibqp->pd;
8fd3cd2a
LR		 1588 int ret;
1589
8fd3cd2a
LR		 1590 mutex_init(&qp->mutex);
1591 ret = _mlx4_ib_create_qp(pd, qp, init_attr, udata);
514aee66
LR		 1592 if (ret)
1593 return ret;
e1b866c6 1594
8fd3cd2a 1595 if (init_attr->qp_type == IB_QPT_GSI &&
e1b866c6 1596 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
915ec7ed 1597 struct mlx4_ib_sqp *sqp = qp->sqp;
e1b866c6
MS		 1598 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1599
1600 if (is_eth &&
1601 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1602 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1603 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1604
1605 if (IS_ERR(sqp->roce_v2_gsi)) {
1606 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1607 sqp->roce_v2_gsi = NULL;
1608 } else {
915ec7ed
LR		 1609 to_mqp(sqp->roce_v2_gsi)->flags |=
1610 MLX4_IB_ROCE_V2_GSI_QP;
e1b866c6
MS		 1611 }
1612
1613 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1614 }
1615 }
514aee66 1616 return 0;
e1b866c6
MS		 1617}
1618
bdeacabd 1619static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
225c7b1f
RD		 1620{
1621 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1622 struct mlx4_ib_qp *mqp = to_mqp(qp);
1623
1624 if (is_qp0(dev, mqp))
1625 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1626
c482af64
JM		 1627 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1628 dev->qp1_proxy[mqp->port - 1] == mqp) {
9433c188
MB		 1629 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1630 dev->qp1_proxy[mqp->port - 1] = NULL;
1631 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1632 }
1633
7b59f0f9
EBE		 1634 if (mqp->counter_index)
1635 mlx4_ib_free_qp_counter(dev, mqp);
1636
3078f5f1
GL		 1637 if (qp->rwq_ind_tbl) {
1638 destroy_qp_rss(dev, mqp);
1639 } else {
bdeacabd 1640 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, udata);
3078f5f1 1641 }
225c7b1f 1642
8fd3cd2a 1643 kfree(mqp->sqp);
225c7b1f
RD		 1644 return 0;
1645}
1646
c4367a26 1647int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
e1b866c6
MS		 1648{
1649 struct mlx4_ib_qp *mqp = to_mqp(qp);
1650
1651 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
915ec7ed 1652 struct mlx4_ib_sqp *sqp = mqp->sqp;
e1b866c6
MS		 1653
1654 if (sqp->roce_v2_gsi)
1655 ib_destroy_qp(sqp->roce_v2_gsi);
1656 }
1657
bdeacabd 1658 return _mlx4_ib_destroy_qp(qp, udata);
e1b866c6
MS		 1659}
1660
1ffeb2eb 1661static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
225c7b1f
RD		 1662{
1663 switch (type) {
1ffeb2eb
JM		 1664 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1665 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1666 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1667 case MLX4_IB_QPT_XRC_INI:
1668 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1669 case MLX4_IB_QPT_SMI:
1670 case MLX4_IB_QPT_GSI:
1671 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1672
1673 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1674 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1675 MLX4_QP_ST_MLX : -1);
1676 case MLX4_IB_QPT_PROXY_SMI:
1677 case MLX4_IB_QPT_TUN_SMI:
1678 case MLX4_IB_QPT_PROXY_GSI:
1679 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1680 MLX4_QP_ST_UD : -1);
1681 default: return -1;
225c7b1f
RD		 1682 }
1683}
1684
65adfa91 1685static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1686 int attr_mask)
1687{
1688 u8 dest_rd_atomic;
1689 u32 access_flags;
1690 u32 hw_access_flags = 0;
1691
1692 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1693 dest_rd_atomic = attr->max_dest_rd_atomic;
1694 else
1695 dest_rd_atomic = qp->resp_depth;
1696
1697 if (attr_mask & IB_QP_ACCESS_FLAGS)
1698 access_flags = attr->qp_access_flags;
1699 else
1700 access_flags = qp->atomic_rd_en;
1701
1702 if (!dest_rd_atomic)
1703 access_flags &= IB_ACCESS_REMOTE_WRITE;
1704
1705 if (access_flags & IB_ACCESS_REMOTE_READ)
1706 hw_access_flags |= MLX4_QP_BIT_RRE;
1707 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1708 hw_access_flags |= MLX4_QP_BIT_RAE;
1709 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1710 hw_access_flags |= MLX4_QP_BIT_RWE;
1711
1712 return cpu_to_be32(hw_access_flags);
1713}
1714
65adfa91 1715static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 1716 int attr_mask)
1717{
1718 if (attr_mask & IB_QP_PKEY_INDEX)
1719 sqp->pkey_index = attr->pkey_index;
1720 if (attr_mask & IB_QP_QKEY)
1721 sqp->qkey = attr->qkey;
1722 if (attr_mask & IB_QP_SQ_PSN)
1723 sqp->send_psn = attr->sq_psn;
1724}
1725
1726static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1727{
1728 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1729}
1730
90898850
DC		 1731static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1732 const struct rdma_ah_attr *ah,
297e0dad 1733 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
2f5bb473 1734 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
225c7b1f 1735{
4c3eb3ca 1736 int vidx;
297e0dad 1737 int smac_index;
2f5bb473 1738 int err;
297e0dad 1739
d8966fcd
DC		 1740 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1741 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1742 if (rdma_ah_get_static_rate(ah)) {
1743 path->static_rate = rdma_ah_get_static_rate(ah) +
1744 MLX4_STAT_RATE_OFFSET;
225c7b1f
RD		 1745 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1746 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1747 --path->static_rate;
1748 } else
1749 path->static_rate = 0;
225c7b1f 1750
d8966fcd
DC		 1751 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1752 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1753 int real_sgid_index =
7492052a 1754 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
5070cd22 1755
54a6d63f
DC		 1756 if (real_sgid_index < 0)
1757 return real_sgid_index;
5070cd22 1758 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
987c8f8f 1759 pr_err("sgid_index (%u) too large. max is %d\n",
5070cd22 1760 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 1761 return -1;
1762 }
1763
1764 path->grh_mylmc |= 1 << 7;
5070cd22 1765 path->mgid_index = real_sgid_index;
d8966fcd 1766 path->hop_limit = grh->hop_limit;
225c7b1f 1767 path->tclass_flowlabel =
d8966fcd
DC		 1768 cpu_to_be32((grh->traffic_class << 20) |
1769 (grh->flow_label));
1770 memcpy(path->rgid, grh->dgid.raw, 16);
225c7b1f
RD		 1771 }
1772
44c58487 1773 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
d8966fcd 1774 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
fa417f7b
EC		 1775 return -1;
1776
2f5bb473 1777 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1778 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
4c3eb3ca 1779
297e0dad 1780 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
4c3eb3ca 1781 if (vlan_tag < 0x1000) {
2f5bb473
JM		 1782 if (smac_info->vid < 0x1000) {
1783 /* both valid vlan ids */
1784 if (smac_info->vid != vlan_tag) {
1785 /* different VIDs. unreg old and reg new */
1786 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1787 if (err)
1788 return err;
1789 smac_info->candidate_vid = vlan_tag;
1790 smac_info->candidate_vlan_index = vidx;
1791 smac_info->candidate_vlan_port = port;
1792 smac_info->update_vid = 1;
1793 path->vlan_index = vidx;
1794 } else {
1795 path->vlan_index = smac_info->vlan_index;
1796 }
1797 } else {
1798 /* no current vlan tag in qp */
1799 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1800 if (err)
1801 return err;
1802 smac_info->candidate_vid = vlan_tag;
1803 smac_info->candidate_vlan_index = vidx;
1804 smac_info->candidate_vlan_port = port;
1805 smac_info->update_vid = 1;
1806 path->vlan_index = vidx;
1807 }
297e0dad 1808 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
2f5bb473
JM		 1809 path->fl = 1 << 6;
1810 } else {
1811 /* have current vlan tag. unregister it at modify-qp success */
1812 if (smac_info->vid < 0x1000) {
1813 smac_info->candidate_vid = 0xFFFF;
1814 smac_info->update_vid = 1;
1815 }
4c3eb3ca 1816 }
2f5bb473
JM		 1817
1818 /* get smac_index for RoCE use.
1819 * If no smac was yet assigned, register one.
1820 * If one was already assigned, but the new mac differs,
1821 * unregister the old one and register the new one.
1822 */
25476b02
JM		 1823 if ((!smac_info->smac && !smac_info->smac_port) ||
1824 smac_info->smac != smac) {
2f5bb473
JM		 1825 /* register candidate now, unreg if needed, after success */
1826 smac_index = mlx4_register_mac(dev->dev, port, smac);
1827 if (smac_index >= 0) {
1828 smac_info->candidate_smac_index = smac_index;
1829 smac_info->candidate_smac = smac;
1830 smac_info->candidate_smac_port = port;
1831 } else {
1832 return -EINVAL;
1833 }
1834 } else {
1835 smac_index = smac_info->smac_index;
1836 }
44c58487 1837 memcpy(path->dmac, ah->roce.dmac, 6);
2f5bb473
JM		 1838 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1839 /* put MAC table smac index for IBoE */
1840 path->grh_mylmc = (u8) (smac_index) | 0x80;
1841 } else {
4c3eb3ca 1842 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
d8966fcd 1843 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
2f5bb473 1844 }
fa417f7b 1845
225c7b1f
RD		 1846 return 0;
1847}
1848
297e0dad
MS		 1849static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1850 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1851 struct mlx4_ib_qp *mqp,
dbf727de
MB		 1852 struct mlx4_qp_path *path, u8 port,
1853 u16 vlan_id, u8 *smac)
297e0dad
MS		 1854{
1855 return _mlx4_set_path(dev, &qp->ah_attr,
dbf727de
MB		 1856 mlx4_mac_to_u64(smac),
1857 vlan_id,
2f5bb473 1858 path, &mqp->pri, port);
297e0dad
MS		 1859}
1860
1861static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1862 const struct ib_qp_attr *qp,
1863 enum ib_qp_attr_mask qp_attr_mask,
2f5bb473 1864 struct mlx4_ib_qp *mqp,
297e0dad
MS		 1865 struct mlx4_qp_path *path, u8 port)
1866{
1867 return _mlx4_set_path(dev, &qp->alt_ah_attr,
dbf727de
MB		 1868 0,
1869 0xffff,
2f5bb473 1870 path, &mqp->alt, port);
297e0dad
MS		 1871}
1872
fa417f7b
EC		 1873static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1874{
1875 struct mlx4_ib_gid_entry *ge, *tmp;
1876
1877 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1878 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1879 ge->added = 1;
1880 ge->port = qp->port;
1881 }
1882 }
1883}
1884
dbf727de
MB		 1885static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1886 struct mlx4_ib_qp *qp,
2f5bb473
JM		 1887 struct mlx4_qp_context *context)
1888{
2f5bb473
JM		 1889 u64 u64_mac;
1890 int smac_index;
1891
3e0629cb 1892 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
2f5bb473
JM		 1893
1894 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
25476b02 1895 if (!qp->pri.smac && !qp->pri.smac_port) {
2f5bb473
JM		 1896 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1897 if (smac_index >= 0) {
1898 qp->pri.candidate_smac_index = smac_index;
1899 qp->pri.candidate_smac = u64_mac;
1900 qp->pri.candidate_smac_port = qp->port;
1901 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1902 } else {
1903 return -ENOENT;
1904 }
1905 }
1906 return 0;
1907}
1908
7b59f0f9
EBE		 1909static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1910{
1911 struct counter_index *new_counter_index;
1912 int err;
1913 u32 tmp_idx;
1914
1915 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1916 IB_LINK_LAYER_ETHERNET ||
1917 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1918 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1919 return 0;
1920
f3301870 1921 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
7b59f0f9
EBE		 1922 if (err)
1923 return err;
1924
1925 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1926 if (!new_counter_index) {
1927 mlx4_counter_free(dev->dev, tmp_idx);
1928 return -ENOMEM;
1929 }
1930
1931 new_counter_index->index = tmp_idx;
1932 new_counter_index->allocated = 1;
1933 qp->counter_index = new_counter_index;
1934
1935 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1936 list_add_tail(&new_counter_index->list,
1937 &dev->counters_table[qp->port - 1].counters_list);
1938 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1939
1940 return 0;
1941}
1942
3b5daf28
MS		 1943enum {
1944 MLX4_QPC_ROCE_MODE_1 = 0,
1945 MLX4_QPC_ROCE_MODE_2 = 2,
1946 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1947};
1948
1949static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1950{
1951 switch (gid_type) {
1952 case IB_GID_TYPE_ROCE:
1953 return MLX4_QPC_ROCE_MODE_1;
1954 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1955 return MLX4_QPC_ROCE_MODE_2;
1956 default:
1957 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1958 }
1959}
1960
3078f5f1
GL		 1961/*
1962 * Go over all RSS QP's childes (WQs) and apply their HW state according to
1963 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
1964 */
89944450
SR		 1965static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num,
1966 struct ib_udata *udata)
3078f5f1 1967{
fba02e6c 1968 int err = 0;
3078f5f1 1969 int i;
3078f5f1
GL		 1970
1971 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
1972 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
1973 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1974
1975 mutex_lock(&wq->mutex);
1976
1977 /* Mlx4_ib restrictions:
1978 * WQ's is associated to a port according to the RSS QP it is
1979 * associates to.
1980 * In case the WQ is associated to a different port by another
1981 * RSS QP, return a failure.
1982 */
1983 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
1984 err = -EINVAL;
1985 mutex_unlock(&wq->mutex);
1986 break;
1987 }
1988 wq->port = port_num;
1989 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
89944450 1990 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY, udata);
3078f5f1
GL		 1991 if (err) {
1992 mutex_unlock(&wq->mutex);
1993 break;
1994 }
1995 }
1996 wq->rss_usecnt++;
1997
1998 mutex_unlock(&wq->mutex);
1999 }
2000
2001 if (i && err) {
2002 int j;
2003
2004 for (j = (i - 1); j >= 0; j--) {
2005 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2006 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2007
2008 mutex_lock(&wq->mutex);
2009
2010 if ((wq->rss_usecnt == 1) &&
2011 (ibwq->state == IB_WQS_RDY))
89944450
SR		 2012 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET,
2013 udata))
3078f5f1
GL		 2014 pr_warn("failed to reverse WQN=0x%06x\n",
2015 ibwq->wq_num);
2016 wq->rss_usecnt--;
2017
2018 mutex_unlock(&wq->mutex);
2019 }
2020 }
2021
2022 return err;
2023}
2024
89944450
SR		 2025static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl,
2026 struct ib_udata *udata)
3078f5f1
GL		 2027{
2028 int i;
2029
2030 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2031 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2032 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2033
2034 mutex_lock(&wq->mutex);
2035
2036 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
89944450 2037 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET, udata))
3078f5f1
GL		 2038 pr_warn("failed to reverse WQN=%x\n",
2039 ibwq->wq_num);
2040 wq->rss_usecnt--;
2041
2042 mutex_unlock(&wq->mutex);
2043 }
2044}
2045
2046static void fill_qp_rss_context(struct mlx4_qp_context *context,
2047 struct mlx4_ib_qp *qp)
2048{
2049 struct mlx4_rss_context *rss_context;
2050
2051 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2052 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2053
2054 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2055 rss_context->default_qpn =
2056 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2057 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2058 rss_context->base_qpn_udp = rss_context->default_qpn;
2059 rss_context->flags = qp->rss_ctx->flags;
2060 /* Currently support just toeplitz */
2061 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2062
2063 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2064 MLX4_EN_RSS_KEY_SIZE);
2065}
2066
400b1ebc 2067static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
65adfa91 2068 const struct ib_qp_attr *attr, int attr_mask,
89944450
SR		 2069 enum ib_qp_state cur_state,
2070 enum ib_qp_state new_state,
2071 struct ib_udata *udata)
225c7b1f 2072{
400b1ebc 2073 struct ib_srq *ibsrq;
47ec3866 2074 const struct ib_gid_attr *gid_attr = NULL;
3078f5f1 2075 struct ib_rwq_ind_table *rwq_ind_tbl;
400b1ebc
GL		 2076 enum ib_qp_type qp_type;
2077 struct mlx4_ib_dev *dev;
2078 struct mlx4_ib_qp *qp;
0a1405da
SH		 2079 struct mlx4_ib_pd *pd;
2080 struct mlx4_ib_cq *send_cq, *recv_cq;
89944450
SR		 2081 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context(
2082 udata, struct mlx4_ib_ucontext, ibucontext);
225c7b1f
RD		 2083 struct mlx4_qp_context *context;
2084 enum mlx4_qp_optpar optpar = 0;
225c7b1f 2085 int sqd_event;
c1c98501 2086 int steer_qp = 0;
225c7b1f 2087 int err = -EINVAL;
3ba8e31d 2088 int counter_index;
225c7b1f 2089
400b1ebc
GL		 2090 if (src_type == MLX4_IB_RWQ_SRC) {
2091 struct ib_wq *ibwq;
2092
3078f5f1 2093 ibwq = (struct ib_wq *)src;
3078f5f1
GL		 2094 ibsrq = NULL;
2095 rwq_ind_tbl = NULL;
2096 qp_type = IB_QPT_RAW_PACKET;
2097 qp = to_mqp((struct ib_qp *)ibwq);
2098 dev = to_mdev(ibwq->device);
2099 pd = to_mpd(ibwq->pd);
400b1ebc
GL		 2100 } else {
2101 struct ib_qp *ibqp;
2102
3078f5f1 2103 ibqp = (struct ib_qp *)src;
3078f5f1
GL		 2104 ibsrq = ibqp->srq;
2105 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2106 qp_type = ibqp->qp_type;
2107 qp = to_mqp(ibqp);
2108 dev = to_mdev(ibqp->device);
2109 pd = get_pd(qp);
400b1ebc
GL		 2110 }
2111
3dec4878
JM		 2112 /* APM is not supported under RoCE */
2113 if (attr_mask & IB_QP_ALT_PATH &&
2114 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2115 IB_LINK_LAYER_ETHERNET)
2116 return -ENOTSUPP;
2117
225c7b1f
RD		 2118 context = kzalloc(sizeof *context, GFP_KERNEL);
2119 if (!context)
2120 return -ENOMEM;
2121
225c7b1f 2122 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1ffeb2eb 2123 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
225c7b1f
RD		 2124
2125 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2126 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2127 else {
2128 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2129 switch (attr->path_mig_state) {
2130 case IB_MIG_MIGRATED:
2131 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2132 break;
2133 case IB_MIG_REARM:
2134 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2135 break;
2136 case IB_MIG_ARMED:
2137 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2138 break;
2139 }
2140 }
2141
ea30b966
MG		 2142 if (qp->inl_recv_sz)
2143 context->param3 |= cpu_to_be32(1 << 25);
2144
6d06c9aa
GL		 2145 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2146 context->param3 |= cpu_to_be32(1 << 29);
2147
400b1ebc 2148 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
225c7b1f 2149 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
400b1ebc 2150 else if (qp_type == IB_QPT_RAW_PACKET)
3987a2d3 2151 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
400b1ebc 2152 else if (qp_type == IB_QPT_UD) {
b832be1e
EC		 2153 if (qp->flags & MLX4_IB_QP_LSO)
2154 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2155 ilog2(dev->dev->caps.max_gso_sz);
2156 else
5f22a1d8 2157 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
b832be1e 2158 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f 2159 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
987c8f8f 2160 pr_err("path MTU (%u) is invalid\n",
225c7b1f 2161 attr->path_mtu);
f5b40431 2162 goto out;
225c7b1f 2163 }
d1f2cd89
EC		 2164 context->mtu_msgmax = (attr->path_mtu << 5) |
2165 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 2166 }
2167
3078f5f1
GL		 2168 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2169 if (qp->rq.wqe_cnt)
2170 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2171 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2172 }
225c7b1f 2173
0e6e7416
RD		 2174 if (qp->sq.wqe_cnt)
2175 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 2176 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2177
7b59f0f9
EBE		 2178 if (new_state == IB_QPS_RESET && qp->counter_index)
2179 mlx4_ib_free_qp_counter(dev, qp);
2180
0a1405da 2181 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0e6e7416 2182 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
0a1405da 2183 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
400b1ebc 2184 if (qp_type == IB_QPT_RAW_PACKET)
02d7ef6f 2185 context->param3 |= cpu_to_be32(1 << 30);
0a1405da 2186 }
0e6e7416 2187
89944450 2188 if (ucontext)
85743f1e 2189 context->usr_page = cpu_to_be32(
89944450 2190 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index));
225c7b1f 2191 else
85743f1e
HN		 2192 context->usr_page = cpu_to_be32(
2193 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
225c7b1f
RD		 2194
2195 if (attr_mask & IB_QP_DEST_QPN)
2196 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2197
2198 if (attr_mask & IB_QP_PORT) {
2199 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2200 !(attr_mask & IB_QP_AV)) {
2201 mlx4_set_sched(&context->pri_path, attr->port_num);
2202 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2203 }
2204 }
2205
cfcde11c 2206 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
7b59f0f9
EBE		 2207 err = create_qp_lb_counter(dev, qp);
2208 if (err)
2209 goto out;
2210
3ba8e31d
EBE		 2211 counter_index =
2212 dev->counters_table[qp->port - 1].default_counter;
7b59f0f9
EBE		 2213 if (qp->counter_index)
2214 counter_index = qp->counter_index->index;
2215
3ba8e31d
EBE		 2216 if (counter_index != -1) {
2217 context->pri_path.counter_index = counter_index;
cfcde11c 2218 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
7b59f0f9
EBE		 2219 if (qp->counter_index) {
2220 context->pri_path.fl |=
2221 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2222 context->pri_path.vlan_control |=
2223 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2224 }
cfcde11c 2225 } else
47d8417f
EBE		 2226 context->pri_path.counter_index =
2227 MLX4_SINK_COUNTER_INDEX(dev->dev);
c1c98501
MB		 2228
2229 if (qp->flags & MLX4_IB_QP_NETIF) {
2230 mlx4_ib_steer_qp_reg(dev, qp, 1);
2231 steer_qp = 1;
2232 }
e1b866c6 2233
400b1ebc 2234 if (qp_type == IB_QPT_GSI) {
e1b866c6
MS		 2235 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2236 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2237 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2238
2239 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2240 }
cfcde11c
OG		 2241 }
2242
225c7b1f 2243 if (attr_mask & IB_QP_PKEY_INDEX) {
1ffeb2eb
JM		 2244 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2245 context->pri_path.disable_pkey_check = 0x40;
225c7b1f
RD		 2246 context->pri_path.pkey_index = attr->pkey_index;
2247 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2248 }
2249
225c7b1f 2250 if (attr_mask & IB_QP_AV) {
400b1ebc 2251 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
dbf727de 2252 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
dbf727de
MB		 2253 u16 vlan = 0xffff;
2254 u8 smac[ETH_ALEN];
d8966fcd
DC		 2255 int is_eth =
2256 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2257 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
dbf727de 2258
d8966fcd 2259 if (is_eth) {
47ec3866 2260 gid_attr = attr->ah_attr.grh.sgid_attr;
a70c0739
PP		 2261 err = rdma_read_gid_l2_fields(gid_attr, &vlan,
2262 &smac[0]);
2263 if (err)
2264 goto out;
dbf727de 2265 }
dbf727de 2266
2f5bb473 2267 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
dbf727de 2268 port_num, vlan, smac))
225c7b1f 2269 goto out;
225c7b1f
RD		 2270
2271 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2272 MLX4_QP_OPTPAR_SCHED_QUEUE);
3b5daf28
MS		 2273
2274 if (is_eth &&
2275 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
47ec3866 2276 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
3b5daf28
MS		 2277
2278 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2279 err = -EINVAL;
2280 goto out;
2281 }
2282 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2283 }
2284
225c7b1f
RD		 2285 }
2286
2287 if (attr_mask & IB_QP_TIMEOUT) {
fa417f7b 2288 context->pri_path.ackto |= attr->timeout << 3;
225c7b1f
RD		 2289 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2290 }
2291
2292 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 2293 if (attr->alt_port_num == 0 ||
2294 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 2295 goto out;
225c7b1f 2296
5ae2a7a8
RD		 2297 if (attr->alt_pkey_index >=
2298 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 2299 goto out;
5ae2a7a8 2300
2f5bb473
JM		 2301 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2302 &context->alt_path,
297e0dad 2303 attr->alt_port_num))
f5b40431 2304 goto out;
225c7b1f
RD		 2305
2306 context->alt_path.pkey_index = attr->alt_pkey_index;
2307 context->alt_path.ackto = attr->alt_timeout << 3;
2308 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2309 }
2310
3078f5f1
GL		 2311 context->pd = cpu_to_be32(pd->pdn);
2312
2313 if (!rwq_ind_tbl) {
108809a0 2314 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
3078f5f1
GL		 2315 get_cqs(qp, src_type, &send_cq, &recv_cq);
2316 } else { /* Set dummy CQs to be compatible with HV and PRM */
2317 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2318 recv_cq = send_cq;
2319 }
0a1405da
SH		 2320 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2321 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
57f01b53 2322
95d04f07 2323 /* Set "fast registration enabled" for all kernel QPs */
89944450 2324 if (!ucontext)
95d04f07
RD		 2325 context->params1 |= cpu_to_be32(1 << 11);
2326
57f01b53
JM		 2327 if (attr_mask & IB_QP_RNR_RETRY) {
2328 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2329 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2330 }
2331
225c7b1f
RD		 2332 if (attr_mask & IB_QP_RETRY_CNT) {
2333 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2334 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2335 }
2336
2337 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2338 if (attr->max_rd_atomic)
2339 context->params1 |=
2340 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2341 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2342 }
2343
2344 if (attr_mask & IB_QP_SQ_PSN)
2345 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2346
225c7b1f
RD		 2347 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2348 if (attr->max_dest_rd_atomic)
2349 context->params2 |=
2350 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2351 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2352 }
2353
2354 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2355 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2356 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2357 }
2358
400b1ebc 2359 if (ibsrq)
225c7b1f
RD		 2360 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2361
2362 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2363 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2364 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2365 }
2366 if (attr_mask & IB_QP_RQ_PSN)
2367 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2368
1ffeb2eb 2369 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
225c7b1f 2370 if (attr_mask & IB_QP_QKEY) {
1ffeb2eb
JM		 2371 if (qp->mlx4_ib_qp_type &
2372 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2373 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2374 else {
2375 if (mlx4_is_mfunc(dev->dev) &&
2376 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2377 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2378 MLX4_RESERVED_QKEY_BASE) {
2379 pr_err("Cannot use reserved QKEY"
2380 " 0x%x (range 0xffff0000..0xffffffff"
2381 " is reserved)\n", attr->qkey);
2382 err = -EINVAL;
2383 goto out;
2384 }
2385 context->qkey = cpu_to_be32(attr->qkey);
2386 }
225c7b1f
RD		 2387 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2388 }
2389
400b1ebc
GL		 2390 if (ibsrq)
2391 context->srqn = cpu_to_be32(1 << 24 |
2392 to_msrq(ibsrq)->msrq.srqn);
225c7b1f 2393
400b1ebc
GL		 2394 if (qp->rq.wqe_cnt &&
2395 cur_state == IB_QPS_RESET &&
2396 new_state == IB_QPS_INIT)
225c7b1f
RD		 2397 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2398
2399 if (cur_state == IB_QPS_INIT &&
2400 new_state == IB_QPS_RTR &&
400b1ebc
GL		 2401 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2402 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
225c7b1f 2403 context->pri_path.sched_queue = (qp->port - 1) << 6;
1ffeb2eb
JM		 2404 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2405 qp->mlx4_ib_qp_type &
2406 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
225c7b1f 2407 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1ffeb2eb
JM		 2408 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2409 context->pri_path.fl = 0x80;
2410 } else {
2411 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2412 context->pri_path.fl = 0x80;
225c7b1f 2413 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1ffeb2eb 2414 }
2f5bb473
JM		 2415 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2416 IB_LINK_LAYER_ETHERNET) {
2417 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2418 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2419 context->pri_path.feup = 1 << 7; /* don't fsm */
2420 /* handle smac_index */
2421 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2422 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2423 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
dbf727de 2424 err = handle_eth_ud_smac_index(dev, qp, context);
bede98e7
MD		 2425 if (err) {
2426 err = -EINVAL;
2427 goto out;
2428 }
9433c188
MB		 2429 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2430 dev->qp1_proxy[qp->port - 1] = qp;
2f5bb473
JM		 2431 }
2432 }
225c7b1f
RD		 2433 }
2434
400b1ebc 2435 if (qp_type == IB_QPT_RAW_PACKET) {
3528f696
EC		 2436 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2437 MLX4_IB_LINK_TYPE_ETH;
d2fce8a9
OG		 2438 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2439 /* set QP to receive both tunneled & non-tunneled packets */
108809a0 2440 if (!rwq_ind_tbl)
d2fce8a9
OG		 2441 context->srqn = cpu_to_be32(7 << 28);
2442 }
2443 }
3528f696 2444
400b1ebc 2445 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
297e0dad
MS		 2446 int is_eth = rdma_port_get_link_layer(
2447 &dev->ib_dev, qp->port) ==
2448 IB_LINK_LAYER_ETHERNET;
2449 if (is_eth) {
2450 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2451 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2452 }
2453 }
2454
225c7b1f
RD		 2455 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2456 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2457 sqd_event = 1;
2458 else
2459 sqd_event = 0;
2460
89944450 2461 if (!ucontext &&
400b1ebc
GL		 2462 cur_state == IB_QPS_RESET &&
2463 new_state == IB_QPS_INIT)
3b5daf28 2464 context->rlkey_roce_mode |= (1 << 4);
d57f5f72 2465
c0be5fb5
EC		 2466 /*
2467 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 2468 * ownership bits of the send queue are set and the SQ
2469 * headroom is stamped so that the hardware doesn't start
2470 * processing stale work requests.
c0be5fb5 2471 */
89944450 2472 if (!ucontext &&
400b1ebc
GL		 2473 cur_state == IB_QPS_RESET &&
2474 new_state == IB_QPS_INIT) {
c0be5fb5
EC		 2475 struct mlx4_wqe_ctrl_seg *ctrl;
2476 int i;
2477
0e6e7416 2478 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 2479 ctrl = get_send_wqe(qp, i);
2480 ctrl->owner_opcode = cpu_to_be32(1 << 31);
f95ccffc
JM		 2481 ctrl->qpn_vlan.fence_size =
2482 1 << (qp->sq.wqe_shift - 4);
2483 stamp_send_wqe(qp, i);
c0be5fb5
EC		 2484 }
2485 }
2486
108809a0
GL		 2487 if (rwq_ind_tbl &&
2488 cur_state == IB_QPS_RESET &&
2489 new_state == IB_QPS_INIT) {
2490 fill_qp_rss_context(context, qp);
2491 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2492 }
2493
225c7b1f
RD		 2494 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2495 to_mlx4_state(new_state), context, optpar,
2496 sqd_event, &qp->mqp);
2497 if (err)
2498 goto out;
2499
2500 qp->state = new_state;
2501
2502 if (attr_mask & IB_QP_ACCESS_FLAGS)
2503 qp->atomic_rd_en = attr->qp_access_flags;
2504 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2505 qp->resp_depth = attr->max_dest_rd_atomic;
fa417f7b 2506 if (attr_mask & IB_QP_PORT) {
225c7b1f 2507 qp->port = attr->port_num;
fa417f7b
EC		 2508 update_mcg_macs(dev, qp);
2509 }
225c7b1f
RD		 2510 if (attr_mask & IB_QP_ALT_PATH)
2511 qp->alt_port = attr->alt_port_num;
2512
2513 if (is_sqp(dev, qp))
915ec7ed 2514 store_sqp_attrs(qp->sqp, attr, attr_mask);
225c7b1f
RD		 2515
2516 /*
2517 * If we moved QP0 to RTR, bring the IB link up; if we moved
2518 * QP0 to RESET or ERROR, bring the link back down.
2519 */
2520 if (is_qp0(dev, qp)) {
2521 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8 2522 if (mlx4_INIT_PORT(dev->dev, qp->port))
987c8f8f 2523 pr_warn("INIT_PORT failed for port %d\n",
5ae2a7a8 2524 qp->port);
225c7b1f
RD		 2525
2526 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2527 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2528 mlx4_CLOSE_PORT(dev->dev, qp->port);
2529 }
2530
2531 /*
2532 * If we moved a kernel QP to RESET, clean up all old CQ
2533 * entries and reinitialize the QP.
2534 */
2f5bb473 2535 if (new_state == IB_QPS_RESET) {
89944450 2536 if (!ucontext) {
2f5bb473 2537 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
400b1ebc 2538 ibsrq ? to_msrq(ibsrq) : NULL);
2f5bb473
JM		 2539 if (send_cq != recv_cq)
2540 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2541
2542 qp->rq.head = 0;
2543 qp->rq.tail = 0;
2544 qp->sq.head = 0;
2545 qp->sq.tail = 0;
2546 qp->sq_next_wqe = 0;
2547 if (qp->rq.wqe_cnt)
2548 *qp->db.db = 0;
225c7b1f 2549
2f5bb473
JM		 2550 if (qp->flags & MLX4_IB_QP_NETIF)
2551 mlx4_ib_steer_qp_reg(dev, qp, 0);
2552 }
25476b02 2553 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2f5bb473
JM		 2554 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2555 qp->pri.smac = 0;
25476b02 2556 qp->pri.smac_port = 0;
2f5bb473
JM		 2557 }
2558 if (qp->alt.smac) {
2559 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2560 qp->alt.smac = 0;
2561 }
2562 if (qp->pri.vid < 0x1000) {
2563 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2564 qp->pri.vid = 0xFFFF;
2565 qp->pri.candidate_vid = 0xFFFF;
2566 qp->pri.update_vid = 0;
2567 }
c1c98501 2568
2f5bb473
JM		 2569 if (qp->alt.vid < 0x1000) {
2570 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2571 qp->alt.vid = 0xFFFF;
2572 qp->alt.candidate_vid = 0xFFFF;
2573 qp->alt.update_vid = 0;
2574 }
225c7b1f 2575 }
225c7b1f 2576out:
7b59f0f9
EBE		 2577 if (err && qp->counter_index)
2578 mlx4_ib_free_qp_counter(dev, qp);
c1c98501
MB		 2579 if (err && steer_qp)
2580 mlx4_ib_steer_qp_reg(dev, qp, 0);
225c7b1f 2581 kfree(context);
25476b02
JM		 2582 if (qp->pri.candidate_smac ||
2583 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2f5bb473
JM		 2584 if (err) {
2585 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2586 } else {
25476b02 2587 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2f5bb473
JM		 2588 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2589 qp->pri.smac = qp->pri.candidate_smac;
2590 qp->pri.smac_index = qp->pri.candidate_smac_index;
2591 qp->pri.smac_port = qp->pri.candidate_smac_port;
2592 }
2593 qp->pri.candidate_smac = 0;
2594 qp->pri.candidate_smac_index = 0;
2595 qp->pri.candidate_smac_port = 0;
2596 }
2597 if (qp->alt.candidate_smac) {
2598 if (err) {
2599 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2600 } else {
2601 if (qp->alt.smac)
2602 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2603 qp->alt.smac = qp->alt.candidate_smac;
2604 qp->alt.smac_index = qp->alt.candidate_smac_index;
2605 qp->alt.smac_port = qp->alt.candidate_smac_port;
2606 }
2607 qp->alt.candidate_smac = 0;
2608 qp->alt.candidate_smac_index = 0;
2609 qp->alt.candidate_smac_port = 0;
2610 }
2611
2612 if (qp->pri.update_vid) {
2613 if (err) {
2614 if (qp->pri.candidate_vid < 0x1000)
2615 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2616 qp->pri.candidate_vid);
2617 } else {
2618 if (qp->pri.vid < 0x1000)
2619 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2620 qp->pri.vid);
2621 qp->pri.vid = qp->pri.candidate_vid;
2622 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2623 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2624 }
2625 qp->pri.candidate_vid = 0xFFFF;
2626 qp->pri.update_vid = 0;
2627 }
2628
2629 if (qp->alt.update_vid) {
2630 if (err) {
2631 if (qp->alt.candidate_vid < 0x1000)
2632 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2633 qp->alt.candidate_vid);
2634 } else {
2635 if (qp->alt.vid < 0x1000)
2636 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2637 qp->alt.vid);
2638 qp->alt.vid = qp->alt.candidate_vid;
2639 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2640 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2641 }
2642 qp->alt.candidate_vid = 0xFFFF;
2643 qp->alt.update_vid = 0;
2644 }
2645
225c7b1f
RD		 2646 return err;
2647}
2648
3078f5f1
GL		 2649enum {
2650 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2651 IB_QP_PORT),
2652};
2653
e1b866c6
MS		 2654static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2655 int attr_mask, struct ib_udata *udata)
65adfa91
MT		 2656{
2657 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2658 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2659 enum ib_qp_state cur_state, new_state;
2660 int err = -EINVAL;
65adfa91
MT		 2661 mutex_lock(&qp->mutex);
2662
2663 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2664 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2665
dd5f03be 2666 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
d31131bb 2667 attr_mask)) {
b1d8eb5a
JM		 2668 pr_debug("qpn 0x%x: invalid attribute mask specified "
2669 "for transition %d to %d. qp_type %d,"
2670 " attr_mask 0x%x\n",
2671 ibqp->qp_num, cur_state, new_state,
2672 ibqp->qp_type, attr_mask);
65adfa91 2673 goto out;
b1d8eb5a 2674 }
65adfa91 2675
3078f5f1
GL		 2676 if (ibqp->rwq_ind_tbl) {
2677 if (!(((cur_state == IB_QPS_RESET) &&
2678 (new_state == IB_QPS_INIT)) ||
2679 ((cur_state == IB_QPS_INIT) &&
2680 (new_state == IB_QPS_RTR)))) {
2681 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2682 ibqp->qp_num, cur_state, new_state);
2683
2684 err = -EOPNOTSUPP;
2685 goto out;
2686 }
2687
2688 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2689 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2690 ibqp->qp_num, attr_mask, cur_state, new_state);
2691
2692 err = -EOPNOTSUPP;
2693 goto out;
2694 }
2695 }
2696
c6215745
MS		 2697 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2698 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2699 if ((ibqp->qp_type == IB_QPT_RC) ||
2700 (ibqp->qp_type == IB_QPT_UD) ||
2701 (ibqp->qp_type == IB_QPT_UC) ||
2702 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2703 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2704 attr->port_num = mlx4_ib_bond_next_port(dev);
2705 }
2706 } else {
2707 /* no sense in changing port_num
2708 * when ports are bonded */
2709 attr_mask &= ~IB_QP_PORT;
2710 }
2711 }
2712
65adfa91 2713 if ((attr_mask & IB_QP_PORT) &&
1ffeb2eb 2714 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
b1d8eb5a
JM		 2715 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2716 "for transition %d to %d. qp_type %d\n",
2717 ibqp->qp_num, attr->port_num, cur_state,
2718 new_state, ibqp->qp_type);
65adfa91
MT		 2719 goto out;
2720 }
2721
3987a2d3
OG		 2722 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2723 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2724 IB_LINK_LAYER_ETHERNET))
2725 goto out;
2726
5ae2a7a8
RD		 2727 if (attr_mask & IB_QP_PKEY_INDEX) {
2728 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
b1d8eb5a
JM		 2729 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2730 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2731 "for transition %d to %d. qp_type %d\n",
2732 ibqp->qp_num, attr->pkey_index, cur_state,
2733 new_state, ibqp->qp_type);
5ae2a7a8 2734 goto out;
b1d8eb5a 2735 }
5ae2a7a8
RD		 2736 }
2737
65adfa91
MT		 2738 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2739 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
b1d8eb5a
JM		 2740 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2741 "Transition %d to %d. qp_type %d\n",
2742 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2743 new_state, ibqp->qp_type);
65adfa91
MT		 2744 goto out;
2745 }
2746
2747 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2748 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
b1d8eb5a
JM		 2749 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2750 "Transition %d to %d. qp_type %d\n",
2751 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2752 new_state, ibqp->qp_type);
65adfa91
MT		 2753 goto out;
2754 }
2755
2756 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2757 err = 0;
2758 goto out;
2759 }
2760
3078f5f1 2761 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
89944450
SR		 2762 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num,
2763 udata);
3078f5f1
GL		 2764 if (err)
2765 goto out;
2766 }
2767
400b1ebc 2768 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
89944450 2769 cur_state, new_state, udata);
65adfa91 2770
3078f5f1 2771 if (ibqp->rwq_ind_tbl && err)
89944450 2772 bring_down_rss_rwqs(ibqp->rwq_ind_tbl, udata);
3078f5f1 2773
c6215745
MS		 2774 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2775 attr->port_num = 1;
2776
65adfa91
MT		 2777out:
2778 mutex_unlock(&qp->mutex);
2779 return err;
2780}
2781
e1b866c6
MS		 2782int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2783 int attr_mask, struct ib_udata *udata)
2784{
2785 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2786 int ret;
2787
26e990ba
JG		 2788 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
2789 return -EOPNOTSUPP;
2790
e1b866c6
MS		 2791 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2792
2793 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
915ec7ed 2794 struct mlx4_ib_sqp *sqp = mqp->sqp;
e1b866c6
MS		 2795 int err = 0;
2796
2797 if (sqp->roce_v2_gsi)
2798 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2799 if (err)
2800 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2801 err);
2802 }
2803 return ret;
2804}
2805
99ec41d0
JM		 2806static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2807{
2808 int i;
2809 for (i = 0; i < dev->caps.num_ports; i++) {
c73c8b1e
EBE		 2810 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2811 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2812 *qkey = dev->caps.spec_qps[i].qp0_qkey;
99ec41d0
JM		 2813 return 0;
2814 }
2815 }
2816 return -EINVAL;
2817}
2818
915ec7ed 2819static int build_sriov_qp0_header(struct mlx4_ib_qp *qp,
f696bf6d 2820 const struct ib_ud_wr *wr,
1ffeb2eb
JM		 2821 void *wqe, unsigned *mlx_seg_len)
2822{
915ec7ed
LR		 2823 struct mlx4_ib_dev *mdev = to_mdev(qp->ibqp.device);
2824 struct mlx4_ib_sqp *sqp = qp->sqp;
2825 struct ib_device *ib_dev = qp->ibqp.device;
1ffeb2eb
JM		 2826 struct mlx4_wqe_mlx_seg *mlx = wqe;
2827 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2828 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 2829 u16 pkey;
2830 u32 qkey;
2831 int send_size;
2832 int header_size;
2833 int spc;
6693ca95 2834 int err;
1ffeb2eb
JM		 2835 int i;
2836
e622f2f4 2837 if (wr->wr.opcode != IB_WR_SEND)
1ffeb2eb
JM		 2838 return -EINVAL;
2839
2840 send_size = 0;
2841
e622f2f4
CH		 2842 for (i = 0; i < wr->wr.num_sge; ++i)
2843 send_size += wr->wr.sg_list[i].length;
1ffeb2eb
JM		 2844
2845 /* for proxy-qp0 sends, need to add in size of tunnel header */
2846 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
915ec7ed 2847 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1ffeb2eb
JM		 2848 send_size += sizeof (struct mlx4_ib_tunnel_header);
2849
25f40220 2850 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
1ffeb2eb 2851
915ec7ed 2852 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1ffeb2eb
JM		 2853 sqp->ud_header.lrh.service_level =
2854 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2855 sqp->ud_header.lrh.destination_lid =
2856 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2857 sqp->ud_header.lrh.source_lid =
2858 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2859 }
2860
2861 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2862
2863 /* force loopback */
2864 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2865 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2866
2867 sqp->ud_header.lrh.virtual_lane = 0;
e622f2f4 2868 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
915ec7ed 2869 err = ib_get_cached_pkey(ib_dev, qp->port, 0, &pkey);
6693ca95
JM		 2870 if (err)
2871 return err;
1ffeb2eb 2872 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
915ec7ed 2873 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
e622f2f4 2874 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1ffeb2eb
JM		 2875 else
2876 sqp->ud_header.bth.destination_qpn =
915ec7ed 2877 cpu_to_be32(mdev->dev->caps.spec_qps[qp->port - 1].qp0_tunnel);
1ffeb2eb
JM		 2878
2879 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
99ec41d0 2880 if (mlx4_is_master(mdev->dev)) {
915ec7ed 2881 if (mlx4_get_parav_qkey(mdev->dev, qp->mqp.qpn, &qkey))
99ec41d0
JM		 2882 return -EINVAL;
2883 } else {
915ec7ed 2884 if (vf_get_qp0_qkey(mdev->dev, qp->mqp.qpn, &qkey))
99ec41d0
JM		 2885 return -EINVAL;
2886 }
1ffeb2eb 2887 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
915ec7ed 2888 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->mqp.qpn);
1ffeb2eb
JM		 2889
2890 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2891 sqp->ud_header.immediate_present = 0;
2892
2893 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2894
2895 /*
2896 * Inline data segments may not cross a 64 byte boundary. If
2897 * our UD header is bigger than the space available up to the
2898 * next 64 byte boundary in the WQE, use two inline data
2899 * segments to hold the UD header.
2900 */
2901 spc = MLX4_INLINE_ALIGN -
2902 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2903 if (header_size <= spc) {
2904 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2905 memcpy(inl + 1, sqp->header_buf, header_size);
2906 i = 1;
2907 } else {
2908 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2909 memcpy(inl + 1, sqp->header_buf, spc);
2910
2911 inl = (void *) (inl + 1) + spc;
2912 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2913 /*
2914 * Need a barrier here to make sure all the data is
2915 * visible before the byte_count field is set.
2916 * Otherwise the HCA prefetcher could grab the 64-byte
2917 * chunk with this inline segment and get a valid (!=
2918 * 0xffffffff) byte count but stale data, and end up
2919 * generating a packet with bad headers.
2920 *
2921 * The first inline segment's byte_count field doesn't
2922 * need a barrier, because it comes after a
2923 * control/MLX segment and therefore is at an offset
2924 * of 16 mod 64.
2925 */
2926 wmb();
2927 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2928 i = 2;
2929 }
2930
2931 *mlx_seg_len =
2932 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2933 return 0;
2934}
2935
fd10ed8e
JM		 2936static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2937{
2938 union sl2vl_tbl_to_u64 tmp_vltab;
2939 u8 vl;
2940
2941 if (sl > 15)
2942 return 0xf;
2943 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2944 vl = tmp_vltab.sl8[sl >> 1];
2945 if (sl & 1)
2946 vl &= 0x0f;
2947 else
2948 vl >>= 4;
2949 return vl;
2950}
2951
a748d60d
TB		 2952static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2953 int index, union ib_gid *gid,
2954 enum ib_gid_type *gid_type)
2955{
2956 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2957 struct mlx4_port_gid_table *port_gid_table;
2958 unsigned long flags;
2959
2960 port_gid_table = &iboe->gids[port_num - 1];
2961 spin_lock_irqsave(&iboe->lock, flags);
2962 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2963 *gid_type = port_gid_table->gids[index].gid_type;
2964 spin_unlock_irqrestore(&iboe->lock, flags);
25e62655 2965 if (rdma_is_zero_gid(gid))
a748d60d
TB		 2966 return -ENOENT;
2967
2968 return 0;
2969}
2970
3ef967a4 2971#define MLX4_ROCEV2_QP1_SPORT 0xC000
915ec7ed 2972static int build_mlx_header(struct mlx4_ib_qp *qp, const struct ib_ud_wr *wr,
f438000f 2973 void *wqe, unsigned *mlx_seg_len)
225c7b1f 2974{
915ec7ed
LR		 2975 struct mlx4_ib_sqp *sqp = qp->sqp;
2976 struct ib_device *ib_dev = qp->ibqp.device;
a748d60d 2977 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
225c7b1f 2978 struct mlx4_wqe_mlx_seg *mlx = wqe;
6ee51a4e 2979 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
225c7b1f 2980 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
e622f2f4 2981 struct mlx4_ib_ah *ah = to_mah(wr->ah);
4c3eb3ca 2982 union ib_gid sgid;
225c7b1f
RD		 2983 u16 pkey;
2984 int send_size;
2985 int header_size;
e61ef241 2986 int spc;
225c7b1f 2987 int i;
1ffeb2eb 2988 int err = 0;
57d88cff 2989 u16 vlan = 0xffff;
a29bec12
RD		 2990 bool is_eth;
2991 bool is_vlan = false;
2992 bool is_grh;
3ef967a4
MS		 2993 bool is_udp = false;
2994 int ip_version = 0;
225c7b1f
RD		 2995
2996 send_size = 0;
e622f2f4
CH		 2997 for (i = 0; i < wr->wr.num_sge; ++i)
2998 send_size += wr->wr.sg_list[i].length;
225c7b1f 2999
915ec7ed 3000 is_eth = rdma_port_get_link_layer(qp->ibqp.device, qp->port) == IB_LINK_LAYER_ETHERNET;
fa417f7b 3001 is_grh = mlx4_ib_ah_grh_present(ah);
4c3eb3ca 3002 if (is_eth) {
a748d60d 3003 enum ib_gid_type gid_type;
1ffeb2eb
JM		 3004 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3005 /* When multi-function is enabled, the ib_core gid
3006 * indexes don't necessarily match the hw ones, so
3007 * we must use our own cache */
6ee51a4e
JM		 3008 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3009 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3010 ah->av.ib.gid_index, &sgid.raw[0]);
3011 if (err)
3012 return err;
1ffeb2eb 3013 } else {
915ec7ed
LR		 3014 err = fill_gid_by_hw_index(ibdev, qp->port,
3015 ah->av.ib.gid_index, &sgid,
3016 &gid_type);
3ef967a4 3017 if (!err) {
a748d60d 3018 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3ef967a4
MS		 3019 if (is_udp) {
3020 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3021 ip_version = 4;
3022 else
3023 ip_version = 6;
3024 is_grh = false;
3025 }
3026 } else {
1ffeb2eb 3027 return err;
3ef967a4 3028 }
1ffeb2eb 3029 }
0e9855db 3030 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
297e0dad 3031 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
cf368beb 3032 is_vlan = true;
297e0dad 3033 }
4c3eb3ca 3034 }
25f40220 3035 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3ef967a4 3036 ip_version, is_udp, 0, &sqp->ud_header);
25f40220
MS		 3037 if (err)
3038 return err;
fa417f7b
EC		 3039
3040 if (!is_eth) {
3041 sqp->ud_header.lrh.service_level =
3042 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3043 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3044 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3045 }
225c7b1f 3046
3ef967a4 3047 if (is_grh || (ip_version == 6)) {
225c7b1f 3048 sqp->ud_header.grh.traffic_class =
fa417f7b 3049 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
225c7b1f 3050 sqp->ud_header.grh.flow_label =
fa417f7b
EC		 3051 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3052 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
baa0be70 3053 if (is_eth) {
6ee51a4e 3054 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
baa0be70
JM		 3055 } else {
3056 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3057 /* When multi-function is enabled, the ib_core gid
3058 * indexes don't necessarily match the hw ones, so
3059 * we must use our own cache
3060 */
915ec7ed
LR		 3061 sqp->ud_header.grh.source_gid.global
3062 .subnet_prefix =
3063 cpu_to_be64(atomic64_read(
3064 &(to_mdev(ib_dev)
3065 ->sriov
3066 .demux[qp->port - 1]
3067 .subnet_prefix)));
3068 sqp->ud_header.grh.source_gid.global
3069 .interface_id =
3070 to_mdev(ib_dev)
3071 ->sriov.demux[qp->port - 1]
3072 .guid_cache[ah->av.ib.gid_index];
baa0be70 3073 } else {
89af969a
PP		 3074 sqp->ud_header.grh.source_gid =
3075 ah->ibah.sgid_attr->gid;
baa0be70 3076 }
6ee51a4e 3077 }
225c7b1f 3078 memcpy(sqp->ud_header.grh.destination_gid.raw,
fa417f7b 3079 ah->av.ib.dgid, 16);
225c7b1f
RD		 3080 }
3081
3ef967a4
MS		 3082 if (ip_version == 4) {
3083 sqp->ud_header.ip4.tos =
3084 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3085 sqp->ud_header.ip4.id = 0;
3086 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3087 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3088
3089 memcpy(&sqp->ud_header.ip4.saddr,
3090 sgid.raw + 12, 4);
3091 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3092 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3093 }
3094
3095 if (is_udp) {
3096 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3097 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3098 sqp->ud_header.udp.csum = 0;
3099 }
3100
225c7b1f 3101 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
fa417f7b
EC		 3102
3103 if (!is_eth) {
915ec7ed
LR		 3104 mlx->flags |=
3105 cpu_to_be32((!qp->ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3106 (sqp->ud_header.lrh.destination_lid ==
3107 IB_LID_PERMISSIVE ?
3108 MLX4_WQE_MLX_SLR :
3109 0) |
3110 (sqp->ud_header.lrh.service_level << 8));
1ffeb2eb
JM		 3111 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3112 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
fa417f7b
EC		 3113 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3114 }
225c7b1f 3115
e622f2f4 3116 switch (wr->wr.opcode) {
225c7b1f
RD		 3117 case IB_WR_SEND:
3118 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3119 sqp->ud_header.immediate_present = 0;
3120 break;
3121 case IB_WR_SEND_WITH_IMM:
3122 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3123 sqp->ud_header.immediate_present = 1;
e622f2f4 3124 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
225c7b1f
RD		 3125 break;
3126 default:
3127 return -EINVAL;
3128 }
3129
fa417f7b 3130 if (is_eth) {
3ef967a4 3131 u16 ether_type;
c0c1d3d7
OD		 3132 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3133
69ae5439 3134 ether_type = (!is_udp) ? ETH_P_IBOE:
3ef967a4
MS		 3135 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3136
c0c1d3d7 3137 mlx->sched_prio = cpu_to_be16(pcp);
fa417f7b 3138
1049f138 3139 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
4bf5cc63 3140 ether_addr_copy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac);
6ee51a4e
JM		 3141 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3142 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3e0629cb 3143
fa417f7b
EC		 3144 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3145 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
4c3eb3ca 3146 if (!is_vlan) {
3ef967a4 3147 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
4c3eb3ca 3148 } else {
3ef967a4 3149 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
4c3eb3ca
EC		 3150 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3151 }
fa417f7b 3152 } else {
915ec7ed
LR		 3153 sqp->ud_header.lrh.virtual_lane =
3154 !qp->ibqp.qp_num ?
3155 15 :
3156 sl_to_vl(to_mdev(ib_dev),
3157 sqp->ud_header.lrh.service_level,
3158 qp->port);
3159 if (qp->ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
fd10ed8e 3160 return -EINVAL;
fa417f7b
EC		 3161 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3162 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3163 }
e622f2f4 3164 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
915ec7ed
LR		 3165 if (!qp->ibqp.qp_num)
3166 err = ib_get_cached_pkey(ib_dev, qp->port, sqp->pkey_index,
6693ca95 3167 &pkey);
225c7b1f 3168 else
915ec7ed 3169 err = ib_get_cached_pkey(ib_dev, qp->port, wr->pkey_index,
6693ca95
JM		 3170 &pkey);
3171 if (err)
3172 return err;
3173
225c7b1f 3174 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
e622f2f4 3175 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
225c7b1f 3176 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
e622f2f4
CH		 3177 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3178 sqp->qkey : wr->remote_qkey);
915ec7ed 3179 sqp->ud_header.deth.source_qpn = cpu_to_be32(qp->ibqp.qp_num);
225c7b1f
RD		 3180
3181 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3182
3183 if (0) {
987c8f8f 3184 pr_err("built UD header of size %d:\n", header_size);
225c7b1f
RD		 3185 for (i = 0; i < header_size / 4; ++i) {
3186 if (i % 8 == 0)
987c8f8f
SP		 3187 pr_err(" [%02x] ", i * 4);
3188 pr_cont(" %08x",
3189 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
225c7b1f 3190 if ((i + 1) % 8 == 0)
987c8f8f 3191 pr_cont("\n");
225c7b1f 3192 }
987c8f8f 3193 pr_err("\n");
225c7b1f
RD		 3194 }
3195
e61ef241
RD		 3196 /*
3197 * Inline data segments may not cross a 64 byte boundary. If
3198 * our UD header is bigger than the space available up to the
3199 * next 64 byte boundary in the WQE, use two inline data
3200 * segments to hold the UD header.
3201 */
3202 spc = MLX4_INLINE_ALIGN -
3203 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3204 if (header_size <= spc) {
3205 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3206 memcpy(inl + 1, sqp->header_buf, header_size);
3207 i = 1;
3208 } else {
3209 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3210 memcpy(inl + 1, sqp->header_buf, spc);
3211
3212 inl = (void *) (inl + 1) + spc;
3213 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3214 /*
3215 * Need a barrier here to make sure all the data is
3216 * visible before the byte_count field is set.
3217 * Otherwise the HCA prefetcher could grab the 64-byte
3218 * chunk with this inline segment and get a valid (!=
3219 * 0xffffffff) byte count but stale data, and end up
3220 * generating a packet with bad headers.
3221 *
3222 * The first inline segment's byte_count field doesn't
3223 * need a barrier, because it comes after a
3224 * control/MLX segment and therefore is at an offset
3225 * of 16 mod 64.
3226 */
3227 wmb();
3228 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3229 i = 2;
3230 }
225c7b1f 3231
f438000f
RD		 3232 *mlx_seg_len =
3233 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3234 return 0;
225c7b1f
RD		 3235}
3236
3237static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3238{
3239 unsigned cur;
3240 struct mlx4_ib_cq *cq;
3241
3242 cur = wq->head - wq->tail;
0e6e7416 3243 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 3244 return 0;
3245
3246 cq = to_mcq(ib_cq);
3247 spin_lock(&cq->lock);
3248 cur = wq->head - wq->tail;
3249 spin_unlock(&cq->lock);
3250
0e6e7416 3251 return cur + nreq >= wq->max_post;
225c7b1f
RD		 3252}
3253
95d04f07
RD		 3254static __be32 convert_access(int acc)
3255{
6ff63e19
SM		 3256 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3257 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3258 (acc & IB_ACCESS_REMOTE_WRITE ?
3259 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3260 (acc & IB_ACCESS_REMOTE_READ ?
3261 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
95d04f07
RD		 3262 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3263 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3264}
3265
1b2cd0fc 3266static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
f696bf6d 3267 const struct ib_reg_wr *wr)
1b2cd0fc
SG		 3268{
3269 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3270
3271 fseg->flags = convert_access(wr->access);
3272 fseg->mem_key = cpu_to_be32(wr->key);
3273 fseg->buf_list = cpu_to_be64(mr->page_map);
3274 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3275 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3276 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3277 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3278 fseg->reserved[0] = 0;
3279 fseg->reserved[1] = 0;
3280}
3281
95d04f07
RD		 3282static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3283{
aee38fad
SM		 3284 memset(iseg, 0, sizeof(*iseg));
3285 iseg->mem_key = cpu_to_be32(rkey);
95d04f07
RD		 3286}
3287
0fbfa6a9
RD		 3288static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3289 u64 remote_addr, u32 rkey)
3290{
3291 rseg->raddr = cpu_to_be64(remote_addr);
3292 rseg->rkey = cpu_to_be32(rkey);
3293 rseg->reserved = 0;
3294}
3295
e622f2f4 3296static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
f696bf6d 3297 const struct ib_atomic_wr *wr)
0fbfa6a9 3298{
e622f2f4
CH		 3299 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3300 aseg->swap_add = cpu_to_be64(wr->swap);
3301 aseg->compare = cpu_to_be64(wr->compare_add);
3302 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3303 aseg->swap_add = cpu_to_be64(wr->compare_add);
3304 aseg->compare = cpu_to_be64(wr->compare_add_mask);
0fbfa6a9 3305 } else {
e622f2f4 3306 aseg->swap_add = cpu_to_be64(wr->compare_add);
0fbfa6a9
RD		 3307 aseg->compare = 0;
3308 }
3309
3310}
3311
6fa8f719 3312static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
f696bf6d 3313 const struct ib_atomic_wr *wr)
6fa8f719 3314{
e622f2f4
CH		 3315 aseg->swap_add = cpu_to_be64(wr->swap);
3316 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3317 aseg->compare = cpu_to_be64(wr->compare_add);
3318 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
6fa8f719
VS		 3319}
3320
0fbfa6a9 3321static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3322 const struct ib_ud_wr *wr)
0fbfa6a9 3323{
e622f2f4
CH		 3324 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3325 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3326 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3327 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3328 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
0fbfa6a9
RD		 3329}
3330
1ffeb2eb
JM		 3331static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3332 struct mlx4_wqe_datagram_seg *dseg,
f696bf6d 3333 const struct ib_ud_wr *wr,
97982f5a 3334 enum mlx4_ib_qp_type qpt)
1ffeb2eb 3335{
e622f2f4 3336 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
1ffeb2eb
JM		 3337 struct mlx4_av sqp_av = {0};
3338 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3339
3340 /* force loopback */
3341 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3342 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3343 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3344 cpu_to_be32(0xf0000000);
3345
3346 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
97982f5a 3347 if (qpt == MLX4_IB_QPT_PROXY_GSI)
c73c8b1e 3348 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
97982f5a 3349 else
c73c8b1e 3350 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
47605df9
JM		 3351 /* Use QKEY from the QP context, which is set by master */
3352 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1ffeb2eb
JM		 3353}
3354
f696bf6d
BVA		 3355static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3356 unsigned *mlx_seg_len)
1ffeb2eb
JM		 3357{
3358 struct mlx4_wqe_inline_seg *inl = wqe;
3359 struct mlx4_ib_tunnel_header hdr;
e622f2f4 3360 struct mlx4_ib_ah *ah = to_mah(wr->ah);
1ffeb2eb
JM		 3361 int spc;
3362 int i;
3363
3364 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
e622f2f4
CH		 3365 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3366 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3367 hdr.qkey = cpu_to_be32(wr->remote_qkey);
5ea8bbfc
JM		 3368 memcpy(hdr.mac, ah->av.eth.mac, 6);
3369 hdr.vlan = ah->av.eth.vlan;
1ffeb2eb
JM		 3370
3371 spc = MLX4_INLINE_ALIGN -
3372 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3373 if (sizeof (hdr) <= spc) {
3374 memcpy(inl + 1, &hdr, sizeof (hdr));
3375 wmb();
3376 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3377 i = 1;
3378 } else {
3379 memcpy(inl + 1, &hdr, spc);
3380 wmb();
3381 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3382
3383 inl = (void *) (inl + 1) + spc;
3384 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3385 wmb();
3386 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3387 i = 2;
3388 }
3389
3390 *mlx_seg_len =
3391 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3392}
3393
6e694ea3
JM		 3394static void set_mlx_icrc_seg(void *dseg)
3395{
3396 u32 *t = dseg;
3397 struct mlx4_wqe_inline_seg *iseg = dseg;
3398
3399 t[1] = 0;
3400
3401 /*
3402 * Need a barrier here before writing the byte_count field to
3403 * make sure that all the data is visible before the
3404 * byte_count field is set. Otherwise, if the segment begins
3405 * a new cacheline, the HCA prefetcher could grab the 64-byte
3406 * chunk and get a valid (!= * 0xffffffff) byte count but
3407 * stale data, and end up sending the wrong data.
3408 */
3409 wmb();
3410
3411 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3412}
3413
3414static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 3415{
d420d9e3
RD		 3416 dseg->lkey = cpu_to_be32(sg->lkey);
3417 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 3418
3419 /*
3420 * Need a barrier here before writing the byte_count field to
3421 * make sure that all the data is visible before the
3422 * byte_count field is set. Otherwise, if the segment begins
3423 * a new cacheline, the HCA prefetcher could grab the 64-byte
3424 * chunk and get a valid (!= * 0xffffffff) byte count but
3425 * stale data, and end up sending the wrong data.
3426 */
3427 wmb();
3428
3429 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 3430}
3431
2242fa4f
RD		 3432static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3433{
3434 dseg->byte_count = cpu_to_be32(sg->length);
3435 dseg->lkey = cpu_to_be32(sg->lkey);
3436 dseg->addr = cpu_to_be64(sg->addr);
3437}
3438
f696bf6d
BVA		 3439static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3440 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3441 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
b832be1e 3442{
e622f2f4 3443 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
b832be1e 3444
417608c2
EC		 3445 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3446 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 3447
3448 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
e622f2f4 3449 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
b832be1e
EC		 3450 return -EINVAL;
3451
e622f2f4 3452 memcpy(wqe->header, wr->header, wr->hlen);
b832be1e 3453
e622f2f4 3454 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
b832be1e
EC		 3455 *lso_seg_len = halign;
3456 return 0;
3457}
3458
f696bf6d 3459static __be32 send_ieth(const struct ib_send_wr *wr)
95d04f07
RD		 3460{
3461 switch (wr->opcode) {
3462 case IB_WR_SEND_WITH_IMM:
3463 case IB_WR_RDMA_WRITE_WITH_IMM:
3464 return wr->ex.imm_data;
3465
3466 case IB_WR_SEND_WITH_INV:
3467 return cpu_to_be32(wr->ex.invalidate_rkey);
3468
3469 default:
3470 return 0;
3471 }
3472}
3473
1ffeb2eb
JM		 3474static void add_zero_len_inline(void *wqe)
3475{
3476 struct mlx4_wqe_inline_seg *inl = wqe;
3477 memset(wqe, 0, 16);
3478 inl->byte_count = cpu_to_be32(1 << 31);
3479}
3480
d34ac5cd
BVA		 3481static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3482 const struct ib_send_wr **bad_wr, bool drain)
225c7b1f
RD		 3483{
3484 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3485 void *wqe;
3486 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 3487 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 3488 unsigned long flags;
3489 int nreq;
3490 int err = 0;
ea54b10c 3491 unsigned ind;
3f649ab7
KC		 3492 int size;
3493 unsigned seglen;
0fd7e1d8
RD		 3494 __be32 dummy;
3495 __be32 *lso_wqe;
3f649ab7 3496 __be32 lso_hdr_sz;
417608c2 3497 __be32 blh;
225c7b1f 3498 int i;
35f05dab 3499 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3500
e1b866c6 3501 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
915ec7ed 3502 struct mlx4_ib_sqp *sqp = qp->sqp;
e1b866c6
MS		 3503
3504 if (sqp->roce_v2_gsi) {
3505 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
a748d60d 3506 enum ib_gid_type gid_type;
e1b866c6
MS		 3507 union ib_gid gid;
3508
915ec7ed 3509 if (!fill_gid_by_hw_index(mdev, qp->port,
a748d60d
TB		 3510 ah->av.ib.gid_index,
3511 &gid, &gid_type))
3512 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3513 to_mqp(sqp->roce_v2_gsi) : qp;
3514 else
e1b866c6
MS		 3515 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3516 ah->av.ib.gid_index);
e1b866c6
MS		 3517 }
3518 }
3519
96db0e03 3520 spin_lock_irqsave(&qp->sq.lock, flags);
1975acd9
YH		 3521 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3522 !drain) {
35f05dab
YH		 3523 err = -EIO;
3524 *bad_wr = wr;
3525 nreq = 0;
3526 goto out;
3527 }
225c7b1f 3528
ea54b10c 3529 ind = qp->sq_next_wqe;
225c7b1f
RD		 3530
3531 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 3532 lso_wqe = &dummy;
417608c2 3533 blh = 0;
0fd7e1d8 3534
225c7b1f
RD		 3535 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3536 err = -ENOMEM;
3537 *bad_wr = wr;
3538 goto out;
3539 }
3540
3541 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3542 err = -EINVAL;
3543 *bad_wr = wr;
3544 goto out;
3545 }
3546
0e6e7416 3547 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 3548 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 3549
3550 ctrl->srcrb_flags =
3551 (wr->send_flags & IB_SEND_SIGNALED ?
3552 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3553 (wr->send_flags & IB_SEND_SOLICITED ?
3554 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 3555 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3556 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3557 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 3558 qp->sq_signal_bits;
3559
95d04f07 3560 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 3561
3562 wqe += sizeof *ctrl;
3563 size = sizeof *ctrl / 16;
3564
1ffeb2eb
JM		 3565 switch (qp->mlx4_ib_qp_type) {
3566 case MLX4_IB_QPT_RC:
3567 case MLX4_IB_QPT_UC:
225c7b1f
RD		 3568 switch (wr->opcode) {
3569 case IB_WR_ATOMIC_CMP_AND_SWP:
3570 case IB_WR_ATOMIC_FETCH_AND_ADD:
6fa8f719 3571 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
e622f2f4
CH		 3572 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3573 atomic_wr(wr)->rkey);
225c7b1f
RD		 3574 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3575
e622f2f4 3576 set_atomic_seg(wqe, atomic_wr(wr));
225c7b1f 3577 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 3578
225c7b1f
RD		 3579 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3580 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
6fa8f719
VS		 3581
3582 break;
3583
3584 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
e622f2f4
CH		 3585 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3586 atomic_wr(wr)->rkey);
6fa8f719
VS		 3587 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3588
e622f2f4 3589 set_masked_atomic_seg(wqe, atomic_wr(wr));
6fa8f719
VS		 3590 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3591
3592 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3593 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
225c7b1f
RD		 3594
3595 break;
3596
3597 case IB_WR_RDMA_READ:
3598 case IB_WR_RDMA_WRITE:
3599 case IB_WR_RDMA_WRITE_WITH_IMM:
e622f2f4
CH		 3600 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3601 rdma_wr(wr)->rkey);
225c7b1f
RD		 3602 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3603 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 3604 break;
95d04f07
RD		 3605
3606 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 3607 ctrl->srcrb_flags |=
3608 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 3609 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3610 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3611 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3612 break;
3613
1b2cd0fc
SG		 3614 case IB_WR_REG_MR:
3615 ctrl->srcrb_flags |=
3616 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3617 set_reg_seg(wqe, reg_wr(wr));
3618 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3619 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3620 break;
3621
225c7b1f
RD		 3622 default:
3623 /* No extra segments required for sends */
3624 break;
3625 }
3626 break;
3627
1ffeb2eb 3628 case MLX4_IB_QPT_TUN_SMI_OWNER:
915ec7ed
LR		 3629 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3630 &seglen);
1ffeb2eb
JM		 3631 if (unlikely(err)) {
3632 *bad_wr = wr;
3633 goto out;
3634 }
3635 wqe += seglen;
3636 size += seglen / 16;
3637 break;
3638 case MLX4_IB_QPT_TUN_SMI:
3639 case MLX4_IB_QPT_TUN_GSI:
3640 /* this is a UD qp used in MAD responses to slaves. */
e622f2f4 3641 set_datagram_seg(wqe, ud_wr(wr));
1ffeb2eb
JM		 3642 /* set the forced-loopback bit in the data seg av */
3643 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3644 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3645 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3646 break;
3647 case MLX4_IB_QPT_UD:
e622f2f4 3648 set_datagram_seg(wqe, ud_wr(wr));
225c7b1f
RD		 3649 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3650 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 3651
3652 if (wr->opcode == IB_WR_LSO) {
e622f2f4
CH		 3653 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3654 &lso_hdr_sz, &blh);
b832be1e
EC		 3655 if (unlikely(err)) {
3656 *bad_wr = wr;
3657 goto out;
3658 }
0fd7e1d8 3659 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 3660 wqe += seglen;
3661 size += seglen / 16;
3662 }
225c7b1f
RD		 3663 break;
3664
1ffeb2eb 3665 case MLX4_IB_QPT_PROXY_SMI_OWNER:
915ec7ed
LR		 3666 err = build_sriov_qp0_header(qp, ud_wr(wr), ctrl,
3667 &seglen);
1ffeb2eb
JM		 3668 if (unlikely(err)) {
3669 *bad_wr = wr;
3670 goto out;
3671 }
3672 wqe += seglen;
3673 size += seglen / 16;
3674 /* to start tunnel header on a cache-line boundary */
3675 add_zero_len_inline(wqe);
3676 wqe += 16;
3677 size++;
e622f2f4 3678 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3679 wqe += seglen;
3680 size += seglen / 16;
3681 break;
3682 case MLX4_IB_QPT_PROXY_SMI:
1ffeb2eb
JM		 3683 case MLX4_IB_QPT_PROXY_GSI:
3684 /* If we are tunneling special qps, this is a UD qp.
3685 * In this case we first add a UD segment targeting
3686 * the tunnel qp, and then add a header with address
3687 * information */
e622f2f4
CH		 3688 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3689 ud_wr(wr),
97982f5a 3690 qp->mlx4_ib_qp_type);
1ffeb2eb
JM		 3691 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3692 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
e622f2f4 3693 build_tunnel_header(ud_wr(wr), wqe, &seglen);
1ffeb2eb
JM		 3694 wqe += seglen;
3695 size += seglen / 16;
3696 break;
3697
3698 case MLX4_IB_QPT_SMI:
3699 case MLX4_IB_QPT_GSI:
915ec7ed 3700 err = build_mlx_header(qp, ud_wr(wr), ctrl, &seglen);
f438000f 3701 if (unlikely(err)) {
225c7b1f
RD		 3702 *bad_wr = wr;
3703 goto out;
3704 }
f438000f
RD		 3705 wqe += seglen;
3706 size += seglen / 16;
225c7b1f
RD		 3707 break;
3708
3709 default:
3710 break;
3711 }
3712
6e694ea3
JM		 3713 /*
3714 * Write data segments in reverse order, so as to
3715 * overwrite cacheline stamp last within each
3716 * cacheline. This avoids issues with WQE
3717 * prefetching.
3718 */
225c7b1f 3719
6e694ea3
JM		 3720 dseg = wqe;
3721 dseg += wr->num_sge - 1;
3722 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 3723
3724 /* Add one more inline data segment for ICRC for MLX sends */
1ffeb2eb
JM		 3725 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3726 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3727 qp->mlx4_ib_qp_type &
3728 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
6e694ea3 3729 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 3730 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3731 }
3732
6e694ea3
JM		 3733 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3734 set_data_seg(dseg, wr->sg_list + i);
3735
0fd7e1d8
RD		 3736 /*
3737 * Possibly overwrite stamping in cacheline with LSO
3738 * segment only after making sure all data segments
3739 * are written.
3740 */
3741 wmb();
3742 *lso_wqe = lso_hdr_sz;
3743
224e92e0
BB		 3744 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3745 MLX4_WQE_CTRL_FENCE : 0) | size;
225c7b1f
RD		 3746
3747 /*
3748 * Make sure descriptor is fully written before
3749 * setting ownership bit (because HW can start
3750 * executing as soon as we do).
3751 */
3752 wmb();
3753
59b0ed12 3754 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
4ba6b8ea 3755 *bad_wr = wr;
225c7b1f
RD		 3756 err = -EINVAL;
3757 goto out;
3758 }
3759
3760 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 3761 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416
RD		 3762
3763 /*
3764 * We can improve latency by not stamping the last
3765 * send queue WQE until after ringing the doorbell, so
3766 * only stamp here if there are still more WQEs to post.
3767 */
f95ccffc
JM		 3768 if (wr->next)
3769 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3770 ind++;
225c7b1f
RD		 3771 }
3772
3773out:
3774 if (likely(nreq)) {
3775 qp->sq.head += nreq;
3776
3777 /*
3778 * Make sure that descriptors are written before
3779 * doorbell record.
3780 */
3781 wmb();
3782
97d82a48
SK		 3783 writel_relaxed(qp->doorbell_qpn,
3784 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
225c7b1f 3785
f95ccffc 3786 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
ea54b10c 3787
ea54b10c 3788 qp->sq_next_wqe = ind;
225c7b1f
RD		 3789 }
3790
96db0e03 3791 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 3792
3793 return err;
3794}
3795
d34ac5cd
BVA		 3796int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3797 const struct ib_send_wr **bad_wr)
1975acd9
YH		 3798{
3799 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3800}
3801
d34ac5cd
BVA		 3802static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3803 const struct ib_recv_wr **bad_wr, bool drain)
225c7b1f
RD		 3804{
3805 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3806 struct mlx4_wqe_data_seg *scat;
3807 unsigned long flags;
3808 int err = 0;
3809 int nreq;
3810 int ind;
1ffeb2eb 3811 int max_gs;
225c7b1f 3812 int i;
35f05dab 3813 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
225c7b1f 3814
1ffeb2eb 3815 max_gs = qp->rq.max_gs;
225c7b1f
RD		 3816 spin_lock_irqsave(&qp->rq.lock, flags);
3817
1975acd9
YH		 3818 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3819 !drain) {
35f05dab
YH		 3820 err = -EIO;
3821 *bad_wr = wr;
3822 nreq = 0;
3823 goto out;
3824 }
3825
0e6e7416 3826 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3827
3828 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 3829 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 3830 err = -ENOMEM;
3831 *bad_wr = wr;
3832 goto out;
3833 }
3834
3835 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3836 err = -EINVAL;
3837 *bad_wr = wr;
3838 goto out;
3839 }
3840
3841 scat = get_recv_wqe(qp, ind);
3842
1ffeb2eb
JM		 3843 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3844 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3845 ib_dma_sync_single_for_device(ibqp->device,
3846 qp->sqp_proxy_rcv[ind].map,
3847 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3848 DMA_FROM_DEVICE);
3849 scat->byte_count =
3850 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3851 /* use dma lkey from upper layer entry */
3852 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3853 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3854 scat++;
3855 max_gs--;
3856 }
3857
2242fa4f
RD		 3858 for (i = 0; i < wr->num_sge; ++i)
3859 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f 3860
1ffeb2eb 3861 if (i < max_gs) {
225c7b1f
RD		 3862 scat[i].byte_count = 0;
3863 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3864 scat[i].addr = 0;
3865 }
3866
3867 qp->rq.wrid[ind] = wr->wr_id;
3868
0e6e7416 3869 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 3870 }
3871
3872out:
3873 if (likely(nreq)) {
3874 qp->rq.head += nreq;
3875
3876 /*
3877 * Make sure that descriptors are written before
3878 * doorbell record.
3879 */
3880 wmb();
3881
3882 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3883 }
3884
3885 spin_unlock_irqrestore(&qp->rq.lock, flags);
3886
3887 return err;
3888}
6a775e2b 3889
d34ac5cd
BVA		 3890int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3891 const struct ib_recv_wr **bad_wr)
1975acd9
YH		 3892{
3893 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3894}
3895
6a775e2b
JM		 3896static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3897{
3898 switch (mlx4_state) {
3899 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3900 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3901 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3902 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3903 case MLX4_QP_STATE_SQ_DRAINING:
3904 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3905 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3906 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3907 default: return -1;
3908 }
3909}
3910
3911static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3912{
3913 switch (mlx4_mig_state) {
3914 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3915 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3916 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3917 default: return -1;
3918 }
3919}
3920
3921static int to_ib_qp_access_flags(int mlx4_flags)
3922{
3923 int ib_flags = 0;
3924
3925 if (mlx4_flags & MLX4_QP_BIT_RRE)
3926 ib_flags |= IB_ACCESS_REMOTE_READ;
3927 if (mlx4_flags & MLX4_QP_BIT_RWE)
3928 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3929 if (mlx4_flags & MLX4_QP_BIT_RAE)
3930 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3931
3932 return ib_flags;
3933}
3934
71d53ab4 3935static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
d8966fcd 3936 struct rdma_ah_attr *ah_attr,
71d53ab4 3937 struct mlx4_qp_path *path)
6a775e2b 3938{
4c3eb3ca 3939 struct mlx4_dev *dev = ibdev->dev;
d8966fcd 3940 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4c3eb3ca 3941
d8966fcd 3942 memset(ah_attr, 0, sizeof(*ah_attr));
d8966fcd 3943 if (port_num == 0 || port_num > dev->caps.num_ports)
6a775e2b 3944 return;
f1228867 3945 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
6a775e2b 3946
44c58487 3947 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
d8966fcd
DC		 3948 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3949 ((path->sched_queue & 4) << 1));
4c3eb3ca 3950 else
d8966fcd 3951 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
44c58487 3952 rdma_ah_set_port_num(ah_attr, port_num);
4c3eb3ca 3953
d8966fcd
DC		 3954 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3955 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3956 rdma_ah_set_static_rate(ah_attr,
3957 path->static_rate ? path->static_rate - 5 : 0);
3958 if (path->grh_mylmc & (1 << 7)) {
3959 rdma_ah_set_grh(ah_attr, NULL,
3960 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3961 path->mgid_index,
3962 path->hop_limit,
3963 (be32_to_cpu(path->tclass_flowlabel)
3964 >> 20) & 0xff);
3965 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
6a775e2b
JM		 3966 }
3967}
3968
3969int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3970 struct ib_qp_init_attr *qp_init_attr)
3971{
3972 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3973 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3974 struct mlx4_qp_context context;
3975 int mlx4_state;
0df67030
DB		 3976 int err = 0;
3977
3078f5f1
GL		 3978 if (ibqp->rwq_ind_tbl)
3979 return -EOPNOTSUPP;
3980
0df67030 3981 mutex_lock(&qp->mutex);
6a775e2b
JM		 3982
3983 if (qp->state == IB_QPS_RESET) {
3984 qp_attr->qp_state = IB_QPS_RESET;
3985 goto done;
3986 }
3987
3988 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 3989 if (err) {
3990 err = -EINVAL;
3991 goto out;
3992 }
6a775e2b
JM		 3993
3994 mlx4_state = be32_to_cpu(context.flags) >> 28;
3995
0df67030
DB		 3996 qp->state = to_ib_qp_state(mlx4_state);
3997 qp_attr->qp_state = qp->state;
6a775e2b
JM		 3998 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3999 qp_attr->path_mig_state =
4000 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4001 qp_attr->qkey = be32_to_cpu(context.qkey);
4002 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4003 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4004 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4005 qp_attr->qp_access_flags =
4006 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4007
8138a4c2
AH		 4008 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC ||
4009 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
4010 qp->ibqp.qp_type == IB_QPT_XRC_TGT) {
71d53ab4
DC		 4011 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4012 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
6a775e2b 4013 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
d8966fcd
DC		 4014 qp_attr->alt_port_num =
4015 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
6a775e2b
JM		 4016 }
4017
4018 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 4019 if (qp_attr->qp_state == IB_QPS_INIT)
4020 qp_attr->port_num = qp->port;
4021 else
4022 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 4023
4024 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4025 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4026
4027 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4028
4029 qp_attr->max_dest_rd_atomic =
4030 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4031 qp_attr->min_rnr_timer =
4032 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4033 qp_attr->timeout = context.pri_path.ackto >> 3;
4034 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4035 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4036 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4037
4038done:
4039 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 4040 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4041 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4042
6a775e2b 4043 if (!ibqp->uobject) {
7f5eb9bb
RD		 4044 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4045 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4046 } else {
4047 qp_attr->cap.max_send_wr = 0;
4048 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 4049 }
4050
7f5eb9bb
RD		 4051 /*
4052 * We don't support inline sends for kernel QPs (yet), and we
4053 * don't know what userspace's value should be.
4054 */
4055 qp_attr->cap.max_inline_data = 0;
4056
4057 qp_init_attr->cap = qp_attr->cap;
4058
521e575b
RL		 4059 qp_init_attr->create_flags = 0;
4060 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4061 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4062
4063 if (qp->flags & MLX4_IB_QP_LSO)
4064 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4065
c1c98501
MB		 4066 if (qp->flags & MLX4_IB_QP_NETIF)
4067 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4068
46db567d
DB		 4069 qp_init_attr->sq_sig_type =
4070 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4071 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4072
0df67030
DB		 4073out:
4074 mutex_unlock(&qp->mutex);
4075 return err;
6a775e2b
JM		 4076}
4077
400b1ebc
GL		 4078struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4079 struct ib_wq_init_attr *init_attr,
4080 struct ib_udata *udata)
4081{
089b645d
LR		 4082 struct mlx4_dev *dev = to_mdev(pd->device)->dev;
4083 struct ib_qp_init_attr ib_qp_init_attr = {};
400b1ebc
GL		 4084 struct mlx4_ib_qp *qp;
4085 struct mlx4_ib_create_wq ucmd;
4086 int err, required_cmd_sz;
4087
e00b64f7 4088 if (!udata)
400b1ebc
GL		 4089 return ERR_PTR(-EINVAL);
4090
078b3573
GL		 4091 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4092 sizeof(ucmd.comp_mask);
400b1ebc
GL		 4093 if (udata->inlen < required_cmd_sz) {
4094 pr_debug("invalid inlen\n");
4095 return ERR_PTR(-EINVAL);
4096 }
4097
4098 if (udata->inlen > sizeof(ucmd) &&
4099 !ib_is_udata_cleared(udata, sizeof(ucmd),
4100 udata->inlen - sizeof(ucmd))) {
4101 pr_debug("inlen is not supported\n");
4102 return ERR_PTR(-EOPNOTSUPP);
4103 }
4104
4105 if (udata->outlen)
4106 return ERR_PTR(-EOPNOTSUPP);
4107
400b1ebc
GL		 4108 if (init_attr->wq_type != IB_WQT_RQ) {
4109 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4110 return ERR_PTR(-EOPNOTSUPP);
4111 }
4112
089b645d
LR		 4113 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS ||
4114 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
400b1ebc
GL		 4115 pr_debug("unsupported create_flags %u\n",
4116 init_attr->create_flags);
4117 return ERR_PTR(-EOPNOTSUPP);
4118 }
4119
4120 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4121 if (!qp)
4122 return ERR_PTR(-ENOMEM);
4123
8fd3cd2a 4124 mutex_init(&qp->mutex);
400b1ebc
GL		 4125 qp->pri.vid = 0xFFFF;
4126 qp->alt.vid = 0xFFFF;
4127
400b1ebc
GL		 4128 ib_qp_init_attr.qp_context = init_attr->wq_context;
4129 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4130 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4131 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4132 ib_qp_init_attr.recv_cq = init_attr->cq;
4133 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4134
6d06c9aa
GL		 4135 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4136 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4137
089b645d 4138 err = create_rq(pd, &ib_qp_init_attr, udata, qp);
400b1ebc
GL		 4139 if (err) {
4140 kfree(qp);
4141 return ERR_PTR(err);
4142 }
4143
4144 qp->ibwq.event_handler = init_attr->event_handler;
4145 qp->ibwq.wq_num = qp->mqp.qpn;
4146 qp->ibwq.state = IB_WQS_RESET;
4147
4148 return &qp->ibwq;
4149}
4150
4151static int ib_wq2qp_state(enum ib_wq_state state)
4152{
4153 switch (state) {
4154 case IB_WQS_RESET:
4155 return IB_QPS_RESET;
4156 case IB_WQS_RDY:
4157 return IB_QPS_RTR;
4158 default:
4159 return IB_QPS_ERR;
4160 }
4161}
4162
89944450
SR		 4163static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state,
4164 struct ib_udata *udata)
400b1ebc
GL		 4165{
4166 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4167 enum ib_qp_state qp_cur_state;
4168 enum ib_qp_state qp_new_state;
4169 int attr_mask;
4170 int err;
4171
4172 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4173 * the WQ logic state.
4174 */
4175 qp_cur_state = qp->state;
4176 qp_new_state = ib_wq2qp_state(new_state);
4177
4178 if (ib_wq2qp_state(new_state) == qp_cur_state)
4179 return 0;
4180
4181 if (new_state == IB_WQS_RDY) {
4182 struct ib_qp_attr attr = {};
4183
4184 attr.port_num = qp->port;
4185 attr_mask = IB_QP_PORT;
4186
4187 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
89944450
SR		 4188 attr_mask, IB_QPS_RESET, IB_QPS_INIT,
4189 udata);
400b1ebc
GL		 4190 if (err) {
4191 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4192 ibwq->wq_num);
4193 return err;
4194 }
4195
4196 qp_cur_state = IB_QPS_INIT;
4197 }
4198
4199 attr_mask = 0;
4200 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
89944450 4201 qp_cur_state, qp_new_state, udata);
400b1ebc
GL		 4202
4203 if (err && (qp_cur_state == IB_QPS_INIT)) {
4204 qp_new_state = IB_QPS_RESET;
4205 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
89944450
SR		 4206 attr_mask, IB_QPS_INIT, IB_QPS_RESET,
4207 udata)) {
400b1ebc
GL		 4208 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4209 ibwq->wq_num);
4210 qp_new_state = IB_QPS_INIT;
4211 }
4212 }
4213
4214 qp->state = qp_new_state;
4215
4216 return err;
4217}
4218
4219int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4220 u32 wq_attr_mask, struct ib_udata *udata)
4221{
4222 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4223 struct mlx4_ib_modify_wq ucmd = {};
4224 size_t required_cmd_sz;
4225 enum ib_wq_state cur_state, new_state;
4226 int err = 0;
4227
4228 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4229 sizeof(ucmd.reserved);
4230 if (udata->inlen < required_cmd_sz)
4231 return -EINVAL;
4232
4233 if (udata->inlen > sizeof(ucmd) &&
4234 !ib_is_udata_cleared(udata, sizeof(ucmd),
4235 udata->inlen - sizeof(ucmd)))
4236 return -EOPNOTSUPP;
4237
4238 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4239 return -EFAULT;
4240
4241 if (ucmd.comp_mask || ucmd.reserved)
4242 return -EOPNOTSUPP;
4243
4244 if (wq_attr_mask & IB_WQ_FLAGS)
4245 return -EOPNOTSUPP;
4246
f9744288
LR		 4247 cur_state = wq_attr->curr_wq_state;
4248 new_state = wq_attr->wq_state;
400b1ebc
GL		 4249
4250 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4251 return -EINVAL;
4252
4253 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4254 return -EINVAL;
4255
3078f5f1
GL		 4256 /* Need to protect against the parent RSS which also may modify WQ
4257 * state.
4258 */
4259 mutex_lock(&qp->mutex);
4260
400b1ebc
GL		 4261 /* Can update HW state only if a RSS QP has already associated to this
4262 * WQ, so we can apply its port on the WQ.
4263 */
4264 if (qp->rss_usecnt)
89944450 4265 err = _mlx4_ib_modify_wq(ibwq, new_state, udata);
400b1ebc
GL		 4266
4267 if (!err)
4268 ibwq->state = new_state;
4269
3078f5f1
GL		 4270 mutex_unlock(&qp->mutex);
4271
400b1ebc
GL		 4272 return err;
4273}
4274
add53535 4275int mlx4_ib_destroy_wq(struct ib_wq *ibwq, struct ib_udata *udata)
400b1ebc
GL		 4276{
4277 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4278 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4279
4280 if (qp->counter_index)
4281 mlx4_ib_free_qp_counter(dev, qp);
4282
bdeacabd 4283 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, udata);
400b1ebc
GL		 4284
4285 kfree(qp);
add53535 4286 return 0;
400b1ebc 4287}
b8d46ca0 4288
c0a6b5ec
LR		 4289int mlx4_ib_create_rwq_ind_table(struct ib_rwq_ind_table *rwq_ind_table,
4290 struct ib_rwq_ind_table_init_attr *init_attr,
4291 struct ib_udata *udata)
b8d46ca0 4292{
b8d46ca0
GL		 4293 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4294 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
c0a6b5ec 4295 struct ib_device *device = rwq_ind_table->device;
b8d46ca0
GL		 4296 unsigned int base_wqn;
4297 size_t min_resp_len;
c0a6b5ec 4298 int i, err = 0;
b8d46ca0
GL		 4299
4300 if (udata->inlen > 0 &&
4301 !ib_is_udata_cleared(udata, 0,
4302 udata->inlen))
c0a6b5ec 4303 return -EOPNOTSUPP;
b8d46ca0
GL		 4304
4305 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4306 if (udata->outlen && udata->outlen < min_resp_len)
c0a6b5ec 4307 return -EINVAL;
b8d46ca0
GL		 4308
4309 if (ind_tbl_size >
4310 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4311 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4312 ind_tbl_size,
4313 device->attrs.rss_caps.max_rwq_indirection_table_size);
c0a6b5ec 4314 return -EINVAL;
b8d46ca0
GL		 4315 }
4316
4317 base_wqn = init_attr->ind_tbl[0]->wq_num;
4318
4319 if (base_wqn % ind_tbl_size) {
4320 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4321 base_wqn);
c0a6b5ec 4322 return -EINVAL;
b8d46ca0
GL		 4323 }
4324
4325 for (i = 1; i < ind_tbl_size; i++) {
4326 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4327 pr_debug("indirection table's WQNs aren't consecutive\n");
c0a6b5ec 4328 return -EINVAL;
b8d46ca0
GL		 4329 }
4330 }
4331
b8d46ca0
GL		 4332 if (udata->outlen) {
4333 resp.response_length = offsetof(typeof(resp), response_length) +
4334 sizeof(resp.response_length);
4335 err = ib_copy_to_udata(udata, &resp, resp.response_length);
b8d46ca0
GL		 4336 }
4337
c0a6b5ec 4338 return err;
b8d46ca0 4339}
1975acd9
YH		 4340
4341struct mlx4_ib_drain_cqe {
4342 struct ib_cqe cqe;
4343 struct completion done;
4344};
4345
4346static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4347{
4348 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4349 struct mlx4_ib_drain_cqe,
4350 cqe);
4351
4352 complete(&cqe->done);
4353}
4354
4355/* This function returns only once the drained WR was completed */
4356static void handle_drain_completion(struct ib_cq *cq,
4357 struct mlx4_ib_drain_cqe *sdrain,
4358 struct mlx4_ib_dev *dev)
4359{
4360 struct mlx4_dev *mdev = dev->dev;
4361
4362 if (cq->poll_ctx == IB_POLL_DIRECT) {
4363 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4364 ib_process_cq_direct(cq, -1);
4365 return;
4366 }
4367
4368 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4369 struct mlx4_ib_cq *mcq = to_mcq(cq);
4370 bool triggered = false;
4371 unsigned long flags;
4372
4373 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4374 /* Make sure that the CQ handler won't run if wasn't run yet */
4375 if (!mcq->mcq.reset_notify_added)
4376 mcq->mcq.reset_notify_added = 1;
4377 else
4378 triggered = true;
4379 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4380
4381 if (triggered) {
4382 /* Wait for any scheduled/running task to be ended */
4383 switch (cq->poll_ctx) {
4384 case IB_POLL_SOFTIRQ:
4385 irq_poll_disable(&cq->iop);
4386 irq_poll_enable(&cq->iop);
4387 break;
4388 case IB_POLL_WORKQUEUE:
4389 cancel_work_sync(&cq->work);
4390 break;
4391 default:
4392 WARN_ON_ONCE(1);
4393 }
4394 }
4395
4396 /* Run the CQ handler - this makes sure that the drain WR will
4397 * be processed if wasn't processed yet.
4398 */
4399 mcq->mcq.comp(&mcq->mcq);
4400 }
4401
4402 wait_for_completion(&sdrain->done);
4403}
4404
4405void mlx4_ib_drain_sq(struct ib_qp *qp)
4406{
4407 struct ib_cq *cq = qp->send_cq;
4408 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4409 struct mlx4_ib_drain_cqe sdrain;
d34ac5cd 4410 const struct ib_send_wr *bad_swr;
1975acd9
YH		 4411 struct ib_rdma_wr swr = {
4412 .wr = {
4413 .next = NULL,
4414 { .wr_cqe = &sdrain.cqe, },
4415 .opcode = IB_WR_RDMA_WRITE,
4416 },
4417 };
4418 int ret;
4419 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4420 struct mlx4_dev *mdev = dev->dev;
4421
4422 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4423 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4424 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4425 return;
4426 }
4427
4428 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4429 init_completion(&sdrain.done);
4430
4431 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4432 if (ret) {
4433 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4434 return;
4435 }
4436
4437 handle_drain_completion(cq, &sdrain, dev);
4438}
4439
4440void mlx4_ib_drain_rq(struct ib_qp *qp)
4441{
4442 struct ib_cq *cq = qp->recv_cq;
4443 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4444 struct mlx4_ib_drain_cqe rdrain;
d34ac5cd
BVA		 4445 struct ib_recv_wr rwr = {};
4446 const struct ib_recv_wr *bad_rwr;
1975acd9
YH		 4447 int ret;
4448 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4449 struct mlx4_dev *mdev = dev->dev;
4450
4451 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4452 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4453 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4454 return;
4455 }
4456
4457 rwr.wr_cqe = &rdrain.cqe;
4458 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4459 init_completion(&rdrain.done);
4460
4461 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4462 if (ret) {
4463 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4464 return;
4465 }
4466
4467 handle_drain_completion(cq, &rdrain, dev);
4468}
Linux 6.x block layer and io_uring tree(s)