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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
ea54b10c JM |
33 | #include <linux/log2.h> |
34 | ||
225c7b1f RD |
35 | #include <rdma/ib_cache.h> |
36 | #include <rdma/ib_pack.h> | |
37 | ||
38 | #include <linux/mlx4/qp.h> | |
39 | ||
40 | #include "mlx4_ib.h" | |
41 | #include "user.h" | |
42 | ||
43 | enum { | |
44 | MLX4_IB_ACK_REQ_FREQ = 8, | |
45 | }; | |
46 | ||
47 | enum { | |
48 | MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, | |
49 | MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f | |
50 | }; | |
51 | ||
52 | enum { | |
53 | /* | |
54 | * Largest possible UD header: send with GRH and immediate data. | |
55 | */ | |
56 | MLX4_IB_UD_HEADER_SIZE = 72 | |
57 | }; | |
58 | ||
59 | struct mlx4_ib_sqp { | |
60 | struct mlx4_ib_qp qp; | |
61 | int pkey_index; | |
62 | u32 qkey; | |
63 | u32 send_psn; | |
64 | struct ib_ud_header ud_header; | |
65 | u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; | |
66 | }; | |
67 | ||
83904132 JM |
68 | enum { |
69 | MLX4_IB_MIN_SQ_STRIDE = 6 | |
70 | }; | |
71 | ||
225c7b1f RD |
72 | static const __be32 mlx4_ib_opcode[] = { |
73 | [IB_WR_SEND] = __constant_cpu_to_be32(MLX4_OPCODE_SEND), | |
b832be1e | 74 | [IB_WR_LSO] = __constant_cpu_to_be32(MLX4_OPCODE_LSO), |
225c7b1f RD |
75 | [IB_WR_SEND_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM), |
76 | [IB_WR_RDMA_WRITE] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), | |
77 | [IB_WR_RDMA_WRITE_WITH_IMM] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), | |
78 | [IB_WR_RDMA_READ] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ), | |
79 | [IB_WR_ATOMIC_CMP_AND_SWP] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), | |
80 | [IB_WR_ATOMIC_FETCH_AND_ADD] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), | |
81 | }; | |
82 | ||
83 | static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) | |
84 | { | |
85 | return container_of(mqp, struct mlx4_ib_sqp, qp); | |
86 | } | |
87 | ||
88 | static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) | |
89 | { | |
90 | return qp->mqp.qpn >= dev->dev->caps.sqp_start && | |
91 | qp->mqp.qpn <= dev->dev->caps.sqp_start + 3; | |
92 | } | |
93 | ||
94 | static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) | |
95 | { | |
96 | return qp->mqp.qpn >= dev->dev->caps.sqp_start && | |
97 | qp->mqp.qpn <= dev->dev->caps.sqp_start + 1; | |
98 | } | |
99 | ||
100 | static void *get_wqe(struct mlx4_ib_qp *qp, int offset) | |
101 | { | |
1c69fc2a | 102 | return mlx4_buf_offset(&qp->buf, offset); |
225c7b1f RD |
103 | } |
104 | ||
105 | static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) | |
106 | { | |
107 | return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); | |
108 | } | |
109 | ||
110 | static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) | |
111 | { | |
112 | return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); | |
113 | } | |
114 | ||
0e6e7416 RD |
115 | /* |
116 | * Stamp a SQ WQE so that it is invalid if prefetched by marking the | |
ea54b10c JM |
117 | * first four bytes of every 64 byte chunk with |
118 | * 0x7FFFFFF | (invalid_ownership_value << 31). | |
119 | * | |
120 | * When the max work request size is less than or equal to the WQE | |
121 | * basic block size, as an optimization, we can stamp all WQEs with | |
122 | * 0xffffffff, and skip the very first chunk of each WQE. | |
0e6e7416 | 123 | */ |
ea54b10c | 124 | static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) |
0e6e7416 | 125 | { |
d2ae16d5 | 126 | __be32 *wqe; |
0e6e7416 | 127 | int i; |
ea54b10c JM |
128 | int s; |
129 | int ind; | |
130 | void *buf; | |
131 | __be32 stamp; | |
9670e553 | 132 | struct mlx4_wqe_ctrl_seg *ctrl; |
ea54b10c | 133 | |
ea54b10c | 134 | if (qp->sq_max_wqes_per_wr > 1) { |
9670e553 | 135 | s = roundup(size, 1U << qp->sq.wqe_shift); |
ea54b10c JM |
136 | for (i = 0; i < s; i += 64) { |
137 | ind = (i >> qp->sq.wqe_shift) + n; | |
138 | stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : | |
139 | cpu_to_be32(0xffffffff); | |
140 | buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); | |
141 | wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); | |
142 | *wqe = stamp; | |
143 | } | |
144 | } else { | |
9670e553 EC |
145 | ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); |
146 | s = (ctrl->fence_size & 0x3f) << 4; | |
ea54b10c JM |
147 | for (i = 64; i < s; i += 64) { |
148 | wqe = buf + i; | |
d2ae16d5 | 149 | *wqe = cpu_to_be32(0xffffffff); |
ea54b10c JM |
150 | } |
151 | } | |
152 | } | |
153 | ||
154 | static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) | |
155 | { | |
156 | struct mlx4_wqe_ctrl_seg *ctrl; | |
157 | struct mlx4_wqe_inline_seg *inl; | |
158 | void *wqe; | |
159 | int s; | |
160 | ||
161 | ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); | |
162 | s = sizeof(struct mlx4_wqe_ctrl_seg); | |
163 | ||
164 | if (qp->ibqp.qp_type == IB_QPT_UD) { | |
165 | struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; | |
166 | struct mlx4_av *av = (struct mlx4_av *)dgram->av; | |
167 | memset(dgram, 0, sizeof *dgram); | |
168 | av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); | |
169 | s += sizeof(struct mlx4_wqe_datagram_seg); | |
170 | } | |
171 | ||
172 | /* Pad the remainder of the WQE with an inline data segment. */ | |
173 | if (size > s) { | |
174 | inl = wqe + s; | |
175 | inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl)); | |
176 | } | |
177 | ctrl->srcrb_flags = 0; | |
178 | ctrl->fence_size = size / 16; | |
179 | /* | |
180 | * Make sure descriptor is fully written before setting ownership bit | |
181 | * (because HW can start executing as soon as we do). | |
182 | */ | |
183 | wmb(); | |
184 | ||
185 | ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | | |
186 | (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); | |
0e6e7416 | 187 | |
ea54b10c JM |
188 | stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); |
189 | } | |
190 | ||
191 | /* Post NOP WQE to prevent wrap-around in the middle of WR */ | |
192 | static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) | |
193 | { | |
194 | unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); | |
195 | if (unlikely(s < qp->sq_max_wqes_per_wr)) { | |
196 | post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); | |
197 | ind += s; | |
198 | } | |
199 | return ind; | |
0e6e7416 RD |
200 | } |
201 | ||
225c7b1f RD |
202 | static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) |
203 | { | |
204 | struct ib_event event; | |
205 | struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; | |
206 | ||
207 | if (type == MLX4_EVENT_TYPE_PATH_MIG) | |
208 | to_mibqp(qp)->port = to_mibqp(qp)->alt_port; | |
209 | ||
210 | if (ibqp->event_handler) { | |
211 | event.device = ibqp->device; | |
212 | event.element.qp = ibqp; | |
213 | switch (type) { | |
214 | case MLX4_EVENT_TYPE_PATH_MIG: | |
215 | event.event = IB_EVENT_PATH_MIG; | |
216 | break; | |
217 | case MLX4_EVENT_TYPE_COMM_EST: | |
218 | event.event = IB_EVENT_COMM_EST; | |
219 | break; | |
220 | case MLX4_EVENT_TYPE_SQ_DRAINED: | |
221 | event.event = IB_EVENT_SQ_DRAINED; | |
222 | break; | |
223 | case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: | |
224 | event.event = IB_EVENT_QP_LAST_WQE_REACHED; | |
225 | break; | |
226 | case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: | |
227 | event.event = IB_EVENT_QP_FATAL; | |
228 | break; | |
229 | case MLX4_EVENT_TYPE_PATH_MIG_FAILED: | |
230 | event.event = IB_EVENT_PATH_MIG_ERR; | |
231 | break; | |
232 | case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: | |
233 | event.event = IB_EVENT_QP_REQ_ERR; | |
234 | break; | |
235 | case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: | |
236 | event.event = IB_EVENT_QP_ACCESS_ERR; | |
237 | break; | |
238 | default: | |
239 | printk(KERN_WARNING "mlx4_ib: Unexpected event type %d " | |
240 | "on QP %06x\n", type, qp->qpn); | |
241 | return; | |
242 | } | |
243 | ||
244 | ibqp->event_handler(&event, ibqp->qp_context); | |
245 | } | |
246 | } | |
247 | ||
b832be1e | 248 | static int send_wqe_overhead(enum ib_qp_type type, u32 flags) |
225c7b1f RD |
249 | { |
250 | /* | |
251 | * UD WQEs must have a datagram segment. | |
252 | * RC and UC WQEs might have a remote address segment. | |
253 | * MLX WQEs need two extra inline data segments (for the UD | |
254 | * header and space for the ICRC). | |
255 | */ | |
256 | switch (type) { | |
257 | case IB_QPT_UD: | |
258 | return sizeof (struct mlx4_wqe_ctrl_seg) + | |
b832be1e EC |
259 | sizeof (struct mlx4_wqe_datagram_seg) + |
260 | ((flags & MLX4_IB_QP_LSO) ? 64 : 0); | |
225c7b1f RD |
261 | case IB_QPT_UC: |
262 | return sizeof (struct mlx4_wqe_ctrl_seg) + | |
263 | sizeof (struct mlx4_wqe_raddr_seg); | |
264 | case IB_QPT_RC: | |
265 | return sizeof (struct mlx4_wqe_ctrl_seg) + | |
266 | sizeof (struct mlx4_wqe_atomic_seg) + | |
267 | sizeof (struct mlx4_wqe_raddr_seg); | |
268 | case IB_QPT_SMI: | |
269 | case IB_QPT_GSI: | |
270 | return sizeof (struct mlx4_wqe_ctrl_seg) + | |
271 | ALIGN(MLX4_IB_UD_HEADER_SIZE + | |
e61ef241 RD |
272 | DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, |
273 | MLX4_INLINE_ALIGN) * | |
225c7b1f RD |
274 | sizeof (struct mlx4_wqe_inline_seg), |
275 | sizeof (struct mlx4_wqe_data_seg)) + | |
276 | ALIGN(4 + | |
277 | sizeof (struct mlx4_wqe_inline_seg), | |
278 | sizeof (struct mlx4_wqe_data_seg)); | |
279 | default: | |
280 | return sizeof (struct mlx4_wqe_ctrl_seg); | |
281 | } | |
282 | } | |
283 | ||
2446304d | 284 | static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, |
a4cd7ed8 | 285 | int is_user, int has_srq, struct mlx4_ib_qp *qp) |
225c7b1f | 286 | { |
2446304d EC |
287 | /* Sanity check RQ size before proceeding */ |
288 | if (cap->max_recv_wr > dev->dev->caps.max_wqes || | |
289 | cap->max_recv_sge > dev->dev->caps.max_rq_sg) | |
290 | return -EINVAL; | |
291 | ||
a4cd7ed8 RD |
292 | if (has_srq) { |
293 | /* QPs attached to an SRQ should have no RQ */ | |
294 | if (cap->max_recv_wr) | |
295 | return -EINVAL; | |
2446304d | 296 | |
0e6e7416 | 297 | qp->rq.wqe_cnt = qp->rq.max_gs = 0; |
a4cd7ed8 RD |
298 | } else { |
299 | /* HW requires >= 1 RQ entry with >= 1 gather entry */ | |
300 | if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) | |
301 | return -EINVAL; | |
302 | ||
0e6e7416 | 303 | qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); |
42c059ea | 304 | qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); |
a4cd7ed8 RD |
305 | qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg)); |
306 | } | |
2446304d | 307 | |
0e6e7416 | 308 | cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; |
2446304d EC |
309 | cap->max_recv_sge = qp->rq.max_gs; |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, | |
315 | enum ib_qp_type type, struct mlx4_ib_qp *qp) | |
316 | { | |
ea54b10c JM |
317 | int s; |
318 | ||
2446304d | 319 | /* Sanity check SQ size before proceeding */ |
225c7b1f | 320 | if (cap->max_send_wr > dev->dev->caps.max_wqes || |
225c7b1f | 321 | cap->max_send_sge > dev->dev->caps.max_sq_sg || |
b832be1e | 322 | cap->max_inline_data + send_wqe_overhead(type, qp->flags) + |
225c7b1f RD |
323 | sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) |
324 | return -EINVAL; | |
325 | ||
326 | /* | |
327 | * For MLX transport we need 2 extra S/G entries: | |
328 | * one for the header and one for the checksum at the end | |
329 | */ | |
330 | if ((type == IB_QPT_SMI || type == IB_QPT_GSI) && | |
331 | cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) | |
332 | return -EINVAL; | |
333 | ||
ea54b10c JM |
334 | s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), |
335 | cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + | |
b832be1e | 336 | send_wqe_overhead(type, qp->flags); |
225c7b1f | 337 | |
cd155c1c RD |
338 | if (s > dev->dev->caps.max_sq_desc_sz) |
339 | return -EINVAL; | |
340 | ||
0e6e7416 | 341 | /* |
ea54b10c JM |
342 | * Hermon supports shrinking WQEs, such that a single work |
343 | * request can include multiple units of 1 << wqe_shift. This | |
344 | * way, work requests can differ in size, and do not have to | |
345 | * be a power of 2 in size, saving memory and speeding up send | |
346 | * WR posting. Unfortunately, if we do this then the | |
347 | * wqe_index field in CQEs can't be used to look up the WR ID | |
348 | * anymore, so we do this only if selective signaling is off. | |
349 | * | |
350 | * Further, on 32-bit platforms, we can't use vmap() to make | |
351 | * the QP buffer virtually contigious. Thus we have to use | |
352 | * constant-sized WRs to make sure a WR is always fully within | |
353 | * a single page-sized chunk. | |
354 | * | |
355 | * Finally, we use NOP work requests to pad the end of the | |
356 | * work queue, to avoid wrap-around in the middle of WR. We | |
357 | * set NEC bit to avoid getting completions with error for | |
358 | * these NOP WRs, but since NEC is only supported starting | |
359 | * with firmware 2.2.232, we use constant-sized WRs for older | |
360 | * firmware. | |
361 | * | |
362 | * And, since MLX QPs only support SEND, we use constant-sized | |
363 | * WRs in this case. | |
364 | * | |
365 | * We look for the smallest value of wqe_shift such that the | |
366 | * resulting number of wqes does not exceed device | |
367 | * capabilities. | |
368 | * | |
369 | * We set WQE size to at least 64 bytes, this way stamping | |
370 | * invalidates each WQE. | |
0e6e7416 | 371 | */ |
ea54b10c JM |
372 | if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && |
373 | qp->sq_signal_bits && BITS_PER_LONG == 64 && | |
374 | type != IB_QPT_SMI && type != IB_QPT_GSI) | |
375 | qp->sq.wqe_shift = ilog2(64); | |
376 | else | |
377 | qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s)); | |
378 | ||
379 | for (;;) { | |
ea54b10c JM |
380 | qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); |
381 | ||
382 | /* | |
383 | * We need to leave 2 KB + 1 WR of headroom in the SQ to | |
384 | * allow HW to prefetch. | |
385 | */ | |
386 | qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; | |
387 | qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * | |
388 | qp->sq_max_wqes_per_wr + | |
389 | qp->sq_spare_wqes); | |
390 | ||
391 | if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) | |
392 | break; | |
393 | ||
394 | if (qp->sq_max_wqes_per_wr <= 1) | |
395 | return -EINVAL; | |
396 | ||
397 | ++qp->sq.wqe_shift; | |
398 | } | |
399 | ||
cd155c1c RD |
400 | qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, |
401 | (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - | |
b832be1e EC |
402 | send_wqe_overhead(type, qp->flags)) / |
403 | sizeof (struct mlx4_wqe_data_seg); | |
0e6e7416 RD |
404 | |
405 | qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + | |
406 | (qp->sq.wqe_cnt << qp->sq.wqe_shift); | |
225c7b1f RD |
407 | if (qp->rq.wqe_shift > qp->sq.wqe_shift) { |
408 | qp->rq.offset = 0; | |
0e6e7416 | 409 | qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; |
225c7b1f | 410 | } else { |
0e6e7416 | 411 | qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; |
225c7b1f RD |
412 | qp->sq.offset = 0; |
413 | } | |
414 | ||
ea54b10c JM |
415 | cap->max_send_wr = qp->sq.max_post = |
416 | (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; | |
cd155c1c RD |
417 | cap->max_send_sge = min(qp->sq.max_gs, |
418 | min(dev->dev->caps.max_sq_sg, | |
419 | dev->dev->caps.max_rq_sg)); | |
54e95f8d RD |
420 | /* We don't support inline sends for kernel QPs (yet) */ |
421 | cap->max_inline_data = 0; | |
225c7b1f RD |
422 | |
423 | return 0; | |
424 | } | |
425 | ||
83904132 JM |
426 | static int set_user_sq_size(struct mlx4_ib_dev *dev, |
427 | struct mlx4_ib_qp *qp, | |
2446304d EC |
428 | struct mlx4_ib_create_qp *ucmd) |
429 | { | |
83904132 JM |
430 | /* Sanity check SQ size before proceeding */ |
431 | if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || | |
432 | ucmd->log_sq_stride > | |
433 | ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || | |
434 | ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) | |
435 | return -EINVAL; | |
436 | ||
0e6e7416 | 437 | qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; |
2446304d EC |
438 | qp->sq.wqe_shift = ucmd->log_sq_stride; |
439 | ||
0e6e7416 RD |
440 | qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + |
441 | (qp->sq.wqe_cnt << qp->sq.wqe_shift); | |
2446304d EC |
442 | |
443 | return 0; | |
444 | } | |
445 | ||
225c7b1f RD |
446 | static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, |
447 | struct ib_qp_init_attr *init_attr, | |
448 | struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp) | |
449 | { | |
225c7b1f | 450 | int err; |
225c7b1f RD |
451 | |
452 | mutex_init(&qp->mutex); | |
453 | spin_lock_init(&qp->sq.lock); | |
454 | spin_lock_init(&qp->rq.lock); | |
455 | ||
456 | qp->state = IB_QPS_RESET; | |
ea54b10c JM |
457 | if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) |
458 | qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); | |
225c7b1f | 459 | |
a4cd7ed8 | 460 | err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp); |
225c7b1f RD |
461 | if (err) |
462 | goto err; | |
463 | ||
464 | if (pd->uobject) { | |
465 | struct mlx4_ib_create_qp ucmd; | |
466 | ||
467 | if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { | |
468 | err = -EFAULT; | |
469 | goto err; | |
470 | } | |
471 | ||
0e6e7416 RD |
472 | qp->sq_no_prefetch = ucmd.sq_no_prefetch; |
473 | ||
83904132 | 474 | err = set_user_sq_size(dev, qp, &ucmd); |
2446304d EC |
475 | if (err) |
476 | goto err; | |
477 | ||
225c7b1f | 478 | qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, |
cb9fbc5c | 479 | qp->buf_size, 0, 0); |
225c7b1f RD |
480 | if (IS_ERR(qp->umem)) { |
481 | err = PTR_ERR(qp->umem); | |
482 | goto err; | |
483 | } | |
484 | ||
485 | err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem), | |
486 | ilog2(qp->umem->page_size), &qp->mtt); | |
487 | if (err) | |
488 | goto err_buf; | |
489 | ||
490 | err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); | |
491 | if (err) | |
492 | goto err_mtt; | |
493 | ||
02d89b87 RD |
494 | if (!init_attr->srq) { |
495 | err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), | |
496 | ucmd.db_addr, &qp->db); | |
497 | if (err) | |
498 | goto err_mtt; | |
499 | } | |
225c7b1f | 500 | } else { |
0e6e7416 RD |
501 | qp->sq_no_prefetch = 0; |
502 | ||
521e575b RL |
503 | if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) |
504 | qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; | |
505 | ||
b832be1e EC |
506 | if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) |
507 | qp->flags |= MLX4_IB_QP_LSO; | |
508 | ||
2446304d EC |
509 | err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp); |
510 | if (err) | |
511 | goto err; | |
512 | ||
02d89b87 | 513 | if (!init_attr->srq) { |
6296883c | 514 | err = mlx4_db_alloc(dev->dev, &qp->db, 0); |
02d89b87 RD |
515 | if (err) |
516 | goto err; | |
225c7b1f | 517 | |
02d89b87 RD |
518 | *qp->db.db = 0; |
519 | } | |
225c7b1f RD |
520 | |
521 | if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) { | |
522 | err = -ENOMEM; | |
523 | goto err_db; | |
524 | } | |
525 | ||
526 | err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, | |
527 | &qp->mtt); | |
528 | if (err) | |
529 | goto err_buf; | |
530 | ||
531 | err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf); | |
532 | if (err) | |
533 | goto err_mtt; | |
534 | ||
0e6e7416 RD |
535 | qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL); |
536 | qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL); | |
225c7b1f RD |
537 | |
538 | if (!qp->sq.wrid || !qp->rq.wrid) { | |
539 | err = -ENOMEM; | |
540 | goto err_wrid; | |
541 | } | |
225c7b1f RD |
542 | } |
543 | ||
544 | err = mlx4_qp_alloc(dev->dev, sqpn, &qp->mqp); | |
545 | if (err) | |
546 | goto err_wrid; | |
547 | ||
548 | /* | |
549 | * Hardware wants QPN written in big-endian order (after | |
550 | * shifting) for send doorbell. Precompute this value to save | |
551 | * a little bit when posting sends. | |
552 | */ | |
553 | qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); | |
554 | ||
225c7b1f RD |
555 | qp->mqp.event = mlx4_ib_qp_event; |
556 | ||
557 | return 0; | |
558 | ||
559 | err_wrid: | |
23f1b384 RD |
560 | if (pd->uobject) { |
561 | if (!init_attr->srq) | |
562 | mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), | |
563 | &qp->db); | |
564 | } else { | |
225c7b1f RD |
565 | kfree(qp->sq.wrid); |
566 | kfree(qp->rq.wrid); | |
567 | } | |
568 | ||
569 | err_mtt: | |
570 | mlx4_mtt_cleanup(dev->dev, &qp->mtt); | |
571 | ||
572 | err_buf: | |
573 | if (pd->uobject) | |
574 | ib_umem_release(qp->umem); | |
575 | else | |
576 | mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); | |
577 | ||
578 | err_db: | |
02d89b87 | 579 | if (!pd->uobject && !init_attr->srq) |
6296883c | 580 | mlx4_db_free(dev->dev, &qp->db); |
225c7b1f RD |
581 | |
582 | err: | |
583 | return err; | |
584 | } | |
585 | ||
586 | static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) | |
587 | { | |
588 | switch (state) { | |
589 | case IB_QPS_RESET: return MLX4_QP_STATE_RST; | |
590 | case IB_QPS_INIT: return MLX4_QP_STATE_INIT; | |
591 | case IB_QPS_RTR: return MLX4_QP_STATE_RTR; | |
592 | case IB_QPS_RTS: return MLX4_QP_STATE_RTS; | |
593 | case IB_QPS_SQD: return MLX4_QP_STATE_SQD; | |
594 | case IB_QPS_SQE: return MLX4_QP_STATE_SQER; | |
595 | case IB_QPS_ERR: return MLX4_QP_STATE_ERR; | |
596 | default: return -1; | |
597 | } | |
598 | } | |
599 | ||
600 | static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) | |
601 | { | |
602 | if (send_cq == recv_cq) | |
603 | spin_lock_irq(&send_cq->lock); | |
604 | else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
605 | spin_lock_irq(&send_cq->lock); | |
606 | spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); | |
607 | } else { | |
608 | spin_lock_irq(&recv_cq->lock); | |
609 | spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); | |
610 | } | |
611 | } | |
612 | ||
613 | static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) | |
614 | { | |
615 | if (send_cq == recv_cq) | |
616 | spin_unlock_irq(&send_cq->lock); | |
617 | else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
618 | spin_unlock(&recv_cq->lock); | |
619 | spin_unlock_irq(&send_cq->lock); | |
620 | } else { | |
621 | spin_unlock(&send_cq->lock); | |
622 | spin_unlock_irq(&recv_cq->lock); | |
623 | } | |
624 | } | |
625 | ||
626 | static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, | |
627 | int is_user) | |
628 | { | |
629 | struct mlx4_ib_cq *send_cq, *recv_cq; | |
630 | ||
631 | if (qp->state != IB_QPS_RESET) | |
632 | if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), | |
633 | MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) | |
634 | printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n", | |
635 | qp->mqp.qpn); | |
636 | ||
637 | send_cq = to_mcq(qp->ibqp.send_cq); | |
638 | recv_cq = to_mcq(qp->ibqp.recv_cq); | |
639 | ||
640 | mlx4_ib_lock_cqs(send_cq, recv_cq); | |
641 | ||
642 | if (!is_user) { | |
643 | __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, | |
644 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); | |
645 | if (send_cq != recv_cq) | |
646 | __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); | |
647 | } | |
648 | ||
649 | mlx4_qp_remove(dev->dev, &qp->mqp); | |
650 | ||
651 | mlx4_ib_unlock_cqs(send_cq, recv_cq); | |
652 | ||
653 | mlx4_qp_free(dev->dev, &qp->mqp); | |
654 | mlx4_mtt_cleanup(dev->dev, &qp->mtt); | |
655 | ||
656 | if (is_user) { | |
02d89b87 RD |
657 | if (!qp->ibqp.srq) |
658 | mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context), | |
659 | &qp->db); | |
225c7b1f RD |
660 | ib_umem_release(qp->umem); |
661 | } else { | |
662 | kfree(qp->sq.wrid); | |
663 | kfree(qp->rq.wrid); | |
664 | mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); | |
02d89b87 | 665 | if (!qp->ibqp.srq) |
6296883c | 666 | mlx4_db_free(dev->dev, &qp->db); |
225c7b1f RD |
667 | } |
668 | } | |
669 | ||
670 | struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, | |
671 | struct ib_qp_init_attr *init_attr, | |
672 | struct ib_udata *udata) | |
673 | { | |
674 | struct mlx4_ib_dev *dev = to_mdev(pd->device); | |
675 | struct mlx4_ib_sqp *sqp; | |
676 | struct mlx4_ib_qp *qp; | |
677 | int err; | |
678 | ||
521e575b RL |
679 | /* |
680 | * We only support LSO and multicast loopback blocking, and | |
681 | * only for kernel UD QPs. | |
682 | */ | |
683 | if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO | | |
684 | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)) | |
b832be1e | 685 | return ERR_PTR(-EINVAL); |
521e575b RL |
686 | |
687 | if (init_attr->create_flags && | |
b832be1e | 688 | (pd->uobject || init_attr->qp_type != IB_QPT_UD)) |
b846f25a EC |
689 | return ERR_PTR(-EINVAL); |
690 | ||
225c7b1f RD |
691 | switch (init_attr->qp_type) { |
692 | case IB_QPT_RC: | |
693 | case IB_QPT_UC: | |
694 | case IB_QPT_UD: | |
695 | { | |
f507d28b | 696 | qp = kzalloc(sizeof *qp, GFP_KERNEL); |
225c7b1f RD |
697 | if (!qp) |
698 | return ERR_PTR(-ENOMEM); | |
699 | ||
700 | err = create_qp_common(dev, pd, init_attr, udata, 0, qp); | |
701 | if (err) { | |
702 | kfree(qp); | |
703 | return ERR_PTR(err); | |
704 | } | |
705 | ||
706 | qp->ibqp.qp_num = qp->mqp.qpn; | |
707 | ||
708 | break; | |
709 | } | |
710 | case IB_QPT_SMI: | |
711 | case IB_QPT_GSI: | |
712 | { | |
713 | /* Userspace is not allowed to create special QPs: */ | |
714 | if (pd->uobject) | |
715 | return ERR_PTR(-EINVAL); | |
716 | ||
f507d28b | 717 | sqp = kzalloc(sizeof *sqp, GFP_KERNEL); |
225c7b1f RD |
718 | if (!sqp) |
719 | return ERR_PTR(-ENOMEM); | |
720 | ||
721 | qp = &sqp->qp; | |
722 | ||
723 | err = create_qp_common(dev, pd, init_attr, udata, | |
724 | dev->dev->caps.sqp_start + | |
725 | (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) + | |
726 | init_attr->port_num - 1, | |
727 | qp); | |
728 | if (err) { | |
729 | kfree(sqp); | |
730 | return ERR_PTR(err); | |
731 | } | |
732 | ||
733 | qp->port = init_attr->port_num; | |
734 | qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1; | |
735 | ||
736 | break; | |
737 | } | |
738 | default: | |
739 | /* Don't support raw QPs */ | |
740 | return ERR_PTR(-EINVAL); | |
741 | } | |
742 | ||
743 | return &qp->ibqp; | |
744 | } | |
745 | ||
746 | int mlx4_ib_destroy_qp(struct ib_qp *qp) | |
747 | { | |
748 | struct mlx4_ib_dev *dev = to_mdev(qp->device); | |
749 | struct mlx4_ib_qp *mqp = to_mqp(qp); | |
750 | ||
751 | if (is_qp0(dev, mqp)) | |
752 | mlx4_CLOSE_PORT(dev->dev, mqp->port); | |
753 | ||
754 | destroy_qp_common(dev, mqp, !!qp->pd->uobject); | |
755 | ||
756 | if (is_sqp(dev, mqp)) | |
757 | kfree(to_msqp(mqp)); | |
758 | else | |
759 | kfree(mqp); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
225c7b1f RD |
764 | static int to_mlx4_st(enum ib_qp_type type) |
765 | { | |
766 | switch (type) { | |
767 | case IB_QPT_RC: return MLX4_QP_ST_RC; | |
768 | case IB_QPT_UC: return MLX4_QP_ST_UC; | |
769 | case IB_QPT_UD: return MLX4_QP_ST_UD; | |
770 | case IB_QPT_SMI: | |
771 | case IB_QPT_GSI: return MLX4_QP_ST_MLX; | |
772 | default: return -1; | |
773 | } | |
774 | } | |
775 | ||
65adfa91 | 776 | static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, |
225c7b1f RD |
777 | int attr_mask) |
778 | { | |
779 | u8 dest_rd_atomic; | |
780 | u32 access_flags; | |
781 | u32 hw_access_flags = 0; | |
782 | ||
783 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) | |
784 | dest_rd_atomic = attr->max_dest_rd_atomic; | |
785 | else | |
786 | dest_rd_atomic = qp->resp_depth; | |
787 | ||
788 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
789 | access_flags = attr->qp_access_flags; | |
790 | else | |
791 | access_flags = qp->atomic_rd_en; | |
792 | ||
793 | if (!dest_rd_atomic) | |
794 | access_flags &= IB_ACCESS_REMOTE_WRITE; | |
795 | ||
796 | if (access_flags & IB_ACCESS_REMOTE_READ) | |
797 | hw_access_flags |= MLX4_QP_BIT_RRE; | |
798 | if (access_flags & IB_ACCESS_REMOTE_ATOMIC) | |
799 | hw_access_flags |= MLX4_QP_BIT_RAE; | |
800 | if (access_flags & IB_ACCESS_REMOTE_WRITE) | |
801 | hw_access_flags |= MLX4_QP_BIT_RWE; | |
802 | ||
803 | return cpu_to_be32(hw_access_flags); | |
804 | } | |
805 | ||
65adfa91 | 806 | static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, |
225c7b1f RD |
807 | int attr_mask) |
808 | { | |
809 | if (attr_mask & IB_QP_PKEY_INDEX) | |
810 | sqp->pkey_index = attr->pkey_index; | |
811 | if (attr_mask & IB_QP_QKEY) | |
812 | sqp->qkey = attr->qkey; | |
813 | if (attr_mask & IB_QP_SQ_PSN) | |
814 | sqp->send_psn = attr->sq_psn; | |
815 | } | |
816 | ||
817 | static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) | |
818 | { | |
819 | path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); | |
820 | } | |
821 | ||
65adfa91 | 822 | static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah, |
225c7b1f RD |
823 | struct mlx4_qp_path *path, u8 port) |
824 | { | |
825 | path->grh_mylmc = ah->src_path_bits & 0x7f; | |
826 | path->rlid = cpu_to_be16(ah->dlid); | |
827 | if (ah->static_rate) { | |
828 | path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET; | |
829 | while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && | |
830 | !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) | |
831 | --path->static_rate; | |
832 | } else | |
833 | path->static_rate = 0; | |
834 | path->counter_index = 0xff; | |
835 | ||
836 | if (ah->ah_flags & IB_AH_GRH) { | |
5ae2a7a8 | 837 | if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) { |
225c7b1f | 838 | printk(KERN_ERR "sgid_index (%u) too large. max is %d\n", |
5ae2a7a8 | 839 | ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1); |
225c7b1f RD |
840 | return -1; |
841 | } | |
842 | ||
843 | path->grh_mylmc |= 1 << 7; | |
844 | path->mgid_index = ah->grh.sgid_index; | |
845 | path->hop_limit = ah->grh.hop_limit; | |
846 | path->tclass_flowlabel = | |
847 | cpu_to_be32((ah->grh.traffic_class << 20) | | |
848 | (ah->grh.flow_label)); | |
849 | memcpy(path->rgid, ah->grh.dgid.raw, 16); | |
850 | } | |
851 | ||
852 | path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | | |
853 | ((port - 1) << 6) | ((ah->sl & 0xf) << 2); | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
65adfa91 MT |
858 | static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, |
859 | const struct ib_qp_attr *attr, int attr_mask, | |
860 | enum ib_qp_state cur_state, enum ib_qp_state new_state) | |
225c7b1f RD |
861 | { |
862 | struct mlx4_ib_dev *dev = to_mdev(ibqp->device); | |
863 | struct mlx4_ib_qp *qp = to_mqp(ibqp); | |
864 | struct mlx4_qp_context *context; | |
865 | enum mlx4_qp_optpar optpar = 0; | |
225c7b1f RD |
866 | int sqd_event; |
867 | int err = -EINVAL; | |
868 | ||
869 | context = kzalloc(sizeof *context, GFP_KERNEL); | |
870 | if (!context) | |
871 | return -ENOMEM; | |
872 | ||
225c7b1f RD |
873 | context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | |
874 | (to_mlx4_st(ibqp->qp_type) << 16)); | |
875 | context->flags |= cpu_to_be32(1 << 8); /* DE? */ | |
876 | ||
877 | if (!(attr_mask & IB_QP_PATH_MIG_STATE)) | |
878 | context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); | |
879 | else { | |
880 | optpar |= MLX4_QP_OPTPAR_PM_STATE; | |
881 | switch (attr->path_mig_state) { | |
882 | case IB_MIG_MIGRATED: | |
883 | context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); | |
884 | break; | |
885 | case IB_MIG_REARM: | |
886 | context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); | |
887 | break; | |
888 | case IB_MIG_ARMED: | |
889 | context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); | |
890 | break; | |
891 | } | |
892 | } | |
893 | ||
b832be1e | 894 | if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) |
225c7b1f | 895 | context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; |
b832be1e EC |
896 | else if (ibqp->qp_type == IB_QPT_UD) { |
897 | if (qp->flags & MLX4_IB_QP_LSO) | |
898 | context->mtu_msgmax = (IB_MTU_4096 << 5) | | |
899 | ilog2(dev->dev->caps.max_gso_sz); | |
900 | else | |
901 | context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; | |
902 | } else if (attr_mask & IB_QP_PATH_MTU) { | |
225c7b1f RD |
903 | if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { |
904 | printk(KERN_ERR "path MTU (%u) is invalid\n", | |
905 | attr->path_mtu); | |
f5b40431 | 906 | goto out; |
225c7b1f | 907 | } |
d1f2cd89 EC |
908 | context->mtu_msgmax = (attr->path_mtu << 5) | |
909 | ilog2(dev->dev->caps.max_msg_sz); | |
225c7b1f RD |
910 | } |
911 | ||
0e6e7416 RD |
912 | if (qp->rq.wqe_cnt) |
913 | context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; | |
225c7b1f RD |
914 | context->rq_size_stride |= qp->rq.wqe_shift - 4; |
915 | ||
0e6e7416 RD |
916 | if (qp->sq.wqe_cnt) |
917 | context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; | |
225c7b1f RD |
918 | context->sq_size_stride |= qp->sq.wqe_shift - 4; |
919 | ||
0e6e7416 RD |
920 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) |
921 | context->sq_size_stride |= !!qp->sq_no_prefetch << 7; | |
922 | ||
225c7b1f RD |
923 | if (qp->ibqp.uobject) |
924 | context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index); | |
925 | else | |
926 | context->usr_page = cpu_to_be32(dev->priv_uar.index); | |
927 | ||
928 | if (attr_mask & IB_QP_DEST_QPN) | |
929 | context->remote_qpn = cpu_to_be32(attr->dest_qp_num); | |
930 | ||
931 | if (attr_mask & IB_QP_PORT) { | |
932 | if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && | |
933 | !(attr_mask & IB_QP_AV)) { | |
934 | mlx4_set_sched(&context->pri_path, attr->port_num); | |
935 | optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; | |
936 | } | |
937 | } | |
938 | ||
939 | if (attr_mask & IB_QP_PKEY_INDEX) { | |
940 | context->pri_path.pkey_index = attr->pkey_index; | |
941 | optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; | |
942 | } | |
943 | ||
225c7b1f RD |
944 | if (attr_mask & IB_QP_AV) { |
945 | if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path, | |
f5b40431 | 946 | attr_mask & IB_QP_PORT ? attr->port_num : qp->port)) |
225c7b1f | 947 | goto out; |
225c7b1f RD |
948 | |
949 | optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | | |
950 | MLX4_QP_OPTPAR_SCHED_QUEUE); | |
951 | } | |
952 | ||
953 | if (attr_mask & IB_QP_TIMEOUT) { | |
954 | context->pri_path.ackto = attr->timeout << 3; | |
955 | optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; | |
956 | } | |
957 | ||
958 | if (attr_mask & IB_QP_ALT_PATH) { | |
225c7b1f RD |
959 | if (attr->alt_port_num == 0 || |
960 | attr->alt_port_num > dev->dev->caps.num_ports) | |
f5b40431 | 961 | goto out; |
225c7b1f | 962 | |
5ae2a7a8 RD |
963 | if (attr->alt_pkey_index >= |
964 | dev->dev->caps.pkey_table_len[attr->alt_port_num]) | |
f5b40431 | 965 | goto out; |
5ae2a7a8 | 966 | |
225c7b1f RD |
967 | if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path, |
968 | attr->alt_port_num)) | |
f5b40431 | 969 | goto out; |
225c7b1f RD |
970 | |
971 | context->alt_path.pkey_index = attr->alt_pkey_index; | |
972 | context->alt_path.ackto = attr->alt_timeout << 3; | |
973 | optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; | |
974 | } | |
975 | ||
976 | context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn); | |
977 | context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); | |
57f01b53 JM |
978 | |
979 | if (attr_mask & IB_QP_RNR_RETRY) { | |
980 | context->params1 |= cpu_to_be32(attr->rnr_retry << 13); | |
981 | optpar |= MLX4_QP_OPTPAR_RNR_RETRY; | |
982 | } | |
983 | ||
225c7b1f RD |
984 | if (attr_mask & IB_QP_RETRY_CNT) { |
985 | context->params1 |= cpu_to_be32(attr->retry_cnt << 16); | |
986 | optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; | |
987 | } | |
988 | ||
989 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { | |
990 | if (attr->max_rd_atomic) | |
991 | context->params1 |= | |
992 | cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); | |
993 | optpar |= MLX4_QP_OPTPAR_SRA_MAX; | |
994 | } | |
995 | ||
996 | if (attr_mask & IB_QP_SQ_PSN) | |
997 | context->next_send_psn = cpu_to_be32(attr->sq_psn); | |
998 | ||
999 | context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn); | |
1000 | ||
1001 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { | |
1002 | if (attr->max_dest_rd_atomic) | |
1003 | context->params2 |= | |
1004 | cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); | |
1005 | optpar |= MLX4_QP_OPTPAR_RRA_MAX; | |
1006 | } | |
1007 | ||
1008 | if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { | |
1009 | context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); | |
1010 | optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; | |
1011 | } | |
1012 | ||
1013 | if (ibqp->srq) | |
1014 | context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); | |
1015 | ||
1016 | if (attr_mask & IB_QP_MIN_RNR_TIMER) { | |
1017 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); | |
1018 | optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; | |
1019 | } | |
1020 | if (attr_mask & IB_QP_RQ_PSN) | |
1021 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); | |
1022 | ||
1023 | context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn); | |
1024 | ||
1025 | if (attr_mask & IB_QP_QKEY) { | |
1026 | context->qkey = cpu_to_be32(attr->qkey); | |
1027 | optpar |= MLX4_QP_OPTPAR_Q_KEY; | |
1028 | } | |
1029 | ||
1030 | if (ibqp->srq) | |
1031 | context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn); | |
1032 | ||
02d89b87 | 1033 | if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) |
225c7b1f RD |
1034 | context->db_rec_addr = cpu_to_be64(qp->db.dma); |
1035 | ||
1036 | if (cur_state == IB_QPS_INIT && | |
1037 | new_state == IB_QPS_RTR && | |
1038 | (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI || | |
1039 | ibqp->qp_type == IB_QPT_UD)) { | |
1040 | context->pri_path.sched_queue = (qp->port - 1) << 6; | |
1041 | if (is_qp0(dev, qp)) | |
1042 | context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; | |
1043 | else | |
1044 | context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; | |
1045 | } | |
1046 | ||
1047 | if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && | |
1048 | attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) | |
1049 | sqd_event = 1; | |
1050 | else | |
1051 | sqd_event = 0; | |
1052 | ||
c0be5fb5 EC |
1053 | /* |
1054 | * Before passing a kernel QP to the HW, make sure that the | |
0e6e7416 RD |
1055 | * ownership bits of the send queue are set and the SQ |
1056 | * headroom is stamped so that the hardware doesn't start | |
1057 | * processing stale work requests. | |
c0be5fb5 EC |
1058 | */ |
1059 | if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { | |
1060 | struct mlx4_wqe_ctrl_seg *ctrl; | |
1061 | int i; | |
1062 | ||
0e6e7416 | 1063 | for (i = 0; i < qp->sq.wqe_cnt; ++i) { |
c0be5fb5 EC |
1064 | ctrl = get_send_wqe(qp, i); |
1065 | ctrl->owner_opcode = cpu_to_be32(1 << 31); | |
9670e553 EC |
1066 | if (qp->sq_max_wqes_per_wr == 1) |
1067 | ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4); | |
0e6e7416 | 1068 | |
ea54b10c | 1069 | stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); |
c0be5fb5 EC |
1070 | } |
1071 | } | |
1072 | ||
225c7b1f RD |
1073 | err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), |
1074 | to_mlx4_state(new_state), context, optpar, | |
1075 | sqd_event, &qp->mqp); | |
1076 | if (err) | |
1077 | goto out; | |
1078 | ||
1079 | qp->state = new_state; | |
1080 | ||
1081 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
1082 | qp->atomic_rd_en = attr->qp_access_flags; | |
1083 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) | |
1084 | qp->resp_depth = attr->max_dest_rd_atomic; | |
1085 | if (attr_mask & IB_QP_PORT) | |
1086 | qp->port = attr->port_num; | |
1087 | if (attr_mask & IB_QP_ALT_PATH) | |
1088 | qp->alt_port = attr->alt_port_num; | |
1089 | ||
1090 | if (is_sqp(dev, qp)) | |
1091 | store_sqp_attrs(to_msqp(qp), attr, attr_mask); | |
1092 | ||
1093 | /* | |
1094 | * If we moved QP0 to RTR, bring the IB link up; if we moved | |
1095 | * QP0 to RESET or ERROR, bring the link back down. | |
1096 | */ | |
1097 | if (is_qp0(dev, qp)) { | |
1098 | if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) | |
5ae2a7a8 RD |
1099 | if (mlx4_INIT_PORT(dev->dev, qp->port)) |
1100 | printk(KERN_WARNING "INIT_PORT failed for port %d\n", | |
1101 | qp->port); | |
225c7b1f RD |
1102 | |
1103 | if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && | |
1104 | (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) | |
1105 | mlx4_CLOSE_PORT(dev->dev, qp->port); | |
1106 | } | |
1107 | ||
1108 | /* | |
1109 | * If we moved a kernel QP to RESET, clean up all old CQ | |
1110 | * entries and reinitialize the QP. | |
1111 | */ | |
1112 | if (new_state == IB_QPS_RESET && !ibqp->uobject) { | |
1113 | mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn, | |
1114 | ibqp->srq ? to_msrq(ibqp->srq): NULL); | |
1115 | if (ibqp->send_cq != ibqp->recv_cq) | |
1116 | mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL); | |
1117 | ||
1118 | qp->rq.head = 0; | |
1119 | qp->rq.tail = 0; | |
1120 | qp->sq.head = 0; | |
1121 | qp->sq.tail = 0; | |
ea54b10c | 1122 | qp->sq_next_wqe = 0; |
02d89b87 RD |
1123 | if (!ibqp->srq) |
1124 | *qp->db.db = 0; | |
225c7b1f RD |
1125 | } |
1126 | ||
1127 | out: | |
225c7b1f RD |
1128 | kfree(context); |
1129 | return err; | |
1130 | } | |
1131 | ||
65adfa91 MT |
1132 | int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
1133 | int attr_mask, struct ib_udata *udata) | |
1134 | { | |
1135 | struct mlx4_ib_dev *dev = to_mdev(ibqp->device); | |
1136 | struct mlx4_ib_qp *qp = to_mqp(ibqp); | |
1137 | enum ib_qp_state cur_state, new_state; | |
1138 | int err = -EINVAL; | |
1139 | ||
1140 | mutex_lock(&qp->mutex); | |
1141 | ||
1142 | cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; | |
1143 | new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; | |
1144 | ||
1145 | if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) | |
1146 | goto out; | |
1147 | ||
65adfa91 MT |
1148 | if ((attr_mask & IB_QP_PORT) && |
1149 | (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) { | |
1150 | goto out; | |
1151 | } | |
1152 | ||
5ae2a7a8 RD |
1153 | if (attr_mask & IB_QP_PKEY_INDEX) { |
1154 | int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; | |
1155 | if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) | |
1156 | goto out; | |
1157 | } | |
1158 | ||
65adfa91 MT |
1159 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && |
1160 | attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { | |
1161 | goto out; | |
1162 | } | |
1163 | ||
1164 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && | |
1165 | attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { | |
1166 | goto out; | |
1167 | } | |
1168 | ||
1169 | if (cur_state == new_state && cur_state == IB_QPS_RESET) { | |
1170 | err = 0; | |
1171 | goto out; | |
1172 | } | |
1173 | ||
65adfa91 MT |
1174 | err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); |
1175 | ||
1176 | out: | |
1177 | mutex_unlock(&qp->mutex); | |
1178 | return err; | |
1179 | } | |
1180 | ||
225c7b1f | 1181 | static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr, |
f438000f | 1182 | void *wqe, unsigned *mlx_seg_len) |
225c7b1f RD |
1183 | { |
1184 | struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev; | |
1185 | struct mlx4_wqe_mlx_seg *mlx = wqe; | |
1186 | struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; | |
1187 | struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah); | |
1188 | u16 pkey; | |
1189 | int send_size; | |
1190 | int header_size; | |
e61ef241 | 1191 | int spc; |
225c7b1f RD |
1192 | int i; |
1193 | ||
1194 | send_size = 0; | |
1195 | for (i = 0; i < wr->num_sge; ++i) | |
1196 | send_size += wr->sg_list[i].length; | |
1197 | ||
1198 | ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header); | |
1199 | ||
1200 | sqp->ud_header.lrh.service_level = | |
1201 | be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28; | |
1202 | sqp->ud_header.lrh.destination_lid = ah->av.dlid; | |
1203 | sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f); | |
1204 | if (mlx4_ib_ah_grh_present(ah)) { | |
1205 | sqp->ud_header.grh.traffic_class = | |
1206 | (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff; | |
1207 | sqp->ud_header.grh.flow_label = | |
1208 | ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff); | |
15261303 | 1209 | sqp->ud_header.grh.hop_limit = ah->av.hop_limit; |
225c7b1f RD |
1210 | ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24, |
1211 | ah->av.gid_index, &sqp->ud_header.grh.source_gid); | |
1212 | memcpy(sqp->ud_header.grh.destination_gid.raw, | |
1213 | ah->av.dgid, 16); | |
1214 | } | |
1215 | ||
1216 | mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); | |
1217 | mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | | |
1218 | (sqp->ud_header.lrh.destination_lid == | |
1219 | IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | | |
1220 | (sqp->ud_header.lrh.service_level << 8)); | |
1221 | mlx->rlid = sqp->ud_header.lrh.destination_lid; | |
1222 | ||
1223 | switch (wr->opcode) { | |
1224 | case IB_WR_SEND: | |
1225 | sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; | |
1226 | sqp->ud_header.immediate_present = 0; | |
1227 | break; | |
1228 | case IB_WR_SEND_WITH_IMM: | |
1229 | sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; | |
1230 | sqp->ud_header.immediate_present = 1; | |
0f39cf3d | 1231 | sqp->ud_header.immediate_data = wr->ex.imm_data; |
225c7b1f RD |
1232 | break; |
1233 | default: | |
1234 | return -EINVAL; | |
1235 | } | |
1236 | ||
1237 | sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0; | |
1238 | if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) | |
1239 | sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; | |
1240 | sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED); | |
1241 | if (!sqp->qp.ibqp.qp_num) | |
1242 | ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); | |
1243 | else | |
1244 | ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey); | |
1245 | sqp->ud_header.bth.pkey = cpu_to_be16(pkey); | |
1246 | sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn); | |
1247 | sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); | |
1248 | sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ? | |
1249 | sqp->qkey : wr->wr.ud.remote_qkey); | |
1250 | sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); | |
1251 | ||
1252 | header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); | |
1253 | ||
1254 | if (0) { | |
1255 | printk(KERN_ERR "built UD header of size %d:\n", header_size); | |
1256 | for (i = 0; i < header_size / 4; ++i) { | |
1257 | if (i % 8 == 0) | |
1258 | printk(" [%02x] ", i * 4); | |
1259 | printk(" %08x", | |
1260 | be32_to_cpu(((__be32 *) sqp->header_buf)[i])); | |
1261 | if ((i + 1) % 8 == 0) | |
1262 | printk("\n"); | |
1263 | } | |
1264 | printk("\n"); | |
1265 | } | |
1266 | ||
e61ef241 RD |
1267 | /* |
1268 | * Inline data segments may not cross a 64 byte boundary. If | |
1269 | * our UD header is bigger than the space available up to the | |
1270 | * next 64 byte boundary in the WQE, use two inline data | |
1271 | * segments to hold the UD header. | |
1272 | */ | |
1273 | spc = MLX4_INLINE_ALIGN - | |
1274 | ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); | |
1275 | if (header_size <= spc) { | |
1276 | inl->byte_count = cpu_to_be32(1 << 31 | header_size); | |
1277 | memcpy(inl + 1, sqp->header_buf, header_size); | |
1278 | i = 1; | |
1279 | } else { | |
1280 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
1281 | memcpy(inl + 1, sqp->header_buf, spc); | |
1282 | ||
1283 | inl = (void *) (inl + 1) + spc; | |
1284 | memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); | |
1285 | /* | |
1286 | * Need a barrier here to make sure all the data is | |
1287 | * visible before the byte_count field is set. | |
1288 | * Otherwise the HCA prefetcher could grab the 64-byte | |
1289 | * chunk with this inline segment and get a valid (!= | |
1290 | * 0xffffffff) byte count but stale data, and end up | |
1291 | * generating a packet with bad headers. | |
1292 | * | |
1293 | * The first inline segment's byte_count field doesn't | |
1294 | * need a barrier, because it comes after a | |
1295 | * control/MLX segment and therefore is at an offset | |
1296 | * of 16 mod 64. | |
1297 | */ | |
1298 | wmb(); | |
1299 | inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc)); | |
1300 | i = 2; | |
1301 | } | |
225c7b1f | 1302 | |
f438000f RD |
1303 | *mlx_seg_len = |
1304 | ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); | |
1305 | return 0; | |
225c7b1f RD |
1306 | } |
1307 | ||
1308 | static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) | |
1309 | { | |
1310 | unsigned cur; | |
1311 | struct mlx4_ib_cq *cq; | |
1312 | ||
1313 | cur = wq->head - wq->tail; | |
0e6e7416 | 1314 | if (likely(cur + nreq < wq->max_post)) |
225c7b1f RD |
1315 | return 0; |
1316 | ||
1317 | cq = to_mcq(ib_cq); | |
1318 | spin_lock(&cq->lock); | |
1319 | cur = wq->head - wq->tail; | |
1320 | spin_unlock(&cq->lock); | |
1321 | ||
0e6e7416 | 1322 | return cur + nreq >= wq->max_post; |
225c7b1f RD |
1323 | } |
1324 | ||
0fbfa6a9 RD |
1325 | static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, |
1326 | u64 remote_addr, u32 rkey) | |
1327 | { | |
1328 | rseg->raddr = cpu_to_be64(remote_addr); | |
1329 | rseg->rkey = cpu_to_be32(rkey); | |
1330 | rseg->reserved = 0; | |
1331 | } | |
1332 | ||
1333 | static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr) | |
1334 | { | |
1335 | if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { | |
1336 | aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap); | |
1337 | aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add); | |
1338 | } else { | |
1339 | aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add); | |
1340 | aseg->compare = 0; | |
1341 | } | |
1342 | ||
1343 | } | |
1344 | ||
1345 | static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, | |
1346 | struct ib_send_wr *wr) | |
1347 | { | |
1348 | memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av)); | |
1349 | dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn); | |
1350 | dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey); | |
0fbfa6a9 RD |
1351 | } |
1352 | ||
6e694ea3 JM |
1353 | static void set_mlx_icrc_seg(void *dseg) |
1354 | { | |
1355 | u32 *t = dseg; | |
1356 | struct mlx4_wqe_inline_seg *iseg = dseg; | |
1357 | ||
1358 | t[1] = 0; | |
1359 | ||
1360 | /* | |
1361 | * Need a barrier here before writing the byte_count field to | |
1362 | * make sure that all the data is visible before the | |
1363 | * byte_count field is set. Otherwise, if the segment begins | |
1364 | * a new cacheline, the HCA prefetcher could grab the 64-byte | |
1365 | * chunk and get a valid (!= * 0xffffffff) byte count but | |
1366 | * stale data, and end up sending the wrong data. | |
1367 | */ | |
1368 | wmb(); | |
1369 | ||
1370 | iseg->byte_count = cpu_to_be32((1 << 31) | 4); | |
1371 | } | |
1372 | ||
1373 | static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) | |
d420d9e3 | 1374 | { |
d420d9e3 RD |
1375 | dseg->lkey = cpu_to_be32(sg->lkey); |
1376 | dseg->addr = cpu_to_be64(sg->addr); | |
6e694ea3 JM |
1377 | |
1378 | /* | |
1379 | * Need a barrier here before writing the byte_count field to | |
1380 | * make sure that all the data is visible before the | |
1381 | * byte_count field is set. Otherwise, if the segment begins | |
1382 | * a new cacheline, the HCA prefetcher could grab the 64-byte | |
1383 | * chunk and get a valid (!= * 0xffffffff) byte count but | |
1384 | * stale data, and end up sending the wrong data. | |
1385 | */ | |
1386 | wmb(); | |
1387 | ||
1388 | dseg->byte_count = cpu_to_be32(sg->length); | |
d420d9e3 RD |
1389 | } |
1390 | ||
2242fa4f RD |
1391 | static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) |
1392 | { | |
1393 | dseg->byte_count = cpu_to_be32(sg->length); | |
1394 | dseg->lkey = cpu_to_be32(sg->lkey); | |
1395 | dseg->addr = cpu_to_be64(sg->addr); | |
1396 | } | |
1397 | ||
47b37475 | 1398 | static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr, |
b832be1e EC |
1399 | struct mlx4_ib_qp *qp, unsigned *lso_seg_len) |
1400 | { | |
1401 | unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16); | |
1402 | ||
1403 | /* | |
1404 | * This is a temporary limitation and will be removed in | |
1405 | * a forthcoming FW release: | |
1406 | */ | |
1407 | if (unlikely(halign > 64)) | |
1408 | return -EINVAL; | |
1409 | ||
1410 | if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && | |
1411 | wr->num_sge > qp->sq.max_gs - (halign >> 4))) | |
1412 | return -EINVAL; | |
1413 | ||
1414 | memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen); | |
1415 | ||
1416 | /* make sure LSO header is written before overwriting stamping */ | |
1417 | wmb(); | |
1418 | ||
1419 | wqe->mss_hdr_size = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 | | |
1420 | wr->wr.ud.hlen); | |
1421 | ||
1422 | *lso_seg_len = halign; | |
1423 | return 0; | |
1424 | } | |
1425 | ||
225c7b1f RD |
1426 | int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, |
1427 | struct ib_send_wr **bad_wr) | |
1428 | { | |
1429 | struct mlx4_ib_qp *qp = to_mqp(ibqp); | |
1430 | void *wqe; | |
1431 | struct mlx4_wqe_ctrl_seg *ctrl; | |
6e694ea3 | 1432 | struct mlx4_wqe_data_seg *dseg; |
225c7b1f RD |
1433 | unsigned long flags; |
1434 | int nreq; | |
1435 | int err = 0; | |
ea54b10c JM |
1436 | unsigned ind; |
1437 | int uninitialized_var(stamp); | |
1438 | int uninitialized_var(size); | |
a3d8e159 | 1439 | unsigned uninitialized_var(seglen); |
225c7b1f RD |
1440 | int i; |
1441 | ||
96db0e03 | 1442 | spin_lock_irqsave(&qp->sq.lock, flags); |
225c7b1f | 1443 | |
ea54b10c | 1444 | ind = qp->sq_next_wqe; |
225c7b1f RD |
1445 | |
1446 | for (nreq = 0; wr; ++nreq, wr = wr->next) { | |
1447 | if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { | |
1448 | err = -ENOMEM; | |
1449 | *bad_wr = wr; | |
1450 | goto out; | |
1451 | } | |
1452 | ||
1453 | if (unlikely(wr->num_sge > qp->sq.max_gs)) { | |
1454 | err = -EINVAL; | |
1455 | *bad_wr = wr; | |
1456 | goto out; | |
1457 | } | |
1458 | ||
0e6e7416 | 1459 | ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); |
ea54b10c | 1460 | qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; |
225c7b1f RD |
1461 | |
1462 | ctrl->srcrb_flags = | |
1463 | (wr->send_flags & IB_SEND_SIGNALED ? | |
1464 | cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | | |
1465 | (wr->send_flags & IB_SEND_SOLICITED ? | |
1466 | cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | | |
8ff095ec EC |
1467 | ((wr->send_flags & IB_SEND_IP_CSUM) ? |
1468 | cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
1469 | MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | | |
225c7b1f RD |
1470 | qp->sq_signal_bits; |
1471 | ||
1472 | if (wr->opcode == IB_WR_SEND_WITH_IMM || | |
1473 | wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) | |
0f39cf3d | 1474 | ctrl->imm = wr->ex.imm_data; |
225c7b1f RD |
1475 | else |
1476 | ctrl->imm = 0; | |
1477 | ||
1478 | wqe += sizeof *ctrl; | |
1479 | size = sizeof *ctrl / 16; | |
1480 | ||
1481 | switch (ibqp->qp_type) { | |
1482 | case IB_QPT_RC: | |
1483 | case IB_QPT_UC: | |
1484 | switch (wr->opcode) { | |
1485 | case IB_WR_ATOMIC_CMP_AND_SWP: | |
1486 | case IB_WR_ATOMIC_FETCH_AND_ADD: | |
0fbfa6a9 RD |
1487 | set_raddr_seg(wqe, wr->wr.atomic.remote_addr, |
1488 | wr->wr.atomic.rkey); | |
225c7b1f RD |
1489 | wqe += sizeof (struct mlx4_wqe_raddr_seg); |
1490 | ||
0fbfa6a9 | 1491 | set_atomic_seg(wqe, wr); |
225c7b1f | 1492 | wqe += sizeof (struct mlx4_wqe_atomic_seg); |
0fbfa6a9 | 1493 | |
225c7b1f RD |
1494 | size += (sizeof (struct mlx4_wqe_raddr_seg) + |
1495 | sizeof (struct mlx4_wqe_atomic_seg)) / 16; | |
1496 | ||
1497 | break; | |
1498 | ||
1499 | case IB_WR_RDMA_READ: | |
1500 | case IB_WR_RDMA_WRITE: | |
1501 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
0fbfa6a9 RD |
1502 | set_raddr_seg(wqe, wr->wr.rdma.remote_addr, |
1503 | wr->wr.rdma.rkey); | |
225c7b1f RD |
1504 | wqe += sizeof (struct mlx4_wqe_raddr_seg); |
1505 | size += sizeof (struct mlx4_wqe_raddr_seg) / 16; | |
225c7b1f RD |
1506 | break; |
1507 | ||
1508 | default: | |
1509 | /* No extra segments required for sends */ | |
1510 | break; | |
1511 | } | |
1512 | break; | |
1513 | ||
1514 | case IB_QPT_UD: | |
0fbfa6a9 | 1515 | set_datagram_seg(wqe, wr); |
225c7b1f RD |
1516 | wqe += sizeof (struct mlx4_wqe_datagram_seg); |
1517 | size += sizeof (struct mlx4_wqe_datagram_seg) / 16; | |
b832be1e EC |
1518 | |
1519 | if (wr->opcode == IB_WR_LSO) { | |
1520 | err = build_lso_seg(wqe, wr, qp, &seglen); | |
1521 | if (unlikely(err)) { | |
1522 | *bad_wr = wr; | |
1523 | goto out; | |
1524 | } | |
1525 | wqe += seglen; | |
1526 | size += seglen / 16; | |
1527 | } | |
225c7b1f RD |
1528 | break; |
1529 | ||
1530 | case IB_QPT_SMI: | |
1531 | case IB_QPT_GSI: | |
f438000f RD |
1532 | err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen); |
1533 | if (unlikely(err)) { | |
225c7b1f RD |
1534 | *bad_wr = wr; |
1535 | goto out; | |
1536 | } | |
f438000f RD |
1537 | wqe += seglen; |
1538 | size += seglen / 16; | |
225c7b1f RD |
1539 | break; |
1540 | ||
1541 | default: | |
1542 | break; | |
1543 | } | |
1544 | ||
6e694ea3 JM |
1545 | /* |
1546 | * Write data segments in reverse order, so as to | |
1547 | * overwrite cacheline stamp last within each | |
1548 | * cacheline. This avoids issues with WQE | |
1549 | * prefetching. | |
1550 | */ | |
225c7b1f | 1551 | |
6e694ea3 JM |
1552 | dseg = wqe; |
1553 | dseg += wr->num_sge - 1; | |
1554 | size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); | |
225c7b1f RD |
1555 | |
1556 | /* Add one more inline data segment for ICRC for MLX sends */ | |
6e694ea3 JM |
1557 | if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI || |
1558 | qp->ibqp.qp_type == IB_QPT_GSI)) { | |
1559 | set_mlx_icrc_seg(dseg + 1); | |
225c7b1f RD |
1560 | size += sizeof (struct mlx4_wqe_data_seg) / 16; |
1561 | } | |
1562 | ||
6e694ea3 JM |
1563 | for (i = wr->num_sge - 1; i >= 0; --i, --dseg) |
1564 | set_data_seg(dseg, wr->sg_list + i); | |
1565 | ||
225c7b1f RD |
1566 | ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? |
1567 | MLX4_WQE_CTRL_FENCE : 0) | size; | |
1568 | ||
1569 | /* | |
1570 | * Make sure descriptor is fully written before | |
1571 | * setting ownership bit (because HW can start | |
1572 | * executing as soon as we do). | |
1573 | */ | |
1574 | wmb(); | |
1575 | ||
59b0ed12 | 1576 | if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { |
225c7b1f RD |
1577 | err = -EINVAL; |
1578 | goto out; | |
1579 | } | |
1580 | ||
1581 | ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | | |
0e6e7416 RD |
1582 | (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0); |
1583 | ||
ea54b10c JM |
1584 | stamp = ind + qp->sq_spare_wqes; |
1585 | ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); | |
1586 | ||
0e6e7416 RD |
1587 | /* |
1588 | * We can improve latency by not stamping the last | |
1589 | * send queue WQE until after ringing the doorbell, so | |
1590 | * only stamp here if there are still more WQEs to post. | |
ea54b10c JM |
1591 | * |
1592 | * Same optimization applies to padding with NOP wqe | |
1593 | * in case of WQE shrinking (used to prevent wrap-around | |
1594 | * in the middle of WR). | |
0e6e7416 | 1595 | */ |
ea54b10c JM |
1596 | if (wr->next) { |
1597 | stamp_send_wqe(qp, stamp, size * 16); | |
1598 | ind = pad_wraparound(qp, ind); | |
1599 | } | |
225c7b1f | 1600 | |
225c7b1f RD |
1601 | } |
1602 | ||
1603 | out: | |
1604 | if (likely(nreq)) { | |
1605 | qp->sq.head += nreq; | |
1606 | ||
1607 | /* | |
1608 | * Make sure that descriptors are written before | |
1609 | * doorbell record. | |
1610 | */ | |
1611 | wmb(); | |
1612 | ||
1613 | writel(qp->doorbell_qpn, | |
1614 | to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); | |
1615 | ||
1616 | /* | |
1617 | * Make sure doorbells don't leak out of SQ spinlock | |
1618 | * and reach the HCA out of order. | |
1619 | */ | |
1620 | mmiowb(); | |
0e6e7416 | 1621 | |
ea54b10c JM |
1622 | stamp_send_wqe(qp, stamp, size * 16); |
1623 | ||
1624 | ind = pad_wraparound(qp, ind); | |
1625 | qp->sq_next_wqe = ind; | |
225c7b1f RD |
1626 | } |
1627 | ||
96db0e03 | 1628 | spin_unlock_irqrestore(&qp->sq.lock, flags); |
225c7b1f RD |
1629 | |
1630 | return err; | |
1631 | } | |
1632 | ||
1633 | int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, | |
1634 | struct ib_recv_wr **bad_wr) | |
1635 | { | |
1636 | struct mlx4_ib_qp *qp = to_mqp(ibqp); | |
1637 | struct mlx4_wqe_data_seg *scat; | |
1638 | unsigned long flags; | |
1639 | int err = 0; | |
1640 | int nreq; | |
1641 | int ind; | |
1642 | int i; | |
1643 | ||
1644 | spin_lock_irqsave(&qp->rq.lock, flags); | |
1645 | ||
0e6e7416 | 1646 | ind = qp->rq.head & (qp->rq.wqe_cnt - 1); |
225c7b1f RD |
1647 | |
1648 | for (nreq = 0; wr; ++nreq, wr = wr->next) { | |
1649 | if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) { | |
1650 | err = -ENOMEM; | |
1651 | *bad_wr = wr; | |
1652 | goto out; | |
1653 | } | |
1654 | ||
1655 | if (unlikely(wr->num_sge > qp->rq.max_gs)) { | |
1656 | err = -EINVAL; | |
1657 | *bad_wr = wr; | |
1658 | goto out; | |
1659 | } | |
1660 | ||
1661 | scat = get_recv_wqe(qp, ind); | |
1662 | ||
2242fa4f RD |
1663 | for (i = 0; i < wr->num_sge; ++i) |
1664 | __set_data_seg(scat + i, wr->sg_list + i); | |
225c7b1f RD |
1665 | |
1666 | if (i < qp->rq.max_gs) { | |
1667 | scat[i].byte_count = 0; | |
1668 | scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); | |
1669 | scat[i].addr = 0; | |
1670 | } | |
1671 | ||
1672 | qp->rq.wrid[ind] = wr->wr_id; | |
1673 | ||
0e6e7416 | 1674 | ind = (ind + 1) & (qp->rq.wqe_cnt - 1); |
225c7b1f RD |
1675 | } |
1676 | ||
1677 | out: | |
1678 | if (likely(nreq)) { | |
1679 | qp->rq.head += nreq; | |
1680 | ||
1681 | /* | |
1682 | * Make sure that descriptors are written before | |
1683 | * doorbell record. | |
1684 | */ | |
1685 | wmb(); | |
1686 | ||
1687 | *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); | |
1688 | } | |
1689 | ||
1690 | spin_unlock_irqrestore(&qp->rq.lock, flags); | |
1691 | ||
1692 | return err; | |
1693 | } | |
6a775e2b JM |
1694 | |
1695 | static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) | |
1696 | { | |
1697 | switch (mlx4_state) { | |
1698 | case MLX4_QP_STATE_RST: return IB_QPS_RESET; | |
1699 | case MLX4_QP_STATE_INIT: return IB_QPS_INIT; | |
1700 | case MLX4_QP_STATE_RTR: return IB_QPS_RTR; | |
1701 | case MLX4_QP_STATE_RTS: return IB_QPS_RTS; | |
1702 | case MLX4_QP_STATE_SQ_DRAINING: | |
1703 | case MLX4_QP_STATE_SQD: return IB_QPS_SQD; | |
1704 | case MLX4_QP_STATE_SQER: return IB_QPS_SQE; | |
1705 | case MLX4_QP_STATE_ERR: return IB_QPS_ERR; | |
1706 | default: return -1; | |
1707 | } | |
1708 | } | |
1709 | ||
1710 | static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) | |
1711 | { | |
1712 | switch (mlx4_mig_state) { | |
1713 | case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; | |
1714 | case MLX4_QP_PM_REARM: return IB_MIG_REARM; | |
1715 | case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; | |
1716 | default: return -1; | |
1717 | } | |
1718 | } | |
1719 | ||
1720 | static int to_ib_qp_access_flags(int mlx4_flags) | |
1721 | { | |
1722 | int ib_flags = 0; | |
1723 | ||
1724 | if (mlx4_flags & MLX4_QP_BIT_RRE) | |
1725 | ib_flags |= IB_ACCESS_REMOTE_READ; | |
1726 | if (mlx4_flags & MLX4_QP_BIT_RWE) | |
1727 | ib_flags |= IB_ACCESS_REMOTE_WRITE; | |
1728 | if (mlx4_flags & MLX4_QP_BIT_RAE) | |
1729 | ib_flags |= IB_ACCESS_REMOTE_ATOMIC; | |
1730 | ||
1731 | return ib_flags; | |
1732 | } | |
1733 | ||
1734 | static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr, | |
1735 | struct mlx4_qp_path *path) | |
1736 | { | |
8fcea95a | 1737 | memset(ib_ah_attr, 0, sizeof *ib_ah_attr); |
6a775e2b JM |
1738 | ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1; |
1739 | ||
1740 | if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports) | |
1741 | return; | |
1742 | ||
1743 | ib_ah_attr->dlid = be16_to_cpu(path->rlid); | |
1744 | ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf; | |
1745 | ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f; | |
1746 | ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; | |
1747 | ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0; | |
1748 | if (ib_ah_attr->ah_flags) { | |
1749 | ib_ah_attr->grh.sgid_index = path->mgid_index; | |
1750 | ib_ah_attr->grh.hop_limit = path->hop_limit; | |
1751 | ib_ah_attr->grh.traffic_class = | |
1752 | (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; | |
1753 | ib_ah_attr->grh.flow_label = | |
586bb586 | 1754 | be32_to_cpu(path->tclass_flowlabel) & 0xfffff; |
6a775e2b JM |
1755 | memcpy(ib_ah_attr->grh.dgid.raw, |
1756 | path->rgid, sizeof ib_ah_attr->grh.dgid.raw); | |
1757 | } | |
1758 | } | |
1759 | ||
1760 | int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
1761 | struct ib_qp_init_attr *qp_init_attr) | |
1762 | { | |
1763 | struct mlx4_ib_dev *dev = to_mdev(ibqp->device); | |
1764 | struct mlx4_ib_qp *qp = to_mqp(ibqp); | |
1765 | struct mlx4_qp_context context; | |
1766 | int mlx4_state; | |
0df67030 DB |
1767 | int err = 0; |
1768 | ||
1769 | mutex_lock(&qp->mutex); | |
6a775e2b JM |
1770 | |
1771 | if (qp->state == IB_QPS_RESET) { | |
1772 | qp_attr->qp_state = IB_QPS_RESET; | |
1773 | goto done; | |
1774 | } | |
1775 | ||
1776 | err = mlx4_qp_query(dev->dev, &qp->mqp, &context); | |
0df67030 DB |
1777 | if (err) { |
1778 | err = -EINVAL; | |
1779 | goto out; | |
1780 | } | |
6a775e2b JM |
1781 | |
1782 | mlx4_state = be32_to_cpu(context.flags) >> 28; | |
1783 | ||
0df67030 DB |
1784 | qp->state = to_ib_qp_state(mlx4_state); |
1785 | qp_attr->qp_state = qp->state; | |
6a775e2b JM |
1786 | qp_attr->path_mtu = context.mtu_msgmax >> 5; |
1787 | qp_attr->path_mig_state = | |
1788 | to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); | |
1789 | qp_attr->qkey = be32_to_cpu(context.qkey); | |
1790 | qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; | |
1791 | qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; | |
1792 | qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; | |
1793 | qp_attr->qp_access_flags = | |
1794 | to_ib_qp_access_flags(be32_to_cpu(context.params2)); | |
1795 | ||
1796 | if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { | |
1797 | to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path); | |
1798 | to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path); | |
1799 | qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; | |
1800 | qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; | |
1801 | } | |
1802 | ||
1803 | qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; | |
1c27cb71 JM |
1804 | if (qp_attr->qp_state == IB_QPS_INIT) |
1805 | qp_attr->port_num = qp->port; | |
1806 | else | |
1807 | qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; | |
6a775e2b JM |
1808 | |
1809 | /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ | |
1810 | qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; | |
1811 | ||
1812 | qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); | |
1813 | ||
1814 | qp_attr->max_dest_rd_atomic = | |
1815 | 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); | |
1816 | qp_attr->min_rnr_timer = | |
1817 | (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; | |
1818 | qp_attr->timeout = context.pri_path.ackto >> 3; | |
1819 | qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; | |
1820 | qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; | |
1821 | qp_attr->alt_timeout = context.alt_path.ackto >> 3; | |
1822 | ||
1823 | done: | |
1824 | qp_attr->cur_qp_state = qp_attr->qp_state; | |
7f5eb9bb RD |
1825 | qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; |
1826 | qp_attr->cap.max_recv_sge = qp->rq.max_gs; | |
1827 | ||
6a775e2b | 1828 | if (!ibqp->uobject) { |
7f5eb9bb RD |
1829 | qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; |
1830 | qp_attr->cap.max_send_sge = qp->sq.max_gs; | |
1831 | } else { | |
1832 | qp_attr->cap.max_send_wr = 0; | |
1833 | qp_attr->cap.max_send_sge = 0; | |
6a775e2b JM |
1834 | } |
1835 | ||
7f5eb9bb RD |
1836 | /* |
1837 | * We don't support inline sends for kernel QPs (yet), and we | |
1838 | * don't know what userspace's value should be. | |
1839 | */ | |
1840 | qp_attr->cap.max_inline_data = 0; | |
1841 | ||
1842 | qp_init_attr->cap = qp_attr->cap; | |
1843 | ||
521e575b RL |
1844 | qp_init_attr->create_flags = 0; |
1845 | if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) | |
1846 | qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; | |
1847 | ||
1848 | if (qp->flags & MLX4_IB_QP_LSO) | |
1849 | qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; | |
1850 | ||
0df67030 DB |
1851 | out: |
1852 | mutex_unlock(&qp->mutex); | |
1853 | return err; | |
6a775e2b JM |
1854 | } |
1855 |