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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #ifndef MLX4_IB_H | |
35 | #define MLX4_IB_H | |
36 | ||
37 | #include <linux/compiler.h> | |
38 | #include <linux/list.h> | |
63019d93 | 39 | #include <linux/mutex.h> |
b9c5d6a6 | 40 | #include <linux/idr.h> |
225c7b1f RD |
41 | |
42 | #include <rdma/ib_verbs.h> | |
43 | #include <rdma/ib_umem.h> | |
b9c5d6a6 | 44 | #include <rdma/ib_mad.h> |
a0c64a17 | 45 | #include <rdma/ib_sa.h> |
225c7b1f RD |
46 | |
47 | #include <linux/mlx4/device.h> | |
48 | #include <linux/mlx4/doorbell.h> | |
3078f5f1 | 49 | #include <linux/mlx4/qp.h> |
34d9a270 | 50 | #include <linux/mlx4/cq.h> |
225c7b1f | 51 | |
b1d8eb5a JM |
52 | #define MLX4_IB_DRV_NAME "mlx4_ib" |
53 | ||
54 | #ifdef pr_fmt | |
55 | #undef pr_fmt | |
56 | #endif | |
57 | #define pr_fmt(fmt) "<" MLX4_IB_DRV_NAME "> %s: " fmt, __func__ | |
58 | ||
59 | #define mlx4_ib_warn(ibdev, format, arg...) \ | |
d66c88a8 | 60 | dev_warn((ibdev)->dev.parent, MLX4_IB_DRV_NAME ": " format, ## arg) |
b1d8eb5a | 61 | |
fc2d0044 SG |
62 | enum { |
63 | MLX4_IB_SQ_MIN_WQE_SHIFT = 6, | |
64 | MLX4_IB_MAX_HEADROOM = 2048 | |
65 | }; | |
66 | ||
67 | #define MLX4_IB_SQ_HEADROOM(shift) ((MLX4_IB_MAX_HEADROOM >> (shift)) + 1) | |
68 | #define MLX4_IB_SQ_MAX_SPARE (MLX4_IB_SQ_HEADROOM(MLX4_IB_SQ_MIN_WQE_SHIFT)) | |
69 | ||
a0c64a17 JM |
70 | /*module param to indicate if SM assigns the alias_GUID*/ |
71 | extern int mlx4_ib_sm_guid_assign; | |
72 | ||
c1c98501 MB |
73 | #define MLX4_IB_UC_STEER_QPN_ALIGN 1 |
74 | #define MLX4_IB_UC_MAX_NUM_QPS 256 | |
ae184dde YH |
75 | |
76 | enum hw_bar_type { | |
77 | HW_BAR_BF, | |
78 | HW_BAR_DB, | |
79 | HW_BAR_CLOCK, | |
80 | HW_BAR_COUNT | |
81 | }; | |
82 | ||
225c7b1f RD |
83 | struct mlx4_ib_ucontext { |
84 | struct ib_ucontext ibucontext; | |
85 | struct mlx4_uar uar; | |
86 | struct list_head db_page_list; | |
87 | struct mutex db_page_mutex; | |
400b1ebc GL |
88 | struct list_head wqn_ranges_list; |
89 | struct mutex wqn_ranges_mutex; /* protect wqn_ranges_list */ | |
225c7b1f RD |
90 | }; |
91 | ||
92 | struct mlx4_ib_pd { | |
93 | struct ib_pd ibpd; | |
94 | u32 pdn; | |
95 | }; | |
96 | ||
012a8ff5 SH |
97 | struct mlx4_ib_xrcd { |
98 | struct ib_xrcd ibxrcd; | |
99 | u32 xrcdn; | |
100 | struct ib_pd *pd; | |
101 | struct ib_cq *cq; | |
102 | }; | |
103 | ||
225c7b1f RD |
104 | struct mlx4_ib_cq_buf { |
105 | struct mlx4_buf buf; | |
106 | struct mlx4_mtt mtt; | |
08ff3235 | 107 | int entry_size; |
225c7b1f RD |
108 | }; |
109 | ||
bbf8eed1 VS |
110 | struct mlx4_ib_cq_resize { |
111 | struct mlx4_ib_cq_buf buf; | |
112 | int cqe; | |
113 | }; | |
114 | ||
225c7b1f RD |
115 | struct mlx4_ib_cq { |
116 | struct ib_cq ibcq; | |
117 | struct mlx4_cq mcq; | |
118 | struct mlx4_ib_cq_buf buf; | |
bbf8eed1 | 119 | struct mlx4_ib_cq_resize *resize_buf; |
6296883c | 120 | struct mlx4_db db; |
225c7b1f | 121 | spinlock_t lock; |
bbf8eed1 | 122 | struct mutex resize_mutex; |
225c7b1f | 123 | struct ib_umem *umem; |
bbf8eed1 | 124 | struct ib_umem *resize_umem; |
4b664c43 | 125 | int create_flags; |
35f05dab YH |
126 | /* List of qps that it serves.*/ |
127 | struct list_head send_qp_list; | |
128 | struct list_head recv_qp_list; | |
225c7b1f RD |
129 | }; |
130 | ||
1b2cd0fc SG |
131 | #define MLX4_MR_PAGES_ALIGN 0x40 |
132 | ||
225c7b1f RD |
133 | struct mlx4_ib_mr { |
134 | struct ib_mr ibmr; | |
1b2cd0fc SG |
135 | __be64 *pages; |
136 | dma_addr_t page_map; | |
137 | u32 npages; | |
138 | u32 max_pages; | |
225c7b1f RD |
139 | struct mlx4_mr mmr; |
140 | struct ib_umem *umem; | |
cbc9355a | 141 | size_t page_map_size; |
225c7b1f RD |
142 | }; |
143 | ||
804d6a89 SM |
144 | struct mlx4_ib_mw { |
145 | struct ib_mw ibmw; | |
146 | struct mlx4_mw mmw; | |
147 | }; | |
148 | ||
146d6e19 MS |
149 | #define MAX_REGS_PER_FLOW 2 |
150 | ||
151 | struct mlx4_flow_reg_id { | |
152 | u64 id; | |
153 | u64 mirror; | |
154 | }; | |
155 | ||
f77c0162 HHZ |
156 | struct mlx4_ib_flow { |
157 | struct ib_flow ibflow; | |
158 | /* translating DMFS verbs sniffer rule to FW API requires two reg IDs */ | |
146d6e19 | 159 | struct mlx4_flow_reg_id reg_id[MAX_REGS_PER_FLOW]; |
f77c0162 HHZ |
160 | }; |
161 | ||
225c7b1f RD |
162 | struct mlx4_ib_wq { |
163 | u64 *wrid; | |
164 | spinlock_t lock; | |
0e6e7416 RD |
165 | int wqe_cnt; |
166 | int max_post; | |
225c7b1f RD |
167 | int max_gs; |
168 | int offset; | |
169 | int wqe_shift; | |
170 | unsigned head; | |
171 | unsigned tail; | |
172 | }; | |
173 | ||
e1b866c6 MS |
174 | enum { |
175 | MLX4_IB_QP_CREATE_ROCE_V2_GSI = IB_QP_CREATE_RESERVED_START | |
176 | }; | |
177 | ||
b832be1e | 178 | enum mlx4_ib_qp_flags { |
1ffeb2eb JM |
179 | MLX4_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO, |
180 | MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK, | |
c1c98501 | 181 | MLX4_IB_QP_NETIF = IB_QP_CREATE_NETIF_QP, |
6d06c9aa | 182 | MLX4_IB_QP_SCATTER_FCS = IB_QP_CREATE_SCATTER_FCS, |
e1b866c6 MS |
183 | |
184 | /* Mellanox specific flags start from IB_QP_CREATE_RESERVED_START */ | |
185 | MLX4_IB_ROCE_V2_GSI_QP = MLX4_IB_QP_CREATE_ROCE_V2_GSI, | |
1ffeb2eb JM |
186 | MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30, |
187 | MLX4_IB_SRIOV_SQP = 1 << 31, | |
b832be1e EC |
188 | }; |
189 | ||
fa417f7b EC |
190 | struct mlx4_ib_gid_entry { |
191 | struct list_head list; | |
192 | union ib_gid gid; | |
193 | int added; | |
194 | u8 port; | |
195 | }; | |
196 | ||
1ffeb2eb JM |
197 | enum mlx4_ib_qp_type { |
198 | /* | |
199 | * IB_QPT_SMI and IB_QPT_GSI have to be the first two entries | |
200 | * here (and in that order) since the MAD layer uses them as | |
201 | * indices into a 2-entry table. | |
202 | */ | |
203 | MLX4_IB_QPT_SMI = IB_QPT_SMI, | |
204 | MLX4_IB_QPT_GSI = IB_QPT_GSI, | |
205 | ||
206 | MLX4_IB_QPT_RC = IB_QPT_RC, | |
207 | MLX4_IB_QPT_UC = IB_QPT_UC, | |
208 | MLX4_IB_QPT_UD = IB_QPT_UD, | |
209 | MLX4_IB_QPT_RAW_IPV6 = IB_QPT_RAW_IPV6, | |
210 | MLX4_IB_QPT_RAW_ETHERTYPE = IB_QPT_RAW_ETHERTYPE, | |
211 | MLX4_IB_QPT_RAW_PACKET = IB_QPT_RAW_PACKET, | |
212 | MLX4_IB_QPT_XRC_INI = IB_QPT_XRC_INI, | |
213 | MLX4_IB_QPT_XRC_TGT = IB_QPT_XRC_TGT, | |
214 | ||
215 | MLX4_IB_QPT_PROXY_SMI_OWNER = 1 << 16, | |
216 | MLX4_IB_QPT_PROXY_SMI = 1 << 17, | |
217 | MLX4_IB_QPT_PROXY_GSI = 1 << 18, | |
218 | MLX4_IB_QPT_TUN_SMI_OWNER = 1 << 19, | |
219 | MLX4_IB_QPT_TUN_SMI = 1 << 20, | |
220 | MLX4_IB_QPT_TUN_GSI = 1 << 21, | |
221 | }; | |
222 | ||
223 | #define MLX4_IB_QPT_ANY_SRIOV (MLX4_IB_QPT_PROXY_SMI_OWNER | \ | |
224 | MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER | \ | |
225 | MLX4_IB_QPT_TUN_SMI | MLX4_IB_QPT_TUN_GSI) | |
226 | ||
0a9a0188 JM |
227 | enum mlx4_ib_mad_ifc_flags { |
228 | MLX4_MAD_IFC_IGNORE_MKEY = 1, | |
229 | MLX4_MAD_IFC_IGNORE_BKEY = 2, | |
230 | MLX4_MAD_IFC_IGNORE_KEYS = (MLX4_MAD_IFC_IGNORE_MKEY | | |
231 | MLX4_MAD_IFC_IGNORE_BKEY), | |
232 | MLX4_MAD_IFC_NET_VIEW = 4, | |
233 | }; | |
234 | ||
fc06573d | 235 | enum { |
0ae207fb HB |
236 | MLX4_NUM_TUNNEL_BUFS = 512, |
237 | MLX4_NUM_WIRE_BUFS = 2048, | |
fc06573d JM |
238 | }; |
239 | ||
1ffeb2eb JM |
240 | struct mlx4_ib_tunnel_header { |
241 | struct mlx4_av av; | |
242 | __be32 remote_qpn; | |
243 | __be32 qkey; | |
244 | __be16 vlan; | |
245 | u8 mac[6]; | |
246 | __be16 pkey_index; | |
247 | u8 reserved[6]; | |
248 | }; | |
249 | ||
250 | struct mlx4_ib_buf { | |
251 | void *addr; | |
252 | dma_addr_t map; | |
253 | }; | |
254 | ||
255 | struct mlx4_rcv_tunnel_hdr { | |
256 | __be32 flags_src_qp; /* flags[6:5] is defined for VLANs: | |
257 | * 0x0 - no vlan was in the packet | |
258 | * 0x01 - C-VLAN was in the packet */ | |
259 | u8 g_ml_path; /* gid bit stands for ipv6/4 header in RoCE */ | |
260 | u8 reserved; | |
261 | __be16 pkey_index; | |
262 | __be16 sl_vid; | |
263 | __be16 slid_mac_47_32; | |
264 | __be32 mac_31_0; | |
265 | }; | |
266 | ||
267 | struct mlx4_ib_proxy_sqp_hdr { | |
268 | struct ib_grh grh; | |
269 | struct mlx4_rcv_tunnel_hdr tun; | |
270 | } __packed; | |
271 | ||
2f5bb473 JM |
272 | struct mlx4_roce_smac_vlan_info { |
273 | u64 smac; | |
274 | int smac_index; | |
275 | int smac_port; | |
276 | u64 candidate_smac; | |
277 | int candidate_smac_index; | |
278 | int candidate_smac_port; | |
279 | u16 vid; | |
280 | int vlan_index; | |
281 | int vlan_port; | |
282 | u16 candidate_vid; | |
283 | int candidate_vlan_index; | |
284 | int candidate_vlan_port; | |
285 | int update_vid; | |
286 | }; | |
287 | ||
400b1ebc GL |
288 | struct mlx4_wqn_range { |
289 | int base_wqn; | |
290 | int size; | |
291 | int refcount; | |
292 | bool dirty; | |
293 | struct list_head list; | |
294 | }; | |
295 | ||
3078f5f1 GL |
296 | struct mlx4_ib_rss { |
297 | unsigned int base_qpn_tbl_sz; | |
298 | u8 flags; | |
299 | u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; | |
300 | }; | |
301 | ||
225c7b1f | 302 | struct mlx4_ib_qp { |
400b1ebc GL |
303 | union { |
304 | struct ib_qp ibqp; | |
305 | struct ib_wq ibwq; | |
306 | }; | |
225c7b1f RD |
307 | struct mlx4_qp mqp; |
308 | struct mlx4_buf buf; | |
309 | ||
6296883c | 310 | struct mlx4_db db; |
225c7b1f RD |
311 | struct mlx4_ib_wq rq; |
312 | ||
313 | u32 doorbell_qpn; | |
314 | __be32 sq_signal_bits; | |
ea54b10c | 315 | unsigned sq_next_wqe; |
0e6e7416 | 316 | int sq_spare_wqes; |
225c7b1f RD |
317 | struct mlx4_ib_wq sq; |
318 | ||
1ffeb2eb | 319 | enum mlx4_ib_qp_type mlx4_ib_qp_type; |
225c7b1f RD |
320 | struct ib_umem *umem; |
321 | struct mlx4_mtt mtt; | |
322 | int buf_size; | |
323 | struct mutex mutex; | |
0a1405da | 324 | u16 xrcdn; |
b832be1e | 325 | u32 flags; |
225c7b1f RD |
326 | u8 port; |
327 | u8 alt_port; | |
328 | u8 atomic_rd_en; | |
329 | u8 resp_depth; | |
0e6e7416 | 330 | u8 sq_no_prefetch; |
225c7b1f | 331 | u8 state; |
fa417f7b | 332 | int mlx_type; |
ea30b966 | 333 | u32 inl_recv_sz; |
fa417f7b | 334 | struct list_head gid_list; |
0ff1fb65 | 335 | struct list_head steering_rules; |
1ffeb2eb | 336 | struct mlx4_ib_buf *sqp_proxy_rcv; |
2f5bb473 JM |
337 | struct mlx4_roce_smac_vlan_info pri; |
338 | struct mlx4_roce_smac_vlan_info alt; | |
c1c98501 | 339 | u64 reg_id; |
35f05dab YH |
340 | struct list_head qps_list; |
341 | struct list_head cq_recv_list; | |
342 | struct list_head cq_send_list; | |
7b59f0f9 | 343 | struct counter_index *counter_index; |
400b1ebc GL |
344 | struct mlx4_wqn_range *wqn_range; |
345 | /* Number of RSS QP parents that uses this WQ */ | |
346 | u32 rss_usecnt; | |
3078f5f1 | 347 | struct mlx4_ib_rss *rss_ctx; |
225c7b1f RD |
348 | }; |
349 | ||
350 | struct mlx4_ib_srq { | |
351 | struct ib_srq ibsrq; | |
352 | struct mlx4_srq msrq; | |
353 | struct mlx4_buf buf; | |
6296883c | 354 | struct mlx4_db db; |
225c7b1f RD |
355 | u64 *wrid; |
356 | spinlock_t lock; | |
357 | int head; | |
358 | int tail; | |
359 | u16 wqe_ctr; | |
360 | struct ib_umem *umem; | |
361 | struct mlx4_mtt mtt; | |
362 | struct mutex mutex; | |
363 | }; | |
364 | ||
365 | struct mlx4_ib_ah { | |
366 | struct ib_ah ibah; | |
fa417f7b EC |
367 | union mlx4_ext_av av; |
368 | }; | |
369 | ||
a0c64a17 JM |
370 | /****************************************/ |
371 | /* alias guid support */ | |
372 | /****************************************/ | |
373 | #define NUM_PORT_ALIAS_GUID 2 | |
374 | #define NUM_ALIAS_GUID_IN_REC 8 | |
375 | #define NUM_ALIAS_GUID_REC_IN_PORT 16 | |
376 | #define GUID_REC_SIZE 8 | |
377 | #define NUM_ALIAS_GUID_PER_PORT 128 | |
378 | #define MLX4_NOT_SET_GUID (0x00LL) | |
379 | #define MLX4_GUID_FOR_DELETE_VAL (~(0x00LL)) | |
380 | ||
381 | enum mlx4_guid_alias_rec_status { | |
382 | MLX4_GUID_INFO_STATUS_IDLE, | |
383 | MLX4_GUID_INFO_STATUS_SET, | |
a0c64a17 JM |
384 | }; |
385 | ||
f5479601 | 386 | #define GUID_STATE_NEED_PORT_INIT 0x01 |
a0c64a17 JM |
387 | |
388 | enum mlx4_guid_alias_rec_method { | |
389 | MLX4_GUID_INFO_RECORD_SET = IB_MGMT_METHOD_SET, | |
390 | MLX4_GUID_INFO_RECORD_DELETE = IB_SA_METHOD_DELETE, | |
391 | }; | |
392 | ||
393 | struct mlx4_sriov_alias_guid_info_rec_det { | |
394 | u8 all_recs[GUID_REC_SIZE * NUM_ALIAS_GUID_IN_REC]; | |
395 | ib_sa_comp_mask guid_indexes; /*indicates what from the 8 records are valid*/ | |
396 | enum mlx4_guid_alias_rec_status status; /*indicates the administraively status of the record.*/ | |
99ee4df6 YH |
397 | unsigned int guids_retry_schedule[NUM_ALIAS_GUID_IN_REC]; |
398 | u64 time_to_run; | |
a0c64a17 JM |
399 | }; |
400 | ||
401 | struct mlx4_sriov_alias_guid_port_rec_det { | |
402 | struct mlx4_sriov_alias_guid_info_rec_det all_rec_per_port[NUM_ALIAS_GUID_REC_IN_PORT]; | |
403 | struct workqueue_struct *wq; | |
404 | struct delayed_work alias_guid_work; | |
405 | u8 port; | |
f5479601 | 406 | u32 state_flags; |
a0c64a17 JM |
407 | struct mlx4_sriov_alias_guid *parent; |
408 | struct list_head cb_list; | |
409 | }; | |
410 | ||
411 | struct mlx4_sriov_alias_guid { | |
412 | struct mlx4_sriov_alias_guid_port_rec_det ports_guid[MLX4_MAX_PORTS]; | |
413 | spinlock_t ag_work_lock; | |
414 | struct ib_sa_client *sa_client; | |
415 | }; | |
416 | ||
fc06573d JM |
417 | struct mlx4_ib_demux_work { |
418 | struct work_struct work; | |
419 | struct mlx4_ib_dev *dev; | |
420 | int slave; | |
421 | int do_init; | |
422 | u8 port; | |
423 | ||
424 | }; | |
425 | ||
1ffeb2eb JM |
426 | struct mlx4_ib_tun_tx_buf { |
427 | struct mlx4_ib_buf buf; | |
428 | struct ib_ah *ah; | |
429 | }; | |
430 | ||
431 | struct mlx4_ib_demux_pv_qp { | |
432 | struct ib_qp *qp; | |
433 | enum ib_qp_type proxy_qpt; | |
434 | struct mlx4_ib_buf *ring; | |
435 | struct mlx4_ib_tun_tx_buf *tx_ring; | |
436 | spinlock_t tx_lock; | |
437 | unsigned tx_ix_head; | |
438 | unsigned tx_ix_tail; | |
439 | }; | |
440 | ||
fc06573d JM |
441 | enum mlx4_ib_demux_pv_state { |
442 | DEMUX_PV_STATE_DOWN, | |
443 | DEMUX_PV_STATE_STARTING, | |
444 | DEMUX_PV_STATE_ACTIVE, | |
445 | DEMUX_PV_STATE_DOWNING, | |
446 | }; | |
447 | ||
1ffeb2eb JM |
448 | struct mlx4_ib_demux_pv_ctx { |
449 | int port; | |
450 | int slave; | |
fc06573d | 451 | enum mlx4_ib_demux_pv_state state; |
1ffeb2eb JM |
452 | int has_smi; |
453 | struct ib_device *ib_dev; | |
454 | struct ib_cq *cq; | |
455 | struct ib_pd *pd; | |
1ffeb2eb JM |
456 | struct work_struct work; |
457 | struct workqueue_struct *wq; | |
7fd1507d | 458 | struct workqueue_struct *wi_wq; |
1ffeb2eb JM |
459 | struct mlx4_ib_demux_pv_qp qp[2]; |
460 | }; | |
461 | ||
462 | struct mlx4_ib_demux_ctx { | |
463 | struct ib_device *ib_dev; | |
464 | int port; | |
465 | struct workqueue_struct *wq; | |
7fd1507d | 466 | struct workqueue_struct *wi_wq; |
1ffeb2eb JM |
467 | struct workqueue_struct *ud_wq; |
468 | spinlock_t ud_lock; | |
8ec07bf8 | 469 | atomic64_t subnet_prefix; |
1ffeb2eb JM |
470 | __be64 guid_cache[128]; |
471 | struct mlx4_ib_dev *dev; | |
b9c5d6a6 OD |
472 | /* the following lock protects both mcg_table and mcg_mgid0_list */ |
473 | struct mutex mcg_table_lock; | |
474 | struct rb_root mcg_table; | |
475 | struct list_head mcg_mgid0_list; | |
476 | struct workqueue_struct *mcg_wq; | |
1ffeb2eb | 477 | struct mlx4_ib_demux_pv_ctx **tun; |
b9c5d6a6 OD |
478 | atomic_t tid; |
479 | int flushing; /* flushing the work queue */ | |
1ffeb2eb JM |
480 | }; |
481 | ||
482 | struct mlx4_ib_sriov { | |
483 | struct mlx4_ib_demux_ctx demux[MLX4_MAX_PORTS]; | |
484 | struct mlx4_ib_demux_pv_ctx *sqps[MLX4_MAX_PORTS]; | |
485 | /* when using this spinlock you should use "irq" because | |
486 | * it may be called from interrupt context.*/ | |
487 | spinlock_t going_down_lock; | |
488 | int is_going_down; | |
3cf69cc8 | 489 | |
a0c64a17 JM |
490 | struct mlx4_sriov_alias_guid alias_guid; |
491 | ||
3cf69cc8 | 492 | /* CM paravirtualization fields */ |
f1430536 MW |
493 | struct xarray pv_id_table; |
494 | u32 pv_id_next; | |
3cf69cc8 AV |
495 | spinlock_t id_map_lock; |
496 | struct rb_root sl_id_map; | |
f1430536 | 497 | struct list_head cm_list; |
227a0e14 HB |
498 | /* Protects the radix-tree */ |
499 | struct mutex rej_tmout_lock; | |
500 | struct radix_tree_root rej_tmout_root; | |
1ffeb2eb JM |
501 | }; |
502 | ||
e26be1bf MS |
503 | struct gid_cache_context { |
504 | int real_index; | |
505 | int refcount; | |
506 | }; | |
507 | ||
508 | struct gid_entry { | |
509 | union ib_gid gid; | |
b699a859 | 510 | enum ib_gid_type gid_type; |
e26be1bf | 511 | struct gid_cache_context *ctx; |
ff3195b3 | 512 | u16 vlan_id; |
e26be1bf MS |
513 | }; |
514 | ||
515 | struct mlx4_port_gid_table { | |
516 | struct gid_entry gids[MLX4_MAX_PORT_GIDS]; | |
517 | }; | |
518 | ||
fa417f7b EC |
519 | struct mlx4_ib_iboe { |
520 | spinlock_t lock; | |
521 | struct net_device *netdevs[MLX4_MAX_PORTS]; | |
3e0629cb | 522 | atomic64_t mac[MLX4_MAX_PORTS]; |
fa417f7b | 523 | struct notifier_block nb; |
e26be1bf | 524 | struct mlx4_port_gid_table gids[MLX4_MAX_PORTS]; |
fc6526fb | 525 | enum ib_port_state last_port_state[MLX4_MAX_PORTS]; |
225c7b1f RD |
526 | }; |
527 | ||
fc06573d JM |
528 | struct pkey_mgt { |
529 | u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; | |
530 | u16 phys_pkey_cache[MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; | |
531 | struct list_head pkey_port_list[MLX4_MFUNC_MAX]; | |
532 | struct kobject *device_parent[MLX4_MFUNC_MAX]; | |
533 | }; | |
534 | ||
c1e7e466 JM |
535 | struct mlx4_ib_iov_sysfs_attr { |
536 | void *ctx; | |
537 | struct kobject *kobj; | |
538 | unsigned long data; | |
539 | u32 entry_num; | |
540 | char name[15]; | |
541 | struct device_attribute dentry; | |
542 | struct device *dev; | |
543 | }; | |
544 | ||
545 | struct mlx4_ib_iov_sysfs_attr_ar { | |
546 | struct mlx4_ib_iov_sysfs_attr dentries[3 * NUM_ALIAS_GUID_PER_PORT + 1]; | |
547 | }; | |
548 | ||
549 | struct mlx4_ib_iov_port { | |
550 | char name[100]; | |
551 | u8 num; | |
552 | struct mlx4_ib_dev *dev; | |
553 | struct list_head list; | |
554 | struct mlx4_ib_iov_sysfs_attr_ar *dentr_ar; | |
555 | struct ib_port_attr attr; | |
556 | struct kobject *cur_port; | |
557 | struct kobject *admin_alias_parent; | |
558 | struct kobject *gids_parent; | |
559 | struct kobject *pkeys_parent; | |
560 | struct kobject *mcgs_parent; | |
561 | struct mlx4_ib_iov_sysfs_attr mcg_dentry; | |
562 | }; | |
563 | ||
c3abb51b | 564 | struct counter_index { |
3ba8e31d | 565 | struct list_head list; |
c3abb51b EBE |
566 | u32 index; |
567 | u8 allocated; | |
568 | }; | |
569 | ||
3ba8e31d EBE |
570 | struct mlx4_ib_counters { |
571 | struct list_head counters_list; | |
572 | struct mutex mutex; /* mutex for accessing counters list */ | |
573 | u32 default_counter; | |
574 | }; | |
575 | ||
3f85f2aa MB |
576 | #define MLX4_DIAG_COUNTERS_TYPES 2 |
577 | ||
578 | struct mlx4_ib_diag_counters { | |
579 | const char **name; | |
580 | u32 *offset; | |
581 | u32 num_counters; | |
582 | }; | |
583 | ||
225c7b1f RD |
584 | struct mlx4_ib_dev { |
585 | struct ib_device ib_dev; | |
586 | struct mlx4_dev *dev; | |
7ff93f8b | 587 | int num_ports; |
225c7b1f RD |
588 | void __iomem *uar_map; |
589 | ||
225c7b1f RD |
590 | struct mlx4_uar priv_uar; |
591 | u32 priv_pdn; | |
592 | MLX4_DECLARE_DOORBELL_LOCK(uar_lock); | |
593 | ||
594 | struct ib_mad_agent *send_agent[MLX4_MAX_PORTS][2]; | |
595 | struct ib_ah *sm_ah[MLX4_MAX_PORTS]; | |
596 | spinlock_t sm_lock; | |
fd10ed8e | 597 | atomic64_t sl2vl[MLX4_MAX_PORTS]; |
1ffeb2eb | 598 | struct mlx4_ib_sriov sriov; |
225c7b1f RD |
599 | |
600 | struct mutex cap_mask_mutex; | |
3b4a8cd5 | 601 | bool ib_active; |
fa417f7b | 602 | struct mlx4_ib_iboe iboe; |
3ba8e31d | 603 | struct mlx4_ib_counters counters_table[MLX4_MAX_PORTS]; |
e605b743 | 604 | int *eq_table; |
c1e7e466 JM |
605 | struct kobject *iov_parent; |
606 | struct kobject *ports_parent; | |
607 | struct kobject *dev_ports_parent[MLX4_MFUNC_MAX]; | |
608 | struct mlx4_ib_iov_port iov_ports[MLX4_MAX_PORTS]; | |
fc06573d | 609 | struct pkey_mgt pkeys; |
c1c98501 MB |
610 | unsigned long *ib_uc_qpns_bitmap; |
611 | int steer_qpn_count; | |
612 | int steer_qpn_base; | |
0a9b7d59 | 613 | int steering_support; |
9433c188 MB |
614 | struct mlx4_ib_qp *qp1_proxy[MLX4_MAX_PORTS]; |
615 | /* lock when destroying qp1_proxy and getting netdev events */ | |
616 | struct mutex qp1_proxy_lock[MLX4_MAX_PORTS]; | |
c6215745 | 617 | u8 bond_next_port; |
35f05dab YH |
618 | /* protect resources needed as part of reset flow */ |
619 | spinlock_t reset_flow_resource_lock; | |
620 | struct list_head qp_list; | |
3f85f2aa | 621 | struct mlx4_ib_diag_counters diag_counters[MLX4_DIAG_COUNTERS_TYPES]; |
225c7b1f RD |
622 | }; |
623 | ||
00f5ce99 JM |
624 | struct ib_event_work { |
625 | struct work_struct work; | |
626 | struct mlx4_ib_dev *ib_dev; | |
627 | struct mlx4_eqe ib_eqe; | |
fd10ed8e | 628 | int port; |
00f5ce99 JM |
629 | }; |
630 | ||
1ffeb2eb JM |
631 | struct mlx4_ib_qp_tunnel_init_attr { |
632 | struct ib_qp_init_attr init_attr; | |
633 | int slave; | |
634 | enum ib_qp_type proxy_qp_type; | |
635 | u8 port; | |
636 | }; | |
637 | ||
4b664c43 MB |
638 | struct mlx4_uverbs_ex_query_device { |
639 | __u32 comp_mask; | |
640 | __u32 reserved; | |
641 | }; | |
642 | ||
225c7b1f RD |
643 | static inline struct mlx4_ib_dev *to_mdev(struct ib_device *ibdev) |
644 | { | |
645 | return container_of(ibdev, struct mlx4_ib_dev, ib_dev); | |
646 | } | |
647 | ||
648 | static inline struct mlx4_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) | |
649 | { | |
650 | return container_of(ibucontext, struct mlx4_ib_ucontext, ibucontext); | |
651 | } | |
652 | ||
653 | static inline struct mlx4_ib_pd *to_mpd(struct ib_pd *ibpd) | |
654 | { | |
655 | return container_of(ibpd, struct mlx4_ib_pd, ibpd); | |
656 | } | |
657 | ||
012a8ff5 SH |
658 | static inline struct mlx4_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) |
659 | { | |
660 | return container_of(ibxrcd, struct mlx4_ib_xrcd, ibxrcd); | |
661 | } | |
662 | ||
225c7b1f RD |
663 | static inline struct mlx4_ib_cq *to_mcq(struct ib_cq *ibcq) |
664 | { | |
665 | return container_of(ibcq, struct mlx4_ib_cq, ibcq); | |
666 | } | |
667 | ||
668 | static inline struct mlx4_ib_cq *to_mibcq(struct mlx4_cq *mcq) | |
669 | { | |
670 | return container_of(mcq, struct mlx4_ib_cq, mcq); | |
671 | } | |
672 | ||
673 | static inline struct mlx4_ib_mr *to_mmr(struct ib_mr *ibmr) | |
674 | { | |
675 | return container_of(ibmr, struct mlx4_ib_mr, ibmr); | |
676 | } | |
677 | ||
804d6a89 SM |
678 | static inline struct mlx4_ib_mw *to_mmw(struct ib_mw *ibmw) |
679 | { | |
680 | return container_of(ibmw, struct mlx4_ib_mw, ibmw); | |
681 | } | |
682 | ||
f77c0162 HHZ |
683 | static inline struct mlx4_ib_flow *to_mflow(struct ib_flow *ibflow) |
684 | { | |
685 | return container_of(ibflow, struct mlx4_ib_flow, ibflow); | |
686 | } | |
687 | ||
225c7b1f RD |
688 | static inline struct mlx4_ib_qp *to_mqp(struct ib_qp *ibqp) |
689 | { | |
690 | return container_of(ibqp, struct mlx4_ib_qp, ibqp); | |
691 | } | |
692 | ||
693 | static inline struct mlx4_ib_qp *to_mibqp(struct mlx4_qp *mqp) | |
694 | { | |
695 | return container_of(mqp, struct mlx4_ib_qp, mqp); | |
696 | } | |
697 | ||
698 | static inline struct mlx4_ib_srq *to_msrq(struct ib_srq *ibsrq) | |
699 | { | |
700 | return container_of(ibsrq, struct mlx4_ib_srq, ibsrq); | |
701 | } | |
702 | ||
703 | static inline struct mlx4_ib_srq *to_mibsrq(struct mlx4_srq *msrq) | |
704 | { | |
705 | return container_of(msrq, struct mlx4_ib_srq, msrq); | |
706 | } | |
707 | ||
708 | static inline struct mlx4_ib_ah *to_mah(struct ib_ah *ibah) | |
709 | { | |
710 | return container_of(ibah, struct mlx4_ib_ah, ibah); | |
711 | } | |
712 | ||
c6215745 MS |
713 | static inline u8 mlx4_ib_bond_next_port(struct mlx4_ib_dev *dev) |
714 | { | |
715 | dev->bond_next_port = (dev->bond_next_port + 1) % dev->num_ports; | |
716 | ||
717 | return dev->bond_next_port + 1; | |
718 | } | |
719 | ||
fc06573d JM |
720 | int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev); |
721 | void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev); | |
722 | ||
ff23dfa1 | 723 | int mlx4_ib_db_map_user(struct ib_udata *udata, unsigned long virt, |
6296883c YP |
724 | struct mlx4_db *db); |
725 | void mlx4_ib_db_unmap_user(struct mlx4_ib_ucontext *context, struct mlx4_db *db); | |
225c7b1f RD |
726 | |
727 | struct ib_mr *mlx4_ib_get_dma_mr(struct ib_pd *pd, int acc); | |
728 | int mlx4_ib_umem_write_mtt(struct mlx4_ib_dev *dev, struct mlx4_mtt *mtt, | |
729 | struct ib_umem *umem); | |
730 | struct ib_mr *mlx4_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
731 | u64 virt_addr, int access_flags, | |
732 | struct ib_udata *udata); | |
c4367a26 | 733 | int mlx4_ib_dereg_mr(struct ib_mr *mr, struct ib_udata *udata); |
b2a239df MB |
734 | struct ib_mw *mlx4_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, |
735 | struct ib_udata *udata); | |
804d6a89 | 736 | int mlx4_ib_dealloc_mw(struct ib_mw *mw); |
c4367a26 | 737 | struct ib_mr *mlx4_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
42a3b153 | 738 | u32 max_num_sg); |
ff2ba993 | 739 | int mlx4_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
9aa8b321 | 740 | unsigned int *sg_offset); |
3fdcb97f | 741 | int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); |
bbf8eed1 | 742 | int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); |
e39afe3d LR |
743 | int mlx4_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, |
744 | struct ib_udata *udata); | |
a52c8e24 | 745 | void mlx4_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); |
225c7b1f RD |
746 | int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); |
747 | int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags); | |
748 | void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); | |
749 | void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); | |
750 | ||
fa5d010c | 751 | int mlx4_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, |
d3456914 LR |
752 | struct ib_udata *udata); |
753 | int mlx4_ib_create_ah_slave(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, | |
754 | int slave_sgid_index, u8 *s_mac, u16 vlan_tag); | |
90898850 | 755 | int mlx4_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
9a9ebf8c LR |
756 | static inline int mlx4_ib_destroy_ah(struct ib_ah *ah, u32 flags) |
757 | { | |
758 | return 0; | |
759 | } | |
225c7b1f | 760 | |
68e326de LR |
761 | int mlx4_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, |
762 | struct ib_udata *udata); | |
225c7b1f RD |
763 | int mlx4_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, |
764 | enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); | |
65541cb7 | 765 | int mlx4_ib_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr); |
119181d1 | 766 | int mlx4_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); |
225c7b1f | 767 | void mlx4_ib_free_srq_wqe(struct mlx4_ib_srq *srq, int wqe_index); |
d34ac5cd BVA |
768 | int mlx4_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, |
769 | const struct ib_recv_wr **bad_wr); | |
225c7b1f RD |
770 | |
771 | struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, | |
772 | struct ib_qp_init_attr *init_attr, | |
773 | struct ib_udata *udata); | |
c4367a26 | 774 | int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); |
1975acd9 YH |
775 | void mlx4_ib_drain_sq(struct ib_qp *qp); |
776 | void mlx4_ib_drain_rq(struct ib_qp *qp); | |
225c7b1f RD |
777 | int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
778 | int attr_mask, struct ib_udata *udata); | |
6a775e2b JM |
779 | int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, |
780 | struct ib_qp_init_attr *qp_init_attr); | |
d34ac5cd BVA |
781 | int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
782 | const struct ib_send_wr **bad_wr); | |
783 | int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, | |
784 | const struct ib_recv_wr **bad_wr); | |
225c7b1f | 785 | |
0a9a0188 | 786 | int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, |
a97e2d86 IW |
787 | int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
788 | const void *in_mad, void *response_mad); | |
e26e7b88 | 789 | int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, |
a97e2d86 | 790 | const struct ib_wc *in_wc, const struct ib_grh *in_grh, |
e26e7b88 LR |
791 | const struct ib_mad *in, struct ib_mad *out, |
792 | size_t *out_mad_size, u16 *out_mad_pkey_index); | |
225c7b1f RD |
793 | int mlx4_ib_mad_init(struct mlx4_ib_dev *dev); |
794 | void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev); | |
795 | ||
0a9a0188 JM |
796 | int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port, |
797 | struct ib_port_attr *props, int netw_view); | |
798 | int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, | |
799 | u16 *pkey, int netw_view); | |
8ad11fb6 | 800 | |
a0c64a17 JM |
801 | int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index, |
802 | union ib_gid *gid, int netw_view); | |
803 | ||
a29bec12 | 804 | static inline bool mlx4_ib_ah_grh_present(struct mlx4_ib_ah *ah) |
225c7b1f | 805 | { |
fa417f7b EC |
806 | u8 port = be32_to_cpu(ah->av.ib.port_pd) >> 24 & 3; |
807 | ||
808 | if (rdma_port_get_link_layer(ah->ibah.device, port) == IB_LINK_LAYER_ETHERNET) | |
a29bec12 | 809 | return true; |
fa417f7b EC |
810 | |
811 | return !!(ah->av.ib.g_slid & 0x80); | |
225c7b1f RD |
812 | } |
813 | ||
b9c5d6a6 OD |
814 | int mlx4_ib_mcg_port_init(struct mlx4_ib_demux_ctx *ctx); |
815 | void mlx4_ib_mcg_port_cleanup(struct mlx4_ib_demux_ctx *ctx, int destroy_wq); | |
816 | void clean_vf_mcast(struct mlx4_ib_demux_ctx *ctx, int slave); | |
817 | int mlx4_ib_mcg_init(void); | |
818 | void mlx4_ib_mcg_destroy(void); | |
819 | ||
820 | int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid); | |
821 | ||
822 | int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port, int slave, | |
823 | struct ib_sa_mad *sa_mad); | |
824 | int mlx4_ib_mcg_demux_handler(struct ib_device *ibdev, int port, int slave, | |
825 | struct ib_sa_mad *mad); | |
826 | ||
fa417f7b EC |
827 | int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, |
828 | union ib_gid *gid); | |
829 | ||
00f5ce99 JM |
830 | void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num, |
831 | enum ib_event_type type); | |
832 | ||
fc06573d JM |
833 | void mlx4_ib_tunnels_update_work(struct work_struct *work); |
834 | ||
b9c5d6a6 OD |
835 | int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port, |
836 | enum ib_qp_type qpt, struct ib_wc *wc, | |
837 | struct ib_grh *grh, struct ib_mad *mad); | |
5ea8bbfc | 838 | |
b9c5d6a6 OD |
839 | int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port, |
840 | enum ib_qp_type dest_qpt, u16 pkey_index, u32 remote_qpn, | |
90898850 | 841 | u32 qkey, struct rdma_ah_attr *attr, u8 *s_mac, |
dbf727de | 842 | u16 vlan_id, struct ib_mad *mad); |
5ea8bbfc | 843 | |
b9c5d6a6 OD |
844 | __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx); |
845 | ||
3cf69cc8 AV |
846 | int mlx4_ib_demux_cm_handler(struct ib_device *ibdev, int port, int *slave, |
847 | struct ib_mad *mad); | |
848 | ||
849 | int mlx4_ib_multiplex_cm_handler(struct ib_device *ibdev, int port, int slave_id, | |
850 | struct ib_mad *mad); | |
851 | ||
852 | void mlx4_ib_cm_paravirt_init(struct mlx4_ib_dev *dev); | |
853 | void mlx4_ib_cm_paravirt_clean(struct mlx4_ib_dev *dev, int slave_id); | |
854 | ||
a0c64a17 JM |
855 | /* alias guid support */ |
856 | void mlx4_ib_init_alias_guid_work(struct mlx4_ib_dev *dev, int port); | |
857 | int mlx4_ib_init_alias_guid_service(struct mlx4_ib_dev *dev); | |
858 | void mlx4_ib_destroy_alias_guid_service(struct mlx4_ib_dev *dev); | |
859 | void mlx4_ib_invalidate_all_guid_record(struct mlx4_ib_dev *dev, int port); | |
860 | ||
861 | void mlx4_ib_notify_slaves_on_guid_change(struct mlx4_ib_dev *dev, | |
862 | int block_num, | |
863 | u8 port_num, u8 *p_data); | |
864 | ||
865 | void mlx4_ib_update_cache_on_guid_change(struct mlx4_ib_dev *dev, | |
866 | int block_num, u8 port_num, | |
867 | u8 *p_data); | |
868 | ||
c1e7e466 JM |
869 | int add_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, |
870 | struct attribute *attr); | |
871 | void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, | |
872 | struct attribute *attr); | |
873 | ib_sa_comp_mask mlx4_ib_get_aguid_comp_mask_from_ix(int index); | |
ee59fa0d YH |
874 | void mlx4_ib_slave_alias_guid_event(struct mlx4_ib_dev *dev, int slave, |
875 | int port, int slave_init); | |
c1e7e466 JM |
876 | |
877 | int mlx4_ib_device_register_sysfs(struct mlx4_ib_dev *device) ; | |
878 | ||
879 | void mlx4_ib_device_unregister_sysfs(struct mlx4_ib_dev *device); | |
880 | ||
afa8fd1d JM |
881 | __be64 mlx4_ib_gen_node_guid(void); |
882 | ||
c1c98501 MB |
883 | int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn); |
884 | void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count); | |
885 | int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp, | |
886 | int is_attach); | |
9376932d MB |
887 | int mlx4_ib_rereg_user_mr(struct ib_mr *mr, int flags, |
888 | u64 start, u64 length, u64 virt_addr, | |
889 | int mr_access_flags, struct ib_pd *pd, | |
890 | struct ib_udata *udata); | |
e26be1bf | 891 | int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev, |
7492052a | 892 | const struct ib_gid_attr *attr); |
afa8fd1d | 893 | |
fd10ed8e JM |
894 | void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev, |
895 | int port); | |
896 | ||
897 | void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port); | |
898 | ||
400b1ebc GL |
899 | struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd, |
900 | struct ib_wq_init_attr *init_attr, | |
901 | struct ib_udata *udata); | |
a49b1dc7 | 902 | void mlx4_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); |
400b1ebc GL |
903 | int mlx4_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, |
904 | u32 wq_attr_mask, struct ib_udata *udata); | |
905 | ||
b8d46ca0 GL |
906 | struct ib_rwq_ind_table |
907 | *mlx4_ib_create_rwq_ind_table(struct ib_device *device, | |
908 | struct ib_rwq_ind_table_init_attr *init_attr, | |
909 | struct ib_udata *udata); | |
910 | int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); | |
ed8637d3 GL |
911 | int mlx4_ib_umem_calc_optimal_mtt_size(struct ib_umem *umem, u64 start_va, |
912 | int *num_of_mtts); | |
b8d46ca0 | 913 | |
225c7b1f | 914 | #endif /* MLX4_IB_H */ |