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IB/cache: Add ib_find_gid_by_filter cache API
[linux-2.6-block.git] / drivers / infiniband / hw / mlx4 / mad.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <rdma/ib_mad.h>
34#include <rdma/ib_smi.h>
37bfc7c1
JM		 35#include <rdma/ib_sa.h>
36#include <rdma/ib_cache.h>
225c7b1f 37
afa8fd1d 38#include <linux/random.h>
225c7b1f 39#include <linux/mlx4/cmd.h>
5a0e3ad6 40#include <linux/gfp.h>
c3779134 41#include <rdma/ib_pma.h>
225c7b1f
RD		 42
43#include "mlx4_ib.h"
44
45enum {
46 MLX4_IB_VENDOR_CLASS1 = 0x9,
47 MLX4_IB_VENDOR_CLASS2 = 0xa
48};
49
fc06573d
JM		 50#define MLX4_TUN_SEND_WRID_SHIFT 34
51#define MLX4_TUN_QPN_SHIFT 32
52#define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT)
53#define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT)
54
55#define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1)
56#define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3)
57
2a4fae14
JM		 58 /* Port mgmt change event handling */
59
60#define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr)
61#define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask)
62#define NUM_IDX_IN_PKEY_TBL_BLK 32
63#define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */
64#define GUID_TBL_BLK_NUM_ENTRIES 8
65#define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES)
66
fc06573d
JM		 67struct mlx4_mad_rcv_buf {
68 struct ib_grh grh;
69 u8 payload[256];
70} __packed;
71
72struct mlx4_mad_snd_buf {
73 u8 payload[256];
74} __packed;
75
76struct mlx4_tunnel_mad {
77 struct ib_grh grh;
78 struct mlx4_ib_tunnel_header hdr;
79 struct ib_mad mad;
80} __packed;
81
82struct mlx4_rcv_tunnel_mad {
83 struct mlx4_rcv_tunnel_hdr hdr;
84 struct ib_grh grh;
85 struct ib_mad mad;
86} __packed;
87
b9c5d6a6 88static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num);
2a4fae14
JM		 89static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num);
90static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
91 int block, u32 change_bitmap);
b9c5d6a6 92
afa8fd1d
JM		 93__be64 mlx4_ib_gen_node_guid(void)
94{
95#define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40))
50bea5c0 96 return cpu_to_be64(NODE_GUID_HI | prandom_u32());
afa8fd1d
JM		 97}
98
b9c5d6a6
OD		 99__be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx)
100{
101 return cpu_to_be64(atomic_inc_return(&ctx->tid)) |
102 cpu_to_be64(0xff00000000000000LL);
103}
104
0a9a0188 105int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
a97e2d86
IW		 106 int port, const struct ib_wc *in_wc,
107 const struct ib_grh *in_grh,
108 const void *in_mad, void *response_mad)
225c7b1f
RD		 109{
110 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
111 void *inbox;
112 int err;
113 u32 in_modifier = port;
114 u8 op_modifier = 0;
115
116 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
117 if (IS_ERR(inmailbox))
118 return PTR_ERR(inmailbox);
119 inbox = inmailbox->buf;
120
121 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
122 if (IS_ERR(outmailbox)) {
123 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
124 return PTR_ERR(outmailbox);
125 }
126
127 memcpy(inbox, in_mad, 256);
128
129 /*
130 * Key check traps can't be generated unless we have in_wc to
131 * tell us where to send the trap.
132 */
0a9a0188 133 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc)
225c7b1f 134 op_modifier |= 0x1;
0a9a0188 135 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc)
225c7b1f 136 op_modifier |= 0x2;
0a9a0188
JM		 137 if (mlx4_is_mfunc(dev->dev) &&
138 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc))
139 op_modifier |= 0x8;
225c7b1f
RD		 140
141 if (in_wc) {
142 struct {
143 __be32 my_qpn;
144 u32 reserved1;
145 __be32 rqpn;
146 u8 sl;
147 u8 g_path;
148 u16 reserved2[2];
149 __be16 pkey;
150 u32 reserved3[11];
151 u8 grh[40];
152 } *ext_info;
153
154 memset(inbox + 256, 0, 256);
155 ext_info = inbox + 256;
156
157 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num);
158 ext_info->rqpn = cpu_to_be32(in_wc->src_qp);
159 ext_info->sl = in_wc->sl << 4;
160 ext_info->g_path = in_wc->dlid_path_bits |
161 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
162 ext_info->pkey = cpu_to_be16(in_wc->pkey_index);
163
164 if (in_grh)
165 memcpy(ext_info->grh, in_grh, 40);
166
167 op_modifier |= 0x4;
168
169 in_modifier |= in_wc->slid << 16;
170 }
171
0a9a0188
JM		 172 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier,
173 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier,
f9baff50 174 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
0a9a0188 175 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED);
225c7b1f 176
fe11cb6b 177 if (!err)
225c7b1f
RD		 178 memcpy(response_mad, outmailbox->buf, 256);
179
180 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
181 mlx4_free_cmd_mailbox(dev->dev, outmailbox);
182
183 return err;
184}
185
186static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl)
187{
188 struct ib_ah *new_ah;
189 struct ib_ah_attr ah_attr;
df7fba66 190 unsigned long flags;
225c7b1f
RD		 191
192 if (!dev->send_agent[port_num - 1][0])
193 return;
194
195 memset(&ah_attr, 0, sizeof ah_attr);
196 ah_attr.dlid = lid;
197 ah_attr.sl = sl;
198 ah_attr.port_num = port_num;
199
200 new_ah = ib_create_ah(dev->send_agent[port_num - 1][0]->qp->pd,
201 &ah_attr);
202 if (IS_ERR(new_ah))
203 return;
204
df7fba66 205 spin_lock_irqsave(&dev->sm_lock, flags);
225c7b1f
RD		 206 if (dev->sm_ah[port_num - 1])
207 ib_destroy_ah(dev->sm_ah[port_num - 1]);
208 dev->sm_ah[port_num - 1] = new_ah;
df7fba66 209 spin_unlock_irqrestore(&dev->sm_lock, flags);
225c7b1f
RD		 210}
211
212/*
00f5ce99
JM		 213 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can
214 * synthesize LID change, Client-Rereg, GID change, and P_Key change events.
225c7b1f 215 */
a97e2d86 216static void smp_snoop(struct ib_device *ibdev, u8 port_num, const struct ib_mad *mad,
00f5ce99 217 u16 prev_lid)
225c7b1f 218{
00f5ce99
JM		 219 struct ib_port_info *pinfo;
220 u16 lid;
54679e14
JM		 221 __be16 *base;
222 u32 bn, pkey_change_bitmap;
223 int i;
224
225c7b1f 225
00f5ce99 226 struct mlx4_ib_dev *dev = to_mdev(ibdev);
225c7b1f
RD		 227 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
228 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
00f5ce99
JM		 229 mad->mad_hdr.method == IB_MGMT_METHOD_SET)
230 switch (mad->mad_hdr.attr_id) {
231 case IB_SMP_ATTR_PORT_INFO:
232 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data;
233 lid = be16_to_cpu(pinfo->lid);
225c7b1f 234
00f5ce99 235 update_sm_ah(dev, port_num,
225c7b1f
RD		 236 be16_to_cpu(pinfo->sm_lid),
237 pinfo->neighbormtu_mastersmsl & 0xf);
238
00f5ce99 239 if (pinfo->clientrereg_resv_subnetto & 0x80)
b9c5d6a6 240 handle_client_rereg_event(dev, port_num);
225c7b1f 241
00f5ce99 242 if (prev_lid != lid)
2a4fae14 243 handle_lid_change_event(dev, port_num);
00f5ce99 244 break;
225c7b1f 245
00f5ce99 246 case IB_SMP_ATTR_PKEY_TABLE:
54679e14
JM		 247 if (!mlx4_is_mfunc(dev->dev)) {
248 mlx4_ib_dispatch_event(dev, port_num,
249 IB_EVENT_PKEY_CHANGE);
250 break;
251 }
252
2a4fae14
JM		 253 /* at this point, we are running in the master.
254 * Slaves do not receive SMPs.
255 */
54679e14
JM		 256 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF;
257 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]);
258 pkey_change_bitmap = 0;
259 for (i = 0; i < 32; i++) {
260 pr_debug("PKEY[%d] = x%x\n",
261 i + bn*32, be16_to_cpu(base[i]));
262 if (be16_to_cpu(base[i]) !=
263 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) {
264 pkey_change_bitmap |= (1 << i);
265 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] =
266 be16_to_cpu(base[i]);
267 }
268 }
269 pr_debug("PKEY Change event: port=%d, "
270 "block=0x%x, change_bitmap=0x%x\n",
271 port_num, bn, pkey_change_bitmap);
272
2a4fae14 273 if (pkey_change_bitmap) {
54679e14
JM		 274 mlx4_ib_dispatch_event(dev, port_num,
275 IB_EVENT_PKEY_CHANGE);
2a4fae14
JM		 276 if (!dev->sriov.is_going_down)
277 __propagate_pkey_ev(dev, port_num, bn,
278 pkey_change_bitmap);
279 }
00f5ce99 280 break;
225c7b1f 281
00f5ce99 282 case IB_SMP_ATTR_GUID_INFO:
6634961c
JM		 283 /* paravirtualized master's guid is guid 0 -- does not change */
284 if (!mlx4_is_master(dev->dev))
285 mlx4_ib_dispatch_event(dev, port_num,
286 IB_EVENT_GID_CHANGE);
2a4fae14
JM		 287 /*if master, notify relevant slaves*/
288 if (mlx4_is_master(dev->dev) &&
289 !dev->sriov.is_going_down) {
290 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod);
291 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num,
292 (u8 *)(&((struct ib_smp *)mad)->data));
293 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num,
294 (u8 *)(&((struct ib_smp *)mad)->data));
295 }
00f5ce99 296 break;
2a4fae14 297
00f5ce99
JM		 298 default:
299 break;
225c7b1f 300 }
225c7b1f
RD		 301}
302
2a4fae14
JM		 303static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
304 int block, u32 change_bitmap)
305{
306 int i, ix, slave, err;
307 int have_event = 0;
308
309 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) {
310 if (slave == mlx4_master_func_num(dev->dev))
311 continue;
312 if (!mlx4_is_slave_active(dev->dev, slave))
313 continue;
314
315 have_event = 0;
316 for (i = 0; i < 32; i++) {
317 if (!(change_bitmap & (1 << i)))
318 continue;
319 for (ix = 0;
320 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) {
321 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1]
322 [ix] == i + 32 * block) {
323 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num);
324 pr_debug("propagate_pkey_ev: slave %d,"
325 " port %d, ix %d (%d)\n",
326 slave, port_num, ix, err);
327 have_event = 1;
328 break;
329 }
330 }
331 if (have_event)
332 break;
333 }
334 }
335}
336
225c7b1f
RD		 337static void node_desc_override(struct ib_device *dev,
338 struct ib_mad *mad)
339{
df7fba66
JM		 340 unsigned long flags;
341
225c7b1f
RD		 342 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
343 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
344 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP &&
345 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) {
df7fba66 346 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags);
225c7b1f 347 memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 64);
df7fba66 348 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags);
225c7b1f
RD		 349 }
350}
351
a97e2d86 352static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, const struct ib_mad *mad)
225c7b1f
RD		 353{
354 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED;
355 struct ib_mad_send_buf *send_buf;
356 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn];
357 int ret;
df7fba66 358 unsigned long flags;
225c7b1f
RD		 359
360 if (agent) {
361 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
da2dfaa3
IW		 362 IB_MGMT_MAD_DATA, GFP_ATOMIC,
363 IB_MGMT_BASE_VERSION);
13974909
DC		 364 if (IS_ERR(send_buf))
365 return;
225c7b1f
RD		 366 /*
367 * We rely here on the fact that MLX QPs don't use the
368 * address handle after the send is posted (this is
369 * wrong following the IB spec strictly, but we know
370 * it's OK for our devices).
371 */
df7fba66 372 spin_lock_irqsave(&dev->sm_lock, flags);
225c7b1f
RD		 373 memcpy(send_buf->mad, mad, sizeof *mad);
374 if ((send_buf->ah = dev->sm_ah[port_num - 1]))
375 ret = ib_post_send_mad(send_buf, NULL);
376 else
377 ret = -EINVAL;
df7fba66 378 spin_unlock_irqrestore(&dev->sm_lock, flags);
225c7b1f
RD		 379
380 if (ret)
381 ib_free_send_mad(send_buf);
382 }
383}
384
37bfc7c1
JM		 385static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave,
386 struct ib_sa_mad *sa_mad)
387{
b9c5d6a6
OD		 388 int ret = 0;
389
390 /* dispatch to different sa handlers */
391 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
392 case IB_SA_ATTR_MC_MEMBER_REC:
393 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad);
394 break;
395 default:
396 break;
397 }
398 return ret;
37bfc7c1
JM		 399}
400
401int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid)
402{
403 struct mlx4_ib_dev *dev = to_mdev(ibdev);
404 int i;
405
406 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
407 if (dev->sriov.demux[port - 1].guid_cache[i] == guid)
408 return i;
409 }
410 return -1;
411}
412
413
2c75d2cc
JM		 414static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave,
415 u8 port, u16 pkey, u16 *ix)
37bfc7c1 416{
2c75d2cc
JM		 417 int i, ret;
418 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF;
419 u16 slot_pkey;
37bfc7c1 420
2c75d2cc
JM		 421 if (slave == mlx4_master_func_num(dev->dev))
422 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix);
37bfc7c1 423
2c75d2cc 424 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1;
37bfc7c1 425
2c75d2cc
JM		 426 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) {
427 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix)
428 continue;
429
430 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i];
431
432 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey);
433 if (ret)
434 continue;
435 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) {
436 if (slot_pkey & 0x8000) {
437 *ix = (u16) pkey_ix;
438 return 0;
439 } else {
440 /* take first partial pkey index found */
441 if (partial_ix == 0xFF)
442 partial_ix = pkey_ix;
443 }
444 }
445 }
446
447 if (partial_ix < 0xFF) {
448 *ix = (u16) partial_ix;
449 return 0;
450 }
451
452 return -EINVAL;
37bfc7c1
JM		 453}
454
455int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
456 enum ib_qp_type dest_qpt, struct ib_wc *wc,
457 struct ib_grh *grh, struct ib_mad *mad)
458{
459 struct ib_sge list;
460 struct ib_send_wr wr, *bad_wr;
461 struct mlx4_ib_demux_pv_ctx *tun_ctx;
462 struct mlx4_ib_demux_pv_qp *tun_qp;
463 struct mlx4_rcv_tunnel_mad *tun_mad;
464 struct ib_ah_attr attr;
465 struct ib_ah *ah;
466 struct ib_qp *src_qp = NULL;
467 unsigned tun_tx_ix = 0;
468 int dqpn;
469 int ret = 0;
37bfc7c1 470 u16 tun_pkey_ix;
2c75d2cc 471 u16 cached_pkey;
6ee51a4e 472 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
37bfc7c1
JM		 473
474 if (dest_qpt > IB_QPT_GSI)
475 return -EINVAL;
476
477 tun_ctx = dev->sriov.demux[port-1].tun[slave];
478
479 /* check if proxy qp created */
480 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE)
481 return -EAGAIN;
482
37bfc7c1
JM		 483 if (!dest_qpt)
484 tun_qp = &tun_ctx->qp[0];
485 else
486 tun_qp = &tun_ctx->qp[1];
487
2c75d2cc 488 /* compute P_Key index to put in tunnel header for slave */
37bfc7c1 489 if (dest_qpt) {
2c75d2cc
JM		 490 u16 pkey_ix;
491 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey);
37bfc7c1
JM		 492 if (ret)
493 return -EINVAL;
494
2c75d2cc
JM		 495 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix);
496 if (ret)
37bfc7c1 497 return -EINVAL;
2c75d2cc 498 tun_pkey_ix = pkey_ix;
37bfc7c1
JM		 499 } else
500 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
501
47605df9 502 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1;
37bfc7c1
JM		 503
504 /* get tunnel tx data buf for slave */
505 src_qp = tun_qp->qp;
506
507 /* create ah. Just need an empty one with the port num for the post send.
508 * The driver will set the force loopback bit in post_send */
509 memset(&attr, 0, sizeof attr);
510 attr.port_num = port;
6ee51a4e 511 if (is_eth) {
b6ffaeff 512 memcpy(&attr.grh.dgid.raw[0], &grh->dgid.raw[0], 16);
6ee51a4e
JM		 513 attr.ah_flags = IB_AH_GRH;
514 }
37bfc7c1
JM		 515 ah = ib_create_ah(tun_ctx->pd, &attr);
516 if (IS_ERR(ah))
517 return -ENOMEM;
518
519 /* allocate tunnel tx buf after pass failure returns */
520 spin_lock(&tun_qp->tx_lock);
521 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >=
522 (MLX4_NUM_TUNNEL_BUFS - 1))
523 ret = -EAGAIN;
524 else
525 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
526 spin_unlock(&tun_qp->tx_lock);
527 if (ret)
528 goto out;
529
530 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr);
531 if (tun_qp->tx_ring[tun_tx_ix].ah)
532 ib_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah);
533 tun_qp->tx_ring[tun_tx_ix].ah = ah;
534 ib_dma_sync_single_for_cpu(&dev->ib_dev,
535 tun_qp->tx_ring[tun_tx_ix].buf.map,
536 sizeof (struct mlx4_rcv_tunnel_mad),
537 DMA_TO_DEVICE);
538
539 /* copy over to tunnel buffer */
540 if (grh)
541 memcpy(&tun_mad->grh, grh, sizeof *grh);
542 memcpy(&tun_mad->mad, mad, sizeof *mad);
543
544 /* adjust tunnel data */
545 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix);
37bfc7c1
JM		 546 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF);
547 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0;
548
5ea8bbfc
JM		 549 if (is_eth) {
550 u16 vlan = 0;
551 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan,
552 NULL)) {
553 /* VST mode */
554 if (vlan != wc->vlan_id)
555 /* Packet vlan is not the VST-assigned vlan.
556 * Drop the packet.
557 */
558 goto out;
559 else
560 /* Remove the vlan tag before forwarding
561 * the packet to the VF.
562 */
563 vlan = 0xffff;
564 } else {
565 vlan = wc->vlan_id;
566 }
567
568 tun_mad->hdr.sl_vid = cpu_to_be16(vlan);
569 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4);
570 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2);
571 } else {
572 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12);
573 tun_mad->hdr.slid_mac_47_32 = cpu_to_be16(wc->slid);
574 }
575
37bfc7c1
JM		 576 ib_dma_sync_single_for_device(&dev->ib_dev,
577 tun_qp->tx_ring[tun_tx_ix].buf.map,
578 sizeof (struct mlx4_rcv_tunnel_mad),
579 DMA_TO_DEVICE);
580
581 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map;
582 list.length = sizeof (struct mlx4_rcv_tunnel_mad);
7dd97576 583 list.lkey = tun_ctx->pd->local_dma_lkey;
37bfc7c1
JM		 584
585 wr.wr.ud.ah = ah;
586 wr.wr.ud.port_num = port;
587 wr.wr.ud.remote_qkey = IB_QP_SET_QKEY;
588 wr.wr.ud.remote_qpn = dqpn;
589 wr.next = NULL;
590 wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt);
591 wr.sg_list = &list;
592 wr.num_sge = 1;
593 wr.opcode = IB_WR_SEND;
594 wr.send_flags = IB_SEND_SIGNALED;
595
596 ret = ib_post_send(src_qp, &wr, &bad_wr);
597out:
598 if (ret)
599 ib_destroy_ah(ah);
600 return ret;
601}
602
603static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
604 struct ib_wc *wc, struct ib_grh *grh,
605 struct ib_mad *mad)
606{
607 struct mlx4_ib_dev *dev = to_mdev(ibdev);
608 int err;
609 int slave;
610 u8 *slave_id;
6ee51a4e
JM		 611 int is_eth = 0;
612
613 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
614 is_eth = 0;
615 else
616 is_eth = 1;
617
618 if (is_eth) {
619 if (!(wc->wc_flags & IB_WC_GRH)) {
620 mlx4_ib_warn(ibdev, "RoCE grh not present.\n");
621 return -EINVAL;
622 }
623 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) {
624 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n");
625 return -EINVAL;
626 }
627 if (mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave)) {
628 mlx4_ib_warn(ibdev, "failed matching grh\n");
629 return -ENOENT;
630 }
631 if (slave >= dev->dev->caps.sqp_demux) {
632 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
633 slave, dev->dev->caps.sqp_demux);
634 return -ENOENT;
635 }
636
637 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad))
638 return 0;
639
640 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
641 if (err)
642 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
643 slave, err);
644 return 0;
645 }
37bfc7c1
JM		 646
647 /* Initially assume that this mad is for us */
648 slave = mlx4_master_func_num(dev->dev);
649
650 /* See if the slave id is encoded in a response mad */
651 if (mad->mad_hdr.method & 0x80) {
652 slave_id = (u8 *) &mad->mad_hdr.tid;
653 slave = *slave_id;
654 if (slave != 255) /*255 indicates the dom0*/
655 *slave_id = 0; /* remap tid */
656 }
657
658 /* If a grh is present, we demux according to it */
659 if (wc->wc_flags & IB_WC_GRH) {
660 slave = mlx4_ib_find_real_gid(ibdev, port, grh->dgid.global.interface_id);
661 if (slave < 0) {
662 mlx4_ib_warn(ibdev, "failed matching grh\n");
663 return -ENOENT;
664 }
665 }
666 /* Class-specific handling */
667 switch (mad->mad_hdr.mgmt_class) {
97982f5a
JM		 668 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
669 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
670 /* 255 indicates the dom0 */
671 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) {
672 if (!mlx4_vf_smi_enabled(dev->dev, slave, port))
673 return -EPERM;
674 /* for a VF. drop unsolicited MADs */
675 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) {
676 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n",
677 slave, mad->mad_hdr.mgmt_class,
678 mad->mad_hdr.method);
679 return -EINVAL;
680 }
681 }
682 break;
37bfc7c1
JM		 683 case IB_MGMT_CLASS_SUBN_ADM:
684 if (mlx4_ib_demux_sa_handler(ibdev, port, slave,
685 (struct ib_sa_mad *) mad))
686 return 0;
687 break;
3cf69cc8
AV		 688 case IB_MGMT_CLASS_CM:
689 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad))
690 return 0;
691 break;
37bfc7c1
JM		 692 case IB_MGMT_CLASS_DEVICE_MGMT:
693 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP)
694 return 0;
695 break;
696 default:
697 /* Drop unsupported classes for slaves in tunnel mode */
698 if (slave != mlx4_master_func_num(dev->dev)) {
699 pr_debug("dropping unsupported ingress mad from class:%d "
700 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave);
701 return 0;
702 }
703 }
704 /*make sure that no slave==255 was not handled yet.*/
705 if (slave >= dev->dev->caps.sqp_demux) {
706 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
707 slave, dev->dev->caps.sqp_demux);
708 return -ENOENT;
709 }
710
711 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
712 if (err)
713 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
714 slave, err);
715 return 0;
716}
717
c3779134 718static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86
IW		 719 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
720 const struct ib_mad *in_mad, struct ib_mad *out_mad)
225c7b1f 721{
f0f6f346 722 u16 slid, prev_lid = 0;
225c7b1f 723 int err;
f0f6f346 724 struct ib_port_attr pattr;
225c7b1f 725
b1d8eb5a
JM		 726 if (in_wc && in_wc->qp->qp_num) {
727 pr_debug("received MAD: slid:%d sqpn:%d "
728 "dlid_bits:%d dqpn:%d wc_flags:0x%x, cls %x, mtd %x, atr %x\n",
729 in_wc->slid, in_wc->src_qp,
730 in_wc->dlid_path_bits,
731 in_wc->qp->qp_num,
732 in_wc->wc_flags,
733 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method,
734 be16_to_cpu(in_mad->mad_hdr.attr_id));
735 if (in_wc->wc_flags & IB_WC_GRH) {
736 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n",
737 be64_to_cpu(in_grh->sgid.global.subnet_prefix),
738 be64_to_cpu(in_grh->sgid.global.interface_id));
739 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n",
740 be64_to_cpu(in_grh->dgid.global.subnet_prefix),
741 be64_to_cpu(in_grh->dgid.global.interface_id));
742 }
743 }
744
225c7b1f
RD		 745 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE);
746
747 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) {
748 forward_trap(to_mdev(ibdev), port_num, in_mad);
749 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
750 }
751
752 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
753 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
754 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
755 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET &&
756 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS)
757 return IB_MAD_RESULT_SUCCESS;
758
759 /*
a6f7feae 760 * Don't process SMInfo queries -- the SMA can't handle them.
225c7b1f 761 */
a6f7feae 762 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO)
225c7b1f
RD		 763 return IB_MAD_RESULT_SUCCESS;
764 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT ||
765 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 ||
6578cf33
EC		 766 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 ||
767 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) {
225c7b1f
RD		 768 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
769 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET)
770 return IB_MAD_RESULT_SUCCESS;
771 } else
772 return IB_MAD_RESULT_SUCCESS;
773
f0f6f346
MS		 774 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
775 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
776 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET &&
777 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO &&
778 !ib_query_port(ibdev, port_num, &pattr))
779 prev_lid = pattr.lid;
780
225c7b1f 781 err = mlx4_MAD_IFC(to_mdev(ibdev),
0a9a0188
JM		 782 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) |
783 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) |
784 MLX4_MAD_IFC_NET_VIEW,
225c7b1f
RD		 785 port_num, in_wc, in_grh, in_mad, out_mad);
786 if (err)
787 return IB_MAD_RESULT_FAILURE;
788
789 if (!out_mad->mad_hdr.status) {
00f5ce99
JM		 790 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV))
791 smp_snoop(ibdev, port_num, in_mad, prev_lid);
992e8e6e
JM		 792 /* slaves get node desc from FW */
793 if (!mlx4_is_slave(to_mdev(ibdev)->dev))
794 node_desc_override(ibdev, out_mad);
225c7b1f
RD		 795 }
796
797 /* set return bit in status of directed route responses */
798 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
799 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15);
800
801 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS)
802 /* no response for trap repress */
803 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
804
805 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
806}
807
c3779134
OG		 808static void edit_counter(struct mlx4_counter *cnt,
809 struct ib_pma_portcounters *pma_cnt)
810{
61a3855b
MD		 811 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data,
812 (be64_to_cpu(cnt->tx_bytes) >> 2));
813 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data,
814 (be64_to_cpu(cnt->rx_bytes) >> 2));
815 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets,
816 be64_to_cpu(cnt->tx_frames));
817 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets,
818 be64_to_cpu(cnt->rx_frames));
c3779134
OG		 819}
820
821static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86
IW		 822 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
823 const struct ib_mad *in_mad, struct ib_mad *out_mad)
c3779134 824{
9616982f 825 struct mlx4_counter counter_stats;
c3779134 826 struct mlx4_ib_dev *dev = to_mdev(ibdev);
3ba8e31d
EBE		 827 struct counter_index *tmp_counter;
828 int err = IB_MAD_RESULT_FAILURE, stats_avail = 0;
c3779134
OG		 829
830 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT)
831 return -EINVAL;
832
9616982f 833 memset(&counter_stats, 0, sizeof(counter_stats));
3ba8e31d
EBE		 834 mutex_lock(&dev->counters_table[port_num - 1].mutex);
835 list_for_each_entry(tmp_counter,
836 &dev->counters_table[port_num - 1].counters_list,
837 list) {
838 err = mlx4_get_counter_stats(dev->dev,
839 tmp_counter->index,
840 &counter_stats, 0);
841 if (err) {
842 err = IB_MAD_RESULT_FAILURE;
843 stats_avail = 0;
844 break;
845 }
846 stats_avail = 1;
847 }
848 mutex_unlock(&dev->counters_table[port_num - 1].mutex);
849 if (stats_avail) {
c3779134 850 memset(out_mad->data, 0, sizeof out_mad->data);
9616982f 851 switch (counter_stats.counter_mode & 0xf) {
c3779134 852 case 0:
9616982f
EBE		 853 edit_counter(&counter_stats,
854 (void *)(out_mad->data + 40));
c3779134
OG		 855 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
856 break;
857 default:
858 err = IB_MAD_RESULT_FAILURE;
859 }
860 }
861
c3779134
OG		 862 return err;
863}
864
865int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
a97e2d86 866 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
4cd7c947
IW		 867 const struct ib_mad_hdr *in, size_t in_mad_size,
868 struct ib_mad_hdr *out, size_t *out_mad_size,
869 u16 *out_mad_pkey_index)
c3779134 870{
7193a141 871 struct mlx4_ib_dev *dev = to_mdev(ibdev);
4cd7c947
IW		 872 const struct ib_mad *in_mad = (const struct ib_mad *)in;
873 struct ib_mad *out_mad = (struct ib_mad *)out;
43bfb972 874 enum rdma_link_layer link = rdma_port_get_link_layer(ibdev, port_num);
4cd7c947 875
3b8ab700
IW		 876 if (WARN_ON_ONCE(in_mad_size != sizeof(*in_mad) ||
877 *out_mad_size != sizeof(*out_mad)))
878 return IB_MAD_RESULT_FAILURE;
4cd7c947 879
43bfb972
OG		 880 /* iboe_process_mad() which uses the HCA flow-counters to implement IB PMA
881 * queries, should be called only by VFs and for that specific purpose
882 */
883 if (link == IB_LINK_LAYER_INFINIBAND) {
884 if (mlx4_is_slave(dev->dev) &&
885 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT &&
886 in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS)
887 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
888 in_grh, in_mad, out_mad);
889
890 return ib_process_mad(ibdev, mad_flags, port_num, in_wc,
891 in_grh, in_mad, out_mad);
c3779134 892 }
43bfb972
OG		 893
894 if (link == IB_LINK_LAYER_ETHERNET)
895 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
896 in_grh, in_mad, out_mad);
897
898 return -EINVAL;
c3779134
OG		 899}
900
225c7b1f
RD		 901static void send_handler(struct ib_mad_agent *agent,
902 struct ib_mad_send_wc *mad_send_wc)
903{
992e8e6e
JM		 904 if (mad_send_wc->send_buf->context[0])
905 ib_destroy_ah(mad_send_wc->send_buf->context[0]);
225c7b1f
RD		 906 ib_free_send_mad(mad_send_wc->send_buf);
907}
908
909int mlx4_ib_mad_init(struct mlx4_ib_dev *dev)
910{
911 struct ib_mad_agent *agent;
912 int p, q;
913 int ret;
fa417f7b 914 enum rdma_link_layer ll;
225c7b1f 915
fa417f7b
EC		 916 for (p = 0; p < dev->num_ports; ++p) {
917 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1);
225c7b1f 918 for (q = 0; q <= 1; ++q) {
fa417f7b
EC		 919 if (ll == IB_LINK_LAYER_INFINIBAND) {
920 agent = ib_register_mad_agent(&dev->ib_dev, p + 1,
921 q ? IB_QPT_GSI : IB_QPT_SMI,
922 NULL, 0, send_handler,
0f29b46d 923 NULL, NULL, 0);
fa417f7b
EC		 924 if (IS_ERR(agent)) {
925 ret = PTR_ERR(agent);
926 goto err;
927 }
928 dev->send_agent[p][q] = agent;
929 } else
930 dev->send_agent[p][q] = NULL;
225c7b1f 931 }
fa417f7b 932 }
225c7b1f
RD		 933
934 return 0;
935
936err:
7ff93f8b 937 for (p = 0; p < dev->num_ports; ++p)
225c7b1f
RD		 938 for (q = 0; q <= 1; ++q)
939 if (dev->send_agent[p][q])
940 ib_unregister_mad_agent(dev->send_agent[p][q]);
941
942 return ret;
943}
944
945void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev)
946{
947 struct ib_mad_agent *agent;
948 int p, q;
949
7ff93f8b 950 for (p = 0; p < dev->num_ports; ++p) {
225c7b1f
RD		 951 for (q = 0; q <= 1; ++q) {
952 agent = dev->send_agent[p][q];
fa417f7b
EC		 953 if (agent) {
954 dev->send_agent[p][q] = NULL;
955 ib_unregister_mad_agent(agent);
956 }
225c7b1f
RD		 957 }
958
959 if (dev->sm_ah[p])
960 ib_destroy_ah(dev->sm_ah[p]);
961 }
962}
00f5ce99 963
2a4fae14
JM		 964static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num)
965{
966 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE);
967
968 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
969 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
970 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK);
971}
972
b9c5d6a6
OD		 973static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num)
974{
a0c64a17 975 /* re-configure the alias-guid and mcg's */
b9c5d6a6 976 if (mlx4_is_master(dev->dev)) {
a0c64a17
JM		 977 mlx4_ib_invalidate_all_guid_record(dev, port_num);
978
2a4fae14 979 if (!dev->sriov.is_going_down) {
b9c5d6a6 980 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0);
2a4fae14
JM		 981 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
982 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK);
983 }
b9c5d6a6
OD		 984 }
985 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER);
986}
987
2a4fae14
JM		 988static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
989 struct mlx4_eqe *eqe)
990{
991 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe),
992 GET_MASK_FROM_EQE(eqe));
993}
994
995static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num,
996 u32 guid_tbl_blk_num, u32 change_bitmap)
997{
998 struct ib_smp *in_mad = NULL;
999 struct ib_smp *out_mad = NULL;
1000 u16 i;
1001
1002 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev))
1003 return;
1004
1005 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL);
1006 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1007 if (!in_mad || !out_mad) {
1008 mlx4_ib_warn(&dev->ib_dev, "failed to allocate memory for guid info mads\n");
1009 goto out;
1010 }
1011
1012 guid_tbl_blk_num *= 4;
1013
1014 for (i = 0; i < 4; i++) {
1015 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff)))
1016 continue;
1017 memset(in_mad, 0, sizeof *in_mad);
1018 memset(out_mad, 0, sizeof *out_mad);
1019
1020 in_mad->base_version = 1;
1021 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1022 in_mad->class_version = 1;
1023 in_mad->method = IB_MGMT_METHOD_GET;
1024 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
1025 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i);
1026
1027 if (mlx4_MAD_IFC(dev,
1028 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW,
1029 port_num, NULL, NULL, in_mad, out_mad)) {
1030 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n");
1031 goto out;
1032 }
1033
1034 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i,
1035 port_num,
1036 (u8 *)(&((struct ib_smp *)out_mad)->data));
1037 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i,
1038 port_num,
1039 (u8 *)(&((struct ib_smp *)out_mad)->data));
1040 }
1041
1042out:
1043 kfree(in_mad);
1044 kfree(out_mad);
1045 return;
1046}
1047
00f5ce99
JM		 1048void handle_port_mgmt_change_event(struct work_struct *work)
1049{
1050 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
1051 struct mlx4_ib_dev *dev = ew->ib_dev;
1052 struct mlx4_eqe *eqe = &(ew->ib_eqe);
1053 u8 port = eqe->event.port_mgmt_change.port;
1054 u32 changed_attr;
2a4fae14
JM		 1055 u32 tbl_block;
1056 u32 change_bitmap;
00f5ce99
JM		 1057
1058 switch (eqe->subtype) {
1059 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO:
1060 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr);
1061
1062 /* Update the SM ah - This should be done before handling
1063 the other changed attributes so that MADs can be sent to the SM */
1064 if (changed_attr & MSTR_SM_CHANGE_MASK) {
1065 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid);
1066 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf;
1067 update_sm_ah(dev, port, lid, sl);
1068 }
1069
1070 /* Check if it is a lid change event */
1071 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK)
2a4fae14 1072 handle_lid_change_event(dev, port);
00f5ce99
JM		 1073
1074 /* Generate GUID changed event */
2a4fae14 1075 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) {
00f5ce99 1076 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
2a4fae14
JM		 1077 /*if master, notify all slaves*/
1078 if (mlx4_is_master(dev->dev))
1079 mlx4_gen_slaves_port_mgt_ev(dev->dev, port,
1080 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK);
1081 }
00f5ce99
JM		 1082
1083 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK)
b9c5d6a6 1084 handle_client_rereg_event(dev, port);
00f5ce99
JM		 1085 break;
1086
1087 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE:
1088 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE);
2a4fae14
JM		 1089 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
1090 propagate_pkey_ev(dev, port, eqe);
00f5ce99
JM		 1091 break;
1092 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO:
6634961c
JM		 1093 /* paravirtualized master's guid is guid 0 -- does not change */
1094 if (!mlx4_is_master(dev->dev))
1095 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
2a4fae14
JM		 1096 /*if master, notify relevant slaves*/
1097 else if (!dev->sriov.is_going_down) {
1098 tbl_block = GET_BLK_PTR_FROM_EQE(eqe);
1099 change_bitmap = GET_MASK_FROM_EQE(eqe);
1100 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap);
1101 }
00f5ce99
JM		 1102 break;
1103 default:
1104 pr_warn("Unsupported subtype 0x%x for "
1105 "Port Management Change event\n", eqe->subtype);
1106 }
1107
1108 kfree(ew);
1109}
1110
1111void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
1112 enum ib_event_type type)
1113{
1114 struct ib_event event;
1115
1116 event.device = &dev->ib_dev;
1117 event.element.port_num = port_num;
1118 event.event = type;
1119
1120 ib_dispatch_event(&event);
1121}
fc06573d
JM		 1122
1123static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg)
1124{
1125 unsigned long flags;
1126 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context;
1127 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1128 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
1129 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE)
1130 queue_work(ctx->wq, &ctx->work);
1131 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
1132}
1133
1134static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx,
1135 struct mlx4_ib_demux_pv_qp *tun_qp,
1136 int index)
1137{
1138 struct ib_sge sg_list;
1139 struct ib_recv_wr recv_wr, *bad_recv_wr;
1140 int size;
1141
1142 size = (tun_qp->qp->qp_type == IB_QPT_UD) ?
1143 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf);
1144
1145 sg_list.addr = tun_qp->ring[index].map;
1146 sg_list.length = size;
7dd97576 1147 sg_list.lkey = ctx->pd->local_dma_lkey;
fc06573d
JM		 1148
1149 recv_wr.next = NULL;
1150 recv_wr.sg_list = &sg_list;
1151 recv_wr.num_sge = 1;
1152 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV |
1153 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt);
1154 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map,
1155 size, DMA_FROM_DEVICE);
1156 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr);
1157}
1158
37bfc7c1
JM		 1159static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port,
1160 int slave, struct ib_sa_mad *sa_mad)
1161{
b9c5d6a6
OD		 1162 int ret = 0;
1163
1164 /* dispatch to different sa handlers */
1165 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
1166 case IB_SA_ATTR_MC_MEMBER_REC:
1167 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad);
1168 break;
1169 default:
1170 break;
1171 }
1172 return ret;
37bfc7c1
JM		 1173}
1174
1175static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave)
1176{
47605df9 1177 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave;
37bfc7c1 1178
47605df9 1179 return (qpn >= proxy_start && qpn <= proxy_start + 1);
37bfc7c1
JM		 1180}
1181
1182
1183int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
5ea8bbfc
JM		 1184 enum ib_qp_type dest_qpt, u16 pkey_index,
1185 u32 remote_qpn, u32 qkey, struct ib_ah_attr *attr,
1186 u8 *s_mac, struct ib_mad *mad)
37bfc7c1
JM		 1187{
1188 struct ib_sge list;
1189 struct ib_send_wr wr, *bad_wr;
1190 struct mlx4_ib_demux_pv_ctx *sqp_ctx;
1191 struct mlx4_ib_demux_pv_qp *sqp;
1192 struct mlx4_mad_snd_buf *sqp_mad;
1193 struct ib_ah *ah;
1194 struct ib_qp *send_qp = NULL;
1195 unsigned wire_tx_ix = 0;
1196 int ret = 0;
1197 u16 wire_pkey_ix;
1198 int src_qpnum;
1199 u8 sgid_index;
1200
1201
1202 sqp_ctx = dev->sriov.sqps[port-1];
1203
1204 /* check if proxy qp created */
1205 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE)
1206 return -EAGAIN;
1207
37bfc7c1
JM		 1208 if (dest_qpt == IB_QPT_SMI) {
1209 src_qpnum = 0;
1210 sqp = &sqp_ctx->qp[0];
1211 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
1212 } else {
1213 src_qpnum = 1;
1214 sqp = &sqp_ctx->qp[1];
1215 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index];
1216 }
1217
1218 send_qp = sqp->qp;
1219
1220 /* create ah */
1221 sgid_index = attr->grh.sgid_index;
1222 attr->grh.sgid_index = 0;
1223 ah = ib_create_ah(sqp_ctx->pd, attr);
1224 if (IS_ERR(ah))
1225 return -ENOMEM;
1226 attr->grh.sgid_index = sgid_index;
1227 to_mah(ah)->av.ib.gid_index = sgid_index;
1228 /* get rid of force-loopback bit */
1229 to_mah(ah)->av.ib.port_pd &= cpu_to_be32(0x7FFFFFFF);
1230 spin_lock(&sqp->tx_lock);
1231 if (sqp->tx_ix_head - sqp->tx_ix_tail >=
1232 (MLX4_NUM_TUNNEL_BUFS - 1))
1233 ret = -EAGAIN;
1234 else
1235 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
1236 spin_unlock(&sqp->tx_lock);
1237 if (ret)
1238 goto out;
1239
1240 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr);
1241 if (sqp->tx_ring[wire_tx_ix].ah)
1242 ib_destroy_ah(sqp->tx_ring[wire_tx_ix].ah);
1243 sqp->tx_ring[wire_tx_ix].ah = ah;
1244 ib_dma_sync_single_for_cpu(&dev->ib_dev,
1245 sqp->tx_ring[wire_tx_ix].buf.map,
1246 sizeof (struct mlx4_mad_snd_buf),
1247 DMA_TO_DEVICE);
1248
1249 memcpy(&sqp_mad->payload, mad, sizeof *mad);
1250
1251 ib_dma_sync_single_for_device(&dev->ib_dev,
1252 sqp->tx_ring[wire_tx_ix].buf.map,
1253 sizeof (struct mlx4_mad_snd_buf),
1254 DMA_TO_DEVICE);
1255
1256 list.addr = sqp->tx_ring[wire_tx_ix].buf.map;
1257 list.length = sizeof (struct mlx4_mad_snd_buf);
7dd97576 1258 list.lkey = sqp_ctx->pd->local_dma_lkey;
37bfc7c1
JM		 1259
1260 wr.wr.ud.ah = ah;
1261 wr.wr.ud.port_num = port;
1262 wr.wr.ud.pkey_index = wire_pkey_ix;
1263 wr.wr.ud.remote_qkey = qkey;
1264 wr.wr.ud.remote_qpn = remote_qpn;
1265 wr.next = NULL;
1266 wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum);
1267 wr.sg_list = &list;
1268 wr.num_sge = 1;
1269 wr.opcode = IB_WR_SEND;
1270 wr.send_flags = IB_SEND_SIGNALED;
5ea8bbfc
JM		 1271 if (s_mac)
1272 memcpy(to_mah(ah)->av.eth.s_mac, s_mac, 6);
1273
37bfc7c1
JM		 1274
1275 ret = ib_post_send(send_qp, &wr, &bad_wr);
1276out:
1277 if (ret)
1278 ib_destroy_ah(ah);
1279 return ret;
1280}
1281
b6ffaeff
JM		 1282static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port)
1283{
b6ffaeff
JM		 1284 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1285 return slave;
449fc488 1286 return mlx4_get_base_gid_ix(dev->dev, slave, port);
b6ffaeff
JM		 1287}
1288
1289static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port,
1290 struct ib_ah_attr *ah_attr)
1291{
1292 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1293 ah_attr->grh.sgid_index = slave;
1294 else
1295 ah_attr->grh.sgid_index += get_slave_base_gid_ix(dev, slave, port);
1296}
1297
37bfc7c1
JM		 1298static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc)
1299{
1300 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1301 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)];
1302 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1);
1303 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr;
1304 struct mlx4_ib_ah ah;
1305 struct ib_ah_attr ah_attr;
1306 u8 *slave_id;
1307 int slave;
449fc488 1308 int port;
37bfc7c1
JM		 1309
1310 /* Get slave that sent this packet */
47605df9
JM		 1311 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn ||
1312 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX ||
37bfc7c1
JM		 1313 (wc->src_qp & 0x1) != ctx->port - 1 ||
1314 wc->src_qp & 0x4) {
1315 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp);
1316 return;
1317 }
47605df9 1318 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8;
37bfc7c1
JM		 1319 if (slave != ctx->slave) {
1320 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: "
1321 "belongs to another slave\n", wc->src_qp);
1322 return;
1323 }
37bfc7c1
JM		 1324
1325 /* Map transaction ID */
1326 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map,
1327 sizeof (struct mlx4_tunnel_mad),
1328 DMA_FROM_DEVICE);
1329 switch (tunnel->mad.mad_hdr.method) {
1330 case IB_MGMT_METHOD_SET:
1331 case IB_MGMT_METHOD_GET:
1332 case IB_MGMT_METHOD_REPORT:
1333 case IB_SA_METHOD_GET_TABLE:
1334 case IB_SA_METHOD_DELETE:
1335 case IB_SA_METHOD_GET_MULTI:
1336 case IB_SA_METHOD_GET_TRACE_TBL:
1337 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid;
1338 if (*slave_id) {
1339 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d "
1340 "class:%d slave:%d\n", *slave_id,
1341 tunnel->mad.mad_hdr.mgmt_class, slave);
1342 return;
1343 } else
1344 *slave_id = slave;
1345 default:
1346 /* nothing */;
1347 }
1348
1349 /* Class-specific handling */
1350 switch (tunnel->mad.mad_hdr.mgmt_class) {
97982f5a
JM		 1351 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
1352 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
1353 if (slave != mlx4_master_func_num(dev->dev) &&
1354 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port))
1355 return;
1356 break;
37bfc7c1
JM		 1357 case IB_MGMT_CLASS_SUBN_ADM:
1358 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave,
1359 (struct ib_sa_mad *) &tunnel->mad))
1360 return;
1361 break;
3cf69cc8
AV		 1362 case IB_MGMT_CLASS_CM:
1363 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave,
1364 (struct ib_mad *) &tunnel->mad))
1365 return;
1366 break;
37bfc7c1
JM		 1367 case IB_MGMT_CLASS_DEVICE_MGMT:
1368 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET &&
1369 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET)
1370 return;
1371 break;
1372 default:
1373 /* Drop unsupported classes for slaves in tunnel mode */
1374 if (slave != mlx4_master_func_num(dev->dev)) {
1375 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d "
1376 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave);
1377 return;
1378 }
1379 }
1380
1381 /* We are using standard ib_core services to send the mad, so generate a
1382 * stadard address handle by decoding the tunnelled mlx4_ah fields */
1383 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av));
1384 ah.ibah.device = ctx->ib_dev;
430910b1
OG		 1385
1386 port = be32_to_cpu(ah.av.ib.port_pd) >> 24;
1387 port = mlx4_slave_convert_port(dev->dev, slave, port);
1388 if (port < 0)
1389 return;
1390 ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff));
1391
37bfc7c1 1392 mlx4_ib_query_ah(&ah.ibah, &ah_attr);
6ee51a4e 1393 if (ah_attr.ah_flags & IB_AH_GRH)
b6ffaeff 1394 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr);
37bfc7c1 1395
5ea8bbfc
JM		 1396 memcpy(ah_attr.dmac, tunnel->hdr.mac, 6);
1397 ah_attr.vlan_id = be16_to_cpu(tunnel->hdr.vlan);
1398 /* if slave have default vlan use it */
1399 mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave,
1400 &ah_attr.vlan_id, &ah_attr.sl);
1401
37bfc7c1
JM		 1402 mlx4_ib_send_to_wire(dev, slave, ctx->port,
1403 is_proxy_qp0(dev, wc->src_qp, slave) ?
1404 IB_QPT_SMI : IB_QPT_GSI,
1405 be16_to_cpu(tunnel->hdr.pkey_index),
1406 be32_to_cpu(tunnel->hdr.remote_qpn),
1407 be32_to_cpu(tunnel->hdr.qkey),
5ea8bbfc 1408 &ah_attr, wc->smac, &tunnel->mad);
37bfc7c1
JM		 1409}
1410
fc06573d
JM		 1411static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1412 enum ib_qp_type qp_type, int is_tun)
1413{
1414 int i;
1415 struct mlx4_ib_demux_pv_qp *tun_qp;
1416 int rx_buf_size, tx_buf_size;
1417
1418 if (qp_type > IB_QPT_GSI)
1419 return -EINVAL;
1420
1421 tun_qp = &ctx->qp[qp_type];
1422
1423 tun_qp->ring = kzalloc(sizeof (struct mlx4_ib_buf) * MLX4_NUM_TUNNEL_BUFS,
1424 GFP_KERNEL);
1425 if (!tun_qp->ring)
1426 return -ENOMEM;
1427
1428 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS,
1429 sizeof (struct mlx4_ib_tun_tx_buf),
1430 GFP_KERNEL);
1431 if (!tun_qp->tx_ring) {
1432 kfree(tun_qp->ring);
1433 tun_qp->ring = NULL;
1434 return -ENOMEM;
1435 }
1436
1437 if (is_tun) {
1438 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1439 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1440 } else {
1441 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1442 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1443 }
1444
1445 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1446 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL);
1447 if (!tun_qp->ring[i].addr)
1448 goto err;
1449 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev,
1450 tun_qp->ring[i].addr,
1451 rx_buf_size,
1452 DMA_FROM_DEVICE);
cc47d369
SO		 1453 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) {
1454 kfree(tun_qp->ring[i].addr);
1455 goto err;
1456 }
fc06573d
JM		 1457 }
1458
1459 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1460 tun_qp->tx_ring[i].buf.addr =
1461 kmalloc(tx_buf_size, GFP_KERNEL);
1462 if (!tun_qp->tx_ring[i].buf.addr)
1463 goto tx_err;
1464 tun_qp->tx_ring[i].buf.map =
1465 ib_dma_map_single(ctx->ib_dev,
1466 tun_qp->tx_ring[i].buf.addr,
1467 tx_buf_size,
1468 DMA_TO_DEVICE);
cc47d369
SO		 1469 if (ib_dma_mapping_error(ctx->ib_dev,
1470 tun_qp->tx_ring[i].buf.map)) {
1471 kfree(tun_qp->tx_ring[i].buf.addr);
1472 goto tx_err;
1473 }
fc06573d
JM		 1474 tun_qp->tx_ring[i].ah = NULL;
1475 }
1476 spin_lock_init(&tun_qp->tx_lock);
1477 tun_qp->tx_ix_head = 0;
1478 tun_qp->tx_ix_tail = 0;
1479 tun_qp->proxy_qpt = qp_type;
1480
1481 return 0;
1482
1483tx_err:
1484 while (i > 0) {
1485 --i;
1486 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1487 tx_buf_size, DMA_TO_DEVICE);
1488 kfree(tun_qp->tx_ring[i].buf.addr);
1489 }
1490 kfree(tun_qp->tx_ring);
1491 tun_qp->tx_ring = NULL;
1492 i = MLX4_NUM_TUNNEL_BUFS;
1493err:
1494 while (i > 0) {
1495 --i;
1496 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1497 rx_buf_size, DMA_FROM_DEVICE);
1498 kfree(tun_qp->ring[i].addr);
1499 }
1500 kfree(tun_qp->ring);
1501 tun_qp->ring = NULL;
1502 return -ENOMEM;
1503}
1504
1505static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1506 enum ib_qp_type qp_type, int is_tun)
1507{
1508 int i;
1509 struct mlx4_ib_demux_pv_qp *tun_qp;
1510 int rx_buf_size, tx_buf_size;
1511
1512 if (qp_type > IB_QPT_GSI)
1513 return;
1514
1515 tun_qp = &ctx->qp[qp_type];
1516 if (is_tun) {
1517 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1518 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1519 } else {
1520 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1521 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1522 }
1523
1524
1525 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1526 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1527 rx_buf_size, DMA_FROM_DEVICE);
1528 kfree(tun_qp->ring[i].addr);
1529 }
1530
1531 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1532 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1533 tx_buf_size, DMA_TO_DEVICE);
1534 kfree(tun_qp->tx_ring[i].buf.addr);
1535 if (tun_qp->tx_ring[i].ah)
1536 ib_destroy_ah(tun_qp->tx_ring[i].ah);
1537 }
1538 kfree(tun_qp->tx_ring);
1539 kfree(tun_qp->ring);
1540}
1541
1542static void mlx4_ib_tunnel_comp_worker(struct work_struct *work)
1543{
37bfc7c1
JM		 1544 struct mlx4_ib_demux_pv_ctx *ctx;
1545 struct mlx4_ib_demux_pv_qp *tun_qp;
1546 struct ib_wc wc;
1547 int ret;
1548 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1549 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1550
1551 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1552 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1553 if (wc.status == IB_WC_SUCCESS) {
1554 switch (wc.opcode) {
1555 case IB_WC_RECV:
1556 mlx4_ib_multiplex_mad(ctx, &wc);
1557 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp,
1558 wc.wr_id &
1559 (MLX4_NUM_TUNNEL_BUFS - 1));
1560 if (ret)
1561 pr_err("Failed reposting tunnel "
1562 "buf:%lld\n", wc.wr_id);
1563 break;
1564 case IB_WC_SEND:
1565 pr_debug("received tunnel send completion:"
1566 "wrid=0x%llx, status=0x%x\n",
1567 wc.wr_id, wc.status);
1568 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1569 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1570 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1571 = NULL;
1572 spin_lock(&tun_qp->tx_lock);
1573 tun_qp->tx_ix_tail++;
1574 spin_unlock(&tun_qp->tx_lock);
1575
1576 break;
1577 default:
1578 break;
1579 }
1580 } else {
1581 pr_debug("mlx4_ib: completion error in tunnel: %d."
1582 " status = %d, wrid = 0x%llx\n",
1583 ctx->slave, wc.status, wc.wr_id);
1584 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1585 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1586 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1587 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1588 = NULL;
1589 spin_lock(&tun_qp->tx_lock);
1590 tun_qp->tx_ix_tail++;
1591 spin_unlock(&tun_qp->tx_lock);
1592 }
1593 }
1594 }
fc06573d
JM		 1595}
1596
1597static void pv_qp_event_handler(struct ib_event *event, void *qp_context)
1598{
1599 struct mlx4_ib_demux_pv_ctx *sqp = qp_context;
1600
1601 /* It's worse than that! He's dead, Jim! */
1602 pr_err("Fatal error (%d) on a MAD QP on port %d\n",
1603 event->event, sqp->port);
1604}
1605
1606static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx,
1607 enum ib_qp_type qp_type, int create_tun)
1608{
1609 int i, ret;
1610 struct mlx4_ib_demux_pv_qp *tun_qp;
1611 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr;
1612 struct ib_qp_attr attr;
1613 int qp_attr_mask_INIT;
1614
1615 if (qp_type > IB_QPT_GSI)
1616 return -EINVAL;
1617
1618 tun_qp = &ctx->qp[qp_type];
1619
1620 memset(&qp_init_attr, 0, sizeof qp_init_attr);
1621 qp_init_attr.init_attr.send_cq = ctx->cq;
1622 qp_init_attr.init_attr.recv_cq = ctx->cq;
1623 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
1624 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS;
1625 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS;
1626 qp_init_attr.init_attr.cap.max_send_sge = 1;
1627 qp_init_attr.init_attr.cap.max_recv_sge = 1;
1628 if (create_tun) {
1629 qp_init_attr.init_attr.qp_type = IB_QPT_UD;
1630 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP;
1631 qp_init_attr.port = ctx->port;
1632 qp_init_attr.slave = ctx->slave;
1633 qp_init_attr.proxy_qp_type = qp_type;
1634 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX |
1635 IB_QP_QKEY | IB_QP_PORT;
1636 } else {
1637 qp_init_attr.init_attr.qp_type = qp_type;
1638 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP;
1639 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY;
1640 }
1641 qp_init_attr.init_attr.port_num = ctx->port;
1642 qp_init_attr.init_attr.qp_context = ctx;
1643 qp_init_attr.init_attr.event_handler = pv_qp_event_handler;
1644 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr);
1645 if (IS_ERR(tun_qp->qp)) {
1646 ret = PTR_ERR(tun_qp->qp);
1647 tun_qp->qp = NULL;
1648 pr_err("Couldn't create %s QP (%d)\n",
1649 create_tun ? "tunnel" : "special", ret);
1650 return ret;
1651 }
1652
1653 memset(&attr, 0, sizeof attr);
1654 attr.qp_state = IB_QPS_INIT;
3eac103f
JM		 1655 ret = 0;
1656 if (create_tun)
1657 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave,
1658 ctx->port, IB_DEFAULT_PKEY_FULL,
1659 &attr.pkey_index);
1660 if (ret || !create_tun)
1661 attr.pkey_index =
1662 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0];
fc06573d
JM		 1663 attr.qkey = IB_QP1_QKEY;
1664 attr.port_num = ctx->port;
1665 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT);
1666 if (ret) {
1667 pr_err("Couldn't change %s qp state to INIT (%d)\n",
1668 create_tun ? "tunnel" : "special", ret);
1669 goto err_qp;
1670 }
1671 attr.qp_state = IB_QPS_RTR;
1672 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE);
1673 if (ret) {
1674 pr_err("Couldn't change %s qp state to RTR (%d)\n",
1675 create_tun ? "tunnel" : "special", ret);
1676 goto err_qp;
1677 }
1678 attr.qp_state = IB_QPS_RTS;
1679 attr.sq_psn = 0;
1680 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN);
1681 if (ret) {
1682 pr_err("Couldn't change %s qp state to RTS (%d)\n",
1683 create_tun ? "tunnel" : "special", ret);
1684 goto err_qp;
1685 }
1686
1687 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1688 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i);
1689 if (ret) {
1690 pr_err(" mlx4_ib_post_pv_buf error"
1691 " (err = %d, i = %d)\n", ret, i);
1692 goto err_qp;
1693 }
1694 }
1695 return 0;
1696
1697err_qp:
1698 ib_destroy_qp(tun_qp->qp);
1699 tun_qp->qp = NULL;
1700 return ret;
1701}
1702
1703/*
1704 * IB MAD completion callback for real SQPs
1705 */
1706static void mlx4_ib_sqp_comp_worker(struct work_struct *work)
1707{
37bfc7c1
JM		 1708 struct mlx4_ib_demux_pv_ctx *ctx;
1709 struct mlx4_ib_demux_pv_qp *sqp;
1710 struct ib_wc wc;
1711 struct ib_grh *grh;
1712 struct ib_mad *mad;
1713
1714 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1715 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1716
1717 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1718 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1719 if (wc.status == IB_WC_SUCCESS) {
1720 switch (wc.opcode) {
1721 case IB_WC_SEND:
1722 ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1723 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1724 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1725 = NULL;
1726 spin_lock(&sqp->tx_lock);
1727 sqp->tx_ix_tail++;
1728 spin_unlock(&sqp->tx_lock);
1729 break;
1730 case IB_WC_RECV:
1731 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *)
1732 (sqp->ring[wc.wr_id &
1733 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload);
1734 grh = &(((struct mlx4_mad_rcv_buf *)
1735 (sqp->ring[wc.wr_id &
1736 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh);
1737 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad);
1738 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id &
1739 (MLX4_NUM_TUNNEL_BUFS - 1)))
1740 pr_err("Failed reposting SQP "
1741 "buf:%lld\n", wc.wr_id);
1742 break;
1743 default:
1744 BUG_ON(1);
1745 break;
1746 }
1747 } else {
1748 pr_debug("mlx4_ib: completion error in tunnel: %d."
1749 " status = %d, wrid = 0x%llx\n",
1750 ctx->slave, wc.status, wc.wr_id);
1751 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1752 ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1753 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1754 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1755 = NULL;
1756 spin_lock(&sqp->tx_lock);
1757 sqp->tx_ix_tail++;
1758 spin_unlock(&sqp->tx_lock);
1759 }
1760 }
1761 }
fc06573d
JM		 1762}
1763
1764static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port,
1765 struct mlx4_ib_demux_pv_ctx **ret_ctx)
1766{
1767 struct mlx4_ib_demux_pv_ctx *ctx;
1768
1769 *ret_ctx = NULL;
1770 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL);
1771 if (!ctx) {
1772 pr_err("failed allocating pv resource context "
1773 "for port %d, slave %d\n", port, slave);
1774 return -ENOMEM;
1775 }
1776
1777 ctx->ib_dev = &dev->ib_dev;
1778 ctx->port = port;
1779 ctx->slave = slave;
1780 *ret_ctx = ctx;
1781 return 0;
1782}
1783
1784static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port)
1785{
1786 if (dev->sriov.demux[port - 1].tun[slave]) {
1787 kfree(dev->sriov.demux[port - 1].tun[slave]);
1788 dev->sriov.demux[port - 1].tun[slave] = NULL;
1789 }
1790}
1791
1792static int create_pv_resources(struct ib_device *ibdev, int slave, int port,
1793 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx)
1794{
1795 int ret, cq_size;
8e37210b 1796 struct ib_cq_init_attr cq_attr = {};
fc06573d 1797
3806d08c
JM		 1798 if (ctx->state != DEMUX_PV_STATE_DOWN)
1799 return -EEXIST;
1800
fc06573d 1801 ctx->state = DEMUX_PV_STATE_STARTING;
97982f5a
JM		 1802 /* have QP0 only if link layer is IB */
1803 if (rdma_port_get_link_layer(ibdev, ctx->port) ==
1804 IB_LINK_LAYER_INFINIBAND)
fc06573d
JM		 1805 ctx->has_smi = 1;
1806
1807 if (ctx->has_smi) {
1808 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun);
1809 if (ret) {
1810 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret);
1811 goto err_out;
1812 }
1813 }
1814
1815 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun);
1816 if (ret) {
1817 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret);
1818 goto err_out_qp0;
1819 }
1820
1821 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS;
1822 if (ctx->has_smi)
1823 cq_size *= 2;
1824
8e37210b 1825 cq_attr.cqe = cq_size;
fc06573d 1826 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler,
8e37210b 1827 NULL, ctx, &cq_attr);
fc06573d
JM		 1828 if (IS_ERR(ctx->cq)) {
1829 ret = PTR_ERR(ctx->cq);
1830 pr_err("Couldn't create tunnel CQ (%d)\n", ret);
1831 goto err_buf;
1832 }
1833
1834 ctx->pd = ib_alloc_pd(ctx->ib_dev);
1835 if (IS_ERR(ctx->pd)) {
1836 ret = PTR_ERR(ctx->pd);
1837 pr_err("Couldn't create tunnel PD (%d)\n", ret);
1838 goto err_cq;
1839 }
1840
fc06573d
JM		 1841 if (ctx->has_smi) {
1842 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun);
1843 if (ret) {
1844 pr_err("Couldn't create %s QP0 (%d)\n",
1845 create_tun ? "tunnel for" : "", ret);
7dd97576 1846 goto err_pd;
fc06573d
JM		 1847 }
1848 }
1849
1850 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun);
1851 if (ret) {
1852 pr_err("Couldn't create %s QP1 (%d)\n",
1853 create_tun ? "tunnel for" : "", ret);
1854 goto err_qp0;
1855 }
1856
1857 if (create_tun)
1858 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker);
1859 else
1860 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker);
1861
1862 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq;
1863
1864 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1865 if (ret) {
1866 pr_err("Couldn't arm tunnel cq (%d)\n", ret);
1867 goto err_wq;
1868 }
1869 ctx->state = DEMUX_PV_STATE_ACTIVE;
1870 return 0;
1871
1872err_wq:
1873 ctx->wq = NULL;
1874 ib_destroy_qp(ctx->qp[1].qp);
1875 ctx->qp[1].qp = NULL;
1876
1877
1878err_qp0:
1879 if (ctx->has_smi)
1880 ib_destroy_qp(ctx->qp[0].qp);
1881 ctx->qp[0].qp = NULL;
1882
fc06573d
JM		 1883err_pd:
1884 ib_dealloc_pd(ctx->pd);
1885 ctx->pd = NULL;
1886
1887err_cq:
1888 ib_destroy_cq(ctx->cq);
1889 ctx->cq = NULL;
1890
1891err_buf:
1892 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun);
1893
1894err_out_qp0:
1895 if (ctx->has_smi)
1896 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun);
1897err_out:
1898 ctx->state = DEMUX_PV_STATE_DOWN;
1899 return ret;
1900}
1901
1902static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port,
1903 struct mlx4_ib_demux_pv_ctx *ctx, int flush)
1904{
1905 if (!ctx)
1906 return;
1907 if (ctx->state > DEMUX_PV_STATE_DOWN) {
1908 ctx->state = DEMUX_PV_STATE_DOWNING;
1909 if (flush)
1910 flush_workqueue(ctx->wq);
1911 if (ctx->has_smi) {
1912 ib_destroy_qp(ctx->qp[0].qp);
1913 ctx->qp[0].qp = NULL;
1914 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1);
1915 }
1916 ib_destroy_qp(ctx->qp[1].qp);
1917 ctx->qp[1].qp = NULL;
1918 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1);
fc06573d
JM		 1919 ib_dealloc_pd(ctx->pd);
1920 ctx->pd = NULL;
1921 ib_destroy_cq(ctx->cq);
1922 ctx->cq = NULL;
1923 ctx->state = DEMUX_PV_STATE_DOWN;
1924 }
1925}
1926
1927static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave,
1928 int port, int do_init)
1929{
1930 int ret = 0;
1931
1932 if (!do_init) {
b9c5d6a6 1933 clean_vf_mcast(&dev->sriov.demux[port - 1], slave);
fc06573d
JM		 1934 /* for master, destroy real sqp resources */
1935 if (slave == mlx4_master_func_num(dev->dev))
1936 destroy_pv_resources(dev, slave, port,
1937 dev->sriov.sqps[port - 1], 1);
1938 /* destroy the tunnel qp resources */
1939 destroy_pv_resources(dev, slave, port,
1940 dev->sriov.demux[port - 1].tun[slave], 1);
1941 return 0;
1942 }
1943
1944 /* create the tunnel qp resources */
1945 ret = create_pv_resources(&dev->ib_dev, slave, port, 1,
1946 dev->sriov.demux[port - 1].tun[slave]);
1947
1948 /* for master, create the real sqp resources */
1949 if (!ret && slave == mlx4_master_func_num(dev->dev))
1950 ret = create_pv_resources(&dev->ib_dev, slave, port, 0,
1951 dev->sriov.sqps[port - 1]);
1952 return ret;
1953}
1954
1955void mlx4_ib_tunnels_update_work(struct work_struct *work)
1956{
1957 struct mlx4_ib_demux_work *dmxw;
1958
1959 dmxw = container_of(work, struct mlx4_ib_demux_work, work);
1960 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port,
1961 dmxw->do_init);
1962 kfree(dmxw);
1963 return;
1964}
1965
1966static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev,
1967 struct mlx4_ib_demux_ctx *ctx,
1968 int port)
1969{
1970 char name[12];
1971 int ret = 0;
1972 int i;
1973
1974 ctx->tun = kcalloc(dev->dev->caps.sqp_demux,
1975 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL);
1976 if (!ctx->tun)
1977 return -ENOMEM;
1978
1979 ctx->dev = dev;
1980 ctx->port = port;
1981 ctx->ib_dev = &dev->ib_dev;
1982
449fc488 1983 for (i = 0;
872bf2fb
YH		 1984 i < min(dev->dev->caps.sqp_demux,
1985 (u16)(dev->dev->persist->num_vfs + 1));
449fc488
MB		 1986 i++) {
1987 struct mlx4_active_ports actv_ports =
1988 mlx4_get_active_ports(dev->dev, i);
1989
1990 if (!test_bit(port - 1, actv_ports.ports))
1991 continue;
1992
fc06573d
JM		 1993 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]);
1994 if (ret) {
1995 ret = -ENOMEM;
b9c5d6a6 1996 goto err_mcg;
fc06573d
JM		 1997 }
1998 }
1999
b9c5d6a6
OD		 2000 ret = mlx4_ib_mcg_port_init(ctx);
2001 if (ret) {
2002 pr_err("Failed initializing mcg para-virt (%d)\n", ret);
2003 goto err_mcg;
2004 }
2005
fc06573d
JM		 2006 snprintf(name, sizeof name, "mlx4_ibt%d", port);
2007 ctx->wq = create_singlethread_workqueue(name);
2008 if (!ctx->wq) {
2009 pr_err("Failed to create tunnelling WQ for port %d\n", port);
2010 ret = -ENOMEM;
2011 goto err_wq;
2012 }
2013
2014 snprintf(name, sizeof name, "mlx4_ibud%d", port);
2015 ctx->ud_wq = create_singlethread_workqueue(name);
2016 if (!ctx->ud_wq) {
2017 pr_err("Failed to create up/down WQ for port %d\n", port);
2018 ret = -ENOMEM;
2019 goto err_udwq;
2020 }
2021
2022 return 0;
2023
2024err_udwq:
2025 destroy_workqueue(ctx->wq);
2026 ctx->wq = NULL;
2027
2028err_wq:
b9c5d6a6
OD		 2029 mlx4_ib_mcg_port_cleanup(ctx, 1);
2030err_mcg:
fc06573d
JM		 2031 for (i = 0; i < dev->dev->caps.sqp_demux; i++)
2032 free_pv_object(dev, i, port);
2033 kfree(ctx->tun);
2034 ctx->tun = NULL;
2035 return ret;
2036}
2037
2038static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx)
2039{
2040 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) {
2041 sqp_ctx->state = DEMUX_PV_STATE_DOWNING;
2042 flush_workqueue(sqp_ctx->wq);
2043 if (sqp_ctx->has_smi) {
2044 ib_destroy_qp(sqp_ctx->qp[0].qp);
2045 sqp_ctx->qp[0].qp = NULL;
2046 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0);
2047 }
2048 ib_destroy_qp(sqp_ctx->qp[1].qp);
2049 sqp_ctx->qp[1].qp = NULL;
2050 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0);
fc06573d
JM		 2051 ib_dealloc_pd(sqp_ctx->pd);
2052 sqp_ctx->pd = NULL;
2053 ib_destroy_cq(sqp_ctx->cq);
2054 sqp_ctx->cq = NULL;
2055 sqp_ctx->state = DEMUX_PV_STATE_DOWN;
2056 }
2057}
2058
2059static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx)
2060{
2061 int i;
2062 if (ctx) {
2063 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
b9c5d6a6 2064 mlx4_ib_mcg_port_cleanup(ctx, 1);
fc06573d
JM		 2065 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2066 if (!ctx->tun[i])
2067 continue;
2068 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN)
2069 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING;
2070 }
2071 flush_workqueue(ctx->wq);
2072 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2073 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0);
2074 free_pv_object(dev, i, ctx->port);
2075 }
2076 kfree(ctx->tun);
2077 destroy_workqueue(ctx->ud_wq);
2078 destroy_workqueue(ctx->wq);
2079 }
2080}
2081
2082static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init)
2083{
2084 int i;
2085
2086 if (!mlx4_is_master(dev->dev))
2087 return;
2088 /* initialize or tear down tunnel QPs for the master */
2089 for (i = 0; i < dev->dev->caps.num_ports; i++)
2090 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init);
2091 return;
2092}
2093
2094int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev)
2095{
2096 int i = 0;
2097 int err;
2098
2099 if (!mlx4_is_mfunc(dev->dev))
2100 return 0;
2101
2102 dev->sriov.is_going_down = 0;
2103 spin_lock_init(&dev->sriov.going_down_lock);
3cf69cc8 2104 mlx4_ib_cm_paravirt_init(dev);
fc06573d
JM		 2105
2106 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n");
2107
2108 if (mlx4_is_slave(dev->dev)) {
2109 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n");
2110 return 0;
2111 }
2112
afa8fd1d
JM		 2113 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2114 if (i == mlx4_master_func_num(dev->dev))
2115 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid);
2116 else
2117 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid());
2118 }
2119
a0c64a17
JM		 2120 err = mlx4_ib_init_alias_guid_service(dev);
2121 if (err) {
2122 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n");
2123 goto paravirt_err;
2124 }
c1e7e466
JM		 2125 err = mlx4_ib_device_register_sysfs(dev);
2126 if (err) {
2127 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n");
2128 goto sysfs_err;
2129 }
a0c64a17 2130
fc06573d
JM		 2131 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n",
2132 dev->dev->caps.sqp_demux);
2133 for (i = 0; i < dev->num_ports; i++) {
a0c64a17
JM		 2134 union ib_gid gid;
2135 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1);
2136 if (err)
2137 goto demux_err;
2138 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id;
fc06573d
JM		 2139 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1,
2140 &dev->sriov.sqps[i]);
2141 if (err)
2142 goto demux_err;
2143 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1);
2144 if (err)
cab66d12 2145 goto free_pv;
fc06573d
JM		 2146 }
2147 mlx4_ib_master_tunnels(dev, 1);
2148 return 0;
2149
cab66d12
DC		 2150free_pv:
2151 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
fc06573d 2152demux_err:
cab66d12 2153 while (--i >= 0) {
fc06573d
JM		 2154 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2155 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
fc06573d 2156 }
c1e7e466
JM		 2157 mlx4_ib_device_unregister_sysfs(dev);
2158
2159sysfs_err:
a0c64a17
JM		 2160 mlx4_ib_destroy_alias_guid_service(dev);
2161
2162paravirt_err:
3cf69cc8 2163 mlx4_ib_cm_paravirt_clean(dev, -1);
fc06573d
JM		 2164
2165 return err;
2166}
2167
2168void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev)
2169{
2170 int i;
2171 unsigned long flags;
2172
2173 if (!mlx4_is_mfunc(dev->dev))
2174 return;
2175
2176 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
2177 dev->sriov.is_going_down = 1;
2178 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
3cf69cc8 2179 if (mlx4_is_master(dev->dev)) {
fc06573d
JM		 2180 for (i = 0; i < dev->num_ports; i++) {
2181 flush_workqueue(dev->sriov.demux[i].ud_wq);
2182 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]);
2183 kfree(dev->sriov.sqps[i]);
2184 dev->sriov.sqps[i] = NULL;
2185 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2186 }
3cf69cc8
AV		 2187
2188 mlx4_ib_cm_paravirt_clean(dev, -1);
a0c64a17 2189 mlx4_ib_destroy_alias_guid_service(dev);
c1e7e466 2190 mlx4_ib_device_unregister_sysfs(dev);
3cf69cc8 2191 }
fc06573d 2192}
Linux 6.x block layer and io_uring tree(s)