Commit | Line | Data |
---|---|---|
225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/mlx4/cq.h> | |
34 | #include <linux/mlx4/qp.h> | |
35 | ||
36 | #include "mlx4_ib.h" | |
37 | #include "user.h" | |
38 | ||
39 | static void mlx4_ib_cq_comp(struct mlx4_cq *cq) | |
40 | { | |
41 | struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; | |
42 | ibcq->comp_handler(ibcq, ibcq->cq_context); | |
43 | } | |
44 | ||
45 | static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) | |
46 | { | |
47 | struct ib_event event; | |
48 | struct ib_cq *ibcq; | |
49 | ||
50 | if (type != MLX4_EVENT_TYPE_CQ_ERROR) { | |
51 | printk(KERN_WARNING "mlx4_ib: Unexpected event type %d " | |
52 | "on CQ %06x\n", type, cq->cqn); | |
53 | return; | |
54 | } | |
55 | ||
56 | ibcq = &to_mibcq(cq)->ibcq; | |
57 | if (ibcq->event_handler) { | |
58 | event.device = ibcq->device; | |
59 | event.event = IB_EVENT_CQ_ERR; | |
60 | event.element.cq = ibcq; | |
61 | ibcq->event_handler(&event, ibcq->cq_context); | |
62 | } | |
63 | } | |
64 | ||
65 | static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) | |
66 | { | |
1c69fc2a | 67 | return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe)); |
225c7b1f RD |
68 | } |
69 | ||
70 | static void *get_cqe(struct mlx4_ib_cq *cq, int n) | |
71 | { | |
72 | return get_cqe_from_buf(&cq->buf, n); | |
73 | } | |
74 | ||
75 | static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) | |
76 | { | |
77 | struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); | |
78 | ||
79 | return (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ | |
80 | !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; | |
81 | } | |
82 | ||
83 | static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) | |
84 | { | |
85 | return get_sw_cqe(cq, cq->mcq.cons_index); | |
86 | } | |
87 | ||
3fdcb97f EC |
88 | int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) |
89 | { | |
90 | struct mlx4_ib_cq *mcq = to_mcq(cq); | |
91 | struct mlx4_ib_dev *dev = to_mdev(cq->device); | |
92 | ||
93 | return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); | |
94 | } | |
95 | ||
225c7b1f RD |
96 | struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector, |
97 | struct ib_ucontext *context, | |
98 | struct ib_udata *udata) | |
99 | { | |
100 | struct mlx4_ib_dev *dev = to_mdev(ibdev); | |
101 | struct mlx4_ib_cq *cq; | |
102 | struct mlx4_uar *uar; | |
103 | int buf_size; | |
104 | int err; | |
105 | ||
106 | if (entries < 1 || entries > dev->dev->caps.max_cqes) | |
107 | return ERR_PTR(-EINVAL); | |
108 | ||
109 | cq = kmalloc(sizeof *cq, GFP_KERNEL); | |
110 | if (!cq) | |
111 | return ERR_PTR(-ENOMEM); | |
112 | ||
113 | entries = roundup_pow_of_two(entries + 1); | |
114 | cq->ibcq.cqe = entries - 1; | |
115 | buf_size = entries * sizeof (struct mlx4_cqe); | |
116 | spin_lock_init(&cq->lock); | |
117 | ||
118 | if (context) { | |
119 | struct mlx4_ib_create_cq ucmd; | |
120 | ||
121 | if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { | |
122 | err = -EFAULT; | |
123 | goto err_cq; | |
124 | } | |
125 | ||
126 | cq->umem = ib_umem_get(context, ucmd.buf_addr, buf_size, | |
127 | IB_ACCESS_LOCAL_WRITE); | |
128 | if (IS_ERR(cq->umem)) { | |
129 | err = PTR_ERR(cq->umem); | |
130 | goto err_cq; | |
131 | } | |
132 | ||
133 | err = mlx4_mtt_init(dev->dev, ib_umem_page_count(cq->umem), | |
134 | ilog2(cq->umem->page_size), &cq->buf.mtt); | |
135 | if (err) | |
136 | goto err_buf; | |
137 | ||
138 | err = mlx4_ib_umem_write_mtt(dev, &cq->buf.mtt, cq->umem); | |
139 | if (err) | |
140 | goto err_mtt; | |
141 | ||
142 | err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr, | |
143 | &cq->db); | |
144 | if (err) | |
145 | goto err_mtt; | |
146 | ||
147 | uar = &to_mucontext(context)->uar; | |
148 | } else { | |
149 | err = mlx4_ib_db_alloc(dev, &cq->db, 1); | |
150 | if (err) | |
151 | goto err_cq; | |
152 | ||
153 | cq->mcq.set_ci_db = cq->db.db; | |
154 | cq->mcq.arm_db = cq->db.db + 1; | |
155 | *cq->mcq.set_ci_db = 0; | |
156 | *cq->mcq.arm_db = 0; | |
157 | ||
158 | if (mlx4_buf_alloc(dev->dev, buf_size, PAGE_SIZE * 2, &cq->buf.buf)) { | |
159 | err = -ENOMEM; | |
160 | goto err_db; | |
161 | } | |
162 | ||
163 | err = mlx4_mtt_init(dev->dev, cq->buf.buf.npages, cq->buf.buf.page_shift, | |
164 | &cq->buf.mtt); | |
165 | if (err) | |
166 | goto err_buf; | |
167 | ||
168 | err = mlx4_buf_write_mtt(dev->dev, &cq->buf.mtt, &cq->buf.buf); | |
169 | if (err) | |
170 | goto err_mtt; | |
171 | ||
172 | uar = &dev->priv_uar; | |
173 | } | |
174 | ||
175 | err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, | |
176 | cq->db.dma, &cq->mcq); | |
177 | if (err) | |
178 | goto err_dbmap; | |
179 | ||
180 | cq->mcq.comp = mlx4_ib_cq_comp; | |
181 | cq->mcq.event = mlx4_ib_cq_event; | |
182 | ||
183 | if (context) | |
184 | if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { | |
185 | err = -EFAULT; | |
186 | goto err_dbmap; | |
187 | } | |
188 | ||
189 | return &cq->ibcq; | |
190 | ||
191 | err_dbmap: | |
192 | if (context) | |
193 | mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db); | |
194 | ||
195 | err_mtt: | |
196 | mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); | |
197 | ||
198 | err_buf: | |
199 | if (context) | |
200 | ib_umem_release(cq->umem); | |
201 | else | |
202 | mlx4_buf_free(dev->dev, entries * sizeof (struct mlx4_cqe), | |
203 | &cq->buf.buf); | |
204 | ||
205 | err_db: | |
206 | if (!context) | |
207 | mlx4_ib_db_free(dev, &cq->db); | |
208 | ||
209 | err_cq: | |
210 | kfree(cq); | |
211 | ||
212 | return ERR_PTR(err); | |
213 | } | |
214 | ||
215 | int mlx4_ib_destroy_cq(struct ib_cq *cq) | |
216 | { | |
217 | struct mlx4_ib_dev *dev = to_mdev(cq->device); | |
218 | struct mlx4_ib_cq *mcq = to_mcq(cq); | |
219 | ||
220 | mlx4_cq_free(dev->dev, &mcq->mcq); | |
221 | mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); | |
222 | ||
223 | if (cq->uobject) { | |
224 | mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db); | |
225 | ib_umem_release(mcq->umem); | |
226 | } else { | |
227 | mlx4_buf_free(dev->dev, (cq->cqe + 1) * sizeof (struct mlx4_cqe), | |
228 | &mcq->buf.buf); | |
229 | mlx4_ib_db_free(dev, &mcq->db); | |
230 | } | |
231 | ||
232 | kfree(mcq); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | static void dump_cqe(void *cqe) | |
238 | { | |
239 | __be32 *buf = cqe; | |
240 | ||
241 | printk(KERN_DEBUG "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
242 | be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), | |
243 | be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), | |
244 | be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); | |
245 | } | |
246 | ||
247 | static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, | |
248 | struct ib_wc *wc) | |
249 | { | |
250 | if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { | |
251 | printk(KERN_DEBUG "local QP operation err " | |
252 | "(QPN %06x, WQE index %x, vendor syndrome %02x, " | |
253 | "opcode = %02x)\n", | |
254 | be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), | |
255 | cqe->vendor_err_syndrome, | |
256 | cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); | |
257 | dump_cqe(cqe); | |
258 | } | |
259 | ||
260 | switch (cqe->syndrome) { | |
261 | case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: | |
262 | wc->status = IB_WC_LOC_LEN_ERR; | |
263 | break; | |
264 | case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: | |
265 | wc->status = IB_WC_LOC_QP_OP_ERR; | |
266 | break; | |
267 | case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: | |
268 | wc->status = IB_WC_LOC_PROT_ERR; | |
269 | break; | |
270 | case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: | |
271 | wc->status = IB_WC_WR_FLUSH_ERR; | |
272 | break; | |
273 | case MLX4_CQE_SYNDROME_MW_BIND_ERR: | |
274 | wc->status = IB_WC_MW_BIND_ERR; | |
275 | break; | |
276 | case MLX4_CQE_SYNDROME_BAD_RESP_ERR: | |
277 | wc->status = IB_WC_BAD_RESP_ERR; | |
278 | break; | |
279 | case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: | |
280 | wc->status = IB_WC_LOC_ACCESS_ERR; | |
281 | break; | |
282 | case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: | |
283 | wc->status = IB_WC_REM_INV_REQ_ERR; | |
284 | break; | |
285 | case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: | |
286 | wc->status = IB_WC_REM_ACCESS_ERR; | |
287 | break; | |
288 | case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: | |
289 | wc->status = IB_WC_REM_OP_ERR; | |
290 | break; | |
291 | case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: | |
292 | wc->status = IB_WC_RETRY_EXC_ERR; | |
293 | break; | |
294 | case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: | |
295 | wc->status = IB_WC_RNR_RETRY_EXC_ERR; | |
296 | break; | |
297 | case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: | |
298 | wc->status = IB_WC_REM_ABORT_ERR; | |
299 | break; | |
300 | default: | |
301 | wc->status = IB_WC_GENERAL_ERR; | |
302 | break; | |
303 | } | |
304 | ||
305 | wc->vendor_err = cqe->vendor_err_syndrome; | |
306 | } | |
307 | ||
8ff095ec EC |
308 | static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum) |
309 | { | |
310 | return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | | |
311 | MLX4_CQE_IPOIB_STATUS_IPV4F | | |
312 | MLX4_CQE_IPOIB_STATUS_IPV4OPT | | |
313 | MLX4_CQE_IPOIB_STATUS_IPV6 | | |
314 | MLX4_CQE_IPOIB_STATUS_IPOK)) == | |
315 | cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | | |
316 | MLX4_CQE_IPOIB_STATUS_IPOK)) && | |
317 | (status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP | | |
318 | MLX4_CQE_IPOIB_STATUS_TCP)) && | |
319 | checksum == cpu_to_be16(0xffff); | |
320 | } | |
321 | ||
225c7b1f RD |
322 | static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, |
323 | struct mlx4_ib_qp **cur_qp, | |
324 | struct ib_wc *wc) | |
325 | { | |
326 | struct mlx4_cqe *cqe; | |
327 | struct mlx4_qp *mqp; | |
328 | struct mlx4_ib_wq *wq; | |
329 | struct mlx4_ib_srq *srq; | |
330 | int is_send; | |
331 | int is_error; | |
b3226184 | 332 | u32 g_mlpath_rqpn; |
225c7b1f RD |
333 | u16 wqe_ctr; |
334 | ||
335 | cqe = next_cqe_sw(cq); | |
336 | if (!cqe) | |
337 | return -EAGAIN; | |
338 | ||
339 | ++cq->mcq.cons_index; | |
340 | ||
341 | /* | |
342 | * Make sure we read CQ entry contents after we've checked the | |
343 | * ownership bit. | |
344 | */ | |
345 | rmb(); | |
346 | ||
347 | is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; | |
348 | is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
349 | MLX4_CQE_OPCODE_ERROR; | |
350 | ||
ea54b10c JM |
351 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP && |
352 | is_send)) { | |
353 | printk(KERN_WARNING "Completion for NOP opcode detected!\n"); | |
354 | return -EINVAL; | |
355 | } | |
356 | ||
225c7b1f RD |
357 | if (!*cur_qp || |
358 | (be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) { | |
359 | /* | |
360 | * We do not have to take the QP table lock here, | |
361 | * because CQs will be locked while QPs are removed | |
362 | * from the table. | |
363 | */ | |
364 | mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, | |
365 | be32_to_cpu(cqe->my_qpn)); | |
366 | if (unlikely(!mqp)) { | |
367 | printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n", | |
368 | cq->mcq.cqn, be32_to_cpu(cqe->my_qpn) & 0xffffff); | |
369 | return -EINVAL; | |
370 | } | |
371 | ||
372 | *cur_qp = to_mibqp(mqp); | |
373 | } | |
374 | ||
375 | wc->qp = &(*cur_qp)->ibqp; | |
376 | ||
377 | if (is_send) { | |
378 | wq = &(*cur_qp)->sq; | |
ea54b10c JM |
379 | if (!(*cur_qp)->sq_signal_bits) { |
380 | wqe_ctr = be16_to_cpu(cqe->wqe_index); | |
381 | wq->tail += (u16) (wqe_ctr - (u16) wq->tail); | |
382 | } | |
0e6e7416 | 383 | wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; |
225c7b1f RD |
384 | ++wq->tail; |
385 | } else if ((*cur_qp)->ibqp.srq) { | |
386 | srq = to_msrq((*cur_qp)->ibqp.srq); | |
387 | wqe_ctr = be16_to_cpu(cqe->wqe_index); | |
388 | wc->wr_id = srq->wrid[wqe_ctr]; | |
389 | mlx4_ib_free_srq_wqe(srq, wqe_ctr); | |
390 | } else { | |
391 | wq = &(*cur_qp)->rq; | |
0e6e7416 | 392 | wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; |
225c7b1f RD |
393 | ++wq->tail; |
394 | } | |
395 | ||
396 | if (unlikely(is_error)) { | |
397 | mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); | |
398 | return 0; | |
399 | } | |
400 | ||
401 | wc->status = IB_WC_SUCCESS; | |
402 | ||
403 | if (is_send) { | |
404 | wc->wc_flags = 0; | |
405 | switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { | |
406 | case MLX4_OPCODE_RDMA_WRITE_IMM: | |
407 | wc->wc_flags |= IB_WC_WITH_IMM; | |
408 | case MLX4_OPCODE_RDMA_WRITE: | |
409 | wc->opcode = IB_WC_RDMA_WRITE; | |
410 | break; | |
411 | case MLX4_OPCODE_SEND_IMM: | |
412 | wc->wc_flags |= IB_WC_WITH_IMM; | |
413 | case MLX4_OPCODE_SEND: | |
414 | wc->opcode = IB_WC_SEND; | |
415 | break; | |
416 | case MLX4_OPCODE_RDMA_READ: | |
19891915 | 417 | wc->opcode = IB_WC_RDMA_READ; |
225c7b1f RD |
418 | wc->byte_len = be32_to_cpu(cqe->byte_cnt); |
419 | break; | |
420 | case MLX4_OPCODE_ATOMIC_CS: | |
421 | wc->opcode = IB_WC_COMP_SWAP; | |
422 | wc->byte_len = 8; | |
423 | break; | |
424 | case MLX4_OPCODE_ATOMIC_FA: | |
425 | wc->opcode = IB_WC_FETCH_ADD; | |
426 | wc->byte_len = 8; | |
427 | break; | |
428 | case MLX4_OPCODE_BIND_MW: | |
429 | wc->opcode = IB_WC_BIND_MW; | |
430 | break; | |
b832be1e EC |
431 | case MLX4_OPCODE_LSO: |
432 | wc->opcode = IB_WC_LSO; | |
433 | break; | |
225c7b1f RD |
434 | } |
435 | } else { | |
436 | wc->byte_len = be32_to_cpu(cqe->byte_cnt); | |
437 | ||
438 | switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { | |
439 | case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: | |
440 | wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; | |
441 | wc->wc_flags = IB_WC_WITH_IMM; | |
442 | wc->imm_data = cqe->immed_rss_invalid; | |
443 | break; | |
444 | case MLX4_RECV_OPCODE_SEND: | |
445 | wc->opcode = IB_WC_RECV; | |
446 | wc->wc_flags = 0; | |
447 | break; | |
448 | case MLX4_RECV_OPCODE_SEND_IMM: | |
449 | wc->opcode = IB_WC_RECV; | |
450 | wc->wc_flags = IB_WC_WITH_IMM; | |
451 | wc->imm_data = cqe->immed_rss_invalid; | |
452 | break; | |
453 | } | |
454 | ||
455 | wc->slid = be16_to_cpu(cqe->rlid); | |
456 | wc->sl = cqe->sl >> 4; | |
b3226184 RD |
457 | g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); |
458 | wc->src_qp = g_mlpath_rqpn & 0xffffff; | |
459 | wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; | |
460 | wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; | |
e1bb7843 | 461 | wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; |
8ff095ec EC |
462 | wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status, |
463 | cqe->checksum); | |
225c7b1f RD |
464 | } |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) | |
470 | { | |
471 | struct mlx4_ib_cq *cq = to_mcq(ibcq); | |
472 | struct mlx4_ib_qp *cur_qp = NULL; | |
473 | unsigned long flags; | |
474 | int npolled; | |
475 | int err = 0; | |
476 | ||
477 | spin_lock_irqsave(&cq->lock, flags); | |
478 | ||
479 | for (npolled = 0; npolled < num_entries; ++npolled) { | |
480 | err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled); | |
481 | if (err) | |
482 | break; | |
483 | } | |
484 | ||
485 | if (npolled) | |
486 | mlx4_cq_set_ci(&cq->mcq); | |
487 | ||
488 | spin_unlock_irqrestore(&cq->lock, flags); | |
489 | ||
490 | if (err == 0 || err == -EAGAIN) | |
491 | return npolled; | |
492 | else | |
493 | return err; | |
494 | } | |
495 | ||
496 | int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) | |
497 | { | |
498 | mlx4_cq_arm(&to_mcq(ibcq)->mcq, | |
499 | (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? | |
500 | MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, | |
501 | to_mdev(ibcq->device)->uar_map, | |
502 | MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) | |
508 | { | |
509 | u32 prod_index; | |
510 | int nfreed = 0; | |
082dee32 JM |
511 | struct mlx4_cqe *cqe, *dest; |
512 | u8 owner_bit; | |
225c7b1f RD |
513 | |
514 | /* | |
515 | * First we need to find the current producer index, so we | |
516 | * know where to start cleaning from. It doesn't matter if HW | |
517 | * adds new entries after this loop -- the QP we're worried | |
518 | * about is already in RESET, so the new entries won't come | |
519 | * from our QP and therefore don't need to be checked. | |
520 | */ | |
521 | for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) | |
522 | if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) | |
523 | break; | |
524 | ||
525 | /* | |
526 | * Now sweep backwards through the CQ, removing CQ entries | |
527 | * that match our QP by copying older entries on top of them. | |
528 | */ | |
529 | while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { | |
530 | cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); | |
531 | if ((be32_to_cpu(cqe->my_qpn) & 0xffffff) == qpn) { | |
532 | if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) | |
533 | mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); | |
534 | ++nfreed; | |
082dee32 JM |
535 | } else if (nfreed) { |
536 | dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); | |
537 | owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; | |
538 | memcpy(dest, cqe, sizeof *cqe); | |
539 | dest->owner_sr_opcode = owner_bit | | |
540 | (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); | |
541 | } | |
225c7b1f RD |
542 | } |
543 | ||
544 | if (nfreed) { | |
545 | cq->mcq.cons_index += nfreed; | |
546 | /* | |
547 | * Make sure update of buffer contents is done before | |
548 | * updating consumer index. | |
549 | */ | |
550 | wmb(); | |
551 | mlx4_cq_set_ci(&cq->mcq); | |
552 | } | |
553 | } | |
554 | ||
555 | void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) | |
556 | { | |
557 | spin_lock_irq(&cq->lock); | |
558 | __mlx4_ib_cq_clean(cq, qpn, srq); | |
559 | spin_unlock_irq(&cq->lock); | |
560 | } |