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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/mlx4/cq.h> | |
35 | #include <linux/mlx4/qp.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
225c7b1f RD |
37 | |
38 | #include "mlx4_ib.h" | |
39 | #include "user.h" | |
40 | ||
41 | static void mlx4_ib_cq_comp(struct mlx4_cq *cq) | |
42 | { | |
43 | struct ib_cq *ibcq = &to_mibcq(cq)->ibcq; | |
44 | ibcq->comp_handler(ibcq, ibcq->cq_context); | |
45 | } | |
46 | ||
47 | static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type) | |
48 | { | |
49 | struct ib_event event; | |
50 | struct ib_cq *ibcq; | |
51 | ||
52 | if (type != MLX4_EVENT_TYPE_CQ_ERROR) { | |
987c8f8f | 53 | pr_warn("Unexpected event type %d " |
225c7b1f RD |
54 | "on CQ %06x\n", type, cq->cqn); |
55 | return; | |
56 | } | |
57 | ||
58 | ibcq = &to_mibcq(cq)->ibcq; | |
59 | if (ibcq->event_handler) { | |
60 | event.device = ibcq->device; | |
61 | event.event = IB_EVENT_CQ_ERR; | |
62 | event.element.cq = ibcq; | |
63 | ibcq->event_handler(&event, ibcq->cq_context); | |
64 | } | |
65 | } | |
66 | ||
67 | static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n) | |
68 | { | |
1c69fc2a | 69 | return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe)); |
225c7b1f RD |
70 | } |
71 | ||
72 | static void *get_cqe(struct mlx4_ib_cq *cq, int n) | |
73 | { | |
74 | return get_cqe_from_buf(&cq->buf, n); | |
75 | } | |
76 | ||
77 | static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n) | |
78 | { | |
79 | struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe); | |
80 | ||
81 | return (!!(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^ | |
82 | !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe; | |
83 | } | |
84 | ||
85 | static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq) | |
86 | { | |
87 | return get_sw_cqe(cq, cq->mcq.cons_index); | |
88 | } | |
89 | ||
3fdcb97f EC |
90 | int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) |
91 | { | |
92 | struct mlx4_ib_cq *mcq = to_mcq(cq); | |
93 | struct mlx4_ib_dev *dev = to_mdev(cq->device); | |
94 | ||
95 | return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period); | |
96 | } | |
97 | ||
bbf8eed1 VS |
98 | static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent) |
99 | { | |
100 | int err; | |
101 | ||
102 | err = mlx4_buf_alloc(dev->dev, nent * sizeof(struct mlx4_cqe), | |
103 | PAGE_SIZE * 2, &buf->buf); | |
104 | ||
105 | if (err) | |
106 | goto out; | |
107 | ||
108 | err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift, | |
109 | &buf->mtt); | |
110 | if (err) | |
111 | goto err_buf; | |
112 | ||
113 | err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf); | |
114 | if (err) | |
115 | goto err_mtt; | |
116 | ||
117 | return 0; | |
118 | ||
119 | err_mtt: | |
120 | mlx4_mtt_cleanup(dev->dev, &buf->mtt); | |
121 | ||
122 | err_buf: | |
123 | mlx4_buf_free(dev->dev, nent * sizeof(struct mlx4_cqe), | |
124 | &buf->buf); | |
125 | ||
126 | out: | |
127 | return err; | |
128 | } | |
129 | ||
130 | static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe) | |
131 | { | |
132 | mlx4_buf_free(dev->dev, (cqe + 1) * sizeof(struct mlx4_cqe), &buf->buf); | |
133 | } | |
134 | ||
135 | static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context, | |
136 | struct mlx4_ib_cq_buf *buf, struct ib_umem **umem, | |
137 | u64 buf_addr, int cqe) | |
138 | { | |
139 | int err; | |
140 | ||
141 | *umem = ib_umem_get(context, buf_addr, cqe * sizeof (struct mlx4_cqe), | |
cb9fbc5c | 142 | IB_ACCESS_LOCAL_WRITE, 1); |
bbf8eed1 VS |
143 | if (IS_ERR(*umem)) |
144 | return PTR_ERR(*umem); | |
145 | ||
146 | err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem), | |
147 | ilog2((*umem)->page_size), &buf->mtt); | |
148 | if (err) | |
149 | goto err_buf; | |
150 | ||
151 | err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem); | |
152 | if (err) | |
153 | goto err_mtt; | |
154 | ||
155 | return 0; | |
156 | ||
157 | err_mtt: | |
158 | mlx4_mtt_cleanup(dev->dev, &buf->mtt); | |
159 | ||
160 | err_buf: | |
161 | ib_umem_release(*umem); | |
162 | ||
163 | return err; | |
164 | } | |
165 | ||
225c7b1f RD |
166 | struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector, |
167 | struct ib_ucontext *context, | |
168 | struct ib_udata *udata) | |
169 | { | |
170 | struct mlx4_ib_dev *dev = to_mdev(ibdev); | |
171 | struct mlx4_ib_cq *cq; | |
172 | struct mlx4_uar *uar; | |
225c7b1f RD |
173 | int err; |
174 | ||
175 | if (entries < 1 || entries > dev->dev->caps.max_cqes) | |
176 | return ERR_PTR(-EINVAL); | |
177 | ||
178 | cq = kmalloc(sizeof *cq, GFP_KERNEL); | |
179 | if (!cq) | |
180 | return ERR_PTR(-ENOMEM); | |
181 | ||
182 | entries = roundup_pow_of_two(entries + 1); | |
183 | cq->ibcq.cqe = entries - 1; | |
bbf8eed1 | 184 | mutex_init(&cq->resize_mutex); |
225c7b1f | 185 | spin_lock_init(&cq->lock); |
bbf8eed1 VS |
186 | cq->resize_buf = NULL; |
187 | cq->resize_umem = NULL; | |
225c7b1f RD |
188 | |
189 | if (context) { | |
190 | struct mlx4_ib_create_cq ucmd; | |
191 | ||
192 | if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { | |
193 | err = -EFAULT; | |
194 | goto err_cq; | |
195 | } | |
196 | ||
bbf8eed1 VS |
197 | err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem, |
198 | ucmd.buf_addr, entries); | |
225c7b1f | 199 | if (err) |
bbf8eed1 | 200 | goto err_cq; |
225c7b1f RD |
201 | |
202 | err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr, | |
203 | &cq->db); | |
204 | if (err) | |
205 | goto err_mtt; | |
206 | ||
207 | uar = &to_mucontext(context)->uar; | |
208 | } else { | |
6296883c | 209 | err = mlx4_db_alloc(dev->dev, &cq->db, 1); |
225c7b1f RD |
210 | if (err) |
211 | goto err_cq; | |
212 | ||
213 | cq->mcq.set_ci_db = cq->db.db; | |
214 | cq->mcq.arm_db = cq->db.db + 1; | |
215 | *cq->mcq.set_ci_db = 0; | |
216 | *cq->mcq.arm_db = 0; | |
217 | ||
bbf8eed1 | 218 | err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries); |
225c7b1f | 219 | if (err) |
bbf8eed1 | 220 | goto err_db; |
225c7b1f RD |
221 | |
222 | uar = &dev->priv_uar; | |
223 | } | |
224 | ||
e605b743 SP |
225 | if (dev->eq_table) |
226 | vector = dev->eq_table[vector % ibdev->num_comp_vectors]; | |
227 | ||
225c7b1f | 228 | err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar, |
b8dd786f | 229 | cq->db.dma, &cq->mcq, vector, 0); |
225c7b1f RD |
230 | if (err) |
231 | goto err_dbmap; | |
232 | ||
233 | cq->mcq.comp = mlx4_ib_cq_comp; | |
234 | cq->mcq.event = mlx4_ib_cq_event; | |
235 | ||
236 | if (context) | |
237 | if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) { | |
238 | err = -EFAULT; | |
239 | goto err_dbmap; | |
240 | } | |
241 | ||
242 | return &cq->ibcq; | |
243 | ||
244 | err_dbmap: | |
245 | if (context) | |
246 | mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db); | |
247 | ||
248 | err_mtt: | |
249 | mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt); | |
250 | ||
225c7b1f RD |
251 | if (context) |
252 | ib_umem_release(cq->umem); | |
253 | else | |
3ae15e16 | 254 | mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); |
225c7b1f RD |
255 | |
256 | err_db: | |
257 | if (!context) | |
6296883c | 258 | mlx4_db_free(dev->dev, &cq->db); |
225c7b1f RD |
259 | |
260 | err_cq: | |
261 | kfree(cq); | |
262 | ||
263 | return ERR_PTR(err); | |
264 | } | |
265 | ||
bbf8eed1 VS |
266 | static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, |
267 | int entries) | |
268 | { | |
269 | int err; | |
270 | ||
271 | if (cq->resize_buf) | |
272 | return -EBUSY; | |
273 | ||
274 | cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC); | |
275 | if (!cq->resize_buf) | |
276 | return -ENOMEM; | |
277 | ||
278 | err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); | |
279 | if (err) { | |
280 | kfree(cq->resize_buf); | |
281 | cq->resize_buf = NULL; | |
282 | return err; | |
283 | } | |
284 | ||
285 | cq->resize_buf->cqe = entries - 1; | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
290 | static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq, | |
291 | int entries, struct ib_udata *udata) | |
292 | { | |
293 | struct mlx4_ib_resize_cq ucmd; | |
294 | int err; | |
295 | ||
296 | if (cq->resize_umem) | |
297 | return -EBUSY; | |
298 | ||
299 | if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) | |
300 | return -EFAULT; | |
301 | ||
302 | cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC); | |
303 | if (!cq->resize_buf) | |
304 | return -ENOMEM; | |
305 | ||
306 | err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf, | |
307 | &cq->resize_umem, ucmd.buf_addr, entries); | |
308 | if (err) { | |
309 | kfree(cq->resize_buf); | |
310 | cq->resize_buf = NULL; | |
311 | return err; | |
312 | } | |
313 | ||
314 | cq->resize_buf->cqe = entries - 1; | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq) | |
320 | { | |
321 | u32 i; | |
322 | ||
323 | i = cq->mcq.cons_index; | |
324 | while (get_sw_cqe(cq, i & cq->ibcq.cqe)) | |
325 | ++i; | |
326 | ||
327 | return i - cq->mcq.cons_index; | |
328 | } | |
329 | ||
330 | static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq) | |
331 | { | |
7798dbf4 | 332 | struct mlx4_cqe *cqe, *new_cqe; |
bbf8eed1 VS |
333 | int i; |
334 | ||
335 | i = cq->mcq.cons_index; | |
336 | cqe = get_cqe(cq, i & cq->ibcq.cqe); | |
337 | while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) { | |
7798dbf4 JM |
338 | new_cqe = get_cqe_from_buf(&cq->resize_buf->buf, |
339 | (i + 1) & cq->resize_buf->cqe); | |
340 | memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), sizeof(struct mlx4_cqe)); | |
341 | new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) | | |
342 | (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0); | |
bbf8eed1 VS |
343 | cqe = get_cqe(cq, ++i & cq->ibcq.cqe); |
344 | } | |
345 | ++cq->mcq.cons_index; | |
346 | } | |
347 | ||
348 | int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) | |
349 | { | |
350 | struct mlx4_ib_dev *dev = to_mdev(ibcq->device); | |
351 | struct mlx4_ib_cq *cq = to_mcq(ibcq); | |
42ab01c3 | 352 | struct mlx4_mtt mtt; |
bbf8eed1 VS |
353 | int outst_cqe; |
354 | int err; | |
355 | ||
356 | mutex_lock(&cq->resize_mutex); | |
357 | ||
358 | if (entries < 1 || entries > dev->dev->caps.max_cqes) { | |
359 | err = -EINVAL; | |
360 | goto out; | |
361 | } | |
362 | ||
363 | entries = roundup_pow_of_two(entries + 1); | |
364 | if (entries == ibcq->cqe + 1) { | |
365 | err = 0; | |
366 | goto out; | |
367 | } | |
368 | ||
369 | if (ibcq->uobject) { | |
370 | err = mlx4_alloc_resize_umem(dev, cq, entries, udata); | |
371 | if (err) | |
372 | goto out; | |
373 | } else { | |
025dfdaf | 374 | /* Can't be smaller than the number of outstanding CQEs */ |
bbf8eed1 VS |
375 | outst_cqe = mlx4_ib_get_outstanding_cqes(cq); |
376 | if (entries < outst_cqe + 1) { | |
377 | err = 0; | |
378 | goto out; | |
379 | } | |
380 | ||
381 | err = mlx4_alloc_resize_buf(dev, cq, entries); | |
382 | if (err) | |
383 | goto out; | |
384 | } | |
385 | ||
42ab01c3 JM |
386 | mtt = cq->buf.mtt; |
387 | ||
bbf8eed1 VS |
388 | err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt); |
389 | if (err) | |
390 | goto err_buf; | |
391 | ||
42ab01c3 | 392 | mlx4_mtt_cleanup(dev->dev, &mtt); |
bbf8eed1 VS |
393 | if (ibcq->uobject) { |
394 | cq->buf = cq->resize_buf->buf; | |
395 | cq->ibcq.cqe = cq->resize_buf->cqe; | |
396 | ib_umem_release(cq->umem); | |
397 | cq->umem = cq->resize_umem; | |
398 | ||
399 | kfree(cq->resize_buf); | |
400 | cq->resize_buf = NULL; | |
401 | cq->resize_umem = NULL; | |
402 | } else { | |
3afa9f19 VS |
403 | struct mlx4_ib_cq_buf tmp_buf; |
404 | int tmp_cqe = 0; | |
405 | ||
bbf8eed1 VS |
406 | spin_lock_irq(&cq->lock); |
407 | if (cq->resize_buf) { | |
408 | mlx4_ib_cq_resize_copy_cqes(cq); | |
3afa9f19 VS |
409 | tmp_buf = cq->buf; |
410 | tmp_cqe = cq->ibcq.cqe; | |
bbf8eed1 VS |
411 | cq->buf = cq->resize_buf->buf; |
412 | cq->ibcq.cqe = cq->resize_buf->cqe; | |
413 | ||
414 | kfree(cq->resize_buf); | |
415 | cq->resize_buf = NULL; | |
416 | } | |
417 | spin_unlock_irq(&cq->lock); | |
3afa9f19 VS |
418 | |
419 | if (tmp_cqe) | |
420 | mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); | |
bbf8eed1 VS |
421 | } |
422 | ||
423 | goto out; | |
424 | ||
425 | err_buf: | |
42ab01c3 | 426 | mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt); |
bbf8eed1 VS |
427 | if (!ibcq->uobject) |
428 | mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf, | |
429 | cq->resize_buf->cqe); | |
430 | ||
431 | kfree(cq->resize_buf); | |
432 | cq->resize_buf = NULL; | |
433 | ||
434 | if (cq->resize_umem) { | |
435 | ib_umem_release(cq->resize_umem); | |
436 | cq->resize_umem = NULL; | |
437 | } | |
438 | ||
439 | out: | |
440 | mutex_unlock(&cq->resize_mutex); | |
441 | return err; | |
442 | } | |
443 | ||
225c7b1f RD |
444 | int mlx4_ib_destroy_cq(struct ib_cq *cq) |
445 | { | |
446 | struct mlx4_ib_dev *dev = to_mdev(cq->device); | |
447 | struct mlx4_ib_cq *mcq = to_mcq(cq); | |
448 | ||
449 | mlx4_cq_free(dev->dev, &mcq->mcq); | |
450 | mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt); | |
451 | ||
452 | if (cq->uobject) { | |
453 | mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db); | |
454 | ib_umem_release(mcq->umem); | |
455 | } else { | |
3ae15e16 | 456 | mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe); |
6296883c | 457 | mlx4_db_free(dev->dev, &mcq->db); |
225c7b1f RD |
458 | } |
459 | ||
460 | kfree(mcq); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static void dump_cqe(void *cqe) | |
466 | { | |
467 | __be32 *buf = cqe; | |
468 | ||
987c8f8f | 469 | pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", |
225c7b1f RD |
470 | be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]), |
471 | be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]), | |
472 | be32_to_cpu(buf[6]), be32_to_cpu(buf[7])); | |
473 | } | |
474 | ||
475 | static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, | |
476 | struct ib_wc *wc) | |
477 | { | |
478 | if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) { | |
987c8f8f | 479 | pr_debug("local QP operation err " |
225c7b1f RD |
480 | "(QPN %06x, WQE index %x, vendor syndrome %02x, " |
481 | "opcode = %02x)\n", | |
482 | be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index), | |
483 | cqe->vendor_err_syndrome, | |
484 | cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); | |
485 | dump_cqe(cqe); | |
486 | } | |
487 | ||
488 | switch (cqe->syndrome) { | |
489 | case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR: | |
490 | wc->status = IB_WC_LOC_LEN_ERR; | |
491 | break; | |
492 | case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR: | |
493 | wc->status = IB_WC_LOC_QP_OP_ERR; | |
494 | break; | |
495 | case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR: | |
496 | wc->status = IB_WC_LOC_PROT_ERR; | |
497 | break; | |
498 | case MLX4_CQE_SYNDROME_WR_FLUSH_ERR: | |
499 | wc->status = IB_WC_WR_FLUSH_ERR; | |
500 | break; | |
501 | case MLX4_CQE_SYNDROME_MW_BIND_ERR: | |
502 | wc->status = IB_WC_MW_BIND_ERR; | |
503 | break; | |
504 | case MLX4_CQE_SYNDROME_BAD_RESP_ERR: | |
505 | wc->status = IB_WC_BAD_RESP_ERR; | |
506 | break; | |
507 | case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR: | |
508 | wc->status = IB_WC_LOC_ACCESS_ERR; | |
509 | break; | |
510 | case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR: | |
511 | wc->status = IB_WC_REM_INV_REQ_ERR; | |
512 | break; | |
513 | case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR: | |
514 | wc->status = IB_WC_REM_ACCESS_ERR; | |
515 | break; | |
516 | case MLX4_CQE_SYNDROME_REMOTE_OP_ERR: | |
517 | wc->status = IB_WC_REM_OP_ERR; | |
518 | break; | |
519 | case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR: | |
520 | wc->status = IB_WC_RETRY_EXC_ERR; | |
521 | break; | |
522 | case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR: | |
523 | wc->status = IB_WC_RNR_RETRY_EXC_ERR; | |
524 | break; | |
525 | case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR: | |
526 | wc->status = IB_WC_REM_ABORT_ERR; | |
527 | break; | |
528 | default: | |
529 | wc->status = IB_WC_GENERAL_ERR; | |
530 | break; | |
531 | } | |
532 | ||
533 | wc->vendor_err = cqe->vendor_err_syndrome; | |
534 | } | |
535 | ||
f780a9f1 | 536 | static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) |
8ff095ec | 537 | { |
f780a9f1 YP |
538 | return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | |
539 | MLX4_CQE_STATUS_IPV4F | | |
540 | MLX4_CQE_STATUS_IPV4OPT | | |
541 | MLX4_CQE_STATUS_IPV6 | | |
542 | MLX4_CQE_STATUS_IPOK)) == | |
543 | cpu_to_be16(MLX4_CQE_STATUS_IPV4 | | |
544 | MLX4_CQE_STATUS_IPOK)) && | |
545 | (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | | |
546 | MLX4_CQE_STATUS_TCP)) && | |
8ff095ec EC |
547 | checksum == cpu_to_be16(0xffff); |
548 | } | |
549 | ||
1ffeb2eb JM |
550 | static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc, |
551 | unsigned tail, struct mlx4_cqe *cqe) | |
552 | { | |
553 | struct mlx4_ib_proxy_sqp_hdr *hdr; | |
554 | ||
555 | ib_dma_sync_single_for_cpu(qp->ibqp.device, | |
556 | qp->sqp_proxy_rcv[tail].map, | |
557 | sizeof (struct mlx4_ib_proxy_sqp_hdr), | |
558 | DMA_FROM_DEVICE); | |
559 | hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr); | |
560 | wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index); | |
561 | wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32); | |
562 | wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12); | |
563 | wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF; | |
564 | wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0; | |
565 | wc->dlid_path_bits = 0; | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
225c7b1f RD |
570 | static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, |
571 | struct mlx4_ib_qp **cur_qp, | |
572 | struct ib_wc *wc) | |
573 | { | |
574 | struct mlx4_cqe *cqe; | |
575 | struct mlx4_qp *mqp; | |
576 | struct mlx4_ib_wq *wq; | |
577 | struct mlx4_ib_srq *srq; | |
578 | int is_send; | |
579 | int is_error; | |
b3226184 | 580 | u32 g_mlpath_rqpn; |
225c7b1f | 581 | u16 wqe_ctr; |
1ffeb2eb | 582 | unsigned tail = 0; |
225c7b1f | 583 | |
bbf8eed1 | 584 | repoll: |
225c7b1f RD |
585 | cqe = next_cqe_sw(cq); |
586 | if (!cqe) | |
587 | return -EAGAIN; | |
588 | ||
589 | ++cq->mcq.cons_index; | |
590 | ||
591 | /* | |
592 | * Make sure we read CQ entry contents after we've checked the | |
593 | * ownership bit. | |
594 | */ | |
595 | rmb(); | |
596 | ||
597 | is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK; | |
598 | is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
599 | MLX4_CQE_OPCODE_ERROR; | |
600 | ||
ea54b10c JM |
601 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP && |
602 | is_send)) { | |
987c8f8f | 603 | pr_warn("Completion for NOP opcode detected!\n"); |
ea54b10c JM |
604 | return -EINVAL; |
605 | } | |
606 | ||
bbf8eed1 VS |
607 | /* Resize CQ in progress */ |
608 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) { | |
609 | if (cq->resize_buf) { | |
610 | struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device); | |
611 | ||
612 | mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); | |
613 | cq->buf = cq->resize_buf->buf; | |
614 | cq->ibcq.cqe = cq->resize_buf->cqe; | |
615 | ||
616 | kfree(cq->resize_buf); | |
617 | cq->resize_buf = NULL; | |
618 | } | |
619 | ||
620 | goto repoll; | |
621 | } | |
622 | ||
225c7b1f | 623 | if (!*cur_qp || |
f780a9f1 | 624 | (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { |
225c7b1f RD |
625 | /* |
626 | * We do not have to take the QP table lock here, | |
627 | * because CQs will be locked while QPs are removed | |
628 | * from the table. | |
629 | */ | |
630 | mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, | |
f780a9f1 | 631 | be32_to_cpu(cqe->vlan_my_qpn)); |
225c7b1f | 632 | if (unlikely(!mqp)) { |
987c8f8f | 633 | pr_warn("CQ %06x with entry for unknown QPN %06x\n", |
f780a9f1 | 634 | cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK); |
225c7b1f RD |
635 | return -EINVAL; |
636 | } | |
637 | ||
638 | *cur_qp = to_mibqp(mqp); | |
639 | } | |
640 | ||
641 | wc->qp = &(*cur_qp)->ibqp; | |
642 | ||
643 | if (is_send) { | |
644 | wq = &(*cur_qp)->sq; | |
ea54b10c JM |
645 | if (!(*cur_qp)->sq_signal_bits) { |
646 | wqe_ctr = be16_to_cpu(cqe->wqe_index); | |
647 | wq->tail += (u16) (wqe_ctr - (u16) wq->tail); | |
648 | } | |
0e6e7416 | 649 | wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; |
225c7b1f RD |
650 | ++wq->tail; |
651 | } else if ((*cur_qp)->ibqp.srq) { | |
652 | srq = to_msrq((*cur_qp)->ibqp.srq); | |
653 | wqe_ctr = be16_to_cpu(cqe->wqe_index); | |
654 | wc->wr_id = srq->wrid[wqe_ctr]; | |
655 | mlx4_ib_free_srq_wqe(srq, wqe_ctr); | |
656 | } else { | |
657 | wq = &(*cur_qp)->rq; | |
1ffeb2eb JM |
658 | tail = wq->tail & (wq->wqe_cnt - 1); |
659 | wc->wr_id = wq->wrid[tail]; | |
225c7b1f RD |
660 | ++wq->tail; |
661 | } | |
662 | ||
663 | if (unlikely(is_error)) { | |
664 | mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc); | |
665 | return 0; | |
666 | } | |
667 | ||
668 | wc->status = IB_WC_SUCCESS; | |
669 | ||
670 | if (is_send) { | |
671 | wc->wc_flags = 0; | |
672 | switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { | |
673 | case MLX4_OPCODE_RDMA_WRITE_IMM: | |
674 | wc->wc_flags |= IB_WC_WITH_IMM; | |
675 | case MLX4_OPCODE_RDMA_WRITE: | |
676 | wc->opcode = IB_WC_RDMA_WRITE; | |
677 | break; | |
678 | case MLX4_OPCODE_SEND_IMM: | |
679 | wc->wc_flags |= IB_WC_WITH_IMM; | |
680 | case MLX4_OPCODE_SEND: | |
95d04f07 | 681 | case MLX4_OPCODE_SEND_INVAL: |
225c7b1f RD |
682 | wc->opcode = IB_WC_SEND; |
683 | break; | |
684 | case MLX4_OPCODE_RDMA_READ: | |
19891915 | 685 | wc->opcode = IB_WC_RDMA_READ; |
225c7b1f RD |
686 | wc->byte_len = be32_to_cpu(cqe->byte_cnt); |
687 | break; | |
688 | case MLX4_OPCODE_ATOMIC_CS: | |
689 | wc->opcode = IB_WC_COMP_SWAP; | |
690 | wc->byte_len = 8; | |
691 | break; | |
692 | case MLX4_OPCODE_ATOMIC_FA: | |
693 | wc->opcode = IB_WC_FETCH_ADD; | |
694 | wc->byte_len = 8; | |
695 | break; | |
6fa8f719 VS |
696 | case MLX4_OPCODE_MASKED_ATOMIC_CS: |
697 | wc->opcode = IB_WC_MASKED_COMP_SWAP; | |
698 | wc->byte_len = 8; | |
699 | break; | |
700 | case MLX4_OPCODE_MASKED_ATOMIC_FA: | |
701 | wc->opcode = IB_WC_MASKED_FETCH_ADD; | |
702 | wc->byte_len = 8; | |
703 | break; | |
225c7b1f RD |
704 | case MLX4_OPCODE_BIND_MW: |
705 | wc->opcode = IB_WC_BIND_MW; | |
706 | break; | |
b832be1e EC |
707 | case MLX4_OPCODE_LSO: |
708 | wc->opcode = IB_WC_LSO; | |
709 | break; | |
95d04f07 RD |
710 | case MLX4_OPCODE_FMR: |
711 | wc->opcode = IB_WC_FAST_REG_MR; | |
712 | break; | |
713 | case MLX4_OPCODE_LOCAL_INVAL: | |
714 | wc->opcode = IB_WC_LOCAL_INV; | |
715 | break; | |
225c7b1f RD |
716 | } |
717 | } else { | |
718 | wc->byte_len = be32_to_cpu(cqe->byte_cnt); | |
719 | ||
720 | switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) { | |
721 | case MLX4_RECV_OPCODE_RDMA_WRITE_IMM: | |
00f7ec36 SW |
722 | wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; |
723 | wc->wc_flags = IB_WC_WITH_IMM; | |
724 | wc->ex.imm_data = cqe->immed_rss_invalid; | |
225c7b1f | 725 | break; |
95d04f07 RD |
726 | case MLX4_RECV_OPCODE_SEND_INVAL: |
727 | wc->opcode = IB_WC_RECV; | |
728 | wc->wc_flags = IB_WC_WITH_INVALIDATE; | |
729 | wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid); | |
730 | break; | |
225c7b1f RD |
731 | case MLX4_RECV_OPCODE_SEND: |
732 | wc->opcode = IB_WC_RECV; | |
733 | wc->wc_flags = 0; | |
734 | break; | |
735 | case MLX4_RECV_OPCODE_SEND_IMM: | |
00f7ec36 SW |
736 | wc->opcode = IB_WC_RECV; |
737 | wc->wc_flags = IB_WC_WITH_IMM; | |
738 | wc->ex.imm_data = cqe->immed_rss_invalid; | |
225c7b1f RD |
739 | break; |
740 | } | |
741 | ||
1ffeb2eb JM |
742 | if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) { |
743 | if ((*cur_qp)->mlx4_ib_qp_type & | |
744 | (MLX4_IB_QPT_PROXY_SMI_OWNER | | |
745 | MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) | |
746 | return use_tunnel_data(*cur_qp, cq, wc, tail, cqe); | |
747 | } | |
748 | ||
225c7b1f | 749 | wc->slid = be16_to_cpu(cqe->rlid); |
b3226184 RD |
750 | g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); |
751 | wc->src_qp = g_mlpath_rqpn & 0xffffff; | |
752 | wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; | |
753 | wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; | |
e1bb7843 | 754 | wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; |
d927d505 OG |
755 | wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status, |
756 | cqe->checksum) ? IB_WC_IP_CSUM_OK : 0; | |
9106c410 OG |
757 | if (rdma_port_get_link_layer(wc->qp->device, |
758 | (*cur_qp)->port) == IB_LINK_LAYER_ETHERNET) | |
759 | wc->sl = be16_to_cpu(cqe->sl_vid) >> 13; | |
760 | else | |
761 | wc->sl = be16_to_cpu(cqe->sl_vid) >> 12; | |
225c7b1f RD |
762 | } |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
767 | int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) | |
768 | { | |
769 | struct mlx4_ib_cq *cq = to_mcq(ibcq); | |
770 | struct mlx4_ib_qp *cur_qp = NULL; | |
771 | unsigned long flags; | |
772 | int npolled; | |
773 | int err = 0; | |
774 | ||
775 | spin_lock_irqsave(&cq->lock, flags); | |
776 | ||
777 | for (npolled = 0; npolled < num_entries; ++npolled) { | |
778 | err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled); | |
779 | if (err) | |
780 | break; | |
781 | } | |
782 | ||
3616f9ce | 783 | mlx4_cq_set_ci(&cq->mcq); |
225c7b1f RD |
784 | |
785 | spin_unlock_irqrestore(&cq->lock, flags); | |
786 | ||
787 | if (err == 0 || err == -EAGAIN) | |
788 | return npolled; | |
789 | else | |
790 | return err; | |
791 | } | |
792 | ||
793 | int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) | |
794 | { | |
795 | mlx4_cq_arm(&to_mcq(ibcq)->mcq, | |
796 | (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? | |
797 | MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT, | |
798 | to_mdev(ibcq->device)->uar_map, | |
799 | MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock)); | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
804 | void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) | |
805 | { | |
806 | u32 prod_index; | |
807 | int nfreed = 0; | |
082dee32 JM |
808 | struct mlx4_cqe *cqe, *dest; |
809 | u8 owner_bit; | |
225c7b1f RD |
810 | |
811 | /* | |
812 | * First we need to find the current producer index, so we | |
813 | * know where to start cleaning from. It doesn't matter if HW | |
814 | * adds new entries after this loop -- the QP we're worried | |
815 | * about is already in RESET, so the new entries won't come | |
816 | * from our QP and therefore don't need to be checked. | |
817 | */ | |
818 | for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index) | |
819 | if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe) | |
820 | break; | |
821 | ||
822 | /* | |
823 | * Now sweep backwards through the CQ, removing CQ entries | |
824 | * that match our QP by copying older entries on top of them. | |
825 | */ | |
826 | while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { | |
827 | cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); | |
f780a9f1 | 828 | if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { |
225c7b1f RD |
829 | if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) |
830 | mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); | |
831 | ++nfreed; | |
082dee32 JM |
832 | } else if (nfreed) { |
833 | dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe); | |
834 | owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK; | |
835 | memcpy(dest, cqe, sizeof *cqe); | |
836 | dest->owner_sr_opcode = owner_bit | | |
837 | (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK); | |
838 | } | |
225c7b1f RD |
839 | } |
840 | ||
841 | if (nfreed) { | |
842 | cq->mcq.cons_index += nfreed; | |
843 | /* | |
844 | * Make sure update of buffer contents is done before | |
845 | * updating consumer index. | |
846 | */ | |
847 | wmb(); | |
848 | mlx4_cq_set_ci(&cq->mcq); | |
849 | } | |
850 | } | |
851 | ||
852 | void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) | |
853 | { | |
854 | spin_lock_irq(&cq->lock); | |
855 | __mlx4_ib_cq_clean(cq, qpn, srq); | |
856 | spin_unlock_irq(&cq->lock); | |
857 | } |