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d41d3aeb | 1 | /* |
759d5768 | 2 | * Copyright (c) 2006 QLogic, Inc. All rights reserved. |
d41d3aeb BS |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #ifndef _IPATH_REGISTERS_H | |
35 | #define _IPATH_REGISTERS_H | |
36 | ||
37 | /* | |
f6f0413e | 38 | * This file should only be included by kernel source, and by the diags. It |
525d0ca1 | 39 | * defines the registers, and their contents, for InfiniPath chips. |
d41d3aeb BS |
40 | */ |
41 | ||
42 | /* | |
43 | * These are the InfiniPath register and buffer bit definitions, | |
44 | * that are visible to software, and needed only by the kernel | |
45 | * and diag code. A few, that are visible to protocol and user | |
46 | * code are in ipath_common.h. Some bits are specific | |
47 | * to a given chip implementation, and have been moved to the | |
48 | * chip-specific source file | |
49 | */ | |
50 | ||
51 | /* kr_revision bits */ | |
52 | #define INFINIPATH_R_CHIPREVMINOR_MASK 0xFF | |
53 | #define INFINIPATH_R_CHIPREVMINOR_SHIFT 0 | |
54 | #define INFINIPATH_R_CHIPREVMAJOR_MASK 0xFF | |
55 | #define INFINIPATH_R_CHIPREVMAJOR_SHIFT 8 | |
56 | #define INFINIPATH_R_ARCH_MASK 0xFF | |
57 | #define INFINIPATH_R_ARCH_SHIFT 16 | |
58 | #define INFINIPATH_R_SOFTWARE_MASK 0xFF | |
59 | #define INFINIPATH_R_SOFTWARE_SHIFT 24 | |
60 | #define INFINIPATH_R_BOARDID_MASK 0xFF | |
61 | #define INFINIPATH_R_BOARDID_SHIFT 32 | |
62 | ||
63 | /* kr_control bits */ | |
64 | #define INFINIPATH_C_FREEZEMODE 0x00000002 | |
65 | #define INFINIPATH_C_LINKENABLE 0x00000004 | |
66 | #define INFINIPATH_C_RESET 0x00000001 | |
67 | ||
68 | /* kr_sendctrl bits */ | |
69 | #define INFINIPATH_S_DISARMPIOBUF_SHIFT 16 | |
70 | ||
71 | #define IPATH_S_ABORT 0 | |
72 | #define IPATH_S_PIOINTBUFAVAIL 1 | |
73 | #define IPATH_S_PIOBUFAVAILUPD 2 | |
74 | #define IPATH_S_PIOENABLE 3 | |
75 | #define IPATH_S_DISARM 31 | |
76 | ||
77 | #define INFINIPATH_S_ABORT (1U << IPATH_S_ABORT) | |
78 | #define INFINIPATH_S_PIOINTBUFAVAIL (1U << IPATH_S_PIOINTBUFAVAIL) | |
79 | #define INFINIPATH_S_PIOBUFAVAILUPD (1U << IPATH_S_PIOBUFAVAILUPD) | |
80 | #define INFINIPATH_S_PIOENABLE (1U << IPATH_S_PIOENABLE) | |
81 | #define INFINIPATH_S_DISARM (1U << IPATH_S_DISARM) | |
82 | ||
83 | /* kr_rcvctrl bits */ | |
84 | #define INFINIPATH_R_PORTENABLE_SHIFT 0 | |
85 | #define INFINIPATH_R_INTRAVAIL_SHIFT 16 | |
86 | #define INFINIPATH_R_TAILUPD 0x80000000 | |
87 | ||
88 | /* kr_intstatus, kr_intclear, kr_intmask bits */ | |
89 | #define INFINIPATH_I_RCVURG_SHIFT 0 | |
90 | #define INFINIPATH_I_RCVAVAIL_SHIFT 12 | |
91 | #define INFINIPATH_I_ERROR 0x80000000 | |
92 | #define INFINIPATH_I_SPIOSENT 0x40000000 | |
93 | #define INFINIPATH_I_SPIOBUFAVAIL 0x20000000 | |
94 | #define INFINIPATH_I_GPIO 0x10000000 | |
95 | ||
96 | /* kr_errorstatus, kr_errorclear, kr_errormask bits */ | |
97 | #define INFINIPATH_E_RFORMATERR 0x0000000000000001ULL | |
98 | #define INFINIPATH_E_RVCRC 0x0000000000000002ULL | |
99 | #define INFINIPATH_E_RICRC 0x0000000000000004ULL | |
100 | #define INFINIPATH_E_RMINPKTLEN 0x0000000000000008ULL | |
101 | #define INFINIPATH_E_RMAXPKTLEN 0x0000000000000010ULL | |
102 | #define INFINIPATH_E_RLONGPKTLEN 0x0000000000000020ULL | |
103 | #define INFINIPATH_E_RSHORTPKTLEN 0x0000000000000040ULL | |
104 | #define INFINIPATH_E_RUNEXPCHAR 0x0000000000000080ULL | |
105 | #define INFINIPATH_E_RUNSUPVL 0x0000000000000100ULL | |
106 | #define INFINIPATH_E_REBP 0x0000000000000200ULL | |
107 | #define INFINIPATH_E_RIBFLOW 0x0000000000000400ULL | |
108 | #define INFINIPATH_E_RBADVERSION 0x0000000000000800ULL | |
109 | #define INFINIPATH_E_RRCVEGRFULL 0x0000000000001000ULL | |
110 | #define INFINIPATH_E_RRCVHDRFULL 0x0000000000002000ULL | |
111 | #define INFINIPATH_E_RBADTID 0x0000000000004000ULL | |
112 | #define INFINIPATH_E_RHDRLEN 0x0000000000008000ULL | |
113 | #define INFINIPATH_E_RHDR 0x0000000000010000ULL | |
114 | #define INFINIPATH_E_RIBLOSTLINK 0x0000000000020000ULL | |
115 | #define INFINIPATH_E_SMINPKTLEN 0x0000000020000000ULL | |
116 | #define INFINIPATH_E_SMAXPKTLEN 0x0000000040000000ULL | |
117 | #define INFINIPATH_E_SUNDERRUN 0x0000000080000000ULL | |
118 | #define INFINIPATH_E_SPKTLEN 0x0000000100000000ULL | |
119 | #define INFINIPATH_E_SDROPPEDSMPPKT 0x0000000200000000ULL | |
120 | #define INFINIPATH_E_SDROPPEDDATAPKT 0x0000000400000000ULL | |
121 | #define INFINIPATH_E_SPIOARMLAUNCH 0x0000000800000000ULL | |
122 | #define INFINIPATH_E_SUNEXPERRPKTNUM 0x0000001000000000ULL | |
123 | #define INFINIPATH_E_SUNSUPVL 0x0000002000000000ULL | |
124 | #define INFINIPATH_E_IBSTATUSCHANGED 0x0001000000000000ULL | |
125 | #define INFINIPATH_E_INVALIDADDR 0x0002000000000000ULL | |
126 | #define INFINIPATH_E_RESET 0x0004000000000000ULL | |
127 | #define INFINIPATH_E_HARDWARE 0x0008000000000000ULL | |
128 | ||
129 | /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */ | |
130 | /* TXEMEMPARITYERR bit 0: PIObuf, 1: PIOpbc, 2: launchfifo | |
131 | * RXEMEMPARITYERR bit 0: rcvbuf, 1: lookupq, 2: eagerTID, 3: expTID | |
132 | * bit 4: flag buffer, 5: datainfo, 6: header info */ | |
133 | #define INFINIPATH_HWE_TXEMEMPARITYERR_MASK 0xFULL | |
134 | #define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40 | |
135 | #define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL | |
136 | #define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44 | |
137 | #define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL | |
138 | #define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL | |
139 | #define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL | |
140 | #define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL | |
141 | ||
142 | /* kr_hwdiagctrl bits */ | |
143 | #define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL | |
144 | #define INFINIPATH_DC_FORCETXEMEMPARITYERR_SHIFT 40 | |
145 | #define INFINIPATH_DC_FORCERXEMEMPARITYERR_MASK 0x7FULL | |
146 | #define INFINIPATH_DC_FORCERXEMEMPARITYERR_SHIFT 44 | |
147 | #define INFINIPATH_DC_FORCERXDSYNCMEMPARITYERR 0x0000000400000000ULL | |
148 | #define INFINIPATH_DC_COUNTERDISABLE 0x1000000000000000ULL | |
149 | #define INFINIPATH_DC_COUNTERWREN 0x2000000000000000ULL | |
150 | #define INFINIPATH_DC_FORCEIBCBUSTOSPCPARITYERR 0x4000000000000000ULL | |
151 | #define INFINIPATH_DC_FORCEIBCBUSFRSPCPARITYERR 0x8000000000000000ULL | |
152 | ||
153 | /* kr_ibcctrl bits */ | |
154 | #define INFINIPATH_IBCC_FLOWCTRLPERIOD_MASK 0xFFULL | |
155 | #define INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT 0 | |
156 | #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_MASK 0xFFULL | |
157 | #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8 | |
158 | #define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL | |
159 | #define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1 | |
f6f0413e BS |
160 | /* cycle through TS1/TS2 till OK */ |
161 | #define INFINIPATH_IBCC_LINKINITCMD_POLL 2 | |
162 | /* wait for TS1, then go on */ | |
163 | #define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3 | |
d41d3aeb BS |
164 | #define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16 |
165 | #define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL | |
166 | #define INFINIPATH_IBCC_LINKCMD_INIT 1 /* move to 0x11 */ | |
167 | #define INFINIPATH_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */ | |
168 | #define INFINIPATH_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */ | |
169 | #define INFINIPATH_IBCC_LINKCMD_SHIFT 18 | |
170 | #define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL | |
171 | #define INFINIPATH_IBCC_MAXPKTLEN_SHIFT 20 | |
172 | #define INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK 0xFULL | |
173 | #define INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT 32 | |
174 | #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_MASK 0xFULL | |
175 | #define INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT 36 | |
176 | #define INFINIPATH_IBCC_CREDITSCALE_MASK 0x7ULL | |
177 | #define INFINIPATH_IBCC_CREDITSCALE_SHIFT 40 | |
178 | #define INFINIPATH_IBCC_LOOPBACK 0x8000000000000000ULL | |
179 | #define INFINIPATH_IBCC_LINKDOWNDEFAULTSTATE 0x4000000000000000ULL | |
180 | ||
181 | /* kr_ibcstatus bits */ | |
182 | #define INFINIPATH_IBCS_LINKTRAININGSTATE_MASK 0xF | |
183 | #define INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT 0 | |
184 | #define INFINIPATH_IBCS_LINKSTATE_MASK 0x7 | |
185 | #define INFINIPATH_IBCS_LINKSTATE_SHIFT 4 | |
186 | #define INFINIPATH_IBCS_TXREADY 0x40000000 | |
187 | #define INFINIPATH_IBCS_TXCREDITOK 0x80000000 | |
f6f0413e BS |
188 | /* link training states (shift by |
189 | INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */ | |
d41d3aeb BS |
190 | #define INFINIPATH_IBCS_LT_STATE_DISABLED 0x00 |
191 | #define INFINIPATH_IBCS_LT_STATE_LINKUP 0x01 | |
192 | #define INFINIPATH_IBCS_LT_STATE_POLLACTIVE 0x02 | |
193 | #define INFINIPATH_IBCS_LT_STATE_POLLQUIET 0x03 | |
194 | #define INFINIPATH_IBCS_LT_STATE_SLEEPDELAY 0x04 | |
195 | #define INFINIPATH_IBCS_LT_STATE_SLEEPQUIET 0x05 | |
196 | #define INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE 0x08 | |
197 | #define INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG 0x09 | |
198 | #define INFINIPATH_IBCS_LT_STATE_CFGWAITRMT 0x0a | |
199 | #define INFINIPATH_IBCS_LT_STATE_CFGIDLE 0x0b | |
200 | #define INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN 0x0c | |
201 | #define INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT 0x0e | |
202 | #define INFINIPATH_IBCS_LT_STATE_RECOVERIDLE 0x0f | |
203 | /* link state machine states (shift by INFINIPATH_IBCS_LINKSTATE_SHIFT) */ | |
204 | #define INFINIPATH_IBCS_L_STATE_DOWN 0x0 | |
205 | #define INFINIPATH_IBCS_L_STATE_INIT 0x1 | |
206 | #define INFINIPATH_IBCS_L_STATE_ARM 0x2 | |
207 | #define INFINIPATH_IBCS_L_STATE_ACTIVE 0x3 | |
208 | #define INFINIPATH_IBCS_L_STATE_ACT_DEFER 0x4 | |
209 | ||
210 | /* combination link status states that we use with some frequency */ | |
211 | #define IPATH_IBSTATE_MASK ((INFINIPATH_IBCS_LINKTRAININGSTATE_MASK \ | |
212 | << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \ | |
213 | (INFINIPATH_IBCS_LINKSTATE_MASK \ | |
214 | <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)) | |
215 | #define IPATH_IBSTATE_INIT ((INFINIPATH_IBCS_L_STATE_INIT \ | |
216 | << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \ | |
217 | (INFINIPATH_IBCS_LT_STATE_LINKUP \ | |
218 | <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)) | |
219 | #define IPATH_IBSTATE_ARM ((INFINIPATH_IBCS_L_STATE_ARM \ | |
220 | << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \ | |
221 | (INFINIPATH_IBCS_LT_STATE_LINKUP \ | |
222 | <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)) | |
223 | #define IPATH_IBSTATE_ACTIVE ((INFINIPATH_IBCS_L_STATE_ACTIVE \ | |
224 | << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \ | |
225 | (INFINIPATH_IBCS_LT_STATE_LINKUP \ | |
226 | <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)) | |
227 | ||
228 | /* kr_extstatus bits */ | |
229 | #define INFINIPATH_EXTS_SERDESPLLLOCK 0x1 | |
230 | #define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL | |
231 | #define INFINIPATH_EXTS_GPIOIN_SHIFT 48 | |
232 | ||
233 | /* kr_extctrl bits */ | |
234 | #define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL | |
235 | #define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32 | |
236 | #define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL | |
237 | #define INFINIPATH_EXTC_GPIOOE_SHIFT 48 | |
238 | #define INFINIPATH_EXTC_SERDESENABLE 0x80000000ULL | |
239 | #define INFINIPATH_EXTC_SERDESCONNECT 0x40000000ULL | |
240 | #define INFINIPATH_EXTC_SERDESENTRUNKING 0x20000000ULL | |
241 | #define INFINIPATH_EXTC_SERDESDISRXFIFO 0x10000000ULL | |
242 | #define INFINIPATH_EXTC_SERDESENPLPBK1 0x08000000ULL | |
243 | #define INFINIPATH_EXTC_SERDESENPLPBK2 0x04000000ULL | |
244 | #define INFINIPATH_EXTC_SERDESENENCDEC 0x02000000ULL | |
245 | #define INFINIPATH_EXTC_LED1SECPORT_ON 0x00000020ULL | |
246 | #define INFINIPATH_EXTC_LED2SECPORT_ON 0x00000010ULL | |
247 | #define INFINIPATH_EXTC_LED1PRIPORT_ON 0x00000008ULL | |
248 | #define INFINIPATH_EXTC_LED2PRIPORT_ON 0x00000004ULL | |
249 | #define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL | |
250 | #define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL | |
251 | ||
252 | /* kr_mdio bits */ | |
253 | #define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL | |
254 | #define INFINIPATH_MDIO_CLKDIV_SHIFT 32 | |
255 | #define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL | |
256 | #define INFINIPATH_MDIO_COMMAND_SHIFT 26 | |
257 | #define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL | |
258 | #define INFINIPATH_MDIO_DEVADDR_SHIFT 21 | |
259 | #define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL | |
260 | #define INFINIPATH_MDIO_REGADDR_SHIFT 16 | |
261 | #define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL | |
262 | #define INFINIPATH_MDIO_DATA_SHIFT 0 | |
263 | #define INFINIPATH_MDIO_CMDVALID 0x0000000040000000ULL | |
264 | #define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL | |
265 | ||
266 | /* kr_partitionkey bits */ | |
267 | #define INFINIPATH_PKEY_SIZE 16 | |
268 | #define INFINIPATH_PKEY_MASK 0xFFFF | |
269 | #define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF | |
270 | ||
271 | /* kr_serdesconfig0 bits */ | |
272 | #define INFINIPATH_SERDC0_RESET_MASK 0xfULL /* overal reset bits */ | |
273 | #define INFINIPATH_SERDC0_RESET_PLL 0x10000000ULL /* pll reset */ | |
f6f0413e BS |
274 | /* tx idle enables (per lane) */ |
275 | #define INFINIPATH_SERDC0_TXIDLE 0xF000ULL | |
276 | /* rx detect enables (per lane) */ | |
277 | #define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL | |
278 | /* L1 Power down; use with RXDETECT, Otherwise not used on IB side */ | |
279 | #define INFINIPATH_SERDC0_L1PWR_DN 0xF0ULL | |
d41d3aeb BS |
280 | |
281 | /* kr_xgxsconfig bits */ | |
282 | #define INFINIPATH_XGXS_RESET 0x7ULL | |
283 | #define INFINIPATH_XGXS_MDIOADDR_MASK 0xfULL | |
284 | #define INFINIPATH_XGXS_MDIOADDR_SHIFT 4 | |
285 | ||
286 | #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */ | |
287 | ||
525d0ca1 | 288 | /* TID entries (memory), HT-only */ |
d41d3aeb BS |
289 | #define INFINIPATH_RT_VALID 0x8000000000000000ULL |
290 | #define INFINIPATH_RT_ADDR_SHIFT 0 | |
291 | #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFF | |
292 | #define INFINIPATH_RT_BUFSIZE_SHIFT 48 | |
293 | ||
294 | /* | |
295 | * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our | |
296 | * PIO send buffers. This is well beyond anything currently | |
297 | * defined in the InfiniBand spec. | |
298 | */ | |
299 | #define IPATH_PIO_MAXIBHDR 128 | |
300 | ||
301 | typedef u64 ipath_err_t; | |
302 | ||
303 | /* mask of defined bits for various registers */ | |
304 | extern u64 infinipath_i_bitsextant; | |
305 | extern ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant; | |
306 | ||
307 | /* masks that are different in various chips, or only exist in some chips */ | |
308 | extern u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask; | |
309 | ||
310 | /* | |
311 | * register bits for selecting i2c direction and values, used for I2C serial | |
312 | * flash | |
313 | */ | |
314 | extern u16 ipath_gpio_sda_num, ipath_gpio_scl_num; | |
315 | extern u64 ipath_gpio_sda, ipath_gpio_scl; | |
316 | ||
317 | /* | |
318 | * These are the infinipath general register numbers (not offsets). | |
319 | * The kernel registers are used directly, those beyond the kernel | |
320 | * registers are calculated from one of the base registers. The use of | |
321 | * an integer type doesn't allow type-checking as thorough as, say, | |
322 | * an enum but allows for better hiding of chip differences. | |
323 | */ | |
324 | typedef const u16 ipath_kreg, /* infinipath general registers */ | |
325 | ipath_creg, /* infinipath counter registers */ | |
326 | ipath_sreg; /* kernel-only, infinipath send registers */ | |
327 | ||
328 | /* | |
329 | * These are the chip registers common to all infinipath chips, and | |
330 | * used both by the kernel and the diagnostics or other user code. | |
331 | * They are all implemented such that 64 bit accesses work. | |
332 | * Some implement no more than 32 bits. Because 64 bit reads | |
333 | * require 2 HT cmds on opteron, we access those with 32 bit | |
334 | * reads for efficiency (they are written as 64 bits, since | |
335 | * the extra 32 bits are nearly free on writes, and it slightly reduces | |
336 | * complexity). The rest are all accessed as 64 bits. | |
337 | */ | |
338 | struct ipath_kregs { | |
339 | /* These are the 32 bit group */ | |
340 | ipath_kreg kr_control; | |
341 | ipath_kreg kr_counterregbase; | |
342 | ipath_kreg kr_intmask; | |
343 | ipath_kreg kr_intstatus; | |
344 | ipath_kreg kr_pagealign; | |
345 | ipath_kreg kr_portcnt; | |
346 | ipath_kreg kr_rcvtidbase; | |
347 | ipath_kreg kr_rcvtidcnt; | |
348 | ipath_kreg kr_rcvegrbase; | |
349 | ipath_kreg kr_rcvegrcnt; | |
350 | ipath_kreg kr_scratch; | |
351 | ipath_kreg kr_sendctrl; | |
352 | ipath_kreg kr_sendpiobufbase; | |
353 | ipath_kreg kr_sendpiobufcnt; | |
354 | ipath_kreg kr_sendpiosize; | |
355 | ipath_kreg kr_sendregbase; | |
356 | ipath_kreg kr_userregbase; | |
357 | /* These are the 64 bit group */ | |
358 | ipath_kreg kr_debugport; | |
359 | ipath_kreg kr_debugportselect; | |
360 | ipath_kreg kr_errorclear; | |
361 | ipath_kreg kr_errormask; | |
362 | ipath_kreg kr_errorstatus; | |
363 | ipath_kreg kr_extctrl; | |
364 | ipath_kreg kr_extstatus; | |
365 | ipath_kreg kr_gpio_clear; | |
366 | ipath_kreg kr_gpio_mask; | |
367 | ipath_kreg kr_gpio_out; | |
368 | ipath_kreg kr_gpio_status; | |
369 | ipath_kreg kr_hwdiagctrl; | |
370 | ipath_kreg kr_hwerrclear; | |
371 | ipath_kreg kr_hwerrmask; | |
372 | ipath_kreg kr_hwerrstatus; | |
373 | ipath_kreg kr_ibcctrl; | |
374 | ipath_kreg kr_ibcstatus; | |
375 | ipath_kreg kr_intblocked; | |
376 | ipath_kreg kr_intclear; | |
377 | ipath_kreg kr_interruptconfig; | |
378 | ipath_kreg kr_mdio; | |
379 | ipath_kreg kr_partitionkey; | |
380 | ipath_kreg kr_rcvbthqp; | |
381 | ipath_kreg kr_rcvbufbase; | |
382 | ipath_kreg kr_rcvbufsize; | |
383 | ipath_kreg kr_rcvctrl; | |
384 | ipath_kreg kr_rcvhdrcnt; | |
385 | ipath_kreg kr_rcvhdrentsize; | |
386 | ipath_kreg kr_rcvhdrsize; | |
387 | ipath_kreg kr_rcvintmembase; | |
388 | ipath_kreg kr_rcvintmemsize; | |
389 | ipath_kreg kr_revision; | |
390 | ipath_kreg kr_sendbuffererror; | |
391 | ipath_kreg kr_sendpioavailaddr; | |
392 | ipath_kreg kr_serdesconfig0; | |
393 | ipath_kreg kr_serdesconfig1; | |
394 | ipath_kreg kr_serdesstatus; | |
395 | ipath_kreg kr_txintmembase; | |
396 | ipath_kreg kr_txintmemsize; | |
397 | ipath_kreg kr_xgxsconfig; | |
398 | ipath_kreg kr_ibpllcfg; | |
f6f0413e BS |
399 | /* use these two (and the following N ports) only with |
400 | * ipath_k*_kreg64_port(); not *kreg64() */ | |
d41d3aeb BS |
401 | ipath_kreg kr_rcvhdraddr; |
402 | ipath_kreg kr_rcvhdrtailaddr; | |
403 | ||
f6f0413e BS |
404 | /* remaining registers are not present on all types of infinipath |
405 | chips */ | |
d41d3aeb BS |
406 | ipath_kreg kr_rcvpktledcnt; |
407 | ipath_kreg kr_pcierbuftestreg0; | |
408 | ipath_kreg kr_pcierbuftestreg1; | |
409 | ipath_kreg kr_pcieq0serdesconfig0; | |
410 | ipath_kreg kr_pcieq0serdesconfig1; | |
411 | ipath_kreg kr_pcieq0serdesstatus; | |
412 | ipath_kreg kr_pcieq1serdesconfig0; | |
413 | ipath_kreg kr_pcieq1serdesconfig1; | |
414 | ipath_kreg kr_pcieq1serdesstatus; | |
415 | }; | |
416 | ||
417 | struct ipath_cregs { | |
418 | ipath_creg cr_badformatcnt; | |
419 | ipath_creg cr_erricrccnt; | |
420 | ipath_creg cr_errlinkcnt; | |
421 | ipath_creg cr_errlpcrccnt; | |
422 | ipath_creg cr_errpkey; | |
423 | ipath_creg cr_errrcvflowctrlcnt; | |
424 | ipath_creg cr_err_rlencnt; | |
425 | ipath_creg cr_errslencnt; | |
426 | ipath_creg cr_errtidfull; | |
427 | ipath_creg cr_errtidvalid; | |
428 | ipath_creg cr_errvcrccnt; | |
429 | ipath_creg cr_ibstatuschange; | |
430 | ipath_creg cr_intcnt; | |
431 | ipath_creg cr_invalidrlencnt; | |
432 | ipath_creg cr_invalidslencnt; | |
433 | ipath_creg cr_lbflowstallcnt; | |
434 | ipath_creg cr_iblinkdowncnt; | |
435 | ipath_creg cr_iblinkerrrecovcnt; | |
436 | ipath_creg cr_ibsymbolerrcnt; | |
437 | ipath_creg cr_pktrcvcnt; | |
438 | ipath_creg cr_pktrcvflowctrlcnt; | |
439 | ipath_creg cr_pktsendcnt; | |
440 | ipath_creg cr_pktsendflowcnt; | |
441 | ipath_creg cr_portovflcnt; | |
442 | ipath_creg cr_rcvebpcnt; | |
443 | ipath_creg cr_rcvovflcnt; | |
444 | ipath_creg cr_rxdroppktcnt; | |
445 | ipath_creg cr_senddropped; | |
446 | ipath_creg cr_sendstallcnt; | |
447 | ipath_creg cr_sendunderruncnt; | |
448 | ipath_creg cr_unsupvlcnt; | |
449 | ipath_creg cr_wordrcvcnt; | |
450 | ipath_creg cr_wordsendcnt; | |
451 | }; | |
452 | ||
453 | #endif /* _IPATH_REGISTERS_H */ |