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IB/ipath: account for attached QPs correctly
[linux-2.6-block.git] / drivers / infiniband / hw / ipath / ipath_pe800.c
CommitLineData
dc741bbd 1/*
759d5768 2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
dc741bbd
BS		 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
35 * InfiniPath PE-800 chip.
36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41
42
43#include "ipath_kernel.h"
44#include "ipath_registers.h"
45
46/*
47 * This file contains all the chip-specific register information and
759d5768 48 * access functions for the QLogic InfiniPath PE800, the PCI-Express chip.
dc741bbd
BS		 49 *
50 * This lists the InfiniPath PE800 registers, in the actual chip layout.
51 * This structure should never be directly accessed.
52 */
53struct _infinipath_do_not_use_kernel_regs {
54 unsigned long long Revision;
55 unsigned long long Control;
56 unsigned long long PageAlign;
57 unsigned long long PortCnt;
58 unsigned long long DebugPortSelect;
59 unsigned long long Reserved0;
60 unsigned long long SendRegBase;
61 unsigned long long UserRegBase;
62 unsigned long long CounterRegBase;
63 unsigned long long Scratch;
64 unsigned long long Reserved1;
65 unsigned long long Reserved2;
66 unsigned long long IntBlocked;
67 unsigned long long IntMask;
68 unsigned long long IntStatus;
69 unsigned long long IntClear;
70 unsigned long long ErrorMask;
71 unsigned long long ErrorStatus;
72 unsigned long long ErrorClear;
73 unsigned long long HwErrMask;
74 unsigned long long HwErrStatus;
75 unsigned long long HwErrClear;
76 unsigned long long HwDiagCtrl;
77 unsigned long long MDIO;
78 unsigned long long IBCStatus;
79 unsigned long long IBCCtrl;
80 unsigned long long ExtStatus;
81 unsigned long long ExtCtrl;
82 unsigned long long GPIOOut;
83 unsigned long long GPIOMask;
84 unsigned long long GPIOStatus;
85 unsigned long long GPIOClear;
86 unsigned long long RcvCtrl;
87 unsigned long long RcvBTHQP;
88 unsigned long long RcvHdrSize;
89 unsigned long long RcvHdrCnt;
90 unsigned long long RcvHdrEntSize;
91 unsigned long long RcvTIDBase;
92 unsigned long long RcvTIDCnt;
93 unsigned long long RcvEgrBase;
94 unsigned long long RcvEgrCnt;
95 unsigned long long RcvBufBase;
96 unsigned long long RcvBufSize;
97 unsigned long long RxIntMemBase;
98 unsigned long long RxIntMemSize;
99 unsigned long long RcvPartitionKey;
100 unsigned long long Reserved3;
101 unsigned long long RcvPktLEDCnt;
102 unsigned long long Reserved4[8];
103 unsigned long long SendCtrl;
104 unsigned long long SendPIOBufBase;
105 unsigned long long SendPIOSize;
106 unsigned long long SendPIOBufCnt;
107 unsigned long long SendPIOAvailAddr;
108 unsigned long long TxIntMemBase;
109 unsigned long long TxIntMemSize;
110 unsigned long long Reserved5;
111 unsigned long long PCIeRBufTestReg0;
112 unsigned long long PCIeRBufTestReg1;
113 unsigned long long Reserved51[6];
114 unsigned long long SendBufferError;
115 unsigned long long SendBufferErrorCONT1;
116 unsigned long long Reserved6SBE[6];
117 unsigned long long RcvHdrAddr0;
118 unsigned long long RcvHdrAddr1;
119 unsigned long long RcvHdrAddr2;
120 unsigned long long RcvHdrAddr3;
121 unsigned long long RcvHdrAddr4;
122 unsigned long long Reserved7RHA[11];
123 unsigned long long RcvHdrTailAddr0;
124 unsigned long long RcvHdrTailAddr1;
125 unsigned long long RcvHdrTailAddr2;
126 unsigned long long RcvHdrTailAddr3;
127 unsigned long long RcvHdrTailAddr4;
128 unsigned long long Reserved8RHTA[11];
129 unsigned long long Reserved9SW[8];
130 unsigned long long SerdesConfig0;
131 unsigned long long SerdesConfig1;
132 unsigned long long SerdesStatus;
133 unsigned long long XGXSConfig;
134 unsigned long long IBPLLCfg;
135 unsigned long long Reserved10SW2[3];
136 unsigned long long PCIEQ0SerdesConfig0;
137 unsigned long long PCIEQ0SerdesConfig1;
138 unsigned long long PCIEQ0SerdesStatus;
139 unsigned long long Reserved11;
140 unsigned long long PCIEQ1SerdesConfig0;
141 unsigned long long PCIEQ1SerdesConfig1;
142 unsigned long long PCIEQ1SerdesStatus;
143 unsigned long long Reserved12;
144};
145
146#define IPATH_KREG_OFFSET(field) (offsetof(struct \
147 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
148#define IPATH_CREG_OFFSET(field) (offsetof( \
149 struct infinipath_counters, field) / sizeof(u64))
150
151static const struct ipath_kregs ipath_pe_kregs = {
152 .kr_control = IPATH_KREG_OFFSET(Control),
153 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
154 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
155 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
156 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
157 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
158 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
159 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
160 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
161 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
162 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
163 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
164 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
165 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
166 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
167 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
168 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
169 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
170 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
171 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
172 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
173 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
174 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
175 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
176 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
177 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
178 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
179 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
180 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
181 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
182 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
183 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
184 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
185 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
186 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
187 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
188 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
189 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
190 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
191 .kr_revision = IPATH_KREG_OFFSET(Revision),
192 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
193 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
194 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
195 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
196 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
197 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
198 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
199 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
200 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
201 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
202 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
203 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
204 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
205 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
206 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
207 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
208
209 /*
210 * These should not be used directly via ipath_read_kreg64(),
211 * use them with ipath_read_kreg64_port()
212 */
213 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
214 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
215
216 /* This group is pe-800-specific; and used only in this file */
217 /* The rcvpktled register controls one of the debug port signals, so
218 * a packet activity LED can be connected to it. */
219 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
220 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
221 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
222 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
223 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
224 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
225 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
226 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
227 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
228};
229
230static const struct ipath_cregs ipath_pe_cregs = {
231 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
232 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
233 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
234 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
235 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
236 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
237 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
238 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
239 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
240 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
241 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
242 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
243 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
244 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
245 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
246 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
247 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
248 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
249 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
250 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
251 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
252 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
253 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
254 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
255 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
256 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
257 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
258 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
259 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
260 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
261 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
262 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
263 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
264};
265
266/* kr_intstatus, kr_intclear, kr_intmask bits */
267#define INFINIPATH_I_RCVURG_MASK 0x1F
268#define INFINIPATH_I_RCVAVAIL_MASK 0x1F
269
270/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
271#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
272#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
273#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
274#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
275#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
276#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
277#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
278#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
279#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
280#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
281#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
282#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
283
284/* kr_extstatus bits */
285#define INFINIPATH_EXTS_FREQSEL 0x2
286#define INFINIPATH_EXTS_SERDESSEL 0x4
287#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
288#define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
289
290#define _IPATH_GPIO_SDA_NUM 1
291#define _IPATH_GPIO_SCL_NUM 0
292
293#define IPATH_GPIO_SDA (1ULL << \
294 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
295#define IPATH_GPIO_SCL (1ULL << \
296 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
297
298/**
299 * ipath_pe_handle_hwerrors - display hardware errors.
300 * @dd: the infinipath device
301 * @msg: the output buffer
302 * @msgl: the size of the output buffer
303 *
304 * Use same msg buffer as regular errors to avoid excessive stack
305 * use. Most hardware errors are catastrophic, but for right now,
306 * we'll print them and continue. We reuse the same message buffer as
307 * ipath_handle_errors() to avoid excessive stack usage.
308 */
ac2ae4c9
RD		 309static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
310 size_t msgl)
dc741bbd
BS		 311{
312 ipath_err_t hwerrs;
313 u32 bits, ctrl;
314 int isfatal = 0;
315 char bitsmsg[64];
316
317 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
318 if (!hwerrs) {
319 /*
320 * better than printing cofusing messages
321 * This seems to be related to clearing the crc error, or
322 * the pll error during init.
323 */
324 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
325 return;
326 } else if (hwerrs == ~0ULL) {
327 ipath_dev_err(dd, "Read of hardware error status failed "
328 "(all bits set); ignoring\n");
329 return;
330 }
331 ipath_stats.sps_hwerrs++;
332
333 /* Always clear the error status register, except MEMBISTFAIL,
334 * regardless of whether we continue or stop using the chip.
335 * We want that set so we know it failed, even across driver reload.
336 * We'll still ignore it in the hwerrmask. We do this partly for
337 * diagnostics, but also for support */
338 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
339 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
340
341 hwerrs &= dd->ipath_hwerrmask;
342
343 /*
344 * make sure we get this much out, unless told to be quiet,
345 * or it's occurred within the last 5 seconds
346 */
347 if ((hwerrs & ~dd->ipath_lasthwerror) ||
348 (ipath_debug & __IPATH_VERBDBG))
349 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
350 "(cleared)\n", (unsigned long long) hwerrs);
351 dd->ipath_lasthwerror |= hwerrs;
352
353 if (hwerrs & ~infinipath_hwe_bitsextant)
354 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
355 "%llx set\n", (unsigned long long)
356 (hwerrs & ~infinipath_hwe_bitsextant));
357
358 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
359 if (ctrl & INFINIPATH_C_FREEZEMODE) {
360 if (hwerrs) {
361 /*
362 * if any set that we aren't ignoring only make the
363 * complaint once, in case it's stuck or recurring,
364 * and we get here multiple times
365 */
366 if (dd->ipath_flags & IPATH_INITTED) {
367 ipath_dev_err(dd, "Fatal Error (freeze "
368 "mode), no longer usable\n");
369 isfatal = 1;
370 }
371 /*
372 * Mark as having had an error for driver, and also
373 * for /sys and status word mapped to user programs.
374 * This marks unit as not usable, until reset
375 */
376 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
377 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
378 dd->ipath_flags &= ~IPATH_INITTED;
379 } else {
380 ipath_dbg("Clearing freezemode on ignored hardware "
381 "error\n");
382 ctrl &= ~INFINIPATH_C_FREEZEMODE;
383 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
384 ctrl);
385 }
386 }
387
388 *msg = '\0';
389
390 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
391 strlcat(msg, "[Memory BIST test failed, PE-800 unusable]",
392 msgl);
393 /* ignore from now on, so disable until driver reloaded */
394 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
395 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
396 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
397 dd->ipath_hwerrmask);
398 }
399 if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
400 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) {
401 bits = (u32) ((hwerrs >>
402 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) &
403 INFINIPATH_HWE_RXEMEMPARITYERR_MASK);
404 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ",
405 bits);
406 strlcat(msg, bitsmsg, msgl);
407 }
408 if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
409 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
410 bits = (u32) ((hwerrs >>
411 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
412 INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
413 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
414 bits);
415 strlcat(msg, bitsmsg, msgl);
416 }
417 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
418 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
419 bits = (u32) ((hwerrs >>
420 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
421 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
422 snprintf(bitsmsg, sizeof bitsmsg,
423 "[PCIe Mem Parity Errs %x] ", bits);
424 strlcat(msg, bitsmsg, msgl);
425 }
426 if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
427 strlcat(msg, "[IB2IPATH Parity]", msgl);
428 if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
429 strlcat(msg, "[IPATH2IB Parity]", msgl);
430
431#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
432 INFINIPATH_HWE_COREPLL_RFSLIP )
433
434 if (hwerrs & _IPATH_PLL_FAIL) {
435 snprintf(bitsmsg, sizeof bitsmsg,
436 "[PLL failed (%llx), PE-800 unusable]",
437 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
438 strlcat(msg, bitsmsg, msgl);
439 /* ignore from now on, so disable until driver reloaded */
440 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
441 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
442 dd->ipath_hwerrmask);
443 }
444
445 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
446 /*
447 * If it occurs, it is left masked since the eternal
448 * interface is unused
449 */
450 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
451 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
452 dd->ipath_hwerrmask);
453 }
454
455 if (hwerrs & INFINIPATH_HWE_PCIEPOISONEDTLP)
456 strlcat(msg, "[PCIe Poisoned TLP]", msgl);
457 if (hwerrs & INFINIPATH_HWE_PCIECPLTIMEOUT)
458 strlcat(msg, "[PCIe completion timeout]", msgl);
459
460 /*
461 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
462 * parity or memory parity error failures, because most likely we
463 * won't be able to talk to the core of the chip. Nonetheless, we
464 * might see them, if they are in parts of the PCIe core that aren't
465 * essential.
466 */
467 if (hwerrs & INFINIPATH_HWE_PCIE1PLLFAILED)
468 strlcat(msg, "[PCIePLL1]", msgl);
469 if (hwerrs & INFINIPATH_HWE_PCIE0PLLFAILED)
470 strlcat(msg, "[PCIePLL0]", msgl);
471 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXTLH)
472 strlcat(msg, "[PCIe XTLH core parity]", msgl);
473 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXADM)
474 strlcat(msg, "[PCIe ADM TX core parity]", msgl);
475 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYRADM)
476 strlcat(msg, "[PCIe ADM RX core parity]", msgl);
477
478 if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
479 strlcat(msg, "[Rx Dsync]", msgl);
480 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
481 strlcat(msg, "[SerDes PLL]", msgl);
482
483 ipath_dev_err(dd, "%s hardware error\n", msg);
484 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
485 /*
486 * for /sys status file ; if no trailing } is copied, we'll
487 * know it was truncated.
488 */
489 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
490 "{%s}", msg);
491 }
492}
493
494/**
495 * ipath_pe_boardname - fill in the board name
496 * @dd: the infinipath device
497 * @name: the output buffer
498 * @namelen: the size of the output buffer
499 *
500 * info is based on the board revision register
501 */
502static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
503 size_t namelen)
504{
505 char *n = NULL;
506 u8 boardrev = dd->ipath_boardrev;
507 int ret;
508
509 switch (boardrev) {
510 case 0:
511 n = "InfiniPath_Emulation";
512 break;
513 case 1:
514 n = "InfiniPath_PE-800-Bringup";
515 break;
516 case 2:
517 n = "InfiniPath_PE-880";
518 break;
519 case 3:
520 n = "InfiniPath_PE-850";
521 break;
522 case 4:
523 n = "InfiniPath_PE-860";
524 break;
525 default:
526 ipath_dev_err(dd,
527 "Don't yet know about board with ID %u\n",
528 boardrev);
529 snprintf(name, namelen, "Unknown_InfiniPath_PE-8xx_%u",
530 boardrev);
531 break;
532 }
533 if (n)
534 snprintf(name, namelen, "%s", n);
535
8307c28e 536 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
dc741bbd
BS		 537 ipath_dev_err(dd, "Unsupported PE-800 revision %u.%u!\n",
538 dd->ipath_majrev, dd->ipath_minrev);
539 ret = 1;
540 } else
541 ret = 0;
542
543 return ret;
544}
545
546/**
547 * ipath_pe_init_hwerrors - enable hardware errors
548 * @dd: the infinipath device
549 *
550 * now that we have finished initializing everything that might reasonably
551 * cause a hardware error, and cleared those errors bits as they occur,
552 * we can enable hardware errors in the mask (potentially enabling
553 * freeze mode), and enable hardware errors as errors (along with
554 * everything else) in errormask
555 */
ac2ae4c9 556static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
dc741bbd
BS		 557{
558 ipath_err_t val;
559 u64 extsval;
560
561 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
562
563 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
564 ipath_dev_err(dd, "MemBIST did not complete!\n");
565
566 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
567
568 if (!dd->ipath_boardrev) // no PLL for Emulator
569 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
570
571 /* workaround bug 9460 in internal interface bus parity checking */
572 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
573
574 dd->ipath_hwerrmask = val;
575}
576
577/**
578 * ipath_pe_bringup_serdes - bring up the serdes
579 * @dd: the infinipath device
580 */
ac2ae4c9 581static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
dc741bbd
BS		 582{
583 u64 val, tmp, config1;
584 int ret = 0, change = 0;
585
586 ipath_dbg("Trying to bringup serdes\n");
587
588 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
589 INFINIPATH_HWE_SERDESPLLFAILED) {
590 ipath_dbg("At start, serdes PLL failed bit set "
591 "in hwerrstatus, clearing and continuing\n");
592 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
593 INFINIPATH_HWE_SERDESPLLFAILED);
594 }
595
596 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
597 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
598
599 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
600 "xgxsconfig %llx\n", (unsigned long long) val,
601 (unsigned long long) config1, (unsigned long long)
602 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
603
604 /*
605 * Force reset on, also set rxdetect enable. Must do before reading
606 * serdesstatus at least for simulation, or some of the bits in
607 * serdes status will come back as undefined and cause simulation
608 * failures
609 */
610 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
611 | INFINIPATH_SERDC0_L1PWR_DN;
612 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
613 /* be sure chip saw it */
614 tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
615 udelay(5); /* need pll reset set at least for a bit */
616 /*
617 * after PLL is reset, set the per-lane Resets and TxIdle and
618 * clear the PLL reset and rxdetect (to get falling edge).
619 * Leave L1PWR bits set (permanently)
620 */
621 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
622 | INFINIPATH_SERDC0_L1PWR_DN);
623 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
624 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
625 "and txidle (%llx)\n", (unsigned long long) val);
626 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
627 /* be sure chip saw it */
628 tmp = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
629 /* need PLL reset clear for at least 11 usec before lane
630 * resets cleared; give it a few more to be sure */
631 udelay(15);
632 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
633
634 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
635 "(writing %llx)\n", (unsigned long long) val);
636 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
637 /* be sure chip saw it */
638 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
639
640 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
641 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
642 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
643 val &=
644 ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
645 INFINIPATH_XGXS_MDIOADDR_SHIFT);
646 /* MDIO address 3 */
647 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
648 change = 1;
649 }
650 if (val & INFINIPATH_XGXS_RESET) {
651 val &= ~INFINIPATH_XGXS_RESET;
652 change = 1;
653 }
654 if (change)
655 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
656
657 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
658
659 /* clear current and de-emphasis bits */
660 config1 &= ~0x0ffffffff00ULL;
661 /* set current to 20ma */
662 config1 |= 0x00000000000ULL;
663 /* set de-emphasis to -5.68dB */
664 config1 |= 0x0cccc000000ULL;
665 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
666
667 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
668 "config1=%llx, sstatus=%llx xgxs=%llx\n",
669 (unsigned long long) val, (unsigned long long) config1,
670 (unsigned long long)
671 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
672 (unsigned long long)
673 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
674
675 if (!ipath_waitfor_mdio_cmdready(dd)) {
676 ipath_write_kreg(
677 dd, dd->ipath_kregs->kr_mdio,
678 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
679 IPATH_MDIO_CTRL_XGXS_REG_8, 0));
680 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
681 IPATH_MDIO_DATAVALID, &val))
682 ipath_dbg("Never got MDIO data for XGXS "
683 "status read\n");
684 else
685 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
686 "'bank' 31 %x\n", (u32) val);
687 } else
688 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
689
690 return ret;
691}
692
693/**
694 * ipath_pe_quiet_serdes - set serdes to txidle
695 * @dd: the infinipath device
696 * Called when driver is being unloaded
697 */
ac2ae4c9 698static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
dc741bbd
BS		 699{
700 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
701
702 val |= INFINIPATH_SERDC0_TXIDLE;
703 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
704 (unsigned long long) val);
705 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
706}
707
708/* this is not yet needed on the PE800, so just return 0. */
709static int ipath_pe_intconfig(struct ipath_devdata *dd)
710{
711 return 0;
712}
713
714/**
715 * ipath_setup_pe_setextled - set the state of the two external LEDs
716 * @dd: the infinipath device
717 * @lst: the L state
718 * @ltst: the LT state
719
720 * These LEDs indicate the physical and logical state of IB link.
721 * For this chip (at least with recommended board pinouts), LED1
722 * is Yellow (logical state) and LED2 is Green (physical state),
723 *
724 * Note: We try to match the Mellanox HCA LED behavior as best
725 * we can. Green indicates physical link state is OK (something is
726 * plugged in, and we can train).
727 * Amber indicates the link is logically up (ACTIVE).
728 * Mellanox further blinks the amber LED to indicate data packet
729 * activity, but we have no hardware support for that, so it would
730 * require waking up every 10-20 msecs and checking the counters
731 * on the chip, and then turning the LED off if appropriate. That's
732 * visible overhead, so not something we will do.
733 *
734 */
735static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
736 u64 ltst)
737{
738 u64 extctl;
739
740 /* the diags use the LED to indicate diag info, so we leave
741 * the external LED alone when the diags are running */
742 if (ipath_diag_inuse)
743 return;
744
745 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
746 INFINIPATH_EXTC_LED2PRIPORT_ON);
747
748 if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
749 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
750 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
751 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
752 dd->ipath_extctrl = extctl;
753 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
754}
755
756/**
757 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
758 * @dd: the infinipath device
759 *
760 * This is called during driver unload.
761 * We do the pci_disable_msi here, not in generic code, because it
762 * isn't used for the HT-400. If we do end up needing pci_enable_msi
763 * at some point in the future for HT-400, we'll move the call back
764 * into the main init_one code.
765 */
766static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
767{
768 dd->ipath_msi_lo = 0; /* just in case unload fails */
769 pci_disable_msi(dd->pcidev);
770}
771
772/**
773 * ipath_setup_pe_config - setup PCIe config related stuff
774 * @dd: the infinipath device
775 * @pdev: the PCI device
776 *
777 * The pci_enable_msi() call will fail on systems with MSI quirks
778 * such as those with AMD8131, even if the device of interest is not
779 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
780 * late in 2.6.16).
781 * All that can be done is to edit the kernel source to remove the quirk
782 * check until that is fixed.
783 * We do not need to call enable_msi() for our HyperTransport chip (HT-400),
784 * even those it uses MSI, and we want to avoid the quirk warning, so
785 * So we call enable_msi only for the PE-800. If we do end up needing
786 * pci_enable_msi at some point in the future for HT-400, we'll move the
787 * call back into the main init_one code.
788 * We save the msi lo and hi values, so we can restore them after
789 * chip reset (the kernel PCI infrastructure doesn't yet handle that
790 * correctly).
791 */
792static int ipath_setup_pe_config(struct ipath_devdata *dd,
793 struct pci_dev *pdev)
794{
795 int pos, ret;
796
797 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
798 ret = pci_enable_msi(dd->pcidev);
799 if (ret)
800 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
801 "interrupts may not work\n", ret);
802 /* continue even if it fails, we may still be OK... */
803
804 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
805 u16 control;
806 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
807 &dd->ipath_msi_lo);
808 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
809 &dd->ipath_msi_hi);
810 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
811 &control);
812 /* now save the data (vector) info */
813 pci_read_config_word(dd->pcidev,
814 pos + ((control & PCI_MSI_FLAGS_64BIT)
815 ? 12 : 8),
816 &dd->ipath_msi_data);
817 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
818 "0x%x, control=0x%x\n", dd->ipath_msi_data,
819 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
820 control);
821 /* we save the cachelinesize also, although it doesn't
822 * really matter */
823 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
824 &dd->ipath_pci_cacheline);
825 } else
826 ipath_dev_err(dd, "Can't find MSI capability, "
827 "can't save MSI settings for reset\n");
828 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
829 u16 linkstat;
830 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
831 &linkstat);
832 linkstat >>= 4;
833 linkstat &= 0x1f;
834 if (linkstat != 8)
835 ipath_dev_err(dd, "PCIe width %u, "
836 "performance reduced\n", linkstat);
837 }
838 else
839 ipath_dev_err(dd, "Can't find PCI Express "
840 "capability!\n");
841 return 0;
842}
843
844static void ipath_init_pe_variables(void)
845{
846 /*
847 * bits for selecting i2c direction and values,
848 * used for I2C serial flash
849 */
850 ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
851 ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
852 ipath_gpio_sda = IPATH_GPIO_SDA;
853 ipath_gpio_scl = IPATH_GPIO_SCL;
854
855 /* variables for sanity checking interrupt and errors */
856 infinipath_hwe_bitsextant =
857 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
858 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
859 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
860 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
861 INFINIPATH_HWE_PCIE1PLLFAILED |
862 INFINIPATH_HWE_PCIE0PLLFAILED |
863 INFINIPATH_HWE_PCIEPOISONEDTLP |
864 INFINIPATH_HWE_PCIECPLTIMEOUT |
865 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
866 INFINIPATH_HWE_PCIEBUSPARITYXADM |
867 INFINIPATH_HWE_PCIEBUSPARITYRADM |
868 INFINIPATH_HWE_MEMBISTFAILED |
869 INFINIPATH_HWE_COREPLL_FBSLIP |
870 INFINIPATH_HWE_COREPLL_RFSLIP |
871 INFINIPATH_HWE_SERDESPLLFAILED |
872 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
873 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
874 infinipath_i_bitsextant =
875 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
876 (INFINIPATH_I_RCVAVAIL_MASK <<
877 INFINIPATH_I_RCVAVAIL_SHIFT) |
878 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
879 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
880 infinipath_e_bitsextant =
881 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
882 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
883 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
884 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
885 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
886 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
887 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
888 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
889 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
890 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
891 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
892 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
893 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
894 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
895 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
896 INFINIPATH_E_HARDWARE;
897
898 infinipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
899 infinipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
900}
901
902/* setup the MSI stuff again after a reset. I'd like to just call
903 * pci_enable_msi() and request_irq() again, but when I do that,
904 * the MSI enable bit doesn't get set in the command word, and
905 * we switch to to a different interrupt vector, which is confusing,
906 * so I instead just do it all inline. Perhaps somehow can tie this
907 * into the PCIe hotplug support at some point
908 * Note, because I'm doing it all here, I don't call pci_disable_msi()
909 * or free_irq() at the start of ipath_setup_pe_reset().
910 */
911static int ipath_reinit_msi(struct ipath_devdata *dd)
912{
913 int pos;
914 u16 control;
915 int ret;
916
917 if (!dd->ipath_msi_lo) {
918 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
919 "initial setup failed?\n");
920 ret = 0;
921 goto bail;
922 }
923
924 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
925 ipath_dev_err(dd, "Can't find MSI capability, "
926 "can't restore MSI settings\n");
927 ret = 0;
928 goto bail;
929 }
930 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
931 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
932 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
933 dd->ipath_msi_lo);
934 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
935 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
936 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
937 dd->ipath_msi_hi);
938 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
939 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
940 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
941 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
942 control, control | PCI_MSI_FLAGS_ENABLE);
943 control |= PCI_MSI_FLAGS_ENABLE;
944 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
945 control);
946 }
947 /* now rewrite the data (vector) info */
948 pci_write_config_word(dd->pcidev, pos +
949 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
950 dd->ipath_msi_data);
951 /* we restore the cachelinesize also, although it doesn't really
952 * matter */
953 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
954 dd->ipath_pci_cacheline);
955 /* and now set the pci master bit again */
956 pci_set_master(dd->pcidev);
957 ret = 1;
958
959bail:
960 return ret;
961}
962
963/* This routine sleeps, so it can only be called from user context, not
964 * from interrupt context. If we need interrupt context, we can split
965 * it into two routines.
966*/
967static int ipath_setup_pe_reset(struct ipath_devdata *dd)
968{
969 u64 val;
970 int i;
971 int ret;
972
973 /* Use ERROR so it shows up in logs, etc. */
974 ipath_dev_err(dd, "Resetting PE-800 unit %u\n",
975 dd->ipath_unit);
c71c30dc
BS		 976 /* keep chip from being accessed in a few places */
977 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
dc741bbd
BS		 978 val = dd->ipath_control | INFINIPATH_C_RESET;
979 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
980 mb();
981
982 for (i = 1; i <= 5; i++) {
983 int r;
984 /* allow MBIST, etc. to complete; longer on each retry.
985 * We sometimes get machine checks from bus timeout if no
986 * response, so for now, make it *really* long.
987 */
988 msleep(1000 + (1 + i) * 2000);
989 if ((r =
990 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
991 dd->ipath_pcibar0)))
992 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
993 r);
994 if ((r =
995 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
996 dd->ipath_pcibar1)))
997 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
998 r);
999 /* now re-enable memory access */
1000 if ((r = pci_enable_device(dd->pcidev)))
1001 ipath_dev_err(dd, "pci_enable_device failed after "
1002 "reset: %d\n", r);
c71c30dc
BS		 1003 /* whether it worked or not, mark as present, again */
1004 dd->ipath_flags |= IPATH_PRESENT;
dc741bbd
BS		 1005 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1006 if (val == dd->ipath_revision) {
1007 ipath_cdbg(VERBOSE, "Got matching revision "
1008 "register %llx on try %d\n",
1009 (unsigned long long) val, i);
1010 ret = ipath_reinit_msi(dd);
1011 goto bail;
1012 }
1013 /* Probably getting -1 back */
1014 ipath_dbg("Didn't get expected revision register, "
1015 "got %llx, try %d\n", (unsigned long long) val,
1016 i + 1);
1017 }
1018 ret = 0; /* failed */
1019
1020bail:
1021 return ret;
1022}
1023
1024/**
1025 * ipath_pe_put_tid - write a TID in chip
1026 * @dd: the infinipath device
1027 * @tidptr: pointer to the expected TID (in chip) to udpate
1028 * @tidtype: 0 for eager, 1 for expected
1029 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1030 *
1031 * This exists as a separate routine to allow for special locking etc.
1032 * It's used for both the full cleanup on exit, as well as the normal
1033 * setup and teardown.
1034 */
1035static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1036 u32 type, unsigned long pa)
1037{
1038 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1039 unsigned long flags = 0; /* keep gcc quiet */
1040
1041 if (pa != dd->ipath_tidinvalid) {
1042 if (pa & ((1U << 11) - 1)) {
1043 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1044 "not 4KB aligned!\n", pa);
1045 return;
1046 }
1047 pa >>= 11;
1048 /* paranoia check */
1049 if (pa & (7<<29))
1050 ipath_dev_err(dd,
1051 "BUG: Physical page address 0x%lx "
1052 "has bits set in 31-29\n", pa);
1053
1054 if (type == 0)
1055 pa |= dd->ipath_tidtemplate;
1056 else /* for now, always full 4KB page */
1057 pa |= 2 << 29;
1058 }
1059
1060 /* workaround chip bug 9437 by writing each TID twice
1061 * and holding a spinlock around the writes, so they don't
1062 * intermix with other TID (eager or expected) writes
1063 * Unfortunately, this call can be done from interrupt level
1064 * for the port 0 eager TIDs, so we have to use irqsave
1065 */
1066 spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1067 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1068 if (dd->ipath_kregbase)
1069 writel(pa, tidp32);
1070 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1071 mmiowb();
1072 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1073}
1074
1075/**
1076 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1077 * @dd: the infinipath device
1078 * @port: the port
1079 *
1080 * clear all TID entries for a port, expected and eager.
1081 * Used from ipath_close(). On PE800, TIDs are only 32 bits,
1082 * not 64, but they are still on 64 bit boundaries, so tidbase
1083 * is declared as u64 * for the pointer math, even though we write 32 bits
1084 */
1085static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1086{
1087 u64 __iomem *tidbase;
1088 unsigned long tidinv;
1089 int i;
1090
1091 if (!dd->ipath_kregbase)
1092 return;
1093
1094 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1095
1096 tidinv = dd->ipath_tidinvalid;
1097 tidbase = (u64 __iomem *)
1098 ((char __iomem *)(dd->ipath_kregbase) +
1099 dd->ipath_rcvtidbase +
1100 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1101
1102 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1103 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv);
1104
1105 tidbase = (u64 __iomem *)
1106 ((char __iomem *)(dd->ipath_kregbase) +
1107 dd->ipath_rcvegrbase +
1108 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1109
1110 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1111 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv);
1112}
1113
1114/**
1115 * ipath_pe_tidtemplate - setup constants for TID updates
1116 * @dd: the infinipath device
1117 *
1118 * We setup stuff that we use a lot, to avoid calculating each time
1119 */
1120static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1121{
1122 u32 egrsize = dd->ipath_rcvegrbufsize;
1123
1124 /* For now, we always allocate 4KB buffers (at init) so we can
1125 * receive max size packets. We may want a module parameter to
1126 * specify 2KB or 4KB and/or make be per port instead of per device
1127 * for those who want to reduce memory footprint. Note that the
1128 * ipath_rcvhdrentsize size must be large enough to hold the largest
1129 * IB header (currently 96 bytes) that we expect to handle (plus of
1130 * course the 2 dwords of RHF).
1131 */
1132 if (egrsize == 2048)
1133 dd->ipath_tidtemplate = 1U << 29;
1134 else if (egrsize == 4096)
1135 dd->ipath_tidtemplate = 2U << 29;
1136 else {
1137 egrsize = 4096;
1138 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1139 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1140 egrsize);
1141 dd->ipath_tidtemplate = 2U << 29;
1142 }
1143 dd->ipath_tidinvalid = 0;
1144}
1145
1146static int ipath_pe_early_init(struct ipath_devdata *dd)
1147{
1148 dd->ipath_flags |= IPATH_4BYTE_TID;
1149
1150 /*
1151 * For openib, we need to be able to handle an IB header of 96 bytes
1152 * or 24 dwords. HT-400 has arbitrary sized receive buffers, so we
1153 * made them the same size as the PIO buffers. The PE-800 does not
1154 * handle arbitrary size buffers, so we need the header large enough
1155 * to handle largest IB header, but still have room for a 2KB MTU
1156 * standard IB packet.
1157 */
1158 dd->ipath_rcvhdrentsize = 24;
1159 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1160
1161 /* For HT-400, we allocate a somewhat overly large eager buffer,
1162 * such that we can guarantee that we can receive the largest packet
1163 * that we can send out. To truly support a 4KB MTU, we need to
1164 * bump this to a larger value. We'll do this when I get around to
1165 * testing 4KB sends on the PE-800, which I have not yet done.
1166 */
1167 dd->ipath_rcvegrbufsize = 2048;
1168 /*
1169 * the min() check here is currently a nop, but it may not always
1170 * be, depending on just how we do ipath_rcvegrbufsize
1171 */
1172 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1173 dd->ipath_rcvegrbufsize +
1174 (dd->ipath_rcvhdrentsize << 2));
1175 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1176
1177 /*
1178 * For PE-800, we can request a receive interrupt for 1 or
1179 * more packets from current offset. For now, we set this
1180 * up for a single packet, to match the HT-400 behavior.
1181 */
1182 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1183
f2080fa3
BS		 1184 ipath_get_eeprom_info(dd);
1185
dc741bbd
BS		 1186 return 0;
1187}
1188
1189int __attribute__((weak)) ipath_unordered_wc(void)
1190{
1191 return 0;
1192}
1193
1194/**
1195 * ipath_init_pe_get_base_info - set chip-specific flags for user code
1196 * @dd: the infinipath device
1197 * @kbase: ipath_base_info pointer
1198 *
1199 * We set the PCIE flag because the lower bandwidth on PCIe vs
1200 * HyperTransport can affect some user packet algorithims.
1201 */
1202static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1203{
1204 struct ipath_base_info *kinfo = kbase;
1205
1206 if (ipath_unordered_wc()) {
1207 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1208 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1209 }
1210 else
1211 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1212
1213 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
1214
1215 return 0;
1216}
1217
1218/**
1219 * ipath_init_pe800_funcs - set up the chip-specific function pointers
1220 * @dd: the infinipath device
1221 *
1222 * This is global, and is called directly at init to set up the
1223 * chip-specific function pointers for later use.
1224 */
1225void ipath_init_pe800_funcs(struct ipath_devdata *dd)
1226{
1227 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1228 dd->ipath_f_bus = ipath_setup_pe_config;
1229 dd->ipath_f_reset = ipath_setup_pe_reset;
1230 dd->ipath_f_get_boardname = ipath_pe_boardname;
1231 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1232 dd->ipath_f_early_init = ipath_pe_early_init;
1233 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1234 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1235 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1236 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1237 dd->ipath_f_put_tid = ipath_pe_put_tid;
1238 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1239 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1240 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1241
1242 /* initialize chip-specific variables */
1243 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1244
1245 /*
1246 * setup the register offsets, since they are different for each
1247 * chip
1248 */
1249 dd->ipath_kregs = &ipath_pe_kregs;
1250 dd->ipath_cregs = &ipath_pe_cregs;
1251
1252 ipath_init_pe_variables();
1253}
1254
Linux 6.x block layer and io_uring tree(s)