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d41d3aeb BS |
1 | #ifndef _IPATH_KERNEL_H |
2 | #define _IPATH_KERNEL_H | |
3 | /* | |
e7eacd36 | 4 | * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved. |
d41d3aeb BS |
5 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | /* | |
37 | * This header file is the base header file for infinipath kernel code | |
38 | * ipath_user.h serves a similar purpose for user code. | |
39 | */ | |
40 | ||
41 | #include <linux/interrupt.h> | |
1fd3b40f BS |
42 | #include <linux/pci.h> |
43 | #include <linux/dma-mapping.h> | |
2c45688f | 44 | #include <linux/mutex.h> |
afce688b RC |
45 | #include <linux/list.h> |
46 | #include <linux/scatterlist.h> | |
d41d3aeb | 47 | #include <asm/io.h> |
49739b3e | 48 | #include <rdma/ib_verbs.h> |
d41d3aeb BS |
49 | |
50 | #include "ipath_common.h" | |
51 | #include "ipath_debug.h" | |
52 | #include "ipath_registers.h" | |
53 | ||
54 | /* only s/w major version of InfiniPath we can handle */ | |
55 | #define IPATH_CHIP_VERS_MAJ 2U | |
56 | ||
57 | /* don't care about this except printing */ | |
58 | #define IPATH_CHIP_VERS_MIN 0U | |
59 | ||
60 | /* temporary, maybe always */ | |
61 | extern struct infinipath_stats ipath_stats; | |
62 | ||
63 | #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ | |
aecd3b5a MA |
64 | /* |
65 | * First-cut critierion for "device is active" is | |
66 | * two thousand dwords combined Tx, Rx traffic per | |
67 | * 5-second interval. SMA packets are 64 dwords, | |
68 | * and occur "a few per second", presumably each way. | |
69 | */ | |
70 | #define IPATH_TRAFFIC_ACTIVE_THRESHOLD (2000) | |
71 | /* | |
72 | * Struct used to indicate which errors are logged in each of the | |
73 | * error-counters that are logged to EEPROM. A counter is incremented | |
74 | * _once_ (saturating at 255) for each event with any bits set in | |
75 | * the error or hwerror register masks below. | |
76 | */ | |
77 | #define IPATH_EEP_LOG_CNT (4) | |
78 | struct ipath_eep_log_mask { | |
79 | u64 errs_to_log; | |
80 | u64 hwerrs_to_log; | |
81 | }; | |
d41d3aeb BS |
82 | |
83 | struct ipath_portdata { | |
84 | void **port_rcvegrbuf; | |
85 | dma_addr_t *port_rcvegrbuf_phys; | |
86 | /* rcvhdrq base, needs mmap before useful */ | |
87 | void *port_rcvhdrq; | |
88 | /* kernel virtual address where hdrqtail is updated */ | |
1fd3b40f | 89 | void *port_rcvhdrtail_kvaddr; |
d41d3aeb BS |
90 | /* |
91 | * temp buffer for expected send setup, allocated at open, instead | |
92 | * of each setup call | |
93 | */ | |
94 | void *port_tid_pg_list; | |
95 | /* when waiting for rcv or pioavail */ | |
96 | wait_queue_head_t port_wait; | |
97 | /* | |
98 | * rcvegr bufs base, physical, must fit | |
99 | * in 44 bits so 32 bit programs mmap64 44 bit works) | |
100 | */ | |
101 | dma_addr_t port_rcvegr_phys; | |
102 | /* mmap of hdrq, must fit in 44 bits */ | |
103 | dma_addr_t port_rcvhdrq_phys; | |
f37bda92 | 104 | dma_addr_t port_rcvhdrqtailaddr_phys; |
d41d3aeb | 105 | /* |
9929b0fb BS |
106 | * number of opens (including slave subports) on this instance |
107 | * (ignoring forks, dup, etc. for now) | |
d41d3aeb BS |
108 | */ |
109 | int port_cnt; | |
110 | /* | |
111 | * how much space to leave at start of eager TID entries for | |
112 | * protocol use, on each TID | |
113 | */ | |
114 | /* instead of calculating it */ | |
115 | unsigned port_port; | |
9929b0fb BS |
116 | /* non-zero if port is being shared. */ |
117 | u16 port_subport_cnt; | |
118 | /* non-zero if port is being shared. */ | |
119 | u16 port_subport_id; | |
e2ab41ca DO |
120 | /* number of pio bufs for this port (all procs, if shared) */ |
121 | u32 port_piocnt; | |
122 | /* first pio buffer for this port */ | |
123 | u32 port_pio_base; | |
d41d3aeb BS |
124 | /* chip offset of PIO buffers for this port */ |
125 | u32 port_piobufs; | |
126 | /* how many alloc_pages() chunks in port_rcvegrbuf_pages */ | |
127 | u32 port_rcvegrbuf_chunks; | |
128 | /* how many egrbufs per chunk */ | |
129 | u32 port_rcvegrbufs_perchunk; | |
130 | /* order for port_rcvegrbuf_pages */ | |
131 | size_t port_rcvegrbuf_size; | |
132 | /* rcvhdrq size (for freeing) */ | |
133 | size_t port_rcvhdrq_size; | |
134 | /* next expected TID to check when looking for free */ | |
135 | u32 port_tidcursor; | |
136 | /* next expected TID to check */ | |
137 | unsigned long port_flag; | |
f2d04231 RW |
138 | /* what happened */ |
139 | unsigned long int_flag; | |
d41d3aeb BS |
140 | /* WAIT_RCV that timed out, no interrupt */ |
141 | u32 port_rcvwait_to; | |
142 | /* WAIT_PIO that timed out, no interrupt */ | |
143 | u32 port_piowait_to; | |
144 | /* WAIT_RCV already happened, no wait */ | |
145 | u32 port_rcvnowait; | |
146 | /* WAIT_PIO already happened, no wait */ | |
147 | u32 port_pionowait; | |
148 | /* total number of rcvhdrqfull errors */ | |
149 | u32 port_hdrqfull; | |
755807a2 DO |
150 | /* |
151 | * Used to suppress multiple instances of same | |
152 | * port staying stuck at same point. | |
153 | */ | |
154 | u32 port_lastrcvhdrqtail; | |
70c51da2 AJ |
155 | /* saved total number of rcvhdrqfull errors for poll edge trigger */ |
156 | u32 port_hdrqfull_poll; | |
157 | /* total number of polled urgent packets */ | |
158 | u32 port_urgent; | |
159 | /* saved total number of polled urgent packets for poll edge trigger */ | |
160 | u32 port_urgent_poll; | |
d41d3aeb | 161 | /* pid of process using this port */ |
40d97692 PE |
162 | struct pid *port_pid; |
163 | struct pid *port_subpid[INFINIPATH_MAX_SUBPORT]; | |
d41d3aeb BS |
164 | /* same size as task_struct .comm[] */ |
165 | char port_comm[16]; | |
166 | /* pkeys set by this use of this port */ | |
167 | u16 port_pkeys[4]; | |
168 | /* so file ops can get at unit */ | |
169 | struct ipath_devdata *port_dd; | |
9929b0fb BS |
170 | /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ |
171 | void *subport_uregbase; | |
172 | /* An array of pages for the eager receive buffers * N */ | |
173 | void *subport_rcvegrbuf; | |
174 | /* An array of pages for the eager header queue entries * N */ | |
175 | void *subport_rcvhdr_base; | |
176 | /* The version of the library which opened this port */ | |
177 | u32 userversion; | |
178 | /* Bitmask of active slaves */ | |
179 | u32 active_slaves; | |
f2d04231 RW |
180 | /* Type of packets or conditions we want to poll for */ |
181 | u16 poll_type; | |
c59a80ac RC |
182 | /* port rcvhdrq head offset */ |
183 | u32 port_head; | |
9355fb6a RC |
184 | /* receive packet sequence counter */ |
185 | u32 port_seq_cnt; | |
d41d3aeb BS |
186 | }; |
187 | ||
188 | struct sk_buff; | |
afce688b RC |
189 | struct ipath_sge_state; |
190 | struct ipath_verbs_txreq; | |
d41d3aeb BS |
191 | |
192 | /* | |
193 | * control information for layered drivers | |
194 | */ | |
195 | struct _ipath_layer { | |
196 | void *l_arg; | |
197 | }; | |
198 | ||
1fd3b40f BS |
199 | struct ipath_skbinfo { |
200 | struct sk_buff *skb; | |
201 | dma_addr_t phys; | |
202 | }; | |
203 | ||
afce688b RC |
204 | struct ipath_sdma_txreq { |
205 | int flags; | |
206 | int sg_count; | |
207 | union { | |
208 | struct scatterlist *sg; | |
209 | void *map_addr; | |
210 | }; | |
211 | void (*callback)(void *, int); | |
212 | void *callback_cookie; | |
213 | int callback_status; | |
214 | u16 start_idx; /* sdma private */ | |
215 | u16 next_descq_idx; /* sdma private */ | |
216 | struct list_head list; /* sdma private */ | |
217 | }; | |
218 | ||
219 | struct ipath_sdma_desc { | |
220 | __le64 qw[2]; | |
221 | }; | |
222 | ||
223 | #define IPATH_SDMA_TXREQ_F_USELARGEBUF 0x1 | |
224 | #define IPATH_SDMA_TXREQ_F_HEADTOHOST 0x2 | |
225 | #define IPATH_SDMA_TXREQ_F_INTREQ 0x4 | |
226 | #define IPATH_SDMA_TXREQ_F_FREEBUF 0x8 | |
227 | #define IPATH_SDMA_TXREQ_F_FREEDESC 0x10 | |
228 | #define IPATH_SDMA_TXREQ_F_VL15 0x20 | |
229 | ||
230 | #define IPATH_SDMA_TXREQ_S_OK 0 | |
231 | #define IPATH_SDMA_TXREQ_S_SENDERROR 1 | |
232 | #define IPATH_SDMA_TXREQ_S_ABORTED 2 | |
233 | #define IPATH_SDMA_TXREQ_S_SHUTDOWN 3 | |
234 | ||
e8ffef73 RD |
235 | #define IPATH_SDMA_STATUS_SCORE_BOARD_DRAIN_IN_PROG (1ull << 63) |
236 | #define IPATH_SDMA_STATUS_ABORT_IN_PROG (1ull << 62) | |
237 | #define IPATH_SDMA_STATUS_INTERNAL_SDMA_ENABLE (1ull << 61) | |
238 | #define IPATH_SDMA_STATUS_SCB_EMPTY (1ull << 30) | |
239 | ||
c4b4d16e RC |
240 | /* max dwords in small buffer packet */ |
241 | #define IPATH_SMALLBUF_DWORDS (dd->ipath_piosize2k >> 2) | |
242 | ||
c4bce803 DO |
243 | /* |
244 | * Possible IB config parameters for ipath_f_get/set_ib_cfg() | |
245 | */ | |
246 | #define IPATH_IB_CFG_LIDLMC 0 /* Get/set LID (LS16b) and Mask (MS16b) */ | |
247 | #define IPATH_IB_CFG_HRTBT 1 /* Get/set Heartbeat off/enable/auto */ | |
248 | #define IPATH_IB_HRTBT_ON 3 /* Heartbeat enabled, sent every 100msec */ | |
249 | #define IPATH_IB_HRTBT_OFF 0 /* Heartbeat off */ | |
250 | #define IPATH_IB_CFG_LWID_ENB 2 /* Get/set allowed Link-width */ | |
251 | #define IPATH_IB_CFG_LWID 3 /* Get currently active Link-width */ | |
252 | #define IPATH_IB_CFG_SPD_ENB 4 /* Get/set allowed Link speeds */ | |
253 | #define IPATH_IB_CFG_SPD 5 /* Get current Link spd */ | |
254 | #define IPATH_IB_CFG_RXPOL_ENB 6 /* Get/set Auto-RX-polarity enable */ | |
255 | #define IPATH_IB_CFG_LREV_ENB 7 /* Get/set Auto-Lane-reversal enable */ | |
256 | #define IPATH_IB_CFG_LINKLATENCY 8 /* Get Auto-Lane-reversal enable */ | |
257 | ||
258 | ||
d41d3aeb BS |
259 | struct ipath_devdata { |
260 | struct list_head ipath_list; | |
261 | ||
262 | struct ipath_kregs const *ipath_kregs; | |
263 | struct ipath_cregs const *ipath_cregs; | |
264 | ||
265 | /* mem-mapped pointer to base of chip regs */ | |
266 | u64 __iomem *ipath_kregbase; | |
267 | /* end of mem-mapped chip space; range checking */ | |
268 | u64 __iomem *ipath_kregend; | |
269 | /* physical address of chip for io_remap, etc. */ | |
270 | unsigned long ipath_physaddr; | |
271 | /* base of memory alloced for ipath_kregbase, for free */ | |
272 | u64 *ipath_kregalloc; | |
d41d3aeb BS |
273 | /* ipath_cfgports pointers */ |
274 | struct ipath_portdata **ipath_pd; | |
275 | /* sk_buffs used by port 0 eager receive queue */ | |
1fd3b40f | 276 | struct ipath_skbinfo *ipath_port0_skbinfo; |
d41d3aeb BS |
277 | /* kvirt address of 1st 2k pio buffer */ |
278 | void __iomem *ipath_pio2kbase; | |
279 | /* kvirt address of 1st 4k pio buffer */ | |
280 | void __iomem *ipath_pio4kbase; | |
281 | /* | |
282 | * points to area where PIOavail registers will be DMA'ed. | |
283 | * Has to be on a page of it's own, because the page will be | |
284 | * mapped into user program space. This copy is *ONLY* ever | |
285 | * written by DMA, not by the driver! Need a copy per device | |
286 | * when we get to multiple devices | |
287 | */ | |
288 | volatile __le64 *ipath_pioavailregs_dma; | |
289 | /* physical address where updates occur */ | |
290 | dma_addr_t ipath_pioavailregs_phys; | |
291 | struct _ipath_layer ipath_layer; | |
292 | /* setup intr */ | |
293 | int (*ipath_f_intrsetup)(struct ipath_devdata *); | |
c4bce803 DO |
294 | /* fallback to alternate interrupt type if possible */ |
295 | int (*ipath_f_intr_fallback)(struct ipath_devdata *); | |
d41d3aeb BS |
296 | /* setup on-chip bus config */ |
297 | int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *); | |
298 | /* hard reset chip */ | |
299 | int (*ipath_f_reset)(struct ipath_devdata *); | |
300 | int (*ipath_f_get_boardname)(struct ipath_devdata *, char *, | |
301 | size_t); | |
302 | void (*ipath_f_init_hwerrors)(struct ipath_devdata *); | |
303 | void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *, | |
304 | size_t); | |
305 | void (*ipath_f_quiet_serdes)(struct ipath_devdata *); | |
306 | int (*ipath_f_bringup_serdes)(struct ipath_devdata *); | |
307 | int (*ipath_f_early_init)(struct ipath_devdata *); | |
308 | void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned); | |
309 | void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*, | |
310 | u32, unsigned long); | |
311 | void (*ipath_f_tidtemplate)(struct ipath_devdata *); | |
312 | void (*ipath_f_cleanup)(struct ipath_devdata *); | |
313 | void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64); | |
314 | /* fill out chip-specific fields */ | |
315 | int (*ipath_f_get_base_info)(struct ipath_portdata *, void *); | |
51f65ebc BS |
316 | /* free irq */ |
317 | void (*ipath_f_free_irq)(struct ipath_devdata *); | |
c4bce803 DO |
318 | struct ipath_message_header *(*ipath_f_get_msgheader) |
319 | (struct ipath_devdata *, __le32 *); | |
60948a41 | 320 | void (*ipath_f_config_ports)(struct ipath_devdata *, ushort); |
c4bce803 DO |
321 | int (*ipath_f_get_ib_cfg)(struct ipath_devdata *, int); |
322 | int (*ipath_f_set_ib_cfg)(struct ipath_devdata *, int, u32); | |
323 | void (*ipath_f_config_jint)(struct ipath_devdata *, u16 , u16); | |
3029fcc3 | 324 | void (*ipath_f_read_counters)(struct ipath_devdata *, |
c4bce803 DO |
325 | struct infinipath_counters *); |
326 | void (*ipath_f_xgxs_reset)(struct ipath_devdata *); | |
327 | /* per chip actions needed for IB Link up/down changes */ | |
328 | int (*ipath_f_ib_updown)(struct ipath_devdata *, int, u64); | |
329 | ||
9355fb6a | 330 | unsigned ipath_lastegr_idx; |
b1c1b6a3 BS |
331 | struct ipath_ibdev *verbs_dev; |
332 | struct timer_list verbs_timer; | |
d41d3aeb BS |
333 | /* total dwords sent (summed from counter) */ |
334 | u64 ipath_sword; | |
335 | /* total dwords rcvd (summed from counter) */ | |
336 | u64 ipath_rword; | |
337 | /* total packets sent (summed from counter) */ | |
338 | u64 ipath_spkts; | |
339 | /* total packets rcvd (summed from counter) */ | |
340 | u64 ipath_rpkts; | |
341 | /* ipath_statusp initially points to this. */ | |
342 | u64 _ipath_status; | |
343 | /* GUID for this interface, in network order */ | |
344 | __be64 ipath_guid; | |
345 | /* | |
346 | * aggregrate of error bits reported since last cleared, for | |
347 | * limiting of error reporting | |
348 | */ | |
349 | ipath_err_t ipath_lasterror; | |
350 | /* | |
351 | * aggregrate of error bits reported since last cleared, for | |
352 | * limiting of hwerror reporting | |
353 | */ | |
354 | ipath_err_t ipath_lasthwerror; | |
78d1e02f | 355 | /* errors masked because they occur too fast */ |
d41d3aeb | 356 | ipath_err_t ipath_maskederrs; |
72708a0a | 357 | u64 ipath_lastlinkrecov; /* link recoveries at last ACTIVE */ |
60e84503 DO |
358 | /* these 5 fields are used to establish deltas for IB Symbol |
359 | * errors and linkrecovery errors. They can be reported on | |
360 | * some chips during link negotiation prior to INIT, and with | |
361 | * DDR when faking DDR negotiations with non-IBTA switches. | |
362 | * The chip counters are adjusted at driver unload if there is | |
363 | * a non-zero delta. | |
364 | */ | |
365 | u64 ibdeltainprog; | |
366 | u64 ibsymdelta; | |
367 | u64 ibsymsnap; | |
368 | u64 iblnkerrdelta; | |
369 | u64 iblnkerrsnap; | |
370 | ||
d41d3aeb BS |
371 | /* time in jiffies at which to re-enable maskederrs */ |
372 | unsigned long ipath_unmasktime; | |
d41d3aeb BS |
373 | /* count of egrfull errors, combined for all ports */ |
374 | u64 ipath_last_tidfull; | |
375 | /* for ipath_qcheck() */ | |
376 | u64 ipath_lastport0rcv_cnt; | |
377 | /* template for writing TIDs */ | |
378 | u64 ipath_tidtemplate; | |
379 | /* value to write to free TIDs */ | |
380 | u64 ipath_tidinvalid; | |
525d0ca1 | 381 | /* IBA6120 rcv interrupt setup */ |
d41d3aeb BS |
382 | u64 ipath_rhdrhead_intr_off; |
383 | ||
384 | /* size of memory at ipath_kregbase */ | |
385 | u32 ipath_kregsize; | |
386 | /* number of registers used for pioavail */ | |
387 | u32 ipath_pioavregs; | |
388 | /* IPATH_POLL, etc. */ | |
389 | u32 ipath_flags; | |
0fd41363 BS |
390 | /* ipath_flags driver is waiting for */ |
391 | u32 ipath_state_wanted; | |
d41d3aeb BS |
392 | /* last buffer for user use, first buf for kernel use is this |
393 | * index. */ | |
394 | u32 ipath_lastport_piobuf; | |
395 | /* is a stats timer active */ | |
396 | u32 ipath_stats_timer_active; | |
3588423f AJ |
397 | /* number of interrupts for this device -- saturates... */ |
398 | u32 ipath_int_counter; | |
d41d3aeb BS |
399 | /* dwords sent read from counter */ |
400 | u32 ipath_lastsword; | |
401 | /* dwords received read from counter */ | |
402 | u32 ipath_lastrword; | |
403 | /* sent packets read from counter */ | |
404 | u32 ipath_lastspkts; | |
405 | /* received packets read from counter */ | |
406 | u32 ipath_lastrpkts; | |
407 | /* pio bufs allocated per port */ | |
408 | u32 ipath_pbufsport; | |
e2ab41ca DO |
409 | /* if remainder on bufs/port, ports < extrabuf get 1 extra */ |
410 | u32 ipath_ports_extrabuf; | |
1d7c2e52 | 411 | u32 ipath_pioupd_thresh; /* update threshold, some chips */ |
d41d3aeb BS |
412 | /* |
413 | * number of ports configured as max; zero is set to number chip | |
414 | * supports, less gives more pio bufs/port, etc. | |
415 | */ | |
416 | u32 ipath_cfgports; | |
d41d3aeb BS |
417 | /* count of port 0 hdrqfull errors */ |
418 | u32 ipath_p0_hdrqfull; | |
60948a41 RC |
419 | /* port 0 number of receive eager buffers */ |
420 | u32 ipath_p0_rcvegrcnt; | |
d41d3aeb | 421 | |
d41d3aeb BS |
422 | /* |
423 | * index of last piobuffer we used. Speeds up searching, by | |
424 | * starting at this point. Doesn't matter if multiple cpu's use and | |
425 | * update, last updater is only write that matters. Whenever it | |
426 | * wraps, we update shadow copies. Need a copy per device when we | |
427 | * get to multiple devices | |
428 | */ | |
429 | u32 ipath_lastpioindex; | |
c4b4d16e | 430 | u32 ipath_lastpioindexl; |
d41d3aeb BS |
431 | /* max length of freezemsg */ |
432 | u32 ipath_freezelen; | |
433 | /* | |
434 | * consecutive times we wanted a PIO buffer but were unable to | |
435 | * get one | |
436 | */ | |
437 | u32 ipath_consec_nopiobuf; | |
438 | /* | |
439 | * hint that we should update ipath_pioavailshadow before | |
440 | * looking for a PIO buffer | |
441 | */ | |
442 | u32 ipath_upd_pio_shadow; | |
443 | /* so we can rewrite it after a chip reset */ | |
444 | u32 ipath_pcibar0; | |
445 | /* so we can rewrite it after a chip reset */ | |
446 | u32 ipath_pcibar1; | |
afce688b RC |
447 | u32 ipath_x1_fix_tries; |
448 | u32 ipath_autoneg_tries; | |
449 | u32 serdes_first_init_done; | |
450 | ||
451 | struct ipath_relock { | |
452 | atomic_t ipath_relock_timer_active; | |
453 | struct timer_list ipath_relock_timer; | |
454 | unsigned int ipath_relock_interval; /* in jiffies */ | |
455 | } ipath_relock_singleton; | |
d41d3aeb | 456 | |
51f65ebc BS |
457 | /* interrupt number */ |
458 | int ipath_irq; | |
d41d3aeb BS |
459 | /* HT/PCI Vendor ID (here for NodeInfo) */ |
460 | u16 ipath_vendorid; | |
461 | /* HT/PCI Device ID (here for NodeInfo) */ | |
462 | u16 ipath_deviceid; | |
463 | /* offset in HT config space of slave/primary interface block */ | |
464 | u8 ipath_ht_slave_off; | |
465 | /* for write combining settings */ | |
466 | unsigned long ipath_wc_cookie; | |
957670a5 BS |
467 | unsigned long ipath_wc_base; |
468 | unsigned long ipath_wc_len; | |
d41d3aeb BS |
469 | /* ref count for each pkey */ |
470 | atomic_t ipath_pkeyrefs[4]; | |
d41d3aeb BS |
471 | /* shadow copy of struct page *'s for exp tid pages */ |
472 | struct page **ipath_pageshadow; | |
1fd3b40f BS |
473 | /* shadow copy of dma handles for exp tid pages */ |
474 | dma_addr_t *ipath_physshadow; | |
c4bce803 | 475 | u64 __iomem *ipath_egrtidbase; |
ddb70c83 DO |
476 | /* lock to workaround chip bug 9437 and others */ |
477 | spinlock_t ipath_kernel_tid_lock; | |
6bb68835 | 478 | spinlock_t ipath_user_tid_lock; |
e342c119 | 479 | spinlock_t ipath_sendctrl_lock; |
3d089098 DO |
480 | /* around ipath_pd and (user ports) port_cnt use (intr vs free) */ |
481 | spinlock_t ipath_uctxt_lock; | |
d41d3aeb BS |
482 | |
483 | /* | |
484 | * IPATH_STATUS_*, | |
485 | * this address is mapped readonly into user processes so they can | |
486 | * get status cheaply, whenever they want. | |
487 | */ | |
488 | u64 *ipath_statusp; | |
489 | /* freeze msg if hw error put chip in freeze */ | |
490 | char *ipath_freezemsg; | |
491 | /* pci access data structure */ | |
492 | struct pci_dev *pcidev; | |
a2acb2ff BS |
493 | struct cdev *user_cdev; |
494 | struct cdev *diag_cdev; | |
f4e91eb4 TJ |
495 | struct device *user_dev; |
496 | struct device *diag_dev; | |
d41d3aeb BS |
497 | /* timer used to prevent stats overflow, error throttling, etc. */ |
498 | struct timer_list ipath_stats_timer; | |
9b436eb4 DO |
499 | /* timer to verify interrupts work, and fallback if possible */ |
500 | struct timer_list ipath_intrchk_timer; | |
35783ec0 BS |
501 | void *ipath_dummy_hdrq; /* used after port close */ |
502 | dma_addr_t ipath_dummy_hdrq_phys; | |
d41d3aeb | 503 | |
afce688b RC |
504 | /* SendDMA related entries */ |
505 | spinlock_t ipath_sdma_lock; | |
f018c7e1 | 506 | unsigned long ipath_sdma_status; |
afce688b RC |
507 | unsigned long ipath_sdma_abort_jiffies; |
508 | unsigned long ipath_sdma_abort_intr_timeout; | |
509 | unsigned long ipath_sdma_buf_jiffies; | |
510 | struct ipath_sdma_desc *ipath_sdma_descq; | |
511 | u64 ipath_sdma_descq_added; | |
512 | u64 ipath_sdma_descq_removed; | |
513 | int ipath_sdma_desc_nreserved; | |
514 | u16 ipath_sdma_descq_cnt; | |
515 | u16 ipath_sdma_descq_tail; | |
516 | u16 ipath_sdma_descq_head; | |
517 | u16 ipath_sdma_next_intr; | |
518 | u16 ipath_sdma_reset_wait; | |
519 | u8 ipath_sdma_generation; | |
520 | struct tasklet_struct ipath_sdma_abort_task; | |
521 | struct tasklet_struct ipath_sdma_notify_task; | |
522 | struct list_head ipath_sdma_activelist; | |
523 | struct list_head ipath_sdma_notifylist; | |
524 | atomic_t ipath_sdma_vl15_count; | |
525 | struct timer_list ipath_sdma_vl15_timer; | |
526 | ||
527 | dma_addr_t ipath_sdma_descq_phys; | |
528 | volatile __le64 *ipath_sdma_head_dma; | |
529 | dma_addr_t ipath_sdma_head_phys; | |
530 | ||
a18e26ae RC |
531 | unsigned long ipath_ureg_align; /* user register alignment */ |
532 | ||
afce688b RC |
533 | struct delayed_work ipath_autoneg_work; |
534 | wait_queue_head_t ipath_autoneg_wait; | |
535 | ||
58411d1c JG |
536 | /* HoL blocking / user app forward-progress state */ |
537 | unsigned ipath_hol_state; | |
538 | unsigned ipath_hol_next; | |
539 | struct timer_list ipath_hol_timer; | |
540 | ||
d41d3aeb BS |
541 | /* |
542 | * Shadow copies of registers; size indicates read access size. | |
543 | * Most of them are readonly, but some are write-only register, | |
544 | * where we manipulate the bits in the shadow copy, and then write | |
545 | * the shadow copy to infinipath. | |
546 | * | |
547 | * We deliberately make most of these 32 bits, since they have | |
548 | * restricted range. For any that we read, we won't to generate 32 | |
549 | * bit accesses, since Opteron will generate 2 separate 32 bit HT | |
550 | * transactions for a 64 bit read, and we want to avoid unnecessary | |
551 | * HT transactions. | |
552 | */ | |
553 | ||
554 | /* This is the 64 bit group */ | |
555 | ||
556 | /* | |
557 | * shadow of pioavail, check to be sure it's large enough at | |
558 | * init time. | |
559 | */ | |
560 | unsigned long ipath_pioavailshadow[8]; | |
c4b4d16e RC |
561 | /* bitmap of send buffers available for the kernel to use with PIO. */ |
562 | unsigned long ipath_pioavailkernel[8]; | |
d41d3aeb BS |
563 | /* shadow of kr_gpio_out, for rmw ops */ |
564 | u64 ipath_gpio_out; | |
8f140b40 AJ |
565 | /* shadow the gpio mask register */ |
566 | u64 ipath_gpio_mask; | |
17b2eb9f MA |
567 | /* shadow the gpio output enable, etc... */ |
568 | u64 ipath_extctrl; | |
d41d3aeb BS |
569 | /* kr_revision shadow */ |
570 | u64 ipath_revision; | |
571 | /* | |
572 | * shadow of ibcctrl, for interrupt handling of link changes, | |
573 | * etc. | |
574 | */ | |
575 | u64 ipath_ibcctrl; | |
576 | /* | |
577 | * last ibcstatus, to suppress "duplicate" status change messages, | |
578 | * mostly from 2 to 3 | |
579 | */ | |
580 | u64 ipath_lastibcstat; | |
581 | /* hwerrmask shadow */ | |
582 | ipath_err_t ipath_hwerrmask; | |
78d1e02f | 583 | ipath_err_t ipath_errormask; /* errormask shadow */ |
d41d3aeb BS |
584 | /* interrupt config reg shadow */ |
585 | u64 ipath_intconfig; | |
586 | /* kr_sendpiobufbase value */ | |
587 | u64 ipath_piobufbase; | |
afce688b RC |
588 | /* kr_ibcddrctrl shadow */ |
589 | u64 ipath_ibcddrctrl; | |
d41d3aeb BS |
590 | |
591 | /* these are the "32 bit" regs */ | |
592 | ||
593 | /* | |
594 | * number of GUIDs in the flash for this interface; may need some | |
595 | * rethinking for setting on other ifaces | |
596 | */ | |
597 | u32 ipath_nguid; | |
598 | /* | |
599 | * the following two are 32-bit bitmasks, but {test,clear,set}_bit | |
600 | * all expect bit fields to be "unsigned long" | |
601 | */ | |
602 | /* shadow kr_rcvctrl */ | |
603 | unsigned long ipath_rcvctrl; | |
604 | /* shadow kr_sendctrl */ | |
605 | unsigned long ipath_sendctrl; | |
afce688b RC |
606 | /* to not count armlaunch after cancel */ |
607 | unsigned long ipath_lastcancel; | |
608 | /* count cases where special trigger was needed (double write) */ | |
609 | unsigned long ipath_spectriggerhit; | |
d41d3aeb BS |
610 | |
611 | /* value we put in kr_rcvhdrcnt */ | |
612 | u32 ipath_rcvhdrcnt; | |
613 | /* value we put in kr_rcvhdrsize */ | |
614 | u32 ipath_rcvhdrsize; | |
615 | /* value we put in kr_rcvhdrentsize */ | |
616 | u32 ipath_rcvhdrentsize; | |
617 | /* offset of last entry in rcvhdrq */ | |
618 | u32 ipath_hdrqlast; | |
619 | /* kr_portcnt value */ | |
620 | u32 ipath_portcnt; | |
621 | /* kr_pagealign value */ | |
622 | u32 ipath_palign; | |
623 | /* number of "2KB" PIO buffers */ | |
624 | u32 ipath_piobcnt2k; | |
625 | /* size in bytes of "2KB" PIO buffers */ | |
626 | u32 ipath_piosize2k; | |
627 | /* number of "4KB" PIO buffers */ | |
628 | u32 ipath_piobcnt4k; | |
629 | /* size in bytes of "4KB" PIO buffers */ | |
630 | u32 ipath_piosize4k; | |
afce688b | 631 | u32 ipath_pioreserved; /* reserved special-inkernel; */ |
d41d3aeb BS |
632 | /* kr_rcvegrbase value */ |
633 | u32 ipath_rcvegrbase; | |
634 | /* kr_rcvegrcnt value */ | |
635 | u32 ipath_rcvegrcnt; | |
636 | /* kr_rcvtidbase value */ | |
637 | u32 ipath_rcvtidbase; | |
638 | /* kr_rcvtidcnt value */ | |
639 | u32 ipath_rcvtidcnt; | |
640 | /* kr_sendregbase */ | |
641 | u32 ipath_sregbase; | |
642 | /* kr_userregbase */ | |
643 | u32 ipath_uregbase; | |
644 | /* kr_counterregbase */ | |
645 | u32 ipath_cregbase; | |
646 | /* shadow the control register contents */ | |
647 | u32 ipath_control; | |
d41d3aeb BS |
648 | /* PCI revision register (HTC rev on FPGA) */ |
649 | u32 ipath_pcirev; | |
650 | ||
651 | /* chip address space used by 4k pio buffers */ | |
652 | u32 ipath_4kalign; | |
653 | /* The MTU programmed for this unit */ | |
654 | u32 ipath_ibmtu; | |
655 | /* | |
656 | * The max size IB packet, included IB headers that we can send. | |
657 | * Starts same as ipath_piosize, but is affected when ibmtu is | |
658 | * changed, or by size of eager buffers | |
659 | */ | |
660 | u32 ipath_ibmaxlen; | |
661 | /* | |
662 | * ibmaxlen at init time, limited by chip and by receive buffer | |
663 | * size. Not changed after init. | |
664 | */ | |
665 | u32 ipath_init_ibmaxlen; | |
666 | /* size of each rcvegrbuffer */ | |
667 | u32 ipath_rcvegrbufsize; | |
6ca2abf4 AJ |
668 | /* localbus width (1, 2,4,8,16,32) from config space */ |
669 | u32 ipath_lbus_width; | |
670 | /* localbus speed (HT: 200,400,800,1000; PCIe 2500) */ | |
671 | u32 ipath_lbus_speed; | |
d41d3aeb BS |
672 | /* |
673 | * number of sequential ibcstatus change for polling active/quiet | |
674 | * (i.e., link not coming up). | |
675 | */ | |
676 | u32 ipath_ibpollcnt; | |
677 | /* low and high portions of MSI capability/vector */ | |
678 | u32 ipath_msi_lo; | |
679 | /* saved after PCIe init for restore after reset */ | |
680 | u32 ipath_msi_hi; | |
681 | /* MSI data (vector) saved for restore */ | |
682 | u16 ipath_msi_data; | |
683 | /* MLID programmed for this instance */ | |
684 | u16 ipath_mlid; | |
685 | /* LID programmed for this instance */ | |
686 | u16 ipath_lid; | |
687 | /* list of pkeys programmed; 0 if not set */ | |
688 | u16 ipath_pkeys[4]; | |
8307c28e BS |
689 | /* |
690 | * ASCII serial number, from flash, large enough for original | |
691 | * all digit strings, and longer QLogic serial number format | |
692 | */ | |
693 | u8 ipath_serial[16]; | |
d41d3aeb | 694 | /* human readable board version */ |
afce688b | 695 | u8 ipath_boardversion[96]; |
6ca2abf4 | 696 | u8 ipath_lbus_info[32]; /* human readable localbus info */ |
d41d3aeb BS |
697 | /* chip major rev, from ipath_revision */ |
698 | u8 ipath_majrev; | |
699 | /* chip minor rev, from ipath_revision */ | |
700 | u8 ipath_minrev; | |
701 | /* board rev, from ipath_revision */ | |
702 | u8 ipath_boardrev; | |
d41d3aeb BS |
703 | /* saved for restore after reset */ |
704 | u8 ipath_pci_cacheline; | |
705 | /* LID mask control */ | |
706 | u8 ipath_lmc; | |
c4bce803 DO |
707 | /* link width supported */ |
708 | u8 ipath_link_width_supported; | |
709 | /* link speed supported */ | |
710 | u8 ipath_link_speed_supported; | |
711 | u8 ipath_link_width_enabled; | |
712 | u8 ipath_link_speed_enabled; | |
713 | u8 ipath_link_width_active; | |
714 | u8 ipath_link_speed_active; | |
30fc5c31 BS |
715 | /* Rx Polarity inversion (compensate for ~tx on partner) */ |
716 | u8 ipath_rx_pol_inv; | |
fba75200 | 717 | |
9355fb6a RC |
718 | u8 ipath_r_portenable_shift; |
719 | u8 ipath_r_intravail_shift; | |
720 | u8 ipath_r_tailupd_shift; | |
721 | u8 ipath_r_portcfg_shift; | |
722 | ||
723 | /* unit # of this chip, if present */ | |
724 | int ipath_unit; | |
725 | ||
fba75200 BS |
726 | /* local link integrity counter */ |
727 | u32 ipath_lli_counter; | |
728 | /* local link integrity errors */ | |
729 | u32 ipath_lli_errors; | |
2c9446a1 BS |
730 | /* |
731 | * Above counts only cases where _successive_ LocalLinkIntegrity | |
732 | * errors were seen in the receive headers of kern-packets. | |
733 | * Below are the three (monotonically increasing) counters | |
734 | * maintained via GPIO interrupts on iba6120-rev2. | |
735 | */ | |
736 | u32 ipath_rxfc_unsupvl_errs; | |
737 | u32 ipath_overrun_thresh_errs; | |
738 | u32 ipath_lli_errs; | |
f62fe77a BS |
739 | |
740 | /* | |
741 | * Not all devices managed by a driver instance are the same | |
742 | * type, so these fields must be per-device. | |
743 | */ | |
744 | u64 ipath_i_bitsextant; | |
745 | ipath_err_t ipath_e_bitsextant; | |
746 | ipath_err_t ipath_hwe_bitsextant; | |
747 | ||
748 | /* | |
749 | * Below should be computable from number of ports, | |
750 | * since they are never modified. | |
751 | */ | |
9355fb6a RC |
752 | u64 ipath_i_rcvavail_mask; |
753 | u64 ipath_i_rcvurg_mask; | |
c4bce803 DO |
754 | u16 ipath_i_rcvurg_shift; |
755 | u16 ipath_i_rcvavail_shift; | |
f62fe77a BS |
756 | |
757 | /* | |
758 | * Register bits for selecting i2c direction and values, used for | |
759 | * I2C serial flash. | |
760 | */ | |
d84e0b28 MA |
761 | u8 ipath_gpio_sda_num; |
762 | u8 ipath_gpio_scl_num; | |
763 | u8 ipath_i2c_chain_type; | |
f62fe77a BS |
764 | u64 ipath_gpio_sda; |
765 | u64 ipath_gpio_scl; | |
82466f00 | 766 | |
17b2eb9f MA |
767 | /* lock for doing RMW of shadows/regs for ExtCtrl and GPIO */ |
768 | spinlock_t ipath_gpio_lock; | |
769 | ||
c4bce803 DO |
770 | /* |
771 | * IB link and linktraining states and masks that vary per chip in | |
772 | * some way. Set at init, to avoid each IB status change interrupt | |
773 | */ | |
774 | u8 ibcs_ls_shift; | |
775 | u8 ibcs_lts_mask; | |
776 | u32 ibcs_mask; | |
777 | u32 ib_init; | |
778 | u32 ib_arm; | |
779 | u32 ib_active; | |
780 | ||
781 | u16 ipath_rhf_offset; /* offset of RHF within receive header entry */ | |
782 | ||
783 | /* | |
784 | * shift/mask for linkcmd, linkinitcmd, maxpktlen in ibccontol | |
785 | * reg. Changes for IBA7220 | |
786 | */ | |
787 | u8 ibcc_lic_mask; /* LinkInitCmd */ | |
788 | u8 ibcc_lc_shift; /* LinkCmd */ | |
789 | u8 ibcc_mpl_shift; /* Maxpktlen */ | |
790 | ||
791 | u8 delay_mult; | |
792 | ||
82466f00 MA |
793 | /* used to override LED behavior */ |
794 | u8 ipath_led_override; /* Substituted for normal value, if non-zero */ | |
795 | u16 ipath_led_override_timeoff; /* delta to next timer event */ | |
796 | u8 ipath_led_override_vals[2]; /* Alternates per blink-frame */ | |
797 | u8 ipath_led_override_phase; /* Just counts, LSB picks from vals[] */ | |
798 | atomic_t ipath_led_override_timer_active; | |
799 | /* Used to flash LEDs in override mode */ | |
800 | struct timer_list ipath_led_override_timer; | |
801 | ||
aecd3b5a MA |
802 | /* Support (including locks) for EEPROM logging of errors and time */ |
803 | /* control access to actual counters, timer */ | |
804 | spinlock_t ipath_eep_st_lock; | |
805 | /* control high-level access to EEPROM */ | |
2c45688f | 806 | struct mutex ipath_eep_lock; |
aecd3b5a MA |
807 | /* Below inc'd by ipath_snap_cntrs(), locked by ipath_eep_st_lock */ |
808 | uint64_t ipath_traffic_wds; | |
809 | /* active time is kept in seconds, but logged in hours */ | |
810 | atomic_t ipath_active_time; | |
811 | /* Below are nominal shadow of EEPROM, new since last EEPROM update */ | |
812 | uint8_t ipath_eep_st_errs[IPATH_EEP_LOG_CNT]; | |
813 | uint8_t ipath_eep_st_new_errs[IPATH_EEP_LOG_CNT]; | |
814 | uint16_t ipath_eep_hrs; | |
815 | /* | |
816 | * masks for which bits of errs, hwerrs that cause | |
817 | * each of the counters to increment. | |
818 | */ | |
819 | struct ipath_eep_log_mask ipath_eep_st_masks[IPATH_EEP_LOG_CNT]; | |
c4bce803 DO |
820 | |
821 | /* interrupt mitigation reload register info */ | |
822 | u16 ipath_jint_idle_ticks; /* idle clock ticks */ | |
823 | u16 ipath_jint_max_packets; /* max packets across all ports */ | |
afce688b RC |
824 | |
825 | /* | |
826 | * lock for access to SerDes, and flags to sequence preset | |
827 | * versus steady-state. 7220-only at the moment. | |
828 | */ | |
829 | spinlock_t ipath_sdepb_lock; | |
830 | u8 ipath_presets_needed; /* Set if presets to be restored next DOWN */ | |
d41d3aeb BS |
831 | }; |
832 | ||
58411d1c JG |
833 | /* ipath_hol_state values (stopping/starting user proc, send flushing) */ |
834 | #define IPATH_HOL_UP 0 | |
835 | #define IPATH_HOL_DOWN 1 | |
836 | /* ipath_hol_next toggle values, used when hol_state IPATH_HOL_DOWN */ | |
837 | #define IPATH_HOL_DOWNSTOP 0 | |
838 | #define IPATH_HOL_DOWNCONT 1 | |
839 | ||
afce688b RC |
840 | /* bit positions for sdma_status */ |
841 | #define IPATH_SDMA_ABORTING 0 | |
842 | #define IPATH_SDMA_DISARMED 1 | |
843 | #define IPATH_SDMA_DISABLED 2 | |
844 | #define IPATH_SDMA_LAYERBUF 3 | |
f018c7e1 RD |
845 | #define IPATH_SDMA_RUNNING 30 |
846 | #define IPATH_SDMA_SHUTDOWN 31 | |
afce688b RC |
847 | |
848 | /* bit combinations that correspond to abort states */ | |
849 | #define IPATH_SDMA_ABORT_NONE 0 | |
850 | #define IPATH_SDMA_ABORT_ABORTING (1UL << IPATH_SDMA_ABORTING) | |
851 | #define IPATH_SDMA_ABORT_DISARMED ((1UL << IPATH_SDMA_ABORTING) | \ | |
852 | (1UL << IPATH_SDMA_DISARMED)) | |
853 | #define IPATH_SDMA_ABORT_DISABLED ((1UL << IPATH_SDMA_ABORTING) | \ | |
854 | (1UL << IPATH_SDMA_DISABLED)) | |
855 | #define IPATH_SDMA_ABORT_ABORTED ((1UL << IPATH_SDMA_ABORTING) | \ | |
856 | (1UL << IPATH_SDMA_DISARMED) | (1UL << IPATH_SDMA_DISABLED)) | |
857 | #define IPATH_SDMA_ABORT_MASK ((1UL<<IPATH_SDMA_ABORTING) | \ | |
858 | (1UL << IPATH_SDMA_DISARMED) | (1UL << IPATH_SDMA_DISABLED)) | |
859 | ||
860 | #define IPATH_SDMA_BUF_NONE 0 | |
861 | #define IPATH_SDMA_BUF_MASK (1UL<<IPATH_SDMA_LAYERBUF) | |
862 | ||
9929b0fb BS |
863 | /* Private data for file operations */ |
864 | struct ipath_filedata { | |
865 | struct ipath_portdata *pd; | |
866 | unsigned subport; | |
867 | unsigned tidcursor; | |
afce688b | 868 | struct ipath_user_sdma_queue *pq; |
9929b0fb | 869 | }; |
d41d3aeb BS |
870 | extern struct list_head ipath_dev_list; |
871 | extern spinlock_t ipath_devs_lock; | |
872 | extern struct ipath_devdata *ipath_lookup(int unit); | |
873 | ||
d41d3aeb BS |
874 | int ipath_init_chip(struct ipath_devdata *, int); |
875 | int ipath_enable_wc(struct ipath_devdata *dd); | |
876 | void ipath_disable_wc(struct ipath_devdata *dd); | |
6ef6aee2 | 877 | int ipath_count_units(int *npresentp, int *nupp, int *maxportsp); |
d41d3aeb | 878 | void ipath_shutdown_device(struct ipath_devdata *); |
0f4fc5eb | 879 | void ipath_clear_freeze(struct ipath_devdata *); |
d41d3aeb BS |
880 | |
881 | struct file_operations; | |
2b8693c0 | 882 | int ipath_cdev_init(int minor, char *name, const struct file_operations *fops, |
f4e91eb4 | 883 | struct cdev **cdevp, struct device **devp); |
d41d3aeb | 884 | void ipath_cdev_cleanup(struct cdev **cdevp, |
f4e91eb4 | 885 | struct device **devp); |
d41d3aeb | 886 | |
a2acb2ff BS |
887 | int ipath_diag_add(struct ipath_devdata *); |
888 | void ipath_diag_remove(struct ipath_devdata *); | |
d41d3aeb | 889 | |
0fd41363 | 890 | extern wait_queue_head_t ipath_state_wait; |
d41d3aeb BS |
891 | |
892 | int ipath_user_add(struct ipath_devdata *dd); | |
a2acb2ff | 893 | void ipath_user_remove(struct ipath_devdata *dd); |
d41d3aeb BS |
894 | |
895 | struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t); | |
896 | ||
897 | extern int ipath_diag_inuse; | |
898 | ||
7d12e780 | 899 | irqreturn_t ipath_intr(int irq, void *devid); |
124b4dcb DO |
900 | int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen, |
901 | ipath_err_t err); | |
d41d3aeb BS |
902 | #if __IPATH_INFO || __IPATH_DBG |
903 | extern const char *ipath_ibcstatus_str[]; | |
904 | #endif | |
905 | ||
906 | /* clean up any per-chip chip-specific stuff */ | |
907 | void ipath_chip_cleanup(struct ipath_devdata *); | |
908 | /* clean up any chip type-specific stuff */ | |
909 | void ipath_chip_done(void); | |
910 | ||
911 | /* check to see if we have to force ordering for write combining */ | |
912 | int ipath_unordered_wc(void); | |
913 | ||
914 | void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first, | |
915 | unsigned cnt); | |
3810f2a8 | 916 | void ipath_cancel_sends(struct ipath_devdata *, int); |
d41d3aeb BS |
917 | |
918 | int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *); | |
f37bda92 | 919 | void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *); |
d41d3aeb BS |
920 | |
921 | int ipath_parse_ushort(const char *str, unsigned short *valp); | |
922 | ||
c59a80ac | 923 | void ipath_kreceive(struct ipath_portdata *); |
d41d3aeb BS |
924 | int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned); |
925 | int ipath_reset_device(int); | |
926 | void ipath_get_faststats(unsigned long); | |
140277e9 | 927 | int ipath_wait_linkstate(struct ipath_devdata *, u32, int); |
34b2aafe BS |
928 | int ipath_set_linkstate(struct ipath_devdata *, u8); |
929 | int ipath_set_mtu(struct ipath_devdata *, u16); | |
930 | int ipath_set_lid(struct ipath_devdata *, u32, u8); | |
30fc5c31 | 931 | int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv); |
6ac50727 DO |
932 | void ipath_enable_armlaunch(struct ipath_devdata *); |
933 | void ipath_disable_armlaunch(struct ipath_devdata *); | |
58411d1c JG |
934 | void ipath_hol_down(struct ipath_devdata *); |
935 | void ipath_hol_up(struct ipath_devdata *); | |
936 | void ipath_hol_event(unsigned long); | |
afce688b RC |
937 | void ipath_toggle_rclkrls(struct ipath_devdata *); |
938 | void ipath_sd7220_clr_ibpar(struct ipath_devdata *); | |
939 | void ipath_set_relock_poll(struct ipath_devdata *, int); | |
940 | void ipath_shutdown_relock_poll(struct ipath_devdata *); | |
d41d3aeb BS |
941 | |
942 | /* for use in system calls, where we want to know device type, etc. */ | |
9929b0fb BS |
943 | #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd |
944 | #define subport_fp(fp) \ | |
945 | ((struct ipath_filedata *)(fp)->private_data)->subport | |
946 | #define tidcursor_fp(fp) \ | |
947 | ((struct ipath_filedata *)(fp)->private_data)->tidcursor | |
afce688b RC |
948 | #define user_sdma_queue_fp(fp) \ |
949 | ((struct ipath_filedata *)(fp)->private_data)->pq | |
d41d3aeb BS |
950 | |
951 | /* | |
952 | * values for ipath_flags | |
953 | */ | |
a51a2513 RC |
954 | /* chip can report link latency (IB 1.2) */ |
955 | #define IPATH_HAS_LINK_LATENCY 0x1 | |
2ba3f56e | 956 | /* The chip is up and initted */ |
d41d3aeb BS |
957 | #define IPATH_INITTED 0x2 |
958 | /* set if any user code has set kr_rcvhdrsize */ | |
959 | #define IPATH_RCVHDRSZ_SET 0x4 | |
960 | /* The chip is present and valid for accesses */ | |
961 | #define IPATH_PRESENT 0x8 | |
962 | /* HT link0 is only 8 bits wide, ignore upper byte crc | |
963 | * errors, etc. */ | |
964 | #define IPATH_8BIT_IN_HT0 0x10 | |
965 | /* HT link1 is only 8 bits wide, ignore upper byte crc | |
966 | * errors, etc. */ | |
967 | #define IPATH_8BIT_IN_HT1 0x20 | |
968 | /* The link is down */ | |
969 | #define IPATH_LINKDOWN 0x40 | |
970 | /* The link level is up (0x11) */ | |
971 | #define IPATH_LINKINIT 0x80 | |
972 | /* The link is in the armed (0x21) state */ | |
973 | #define IPATH_LINKARMED 0x100 | |
974 | /* The link is in the active (0x31) state */ | |
975 | #define IPATH_LINKACTIVE 0x200 | |
976 | /* link current state is unknown */ | |
977 | #define IPATH_LINKUNK 0x400 | |
210d6ca3 RC |
978 | /* Write combining flush needed for PIO */ |
979 | #define IPATH_PIO_FLUSH_WC 0x1000 | |
9355fb6a RC |
980 | /* DMA Receive tail pointer */ |
981 | #define IPATH_NODMA_RTAIL 0x2000 | |
d41d3aeb BS |
982 | /* no IB cable, or no device on IB cable */ |
983 | #define IPATH_NOCABLE 0x4000 | |
984 | /* Supports port zero per packet receive interrupts via | |
985 | * GPIO */ | |
986 | #define IPATH_GPIO_INTR 0x8000 | |
987 | /* uses the coded 4byte TID, not 8 byte */ | |
988 | #define IPATH_4BYTE_TID 0x10000 | |
989 | /* packet/word counters are 32 bit, else those 4 counters | |
990 | * are 64bit */ | |
991 | #define IPATH_32BITCOUNTERS 0x20000 | |
7da0498e AJ |
992 | /* Interrupt register is 64 bits */ |
993 | #define IPATH_INTREG_64 0x40000 | |
9355fb6a | 994 | /* can miss port0 rx interrupts */ |
d41d3aeb | 995 | #define IPATH_DISABLED 0x80000 /* administratively disabled */ |
2c9446a1 BS |
996 | /* Use GPIO interrupts for new counters */ |
997 | #define IPATH_GPIO_ERRINTRS 0x100000 | |
4ea61b54 | 998 | #define IPATH_SWAP_PIOBUFS 0x200000 |
afce688b RC |
999 | /* Supports Send DMA */ |
1000 | #define IPATH_HAS_SEND_DMA 0x400000 | |
1001 | /* Supports Send Count (not just word count) in PBC */ | |
1002 | #define IPATH_HAS_PBC_CNT 0x800000 | |
359193ef MA |
1003 | /* Suppress heartbeat, even if turning off loopback */ |
1004 | #define IPATH_NO_HRTBT 0x1000000 | |
afce688b | 1005 | #define IPATH_HAS_THRESH_UPDATE 0x4000000 |
359193ef | 1006 | #define IPATH_HAS_MULT_IB_SPEED 0x8000000 |
afce688b RC |
1007 | #define IPATH_IB_AUTONEG_INPROG 0x10000000 |
1008 | #define IPATH_IB_AUTONEG_FAILED 0x20000000 | |
4330e4da MA |
1009 | /* Linkdown-disable intentionally, Do not attempt to bring up */ |
1010 | #define IPATH_IB_LINK_DISABLED 0x40000000 | |
58411d1c | 1011 | #define IPATH_IB_FORCE_NOTIFY 0x80000000 /* force notify on next ib change */ |
2c9446a1 BS |
1012 | |
1013 | /* Bits in GPIO for the added interrupts */ | |
1014 | #define IPATH_GPIO_PORT0_BIT 2 | |
1015 | #define IPATH_GPIO_RXUVL_BIT 3 | |
1016 | #define IPATH_GPIO_OVRUN_BIT 4 | |
1017 | #define IPATH_GPIO_LLI_BIT 5 | |
1018 | #define IPATH_GPIO_ERRINTR_MASK 0x38 | |
d41d3aeb BS |
1019 | |
1020 | /* portdata flag bit offsets */ | |
1021 | /* waiting for a packet to arrive */ | |
1022 | #define IPATH_PORT_WAITING_RCV 2 | |
947d7617 RC |
1023 | /* master has not finished initializing */ |
1024 | #define IPATH_PORT_MASTER_UNINIT 4 | |
f2d04231 RW |
1025 | /* waiting for an urgent packet to arrive */ |
1026 | #define IPATH_PORT_WAITING_URG 5 | |
d41d3aeb BS |
1027 | |
1028 | /* free up any allocated data at closes */ | |
1029 | void ipath_free_data(struct ipath_portdata *dd); | |
c4b4d16e RC |
1030 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32, u32 *); |
1031 | void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start, | |
1032 | unsigned len, int avail); | |
afce688b | 1033 | void ipath_init_iba7220_funcs(struct ipath_devdata *); |
525d0ca1 BS |
1034 | void ipath_init_iba6120_funcs(struct ipath_devdata *); |
1035 | void ipath_init_iba6110_funcs(struct ipath_devdata *); | |
f2080fa3 | 1036 | void ipath_get_eeprom_info(struct ipath_devdata *); |
aecd3b5a MA |
1037 | int ipath_update_eeprom_log(struct ipath_devdata *dd); |
1038 | void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr); | |
d41d3aeb | 1039 | u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg); |
e2ab41ca | 1040 | void ipath_disarm_senderrbufs(struct ipath_devdata *); |
c4b4d16e | 1041 | void ipath_force_pio_avail_update(struct ipath_devdata *); |
49739b3e | 1042 | void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev); |
d41d3aeb | 1043 | |
82466f00 MA |
1044 | /* |
1045 | * Set LED override, only the two LSBs have "public" meaning, but | |
1046 | * any non-zero value substitutes them for the Link and LinkTrain | |
1047 | * LED states. | |
1048 | */ | |
1049 | #define IPATH_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ | |
1050 | #define IPATH_LED_LOG 2 /* Logical (link) YELLOW LED */ | |
1051 | void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val); | |
1052 | ||
afce688b RC |
1053 | /* send dma routines */ |
1054 | int setup_sdma(struct ipath_devdata *); | |
1055 | void teardown_sdma(struct ipath_devdata *); | |
124b4dcb | 1056 | void ipath_restart_sdma(struct ipath_devdata *); |
afce688b RC |
1057 | void ipath_sdma_intr(struct ipath_devdata *); |
1058 | int ipath_sdma_verbs_send(struct ipath_devdata *, struct ipath_sge_state *, | |
1059 | u32, struct ipath_verbs_txreq *); | |
1060 | /* ipath_sdma_lock should be locked before calling this. */ | |
1061 | int ipath_sdma_make_progress(struct ipath_devdata *dd); | |
1062 | ||
1063 | /* must be called under ipath_sdma_lock */ | |
1064 | static inline u16 ipath_sdma_descq_freecnt(const struct ipath_devdata *dd) | |
1065 | { | |
1066 | return dd->ipath_sdma_descq_cnt - | |
1067 | (dd->ipath_sdma_descq_added - dd->ipath_sdma_descq_removed) - | |
1068 | 1 - dd->ipath_sdma_desc_nreserved; | |
1069 | } | |
1070 | ||
1071 | static inline void ipath_sdma_desc_reserve(struct ipath_devdata *dd, u16 cnt) | |
1072 | { | |
1073 | dd->ipath_sdma_desc_nreserved += cnt; | |
1074 | } | |
1075 | ||
1076 | static inline void ipath_sdma_desc_unreserve(struct ipath_devdata *dd, u16 cnt) | |
1077 | { | |
1078 | dd->ipath_sdma_desc_nreserved -= cnt; | |
1079 | } | |
1080 | ||
d41d3aeb BS |
1081 | /* |
1082 | * number of words used for protocol header if not set by ipath_userinit(); | |
1083 | */ | |
1084 | #define IPATH_DFLT_RCVHDRSIZE 9 | |
1085 | ||
d41d3aeb | 1086 | int ipath_get_user_pages(unsigned long, size_t, struct page **); |
d41d3aeb BS |
1087 | void ipath_release_user_pages(struct page **, size_t); |
1088 | void ipath_release_user_pages_on_close(struct page **, size_t); | |
1089 | int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int); | |
1090 | int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int); | |
d84e0b28 MA |
1091 | int ipath_tempsense_read(struct ipath_devdata *, u8 regnum); |
1092 | int ipath_tempsense_write(struct ipath_devdata *, u8 regnum, u8 data); | |
d41d3aeb BS |
1093 | |
1094 | /* these are used for the registers that vary with port */ | |
1095 | void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg, | |
1096 | unsigned, u64); | |
d41d3aeb BS |
1097 | |
1098 | /* | |
1099 | * We could have a single register get/put routine, that takes a group type, | |
1100 | * but this is somewhat clearer and cleaner. It also gives us some error | |
1101 | * checking. 64 bit register reads should always work, but are inefficient | |
1102 | * on opteron (the northbridge always generates 2 separate HT 32 bit reads), | |
1103 | * so we use kreg32 wherever possible. User register and counter register | |
1104 | * reads are always 32 bit reads, so only one form of those routines. | |
1105 | */ | |
1106 | ||
1107 | /* | |
1108 | * At the moment, none of the s-registers are writable, so no | |
afce688b | 1109 | * ipath_write_sreg(). |
d41d3aeb BS |
1110 | */ |
1111 | ||
1112 | /** | |
1113 | * ipath_read_ureg32 - read 32-bit virtualized per-port register | |
1114 | * @dd: device | |
1115 | * @regno: register number | |
1116 | * @port: port number | |
1117 | * | |
1118 | * Return the contents of a register that is virtualized to be per port. | |
685f97e8 BS |
1119 | * Returns -1 on errors (not distinguishable from valid contents at |
1120 | * runtime; we may add a separate error variable at some point). | |
d41d3aeb BS |
1121 | */ |
1122 | static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd, | |
1123 | ipath_ureg regno, int port) | |
1124 | { | |
c71c30dc | 1125 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
1126 | return 0; |
1127 | ||
1128 | return readl(regno + (u64 __iomem *) | |
1129 | (dd->ipath_uregbase + | |
1130 | (char __iomem *)dd->ipath_kregbase + | |
a18e26ae | 1131 | dd->ipath_ureg_align * port)); |
d41d3aeb BS |
1132 | } |
1133 | ||
1134 | /** | |
1135 | * ipath_write_ureg - write 32-bit virtualized per-port register | |
1136 | * @dd: device | |
1137 | * @regno: register number | |
1138 | * @value: value | |
1139 | * @port: port | |
1140 | * | |
1141 | * Write the contents of a register that is virtualized to be per port. | |
1142 | */ | |
1143 | static inline void ipath_write_ureg(const struct ipath_devdata *dd, | |
1144 | ipath_ureg regno, u64 value, int port) | |
1145 | { | |
1146 | u64 __iomem *ubase = (u64 __iomem *) | |
1147 | (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase + | |
a18e26ae | 1148 | dd->ipath_ureg_align * port); |
d41d3aeb BS |
1149 | if (dd->ipath_kregbase) |
1150 | writeq(value, &ubase[regno]); | |
1151 | } | |
1152 | ||
1153 | static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd, | |
1154 | ipath_kreg regno) | |
1155 | { | |
c71c30dc | 1156 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
1157 | return -1; |
1158 | return readl((u32 __iomem *) & dd->ipath_kregbase[regno]); | |
1159 | } | |
1160 | ||
1161 | static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd, | |
1162 | ipath_kreg regno) | |
1163 | { | |
c71c30dc | 1164 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
1165 | return -1; |
1166 | ||
1167 | return readq(&dd->ipath_kregbase[regno]); | |
1168 | } | |
1169 | ||
1170 | static inline void ipath_write_kreg(const struct ipath_devdata *dd, | |
1171 | ipath_kreg regno, u64 value) | |
1172 | { | |
1173 | if (dd->ipath_kregbase) | |
1174 | writeq(value, &dd->ipath_kregbase[regno]); | |
1175 | } | |
1176 | ||
1177 | static inline u64 ipath_read_creg(const struct ipath_devdata *dd, | |
1178 | ipath_sreg regno) | |
1179 | { | |
c71c30dc | 1180 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
1181 | return 0; |
1182 | ||
1183 | return readq(regno + (u64 __iomem *) | |
1184 | (dd->ipath_cregbase + | |
1185 | (char __iomem *)dd->ipath_kregbase)); | |
1186 | } | |
1187 | ||
1188 | static inline u32 ipath_read_creg32(const struct ipath_devdata *dd, | |
1189 | ipath_sreg regno) | |
1190 | { | |
c71c30dc | 1191 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
1192 | return 0; |
1193 | return readl(regno + (u64 __iomem *) | |
1194 | (dd->ipath_cregbase + | |
1195 | (char __iomem *)dd->ipath_kregbase)); | |
1196 | } | |
1197 | ||
6c719cae RC |
1198 | static inline void ipath_write_creg(const struct ipath_devdata *dd, |
1199 | ipath_creg regno, u64 value) | |
1200 | { | |
1201 | if (dd->ipath_kregbase) | |
1202 | writeq(value, regno + (u64 __iomem *) | |
1203 | (dd->ipath_cregbase + | |
1204 | (char __iomem *)dd->ipath_kregbase)); | |
1205 | } | |
1206 | ||
c59a80ac RC |
1207 | static inline void ipath_clear_rcvhdrtail(const struct ipath_portdata *pd) |
1208 | { | |
1209 | *((u64 *) pd->port_rcvhdrtail_kvaddr) = 0ULL; | |
1210 | } | |
1211 | ||
1212 | static inline u32 ipath_get_rcvhdrtail(const struct ipath_portdata *pd) | |
1213 | { | |
1214 | return (u32) le64_to_cpu(*((volatile __le64 *) | |
1215 | pd->port_rcvhdrtail_kvaddr)); | |
1216 | } | |
1217 | ||
9355fb6a RC |
1218 | static inline u32 ipath_get_hdrqtail(const struct ipath_portdata *pd) |
1219 | { | |
1220 | const struct ipath_devdata *dd = pd->port_dd; | |
1221 | u32 hdrqtail; | |
1222 | ||
1223 | if (dd->ipath_flags & IPATH_NODMA_RTAIL) { | |
1224 | __le32 *rhf_addr; | |
1225 | u32 seq; | |
1226 | ||
1227 | rhf_addr = (__le32 *) pd->port_rcvhdrq + | |
1228 | pd->port_head + dd->ipath_rhf_offset; | |
1229 | seq = ipath_hdrget_seq(rhf_addr); | |
1230 | hdrqtail = pd->port_head; | |
1231 | if (seq == pd->port_seq_cnt) | |
1232 | hdrqtail++; | |
1233 | } else | |
1234 | hdrqtail = ipath_get_rcvhdrtail(pd); | |
1235 | ||
1236 | return hdrqtail; | |
1237 | } | |
1238 | ||
7da0498e AJ |
1239 | static inline u64 ipath_read_ireg(const struct ipath_devdata *dd, ipath_kreg r) |
1240 | { | |
1241 | return (dd->ipath_flags & IPATH_INTREG_64) ? | |
1242 | ipath_read_kreg64(dd, r) : ipath_read_kreg32(dd, r); | |
1243 | } | |
1244 | ||
c4bce803 DO |
1245 | /* |
1246 | * from contents of IBCStatus (or a saved copy), return linkstate | |
1247 | * Report ACTIVE_DEFER as ACTIVE, because we treat them the same | |
1248 | * everywhere, anyway (and should be, for almost all purposes). | |
1249 | */ | |
1250 | static inline u32 ipath_ib_linkstate(struct ipath_devdata *dd, u64 ibcs) | |
1251 | { | |
1252 | u32 state = (u32)(ibcs >> dd->ibcs_ls_shift) & | |
1253 | INFINIPATH_IBCS_LINKSTATE_MASK; | |
1254 | if (state == INFINIPATH_IBCS_L_STATE_ACT_DEFER) | |
1255 | state = INFINIPATH_IBCS_L_STATE_ACTIVE; | |
1256 | return state; | |
1257 | } | |
1258 | ||
1259 | /* from contents of IBCStatus (or a saved copy), return linktrainingstate */ | |
1260 | static inline u32 ipath_ib_linktrstate(struct ipath_devdata *dd, u64 ibcs) | |
1261 | { | |
1262 | return (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & | |
1263 | dd->ibcs_lts_mask; | |
1264 | } | |
1265 | ||
58411d1c JG |
1266 | /* |
1267 | * from contents of IBCStatus (or a saved copy), return logical link state | |
1268 | * combination of link state and linktraining state (down, active, init, | |
1269 | * arm, etc. | |
1270 | */ | |
1271 | static inline u32 ipath_ib_state(struct ipath_devdata *dd, u64 ibcs) | |
1272 | { | |
1273 | u32 ibs; | |
1274 | ibs = (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & | |
1275 | dd->ibcs_lts_mask; | |
1276 | ibs |= (u32)(ibcs & | |
1277 | (INFINIPATH_IBCS_LINKSTATE_MASK << dd->ibcs_ls_shift)); | |
1278 | return ibs; | |
1279 | } | |
1280 | ||
d41d3aeb BS |
1281 | /* |
1282 | * sysfs interface. | |
1283 | */ | |
1284 | ||
1285 | struct device_driver; | |
1286 | ||
b55f4f06 | 1287 | extern const char ib_ipath_version[]; |
d41d3aeb | 1288 | |
a4dbd674 | 1289 | extern const struct attribute_group *ipath_driver_attr_groups[]; |
d41d3aeb BS |
1290 | |
1291 | int ipath_device_create_group(struct device *, struct ipath_devdata *); | |
1292 | void ipath_device_remove_group(struct device *, struct ipath_devdata *); | |
1293 | int ipath_expose_reset(struct device *); | |
1294 | ||
1295 | int ipath_init_ipathfs(void); | |
1296 | void ipath_exit_ipathfs(void); | |
1297 | int ipathfs_add_device(struct ipath_devdata *); | |
1298 | int ipathfs_remove_device(struct ipath_devdata *); | |
1299 | ||
1fd3b40f BS |
1300 | /* |
1301 | * dma_addr wrappers - all 0's invalid for hw | |
1302 | */ | |
1303 | dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long, | |
1304 | size_t, int); | |
1305 | dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int); | |
afce688b | 1306 | const char *ipath_get_unit_name(int unit); |
1fd3b40f | 1307 | |
d41d3aeb BS |
1308 | /* |
1309 | * Flush write combining store buffers (if present) and perform a write | |
1310 | * barrier. | |
1311 | */ | |
1312 | #if defined(CONFIG_X86_64) | |
1313 | #define ipath_flush_wc() asm volatile("sfence" ::: "memory") | |
1314 | #else | |
1315 | #define ipath_flush_wc() wmb() | |
1316 | #endif | |
1317 | ||
1318 | extern unsigned ipath_debug; /* debugging bit mask */ | |
72708a0a | 1319 | extern unsigned ipath_linkrecovery; |
826d8010 | 1320 | extern unsigned ipath_mtu4096; |
d41d3aeb BS |
1321 | extern struct mutex ipath_mutex; |
1322 | ||
b55f4f06 | 1323 | #define IPATH_DRV_NAME "ib_ipath" |
d41d3aeb | 1324 | #define IPATH_MAJOR 233 |
a2acb2ff | 1325 | #define IPATH_USER_MINOR_BASE 0 |
98341f26 | 1326 | #define IPATH_DIAGPKT_MINOR 127 |
a2acb2ff BS |
1327 | #define IPATH_DIAG_MINOR_BASE 129 |
1328 | #define IPATH_NMINORS 255 | |
d41d3aeb BS |
1329 | |
1330 | #define ipath_dev_err(dd,fmt,...) \ | |
1331 | do { \ | |
1332 | const struct ipath_devdata *__dd = (dd); \ | |
1333 | if (__dd->pcidev) \ | |
1334 | dev_err(&__dd->pcidev->dev, "%s: " fmt, \ | |
1335 | ipath_get_unit_name(__dd->ipath_unit), \ | |
1336 | ##__VA_ARGS__); \ | |
1337 | else \ | |
1338 | printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \ | |
1339 | ipath_get_unit_name(__dd->ipath_unit), \ | |
1340 | ##__VA_ARGS__); \ | |
1341 | } while (0) | |
1342 | ||
1343 | #if _IPATH_DEBUGGING | |
1344 | ||
1345 | # define __IPATH_DBG_WHICH(which,fmt,...) \ | |
1346 | do { \ | |
2ba3f56e | 1347 | if (unlikely(ipath_debug & (which))) \ |
d41d3aeb BS |
1348 | printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \ |
1349 | __func__,##__VA_ARGS__); \ | |
1350 | } while(0) | |
1351 | ||
1352 | # define ipath_dbg(fmt,...) \ | |
1353 | __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__) | |
1354 | # define ipath_cdbg(which,fmt,...) \ | |
1355 | __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__) | |
1356 | ||
1357 | #else /* ! _IPATH_DEBUGGING */ | |
1358 | ||
1359 | # define ipath_dbg(fmt,...) | |
1360 | # define ipath_cdbg(which,fmt,...) | |
1361 | ||
1362 | #endif /* _IPATH_DEBUGGING */ | |
1363 | ||
8d588f8b BS |
1364 | /* |
1365 | * this is used for formatting hw error messages... | |
1366 | */ | |
1367 | struct ipath_hwerror_msgs { | |
1368 | u64 mask; | |
1369 | const char *msg; | |
1370 | }; | |
1371 | ||
1372 | #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b } | |
1373 | ||
1374 | /* in ipath_intr.c... */ | |
1375 | void ipath_format_hwerrors(u64 hwerrs, | |
1376 | const struct ipath_hwerror_msgs *hwerrmsgs, | |
1377 | size_t nhwerrmsgs, | |
1378 | char *msg, size_t lmsg); | |
1379 | ||
d41d3aeb | 1380 | #endif /* _IPATH_KERNEL_H */ |