Commit | Line | Data |
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097709fe | 1 | /* |
759d5768 | 2 | * Copyright (c) 2006 QLogic, Inc. All rights reserved. |
097709fe BS |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/pci.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/vmalloc.h> | |
37 | ||
38 | #include "ipath_kernel.h" | |
39 | #include "ips_common.h" | |
40 | ||
41 | /* | |
42 | * min buffers we want to have per port, after driver | |
43 | */ | |
44 | #define IPATH_MIN_USER_PORT_BUFCNT 8 | |
45 | ||
46 | /* | |
47 | * Number of ports we are configured to use (to allow for more pio | |
48 | * buffers per port, etc.) Zero means use chip value. | |
49 | */ | |
50 | static ushort ipath_cfgports; | |
51 | ||
52 | module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO); | |
53 | MODULE_PARM_DESC(cfgports, "Set max number of ports to use"); | |
54 | ||
55 | /* | |
56 | * Number of buffers reserved for driver (layered drivers and SMA | |
52e7fad8 BS |
57 | * send). Reserved at end of buffer list. Initialized based on |
58 | * number of PIO buffers if not set via module interface. | |
59 | * The problem with this is that it's global, but we'll use different | |
60 | * numbers for different chip types. So the default value is not | |
61 | * very useful. I've redefined it for the 1.3 release so that it's | |
62 | * zero unless set by the user to something else, in which case we | |
63 | * try to respect it. | |
097709fe | 64 | */ |
52e7fad8 | 65 | static ushort ipath_kpiobufs; |
097709fe BS |
66 | |
67 | static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp); | |
68 | ||
52e7fad8 | 69 | module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort, |
097709fe BS |
70 | &ipath_kpiobufs, S_IWUSR | S_IRUGO); |
71 | MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver"); | |
72 | ||
73 | /** | |
74 | * create_port0_egr - allocate the eager TID buffers | |
75 | * @dd: the infinipath device | |
76 | * | |
77 | * This code is now quite different for user and kernel, because | |
78 | * the kernel uses skb's, for the accelerated network performance. | |
79 | * This is the kernel (port0) version. | |
80 | * | |
81 | * Allocate the eager TID buffers and program them into infinipath. | |
82 | * We use the network layer alloc_skb() allocator to allocate the | |
83 | * memory, and either use the buffers as is for things like SMA | |
84 | * packets, or pass the buffers up to the ipath layered driver and | |
85 | * thence the network layer, replacing them as we do so (see | |
86 | * ipath_rcv_layer()). | |
87 | */ | |
88 | static int create_port0_egr(struct ipath_devdata *dd) | |
89 | { | |
90 | unsigned e, egrcnt; | |
91 | struct sk_buff **skbs; | |
92 | int ret; | |
93 | ||
94 | egrcnt = dd->ipath_rcvegrcnt; | |
95 | ||
96 | skbs = vmalloc(sizeof(*dd->ipath_port0_skbs) * egrcnt); | |
97 | if (skbs == NULL) { | |
98 | ipath_dev_err(dd, "allocation error for eager TID " | |
99 | "skb array\n"); | |
100 | ret = -ENOMEM; | |
101 | goto bail; | |
102 | } | |
103 | for (e = 0; e < egrcnt; e++) { | |
104 | /* | |
105 | * This is a bit tricky in that we allocate extra | |
106 | * space for 2 bytes of the 14 byte ethernet header. | |
107 | * These two bytes are passed in the ipath header so | |
108 | * the rest of the data is word aligned. We allocate | |
109 | * 4 bytes so that the data buffer stays word aligned. | |
110 | * See ipath_kreceive() for more details. | |
111 | */ | |
112 | skbs[e] = ipath_alloc_skb(dd, GFP_KERNEL); | |
113 | if (!skbs[e]) { | |
114 | ipath_dev_err(dd, "SKB allocation error for " | |
115 | "eager TID %u\n", e); | |
116 | while (e != 0) | |
117 | dev_kfree_skb(skbs[--e]); | |
60460dfd | 118 | vfree(skbs); |
097709fe BS |
119 | ret = -ENOMEM; |
120 | goto bail; | |
121 | } | |
122 | } | |
123 | /* | |
124 | * After loop above, so we can test non-NULL to see if ready | |
125 | * to use at receive, etc. | |
126 | */ | |
127 | dd->ipath_port0_skbs = skbs; | |
128 | ||
129 | for (e = 0; e < egrcnt; e++) { | |
130 | unsigned long phys = | |
131 | virt_to_phys(dd->ipath_port0_skbs[e]->data); | |
132 | dd->ipath_f_put_tid(dd, e + (u64 __iomem *) | |
133 | ((char __iomem *) dd->ipath_kregbase + | |
134 | dd->ipath_rcvegrbase), 0, phys); | |
135 | } | |
136 | ||
137 | ret = 0; | |
138 | ||
139 | bail: | |
140 | return ret; | |
141 | } | |
142 | ||
143 | static int bringup_link(struct ipath_devdata *dd) | |
144 | { | |
145 | u64 val, ibc; | |
146 | int ret = 0; | |
147 | ||
148 | /* hold IBC in reset */ | |
149 | dd->ipath_control &= ~INFINIPATH_C_LINKENABLE; | |
150 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
151 | dd->ipath_control); | |
152 | ||
153 | /* | |
154 | * Note that prior to try 14 or 15 of IB, the credit scaling | |
155 | * wasn't working, because it was swapped for writes with the | |
156 | * 1 bit default linkstate field | |
157 | */ | |
158 | ||
159 | /* ignore pbc and align word */ | |
160 | val = dd->ipath_piosize2k - 2 * sizeof(u32); | |
161 | /* | |
162 | * for ICRC, which we only send in diag test pkt mode, and we | |
163 | * don't need to worry about that for mtu | |
164 | */ | |
165 | val += 1; | |
166 | /* | |
167 | * Set the IBC maxpktlength to the size of our pio buffers the | |
168 | * maxpktlength is in words. This is *not* the IB data MTU. | |
169 | */ | |
170 | ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT; | |
171 | /* in KB */ | |
172 | ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT; | |
173 | /* | |
174 | * How often flowctrl sent. More or less in usecs; balance against | |
175 | * watermark value, so that in theory senders always get a flow | |
176 | * control update in time to not let the IB link go idle. | |
177 | */ | |
178 | ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT; | |
179 | /* max error tolerance */ | |
180 | ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT; | |
181 | /* use "real" buffer space for */ | |
182 | ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT; | |
183 | /* IB credit flow control. */ | |
184 | ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT; | |
185 | /* initially come up waiting for TS1, without sending anything. */ | |
186 | dd->ipath_ibcctrl = ibc; | |
187 | /* | |
188 | * Want to start out with both LINKCMD and LINKINITCMD in NOP | |
189 | * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that | |
190 | * to stay a NOP | |
191 | */ | |
192 | ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE << | |
193 | INFINIPATH_IBCC_LINKINITCMD_SHIFT; | |
194 | ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n", | |
195 | (unsigned long long) ibc); | |
196 | ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc); | |
197 | ||
198 | // be sure chip saw it | |
199 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); | |
200 | ||
201 | ret = dd->ipath_f_bringup_serdes(dd); | |
202 | ||
203 | if (ret) | |
204 | dev_info(&dd->pcidev->dev, "Could not initialize SerDes, " | |
205 | "not usable\n"); | |
206 | else { | |
207 | /* enable IBC */ | |
208 | dd->ipath_control |= INFINIPATH_C_LINKENABLE; | |
209 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, | |
210 | dd->ipath_control); | |
211 | } | |
212 | ||
213 | return ret; | |
214 | } | |
215 | ||
216 | static int init_chip_first(struct ipath_devdata *dd, | |
217 | struct ipath_portdata **pdp) | |
218 | { | |
219 | struct ipath_portdata *pd = NULL; | |
220 | int ret = 0; | |
221 | u64 val; | |
222 | ||
223 | /* | |
224 | * skip cfgports stuff because we are not allocating memory, | |
225 | * and we don't want problems if the portcnt changed due to | |
226 | * cfgports. We do still check and report a difference, if | |
227 | * not same (should be impossible). | |
228 | */ | |
229 | dd->ipath_portcnt = | |
230 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt); | |
231 | if (!ipath_cfgports) | |
232 | dd->ipath_cfgports = dd->ipath_portcnt; | |
233 | else if (ipath_cfgports <= dd->ipath_portcnt) { | |
234 | dd->ipath_cfgports = ipath_cfgports; | |
235 | ipath_dbg("Configured to use %u ports out of %u in chip\n", | |
236 | dd->ipath_cfgports, dd->ipath_portcnt); | |
237 | } else { | |
238 | dd->ipath_cfgports = dd->ipath_portcnt; | |
239 | ipath_dbg("Tried to configured to use %u ports; chip " | |
240 | "only supports %u\n", ipath_cfgports, | |
241 | dd->ipath_portcnt); | |
242 | } | |
243 | dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_cfgports, | |
244 | GFP_KERNEL); | |
245 | ||
246 | if (!dd->ipath_pd) { | |
247 | ipath_dev_err(dd, "Unable to allocate portdata array, " | |
248 | "failing\n"); | |
249 | ret = -ENOMEM; | |
250 | goto done; | |
251 | } | |
252 | ||
253 | dd->ipath_lastegrheads = kzalloc(sizeof(*dd->ipath_lastegrheads) | |
254 | * dd->ipath_cfgports, | |
255 | GFP_KERNEL); | |
256 | dd->ipath_lastrcvhdrqtails = | |
257 | kzalloc(sizeof(*dd->ipath_lastrcvhdrqtails) | |
258 | * dd->ipath_cfgports, GFP_KERNEL); | |
259 | ||
260 | if (!dd->ipath_lastegrheads || !dd->ipath_lastrcvhdrqtails) { | |
261 | ipath_dev_err(dd, "Unable to allocate head arrays, " | |
262 | "failing\n"); | |
263 | ret = -ENOMEM; | |
264 | goto done; | |
265 | } | |
266 | ||
267 | dd->ipath_pd[0] = kzalloc(sizeof(*pd), GFP_KERNEL); | |
268 | ||
269 | if (!dd->ipath_pd[0]) { | |
270 | ipath_dev_err(dd, "Unable to allocate portdata for port " | |
271 | "0, failing\n"); | |
272 | ret = -ENOMEM; | |
273 | goto done; | |
274 | } | |
275 | pd = dd->ipath_pd[0]; | |
276 | pd->port_dd = dd; | |
277 | pd->port_port = 0; | |
278 | pd->port_cnt = 1; | |
279 | /* The port 0 pkey table is used by the layer interface. */ | |
280 | pd->port_pkeys[0] = IPS_DEFAULT_P_KEY; | |
281 | dd->ipath_rcvtidcnt = | |
282 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt); | |
283 | dd->ipath_rcvtidbase = | |
284 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase); | |
285 | dd->ipath_rcvegrcnt = | |
286 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt); | |
287 | dd->ipath_rcvegrbase = | |
288 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase); | |
289 | dd->ipath_palign = | |
290 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign); | |
291 | dd->ipath_piobufbase = | |
292 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase); | |
293 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize); | |
294 | dd->ipath_piosize2k = val & ~0U; | |
295 | dd->ipath_piosize4k = val >> 32; | |
296 | dd->ipath_ibmtu = 4096; /* default to largest legal MTU */ | |
297 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt); | |
298 | dd->ipath_piobcnt2k = val & ~0U; | |
299 | dd->ipath_piobcnt4k = val >> 32; | |
300 | dd->ipath_pio2kbase = | |
301 | (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) + | |
302 | (dd->ipath_piobufbase & 0xffffffff)); | |
303 | if (dd->ipath_piobcnt4k) { | |
304 | dd->ipath_pio4kbase = (u32 __iomem *) | |
305 | (((char __iomem *) dd->ipath_kregbase) + | |
306 | (dd->ipath_piobufbase >> 32)); | |
307 | /* | |
308 | * 4K buffers take 2 pages; we use roundup just to be | |
309 | * paranoid; we calculate it once here, rather than on | |
310 | * ever buf allocate | |
311 | */ | |
312 | dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k, | |
313 | dd->ipath_palign); | |
314 | ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p " | |
315 | "(%x aligned)\n", | |
316 | dd->ipath_piobcnt2k, dd->ipath_piosize2k, | |
317 | dd->ipath_pio2kbase, dd->ipath_piobcnt4k, | |
318 | dd->ipath_piosize4k, dd->ipath_pio4kbase, | |
319 | dd->ipath_4kalign); | |
320 | } | |
321 | else ipath_dbg("%u 2k piobufs @ %p\n", | |
322 | dd->ipath_piobcnt2k, dd->ipath_pio2kbase); | |
323 | ||
324 | spin_lock_init(&dd->ipath_tid_lock); | |
325 | ||
326 | done: | |
327 | *pdp = pd; | |
328 | return ret; | |
329 | } | |
330 | ||
331 | /** | |
332 | * init_chip_reset - re-initialize after a reset, or enable | |
333 | * @dd: the infinipath device | |
334 | * @pdp: output for port data | |
335 | * | |
336 | * sanity check at least some of the values after reset, and | |
337 | * ensure no receive or transmit (explictly, in case reset | |
338 | * failed | |
339 | */ | |
340 | static int init_chip_reset(struct ipath_devdata *dd, | |
341 | struct ipath_portdata **pdp) | |
342 | { | |
343 | struct ipath_portdata *pd; | |
344 | u32 rtmp; | |
345 | ||
346 | *pdp = pd = dd->ipath_pd[0]; | |
347 | /* ensure chip does no sends or receives while we re-initialize */ | |
348 | dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U; | |
349 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 0); | |
350 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0); | |
351 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0); | |
352 | ||
353 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt); | |
354 | if (dd->ipath_portcnt != rtmp) | |
355 | dev_info(&dd->pcidev->dev, "portcnt was %u before " | |
356 | "reset, now %u, using original\n", | |
357 | dd->ipath_portcnt, rtmp); | |
358 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt); | |
359 | if (rtmp != dd->ipath_rcvtidcnt) | |
360 | dev_info(&dd->pcidev->dev, "tidcnt was %u before " | |
361 | "reset, now %u, using original\n", | |
362 | dd->ipath_rcvtidcnt, rtmp); | |
363 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase); | |
364 | if (rtmp != dd->ipath_rcvtidbase) | |
365 | dev_info(&dd->pcidev->dev, "tidbase was %u before " | |
366 | "reset, now %u, using original\n", | |
367 | dd->ipath_rcvtidbase, rtmp); | |
368 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt); | |
369 | if (rtmp != dd->ipath_rcvegrcnt) | |
370 | dev_info(&dd->pcidev->dev, "egrcnt was %u before " | |
371 | "reset, now %u, using original\n", | |
372 | dd->ipath_rcvegrcnt, rtmp); | |
373 | rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase); | |
374 | if (rtmp != dd->ipath_rcvegrbase) | |
375 | dev_info(&dd->pcidev->dev, "egrbase was %u before " | |
376 | "reset, now %u, using original\n", | |
377 | dd->ipath_rcvegrbase, rtmp); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static int init_pioavailregs(struct ipath_devdata *dd) | |
383 | { | |
384 | int ret; | |
385 | ||
386 | dd->ipath_pioavailregs_dma = dma_alloc_coherent( | |
387 | &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys, | |
388 | GFP_KERNEL); | |
389 | if (!dd->ipath_pioavailregs_dma) { | |
390 | ipath_dev_err(dd, "failed to allocate PIOavail reg area " | |
391 | "in memory\n"); | |
392 | ret = -ENOMEM; | |
393 | goto done; | |
394 | } | |
395 | ||
396 | /* | |
397 | * we really want L2 cache aligned, but for current CPUs of | |
398 | * interest, they are the same. | |
399 | */ | |
400 | dd->ipath_statusp = (u64 *) | |
401 | ((char *)dd->ipath_pioavailregs_dma + | |
402 | ((2 * L1_CACHE_BYTES + | |
403 | dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES)); | |
404 | /* copy the current value now that it's really allocated */ | |
405 | *dd->ipath_statusp = dd->_ipath_status; | |
406 | /* | |
407 | * setup buffer to hold freeze msg, accessible to apps, | |
408 | * following statusp | |
409 | */ | |
410 | dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1]; | |
411 | /* and its length */ | |
412 | dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]); | |
413 | ||
f37bda92 | 414 | ret = 0; |
097709fe | 415 | |
097709fe BS |
416 | done: |
417 | return ret; | |
418 | } | |
419 | ||
420 | /** | |
421 | * init_shadow_tids - allocate the shadow TID array | |
422 | * @dd: the infinipath device | |
423 | * | |
424 | * allocate the shadow TID array, so we can ipath_munlock previous | |
425 | * entries. It may make more sense to move the pageshadow to the | |
426 | * port data structure, so we only allocate memory for ports actually | |
427 | * in use, since we at 8k per port, now. | |
428 | */ | |
429 | static void init_shadow_tids(struct ipath_devdata *dd) | |
430 | { | |
431 | dd->ipath_pageshadow = (struct page **) | |
432 | vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
433 | sizeof(struct page *)); | |
434 | if (!dd->ipath_pageshadow) | |
435 | ipath_dev_err(dd, "failed to allocate shadow page * " | |
436 | "array, no expected sends!\n"); | |
437 | else | |
438 | memset(dd->ipath_pageshadow, 0, | |
439 | dd->ipath_cfgports * dd->ipath_rcvtidcnt * | |
440 | sizeof(struct page *)); | |
441 | } | |
442 | ||
443 | static void enable_chip(struct ipath_devdata *dd, | |
444 | struct ipath_portdata *pd, int reinit) | |
445 | { | |
446 | u32 val; | |
447 | int i; | |
448 | ||
449 | if (!reinit) { | |
450 | init_waitqueue_head(&ipath_sma_state_wait); | |
451 | } | |
452 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, | |
453 | dd->ipath_rcvctrl); | |
454 | ||
455 | /* Enable PIO send, and update of PIOavail regs to memory. */ | |
456 | dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE | | |
457 | INFINIPATH_S_PIOBUFAVAILUPD; | |
458 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
459 | dd->ipath_sendctrl); | |
460 | ||
461 | /* | |
462 | * enable port 0 receive, and receive interrupt. other ports | |
463 | * done as user opens and inits them. | |
464 | */ | |
465 | dd->ipath_rcvctrl = INFINIPATH_R_TAILUPD | | |
466 | (1ULL << INFINIPATH_R_PORTENABLE_SHIFT) | | |
467 | (1ULL << INFINIPATH_R_INTRAVAIL_SHIFT); | |
468 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, | |
469 | dd->ipath_rcvctrl); | |
470 | ||
471 | /* | |
472 | * now ready for use. this should be cleared whenever we | |
473 | * detect a reset, or initiate one. | |
474 | */ | |
475 | dd->ipath_flags |= IPATH_INITTED; | |
476 | ||
477 | /* | |
478 | * init our shadow copies of head from tail values, and write | |
479 | * head values to match. | |
480 | */ | |
481 | val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0); | |
482 | (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0); | |
483 | dd->ipath_port0head = ipath_read_ureg32(dd, ur_rcvhdrtail, 0); | |
484 | ||
485 | /* Initialize so we interrupt on next packet received */ | |
486 | (void)ipath_write_ureg(dd, ur_rcvhdrhead, | |
487 | dd->ipath_rhdrhead_intr_off | | |
488 | dd->ipath_port0head, 0); | |
489 | ||
490 | /* | |
491 | * by now pioavail updates to memory should have occurred, so | |
492 | * copy them into our working/shadow registers; this is in | |
493 | * case something went wrong with abort, but mostly to get the | |
494 | * initial values of the generation bit correct. | |
495 | */ | |
496 | for (i = 0; i < dd->ipath_pioavregs; i++) { | |
497 | __le64 val; | |
498 | ||
499 | /* | |
500 | * Chip Errata bug 6641; even and odd qwords>3 are swapped. | |
501 | */ | |
502 | if (i > 3) { | |
503 | if (i & 1) | |
504 | val = dd->ipath_pioavailregs_dma[i - 1]; | |
505 | else | |
506 | val = dd->ipath_pioavailregs_dma[i + 1]; | |
507 | } | |
508 | else | |
509 | val = dd->ipath_pioavailregs_dma[i]; | |
510 | dd->ipath_pioavailshadow[i] = le64_to_cpu(val); | |
511 | } | |
512 | /* can get counters, stats, etc. */ | |
513 | dd->ipath_flags |= IPATH_PRESENT; | |
514 | } | |
515 | ||
516 | static int init_housekeeping(struct ipath_devdata *dd, | |
517 | struct ipath_portdata **pdp, int reinit) | |
518 | { | |
519 | char boardn[32]; | |
520 | int ret = 0; | |
521 | ||
522 | /* | |
523 | * have to clear shadow copies of registers at init that are | |
524 | * not otherwise set here, or all kinds of bizarre things | |
525 | * happen with driver on chip reset | |
526 | */ | |
527 | dd->ipath_rcvhdrsize = 0; | |
528 | ||
529 | /* | |
530 | * Don't clear ipath_flags as 8bit mode was set before | |
531 | * entering this func. However, we do set the linkstate to | |
532 | * unknown, so we can watch for a transition. | |
52e7fad8 BS |
533 | * PRESENT is set because we want register reads to work, |
534 | * and the kernel infrastructure saw it in config space; | |
535 | * We clear it if we have failures. | |
097709fe | 536 | */ |
52e7fad8 | 537 | dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT; |
097709fe BS |
538 | dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED | |
539 | IPATH_LINKDOWN | IPATH_LINKINIT); | |
540 | ||
541 | ipath_cdbg(VERBOSE, "Try to read spc chip revision\n"); | |
542 | dd->ipath_revision = | |
543 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision); | |
544 | ||
545 | /* | |
546 | * set up fundamental info we need to use the chip; we assume | |
547 | * if the revision reg and these regs are OK, we don't need to | |
548 | * special case the rest | |
549 | */ | |
550 | dd->ipath_sregbase = | |
551 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase); | |
552 | dd->ipath_cregbase = | |
553 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase); | |
554 | dd->ipath_uregbase = | |
555 | ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase); | |
556 | ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, " | |
557 | "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase, | |
558 | dd->ipath_uregbase, dd->ipath_cregbase); | |
559 | if ((dd->ipath_revision & 0xffffffff) == 0xffffffff | |
560 | || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff | |
561 | || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff | |
562 | || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) { | |
563 | ipath_dev_err(dd, "Register read failures from chip, " | |
564 | "giving up initialization\n"); | |
52e7fad8 | 565 | dd->ipath_flags &= ~IPATH_PRESENT; |
097709fe BS |
566 | ret = -ENODEV; |
567 | goto done; | |
568 | } | |
569 | ||
570 | /* clear the initial reset flag, in case first driver load */ | |
571 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, | |
572 | INFINIPATH_E_RESET); | |
573 | ||
574 | if (reinit) | |
575 | ret = init_chip_reset(dd, pdp); | |
576 | else | |
577 | ret = init_chip_first(dd, pdp); | |
578 | ||
579 | if (ret) | |
580 | goto done; | |
581 | ||
582 | ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, " | |
583 | "%u egrtids\n", (unsigned long long) dd->ipath_revision, | |
584 | dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt, | |
585 | dd->ipath_rcvegrcnt); | |
586 | ||
587 | if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) & | |
588 | INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) { | |
589 | ipath_dev_err(dd, "Driver only handles version %d, " | |
590 | "chip swversion is %d (%llx), failng\n", | |
591 | IPATH_CHIP_SWVERSION, | |
592 | (int)(dd->ipath_revision >> | |
593 | INFINIPATH_R_SOFTWARE_SHIFT) & | |
594 | INFINIPATH_R_SOFTWARE_MASK, | |
595 | (unsigned long long) dd->ipath_revision); | |
596 | ret = -ENOSYS; | |
597 | goto done; | |
598 | } | |
599 | dd->ipath_majrev = (u8) ((dd->ipath_revision >> | |
600 | INFINIPATH_R_CHIPREVMAJOR_SHIFT) & | |
601 | INFINIPATH_R_CHIPREVMAJOR_MASK); | |
602 | dd->ipath_minrev = (u8) ((dd->ipath_revision >> | |
603 | INFINIPATH_R_CHIPREVMINOR_SHIFT) & | |
604 | INFINIPATH_R_CHIPREVMINOR_MASK); | |
605 | dd->ipath_boardrev = (u8) ((dd->ipath_revision >> | |
606 | INFINIPATH_R_BOARDID_SHIFT) & | |
607 | INFINIPATH_R_BOARDID_MASK); | |
608 | ||
609 | ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn); | |
610 | ||
611 | snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion), | |
612 | "Driver %u.%u, %s, InfiniPath%u %u.%u, PCI %u, " | |
613 | "SW Compat %u\n", | |
614 | IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn, | |
615 | (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) & | |
616 | INFINIPATH_R_ARCH_MASK, | |
617 | dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev, | |
618 | (unsigned)(dd->ipath_revision >> | |
619 | INFINIPATH_R_SOFTWARE_SHIFT) & | |
620 | INFINIPATH_R_SOFTWARE_MASK); | |
621 | ||
622 | ipath_dbg("%s", dd->ipath_boardversion); | |
623 | ||
624 | done: | |
625 | return ret; | |
626 | } | |
627 | ||
628 | ||
629 | /** | |
630 | * ipath_init_chip - do the actual initialization sequence on the chip | |
631 | * @dd: the infinipath device | |
632 | * @reinit: reinitializing, so don't allocate new memory | |
633 | * | |
634 | * Do the actual initialization sequence on the chip. This is done | |
635 | * both from the init routine called from the PCI infrastructure, and | |
636 | * when we reset the chip, or detect that it was reset internally, | |
637 | * or it's administratively re-enabled. | |
638 | * | |
639 | * Memory allocation here and in called routines is only done in | |
640 | * the first case (reinit == 0). We have to be careful, because even | |
641 | * without memory allocation, we need to re-write all the chip registers | |
642 | * TIDs, etc. after the reset or enable has completed. | |
643 | */ | |
644 | int ipath_init_chip(struct ipath_devdata *dd, int reinit) | |
645 | { | |
646 | int ret = 0, i; | |
647 | u32 val32, kpiobufs; | |
f37bda92 | 648 | u64 val; |
097709fe BS |
649 | struct ipath_portdata *pd = NULL; /* keep gcc4 happy */ |
650 | ||
651 | ret = init_housekeeping(dd, &pd, reinit); | |
652 | if (ret) | |
653 | goto done; | |
654 | ||
655 | /* | |
656 | * we ignore most issues after reporting them, but have to specially | |
657 | * handle hardware-disabled chips. | |
658 | */ | |
659 | if (ret == 2) { | |
660 | /* unique error, known to ipath_init_one */ | |
661 | ret = -EPERM; | |
662 | goto done; | |
663 | } | |
664 | ||
665 | /* | |
666 | * We could bump this to allow for full rcvegrcnt + rcvtidcnt, | |
667 | * but then it no longer nicely fits power of two, and since | |
668 | * we now use routines that backend onto __get_free_pages, the | |
669 | * rest would be wasted. | |
670 | */ | |
671 | dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt; | |
672 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt, | |
673 | dd->ipath_rcvhdrcnt); | |
674 | ||
675 | /* | |
676 | * Set up the shadow copies of the piobufavail registers, | |
677 | * which we compare against the chip registers for now, and | |
678 | * the in memory DMA'ed copies of the registers. This has to | |
679 | * be done early, before we calculate lastport, etc. | |
680 | */ | |
681 | val = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; | |
682 | /* | |
683 | * calc number of pioavail registers, and save it; we have 2 | |
684 | * bits per buffer. | |
685 | */ | |
686 | dd->ipath_pioavregs = ALIGN(val, sizeof(u64) * BITS_PER_BYTE / 2) | |
687 | / (sizeof(u64) * BITS_PER_BYTE / 2); | |
52e7fad8 BS |
688 | if (ipath_kpiobufs == 0) { |
689 | /* not set by user, or set explictly to default */ | |
690 | if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) > 128) | |
691 | kpiobufs = 32; | |
692 | else | |
693 | kpiobufs = 16; | |
694 | } | |
695 | else | |
097709fe BS |
696 | kpiobufs = ipath_kpiobufs; |
697 | ||
698 | if (kpiobufs > | |
699 | (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - | |
700 | (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT))) { | |
701 | i = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - | |
702 | (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT); | |
703 | if (i < 0) | |
704 | i = 0; | |
705 | dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs for " | |
706 | "kernel leaves too few for %d user ports " | |
707 | "(%d each); using %u\n", kpiobufs, | |
708 | dd->ipath_cfgports - 1, | |
709 | IPATH_MIN_USER_PORT_BUFCNT, i); | |
710 | /* | |
711 | * shouldn't change ipath_kpiobufs, because could be | |
712 | * different for different devices... | |
713 | */ | |
714 | kpiobufs = i; | |
715 | } | |
716 | dd->ipath_lastport_piobuf = | |
717 | dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - kpiobufs; | |
718 | dd->ipath_pbufsport = dd->ipath_cfgports > 1 | |
719 | ? dd->ipath_lastport_piobuf / (dd->ipath_cfgports - 1) | |
720 | : 0; | |
721 | val32 = dd->ipath_lastport_piobuf - | |
722 | (dd->ipath_pbufsport * (dd->ipath_cfgports - 1)); | |
723 | if (val32 > 0) { | |
724 | ipath_dbg("allocating %u pbufs/port leaves %u unused, " | |
725 | "add to kernel\n", dd->ipath_pbufsport, val32); | |
726 | dd->ipath_lastport_piobuf -= val32; | |
727 | ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n", | |
728 | dd->ipath_pbufsport, val32); | |
729 | } | |
730 | dd->ipath_lastpioindex = dd->ipath_lastport_piobuf; | |
731 | ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u " | |
732 | "each for %u user ports\n", kpiobufs, | |
733 | dd->ipath_piobcnt2k + dd->ipath_piobcnt4k, | |
734 | dd->ipath_pbufsport, dd->ipath_cfgports - 1); | |
735 | ||
736 | dd->ipath_f_early_init(dd); | |
737 | ||
738 | /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be | |
739 | * done after early_init */ | |
740 | dd->ipath_hdrqlast = | |
741 | dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1); | |
742 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize, | |
743 | dd->ipath_rcvhdrentsize); | |
744 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize, | |
745 | dd->ipath_rcvhdrsize); | |
746 | ||
747 | if (!reinit) { | |
748 | ret = init_pioavailregs(dd); | |
749 | init_shadow_tids(dd); | |
750 | if (ret) | |
751 | goto done; | |
752 | } | |
753 | ||
754 | (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr, | |
755 | dd->ipath_pioavailregs_phys); | |
756 | /* | |
757 | * this is to detect s/w errors, which the h/w works around by | |
758 | * ignoring the low 6 bits of address, if it wasn't aligned. | |
759 | */ | |
760 | val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr); | |
761 | if (val != dd->ipath_pioavailregs_phys) { | |
762 | ipath_dev_err(dd, "Catastrophic software error, " | |
763 | "SendPIOAvailAddr written as %lx, " | |
764 | "read back as %llx\n", | |
765 | (unsigned long) dd->ipath_pioavailregs_phys, | |
766 | (unsigned long long) val); | |
767 | ret = -EINVAL; | |
768 | goto done; | |
769 | } | |
770 | ||
097709fe BS |
771 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP); |
772 | ||
773 | /* | |
774 | * make sure we are not in freeze, and PIO send enabled, so | |
775 | * writes to pbc happen | |
776 | */ | |
777 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL); | |
778 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
779 | ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); | |
780 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL); | |
781 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, | |
782 | INFINIPATH_S_PIOENABLE); | |
783 | ||
784 | /* | |
785 | * before error clears, since we expect serdes pll errors during | |
786 | * this, the first time after reset | |
787 | */ | |
788 | if (bringup_link(dd)) { | |
789 | dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n"); | |
790 | ret = -ENETDOWN; | |
791 | goto done; | |
792 | } | |
793 | ||
794 | /* | |
795 | * clear any "expected" hwerrs from reset and/or initialization | |
796 | * clear any that aren't enabled (at least this once), and then | |
797 | * set the enable mask | |
798 | */ | |
799 | dd->ipath_f_init_hwerrors(dd); | |
800 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, | |
801 | ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED); | |
802 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, | |
803 | dd->ipath_hwerrmask); | |
804 | ||
805 | dd->ipath_maskederrs = dd->ipath_ignorederrs; | |
806 | /* clear all */ | |
807 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL); | |
808 | /* enable errors that are masked, at least this first time. */ | |
809 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, | |
810 | ~dd->ipath_maskederrs); | |
811 | /* clear any interrups up to this point (ints still not enabled) */ | |
812 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL); | |
813 | ||
814 | ipath_stats.sps_lid[dd->ipath_unit] = dd->ipath_lid; | |
815 | ||
816 | /* | |
817 | * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing | |
818 | * re-init, the simplest way to handle this is to free | |
819 | * existing, and re-allocate. | |
820 | */ | |
f37bda92 BS |
821 | if (reinit) { |
822 | struct ipath_portdata *pd = dd->ipath_pd[0]; | |
823 | dd->ipath_pd[0] = NULL; | |
824 | ipath_free_pddata(dd, pd); | |
825 | } | |
097709fe BS |
826 | dd->ipath_f_tidtemplate(dd); |
827 | ret = ipath_create_rcvhdrq(dd, pd); | |
f37bda92 BS |
828 | if (!ret) { |
829 | dd->ipath_hdrqtailptr = | |
830 | (volatile __le64 *)pd->port_rcvhdrtail_kvaddr; | |
097709fe | 831 | ret = create_port0_egr(dd); |
f37bda92 | 832 | } |
097709fe BS |
833 | if (ret) |
834 | ipath_dev_err(dd, "failed to allocate port 0 (kernel) " | |
835 | "rcvhdrq and/or egr bufs\n"); | |
836 | else | |
837 | enable_chip(dd, pd, reinit); | |
838 | ||
839 | /* | |
840 | * cause retrigger of pending interrupts ignored during init, | |
841 | * even if we had errors | |
842 | */ | |
843 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); | |
844 | ||
845 | if(!dd->ipath_stats_timer_active) { | |
846 | /* | |
847 | * first init, or after an admin disable/enable | |
848 | * set up stats retrieval timer, even if we had errors | |
849 | * in last portion of setup | |
850 | */ | |
851 | init_timer(&dd->ipath_stats_timer); | |
852 | dd->ipath_stats_timer.function = ipath_get_faststats; | |
853 | dd->ipath_stats_timer.data = (unsigned long) dd; | |
854 | /* every 5 seconds; */ | |
855 | dd->ipath_stats_timer.expires = jiffies + 5 * HZ; | |
856 | /* takes ~16 seconds to overflow at full IB 4x bandwdith */ | |
857 | add_timer(&dd->ipath_stats_timer); | |
858 | dd->ipath_stats_timer_active = 1; | |
859 | } | |
860 | ||
861 | done: | |
862 | if (!ret) { | |
097709fe BS |
863 | *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT; |
864 | if (!dd->ipath_f_intrsetup(dd)) { | |
865 | /* now we can enable all interrupts from the chip */ | |
866 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, | |
867 | -1LL); | |
868 | /* force re-interrupt of any pending interrupts. */ | |
869 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, | |
870 | 0ULL); | |
871 | /* chip is usable; mark it as initialized */ | |
872 | *dd->ipath_statusp |= IPATH_STATUS_INITTED; | |
873 | } else | |
874 | ipath_dev_err(dd, "No interrupts enabled, couldn't " | |
875 | "setup interrupt address\n"); | |
876 | ||
877 | if (dd->ipath_cfgports > ipath_stats.sps_nports) | |
878 | /* | |
879 | * sps_nports is a global, so, we set it to | |
880 | * the highest number of ports of any of the | |
881 | * chips we find; we never decrement it, at | |
882 | * least for now. Since this might have changed | |
883 | * over disable/enable or prior to reset, always | |
884 | * do the check and potentially adjust. | |
885 | */ | |
886 | ipath_stats.sps_nports = dd->ipath_cfgports; | |
887 | } else | |
888 | ipath_dbg("Failed (%d) to initialize chip\n", ret); | |
889 | ||
890 | /* if ret is non-zero, we probably should do some cleanup | |
891 | here... */ | |
892 | return ret; | |
893 | } | |
894 | ||
895 | static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp) | |
896 | { | |
897 | struct ipath_devdata *dd; | |
898 | unsigned long flags; | |
899 | unsigned short val; | |
900 | int ret; | |
901 | ||
902 | ret = ipath_parse_ushort(str, &val); | |
903 | ||
904 | spin_lock_irqsave(&ipath_devs_lock, flags); | |
905 | ||
906 | if (ret < 0) | |
907 | goto bail; | |
908 | ||
909 | if (val == 0) { | |
910 | ret = -EINVAL; | |
911 | goto bail; | |
912 | } | |
913 | ||
914 | list_for_each_entry(dd, &ipath_dev_list, ipath_list) { | |
915 | if (dd->ipath_kregbase) | |
916 | continue; | |
917 | if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - | |
918 | (dd->ipath_cfgports * | |
919 | IPATH_MIN_USER_PORT_BUFCNT))) | |
920 | { | |
921 | ipath_dev_err( | |
922 | dd, | |
923 | "Allocating %d PIO bufs for kernel leaves " | |
924 | "too few for %d user ports (%d each)\n", | |
925 | val, dd->ipath_cfgports - 1, | |
926 | IPATH_MIN_USER_PORT_BUFCNT); | |
927 | ret = -EINVAL; | |
928 | goto bail; | |
929 | } | |
930 | dd->ipath_lastport_piobuf = | |
931 | dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val; | |
932 | } | |
933 | ||
934 | ret = 0; | |
935 | bail: | |
936 | spin_unlock_irqrestore(&ipath_devs_lock, flags); | |
937 | ||
938 | return ret; | |
939 | } |