[linux-2.6-block.git] / drivers / infiniband / hw / i40iw / i40iw_user.h

/*******************************************************************************
*
* Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses.  You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenFabrics.org BSD license below:
*
*   Redistribution and use in source and binary forms, with or
*   without modification, are permitted provided that the following
*   conditions are met:
*
*    - Redistributions of source code must retain the above
*	copyright notice, this list of conditions and the following
*	disclaimer.
*
*    - Redistributions in binary form must reproduce the above
*	copyright notice, this list of conditions and the following
*	disclaimer in the documentation and/or other materials
*	provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*******************************************************************************/

#ifndef I40IW_USER_H
#define I40IW_USER_H

enum i40iw_device_capabilities_const {
	I40IW_WQE_SIZE =			4,
	I40IW_CQP_WQE_SIZE =			8,
	I40IW_CQE_SIZE =			4,
	I40IW_EXTENDED_CQE_SIZE =		8,
	I40IW_AEQE_SIZE =			2,
	I40IW_CEQE_SIZE =			1,
	I40IW_CQP_CTX_SIZE =			8,
	I40IW_SHADOW_AREA_SIZE =		8,
	I40IW_CEQ_MAX_COUNT =			256,
	I40IW_QUERY_FPM_BUF_SIZE =		128,
	I40IW_COMMIT_FPM_BUF_SIZE =		128,
	I40IW_MIN_IW_QP_ID =			1,
	I40IW_MAX_IW_QP_ID =			262143,
	I40IW_MIN_CEQID =			0,
	I40IW_MAX_CEQID =			256,
	I40IW_MIN_CQID =			0,
	I40IW_MAX_CQID =			131071,
	I40IW_MIN_AEQ_ENTRIES =			1,
	I40IW_MAX_AEQ_ENTRIES =			524287,
	I40IW_MIN_CEQ_ENTRIES =			1,
	I40IW_MAX_CEQ_ENTRIES =			131071,
	I40IW_MIN_CQ_SIZE =			1,
	I40IW_MAX_CQ_SIZE =			1048575,
	I40IW_MAX_AEQ_ALLOCATE_COUNT =		255,
	I40IW_DB_ID_ZERO =			0,
	I40IW_MAX_WQ_FRAGMENT_COUNT =		3,
	I40IW_MAX_SGE_RD =			1,
	I40IW_MAX_OUTBOUND_MESSAGE_SIZE =	2147483647,
	I40IW_MAX_INBOUND_MESSAGE_SIZE =	2147483647,
	I40IW_MAX_PUSH_PAGE_COUNT =		4096,
	I40IW_MAX_PE_ENABLED_VF_COUNT =		32,
	I40IW_MAX_VF_FPM_ID =			47,
	I40IW_MAX_VF_PER_PF =			127,
	I40IW_MAX_SQ_PAYLOAD_SIZE =		2145386496,
	I40IW_MAX_INLINE_DATA_SIZE =		48,
	I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE =	48,
	I40IW_MAX_IRD_SIZE =			32,
	I40IW_QPCTX_ENCD_MAXIRD =		3,
	I40IW_MAX_WQ_ENTRIES =			2048,
	I40IW_MAX_ORD_SIZE =			32,
	I40IW_Q2_BUFFER_SIZE =			(248 + 100),
	I40IW_QP_CTX_SIZE =			248
};

#define i40iw_handle void *
#define i40iw_adapter_handle i40iw_handle
#define i40iw_qp_handle i40iw_handle
#define i40iw_cq_handle i40iw_handle
#define i40iw_srq_handle i40iw_handle
#define i40iw_pd_id i40iw_handle
#define i40iw_stag_handle i40iw_handle
#define i40iw_stag_index u32
#define i40iw_stag u32
#define i40iw_stag_key u8

#define i40iw_tagged_offset u64
#define i40iw_access_privileges u32
#define i40iw_physical_fragment u64
#define i40iw_address_list u64 *

#define I40IW_CREATE_STAG(index, key)       (((index) << 8) + (key))

#define I40IW_STAG_KEY_FROM_STAG(stag)      ((stag) && 0x000000FF)

#define I40IW_STAG_INDEX_FROM_STAG(stag)    (((stag) && 0xFFFFFF00) >> 8)

#define	I40IW_MAX_MR_SIZE	0x10000000000L

struct i40iw_qp_uk;
struct i40iw_cq_uk;
struct i40iw_srq_uk;
struct i40iw_qp_uk_init_info;
struct i40iw_cq_uk_init_info;
struct i40iw_srq_uk_init_info;

struct i40iw_sge {
	i40iw_tagged_offset tag_off;
	u32 len;
	i40iw_stag stag;
};

#define i40iw_sgl struct i40iw_sge *

struct i40iw_ring {
	u32 head;
	u32 tail;
	u32 size;
};

struct i40iw_cqe {
	u64 buf[I40IW_CQE_SIZE];
};

struct i40iw_extended_cqe {
	u64 buf[I40IW_EXTENDED_CQE_SIZE];
};

struct i40iw_wqe {
	u64 buf[I40IW_WQE_SIZE];
};

struct i40iw_qp_uk_ops;

enum i40iw_addressing_type {
	I40IW_ADDR_TYPE_ZERO_BASED = 0,
	I40IW_ADDR_TYPE_VA_BASED = 1,
};

#define I40IW_ACCESS_FLAGS_LOCALREAD		0x01
#define I40IW_ACCESS_FLAGS_LOCALWRITE		0x02
#define I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY	0x04
#define I40IW_ACCESS_FLAGS_REMOTEREAD		0x05
#define I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY	0x08
#define I40IW_ACCESS_FLAGS_REMOTEWRITE		0x0a
#define I40IW_ACCESS_FLAGS_BIND_WINDOW		0x10
#define I40IW_ACCESS_FLAGS_ALL			0x1F

#define I40IW_OP_TYPE_RDMA_WRITE	0
#define I40IW_OP_TYPE_RDMA_READ		1
#define I40IW_OP_TYPE_SEND		3
#define I40IW_OP_TYPE_SEND_INV		4
#define I40IW_OP_TYPE_SEND_SOL		5
#define I40IW_OP_TYPE_SEND_SOL_INV	6
#define I40IW_OP_TYPE_REC		7
#define I40IW_OP_TYPE_BIND_MW		8
#define I40IW_OP_TYPE_FAST_REG_NSMR	9
#define I40IW_OP_TYPE_INV_STAG		10
#define I40IW_OP_TYPE_RDMA_READ_INV_STAG 11
#define I40IW_OP_TYPE_NOP		12

enum i40iw_completion_status {
	I40IW_COMPL_STATUS_SUCCESS = 0,
	I40IW_COMPL_STATUS_FLUSHED,
	I40IW_COMPL_STATUS_INVALID_WQE,
	I40IW_COMPL_STATUS_QP_CATASTROPHIC,
	I40IW_COMPL_STATUS_REMOTE_TERMINATION,
	I40IW_COMPL_STATUS_INVALID_STAG,
	I40IW_COMPL_STATUS_BASE_BOUND_VIOLATION,
	I40IW_COMPL_STATUS_ACCESS_VIOLATION,
	I40IW_COMPL_STATUS_INVALID_PD_ID,
	I40IW_COMPL_STATUS_WRAP_ERROR,
	I40IW_COMPL_STATUS_STAG_INVALID_PDID,
	I40IW_COMPL_STATUS_RDMA_READ_ZERO_ORD,
	I40IW_COMPL_STATUS_QP_NOT_PRIVLEDGED,
	I40IW_COMPL_STATUS_STAG_NOT_INVALID,
	I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_SIZE,
	I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_ENTRY,
	I40IW_COMPL_STATUS_INVALID_FBO,
	I40IW_COMPL_STATUS_INVALID_LENGTH,
	I40IW_COMPL_STATUS_INVALID_ACCESS,
	I40IW_COMPL_STATUS_PHYS_BUFFER_LIST_TOO_LONG,
	I40IW_COMPL_STATUS_INVALID_VIRT_ADDRESS,
	I40IW_COMPL_STATUS_INVALID_REGION,
	I40IW_COMPL_STATUS_INVALID_WINDOW,
	I40IW_COMPL_STATUS_INVALID_TOTAL_LENGTH
};

enum i40iw_completion_notify {
	IW_CQ_COMPL_EVENT = 0,
	IW_CQ_COMPL_SOLICITED = 1
};

struct i40iw_post_send {
	i40iw_sgl sg_list;
	u32 num_sges;
};

struct i40iw_post_inline_send {
	void *data;
	u32 len;
};

struct i40iw_post_send_w_inv {
	i40iw_sgl sg_list;
	u32 num_sges;
	i40iw_stag remote_stag_to_inv;
};

struct i40iw_post_inline_send_w_inv {
	void *data;
	u32 len;
	i40iw_stag remote_stag_to_inv;
};

struct i40iw_rdma_write {
	i40iw_sgl lo_sg_list;
	u32 num_lo_sges;
	struct i40iw_sge rem_addr;
};

struct i40iw_inline_rdma_write {
	void *data;
	u32 len;
	struct i40iw_sge rem_addr;
};

struct i40iw_rdma_read {
	struct i40iw_sge lo_addr;
	struct i40iw_sge rem_addr;
};

struct i40iw_bind_window {
	i40iw_stag mr_stag;
	u64 bind_length;
	void *va;
	enum i40iw_addressing_type addressing_type;
	bool enable_reads;
	bool enable_writes;
	i40iw_stag mw_stag;
};

struct i40iw_inv_local_stag {
	i40iw_stag target_stag;
};

struct i40iw_post_sq_info {
	u64 wr_id;
	u8 op_type;
	bool signaled;
	bool read_fence;
	bool local_fence;
	bool inline_data;
	bool defer_flag;
	union {
		struct i40iw_post_send send;
		struct i40iw_post_send send_w_sol;
		struct i40iw_post_send_w_inv send_w_inv;
		struct i40iw_post_send_w_inv send_w_sol_inv;
		struct i40iw_rdma_write rdma_write;
		struct i40iw_rdma_read rdma_read;
		struct i40iw_rdma_read rdma_read_inv;
		struct i40iw_bind_window bind_window;
		struct i40iw_inv_local_stag inv_local_stag;
		struct i40iw_inline_rdma_write inline_rdma_write;
		struct i40iw_post_inline_send inline_send;
		struct i40iw_post_inline_send inline_send_w_sol;
		struct i40iw_post_inline_send_w_inv inline_send_w_inv;
		struct i40iw_post_inline_send_w_inv inline_send_w_sol_inv;
	} op;
};

struct i40iw_post_rq_info {
	u64 wr_id;
	i40iw_sgl sg_list;
	u32 num_sges;
};

struct i40iw_cq_poll_info {
	u64 wr_id;
	i40iw_qp_handle qp_handle;
	u32 bytes_xfered;
	u32 tcp_seq_num;
	u32 qp_id;
	i40iw_stag inv_stag;
	enum i40iw_completion_status comp_status;
	u16 major_err;
	u16 minor_err;
	u8 op_type;
	bool stag_invalid_set;
	bool push_dropped;
	bool error;
	bool is_srq;
	bool solicited_event;
};

struct i40iw_qp_uk_ops {
	void (*iw_qp_post_wr)(struct i40iw_qp_uk *);
	void (*iw_qp_ring_push_db)(struct i40iw_qp_uk *, u32);
	enum i40iw_status_code (*iw_rdma_write)(struct i40iw_qp_uk *,
						struct i40iw_post_sq_info *, bool);
	enum i40iw_status_code (*iw_rdma_read)(struct i40iw_qp_uk *,
					       struct i40iw_post_sq_info *, bool, bool);
	enum i40iw_status_code (*iw_send)(struct i40iw_qp_uk *,
					  struct i40iw_post_sq_info *, u32, bool);
	enum i40iw_status_code (*iw_inline_rdma_write)(struct i40iw_qp_uk *,
						       struct i40iw_post_sq_info *, bool);
	enum i40iw_status_code (*iw_inline_send)(struct i40iw_qp_uk *,
						 struct i40iw_post_sq_info *, u32, bool);
	enum i40iw_status_code (*iw_stag_local_invalidate)(struct i40iw_qp_uk *,
							   struct i40iw_post_sq_info *, bool);
	enum i40iw_status_code (*iw_mw_bind)(struct i40iw_qp_uk *,
					     struct i40iw_post_sq_info *, bool);
	enum i40iw_status_code (*iw_post_receive)(struct i40iw_qp_uk *,
						  struct i40iw_post_rq_info *);
	enum i40iw_status_code (*iw_post_nop)(struct i40iw_qp_uk *, u64, bool, bool);
};

struct i40iw_cq_ops {
	void (*iw_cq_request_notification)(struct i40iw_cq_uk *,
					   enum i40iw_completion_notify);
	enum i40iw_status_code (*iw_cq_poll_completion)(struct i40iw_cq_uk *,
							struct i40iw_cq_poll_info *);
	enum i40iw_status_code (*iw_cq_post_entries)(struct i40iw_cq_uk *, u8 count);
	void (*iw_cq_clean)(void *, struct i40iw_cq_uk *);
};

struct i40iw_dev_uk;

struct i40iw_device_uk_ops {
	enum i40iw_status_code (*iwarp_cq_uk_init)(struct i40iw_cq_uk *,
						   struct i40iw_cq_uk_init_info *);
	enum i40iw_status_code (*iwarp_qp_uk_init)(struct i40iw_qp_uk *,
						   struct i40iw_qp_uk_init_info *);
};

struct i40iw_dev_uk {
	struct i40iw_device_uk_ops ops_uk;
};

struct i40iw_sq_uk_wr_trk_info {
	u64 wrid;
	u32 wr_len;
	u8 wqe_size;
	u8 reserved[3];
};

struct i40iw_qp_quanta {
	u64 elem[I40IW_WQE_SIZE];
};

struct i40iw_qp_uk {
	struct i40iw_qp_quanta *sq_base;
	struct i40iw_qp_quanta *rq_base;
	u32 __iomem *wqe_alloc_reg;
	struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
	u64 *rq_wrid_array;
	u64 *shadow_area;
	u32 *push_db;
	u64 *push_wqe;
	struct i40iw_ring sq_ring;
	struct i40iw_ring rq_ring;
	struct i40iw_ring initial_ring;
	u32 qp_id;
	u32 sq_size;
	u32 rq_size;
	u32 max_sq_frag_cnt;
	u32 max_rq_frag_cnt;
	struct i40iw_qp_uk_ops ops;
	bool use_srq;
	u8 swqe_polarity;
	u8 swqe_polarity_deferred;
	u8 rwqe_polarity;
	u8 rq_wqe_size;
	u8 rq_wqe_size_multiplier;
	bool deferred_flag;
};

struct i40iw_cq_uk {
	struct i40iw_cqe *cq_base;
	u32 __iomem *cqe_alloc_reg;
	u64 *shadow_area;
	u32 cq_id;
	u32 cq_size;
	struct i40iw_ring cq_ring;
	u8 polarity;
	bool avoid_mem_cflct;

	struct i40iw_cq_ops ops;
};

struct i40iw_qp_uk_init_info {
	struct i40iw_qp_quanta *sq;
	struct i40iw_qp_quanta *rq;
	u32 __iomem *wqe_alloc_reg;
	u64 *shadow_area;
	struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
	u64 *rq_wrid_array;
	u32 *push_db;
	u64 *push_wqe;
	u32 qp_id;
	u32 sq_size;
	u32 rq_size;
	u32 max_sq_frag_cnt;
	u32 max_rq_frag_cnt;
	u32 max_inline_data;

};

struct i40iw_cq_uk_init_info {
	u32 __iomem *cqe_alloc_reg;
	struct i40iw_cqe *cq_base;
	u64 *shadow_area;
	u32 cq_size;
	u32 cq_id;
	bool avoid_mem_cflct;
};

void i40iw_device_init_uk(struct i40iw_dev_uk *dev);

void i40iw_qp_post_wr(struct i40iw_qp_uk *qp);
u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx,
				u8 wqe_size,
				u32 total_size,
				u64 wr_id
				);
u64 *i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx);
u64 *i40iw_qp_get_next_srq_wqe(struct i40iw_srq_uk *srq, u32 *wqe_idx);

enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq,
					struct i40iw_cq_uk_init_info *info);
enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
					struct i40iw_qp_uk_init_info *info);

void i40iw_clean_cq(void *queue, struct i40iw_cq_uk *cq);
enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp, u64 wr_id,
				 bool signaled, bool post_sq);
enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size);
enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size);
enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
							 u8 *wqe_size);
enum i40iw_status_code i40iw_get_wqe_shift(u32 wqdepth, u32 sge, u32 inline_data, u8 *shift);
#endif
Commit	Line	Data
280cfc4b FL	1	/*******************************************************************************
	2	*
	3	* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenFabrics.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*
	33	*******************************************************************************/
	34
	35	#ifndef I40IW_USER_H
	36	#define I40IW_USER_H
	37
	38	enum i40iw_device_capabilities_const {
	39	I40IW_WQE_SIZE = 4,
	40	I40IW_CQP_WQE_SIZE = 8,
	41	I40IW_CQE_SIZE = 4,
	42	I40IW_EXTENDED_CQE_SIZE = 8,
	43	I40IW_AEQE_SIZE = 2,
	44	I40IW_CEQE_SIZE = 1,
	45	I40IW_CQP_CTX_SIZE = 8,
	46	I40IW_SHADOW_AREA_SIZE = 8,
	47	I40IW_CEQ_MAX_COUNT = 256,
	48	I40IW_QUERY_FPM_BUF_SIZE = 128,
	49	I40IW_COMMIT_FPM_BUF_SIZE = 128,
	50	I40IW_MIN_IW_QP_ID = 1,
	51	I40IW_MAX_IW_QP_ID = 262143,
	52	I40IW_MIN_CEQID = 0,
	53	I40IW_MAX_CEQID = 256,
	54	I40IW_MIN_CQID = 0,
	55	I40IW_MAX_CQID = 131071,
	56	I40IW_MIN_AEQ_ENTRIES = 1,
	57	I40IW_MAX_AEQ_ENTRIES = 524287,
	58	I40IW_MIN_CEQ_ENTRIES = 1,
	59	I40IW_MAX_CEQ_ENTRIES = 131071,
	60	I40IW_MIN_CQ_SIZE = 1,
	61	I40IW_MAX_CQ_SIZE = 1048575,
	62	I40IW_MAX_AEQ_ALLOCATE_COUNT = 255,
	63	I40IW_DB_ID_ZERO = 0,
23ef48ad	64	I40IW_MAX_WQ_FRAGMENT_COUNT = 3,
280cfc4b FL	65	I40IW_MAX_SGE_RD = 1,
	66	I40IW_MAX_OUTBOUND_MESSAGE_SIZE = 2147483647,
	67	I40IW_MAX_INBOUND_MESSAGE_SIZE = 2147483647,
	68	I40IW_MAX_PUSH_PAGE_COUNT = 4096,
	69	I40IW_MAX_PE_ENABLED_VF_COUNT = 32,
	70	I40IW_MAX_VF_FPM_ID = 47,
	71	I40IW_MAX_VF_PER_PF = 127,
	72	I40IW_MAX_SQ_PAYLOAD_SIZE = 2145386496,
23ef48ad IM	73	I40IW_MAX_INLINE_DATA_SIZE = 48,
23ef48ad IM	74	I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE = 48,
280cfc4b FL	75	I40IW_MAX_IRD_SIZE = 32,
	76	I40IW_QPCTX_ENCD_MAXIRD = 3,
	77	I40IW_MAX_WQ_ENTRIES = 2048,
	78	I40IW_MAX_ORD_SIZE = 32,
	79	I40IW_Q2_BUFFER_SIZE = (248 + 100),
	80	I40IW_QP_CTX_SIZE = 248
	81	};
	82
	83	#define i40iw_handle void *
	84	#define i40iw_adapter_handle i40iw_handle
	85	#define i40iw_qp_handle i40iw_handle
	86	#define i40iw_cq_handle i40iw_handle
	87	#define i40iw_srq_handle i40iw_handle
	88	#define i40iw_pd_id i40iw_handle
	89	#define i40iw_stag_handle i40iw_handle
	90	#define i40iw_stag_index u32
	91	#define i40iw_stag u32
	92	#define i40iw_stag_key u8
	93
	94	#define i40iw_tagged_offset u64
	95	#define i40iw_access_privileges u32
	96	#define i40iw_physical_fragment u64
	97	#define i40iw_address_list u64 *
	98
	99	#define I40IW_CREATE_STAG(index, key) (((index) << 8) + (key))
	100
	101	#define I40IW_STAG_KEY_FROM_STAG(stag) ((stag) && 0x000000FF)
	102
	103	#define I40IW_STAG_INDEX_FROM_STAG(stag) (((stag) && 0xFFFFFF00) >> 8)
	104
6b900365 IM	105	#define I40IW_MAX_MR_SIZE 0x10000000000L
6b900365 IM	106
280cfc4b FL	107	struct i40iw_qp_uk;
	108	struct i40iw_cq_uk;
	109	struct i40iw_srq_uk;
	110	struct i40iw_qp_uk_init_info;
	111	struct i40iw_cq_uk_init_info;
	112	struct i40iw_srq_uk_init_info;
	113
	114	struct i40iw_sge {
	115	i40iw_tagged_offset tag_off;
	116	u32 len;
	117	i40iw_stag stag;
	118	};
	119
	120	#define i40iw_sgl struct i40iw_sge *
	121
	122	struct i40iw_ring {
	123	u32 head;
	124	u32 tail;
	125	u32 size;
	126	};
	127
	128	struct i40iw_cqe {
	129	u64 buf[I40IW_CQE_SIZE];
	130	};
	131
	132	struct i40iw_extended_cqe {
	133	u64 buf[I40IW_EXTENDED_CQE_SIZE];
	134	};
	135
	136	struct i40iw_wqe {
	137	u64 buf[I40IW_WQE_SIZE];
	138	};
	139
	140	struct i40iw_qp_uk_ops;
	141
	142	enum i40iw_addressing_type {
	143	I40IW_ADDR_TYPE_ZERO_BASED = 0,
	144	I40IW_ADDR_TYPE_VA_BASED = 1,
	145	};
	146
	147	#define I40IW_ACCESS_FLAGS_LOCALREAD 0x01
	148	#define I40IW_ACCESS_FLAGS_LOCALWRITE 0x02
	149	#define I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04
	150	#define I40IW_ACCESS_FLAGS_REMOTEREAD 0x05
	151	#define I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08
	152	#define I40IW_ACCESS_FLAGS_REMOTEWRITE 0x0a
	153	#define I40IW_ACCESS_FLAGS_BIND_WINDOW 0x10
	154	#define I40IW_ACCESS_FLAGS_ALL 0x1F
	155
	156	#define I40IW_OP_TYPE_RDMA_WRITE 0
	157	#define I40IW_OP_TYPE_RDMA_READ 1
	158	#define I40IW_OP_TYPE_SEND 3
	159	#define I40IW_OP_TYPE_SEND_INV 4
	160	#define I40IW_OP_TYPE_SEND_SOL 5
	161	#define I40IW_OP_TYPE_SEND_SOL_INV 6
	162	#define I40IW_OP_TYPE_REC 7
	163	#define I40IW_OP_TYPE_BIND_MW 8
	164	#define I40IW_OP_TYPE_FAST_REG_NSMR 9
	165	#define I40IW_OP_TYPE_INV_STAG 10
	166	#define I40IW_OP_TYPE_RDMA_READ_INV_STAG 11
	167	#define I40IW_OP_TYPE_NOP 12
	168
	169	enum i40iw_completion_status {
	170	I40IW_COMPL_STATUS_SUCCESS = 0,
171	I40IW_COMPL_STATUS_FLUSHED,
172	I40IW_COMPL_STATUS_INVALID_WQE,
173	I40IW_COMPL_STATUS_QP_CATASTROPHIC,
174	I40IW_COMPL_STATUS_REMOTE_TERMINATION,
175	I40IW_COMPL_STATUS_INVALID_STAG,
176	I40IW_COMPL_STATUS_BASE_BOUND_VIOLATION,
177	I40IW_COMPL_STATUS_ACCESS_VIOLATION,
178	I40IW_COMPL_STATUS_INVALID_PD_ID,
179	I40IW_COMPL_STATUS_WRAP_ERROR,
180	I40IW_COMPL_STATUS_STAG_INVALID_PDID,
181	I40IW_COMPL_STATUS_RDMA_READ_ZERO_ORD,
182	I40IW_COMPL_STATUS_QP_NOT_PRIVLEDGED,
183	I40IW_COMPL_STATUS_STAG_NOT_INVALID,
184	I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_SIZE,
185	I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_ENTRY,
186	I40IW_COMPL_STATUS_INVALID_FBO,
187	I40IW_COMPL_STATUS_INVALID_LENGTH,
188	I40IW_COMPL_STATUS_INVALID_ACCESS,
189	I40IW_COMPL_STATUS_PHYS_BUFFER_LIST_TOO_LONG,
190	I40IW_COMPL_STATUS_INVALID_VIRT_ADDRESS,
191	I40IW_COMPL_STATUS_INVALID_REGION,
192	I40IW_COMPL_STATUS_INVALID_WINDOW,
193	I40IW_COMPL_STATUS_INVALID_TOTAL_LENGTH
194	};
195
196	enum i40iw_completion_notify {
197	IW_CQ_COMPL_EVENT = 0,
198	IW_CQ_COMPL_SOLICITED = 1
199	};
200
201	struct i40iw_post_send {
202	i40iw_sgl sg_list;
23ef48ad	203	u32 num_sges;
280cfc4b FL	204	};
	205
	206	struct i40iw_post_inline_send {
	207	void *data;
	208	u32 len;
	209	};
	210
	211	struct i40iw_post_send_w_inv {
	212	i40iw_sgl sg_list;
	213	u32 num_sges;
	214	i40iw_stag remote_stag_to_inv;
	215	};
	216
	217	struct i40iw_post_inline_send_w_inv {
	218	void *data;
	219	u32 len;
	220	i40iw_stag remote_stag_to_inv;
	221	};
	222
	223	struct i40iw_rdma_write {
	224	i40iw_sgl lo_sg_list;
23ef48ad	225	u32 num_lo_sges;
280cfc4b FL	226	struct i40iw_sge rem_addr;
	227	};
	228
	229	struct i40iw_inline_rdma_write {
	230	void *data;
	231	u32 len;
	232	struct i40iw_sge rem_addr;
	233	};
	234
	235	struct i40iw_rdma_read {
	236	struct i40iw_sge lo_addr;
	237	struct i40iw_sge rem_addr;
	238	};
	239
	240	struct i40iw_bind_window {
	241	i40iw_stag mr_stag;
	242	u64 bind_length;
	243	void *va;
	244	enum i40iw_addressing_type addressing_type;
	245	bool enable_reads;
	246	bool enable_writes;
	247	i40iw_stag mw_stag;
	248	};
	249
	250	struct i40iw_inv_local_stag {
	251	i40iw_stag target_stag;
	252	};
	253
	254	struct i40iw_post_sq_info {
	255	u64 wr_id;
	256	u8 op_type;
	257	bool signaled;
	258	bool read_fence;
	259	bool local_fence;
	260	bool inline_data;
	261	bool defer_flag;
	262	union {
	263	struct i40iw_post_send send;
	264	struct i40iw_post_send send_w_sol;
	265	struct i40iw_post_send_w_inv send_w_inv;
	266	struct i40iw_post_send_w_inv send_w_sol_inv;
	267	struct i40iw_rdma_write rdma_write;
	268	struct i40iw_rdma_read rdma_read;
	269	struct i40iw_rdma_read rdma_read_inv;
	270	struct i40iw_bind_window bind_window;
	271	struct i40iw_inv_local_stag inv_local_stag;
	272	struct i40iw_inline_rdma_write inline_rdma_write;
	273	struct i40iw_post_inline_send inline_send;
	274	struct i40iw_post_inline_send inline_send_w_sol;
	275	struct i40iw_post_inline_send_w_inv inline_send_w_inv;
	276	struct i40iw_post_inline_send_w_inv inline_send_w_sol_inv;
	277	} op;
	278	};
	279
	280	struct i40iw_post_rq_info {
	281	u64 wr_id;
	282	i40iw_sgl sg_list;
	283	u32 num_sges;
	284	};
	285
	286	struct i40iw_cq_poll_info {
	287	u64 wr_id;
	288	i40iw_qp_handle qp_handle;
	289	u32 bytes_xfered;
290	u32 tcp_seq_num;
291	u32 qp_id;
292	i40iw_stag inv_stag;
293	enum i40iw_completion_status comp_status;
294	u16 major_err;
295	u16 minor_err;
296	u8 op_type;
297	bool stag_invalid_set;
298	bool push_dropped;
299	bool error;
300	bool is_srq;
301	bool solicited_event;
302	};
303
304	struct i40iw_qp_uk_ops {
305	void (iw_qp_post_wr)(struct i40iw_qp_uk );
306	void (iw_qp_ring_push_db)(struct i40iw_qp_uk , u32);
307	enum i40iw_status_code (iw_rdma_write)(struct i40iw_qp_uk ,
308	struct i40iw_post_sq_info *, bool);
309	enum i40iw_status_code (iw_rdma_read)(struct i40iw_qp_uk ,
310	struct i40iw_post_sq_info *, bool, bool);
311	enum i40iw_status_code (iw_send)(struct i40iw_qp_uk ,
312	struct i40iw_post_sq_info *, u32, bool);
313	enum i40iw_status_code (iw_inline_rdma_write)(struct i40iw_qp_uk ,
314	struct i40iw_post_sq_info *, bool);
315	enum i40iw_status_code (iw_inline_send)(struct i40iw_qp_uk ,
316	struct i40iw_post_sq_info *, u32, bool);
317	enum i40iw_status_code (iw_stag_local_invalidate)(struct i40iw_qp_uk ,
318	struct i40iw_post_sq_info *, bool);
319	enum i40iw_status_code (iw_mw_bind)(struct i40iw_qp_uk ,
320	struct i40iw_post_sq_info *, bool);
321	enum i40iw_status_code (iw_post_receive)(struct i40iw_qp_uk ,
322	struct i40iw_post_rq_info *);
323	enum i40iw_status_code (iw_post_nop)(struct i40iw_qp_uk , u64, bool, bool);
324	};
325
326	struct i40iw_cq_ops {
327	void (iw_cq_request_notification)(struct i40iw_cq_uk ,
328	enum i40iw_completion_notify);
329	enum i40iw_status_code (iw_cq_poll_completion)(struct i40iw_cq_uk ,
b54143be	330	struct i40iw_cq_poll_info *);
280cfc4b FL	331	enum i40iw_status_code (iw_cq_post_entries)(struct i40iw_cq_uk , u8 count);
	332	void (iw_cq_clean)(void , struct i40iw_cq_uk *);
	333	};
	334
	335	struct i40iw_dev_uk;
	336
	337	struct i40iw_device_uk_ops {
	338	enum i40iw_status_code (iwarp_cq_uk_init)(struct i40iw_cq_uk ,
	339	struct i40iw_cq_uk_init_info *);
	340	enum i40iw_status_code (iwarp_qp_uk_init)(struct i40iw_qp_uk ,
	341	struct i40iw_qp_uk_init_info *);
	342	};
	343
	344	struct i40iw_dev_uk {
	345	struct i40iw_device_uk_ops ops_uk;
	346	};
	347
	348	struct i40iw_sq_uk_wr_trk_info {
	349	u64 wrid;
23ef48ad IM	350	u32 wr_len;
	351	u8 wqe_size;
	352	u8 reserved[3];
280cfc4b FL	353	};
	354
	355	struct i40iw_qp_quanta {
	356	u64 elem[I40IW_WQE_SIZE];
	357	};
	358
	359	struct i40iw_qp_uk {
	360	struct i40iw_qp_quanta *sq_base;
	361	struct i40iw_qp_quanta *rq_base;
	362	u32 __iomem *wqe_alloc_reg;
	363	struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
	364	u64 *rq_wrid_array;
	365	u64 *shadow_area;
	366	u32 *push_db;
	367	u64 *push_wqe;
	368	struct i40iw_ring sq_ring;
	369	struct i40iw_ring rq_ring;
	370	struct i40iw_ring initial_ring;
	371	u32 qp_id;
	372	u32 sq_size;
	373	u32 rq_size;
23ef48ad IM	374	u32 max_sq_frag_cnt;
23ef48ad IM	375	u32 max_rq_frag_cnt;
280cfc4b FL	376	struct i40iw_qp_uk_ops ops;
	377	bool use_srq;
	378	u8 swqe_polarity;
	379	u8 swqe_polarity_deferred;
	380	u8 rwqe_polarity;
	381	u8 rq_wqe_size;
	382	u8 rq_wqe_size_multiplier;
280cfc4b FL	383	bool deferred_flag;
	384	};
	385
	386	struct i40iw_cq_uk {
	387	struct i40iw_cqe *cq_base;
	388	u32 __iomem *cqe_alloc_reg;
	389	u64 *shadow_area;
	390	u32 cq_id;
	391	u32 cq_size;
	392	struct i40iw_ring cq_ring;
	393	u8 polarity;
	394	bool avoid_mem_cflct;
	395
	396	struct i40iw_cq_ops ops;
	397	};
	398
	399	struct i40iw_qp_uk_init_info {
	400	struct i40iw_qp_quanta *sq;
	401	struct i40iw_qp_quanta *rq;
	402	u32 __iomem *wqe_alloc_reg;
	403	u64 *shadow_area;
	404	struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array;
	405	u64 *rq_wrid_array;
	406	u32 *push_db;
	407	u64 *push_wqe;
	408	u32 qp_id;
	409	u32 sq_size;
	410	u32 rq_size;
23ef48ad IM	411	u32 max_sq_frag_cnt;
	412	u32 max_rq_frag_cnt;
	413	u32 max_inline_data;
280cfc4b FL	414
	415	};
	416
	417	struct i40iw_cq_uk_init_info {
	418	u32 __iomem *cqe_alloc_reg;
	419	struct i40iw_cqe *cq_base;
	420	u64 *shadow_area;
	421	u32 cq_size;
	422	u32 cq_id;
	423	bool avoid_mem_cflct;
	424	};
	425
	426	void i40iw_device_init_uk(struct i40iw_dev_uk *dev);
	427
	428	void i40iw_qp_post_wr(struct i40iw_qp_uk *qp);
	429	u64 i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk qp, u32 *wqe_idx,
23ef48ad IM	430	u8 wqe_size,
	431	u32 total_size,
	432	u64 wr_id
	433	);
280cfc4b FL	434	u64 i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk qp, u32 *wqe_idx);
	435	u64 i40iw_qp_get_next_srq_wqe(struct i40iw_srq_uk srq, u32 *wqe_idx);
	436
	437	enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq,
	438	struct i40iw_cq_uk_init_info *info);
	439	enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
	440	struct i40iw_qp_uk_init_info *info);
	441
	442	void i40iw_clean_cq(void queue, struct i40iw_cq_uk cq);
	443	enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp, u64 wr_id,
	444	bool signaled, bool post_sq);
23ef48ad IM	445	enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size);
23ef48ad IM	446	enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size);
280cfc4b FL	447	enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
280cfc4b FL	448	u8 *wqe_size);
23ef48ad	449	enum i40iw_status_code i40iw_get_wqe_shift(u32 wqdepth, u32 sge, u32 inline_data, u8 *shift);
280cfc4b	450	#endif