[linux-2.6-block.git] / drivers / infiniband / hw / i40iw / i40iw_osdep.h

/*******************************************************************************
*
* Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses.  You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenFabrics.org BSD license below:
*
*   Redistribution and use in source and binary forms, with or
*   without modification, are permitted provided that the following
*   conditions are met:
*
*    - Redistributions of source code must retain the above
*	copyright notice, this list of conditions and the following
*	disclaimer.
*
*    - Redistributions in binary form must reproduce the above
*	copyright notice, this list of conditions and the following
*	disclaimer in the documentation and/or other materials
*	provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*******************************************************************************/

#ifndef I40IW_OSDEP_H
#define I40IW_OSDEP_H

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/bitops.h>
#include <net/tcp.h>
#include <crypto/hash.h>
/* get readq/writeq support for 32 bit kernels, use the low-first version */
#include <linux/io-64-nonatomic-lo-hi.h>

#define STATS_TIMER_DELAY 1000

static inline void set_64bit_val(u64 *wqe_words, u32 byte_index, u64 value)
{
	wqe_words[byte_index >> 3] = value;
}

/**
 * set_32bit_val - set 32 value to hw wqe
 * @wqe_words: wqe addr to write
 * @byte_index: index in wqe
 * @value: value to write
 **/
static inline void set_32bit_val(u32 *wqe_words, u32 byte_index, u32 value)
{
	wqe_words[byte_index >> 2] = value;
}

/**
 * get_64bit_val - read 64 bit value from wqe
 * @wqe_words: wqe addr
 * @byte_index: index to read from
 * @value: read value
 **/
static inline void get_64bit_val(u64 *wqe_words, u32 byte_index, u64 *value)
{
	*value = wqe_words[byte_index >> 3];
}

/**
 * get_32bit_val - read 32 bit value from wqe
 * @wqe_words: wqe addr
 * @byte_index: index to reaad from
 * @value: return 32 bit value
 **/
static inline void get_32bit_val(u32 *wqe_words, u32 byte_index, u32 *value)
{
	*value = wqe_words[byte_index >> 2];
}

struct i40iw_dma_mem {
	void *va;
	dma_addr_t pa;
	u32 size;
} __packed;

struct i40iw_virt_mem {
	void *va;
	u32 size;
} __packed;

#define i40iw_debug(h, m, s, ...)                               \
do {                                                            \
	if (((m) & (h)->debug_mask))                            \
		pr_info("i40iw " s, ##__VA_ARGS__);             \
} while (0)

#define i40iw_flush(a)          readl((a)->hw_addr + I40E_GLGEN_STAT)

#define I40E_GLHMC_VFSDCMD(_i)  (0x000C8000 + ((_i) * 4)) \
				/* _i=0...31 */
#define I40E_GLHMC_VFSDCMD_MAX_INDEX    31
#define I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT  0
#define I40E_GLHMC_VFSDCMD_PMSDIDX_MASK  (0xFFF \
					  << I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT)
#define I40E_GLHMC_VFSDCMD_PF_SHIFT       16
#define I40E_GLHMC_VFSDCMD_PF_MASK        (0xF << I40E_GLHMC_VFSDCMD_PF_SHIFT)
#define I40E_GLHMC_VFSDCMD_VF_SHIFT       20
#define I40E_GLHMC_VFSDCMD_VF_MASK        (0x1FF << I40E_GLHMC_VFSDCMD_VF_SHIFT)
#define I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT 29
#define I40E_GLHMC_VFSDCMD_PMF_TYPE_MASK  (0x3 \
					   << I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT)
#define I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT   31
#define I40E_GLHMC_VFSDCMD_PMSDWR_MASK  (0x1 << I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT)

#define I40E_GLHMC_VFSDDATAHIGH(_i)     (0x000C8200 + ((_i) * 4)) \
				/* _i=0...31 */
#define I40E_GLHMC_VFSDDATAHIGH_MAX_INDEX       31
#define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT 0
#define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_MASK  (0xFFFFFFFF \
			<< I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT)

#define I40E_GLHMC_VFSDDATALOW(_i)      (0x000C8100 + ((_i) * 4)) \
				/* _i=0...31 */
#define I40E_GLHMC_VFSDDATALOW_MAX_INDEX        31
#define I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT   0
#define I40E_GLHMC_VFSDDATALOW_PMSDVALID_MASK  (0x1 \
			<< I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT)
#define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT    1
#define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_MASK  (0x1 \
			<< I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT)
#define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT 2
#define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_MASK  (0x3FF \
			<< I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT)
#define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT 12
#define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_MASK  (0xFFFFF \
			<< I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT)

#define I40E_GLPE_FWLDSTATUS                     0x0000D200
#define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT 0
#define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_MASK  (0x1 \
			<< I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT)
#define I40E_GLPE_FWLDSTATUS_DONE_SHIFT           1
#define I40E_GLPE_FWLDSTATUS_DONE_MASK  (0x1 << I40E_GLPE_FWLDSTATUS_DONE_SHIFT)
#define I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT       2
#define I40E_GLPE_FWLDSTATUS_CQP_FAIL_MASK  (0x1 \
			 << I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT)
#define I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT       3
#define I40E_GLPE_FWLDSTATUS_TEP_FAIL_MASK  (0x1 \
			 << I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT)
#define I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT       4
#define I40E_GLPE_FWLDSTATUS_OOP_FAIL_MASK  (0x1 \
			 << I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT)

struct i40iw_sc_dev;
struct i40iw_sc_qp;
struct i40iw_puda_buf;
struct i40iw_puda_completion_info;
struct i40iw_update_sds_info;
struct i40iw_hmc_fcn_info;
struct i40iw_virtchnl_work_info;
struct i40iw_manage_vf_pble_info;
struct i40iw_device;
struct i40iw_hmc_info;
struct i40iw_hw;

u8 __iomem *i40iw_get_hw_addr(void *dev);
void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
enum i40iw_status_code i40iw_vf_wait_vchnl_resp(struct i40iw_sc_dev *dev);
bool i40iw_vf_clear_to_send(struct i40iw_sc_dev *dev);
enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc, void *addr,
					      u32 length, u32 value);
struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *buf);
void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length, u32 seqnum);
void i40iw_free_hash_desc(struct shash_desc *);
enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **);
enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
						 struct i40iw_puda_buf *buf);
enum i40iw_status_code i40iw_cqp_sds_cmd(struct i40iw_sc_dev *dev,
					 struct i40iw_update_sds_info *info);
enum i40iw_status_code i40iw_cqp_manage_hmc_fcn_cmd(struct i40iw_sc_dev *dev,
						    struct i40iw_hmc_fcn_info *hmcfcninfo);
enum i40iw_status_code i40iw_cqp_query_fpm_values_cmd(struct i40iw_sc_dev *dev,
						      struct i40iw_dma_mem *values_mem,
						      u8 hmc_fn_id);
enum i40iw_status_code i40iw_cqp_commit_fpm_values_cmd(struct i40iw_sc_dev *dev,
						       struct i40iw_dma_mem *values_mem,
						       u8 hmc_fn_id);
enum i40iw_status_code i40iw_alloc_query_fpm_buf(struct i40iw_sc_dev *dev,
						 struct i40iw_dma_mem *mem);
enum i40iw_status_code i40iw_cqp_manage_vf_pble_bp(struct i40iw_sc_dev *dev,
						   struct i40iw_manage_vf_pble_info *info);
void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev,
			    struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);
void *i40iw_remove_head(struct list_head *list);

void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);
void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);
void i40iw_terminate_start_timer(struct i40iw_sc_qp *qp);
void i40iw_terminate_del_timer(struct i40iw_sc_qp *qp);

enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
						  struct i40iw_manage_vf_pble_info *info,
						  bool wait);
struct i40iw_dev_pestat;
void i40iw_hw_stats_start_timer(struct i40iw_sc_dev *);
void i40iw_hw_stats_del_timer(struct i40iw_sc_dev *);
#define i40iw_mmiowb() mmiowb()
void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value);
u32  i40iw_rd32(struct i40iw_hw *hw, u32 reg);
#endif				/* _I40IW_OSDEP_H_ */
Commit	Line	Data
4e9042e6 FL	1	/*******************************************************************************
	2	*
	3	* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenFabrics.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*
	33	*******************************************************************************/
	34
	35	#ifndef I40IW_OSDEP_H
	36	#define I40IW_OSDEP_H
	37
	38	#include <linux/kernel.h>
	39	#include <linux/string.h>
	40	#include <linux/bitops.h>
	41	#include <net/tcp.h>
34abf9ed	42	#include <crypto/hash.h>
4e9042e6 FL	43	/* get readq/writeq support for 32 bit kernels, use the low-first version */
	44	#include <linux/io-64-nonatomic-lo-hi.h>
	45
	46	#define STATS_TIMER_DELAY 1000
	47
	48	static inline void set_64bit_val(u64 *wqe_words, u32 byte_index, u64 value)
	49	{
	50	wqe_words[byte_index >> 3] = value;
	51	}
	52
	53	/**
	54	* set_32bit_val - set 32 value to hw wqe
	55	* @wqe_words: wqe addr to write
	56	* @byte_index: index in wqe
	57	* @value: value to write
	58	**/
	59	static inline void set_32bit_val(u32 *wqe_words, u32 byte_index, u32 value)
	60	{
	61	wqe_words[byte_index >> 2] = value;
	62	}
	63
	64	/**
	65	* get_64bit_val - read 64 bit value from wqe
	66	* @wqe_words: wqe addr
	67	* @byte_index: index to read from
	68	* @value: read value
	69	**/
	70	static inline void get_64bit_val(u64 wqe_words, u32 byte_index, u64 value)
	71	{
	72	*value = wqe_words[byte_index >> 3];
	73	}
	74
	75	/**
	76	* get_32bit_val - read 32 bit value from wqe
	77	* @wqe_words: wqe addr
	78	* @byte_index: index to reaad from
	79	* @value: return 32 bit value
	80	**/
	81	static inline void get_32bit_val(u32 wqe_words, u32 byte_index, u32 value)
	82	{
	83	*value = wqe_words[byte_index >> 2];
	84	}
	85
	86	struct i40iw_dma_mem {
	87	void *va;
	88	dma_addr_t pa;
	89	u32 size;
	90	} __packed;
	91
	92	struct i40iw_virt_mem {
	93	void *va;
	94	u32 size;
	95	} __packed;
	96
	97	#define i40iw_debug(h, m, s, ...) \
	98	do { \
	99	if (((m) & (h)->debug_mask)) \
	100	pr_info("i40iw " s, ##__VA_ARGS__); \
	101	} while (0)
	102
	103	#define i40iw_flush(a) readl((a)->hw_addr + I40E_GLGEN_STAT)
	104
	105	#define I40E_GLHMC_VFSDCMD(_i) (0x000C8000 + ((_i) * 4)) \
	106	/* _i=0...31 */
107	#define I40E_GLHMC_VFSDCMD_MAX_INDEX 31
108	#define I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT 0
109	#define I40E_GLHMC_VFSDCMD_PMSDIDX_MASK (0xFFF \
110	<< I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT)
111	#define I40E_GLHMC_VFSDCMD_PF_SHIFT 16
112	#define I40E_GLHMC_VFSDCMD_PF_MASK (0xF << I40E_GLHMC_VFSDCMD_PF_SHIFT)
113	#define I40E_GLHMC_VFSDCMD_VF_SHIFT 20
114	#define I40E_GLHMC_VFSDCMD_VF_MASK (0x1FF << I40E_GLHMC_VFSDCMD_VF_SHIFT)
115	#define I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT 29
116	#define I40E_GLHMC_VFSDCMD_PMF_TYPE_MASK (0x3 \
117	<< I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT)
118	#define I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT 31
119	#define I40E_GLHMC_VFSDCMD_PMSDWR_MASK (0x1 << I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT)
120
121	#define I40E_GLHMC_VFSDDATAHIGH(_i) (0x000C8200 + ((_i) * 4)) \
122	/* _i=0...31 */
123	#define I40E_GLHMC_VFSDDATAHIGH_MAX_INDEX 31
124	#define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT 0
125	#define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_MASK (0xFFFFFFFF \
126	<< I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT)
127
128	#define I40E_GLHMC_VFSDDATALOW(_i) (0x000C8100 + ((_i) * 4)) \
129	/* _i=0...31 */
130	#define I40E_GLHMC_VFSDDATALOW_MAX_INDEX 31
131	#define I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT 0
132	#define I40E_GLHMC_VFSDDATALOW_PMSDVALID_MASK (0x1 \
133	<< I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT)
134	#define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT 1
135	#define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_MASK (0x1 \
136	<< I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT)
137	#define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT 2
138	#define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_MASK (0x3FF \
139	<< I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT)
140	#define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT 12
141	#define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_MASK (0xFFFFF \
142	<< I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT)
143
144	#define I40E_GLPE_FWLDSTATUS 0x0000D200
145	#define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT 0
146	#define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_MASK (0x1 \
147	<< I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT)
148	#define I40E_GLPE_FWLDSTATUS_DONE_SHIFT 1
149	#define I40E_GLPE_FWLDSTATUS_DONE_MASK (0x1 << I40E_GLPE_FWLDSTATUS_DONE_SHIFT)
150	#define I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT 2
151	#define I40E_GLPE_FWLDSTATUS_CQP_FAIL_MASK (0x1 \
152	<< I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT)
153	#define I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT 3
154	#define I40E_GLPE_FWLDSTATUS_TEP_FAIL_MASK (0x1 \
155	<< I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT)
156	#define I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT 4
157	#define I40E_GLPE_FWLDSTATUS_OOP_FAIL_MASK (0x1 \
158	<< I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT)
159
160	struct i40iw_sc_dev;
161	struct i40iw_sc_qp;
162	struct i40iw_puda_buf;
163	struct i40iw_puda_completion_info;
164	struct i40iw_update_sds_info;
165	struct i40iw_hmc_fcn_info;
166	struct i40iw_virtchnl_work_info;
167	struct i40iw_manage_vf_pble_info;
168	struct i40iw_device;
169	struct i40iw_hmc_info;
170	struct i40iw_hw;
171
172	u8 __iomem i40iw_get_hw_addr(void dev);
173	void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev dev, struct i40iw_sc_qp qp);
174	enum i40iw_status_code i40iw_vf_wait_vchnl_resp(struct i40iw_sc_dev *dev);
f69c3331	175	bool i40iw_vf_clear_to_send(struct i40iw_sc_dev *dev);
34abf9ed	176	enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc desc, void addr,
4e9042e6 FL	177	u32 length, u32 value);
	178	struct i40iw_sc_qp i40iw_ieq_get_qp(struct i40iw_sc_dev dev, struct i40iw_puda_buf *buf);
	179	void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length, u32 seqnum);
34abf9ed TN	180	void i40iw_free_hash_desc(struct shash_desc *);
34abf9ed TN	181	enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **);
4e9042e6 FL	182	enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
	183	struct i40iw_puda_buf *buf);
	184	enum i40iw_status_code i40iw_cqp_sds_cmd(struct i40iw_sc_dev *dev,
	185	struct i40iw_update_sds_info *info);
	186	enum i40iw_status_code i40iw_cqp_manage_hmc_fcn_cmd(struct i40iw_sc_dev *dev,
	187	struct i40iw_hmc_fcn_info *hmcfcninfo);
	188	enum i40iw_status_code i40iw_cqp_query_fpm_values_cmd(struct i40iw_sc_dev *dev,
	189	struct i40iw_dma_mem *values_mem,
	190	u8 hmc_fn_id);
	191	enum i40iw_status_code i40iw_cqp_commit_fpm_values_cmd(struct i40iw_sc_dev *dev,
	192	struct i40iw_dma_mem *values_mem,
	193	u8 hmc_fn_id);
	194	enum i40iw_status_code i40iw_alloc_query_fpm_buf(struct i40iw_sc_dev *dev,
	195	struct i40iw_dma_mem *mem);
	196	enum i40iw_status_code i40iw_cqp_manage_vf_pble_bp(struct i40iw_sc_dev *dev,
	197	struct i40iw_manage_vf_pble_info *info);
	198	void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev,
	199	struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);
	200	void i40iw_remove_head(struct list_head list);
	201
	202	void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);
	203	void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);
	204	void i40iw_terminate_start_timer(struct i40iw_sc_qp *qp);
	205	void i40iw_terminate_del_timer(struct i40iw_sc_qp *qp);
	206
	207	enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
	208	struct i40iw_manage_vf_pble_info *info,
	209	bool wait);
	210	struct i40iw_dev_pestat;
	211	void i40iw_hw_stats_start_timer(struct i40iw_sc_dev *);
	212	void i40iw_hw_stats_del_timer(struct i40iw_sc_dev *);
	213	#define i40iw_mmiowb() mmiowb()
	214	void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value);
	215	u32 i40iw_rd32(struct i40iw_hw *hw, u32 reg);
	216	#endif /* _I40IW_OSDEP_H_ */