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9a443537 | 1 | /* |
2 | * Copyright (c) 2016 Hisilicon Limited. | |
3 | * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/platform_device.h> | |
e89bf462 | 35 | #include <linux/vmalloc.h> |
9a443537 | 36 | #include <rdma/ib_umem.h> |
37 | #include "hns_roce_device.h" | |
38 | #include "hns_roce_cmd.h" | |
39 | #include "hns_roce_hem.h" | |
40 | ||
41 | static u32 hw_index_to_key(unsigned long ind) | |
42 | { | |
43 | return (u32)(ind >> 24) | (ind << 8); | |
44 | } | |
45 | ||
bfcc681b | 46 | unsigned long key_to_hw_index(u32 key) |
9a443537 | 47 | { |
48 | return (key << 24) | (key >> 8); | |
49 | } | |
50 | ||
6eef5242 YL |
51 | static int hns_roce_hw_create_mpt(struct hns_roce_dev *hr_dev, |
52 | struct hns_roce_cmd_mailbox *mailbox, | |
53 | unsigned long mpt_index) | |
9a443537 | 54 | { |
55 | return hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, mpt_index, 0, | |
6eef5242 | 56 | HNS_ROCE_CMD_CREATE_MPT, |
6b877c32 | 57 | HNS_ROCE_CMD_TIMEOUT_MSECS); |
9a443537 | 58 | } |
59 | ||
6eef5242 YL |
60 | int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, |
61 | struct hns_roce_cmd_mailbox *mailbox, | |
62 | unsigned long mpt_index) | |
9a443537 | 63 | { |
64 | return hns_roce_cmd_mbox(hr_dev, 0, mailbox ? mailbox->dma : 0, | |
6eef5242 | 65 | mpt_index, !mailbox, HNS_ROCE_CMD_DESTROY_MPT, |
6b877c32 | 66 | HNS_ROCE_CMD_TIMEOUT_MSECS); |
9a443537 | 67 | } |
68 | ||
69 | static int hns_roce_buddy_alloc(struct hns_roce_buddy *buddy, int order, | |
70 | unsigned long *seg) | |
71 | { | |
72 | int o; | |
73 | u32 m; | |
74 | ||
75 | spin_lock(&buddy->lock); | |
76 | ||
77 | for (o = order; o <= buddy->max_order; ++o) { | |
78 | if (buddy->num_free[o]) { | |
79 | m = 1 << (buddy->max_order - o); | |
80 | *seg = find_first_bit(buddy->bits[o], m); | |
81 | if (*seg < m) | |
82 | goto found; | |
83 | } | |
84 | } | |
85 | spin_unlock(&buddy->lock); | |
1ceb0b11 | 86 | return -EINVAL; |
9a443537 | 87 | |
88 | found: | |
89 | clear_bit(*seg, buddy->bits[o]); | |
90 | --buddy->num_free[o]; | |
91 | ||
92 | while (o > order) { | |
93 | --o; | |
94 | *seg <<= 1; | |
95 | set_bit(*seg ^ 1, buddy->bits[o]); | |
96 | ++buddy->num_free[o]; | |
97 | } | |
98 | ||
99 | spin_unlock(&buddy->lock); | |
100 | ||
101 | *seg <<= order; | |
102 | return 0; | |
103 | } | |
104 | ||
105 | static void hns_roce_buddy_free(struct hns_roce_buddy *buddy, unsigned long seg, | |
106 | int order) | |
107 | { | |
108 | seg >>= order; | |
109 | ||
110 | spin_lock(&buddy->lock); | |
111 | ||
112 | while (test_bit(seg ^ 1, buddy->bits[order])) { | |
113 | clear_bit(seg ^ 1, buddy->bits[order]); | |
114 | --buddy->num_free[order]; | |
115 | seg >>= 1; | |
116 | ++order; | |
117 | } | |
118 | ||
119 | set_bit(seg, buddy->bits[order]); | |
120 | ++buddy->num_free[order]; | |
121 | ||
122 | spin_unlock(&buddy->lock); | |
123 | } | |
124 | ||
125 | static int hns_roce_buddy_init(struct hns_roce_buddy *buddy, int max_order) | |
126 | { | |
127 | int i, s; | |
128 | ||
129 | buddy->max_order = max_order; | |
130 | spin_lock_init(&buddy->lock); | |
4418b27b ME |
131 | buddy->bits = kcalloc(buddy->max_order + 1, |
132 | sizeof(*buddy->bits), | |
133 | GFP_KERNEL); | |
134 | buddy->num_free = kcalloc(buddy->max_order + 1, | |
135 | sizeof(*buddy->num_free), | |
136 | GFP_KERNEL); | |
9a443537 | 137 | if (!buddy->bits || !buddy->num_free) |
138 | goto err_out; | |
139 | ||
140 | for (i = 0; i <= buddy->max_order; ++i) { | |
141 | s = BITS_TO_LONGS(1 << (buddy->max_order - i)); | |
8d497eb0 WHX |
142 | buddy->bits[i] = kcalloc(s, sizeof(long), GFP_KERNEL | |
143 | __GFP_NOWARN); | |
144 | if (!buddy->bits[i]) { | |
fad953ce | 145 | buddy->bits[i] = vzalloc(array_size(s, sizeof(long))); |
8d497eb0 WHX |
146 | if (!buddy->bits[i]) |
147 | goto err_out_free; | |
148 | } | |
9a443537 | 149 | } |
150 | ||
151 | set_bit(0, buddy->bits[buddy->max_order]); | |
152 | buddy->num_free[buddy->max_order] = 1; | |
153 | ||
154 | return 0; | |
155 | ||
156 | err_out_free: | |
157 | for (i = 0; i <= buddy->max_order; ++i) | |
8d497eb0 | 158 | kvfree(buddy->bits[i]); |
9a443537 | 159 | |
160 | err_out: | |
161 | kfree(buddy->bits); | |
162 | kfree(buddy->num_free); | |
163 | return -ENOMEM; | |
164 | } | |
165 | ||
166 | static void hns_roce_buddy_cleanup(struct hns_roce_buddy *buddy) | |
167 | { | |
168 | int i; | |
169 | ||
170 | for (i = 0; i <= buddy->max_order; ++i) | |
8d497eb0 | 171 | kvfree(buddy->bits[i]); |
9a443537 | 172 | |
173 | kfree(buddy->bits); | |
174 | kfree(buddy->num_free); | |
175 | } | |
176 | ||
177 | static int hns_roce_alloc_mtt_range(struct hns_roce_dev *hr_dev, int order, | |
9766edc3 | 178 | unsigned long *seg, u32 mtt_type) |
9a443537 | 179 | { |
180 | struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; | |
9766edc3 SX |
181 | struct hns_roce_hem_table *table; |
182 | struct hns_roce_buddy *buddy; | |
183 | int ret; | |
184 | ||
c7bcb134 LO |
185 | switch (mtt_type) { |
186 | case MTT_TYPE_WQE: | |
9766edc3 SX |
187 | buddy = &mr_table->mtt_buddy; |
188 | table = &mr_table->mtt_table; | |
c7bcb134 LO |
189 | break; |
190 | case MTT_TYPE_CQE: | |
9766edc3 SX |
191 | buddy = &mr_table->mtt_cqe_buddy; |
192 | table = &mr_table->mtt_cqe_table; | |
c7bcb134 LO |
193 | break; |
194 | case MTT_TYPE_SRQWQE: | |
195 | buddy = &mr_table->mtt_srqwqe_buddy; | |
196 | table = &mr_table->mtt_srqwqe_table; | |
197 | break; | |
198 | case MTT_TYPE_IDX: | |
199 | buddy = &mr_table->mtt_idx_buddy; | |
200 | table = &mr_table->mtt_idx_table; | |
201 | break; | |
202 | default: | |
203 | dev_err(hr_dev->dev, "Unsupport MTT table type: %d\n", | |
204 | mtt_type); | |
205 | return -EINVAL; | |
9766edc3 | 206 | } |
9a443537 | 207 | |
9766edc3 | 208 | ret = hns_roce_buddy_alloc(buddy, order, seg); |
1ceb0b11 YL |
209 | if (ret) |
210 | return ret; | |
9a443537 | 211 | |
1ceb0b11 YL |
212 | ret = hns_roce_table_get_range(hr_dev, table, *seg, |
213 | *seg + (1 << order) - 1); | |
214 | if (ret) { | |
9766edc3 | 215 | hns_roce_buddy_free(buddy, *seg, order); |
1ceb0b11 | 216 | return ret; |
9a443537 | 217 | } |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
222 | int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift, | |
223 | struct hns_roce_mtt *mtt) | |
224 | { | |
9766edc3 | 225 | int ret; |
9a443537 | 226 | int i; |
227 | ||
228 | /* Page num is zero, correspond to DMA memory register */ | |
229 | if (!npages) { | |
230 | mtt->order = -1; | |
231 | mtt->page_shift = HNS_ROCE_HEM_PAGE_SHIFT; | |
232 | return 0; | |
233 | } | |
234 | ||
ad61dd30 | 235 | /* Note: if page_shift is zero, FAST memory register */ |
9a443537 | 236 | mtt->page_shift = page_shift; |
237 | ||
238 | /* Compute MTT entry necessary */ | |
239 | for (mtt->order = 0, i = HNS_ROCE_MTT_ENTRY_PER_SEG; i < npages; | |
240 | i <<= 1) | |
241 | ++mtt->order; | |
242 | ||
243 | /* Allocate MTT entry */ | |
9766edc3 SX |
244 | ret = hns_roce_alloc_mtt_range(hr_dev, mtt->order, &mtt->first_seg, |
245 | mtt->mtt_type); | |
30d41e18 | 246 | if (ret) |
9a443537 | 247 | return -ENOMEM; |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, struct hns_roce_mtt *mtt) | |
253 | { | |
254 | struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; | |
255 | ||
256 | if (mtt->order < 0) | |
257 | return; | |
258 | ||
c7bcb134 LO |
259 | switch (mtt->mtt_type) { |
260 | case MTT_TYPE_WQE: | |
9766edc3 SX |
261 | hns_roce_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, |
262 | mtt->order); | |
263 | hns_roce_table_put_range(hr_dev, &mr_table->mtt_table, | |
264 | mtt->first_seg, | |
265 | mtt->first_seg + (1 << mtt->order) - 1); | |
c7bcb134 LO |
266 | break; |
267 | case MTT_TYPE_CQE: | |
9766edc3 SX |
268 | hns_roce_buddy_free(&mr_table->mtt_cqe_buddy, mtt->first_seg, |
269 | mtt->order); | |
270 | hns_roce_table_put_range(hr_dev, &mr_table->mtt_cqe_table, | |
271 | mtt->first_seg, | |
272 | mtt->first_seg + (1 << mtt->order) - 1); | |
c7bcb134 LO |
273 | break; |
274 | case MTT_TYPE_SRQWQE: | |
275 | hns_roce_buddy_free(&mr_table->mtt_srqwqe_buddy, mtt->first_seg, | |
276 | mtt->order); | |
277 | hns_roce_table_put_range(hr_dev, &mr_table->mtt_srqwqe_table, | |
278 | mtt->first_seg, | |
279 | mtt->first_seg + (1 << mtt->order) - 1); | |
280 | break; | |
281 | case MTT_TYPE_IDX: | |
282 | hns_roce_buddy_free(&mr_table->mtt_idx_buddy, mtt->first_seg, | |
283 | mtt->order); | |
284 | hns_roce_table_put_range(hr_dev, &mr_table->mtt_idx_table, | |
285 | mtt->first_seg, | |
286 | mtt->first_seg + (1 << mtt->order) - 1); | |
287 | break; | |
288 | default: | |
289 | dev_err(hr_dev->dev, | |
290 | "Unsupport mtt type %d, clean mtt failed\n", | |
291 | mtt->mtt_type); | |
292 | break; | |
9766edc3 | 293 | } |
9a443537 | 294 | } |
295 | ||
ff795f71 WHX |
296 | static void hns_roce_loop_free(struct hns_roce_dev *hr_dev, |
297 | struct hns_roce_mr *mr, int err_loop_index, | |
298 | int loop_i, int loop_j) | |
299 | { | |
300 | struct device *dev = hr_dev->dev; | |
301 | u32 mhop_num; | |
302 | u32 pbl_bt_sz; | |
303 | u64 bt_idx; | |
304 | int i, j; | |
305 | ||
306 | pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT); | |
307 | mhop_num = hr_dev->caps.pbl_hop_num; | |
308 | ||
309 | i = loop_i; | |
ff795f71 WHX |
310 | if (mhop_num == 3 && err_loop_index == 2) { |
311 | for (; i >= 0; i--) { | |
312 | dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i], | |
313 | mr->pbl_l1_dma_addr[i]); | |
314 | ||
2a3d923f | 315 | for (j = 0; j < pbl_bt_sz / BA_BYTE_LEN; j++) { |
ff795f71 WHX |
316 | if (i == loop_i && j >= loop_j) |
317 | break; | |
318 | ||
2a3d923f | 319 | bt_idx = i * pbl_bt_sz / BA_BYTE_LEN + j; |
ff795f71 WHX |
320 | dma_free_coherent(dev, pbl_bt_sz, |
321 | mr->pbl_bt_l2[bt_idx], | |
322 | mr->pbl_l2_dma_addr[bt_idx]); | |
323 | } | |
324 | } | |
325 | } else if (mhop_num == 3 && err_loop_index == 1) { | |
326 | for (i -= 1; i >= 0; i--) { | |
327 | dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i], | |
328 | mr->pbl_l1_dma_addr[i]); | |
329 | ||
2a3d923f LO |
330 | for (j = 0; j < pbl_bt_sz / BA_BYTE_LEN; j++) { |
331 | bt_idx = i * pbl_bt_sz / BA_BYTE_LEN + j; | |
ff795f71 WHX |
332 | dma_free_coherent(dev, pbl_bt_sz, |
333 | mr->pbl_bt_l2[bt_idx], | |
334 | mr->pbl_l2_dma_addr[bt_idx]); | |
335 | } | |
336 | } | |
337 | } else if (mhop_num == 2 && err_loop_index == 1) { | |
338 | for (i -= 1; i >= 0; i--) | |
339 | dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i], | |
340 | mr->pbl_l1_dma_addr[i]); | |
341 | } else { | |
342 | dev_warn(dev, "not support: mhop_num=%d, err_loop_index=%d.", | |
343 | mhop_num, err_loop_index); | |
344 | return; | |
345 | } | |
346 | ||
347 | dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l0, mr->pbl_l0_dma_addr); | |
348 | mr->pbl_bt_l0 = NULL; | |
349 | mr->pbl_l0_dma_addr = 0; | |
350 | } | |
89b4b70b | 351 | static int pbl_1hop_alloc(struct hns_roce_dev *hr_dev, int npages, |
352 | struct hns_roce_mr *mr, u32 pbl_bt_sz) | |
353 | { | |
354 | struct device *dev = hr_dev->dev; | |
ff795f71 | 355 | |
89b4b70b | 356 | if (npages > pbl_bt_sz / 8) { |
357 | dev_err(dev, "npages %d is larger than buf_pg_sz!", | |
358 | npages); | |
359 | return -EINVAL; | |
360 | } | |
361 | mr->pbl_buf = dma_alloc_coherent(dev, npages * 8, | |
362 | &(mr->pbl_dma_addr), | |
363 | GFP_KERNEL); | |
364 | if (!mr->pbl_buf) | |
365 | return -ENOMEM; | |
366 | ||
367 | mr->pbl_size = npages; | |
368 | mr->pbl_ba = mr->pbl_dma_addr; | |
369 | mr->pbl_hop_num = 1; | |
370 | mr->pbl_ba_pg_sz = hr_dev->caps.pbl_ba_pg_sz; | |
371 | mr->pbl_buf_pg_sz = hr_dev->caps.pbl_buf_pg_sz; | |
372 | return 0; | |
373 | ||
374 | } | |
375 | ||
376 | ||
377 | static int pbl_2hop_alloc(struct hns_roce_dev *hr_dev, int npages, | |
378 | struct hns_roce_mr *mr, u32 pbl_bt_sz) | |
ff795f71 WHX |
379 | { |
380 | struct device *dev = hr_dev->dev; | |
ff795f71 | 381 | int npages_allocated; |
ff795f71 WHX |
382 | u64 pbl_last_bt_num; |
383 | u64 pbl_bt_cnt = 0; | |
ff795f71 | 384 | u64 size; |
89b4b70b | 385 | int i; |
ff795f71 | 386 | |
ff795f71 WHX |
387 | pbl_last_bt_num = (npages + pbl_bt_sz / 8 - 1) / (pbl_bt_sz / 8); |
388 | ||
89b4b70b | 389 | /* alloc L1 BT */ |
390 | for (i = 0; i < pbl_bt_sz / 8; i++) { | |
391 | if (pbl_bt_cnt + 1 < pbl_last_bt_num) { | |
392 | size = pbl_bt_sz; | |
393 | } else { | |
394 | npages_allocated = i * (pbl_bt_sz / 8); | |
395 | size = (npages - npages_allocated) * 8; | |
ff795f71 | 396 | } |
89b4b70b | 397 | mr->pbl_bt_l1[i] = dma_alloc_coherent(dev, size, |
398 | &(mr->pbl_l1_dma_addr[i]), | |
399 | GFP_KERNEL); | |
400 | if (!mr->pbl_bt_l1[i]) { | |
401 | hns_roce_loop_free(hr_dev, mr, 1, i, 0); | |
ff795f71 | 402 | return -ENOMEM; |
89b4b70b | 403 | } |
ff795f71 | 404 | |
89b4b70b | 405 | *(mr->pbl_bt_l0 + i) = mr->pbl_l1_dma_addr[i]; |
406 | ||
407 | pbl_bt_cnt++; | |
408 | if (pbl_bt_cnt >= pbl_last_bt_num) | |
409 | break; | |
ff795f71 WHX |
410 | } |
411 | ||
89b4b70b | 412 | mr->l0_chunk_last_num = i + 1; |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static int pbl_3hop_alloc(struct hns_roce_dev *hr_dev, int npages, | |
418 | struct hns_roce_mr *mr, u32 pbl_bt_sz) | |
419 | { | |
420 | struct device *dev = hr_dev->dev; | |
421 | int mr_alloc_done = 0; | |
422 | int npages_allocated; | |
423 | u64 pbl_last_bt_num; | |
424 | u64 pbl_bt_cnt = 0; | |
425 | u64 bt_idx; | |
426 | u64 size; | |
427 | int i; | |
428 | int j = 0; | |
429 | ||
430 | pbl_last_bt_num = (npages + pbl_bt_sz / 8 - 1) / (pbl_bt_sz / 8); | |
431 | ||
432 | mr->pbl_l2_dma_addr = kcalloc(pbl_last_bt_num, | |
433 | sizeof(*mr->pbl_l2_dma_addr), | |
ff795f71 | 434 | GFP_KERNEL); |
89b4b70b | 435 | if (!mr->pbl_l2_dma_addr) |
ff795f71 WHX |
436 | return -ENOMEM; |
437 | ||
89b4b70b | 438 | mr->pbl_bt_l2 = kcalloc(pbl_last_bt_num, |
439 | sizeof(*mr->pbl_bt_l2), | |
ff795f71 | 440 | GFP_KERNEL); |
89b4b70b | 441 | if (!mr->pbl_bt_l2) |
442 | goto err_kcalloc_bt_l2; | |
443 | ||
444 | /* alloc L1, L2 BT */ | |
445 | for (i = 0; i < pbl_bt_sz / 8; i++) { | |
446 | mr->pbl_bt_l1[i] = dma_alloc_coherent(dev, pbl_bt_sz, | |
447 | &(mr->pbl_l1_dma_addr[i]), | |
448 | GFP_KERNEL); | |
449 | if (!mr->pbl_bt_l1[i]) { | |
450 | hns_roce_loop_free(hr_dev, mr, 1, i, 0); | |
451 | goto err_dma_alloc_l0; | |
452 | } | |
ff795f71 | 453 | |
89b4b70b | 454 | *(mr->pbl_bt_l0 + i) = mr->pbl_l1_dma_addr[i]; |
ff795f71 | 455 | |
89b4b70b | 456 | for (j = 0; j < pbl_bt_sz / 8; j++) { |
457 | bt_idx = i * pbl_bt_sz / 8 + j; | |
ff795f71 | 458 | |
ff795f71 WHX |
459 | if (pbl_bt_cnt + 1 < pbl_last_bt_num) { |
460 | size = pbl_bt_sz; | |
461 | } else { | |
89b4b70b | 462 | npages_allocated = bt_idx * |
463 | (pbl_bt_sz / 8); | |
ff795f71 WHX |
464 | size = (npages - npages_allocated) * 8; |
465 | } | |
89b4b70b | 466 | mr->pbl_bt_l2[bt_idx] = dma_alloc_coherent( |
467 | dev, size, | |
468 | &(mr->pbl_l2_dma_addr[bt_idx]), | |
469 | GFP_KERNEL); | |
470 | if (!mr->pbl_bt_l2[bt_idx]) { | |
471 | hns_roce_loop_free(hr_dev, mr, 2, i, j); | |
ff795f71 WHX |
472 | goto err_dma_alloc_l0; |
473 | } | |
474 | ||
89b4b70b | 475 | *(mr->pbl_bt_l1[i] + j) = |
476 | mr->pbl_l2_dma_addr[bt_idx]; | |
ff795f71 WHX |
477 | |
478 | pbl_bt_cnt++; | |
89b4b70b | 479 | if (pbl_bt_cnt >= pbl_last_bt_num) { |
480 | mr_alloc_done = 1; | |
ff795f71 | 481 | break; |
ff795f71 | 482 | } |
ff795f71 | 483 | } |
89b4b70b | 484 | |
485 | if (mr_alloc_done) | |
486 | break; | |
ff795f71 WHX |
487 | } |
488 | ||
489 | mr->l0_chunk_last_num = i + 1; | |
89b4b70b | 490 | mr->l1_chunk_last_num = j + 1; |
ff795f71 | 491 | |
ff795f71 WHX |
492 | |
493 | return 0; | |
494 | ||
495 | err_dma_alloc_l0: | |
496 | kfree(mr->pbl_bt_l2); | |
497 | mr->pbl_bt_l2 = NULL; | |
498 | ||
499 | err_kcalloc_bt_l2: | |
500 | kfree(mr->pbl_l2_dma_addr); | |
501 | mr->pbl_l2_dma_addr = NULL; | |
502 | ||
89b4b70b | 503 | return -ENOMEM; |
504 | } | |
505 | ||
506 | ||
507 | /* PBL multi hop addressing */ | |
508 | static int hns_roce_mhop_alloc(struct hns_roce_dev *hr_dev, int npages, | |
509 | struct hns_roce_mr *mr) | |
510 | { | |
511 | struct device *dev = hr_dev->dev; | |
512 | u32 pbl_bt_sz; | |
513 | u32 mhop_num; | |
514 | ||
515 | mhop_num = (mr->type == MR_TYPE_FRMR ? 1 : hr_dev->caps.pbl_hop_num); | |
516 | pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT); | |
517 | ||
518 | if (mhop_num == HNS_ROCE_HOP_NUM_0) | |
519 | return 0; | |
520 | ||
89b4b70b | 521 | if (mhop_num == 1) |
522 | return pbl_1hop_alloc(hr_dev, npages, mr, pbl_bt_sz); | |
523 | ||
524 | mr->pbl_l1_dma_addr = kcalloc(pbl_bt_sz / 8, | |
525 | sizeof(*mr->pbl_l1_dma_addr), | |
526 | GFP_KERNEL); | |
527 | if (!mr->pbl_l1_dma_addr) | |
528 | return -ENOMEM; | |
529 | ||
530 | mr->pbl_bt_l1 = kcalloc(pbl_bt_sz / 8, sizeof(*mr->pbl_bt_l1), | |
531 | GFP_KERNEL); | |
532 | if (!mr->pbl_bt_l1) | |
533 | goto err_kcalloc_bt_l1; | |
534 | ||
535 | /* alloc L0 BT */ | |
536 | mr->pbl_bt_l0 = dma_alloc_coherent(dev, pbl_bt_sz, | |
537 | &(mr->pbl_l0_dma_addr), | |
538 | GFP_KERNEL); | |
539 | if (!mr->pbl_bt_l0) | |
540 | goto err_kcalloc_l2_dma; | |
541 | ||
542 | if (mhop_num == 2) { | |
543 | if (pbl_2hop_alloc(hr_dev, npages, mr, pbl_bt_sz)) | |
544 | goto err_kcalloc_l2_dma; | |
545 | } | |
546 | ||
547 | if (mhop_num == 3) { | |
548 | if (pbl_3hop_alloc(hr_dev, npages, mr, pbl_bt_sz)) | |
549 | goto err_kcalloc_l2_dma; | |
550 | } | |
551 | ||
552 | ||
553 | mr->pbl_size = npages; | |
554 | mr->pbl_ba = mr->pbl_l0_dma_addr; | |
555 | mr->pbl_hop_num = hr_dev->caps.pbl_hop_num; | |
556 | mr->pbl_ba_pg_sz = hr_dev->caps.pbl_ba_pg_sz; | |
557 | mr->pbl_buf_pg_sz = hr_dev->caps.pbl_buf_pg_sz; | |
558 | ||
559 | return 0; | |
560 | ||
ff795f71 WHX |
561 | err_kcalloc_l2_dma: |
562 | kfree(mr->pbl_bt_l1); | |
563 | mr->pbl_bt_l1 = NULL; | |
564 | ||
565 | err_kcalloc_bt_l1: | |
566 | kfree(mr->pbl_l1_dma_addr); | |
567 | mr->pbl_l1_dma_addr = NULL; | |
568 | ||
569 | return -ENOMEM; | |
570 | } | |
571 | ||
9a443537 | 572 | static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova, |
573 | u64 size, u32 access, int npages, | |
574 | struct hns_roce_mr *mr) | |
575 | { | |
13ca970e | 576 | struct device *dev = hr_dev->dev; |
9a443537 | 577 | unsigned long index = 0; |
2a3d923f | 578 | int ret; |
9a443537 | 579 | |
580 | /* Allocate a key for mr from mr_table */ | |
581 | ret = hns_roce_bitmap_alloc(&hr_dev->mr_table.mtpt_bitmap, &index); | |
1ceb0b11 | 582 | if (ret) |
9a443537 | 583 | return -ENOMEM; |
584 | ||
585 | mr->iova = iova; /* MR va starting addr */ | |
586 | mr->size = size; /* MR addr range */ | |
587 | mr->pd = pd; /* MR num */ | |
588 | mr->access = access; /* MR access permit */ | |
589 | mr->enabled = 0; /* MR active status */ | |
590 | mr->key = hw_index_to_key(index); /* MR key */ | |
591 | ||
592 | if (size == ~0ull) { | |
9a443537 | 593 | mr->pbl_buf = NULL; |
594 | mr->pbl_dma_addr = 0; | |
ff795f71 WHX |
595 | /* PBL multi-hop addressing parameters */ |
596 | mr->pbl_bt_l2 = NULL; | |
597 | mr->pbl_bt_l1 = NULL; | |
598 | mr->pbl_bt_l0 = NULL; | |
599 | mr->pbl_l2_dma_addr = NULL; | |
600 | mr->pbl_l1_dma_addr = NULL; | |
601 | mr->pbl_l0_dma_addr = 0; | |
9a443537 | 602 | } else { |
ff795f71 | 603 | if (!hr_dev->caps.pbl_hop_num) { |
2a3d923f LO |
604 | mr->pbl_buf = dma_alloc_coherent(dev, |
605 | npages * BA_BYTE_LEN, | |
ff795f71 WHX |
606 | &(mr->pbl_dma_addr), |
607 | GFP_KERNEL); | |
608 | if (!mr->pbl_buf) | |
609 | return -ENOMEM; | |
610 | } else { | |
611 | ret = hns_roce_mhop_alloc(hr_dev, npages, mr); | |
612 | } | |
9a443537 | 613 | } |
614 | ||
ff795f71 WHX |
615 | return ret; |
616 | } | |
617 | ||
618 | static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev, | |
619 | struct hns_roce_mr *mr) | |
620 | { | |
621 | struct device *dev = hr_dev->dev; | |
622 | int npages_allocated; | |
623 | int npages; | |
624 | int i, j; | |
625 | u32 pbl_bt_sz; | |
626 | u32 mhop_num; | |
627 | u64 bt_idx; | |
628 | ||
68a997c5 | 629 | npages = mr->pbl_size; |
ff795f71 | 630 | pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT); |
68a997c5 | 631 | mhop_num = (mr->type == MR_TYPE_FRMR) ? 1 : hr_dev->caps.pbl_hop_num; |
ff795f71 WHX |
632 | |
633 | if (mhop_num == HNS_ROCE_HOP_NUM_0) | |
634 | return; | |
635 | ||
ff795f71 | 636 | if (mhop_num == 1) { |
2a3d923f | 637 | dma_free_coherent(dev, (unsigned int)(npages * BA_BYTE_LEN), |
ff795f71 WHX |
638 | mr->pbl_buf, mr->pbl_dma_addr); |
639 | return; | |
640 | } | |
641 | ||
642 | dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l0, | |
643 | mr->pbl_l0_dma_addr); | |
644 | ||
645 | if (mhop_num == 2) { | |
646 | for (i = 0; i < mr->l0_chunk_last_num; i++) { | |
647 | if (i == mr->l0_chunk_last_num - 1) { | |
2a3d923f LO |
648 | npages_allocated = |
649 | i * (pbl_bt_sz / BA_BYTE_LEN); | |
ff795f71 WHX |
650 | |
651 | dma_free_coherent(dev, | |
2a3d923f LO |
652 | (npages - npages_allocated) * BA_BYTE_LEN, |
653 | mr->pbl_bt_l1[i], | |
654 | mr->pbl_l1_dma_addr[i]); | |
ff795f71 WHX |
655 | |
656 | break; | |
657 | } | |
658 | ||
659 | dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i], | |
660 | mr->pbl_l1_dma_addr[i]); | |
661 | } | |
662 | } else if (mhop_num == 3) { | |
663 | for (i = 0; i < mr->l0_chunk_last_num; i++) { | |
664 | dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i], | |
665 | mr->pbl_l1_dma_addr[i]); | |
666 | ||
2a3d923f LO |
667 | for (j = 0; j < pbl_bt_sz / BA_BYTE_LEN; j++) { |
668 | bt_idx = i * (pbl_bt_sz / BA_BYTE_LEN) + j; | |
ff795f71 WHX |
669 | |
670 | if ((i == mr->l0_chunk_last_num - 1) | |
671 | && j == mr->l1_chunk_last_num - 1) { | |
672 | npages_allocated = bt_idx * | |
2a3d923f | 673 | (pbl_bt_sz / BA_BYTE_LEN); |
ff795f71 WHX |
674 | |
675 | dma_free_coherent(dev, | |
2a3d923f LO |
676 | (npages - npages_allocated) * |
677 | BA_BYTE_LEN, | |
ff795f71 WHX |
678 | mr->pbl_bt_l2[bt_idx], |
679 | mr->pbl_l2_dma_addr[bt_idx]); | |
680 | ||
681 | break; | |
682 | } | |
683 | ||
684 | dma_free_coherent(dev, pbl_bt_sz, | |
685 | mr->pbl_bt_l2[bt_idx], | |
686 | mr->pbl_l2_dma_addr[bt_idx]); | |
687 | } | |
688 | } | |
689 | } | |
690 | ||
691 | kfree(mr->pbl_bt_l1); | |
692 | kfree(mr->pbl_l1_dma_addr); | |
693 | mr->pbl_bt_l1 = NULL; | |
694 | mr->pbl_l1_dma_addr = NULL; | |
695 | if (mhop_num == 3) { | |
696 | kfree(mr->pbl_bt_l2); | |
697 | kfree(mr->pbl_l2_dma_addr); | |
698 | mr->pbl_bt_l2 = NULL; | |
699 | mr->pbl_l2_dma_addr = NULL; | |
700 | } | |
9a443537 | 701 | } |
702 | ||
703 | static void hns_roce_mr_free(struct hns_roce_dev *hr_dev, | |
704 | struct hns_roce_mr *mr) | |
705 | { | |
13ca970e | 706 | struct device *dev = hr_dev->dev; |
9a443537 | 707 | int npages = 0; |
708 | int ret; | |
709 | ||
710 | if (mr->enabled) { | |
6eef5242 YL |
711 | ret = hns_roce_hw_destroy_mpt(hr_dev, NULL, |
712 | key_to_hw_index(mr->key) & | |
713 | (hr_dev->caps.num_mtpts - 1)); | |
9a443537 | 714 | if (ret) |
6eef5242 | 715 | dev_warn(dev, "DESTROY_MPT failed (%d)\n", ret); |
9a443537 | 716 | } |
717 | ||
718 | if (mr->size != ~0ULL) { | |
68a997c5 YL |
719 | if (mr->type == MR_TYPE_MR) |
720 | npages = ib_umem_page_count(mr->umem); | |
ff795f71 WHX |
721 | |
722 | if (!hr_dev->caps.pbl_hop_num) | |
2a3d923f LO |
723 | dma_free_coherent(dev, |
724 | (unsigned int)(npages * BA_BYTE_LEN), | |
ff795f71 WHX |
725 | mr->pbl_buf, mr->pbl_dma_addr); |
726 | else | |
727 | hns_roce_mhop_free(hr_dev, mr); | |
9a443537 | 728 | } |
729 | ||
ff795f71 WHX |
730 | if (mr->enabled) |
731 | hns_roce_table_put(hr_dev, &hr_dev->mr_table.mtpt_table, | |
732 | key_to_hw_index(mr->key)); | |
733 | ||
9a443537 | 734 | hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap, |
5e6ff78a | 735 | key_to_hw_index(mr->key), BITMAP_NO_RR); |
9a443537 | 736 | } |
737 | ||
738 | static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev, | |
739 | struct hns_roce_mr *mr) | |
740 | { | |
741 | int ret; | |
742 | unsigned long mtpt_idx = key_to_hw_index(mr->key); | |
13ca970e | 743 | struct device *dev = hr_dev->dev; |
9a443537 | 744 | struct hns_roce_cmd_mailbox *mailbox; |
745 | struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; | |
746 | ||
747 | /* Prepare HEM entry memory */ | |
748 | ret = hns_roce_table_get(hr_dev, &mr_table->mtpt_table, mtpt_idx); | |
749 | if (ret) | |
750 | return ret; | |
751 | ||
752 | /* Allocate mailbox memory */ | |
753 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
754 | if (IS_ERR(mailbox)) { | |
755 | ret = PTR_ERR(mailbox); | |
756 | goto err_table; | |
757 | } | |
758 | ||
68a997c5 YL |
759 | if (mr->type != MR_TYPE_FRMR) |
760 | ret = hr_dev->hw->write_mtpt(mailbox->buf, mr, mtpt_idx); | |
761 | else | |
762 | ret = hr_dev->hw->frmr_write_mtpt(mailbox->buf, mr); | |
9a443537 | 763 | if (ret) { |
764 | dev_err(dev, "Write mtpt fail!\n"); | |
765 | goto err_page; | |
766 | } | |
767 | ||
6eef5242 YL |
768 | ret = hns_roce_hw_create_mpt(hr_dev, mailbox, |
769 | mtpt_idx & (hr_dev->caps.num_mtpts - 1)); | |
9a443537 | 770 | if (ret) { |
6eef5242 | 771 | dev_err(dev, "CREATE_MPT failed (%d)\n", ret); |
9a443537 | 772 | goto err_page; |
773 | } | |
774 | ||
775 | mr->enabled = 1; | |
776 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
777 | ||
778 | return 0; | |
779 | ||
780 | err_page: | |
781 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
782 | ||
783 | err_table: | |
784 | hns_roce_table_put(hr_dev, &mr_table->mtpt_table, mtpt_idx); | |
785 | return ret; | |
786 | } | |
787 | ||
788 | static int hns_roce_write_mtt_chunk(struct hns_roce_dev *hr_dev, | |
789 | struct hns_roce_mtt *mtt, u32 start_index, | |
790 | u32 npages, u64 *page_list) | |
791 | { | |
6a93c77a | 792 | struct hns_roce_hem_table *table; |
9a443537 | 793 | dma_addr_t dma_handle; |
6a93c77a | 794 | __le64 *mtts; |
9a8982dc | 795 | u32 bt_page_size; |
6a93c77a | 796 | u32 i; |
9a443537 | 797 | |
c7bcb134 LO |
798 | switch (mtt->mtt_type) { |
799 | case MTT_TYPE_WQE: | |
800 | table = &hr_dev->mr_table.mtt_table; | |
9a8982dc | 801 | bt_page_size = 1 << (hr_dev->caps.mtt_ba_pg_sz + PAGE_SHIFT); |
c7bcb134 LO |
802 | break; |
803 | case MTT_TYPE_CQE: | |
804 | table = &hr_dev->mr_table.mtt_cqe_table; | |
9a8982dc | 805 | bt_page_size = 1 << (hr_dev->caps.cqe_ba_pg_sz + PAGE_SHIFT); |
c7bcb134 LO |
806 | break; |
807 | case MTT_TYPE_SRQWQE: | |
808 | table = &hr_dev->mr_table.mtt_srqwqe_table; | |
809 | bt_page_size = 1 << (hr_dev->caps.srqwqe_ba_pg_sz + PAGE_SHIFT); | |
810 | break; | |
811 | case MTT_TYPE_IDX: | |
812 | table = &hr_dev->mr_table.mtt_idx_table; | |
813 | bt_page_size = 1 << (hr_dev->caps.idx_ba_pg_sz + PAGE_SHIFT); | |
814 | break; | |
815 | default: | |
816 | return -EINVAL; | |
817 | } | |
9a8982dc | 818 | |
9a443537 | 819 | /* All MTTs must fit in the same page */ |
9a8982dc WHX |
820 | if (start_index / (bt_page_size / sizeof(u64)) != |
821 | (start_index + npages - 1) / (bt_page_size / sizeof(u64))) | |
9a443537 | 822 | return -EINVAL; |
823 | ||
824 | if (start_index & (HNS_ROCE_MTT_ENTRY_PER_SEG - 1)) | |
825 | return -EINVAL; | |
826 | ||
6a93c77a | 827 | mtts = hns_roce_table_find(hr_dev, table, |
4772e03d LO |
828 | mtt->first_seg + |
829 | start_index / HNS_ROCE_MTT_ENTRY_PER_SEG, | |
9a443537 | 830 | &dma_handle); |
831 | if (!mtts) | |
832 | return -ENOMEM; | |
833 | ||
834 | /* Save page addr, low 12 bits : 0 */ | |
6a93c77a SX |
835 | for (i = 0; i < npages; ++i) { |
836 | if (!hr_dev->caps.mtt_hop_num) | |
837 | mtts[i] = cpu_to_le64(page_list[i] >> PAGE_ADDR_SHIFT); | |
838 | else | |
839 | mtts[i] = cpu_to_le64(page_list[i]); | |
840 | } | |
9a443537 | 841 | |
842 | return 0; | |
843 | } | |
844 | ||
845 | static int hns_roce_write_mtt(struct hns_roce_dev *hr_dev, | |
846 | struct hns_roce_mtt *mtt, u32 start_index, | |
847 | u32 npages, u64 *page_list) | |
848 | { | |
849 | int chunk; | |
850 | int ret; | |
9a8982dc | 851 | u32 bt_page_size; |
9a443537 | 852 | |
853 | if (mtt->order < 0) | |
854 | return -EINVAL; | |
855 | ||
c7bcb134 LO |
856 | switch (mtt->mtt_type) { |
857 | case MTT_TYPE_WQE: | |
9a8982dc | 858 | bt_page_size = 1 << (hr_dev->caps.mtt_ba_pg_sz + PAGE_SHIFT); |
c7bcb134 LO |
859 | break; |
860 | case MTT_TYPE_CQE: | |
9a8982dc | 861 | bt_page_size = 1 << (hr_dev->caps.cqe_ba_pg_sz + PAGE_SHIFT); |
c7bcb134 LO |
862 | break; |
863 | case MTT_TYPE_SRQWQE: | |
864 | bt_page_size = 1 << (hr_dev->caps.srqwqe_ba_pg_sz + PAGE_SHIFT); | |
865 | break; | |
866 | case MTT_TYPE_IDX: | |
867 | bt_page_size = 1 << (hr_dev->caps.idx_ba_pg_sz + PAGE_SHIFT); | |
868 | break; | |
869 | default: | |
870 | dev_err(hr_dev->dev, | |
871 | "Unsupport mtt type %d, write mtt failed\n", | |
872 | mtt->mtt_type); | |
873 | return -EINVAL; | |
874 | } | |
9a8982dc | 875 | |
9a443537 | 876 | while (npages > 0) { |
9a8982dc | 877 | chunk = min_t(int, bt_page_size / sizeof(u64), npages); |
9a443537 | 878 | |
879 | ret = hns_roce_write_mtt_chunk(hr_dev, mtt, start_index, chunk, | |
880 | page_list); | |
881 | if (ret) | |
882 | return ret; | |
883 | ||
884 | npages -= chunk; | |
885 | start_index += chunk; | |
886 | page_list += chunk; | |
887 | } | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev, | |
893 | struct hns_roce_mtt *mtt, struct hns_roce_buf *buf) | |
894 | { | |
9766edc3 SX |
895 | u64 *page_list; |
896 | int ret; | |
897 | u32 i; | |
9a443537 | 898 | |
899 | page_list = kmalloc_array(buf->npages, sizeof(*page_list), GFP_KERNEL); | |
900 | if (!page_list) | |
901 | return -ENOMEM; | |
902 | ||
cc23267a XW |
903 | for (i = 0; i < buf->npages; ++i) |
904 | page_list[i] = hns_roce_buf_page(buf, i); | |
9a443537 | 905 | |
9a443537 | 906 | ret = hns_roce_write_mtt(hr_dev, mtt, 0, buf->npages, page_list); |
907 | ||
908 | kfree(page_list); | |
909 | ||
910 | return ret; | |
911 | } | |
912 | ||
913 | int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev) | |
914 | { | |
915 | struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; | |
9766edc3 | 916 | int ret; |
9a443537 | 917 | |
918 | ret = hns_roce_bitmap_init(&mr_table->mtpt_bitmap, | |
919 | hr_dev->caps.num_mtpts, | |
920 | hr_dev->caps.num_mtpts - 1, | |
921 | hr_dev->caps.reserved_mrws, 0); | |
922 | if (ret) | |
923 | return ret; | |
924 | ||
925 | ret = hns_roce_buddy_init(&mr_table->mtt_buddy, | |
926 | ilog2(hr_dev->caps.num_mtt_segs)); | |
927 | if (ret) | |
928 | goto err_buddy; | |
929 | ||
9766edc3 SX |
930 | if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) { |
931 | ret = hns_roce_buddy_init(&mr_table->mtt_cqe_buddy, | |
932 | ilog2(hr_dev->caps.num_cqe_segs)); | |
933 | if (ret) | |
934 | goto err_buddy_cqe; | |
935 | } | |
c7bcb134 LO |
936 | |
937 | if (hr_dev->caps.num_srqwqe_segs) { | |
938 | ret = hns_roce_buddy_init(&mr_table->mtt_srqwqe_buddy, | |
939 | ilog2(hr_dev->caps.num_srqwqe_segs)); | |
940 | if (ret) | |
941 | goto err_buddy_srqwqe; | |
942 | } | |
943 | ||
944 | if (hr_dev->caps.num_idx_segs) { | |
945 | ret = hns_roce_buddy_init(&mr_table->mtt_idx_buddy, | |
946 | ilog2(hr_dev->caps.num_idx_segs)); | |
947 | if (ret) | |
948 | goto err_buddy_idx; | |
949 | } | |
950 | ||
9a443537 | 951 | return 0; |
952 | ||
c7bcb134 LO |
953 | err_buddy_idx: |
954 | if (hr_dev->caps.num_srqwqe_segs) | |
955 | hns_roce_buddy_cleanup(&mr_table->mtt_srqwqe_buddy); | |
956 | ||
957 | err_buddy_srqwqe: | |
958 | if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) | |
959 | hns_roce_buddy_cleanup(&mr_table->mtt_cqe_buddy); | |
960 | ||
9766edc3 SX |
961 | err_buddy_cqe: |
962 | hns_roce_buddy_cleanup(&mr_table->mtt_buddy); | |
963 | ||
9a443537 | 964 | err_buddy: |
965 | hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap); | |
966 | return ret; | |
967 | } | |
968 | ||
969 | void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev) | |
970 | { | |
971 | struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; | |
972 | ||
c7bcb134 LO |
973 | if (hr_dev->caps.num_idx_segs) |
974 | hns_roce_buddy_cleanup(&mr_table->mtt_idx_buddy); | |
975 | if (hr_dev->caps.num_srqwqe_segs) | |
976 | hns_roce_buddy_cleanup(&mr_table->mtt_srqwqe_buddy); | |
9a443537 | 977 | hns_roce_buddy_cleanup(&mr_table->mtt_buddy); |
9766edc3 SX |
978 | if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) |
979 | hns_roce_buddy_cleanup(&mr_table->mtt_cqe_buddy); | |
9a443537 | 980 | hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap); |
981 | } | |
982 | ||
983 | struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc) | |
984 | { | |
ff795f71 WHX |
985 | struct hns_roce_mr *mr; |
986 | int ret; | |
9a443537 | 987 | |
988 | mr = kmalloc(sizeof(*mr), GFP_KERNEL); | |
989 | if (mr == NULL) | |
990 | return ERR_PTR(-ENOMEM); | |
991 | ||
68a997c5 YL |
992 | mr->type = MR_TYPE_DMA; |
993 | ||
9a443537 | 994 | /* Allocate memory region key */ |
995 | ret = hns_roce_mr_alloc(to_hr_dev(pd->device), to_hr_pd(pd)->pdn, 0, | |
996 | ~0ULL, acc, 0, mr); | |
997 | if (ret) | |
998 | goto err_free; | |
999 | ||
1000 | ret = hns_roce_mr_enable(to_hr_dev(pd->device), mr); | |
1001 | if (ret) | |
1002 | goto err_mr; | |
1003 | ||
1004 | mr->ibmr.rkey = mr->ibmr.lkey = mr->key; | |
1005 | mr->umem = NULL; | |
1006 | ||
1007 | return &mr->ibmr; | |
1008 | ||
1009 | err_mr: | |
1010 | hns_roce_mr_free(to_hr_dev(pd->device), mr); | |
1011 | ||
1012 | err_free: | |
1013 | kfree(mr); | |
1014 | return ERR_PTR(ret); | |
1015 | } | |
1016 | ||
1017 | int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, | |
1018 | struct hns_roce_mtt *mtt, struct ib_umem *umem) | |
1019 | { | |
9a8982dc | 1020 | struct device *dev = hr_dev->dev; |
3856ec55 | 1021 | struct sg_dma_page_iter sg_iter; |
9a8982dc | 1022 | unsigned int order; |
9a8982dc | 1023 | int npage = 0; |
9a443537 | 1024 | int ret = 0; |
3856ec55 | 1025 | int i; |
9a8982dc | 1026 | u64 page_addr; |
9a443537 | 1027 | u64 *pages; |
9a8982dc | 1028 | u32 bt_page_size; |
9a443537 | 1029 | u32 n; |
9a443537 | 1030 | |
c7bcb134 LO |
1031 | switch (mtt->mtt_type) { |
1032 | case MTT_TYPE_WQE: | |
1033 | order = hr_dev->caps.mtt_ba_pg_sz; | |
1034 | break; | |
1035 | case MTT_TYPE_CQE: | |
1036 | order = hr_dev->caps.cqe_ba_pg_sz; | |
1037 | break; | |
1038 | case MTT_TYPE_SRQWQE: | |
1039 | order = hr_dev->caps.srqwqe_ba_pg_sz; | |
1040 | break; | |
1041 | case MTT_TYPE_IDX: | |
1042 | order = hr_dev->caps.idx_ba_pg_sz; | |
1043 | break; | |
1044 | default: | |
1045 | dev_err(dev, "Unsupport mtt type %d, write mtt failed\n", | |
1046 | mtt->mtt_type); | |
1047 | return -EINVAL; | |
1048 | } | |
1049 | ||
9a8982dc WHX |
1050 | bt_page_size = 1 << (order + PAGE_SHIFT); |
1051 | ||
1052 | pages = (u64 *) __get_free_pages(GFP_KERNEL, order); | |
9a443537 | 1053 | if (!pages) |
1054 | return -ENOMEM; | |
1055 | ||
1056 | i = n = 0; | |
1057 | ||
3856ec55 SS |
1058 | for_each_sg_dma_page(umem->sg_head.sgl, &sg_iter, umem->nmap, 0) { |
1059 | page_addr = sg_page_iter_dma_address(&sg_iter); | |
1060 | if (!(npage % (1 << (mtt->page_shift - PAGE_SHIFT)))) { | |
1061 | if (page_addr & ((1 << mtt->page_shift) - 1)) { | |
1062 | dev_err(dev, | |
eca44507 WL |
1063 | "page_addr is not page_shift %d alignment!\n", |
1064 | mtt->page_shift); | |
3856ec55 SS |
1065 | ret = -EINVAL; |
1066 | goto out; | |
9a443537 | 1067 | } |
3856ec55 SS |
1068 | pages[i++] = page_addr; |
1069 | } | |
1070 | npage++; | |
1071 | if (i == bt_page_size / sizeof(u64)) { | |
1072 | ret = hns_roce_write_mtt(hr_dev, mtt, n, i, pages); | |
1073 | if (ret) | |
1074 | goto out; | |
1075 | n += i; | |
1076 | i = 0; | |
9a443537 | 1077 | } |
1078 | } | |
1079 | ||
1080 | if (i) | |
1081 | ret = hns_roce_write_mtt(hr_dev, mtt, n, i, pages); | |
1082 | ||
1083 | out: | |
d480bb50 | 1084 | free_pages((unsigned long) pages, order); |
9a443537 | 1085 | return ret; |
1086 | } | |
1087 | ||
ff795f71 WHX |
1088 | static int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev, |
1089 | struct hns_roce_mr *mr, | |
9a443537 | 1090 | struct ib_umem *umem) |
1091 | { | |
3856ec55 SS |
1092 | struct sg_dma_page_iter sg_iter; |
1093 | int i = 0, j = 0; | |
9a8982dc WHX |
1094 | u64 page_addr; |
1095 | u32 pbl_bt_sz; | |
ff795f71 WHX |
1096 | |
1097 | if (hr_dev->caps.pbl_hop_num == HNS_ROCE_HOP_NUM_0) | |
1098 | return 0; | |
9a443537 | 1099 | |
9a8982dc | 1100 | pbl_bt_sz = 1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT); |
3856ec55 SS |
1101 | for_each_sg_dma_page(umem->sg_head.sgl, &sg_iter, umem->nmap, 0) { |
1102 | page_addr = sg_page_iter_dma_address(&sg_iter); | |
1103 | if (!hr_dev->caps.pbl_hop_num) { | |
2a3d923f | 1104 | /* for hip06, page addr is aligned to 4K */ |
3856ec55 SS |
1105 | mr->pbl_buf[i++] = page_addr >> 12; |
1106 | } else if (hr_dev->caps.pbl_hop_num == 1) { | |
1107 | mr->pbl_buf[i++] = page_addr; | |
1108 | } else { | |
1109 | if (hr_dev->caps.pbl_hop_num == 2) | |
1110 | mr->pbl_bt_l1[i][j] = page_addr; | |
1111 | else if (hr_dev->caps.pbl_hop_num == 3) | |
1112 | mr->pbl_bt_l2[i][j] = page_addr; | |
1113 | ||
1114 | j++; | |
2a3d923f | 1115 | if (j >= (pbl_bt_sz / BA_BYTE_LEN)) { |
3856ec55 SS |
1116 | i++; |
1117 | j = 0; | |
ff795f71 WHX |
1118 | } |
1119 | } | |
9a443537 | 1120 | } |
1121 | ||
1122 | /* Memory barrier */ | |
1123 | mb(); | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
1129 | u64 virt_addr, int access_flags, | |
1130 | struct ib_udata *udata) | |
1131 | { | |
1132 | struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); | |
13ca970e | 1133 | struct device *dev = hr_dev->dev; |
ff795f71 WHX |
1134 | struct hns_roce_mr *mr; |
1135 | int bt_size; | |
1136 | int ret; | |
1137 | int n; | |
1138 | int i; | |
9a443537 | 1139 | |
1140 | mr = kmalloc(sizeof(*mr), GFP_KERNEL); | |
1141 | if (!mr) | |
1142 | return ERR_PTR(-ENOMEM); | |
1143 | ||
c320e527 | 1144 | mr->umem = ib_umem_get(pd->device, start, length, access_flags); |
9a443537 | 1145 | if (IS_ERR(mr->umem)) { |
1146 | ret = PTR_ERR(mr->umem); | |
1147 | goto err_free; | |
1148 | } | |
1149 | ||
1150 | n = ib_umem_page_count(mr->umem); | |
9a443537 | 1151 | |
ff795f71 WHX |
1152 | if (!hr_dev->caps.pbl_hop_num) { |
1153 | if (n > HNS_ROCE_MAX_MTPT_PBL_NUM) { | |
1154 | dev_err(dev, | |
1155 | " MR len %lld err. MR is limited to 4G at most!\n", | |
1156 | length); | |
1157 | ret = -EINVAL; | |
1158 | goto err_umem; | |
1159 | } | |
1160 | } else { | |
4af07f01 | 1161 | u64 pbl_size = 1; |
ff795f71 | 1162 | |
2a3d923f LO |
1163 | bt_size = (1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT)) / |
1164 | BA_BYTE_LEN; | |
ff795f71 WHX |
1165 | for (i = 0; i < hr_dev->caps.pbl_hop_num; i++) |
1166 | pbl_size *= bt_size; | |
1167 | if (n > pbl_size) { | |
1168 | dev_err(dev, | |
4af07f01 | 1169 | " MR len %lld err. MR page num is limited to %lld!\n", |
ff795f71 WHX |
1170 | length, pbl_size); |
1171 | ret = -EINVAL; | |
1172 | goto err_umem; | |
1173 | } | |
9a443537 | 1174 | } |
1175 | ||
68a997c5 YL |
1176 | mr->type = MR_TYPE_MR; |
1177 | ||
9a443537 | 1178 | ret = hns_roce_mr_alloc(hr_dev, to_hr_pd(pd)->pdn, virt_addr, length, |
1179 | access_flags, n, mr); | |
1180 | if (ret) | |
1181 | goto err_umem; | |
1182 | ||
ff795f71 | 1183 | ret = hns_roce_ib_umem_write_mr(hr_dev, mr, mr->umem); |
9a443537 | 1184 | if (ret) |
1185 | goto err_mr; | |
1186 | ||
1187 | ret = hns_roce_mr_enable(hr_dev, mr); | |
1188 | if (ret) | |
1189 | goto err_mr; | |
1190 | ||
1191 | mr->ibmr.rkey = mr->ibmr.lkey = mr->key; | |
1192 | ||
1193 | return &mr->ibmr; | |
1194 | ||
1195 | err_mr: | |
1196 | hns_roce_mr_free(hr_dev, mr); | |
1197 | ||
1198 | err_umem: | |
1199 | ib_umem_release(mr->umem); | |
1200 | ||
1201 | err_free: | |
1202 | kfree(mr); | |
1203 | return ERR_PTR(ret); | |
1204 | } | |
1205 | ||
3ee0e170 LO |
1206 | static int rereg_mr_trans(struct ib_mr *ibmr, int flags, |
1207 | u64 start, u64 length, | |
1208 | u64 virt_addr, int mr_access_flags, | |
1209 | struct hns_roce_cmd_mailbox *mailbox, | |
1210 | u32 pdn, struct ib_udata *udata) | |
1211 | { | |
1212 | struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device); | |
1213 | struct hns_roce_mr *mr = to_hr_mr(ibmr); | |
1214 | struct device *dev = hr_dev->dev; | |
1215 | int npages; | |
1216 | int ret; | |
1217 | ||
1218 | if (mr->size != ~0ULL) { | |
1219 | npages = ib_umem_page_count(mr->umem); | |
1220 | ||
1221 | if (hr_dev->caps.pbl_hop_num) | |
1222 | hns_roce_mhop_free(hr_dev, mr); | |
1223 | else | |
1224 | dma_free_coherent(dev, npages * 8, | |
1225 | mr->pbl_buf, mr->pbl_dma_addr); | |
1226 | } | |
1227 | ib_umem_release(mr->umem); | |
1228 | ||
c320e527 | 1229 | mr->umem = ib_umem_get(ibmr->device, start, length, mr_access_flags); |
3ee0e170 LO |
1230 | if (IS_ERR(mr->umem)) { |
1231 | ret = PTR_ERR(mr->umem); | |
1232 | mr->umem = NULL; | |
1233 | return -ENOMEM; | |
1234 | } | |
1235 | npages = ib_umem_page_count(mr->umem); | |
1236 | ||
1237 | if (hr_dev->caps.pbl_hop_num) { | |
1238 | ret = hns_roce_mhop_alloc(hr_dev, npages, mr); | |
1239 | if (ret) | |
1240 | goto release_umem; | |
1241 | } else { | |
1242 | mr->pbl_buf = dma_alloc_coherent(dev, npages * 8, | |
1243 | &(mr->pbl_dma_addr), | |
1244 | GFP_KERNEL); | |
1245 | if (!mr->pbl_buf) { | |
1246 | ret = -ENOMEM; | |
1247 | goto release_umem; | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | ret = hr_dev->hw->rereg_write_mtpt(hr_dev, mr, flags, pdn, | |
1252 | mr_access_flags, virt_addr, | |
1253 | length, mailbox->buf); | |
1254 | if (ret) | |
1255 | goto release_umem; | |
1256 | ||
1257 | ||
1258 | ret = hns_roce_ib_umem_write_mr(hr_dev, mr, mr->umem); | |
1259 | if (ret) { | |
1260 | if (mr->size != ~0ULL) { | |
1261 | npages = ib_umem_page_count(mr->umem); | |
1262 | ||
1263 | if (hr_dev->caps.pbl_hop_num) | |
1264 | hns_roce_mhop_free(hr_dev, mr); | |
1265 | else | |
1266 | dma_free_coherent(dev, npages * 8, | |
1267 | mr->pbl_buf, | |
1268 | mr->pbl_dma_addr); | |
1269 | } | |
1270 | ||
1271 | goto release_umem; | |
1272 | } | |
1273 | ||
1274 | return 0; | |
1275 | ||
1276 | release_umem: | |
1277 | ib_umem_release(mr->umem); | |
1278 | return ret; | |
1279 | ||
1280 | } | |
1281 | ||
1282 | ||
a2c80b7b WHX |
1283 | int hns_roce_rereg_user_mr(struct ib_mr *ibmr, int flags, u64 start, u64 length, |
1284 | u64 virt_addr, int mr_access_flags, struct ib_pd *pd, | |
1285 | struct ib_udata *udata) | |
1286 | { | |
1287 | struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device); | |
1288 | struct hns_roce_mr *mr = to_hr_mr(ibmr); | |
1289 | struct hns_roce_cmd_mailbox *mailbox; | |
1290 | struct device *dev = hr_dev->dev; | |
1291 | unsigned long mtpt_idx; | |
1292 | u32 pdn = 0; | |
a2c80b7b WHX |
1293 | int ret; |
1294 | ||
1295 | if (!mr->enabled) | |
1296 | return -EINVAL; | |
1297 | ||
1298 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
1299 | if (IS_ERR(mailbox)) | |
1300 | return PTR_ERR(mailbox); | |
1301 | ||
1302 | mtpt_idx = key_to_hw_index(mr->key) & (hr_dev->caps.num_mtpts - 1); | |
1303 | ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, mtpt_idx, 0, | |
1304 | HNS_ROCE_CMD_QUERY_MPT, | |
1305 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
1306 | if (ret) | |
1307 | goto free_cmd_mbox; | |
1308 | ||
6eef5242 | 1309 | ret = hns_roce_hw_destroy_mpt(hr_dev, NULL, mtpt_idx); |
a2c80b7b | 1310 | if (ret) |
6eef5242 | 1311 | dev_warn(dev, "DESTROY_MPT failed (%d)\n", ret); |
a2c80b7b WHX |
1312 | |
1313 | mr->enabled = 0; | |
1314 | ||
1315 | if (flags & IB_MR_REREG_PD) | |
1316 | pdn = to_hr_pd(pd)->pdn; | |
1317 | ||
1318 | if (flags & IB_MR_REREG_TRANS) { | |
3ee0e170 LO |
1319 | ret = rereg_mr_trans(ibmr, flags, |
1320 | start, length, | |
1321 | virt_addr, mr_access_flags, | |
1322 | mailbox, pdn, udata); | |
1323 | if (ret) | |
a2c80b7b | 1324 | goto free_cmd_mbox; |
3ee0e170 LO |
1325 | } else { |
1326 | ret = hr_dev->hw->rereg_write_mtpt(hr_dev, mr, flags, pdn, | |
1327 | mr_access_flags, virt_addr, | |
1328 | length, mailbox->buf); | |
1329 | if (ret) | |
a2c80b7b WHX |
1330 | goto free_cmd_mbox; |
1331 | } | |
1332 | ||
6eef5242 | 1333 | ret = hns_roce_hw_create_mpt(hr_dev, mailbox, mtpt_idx); |
a2c80b7b | 1334 | if (ret) { |
6eef5242 | 1335 | dev_err(dev, "CREATE_MPT failed (%d)\n", ret); |
3ee0e170 LO |
1336 | ib_umem_release(mr->umem); |
1337 | goto free_cmd_mbox; | |
a2c80b7b WHX |
1338 | } |
1339 | ||
1340 | mr->enabled = 1; | |
1341 | if (flags & IB_MR_REREG_ACCESS) | |
1342 | mr->access = mr_access_flags; | |
1343 | ||
1344 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
1345 | ||
1346 | return 0; | |
1347 | ||
a2c80b7b WHX |
1348 | free_cmd_mbox: |
1349 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
1350 | ||
1351 | return ret; | |
1352 | } | |
1353 | ||
c4367a26 | 1354 | int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata) |
9a443537 | 1355 | { |
bfcc681b | 1356 | struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device); |
9a443537 | 1357 | struct hns_roce_mr *mr = to_hr_mr(ibmr); |
bfcc681b | 1358 | int ret = 0; |
9a443537 | 1359 | |
bfcc681b | 1360 | if (hr_dev->hw->dereg_mr) { |
c4367a26 | 1361 | ret = hr_dev->hw->dereg_mr(hr_dev, mr, udata); |
bfcc681b SX |
1362 | } else { |
1363 | hns_roce_mr_free(hr_dev, mr); | |
9a443537 | 1364 | |
836a0fbb | 1365 | ib_umem_release(mr->umem); |
bfcc681b SX |
1366 | kfree(mr); |
1367 | } | |
1368 | ||
1369 | return ret; | |
9a443537 | 1370 | } |
c7c28191 | 1371 | |
68a997c5 | 1372 | struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
c4367a26 | 1373 | u32 max_num_sg, struct ib_udata *udata) |
68a997c5 YL |
1374 | { |
1375 | struct hns_roce_dev *hr_dev = to_hr_dev(pd->device); | |
1376 | struct device *dev = hr_dev->dev; | |
1377 | struct hns_roce_mr *mr; | |
1378 | u64 length; | |
1379 | u32 page_size; | |
1380 | int ret; | |
1381 | ||
1382 | page_size = 1 << (hr_dev->caps.pbl_buf_pg_sz + PAGE_SHIFT); | |
1383 | length = max_num_sg * page_size; | |
1384 | ||
1385 | if (mr_type != IB_MR_TYPE_MEM_REG) | |
1386 | return ERR_PTR(-EINVAL); | |
1387 | ||
1388 | if (max_num_sg > HNS_ROCE_FRMR_MAX_PA) { | |
1389 | dev_err(dev, "max_num_sg larger than %d\n", | |
1390 | HNS_ROCE_FRMR_MAX_PA); | |
1391 | return ERR_PTR(-EINVAL); | |
1392 | } | |
1393 | ||
1394 | mr = kzalloc(sizeof(*mr), GFP_KERNEL); | |
1395 | if (!mr) | |
1396 | return ERR_PTR(-ENOMEM); | |
1397 | ||
1398 | mr->type = MR_TYPE_FRMR; | |
1399 | ||
1400 | /* Allocate memory region key */ | |
1401 | ret = hns_roce_mr_alloc(hr_dev, to_hr_pd(pd)->pdn, 0, length, | |
1402 | 0, max_num_sg, mr); | |
1403 | if (ret) | |
1404 | goto err_free; | |
1405 | ||
1406 | ret = hns_roce_mr_enable(hr_dev, mr); | |
1407 | if (ret) | |
1408 | goto err_mr; | |
1409 | ||
1410 | mr->ibmr.rkey = mr->ibmr.lkey = mr->key; | |
1411 | mr->umem = NULL; | |
1412 | ||
1413 | return &mr->ibmr; | |
1414 | ||
1415 | err_mr: | |
1416 | hns_roce_mr_free(to_hr_dev(pd->device), mr); | |
1417 | ||
1418 | err_free: | |
1419 | kfree(mr); | |
1420 | return ERR_PTR(ret); | |
1421 | } | |
1422 | ||
1423 | static int hns_roce_set_page(struct ib_mr *ibmr, u64 addr) | |
1424 | { | |
1425 | struct hns_roce_mr *mr = to_hr_mr(ibmr); | |
1426 | ||
bfe86035 | 1427 | mr->pbl_buf[mr->npages++] = addr; |
68a997c5 YL |
1428 | |
1429 | return 0; | |
1430 | } | |
1431 | ||
1432 | int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, | |
1433 | unsigned int *sg_offset) | |
1434 | { | |
1435 | struct hns_roce_mr *mr = to_hr_mr(ibmr); | |
1436 | ||
1437 | mr->npages = 0; | |
1438 | ||
1439 | return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, hns_roce_set_page); | |
1440 | } | |
1441 | ||
c7c28191 YL |
1442 | static void hns_roce_mw_free(struct hns_roce_dev *hr_dev, |
1443 | struct hns_roce_mw *mw) | |
1444 | { | |
1445 | struct device *dev = hr_dev->dev; | |
1446 | int ret; | |
1447 | ||
1448 | if (mw->enabled) { | |
6eef5242 YL |
1449 | ret = hns_roce_hw_destroy_mpt(hr_dev, NULL, |
1450 | key_to_hw_index(mw->rkey) & | |
1451 | (hr_dev->caps.num_mtpts - 1)); | |
c7c28191 | 1452 | if (ret) |
6eef5242 | 1453 | dev_warn(dev, "MW DESTROY_MPT failed (%d)\n", ret); |
c7c28191 YL |
1454 | |
1455 | hns_roce_table_put(hr_dev, &hr_dev->mr_table.mtpt_table, | |
1456 | key_to_hw_index(mw->rkey)); | |
1457 | } | |
1458 | ||
1459 | hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap, | |
1460 | key_to_hw_index(mw->rkey), BITMAP_NO_RR); | |
1461 | } | |
1462 | ||
1463 | static int hns_roce_mw_enable(struct hns_roce_dev *hr_dev, | |
1464 | struct hns_roce_mw *mw) | |
1465 | { | |
1466 | struct hns_roce_mr_table *mr_table = &hr_dev->mr_table; | |
1467 | struct hns_roce_cmd_mailbox *mailbox; | |
1468 | struct device *dev = hr_dev->dev; | |
1469 | unsigned long mtpt_idx = key_to_hw_index(mw->rkey); | |
1470 | int ret; | |
1471 | ||
1472 | /* prepare HEM entry memory */ | |
1473 | ret = hns_roce_table_get(hr_dev, &mr_table->mtpt_table, mtpt_idx); | |
1474 | if (ret) | |
1475 | return ret; | |
1476 | ||
1477 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
1478 | if (IS_ERR(mailbox)) { | |
1479 | ret = PTR_ERR(mailbox); | |
1480 | goto err_table; | |
1481 | } | |
1482 | ||
1483 | ret = hr_dev->hw->mw_write_mtpt(mailbox->buf, mw); | |
1484 | if (ret) { | |
1485 | dev_err(dev, "MW write mtpt fail!\n"); | |
1486 | goto err_page; | |
1487 | } | |
1488 | ||
6eef5242 YL |
1489 | ret = hns_roce_hw_create_mpt(hr_dev, mailbox, |
1490 | mtpt_idx & (hr_dev->caps.num_mtpts - 1)); | |
c7c28191 | 1491 | if (ret) { |
6eef5242 | 1492 | dev_err(dev, "MW CREATE_MPT failed (%d)\n", ret); |
c7c28191 YL |
1493 | goto err_page; |
1494 | } | |
1495 | ||
1496 | mw->enabled = 1; | |
1497 | ||
1498 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
1499 | ||
1500 | return 0; | |
1501 | ||
1502 | err_page: | |
1503 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
1504 | ||
1505 | err_table: | |
1506 | hns_roce_table_put(hr_dev, &mr_table->mtpt_table, mtpt_idx); | |
1507 | ||
1508 | return ret; | |
1509 | } | |
1510 | ||
1511 | struct ib_mw *hns_roce_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, | |
1512 | struct ib_udata *udata) | |
1513 | { | |
1514 | struct hns_roce_dev *hr_dev = to_hr_dev(ib_pd->device); | |
1515 | struct hns_roce_mw *mw; | |
1516 | unsigned long index = 0; | |
1517 | int ret; | |
1518 | ||
1519 | mw = kmalloc(sizeof(*mw), GFP_KERNEL); | |
1520 | if (!mw) | |
1521 | return ERR_PTR(-ENOMEM); | |
1522 | ||
1523 | /* Allocate a key for mw from bitmap */ | |
1524 | ret = hns_roce_bitmap_alloc(&hr_dev->mr_table.mtpt_bitmap, &index); | |
1525 | if (ret) | |
1526 | goto err_bitmap; | |
1527 | ||
1528 | mw->rkey = hw_index_to_key(index); | |
1529 | ||
1530 | mw->ibmw.rkey = mw->rkey; | |
1531 | mw->ibmw.type = type; | |
1532 | mw->pdn = to_hr_pd(ib_pd)->pdn; | |
1533 | mw->pbl_hop_num = hr_dev->caps.pbl_hop_num; | |
1534 | mw->pbl_ba_pg_sz = hr_dev->caps.pbl_ba_pg_sz; | |
1535 | mw->pbl_buf_pg_sz = hr_dev->caps.pbl_buf_pg_sz; | |
1536 | ||
1537 | ret = hns_roce_mw_enable(hr_dev, mw); | |
1538 | if (ret) | |
1539 | goto err_mw; | |
1540 | ||
1541 | return &mw->ibmw; | |
1542 | ||
1543 | err_mw: | |
1544 | hns_roce_mw_free(hr_dev, mw); | |
1545 | ||
1546 | err_bitmap: | |
1547 | kfree(mw); | |
1548 | ||
1549 | return ERR_PTR(ret); | |
1550 | } | |
1551 | ||
1552 | int hns_roce_dealloc_mw(struct ib_mw *ibmw) | |
1553 | { | |
1554 | struct hns_roce_dev *hr_dev = to_hr_dev(ibmw->device); | |
1555 | struct hns_roce_mw *mw = to_hr_mw(ibmw); | |
1556 | ||
1557 | hns_roce_mw_free(hr_dev, mw); | |
1558 | kfree(mw); | |
1559 | ||
1560 | return 0; | |
1561 | } | |
38389eaa LO |
1562 | |
1563 | void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift, | |
1564 | int buf_pg_shift) | |
1565 | { | |
3c873161 XW |
1566 | hns_roce_hem_list_init(&mtr->hem_list); |
1567 | mtr->hem_cfg.buf_pg_shift = buf_pg_shift; | |
1568 | mtr->hem_cfg.ba_pg_shift = bt_pg_shift; | |
38389eaa LO |
1569 | } |
1570 | ||
1571 | void hns_roce_mtr_cleanup(struct hns_roce_dev *hr_dev, | |
1572 | struct hns_roce_mtr *mtr) | |
1573 | { | |
1574 | hns_roce_hem_list_release(hr_dev, &mtr->hem_list); | |
1575 | } | |
38389eaa | 1576 | |
3c873161 XW |
1577 | static int mtr_map_region(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, |
1578 | dma_addr_t *pages, struct hns_roce_buf_region *region) | |
38389eaa | 1579 | { |
3c873161 | 1580 | __le64 *mtts; |
38389eaa LO |
1581 | int offset; |
1582 | int count; | |
1583 | int npage; | |
3c873161 | 1584 | u64 addr; |
38389eaa LO |
1585 | int end; |
1586 | int i; | |
1587 | ||
3c873161 XW |
1588 | /* if hopnum is 0, buffer cannot store BAs, so skip write mtt */ |
1589 | if (!region->hopnum) | |
1590 | return 0; | |
1591 | ||
1592 | offset = region->offset; | |
1593 | end = offset + region->count; | |
38389eaa LO |
1594 | npage = 0; |
1595 | while (offset < end) { | |
1596 | mtts = hns_roce_hem_list_find_mtt(hr_dev, &mtr->hem_list, | |
1597 | offset, &count, NULL); | |
1598 | if (!mtts) | |
1599 | return -ENOBUFS; | |
1600 | ||
38389eaa LO |
1601 | for (i = 0; i < count; i++) { |
1602 | if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) | |
3c873161 | 1603 | addr = to_hr_hw_page_addr(pages[npage]); |
38389eaa | 1604 | else |
3c873161 | 1605 | addr = pages[npage]; |
38389eaa | 1606 | |
3c873161 | 1607 | mtts[i] = cpu_to_le64(addr); |
38389eaa LO |
1608 | npage++; |
1609 | } | |
1610 | offset += count; | |
1611 | } | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1617 | dma_addr_t **bufs, struct hns_roce_buf_region *regions, | |
1618 | int region_cnt) | |
1619 | { | |
1620 | struct hns_roce_buf_region *r; | |
1621 | int ret; | |
1622 | int i; | |
1623 | ||
1624 | ret = hns_roce_hem_list_request(hr_dev, &mtr->hem_list, regions, | |
3c873161 | 1625 | region_cnt, mtr->hem_cfg.ba_pg_shift); |
38389eaa LO |
1626 | if (ret) |
1627 | return ret; | |
1628 | ||
3c873161 | 1629 | mtr->hem_cfg.root_ba = mtr->hem_list.root_ba; |
38389eaa LO |
1630 | for (i = 0; i < region_cnt; i++) { |
1631 | r = ®ions[i]; | |
3c873161 | 1632 | ret = mtr_map_region(hr_dev, mtr, bufs[i], r); |
38389eaa LO |
1633 | if (ret) { |
1634 | dev_err(hr_dev->dev, | |
1635 | "write mtr[%d/%d] err %d,offset=%d.\n", | |
1636 | i, region_cnt, ret, r->offset); | |
1637 | goto err_write; | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | return 0; | |
1642 | ||
1643 | err_write: | |
1644 | hns_roce_hem_list_release(hr_dev, &mtr->hem_list); | |
1645 | ||
1646 | return ret; | |
1647 | } | |
1648 | ||
3c873161 XW |
1649 | static inline bool mtr_has_mtt(struct hns_roce_buf_attr *attr) |
1650 | { | |
1651 | int i; | |
1652 | ||
1653 | for (i = 0; i < attr->region_count; i++) | |
1654 | if (attr->region[i].hopnum != HNS_ROCE_HOP_NUM_0 && | |
1655 | attr->region[i].hopnum > 0) | |
1656 | return true; | |
1657 | ||
1658 | /* because the mtr only one root base address, when hopnum is 0 means | |
1659 | * root base address equals the first buffer address, thus all alloced | |
1660 | * memory must in a continuous space accessed by direct mode. | |
1661 | */ | |
1662 | return false; | |
1663 | } | |
1664 | ||
1665 | static inline size_t mtr_bufs_size(struct hns_roce_buf_attr *attr) | |
1666 | { | |
1667 | size_t size = 0; | |
1668 | int i; | |
1669 | ||
1670 | for (i = 0; i < attr->region_count; i++) | |
1671 | size += attr->region[i].size; | |
1672 | ||
1673 | return size; | |
1674 | } | |
1675 | ||
1676 | static inline int mtr_umem_page_count(struct ib_umem *umem, int page_shift) | |
1677 | { | |
1678 | int count = ib_umem_page_count(umem); | |
1679 | ||
1680 | if (page_shift >= PAGE_SHIFT) | |
1681 | count >>= page_shift - PAGE_SHIFT; | |
1682 | else | |
1683 | count <<= PAGE_SHIFT - page_shift; | |
1684 | ||
1685 | return count; | |
1686 | } | |
1687 | ||
1688 | static inline size_t mtr_kmem_direct_size(bool is_direct, size_t alloc_size, | |
1689 | int page_shift) | |
1690 | { | |
1691 | if (is_direct) | |
1692 | return ALIGN(alloc_size, 1 << page_shift); | |
1693 | else | |
1694 | return HNS_HW_DIRECT_PAGE_COUNT << page_shift; | |
1695 | } | |
1696 | ||
1697 | /* | |
1698 | * check the given pages in continuous address space | |
1699 | * Returns 0 on success, or the error page num. | |
1700 | */ | |
1701 | static inline int mtr_check_direct_pages(dma_addr_t *pages, int page_count, | |
1702 | int page_shift) | |
1703 | { | |
1704 | size_t page_size = 1 << page_shift; | |
1705 | int i; | |
1706 | ||
1707 | for (i = 1; i < page_count; i++) | |
1708 | if (pages[i] - pages[i - 1] != page_size) | |
1709 | return i; | |
1710 | ||
1711 | return 0; | |
1712 | } | |
1713 | ||
1714 | static void mtr_free_bufs(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr) | |
1715 | { | |
1716 | /* release user buffers */ | |
1717 | if (mtr->umem) { | |
1718 | ib_umem_release(mtr->umem); | |
1719 | mtr->umem = NULL; | |
1720 | } | |
1721 | ||
1722 | /* release kernel buffers */ | |
1723 | if (mtr->kmem) { | |
1724 | hns_roce_buf_free(hr_dev, mtr->kmem); | |
1725 | kfree(mtr->kmem); | |
1726 | mtr->kmem = NULL; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | static int mtr_alloc_bufs(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1731 | struct hns_roce_buf_attr *buf_attr, bool is_direct, | |
1732 | struct ib_udata *udata, unsigned long user_addr) | |
1733 | { | |
1734 | struct ib_device *ibdev = &hr_dev->ib_dev; | |
1735 | int max_pg_shift = buf_attr->page_shift; | |
1736 | int best_pg_shift = 0; | |
1737 | int all_pg_count = 0; | |
1738 | size_t direct_size; | |
1739 | size_t total_size; | |
1740 | unsigned long tmp; | |
1741 | int ret = 0; | |
1742 | ||
1743 | total_size = mtr_bufs_size(buf_attr); | |
1744 | if (total_size < 1) { | |
1745 | ibdev_err(ibdev, "Failed to check mtr size\n"); | |
1746 | return -EINVAL; | |
1747 | } | |
1748 | ||
1749 | if (udata) { | |
1750 | mtr->kmem = NULL; | |
1751 | mtr->umem = ib_umem_get(ibdev, user_addr, total_size, | |
1752 | buf_attr->user_access); | |
1753 | if (IS_ERR_OR_NULL(mtr->umem)) { | |
1754 | ibdev_err(ibdev, "Failed to get umem, ret %ld\n", | |
1755 | PTR_ERR(mtr->umem)); | |
1756 | return -ENOMEM; | |
1757 | } | |
1758 | if (buf_attr->fixed_page) { | |
1759 | best_pg_shift = max_pg_shift; | |
1760 | } else { | |
1761 | tmp = GENMASK(max_pg_shift, 0); | |
1762 | ret = ib_umem_find_best_pgsz(mtr->umem, tmp, user_addr); | |
1763 | best_pg_shift = (ret <= PAGE_SIZE) ? | |
1764 | PAGE_SHIFT : ilog2(ret); | |
1765 | } | |
1766 | all_pg_count = mtr_umem_page_count(mtr->umem, best_pg_shift); | |
1767 | ret = 0; | |
1768 | } else { | |
1769 | mtr->umem = NULL; | |
1770 | mtr->kmem = kzalloc(sizeof(*mtr->kmem), GFP_KERNEL); | |
1771 | if (!mtr->kmem) { | |
1772 | ibdev_err(ibdev, "Failed to alloc kmem\n"); | |
1773 | return -ENOMEM; | |
1774 | } | |
1775 | direct_size = mtr_kmem_direct_size(is_direct, total_size, | |
1776 | max_pg_shift); | |
1777 | ret = hns_roce_buf_alloc(hr_dev, total_size, direct_size, | |
1778 | mtr->kmem, max_pg_shift); | |
1779 | if (ret) { | |
1780 | ibdev_err(ibdev, "Failed to alloc kmem, ret %d\n", ret); | |
1781 | goto err_alloc_mem; | |
1782 | } else { | |
1783 | best_pg_shift = max_pg_shift; | |
1784 | all_pg_count = mtr->kmem->npages; | |
1785 | } | |
1786 | } | |
1787 | ||
1788 | /* must bigger than minimum hardware page shift */ | |
1789 | if (best_pg_shift < PAGE_ADDR_SHIFT || all_pg_count < 1) { | |
1790 | ret = -EINVAL; | |
1791 | ibdev_err(ibdev, "Failed to check mtr page shift %d count %d\n", | |
1792 | best_pg_shift, all_pg_count); | |
1793 | goto err_alloc_mem; | |
1794 | } | |
1795 | ||
1796 | mtr->hem_cfg.buf_pg_shift = best_pg_shift; | |
1797 | mtr->hem_cfg.buf_pg_count = all_pg_count; | |
1798 | ||
1799 | return 0; | |
1800 | err_alloc_mem: | |
1801 | mtr_free_bufs(hr_dev, mtr); | |
1802 | return ret; | |
1803 | } | |
1804 | ||
1805 | static int mtr_get_pages(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1806 | dma_addr_t *pages, int count, int page_shift) | |
1807 | { | |
1808 | struct ib_device *ibdev = &hr_dev->ib_dev; | |
1809 | int npage; | |
1810 | int err; | |
1811 | ||
1812 | if (mtr->umem) | |
1813 | npage = hns_roce_get_umem_bufs(hr_dev, pages, count, 0, | |
1814 | mtr->umem, page_shift); | |
1815 | else | |
1816 | npage = hns_roce_get_kmem_bufs(hr_dev, pages, count, 0, | |
1817 | mtr->kmem); | |
1818 | ||
1819 | if (mtr->hem_cfg.is_direct && npage > 1) { | |
1820 | err = mtr_check_direct_pages(pages, npage, page_shift); | |
1821 | if (err) { | |
1822 | ibdev_err(ibdev, "Failed to check %s direct page-%d\n", | |
1823 | mtr->umem ? "user" : "kernel", err); | |
1824 | npage = err; | |
1825 | } | |
1826 | } | |
1827 | ||
1828 | return npage; | |
1829 | } | |
1830 | ||
1831 | int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1832 | struct hns_roce_buf_region *regions, int region_cnt, | |
1833 | dma_addr_t *pages, int page_cnt) | |
1834 | { | |
1835 | struct ib_device *ibdev = &hr_dev->ib_dev; | |
1836 | struct hns_roce_buf_region *r; | |
1837 | int err; | |
1838 | int i; | |
1839 | ||
1840 | for (i = 0; i < region_cnt; i++) { | |
1841 | r = ®ions[i]; | |
1842 | if (r->offset + r->count > page_cnt) { | |
1843 | err = -EINVAL; | |
1844 | ibdev_err(ibdev, | |
1845 | "Failed to check mtr%d end %d + %d, max %d\n", | |
1846 | i, r->offset, r->count, page_cnt); | |
1847 | return err; | |
1848 | } | |
1849 | ||
1850 | err = mtr_map_region(hr_dev, mtr, &pages[r->offset], r); | |
1851 | if (err) { | |
1852 | ibdev_err(ibdev, | |
1853 | "Failed to map mtr%d offset %d, err %d\n", | |
1854 | i, r->offset, err); | |
1855 | return err; | |
1856 | } | |
1857 | } | |
1858 | ||
1859 | return 0; | |
1860 | } | |
1861 | ||
38389eaa LO |
1862 | int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, |
1863 | int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr) | |
1864 | { | |
38389eaa LO |
1865 | int mtt_count; |
1866 | int total = 0; | |
3c873161 | 1867 | __le64 *mtts; |
38389eaa | 1868 | int npage; |
3c873161 | 1869 | u64 addr; |
38389eaa LO |
1870 | int left; |
1871 | ||
3c873161 | 1872 | if (!mtt_buf || mtt_max < 1) |
38389eaa LO |
1873 | goto done; |
1874 | ||
3c873161 XW |
1875 | /* no mtt memory in direct mode, so just return the buffer address */ |
1876 | if (mtr->hem_cfg.is_direct) { | |
1877 | npage = offset; | |
1878 | for (total = 0; total < mtt_max; total++, npage++) { | |
1879 | addr = mtr->hem_cfg.root_ba + | |
1880 | (npage << mtr->hem_cfg.buf_pg_shift); | |
1881 | ||
1882 | if (hr_dev->hw_rev == HNS_ROCE_HW_VER1) | |
1883 | mtt_buf[total] = to_hr_hw_page_addr(addr); | |
1884 | else | |
1885 | mtt_buf[total] = addr; | |
1886 | } | |
1887 | ||
1888 | goto done; | |
1889 | } | |
1890 | ||
38389eaa LO |
1891 | left = mtt_max; |
1892 | while (left > 0) { | |
1893 | mtt_count = 0; | |
3c873161 | 1894 | mtts = hns_roce_hem_list_find_mtt(hr_dev, &mtr->hem_list, |
38389eaa LO |
1895 | offset + total, |
1896 | &mtt_count, NULL); | |
3c873161 | 1897 | if (!mtts || !mtt_count) |
38389eaa LO |
1898 | goto done; |
1899 | ||
1900 | npage = min(mtt_count, left); | |
38389eaa | 1901 | left -= npage; |
3c873161 XW |
1902 | for (mtt_count = 0; mtt_count < npage; mtt_count++) |
1903 | mtt_buf[total++] = le64_to_cpu(mtts[mtt_count]); | |
38389eaa LO |
1904 | } |
1905 | ||
1906 | done: | |
1907 | if (base_addr) | |
3c873161 | 1908 | *base_addr = mtr->hem_cfg.root_ba; |
38389eaa LO |
1909 | |
1910 | return total; | |
1911 | } | |
3c873161 XW |
1912 | |
1913 | /* convert buffer size to page index and page count */ | |
1914 | static int mtr_init_region(struct hns_roce_buf_attr *attr, int page_cnt, | |
1915 | struct hns_roce_buf_region *regions, int region_cnt, | |
1916 | int page_shift) | |
1917 | { | |
1918 | unsigned int page_size = 1 << page_shift; | |
1919 | int max_region = attr->region_count; | |
1920 | struct hns_roce_buf_region *r; | |
1921 | int page_idx = 0; | |
1922 | int i = 0; | |
1923 | ||
1924 | for (; i < region_cnt && i < max_region && page_idx < page_cnt; i++) { | |
1925 | r = ®ions[i]; | |
1926 | r->hopnum = attr->region[i].hopnum == HNS_ROCE_HOP_NUM_0 ? | |
1927 | 0 : attr->region[i].hopnum; | |
1928 | r->offset = page_idx; | |
1929 | r->count = DIV_ROUND_UP(attr->region[i].size, page_size); | |
1930 | page_idx += r->count; | |
1931 | } | |
1932 | ||
1933 | return i; | |
1934 | } | |
1935 | ||
1936 | /** | |
1937 | * hns_roce_mtr_create - Create hns memory translate region. | |
1938 | * | |
1939 | * @mtr: memory translate region | |
1940 | * @init_attr: init attribute for creating mtr | |
1941 | * @page_shift: page shift for multi-hop base address table | |
1942 | * @udata: user space context, if it's NULL, means kernel space | |
1943 | * @user_addr: userspace virtual address to start at | |
1944 | * @buf_alloced: mtr has private buffer, true means need to alloc | |
1945 | */ | |
1946 | int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1947 | struct hns_roce_buf_attr *buf_attr, int page_shift, | |
1948 | struct ib_udata *udata, unsigned long user_addr) | |
1949 | { | |
1950 | struct hns_roce_buf_region regions[HNS_ROCE_MAX_BT_REGION] = {}; | |
1951 | struct ib_device *ibdev = &hr_dev->ib_dev; | |
1952 | dma_addr_t *pages = NULL; | |
1953 | int region_cnt = 0; | |
1954 | int all_pg_cnt; | |
1955 | int get_pg_cnt; | |
1956 | bool has_mtt; | |
1957 | int err = 0; | |
1958 | ||
1959 | has_mtt = mtr_has_mtt(buf_attr); | |
1960 | /* if buffer only need mtt, just init the hem cfg */ | |
1961 | if (buf_attr->mtt_only) { | |
1962 | mtr->hem_cfg.buf_pg_shift = buf_attr->page_shift; | |
1963 | mtr->hem_cfg.buf_pg_count = mtr_bufs_size(buf_attr) >> | |
1964 | buf_attr->page_shift; | |
1965 | mtr->umem = NULL; | |
1966 | mtr->kmem = NULL; | |
1967 | } else { | |
1968 | err = mtr_alloc_bufs(hr_dev, mtr, buf_attr, !has_mtt, udata, | |
1969 | user_addr); | |
1970 | if (err) { | |
1971 | ibdev_err(ibdev, "Failed to alloc mtr bufs, err %d\n", | |
1972 | err); | |
1973 | return err; | |
1974 | } | |
1975 | } | |
1976 | ||
1977 | /* alloc mtt memory */ | |
1978 | all_pg_cnt = mtr->hem_cfg.buf_pg_count; | |
1979 | hns_roce_hem_list_init(&mtr->hem_list); | |
1980 | mtr->hem_cfg.is_direct = !has_mtt; | |
1981 | mtr->hem_cfg.ba_pg_shift = page_shift; | |
1982 | if (has_mtt) { | |
1983 | region_cnt = mtr_init_region(buf_attr, all_pg_cnt, | |
1984 | regions, ARRAY_SIZE(regions), | |
1985 | mtr->hem_cfg.buf_pg_shift); | |
1986 | if (region_cnt < 1) { | |
1987 | err = -ENOBUFS; | |
1988 | ibdev_err(ibdev, "Failed to init mtr region %d\n", | |
1989 | region_cnt); | |
1990 | goto err_alloc_bufs; | |
1991 | } | |
1992 | err = hns_roce_hem_list_request(hr_dev, &mtr->hem_list, | |
1993 | regions, region_cnt, | |
1994 | page_shift); | |
1995 | if (err) { | |
1996 | ibdev_err(ibdev, "Failed to request mtr hem, err %d\n", | |
1997 | err); | |
1998 | goto err_alloc_bufs; | |
1999 | } | |
2000 | mtr->hem_cfg.root_ba = mtr->hem_list.root_ba; | |
2001 | } | |
2002 | ||
2003 | /* no buffer to map */ | |
2004 | if (buf_attr->mtt_only) | |
2005 | return 0; | |
2006 | ||
2007 | /* alloc a tmp array to store buffer's dma address */ | |
2008 | pages = kvcalloc(all_pg_cnt, sizeof(dma_addr_t), GFP_KERNEL); | |
2009 | if (!pages) { | |
2010 | err = -ENOMEM; | |
2011 | ibdev_err(ibdev, "Failed to alloc mtr page list %d\n", | |
2012 | all_pg_cnt); | |
2013 | goto err_alloc_hem_list; | |
2014 | } | |
2015 | ||
2016 | get_pg_cnt = mtr_get_pages(hr_dev, mtr, pages, all_pg_cnt, | |
2017 | mtr->hem_cfg.buf_pg_shift); | |
2018 | if (get_pg_cnt != all_pg_cnt) { | |
2019 | ibdev_err(ibdev, "Failed to get mtr page %d != %d\n", | |
2020 | get_pg_cnt, all_pg_cnt); | |
2021 | err = -ENOBUFS; | |
2022 | goto err_alloc_page_list; | |
2023 | } | |
2024 | ||
2025 | if (!has_mtt) { | |
2026 | mtr->hem_cfg.root_ba = pages[0]; | |
2027 | } else { | |
2028 | /* write buffer's dma address to BA table */ | |
2029 | err = hns_roce_mtr_map(hr_dev, mtr, regions, region_cnt, pages, | |
2030 | all_pg_cnt); | |
2031 | if (err) { | |
2032 | ibdev_err(ibdev, "Failed to map mtr pages, err %d\n", | |
2033 | err); | |
2034 | goto err_alloc_page_list; | |
2035 | } | |
2036 | } | |
2037 | ||
2038 | /* drop tmp array */ | |
2039 | kvfree(pages); | |
2040 | return 0; | |
2041 | err_alloc_page_list: | |
2042 | kvfree(pages); | |
2043 | err_alloc_hem_list: | |
2044 | hns_roce_hem_list_release(hr_dev, &mtr->hem_list); | |
2045 | err_alloc_bufs: | |
2046 | mtr_free_bufs(hr_dev, mtr); | |
2047 | return err; | |
2048 | } | |
2049 | ||
2050 | void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr) | |
2051 | { | |
2052 | /* release multi-hop addressing resource */ | |
2053 | hns_roce_hem_list_release(hr_dev, &mtr->hem_list); | |
2054 | ||
2055 | /* free buffers */ | |
2056 | mtr_free_bufs(hr_dev, mtr); | |
2057 | } |