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a04ff739 WHX |
1 | /* |
2 | * Copyright (c) 2016-2017 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef _HNS_ROCE_HW_V2_H | |
34 | #define _HNS_ROCE_HW_V2_H | |
35 | ||
cfc85f3e WHX |
36 | #include <linux/bitops.h> |
37 | ||
38 | #define HNS_ROCE_VF_QPC_BT_NUM 256 | |
6a157f7d | 39 | #define HNS_ROCE_VF_SCCC_BT_NUM 64 |
cfc85f3e WHX |
40 | #define HNS_ROCE_VF_SRQC_BT_NUM 64 |
41 | #define HNS_ROCE_VF_CQC_BT_NUM 64 | |
42 | #define HNS_ROCE_VF_MPT_BT_NUM 64 | |
43 | #define HNS_ROCE_VF_EQC_NUM 64 | |
44 | #define HNS_ROCE_VF_SMAC_NUM 32 | |
45 | #define HNS_ROCE_VF_SGID_NUM 32 | |
46 | #define HNS_ROCE_VF_SL_NUM 8 | |
47 | ||
48 | #define HNS_ROCE_V2_MAX_QP_NUM 0x2000 | |
0e40dc2f | 49 | #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200 |
cfc85f3e | 50 | #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000 |
d16da119 LO |
51 | #define HNS_ROCE_V2_MAX_SRQ 0x100000 |
52 | #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000 | |
53 | #define HNS_ROCE_V2_MAX_SRQ_SGE 0x100 | |
cfc85f3e | 54 | #define HNS_ROCE_V2_MAX_CQ_NUM 0x8000 |
0e40dc2f | 55 | #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100 |
5c1f167a | 56 | #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000 |
3180236c | 57 | #define HNS_ROCE_V2_MAX_CQE_NUM 0x10000 |
5c1f167a | 58 | #define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000 |
cfc85f3e WHX |
59 | #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100 |
60 | #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff | |
5c1f167a | 61 | #define HNS_ROCE_V2_MAX_SRQ_SGE_NUM 0x100 |
05ad5482 | 62 | #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000 |
cfc85f3e WHX |
63 | #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 |
64 | #define HNS_ROCE_V2_UAR_NUM 256 | |
65 | #define HNS_ROCE_V2_PHY_UAR_NUM 1 | |
a5073d60 YL |
66 | #define HNS_ROCE_V2_MAX_IRQ_NUM 65 |
67 | #define HNS_ROCE_V2_COMP_VEC_NUM 63 | |
68 | #define HNS_ROCE_V2_AEQE_VEC_NUM 1 | |
69 | #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1 | |
cfc85f3e | 70 | #define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000 |
3180236c WHX |
71 | #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000 |
72 | #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000 | |
5c1f167a LO |
73 | #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000 |
74 | #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000 | |
3180236c | 75 | #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 |
cfc85f3e WHX |
76 | #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 |
77 | #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 | |
78 | #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 | |
79 | #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16 | |
80 | #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64 | |
81 | #define HNS_ROCE_V2_QPC_ENTRY_SZ 256 | |
82 | #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64 | |
e92f2c18 | 83 | #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48 |
cfc85f3e | 84 | #define HNS_ROCE_V2_CQC_ENTRY_SZ 64 |
5c1f167a | 85 | #define HNS_ROCE_V2_SRQC_ENTRY_SZ 64 |
cfc85f3e WHX |
86 | #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64 |
87 | #define HNS_ROCE_V2_MTT_ENTRY_SZ 64 | |
88 | #define HNS_ROCE_V2_CQE_ENTRY_SIZE 32 | |
6a157f7d | 89 | #define HNS_ROCE_V2_SCCC_ENTRY_SZ 32 |
0e40dc2f YL |
90 | #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ 4096 |
91 | #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ 4096 | |
cfc85f3e WHX |
92 | #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 |
93 | #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 | |
2d407888 | 94 | #define HNS_ROCE_INVALID_LKEY 0x100 |
d59fcacc | 95 | #define HNS_ROCE_CMQ_TX_TIMEOUT 30000 |
0b25c9cc | 96 | #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2 |
06ef0ee4 | 97 | #define HNS_ROCE_V2_RSV_QPS 8 |
a04ff739 | 98 | |
a25d13cb | 99 | #define HNS_ROCE_CONTEXT_HOP_NUM 1 |
6a157f7d | 100 | #define HNS_ROCE_SCCC_HOP_NUM 1 |
a25d13cb | 101 | #define HNS_ROCE_MTT_HOP_NUM 1 |
6a93c77a | 102 | #define HNS_ROCE_CQE_HOP_NUM 1 |
c7bcb134 | 103 | #define HNS_ROCE_SRQWQE_HOP_NUM 1 |
ff795f71 | 104 | #define HNS_ROCE_PBL_HOP_NUM 2 |
a5073d60 | 105 | #define HNS_ROCE_EQE_HOP_NUM 2 |
c7bcb134 | 106 | #define HNS_ROCE_IDX_HOP_NUM 1 |
a5073d60 | 107 | |
b5ff0f61 | 108 | #define HNS_ROCE_V2_GID_INDEX_NUM 256 |
a25d13cb | 109 | |
29a1fe5d WHX |
110 | #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18) |
111 | ||
a04ff739 WHX |
112 | #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0 |
113 | #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1 | |
114 | #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2 | |
115 | #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3 | |
116 | #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4 | |
117 | #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5 | |
118 | ||
119 | #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT) | |
120 | #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT) | |
121 | #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT) | |
122 | #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT) | |
123 | #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT) | |
124 | #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT) | |
125 | ||
126 | #define HNS_ROCE_CMQ_DESC_NUM_S 3 | |
127 | #define HNS_ROCE_CMQ_EN_B 16 | |
128 | #define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B) | |
129 | ||
aa84fa18 YL |
130 | #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5 |
131 | ||
a81fba28 WHX |
132 | #define check_whether_last_step(hop_num, step_idx) \ |
133 | ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \ | |
134 | (step_idx == 1 && hop_num == 1) || \ | |
135 | (step_idx == 2 && hop_num == 2)) | |
0c1c3880 LO |
136 | #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0 |
137 | #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT) | |
a81fba28 | 138 | |
426c4146 LO |
139 | #define CMD_CSQ_DESC_NUM 1024 |
140 | #define CMD_CRQ_DESC_NUM 1024 | |
141 | ||
a5073d60 YL |
142 | enum { |
143 | NO_ARMED = 0x0, | |
144 | REG_NXT_CEQE = 0x2, | |
145 | REG_NXT_SE_CEQE = 0x3 | |
146 | }; | |
147 | ||
93aa2187 WHX |
148 | #define V2_CQ_DB_REQ_NOT_SOL 0 |
149 | #define V2_CQ_DB_REQ_NOT 1 | |
150 | ||
151 | #define V2_CQ_STATE_VALID 1 | |
926a01dc WHX |
152 | #define V2_QKEY_VAL 0x80010000 |
153 | ||
154 | #define GID_LEN_V2 16 | |
93aa2187 WHX |
155 | |
156 | #define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff | |
157 | ||
2d407888 WHX |
158 | enum { |
159 | HNS_ROCE_V2_WQE_OP_SEND = 0x0, | |
160 | HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1, | |
161 | HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2, | |
162 | HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3, | |
163 | HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4, | |
164 | HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5, | |
165 | HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6, | |
166 | HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7, | |
167 | HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8, | |
168 | HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9, | |
169 | HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa, | |
170 | HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb, | |
171 | HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc, | |
172 | HNS_ROCE_V2_WQE_OP_MASK = 0x1f, | |
173 | }; | |
174 | ||
93aa2187 WHX |
175 | enum { |
176 | HNS_ROCE_SQ_OPCODE_SEND = 0x0, | |
177 | HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1, | |
178 | HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2, | |
179 | HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3, | |
180 | HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4, | |
181 | HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5, | |
182 | HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6, | |
183 | HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7, | |
184 | HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8, | |
185 | HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9, | |
186 | HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa, | |
187 | HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb, | |
188 | HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc, | |
189 | }; | |
190 | ||
191 | enum { | |
192 | /* rq operations */ | |
193 | HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0, | |
194 | HNS_ROCE_V2_OPCODE_SEND = 0x1, | |
195 | HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2, | |
196 | HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3, | |
197 | }; | |
198 | ||
199 | enum { | |
2d407888 WHX |
200 | HNS_ROCE_V2_SQ_DB = 0x0, |
201 | HNS_ROCE_V2_RQ_DB = 0x1, | |
202 | HNS_ROCE_V2_SRQ_DB = 0x2, | |
93aa2187 WHX |
203 | HNS_ROCE_V2_CQ_DB_PTR = 0x3, |
204 | HNS_ROCE_V2_CQ_DB_NTR = 0x4, | |
205 | }; | |
206 | ||
207 | enum { | |
208 | HNS_ROCE_CQE_V2_SUCCESS = 0x00, | |
209 | HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01, | |
210 | HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02, | |
211 | HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04, | |
212 | HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05, | |
213 | HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06, | |
214 | HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10, | |
215 | HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11, | |
216 | HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12, | |
217 | HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13, | |
218 | HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14, | |
219 | HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15, | |
220 | HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16, | |
221 | HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22, | |
222 | ||
223 | HNS_ROCE_V2_CQE_STATUS_MASK = 0xff, | |
224 | }; | |
225 | ||
a04ff739 WHX |
226 | /* CMQ command */ |
227 | enum hns_roce_opcode_type { | |
3a63c964 | 228 | HNS_QUERY_FW_VER = 0x0001, |
a04ff739 WHX |
229 | HNS_ROCE_OPC_QUERY_HW_VER = 0x8000, |
230 | HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001, | |
231 | HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004, | |
232 | HNS_ROCE_OPC_QUERY_PF_RES = 0x8400, | |
233 | HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401, | |
6b63597d | 234 | HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403, |
ded58ff9 | 235 | HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404, |
0e40dc2f | 236 | HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406, |
4db134a3 | 237 | HNS_ROCE_OPC_CFG_SGID_TB = 0x8500, |
e8e8b652 | 238 | HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501, |
f747b689 LO |
239 | HNS_ROCE_OPC_POST_MB = 0x8504, |
240 | HNS_ROCE_OPC_QUERY_MB_ST = 0x8505, | |
a04ff739 | 241 | HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506, |
aa84fa18 YL |
242 | HNS_ROCE_OPC_CLR_SCCC = 0x8509, |
243 | HNS_ROCE_OPC_QUERY_SCCC = 0x850a, | |
244 | HNS_ROCE_OPC_RESET_SCCC = 0x850b, | |
0c1c3880 | 245 | HNS_SWITCH_PARAMETER_CFG = 0x1033, |
a04ff739 WHX |
246 | }; |
247 | ||
248 | enum { | |
249 | TYPE_CRQ, | |
250 | TYPE_CSQ, | |
251 | }; | |
252 | ||
253 | enum hns_roce_cmd_return_status { | |
254 | CMD_EXEC_SUCCESS = 0, | |
255 | CMD_NO_AUTH = 1, | |
256 | CMD_NOT_EXEC = 2, | |
257 | CMD_QUEUE_FULL = 3, | |
258 | }; | |
259 | ||
b5ff0f61 WHX |
260 | enum hns_roce_sgid_type { |
261 | GID_TYPE_FLAG_ROCE_V1 = 0, | |
262 | GID_TYPE_FLAG_ROCE_V2_IPV4, | |
263 | GID_TYPE_FLAG_ROCE_V2_IPV6, | |
264 | }; | |
265 | ||
93aa2187 | 266 | struct hns_roce_v2_cq_context { |
8b9b8d14 | 267 | __le32 byte_4_pg_ceqn; |
268 | __le32 byte_8_cqn; | |
269 | __le32 cqe_cur_blk_addr; | |
270 | __le32 byte_16_hop_addr; | |
271 | __le32 cqe_nxt_blk_addr; | |
272 | __le32 byte_24_pgsz_addr; | |
273 | __le32 byte_28_cq_pi; | |
274 | __le32 byte_32_cq_ci; | |
275 | __le32 cqe_ba; | |
276 | __le32 byte_40_cqe_ba; | |
277 | __le32 byte_44_db_record; | |
278 | __le32 db_record_addr; | |
279 | __le32 byte_52_cqe_cnt; | |
280 | __le32 byte_56_cqe_period_maxcnt; | |
281 | __le32 cqe_report_timer; | |
282 | __le32 byte_64_se_cqe_idx; | |
93aa2187 | 283 | }; |
a5073d60 YL |
284 | #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0 |
285 | #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0 | |
286 | ||
93aa2187 WHX |
287 | #define V2_CQC_BYTE_4_CQ_ST_S 0 |
288 | #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0) | |
289 | ||
290 | #define V2_CQC_BYTE_4_POLL_S 2 | |
291 | ||
292 | #define V2_CQC_BYTE_4_SE_S 3 | |
293 | ||
294 | #define V2_CQC_BYTE_4_OVER_IGNORE_S 4 | |
295 | ||
296 | #define V2_CQC_BYTE_4_COALESCE_S 5 | |
297 | ||
298 | #define V2_CQC_BYTE_4_ARM_ST_S 6 | |
299 | #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6) | |
300 | ||
301 | #define V2_CQC_BYTE_4_SHIFT_S 8 | |
302 | #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8) | |
303 | ||
304 | #define V2_CQC_BYTE_4_CMD_SN_S 13 | |
305 | #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13) | |
306 | ||
307 | #define V2_CQC_BYTE_4_CEQN_S 15 | |
308 | #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15) | |
309 | ||
310 | #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24 | |
311 | #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24) | |
312 | ||
313 | #define V2_CQC_BYTE_8_CQN_S 0 | |
314 | #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0) | |
315 | ||
316 | #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0 | |
317 | #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0) | |
318 | ||
319 | #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30 | |
320 | #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30) | |
321 | ||
322 | #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0 | |
323 | #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0) | |
324 | ||
325 | #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24 | |
326 | #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24) | |
327 | ||
328 | #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28 | |
329 | #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28) | |
330 | ||
331 | #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0 | |
332 | #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0) | |
333 | ||
334 | #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0 | |
335 | #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0) | |
336 | ||
337 | #define V2_CQC_BYTE_40_CQE_BA_S 0 | |
338 | #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0) | |
339 | ||
340 | #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0 | |
341 | ||
9b44703d YL |
342 | #define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1 |
343 | #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1) | |
344 | ||
93aa2187 WHX |
345 | #define V2_CQC_BYTE_52_CQE_CNT_S 0 |
346 | #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0) | |
347 | ||
348 | #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0 | |
349 | #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0) | |
350 | ||
351 | #define V2_CQC_BYTE_56_CQ_PERIOD_S 16 | |
352 | #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16) | |
353 | ||
354 | #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0 | |
355 | #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0) | |
356 | ||
c7bcb134 LO |
357 | struct hns_roce_srq_context { |
358 | __le32 byte_4_srqn_srqst; | |
359 | __le32 byte_8_limit_wl; | |
360 | __le32 byte_12_xrcd; | |
361 | __le32 byte_16_pi_ci; | |
362 | __le32 wqe_bt_ba; | |
363 | __le32 byte_24_wqe_bt_ba; | |
364 | __le32 byte_28_rqws_pd; | |
365 | __le32 idx_bt_ba; | |
366 | __le32 rsv_idx_bt_ba; | |
367 | __le32 idx_cur_blk_addr; | |
368 | __le32 byte_44_idxbufpgsz_addr; | |
369 | __le32 idx_nxt_blk_addr; | |
370 | __le32 rsv_idxnxtblkaddr; | |
371 | __le32 byte_56_xrc_cqn; | |
372 | __le32 db_record_addr_record_en; | |
373 | __le32 db_record_addr; | |
374 | }; | |
375 | ||
376 | #define SRQC_BYTE_4_SRQ_ST_S 0 | |
377 | #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0) | |
378 | ||
379 | #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2 | |
380 | #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2) | |
381 | ||
382 | #define SRQC_BYTE_4_SRQ_SHIFT_S 4 | |
383 | #define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4) | |
384 | ||
385 | #define SRQC_BYTE_4_SRQN_S 8 | |
386 | #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8) | |
387 | ||
388 | #define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0 | |
389 | #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0) | |
390 | ||
391 | #define SRQC_BYTE_12_SRQ_XRCD_S 0 | |
392 | #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0) | |
393 | ||
394 | #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0 | |
395 | #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0) | |
396 | ||
397 | #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0 | |
398 | #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16) | |
399 | ||
400 | #define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0 | |
401 | #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0) | |
402 | ||
403 | #define SRQC_BYTE_28_PD_S 0 | |
404 | #define SRQC_BYTE_28_PD_M GENMASK(23, 0) | |
405 | ||
406 | #define SRQC_BYTE_28_RQWS_S 24 | |
407 | #define SRQC_BYTE_28_RQWS_M GENMASK(27, 24) | |
408 | ||
409 | #define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0 | |
410 | #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0) | |
411 | ||
412 | #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0 | |
413 | #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0) | |
414 | ||
415 | #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22 | |
416 | #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22) | |
417 | ||
418 | #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24 | |
419 | #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24) | |
420 | ||
421 | #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28 | |
422 | #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28) | |
423 | ||
424 | #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0 | |
425 | #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0) | |
426 | ||
427 | #define SRQC_BYTE_56_SRQ_XRC_CQN_S 0 | |
428 | #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0) | |
429 | ||
430 | #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24 | |
431 | #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24) | |
432 | ||
433 | #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28 | |
434 | #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28) | |
435 | ||
436 | #define SRQC_BYTE_60_SRQ_RECORD_EN_S 0 | |
437 | ||
438 | #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1 | |
439 | #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1) | |
440 | ||
926a01dc WHX |
441 | enum{ |
442 | V2_MPT_ST_VALID = 0x1, | |
c7c28191 | 443 | V2_MPT_ST_FREE = 0x2, |
926a01dc WHX |
444 | }; |
445 | ||
446 | enum hns_roce_v2_qp_state { | |
447 | HNS_ROCE_QP_ST_RST, | |
448 | HNS_ROCE_QP_ST_INIT, | |
449 | HNS_ROCE_QP_ST_RTR, | |
450 | HNS_ROCE_QP_ST_RTS, | |
451 | HNS_ROCE_QP_ST_SQER, | |
452 | HNS_ROCE_QP_ST_SQD, | |
453 | HNS_ROCE_QP_ST_ERR, | |
454 | HNS_ROCE_QP_ST_SQ_DRAINING, | |
455 | HNS_ROCE_QP_NUM_ST | |
456 | }; | |
457 | ||
458 | struct hns_roce_v2_qp_context { | |
8b9b8d14 | 459 | __le32 byte_4_sqpn_tst; |
460 | __le32 wqe_sge_ba; | |
461 | __le32 byte_12_sq_hop; | |
462 | __le32 byte_16_buf_ba_pg_sz; | |
463 | __le32 byte_20_smac_sgid_idx; | |
464 | __le32 byte_24_mtu_tc; | |
465 | __le32 byte_28_at_fl; | |
926a01dc | 466 | u8 dgid[GID_LEN_V2]; |
8b9b8d14 | 467 | __le32 dmac; |
468 | __le32 byte_52_udpspn_dmac; | |
469 | __le32 byte_56_dqpn_err; | |
2362ccee | 470 | __le32 byte_60_qpst_tempid; |
8b9b8d14 | 471 | __le32 qkey_xrcd; |
472 | __le32 byte_68_rq_db; | |
473 | __le32 rq_db_record_addr; | |
474 | __le32 byte_76_srqn_op_en; | |
475 | __le32 byte_80_rnr_rx_cqn; | |
476 | __le32 byte_84_rq_ci_pi; | |
477 | __le32 rq_cur_blk_addr; | |
478 | __le32 byte_92_srq_info; | |
479 | __le32 byte_96_rx_reqmsn; | |
480 | __le32 rq_nxt_blk_addr; | |
481 | __le32 byte_104_rq_sge; | |
482 | __le32 byte_108_rx_reqepsn; | |
483 | __le32 rq_rnr_timer; | |
484 | __le32 rx_msg_len; | |
485 | __le32 rx_rkey_pkt_info; | |
486 | __le64 rx_va; | |
487 | __le32 byte_132_trrl; | |
488 | __le32 trrl_ba; | |
489 | __le32 byte_140_raq; | |
490 | __le32 byte_144_raq; | |
491 | __le32 byte_148_raq; | |
492 | __le32 byte_152_raq; | |
493 | __le32 byte_156_raq; | |
494 | __le32 byte_160_sq_ci_pi; | |
495 | __le32 sq_cur_blk_addr; | |
496 | __le32 byte_168_irrl_idx; | |
497 | __le32 byte_172_sq_psn; | |
498 | __le32 byte_176_msg_pktn; | |
499 | __le32 sq_cur_sge_blk_addr; | |
500 | __le32 byte_184_irrl_idx; | |
501 | __le32 cur_sge_offset; | |
502 | __le32 byte_192_ext_sge; | |
503 | __le32 byte_196_sq_psn; | |
504 | __le32 byte_200_sq_max; | |
505 | __le32 irrl_ba; | |
506 | __le32 byte_208_irrl; | |
507 | __le32 byte_212_lsn; | |
508 | __le32 sq_timer; | |
509 | __le32 byte_220_retry_psn_msn; | |
510 | __le32 byte_224_retry_msg; | |
511 | __le32 rx_sq_cur_blk_addr; | |
512 | __le32 byte_232_irrl_sge; | |
513 | __le32 irrl_cur_sge_offset; | |
514 | __le32 byte_240_irrl_tail; | |
515 | __le32 byte_244_rnr_rxack; | |
516 | __le32 byte_248_ack_psn; | |
517 | __le32 byte_252_err_txcqn; | |
518 | __le32 byte_256_sqflush_rqcqe; | |
926a01dc WHX |
519 | }; |
520 | ||
521 | #define V2_QPC_BYTE_4_TST_S 0 | |
522 | #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0) | |
523 | ||
524 | #define V2_QPC_BYTE_4_SGE_SHIFT_S 3 | |
525 | #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3) | |
526 | ||
527 | #define V2_QPC_BYTE_4_SQPN_S 8 | |
528 | #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8) | |
529 | ||
530 | #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0 | |
531 | #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0) | |
532 | ||
533 | #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29 | |
534 | #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29) | |
535 | ||
536 | #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31 | |
537 | ||
538 | #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0 | |
539 | #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0) | |
540 | ||
541 | #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4 | |
542 | #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4) | |
543 | ||
544 | #define V2_QPC_BYTE_16_PD_S 8 | |
545 | #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8) | |
546 | ||
547 | #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0 | |
548 | #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0) | |
549 | ||
550 | #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2 | |
551 | #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2) | |
552 | ||
553 | #define V2_QPC_BYTE_20_RQWS_S 4 | |
554 | #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4) | |
555 | ||
556 | #define V2_QPC_BYTE_20_SQ_SHIFT_S 8 | |
557 | #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8) | |
558 | ||
559 | #define V2_QPC_BYTE_20_RQ_SHIFT_S 12 | |
560 | #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12) | |
561 | ||
562 | #define V2_QPC_BYTE_20_SGID_IDX_S 16 | |
563 | #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16) | |
564 | ||
565 | #define V2_QPC_BYTE_20_SMAC_IDX_S 24 | |
566 | #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24) | |
567 | ||
568 | #define V2_QPC_BYTE_24_HOP_LIMIT_S 0 | |
569 | #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0) | |
570 | ||
571 | #define V2_QPC_BYTE_24_TC_S 8 | |
572 | #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8) | |
573 | ||
c8e46f8d LO |
574 | #define V2_QPC_BYTE_24_VLAN_ID_S 16 |
575 | #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16) | |
926a01dc WHX |
576 | |
577 | #define V2_QPC_BYTE_24_MTU_S 28 | |
578 | #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28) | |
579 | ||
580 | #define V2_QPC_BYTE_28_FL_S 0 | |
581 | #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0) | |
582 | ||
583 | #define V2_QPC_BYTE_28_SL_S 20 | |
584 | #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20) | |
585 | ||
586 | #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24 | |
587 | ||
588 | #define V2_QPC_BYTE_28_CE_FLAG_S 25 | |
589 | ||
590 | #define V2_QPC_BYTE_28_LBI_S 26 | |
591 | ||
592 | #define V2_QPC_BYTE_28_AT_S 27 | |
593 | #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27) | |
594 | ||
595 | #define V2_QPC_BYTE_52_DMAC_S 0 | |
596 | #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0) | |
597 | ||
598 | #define V2_QPC_BYTE_52_UDPSPN_S 16 | |
599 | #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16) | |
600 | ||
601 | #define V2_QPC_BYTE_56_DQPN_S 0 | |
602 | #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0) | |
603 | ||
604 | #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24 | |
605 | #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25 | |
606 | #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26 | |
607 | #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27 | |
608 | ||
609 | #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28 | |
610 | #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28) | |
611 | ||
2362ccee LO |
612 | #define V2_QPC_BYTE_60_TEMPID_S 0 |
613 | #define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0) | |
926a01dc | 614 | |
2362ccee LO |
615 | #define V2_QPC_BYTE_60_SCC_TOKEN_S 8 |
616 | #define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8) | |
926a01dc | 617 | |
2362ccee | 618 | #define V2_QPC_BYTE_60_SQ_DB_DOING_S 27 |
926a01dc | 619 | |
2362ccee | 620 | #define V2_QPC_BYTE_60_RQ_DB_DOING_S 28 |
926a01dc WHX |
621 | |
622 | #define V2_QPC_BYTE_60_QP_ST_S 29 | |
623 | #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29) | |
624 | ||
625 | #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0 | |
626 | ||
627 | #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1 | |
628 | #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1) | |
629 | ||
630 | #define V2_QPC_BYTE_76_SRQN_S 0 | |
631 | #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0) | |
632 | ||
633 | #define V2_QPC_BYTE_76_SRQ_EN_S 24 | |
634 | ||
635 | #define V2_QPC_BYTE_76_RRE_S 25 | |
636 | ||
637 | #define V2_QPC_BYTE_76_RWE_S 26 | |
638 | ||
639 | #define V2_QPC_BYTE_76_ATE_S 27 | |
640 | ||
641 | #define V2_QPC_BYTE_76_RQIE_S 28 | |
642 | ||
caf3e406 | 643 | #define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30 |
926a01dc WHX |
644 | #define V2_QPC_BYTE_80_RX_CQN_S 0 |
645 | #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0) | |
646 | ||
647 | #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27 | |
648 | #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27) | |
649 | ||
650 | #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0 | |
651 | #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0) | |
652 | ||
653 | #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16 | |
654 | #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16) | |
655 | ||
656 | #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0 | |
657 | #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
658 | ||
659 | #define V2_QPC_BYTE_92_SRQ_INFO_S 20 | |
660 | #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20) | |
661 | ||
662 | #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0 | |
663 | #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0) | |
664 | ||
665 | #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0 | |
666 | #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0) | |
667 | ||
668 | #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24 | |
669 | #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24) | |
670 | ||
671 | #define V2_QPC_BYTE_108_INV_CREDIT_S 0 | |
672 | ||
673 | #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3 | |
674 | ||
675 | #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4 | |
676 | #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4) | |
677 | ||
678 | #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7 | |
679 | ||
680 | #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8 | |
681 | #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8) | |
682 | ||
683 | #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0 | |
684 | #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0) | |
685 | ||
686 | #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8 | |
687 | #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8) | |
688 | ||
689 | #define V2_QPC_BYTE_132_TRRL_BA_S 16 | |
690 | #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16) | |
691 | ||
692 | #define V2_QPC_BYTE_140_TRRL_BA_S 0 | |
693 | #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0) | |
694 | ||
695 | #define V2_QPC_BYTE_140_RR_MAX_S 12 | |
696 | #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12) | |
697 | ||
2362ccee | 698 | #define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15 |
926a01dc WHX |
699 | |
700 | #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16 | |
701 | #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16) | |
702 | ||
703 | #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24 | |
704 | #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24) | |
705 | ||
706 | #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0 | |
707 | #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0) | |
708 | ||
926a01dc WHX |
709 | #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25 |
710 | #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25) | |
711 | ||
712 | #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31 | |
713 | ||
714 | #define V2_QPC_BYTE_148_RQ_MSN_S 0 | |
715 | #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0) | |
716 | ||
717 | #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24 | |
718 | #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24) | |
719 | ||
720 | #define V2_QPC_BYTE_152_RAQ_PSN_S 8 | |
721 | #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(31, 8) | |
722 | ||
723 | #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24 | |
724 | #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24) | |
725 | ||
726 | #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0 | |
727 | #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0) | |
728 | ||
729 | #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0 | |
730 | #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0) | |
731 | ||
732 | #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16 | |
733 | #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16) | |
734 | ||
735 | #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0 | |
736 | #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
737 | ||
738 | #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20 | |
739 | ||
b5fddb7c | 740 | #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21 |
741 | ||
742 | #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22 | |
743 | #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22) | |
926a01dc | 744 | |
caf3e406 | 745 | #define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24 |
2362ccee LO |
746 | #define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25 |
747 | #define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26 | |
748 | #define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27 | |
926a01dc WHX |
749 | #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28 |
750 | #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28) | |
751 | ||
752 | #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0 | |
753 | #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0) | |
754 | ||
755 | #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6 | |
756 | ||
757 | #define V2_QPC_BYTE_172_FRE_S 7 | |
758 | ||
759 | #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8 | |
760 | #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8) | |
761 | ||
762 | #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0 | |
763 | #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0) | |
764 | ||
765 | #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24 | |
766 | #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24) | |
767 | ||
768 | #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0 | |
769 | #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0) | |
770 | ||
771 | #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20 | |
772 | #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20) | |
773 | ||
774 | #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0 | |
775 | #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0) | |
776 | ||
777 | #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24 | |
778 | #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24) | |
779 | ||
780 | #define V2_QPC_BYTE_196_IRRL_HEAD_S 0 | |
781 | #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0) | |
782 | ||
783 | #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8 | |
784 | #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8) | |
785 | ||
786 | #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0 | |
787 | #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0) | |
788 | ||
789 | #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16 | |
790 | #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16) | |
791 | ||
792 | #define V2_QPC_BYTE_208_IRRL_BA_S 0 | |
793 | #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0) | |
794 | ||
795 | #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26 | |
796 | ||
797 | #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27 | |
798 | ||
799 | #define V2_QPC_BYTE_208_RMT_E2E_S 28 | |
800 | ||
801 | #define V2_QPC_BYTE_208_SR_MAX_S 29 | |
802 | #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29) | |
803 | ||
804 | #define V2_QPC_BYTE_212_LSN_S 0 | |
805 | #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0) | |
806 | ||
807 | #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24 | |
808 | #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24) | |
809 | ||
810 | #define V2_QPC_BYTE_212_CHECK_FLG_S 27 | |
811 | #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27) | |
812 | ||
813 | #define V2_QPC_BYTE_212_RETRY_CNT_S 29 | |
814 | #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29) | |
815 | ||
816 | #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0 | |
817 | #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0) | |
818 | ||
819 | #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16 | |
820 | #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16) | |
821 | ||
822 | #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0 | |
823 | #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0) | |
824 | ||
825 | #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8 | |
826 | #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8) | |
827 | ||
828 | #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0 | |
829 | #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
830 | ||
831 | #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20 | |
832 | #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20) | |
833 | ||
2362ccee LO |
834 | #define V2_QPC_BYTE_232_SO_LP_VLD_S 29 |
835 | #define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30 | |
836 | #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31 | |
837 | ||
926a01dc WHX |
838 | #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0 |
839 | #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0) | |
840 | ||
841 | #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8 | |
842 | #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8) | |
843 | ||
844 | #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16 | |
845 | #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16) | |
846 | ||
847 | #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0 | |
848 | #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0) | |
849 | ||
850 | #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24 | |
851 | #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24) | |
852 | ||
853 | #define V2_QPC_BYTE_244_RNR_CNT_S 27 | |
854 | #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27) | |
855 | ||
2362ccee LO |
856 | #define V2_QPC_BYTE_244_LCL_OP_FLG_S 30 |
857 | #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31 | |
858 | ||
926a01dc WHX |
859 | #define V2_QPC_BYTE_248_IRRL_PSN_S 0 |
860 | #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0) | |
861 | ||
862 | #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24 | |
863 | ||
864 | #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25 | |
865 | #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25) | |
866 | ||
867 | #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27 | |
868 | ||
869 | #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28 | |
870 | ||
871 | #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31 | |
872 | ||
873 | #define V2_QPC_BYTE_252_TX_CQN_S 0 | |
874 | #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0) | |
875 | ||
876 | #define V2_QPC_BYTE_252_SIG_TYPE_S 24 | |
877 | ||
878 | #define V2_QPC_BYTE_252_ERR_TYPE_S 25 | |
879 | #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25) | |
880 | ||
881 | #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0 | |
882 | #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0) | |
883 | ||
884 | #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16 | |
885 | #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16) | |
886 | ||
93aa2187 | 887 | struct hns_roce_v2_cqe { |
8b9b8d14 | 888 | __le32 byte_4; |
ccb8a29e JG |
889 | union { |
890 | __le32 rkey; | |
0c4a0e29 | 891 | __le32 immtdata; |
ccb8a29e | 892 | }; |
8b9b8d14 | 893 | __le32 byte_12; |
894 | __le32 byte_16; | |
895 | __le32 byte_cnt; | |
2eade675 | 896 | u8 smac[4]; |
8b9b8d14 | 897 | __le32 byte_28; |
898 | __le32 byte_32; | |
93aa2187 WHX |
899 | }; |
900 | ||
901 | #define V2_CQE_BYTE_4_OPCODE_S 0 | |
902 | #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
903 | ||
904 | #define V2_CQE_BYTE_4_RQ_INLINE_S 5 | |
905 | ||
906 | #define V2_CQE_BYTE_4_S_R_S 6 | |
907 | ||
908 | #define V2_CQE_BYTE_4_OWNER_S 7 | |
909 | ||
910 | #define V2_CQE_BYTE_4_STATUS_S 8 | |
911 | #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8) | |
912 | ||
913 | #define V2_CQE_BYTE_4_WQE_INDX_S 16 | |
914 | #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16) | |
915 | ||
916 | #define V2_CQE_BYTE_12_XRC_SRQN_S 0 | |
917 | #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0) | |
918 | ||
919 | #define V2_CQE_BYTE_16_LCL_QPN_S 0 | |
920 | #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0) | |
921 | ||
922 | #define V2_CQE_BYTE_16_SUB_STATUS_S 24 | |
923 | #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24) | |
924 | ||
925 | #define V2_CQE_BYTE_28_SMAC_4_S 0 | |
926 | #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0) | |
927 | ||
928 | #define V2_CQE_BYTE_28_SMAC_5_S 8 | |
929 | #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8) | |
930 | ||
931 | #define V2_CQE_BYTE_28_PORT_TYPE_S 16 | |
932 | #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16) | |
933 | ||
944e6409 LO |
934 | #define V2_CQE_BYTE_28_VID_S 18 |
935 | #define V2_CQE_BYTE_28_VID_M GENMASK(29, 18) | |
936 | ||
937 | #define V2_CQE_BYTE_28_VID_VLD_S 30 | |
938 | ||
93aa2187 WHX |
939 | #define V2_CQE_BYTE_32_RMT_QPN_S 0 |
940 | #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0) | |
941 | ||
942 | #define V2_CQE_BYTE_32_SL_S 24 | |
943 | #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24) | |
944 | ||
945 | #define V2_CQE_BYTE_32_PORTN_S 27 | |
946 | #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27) | |
947 | ||
948 | #define V2_CQE_BYTE_32_GRH_S 30 | |
949 | ||
950 | #define V2_CQE_BYTE_32_LPK_S 31 | |
951 | ||
3958cc56 WHX |
952 | struct hns_roce_v2_mpt_entry { |
953 | __le32 byte_4_pd_hop_st; | |
954 | __le32 byte_8_mw_cnt_en; | |
955 | __le32 byte_12_mw_pa; | |
956 | __le32 bound_lkey; | |
957 | __le32 len_l; | |
958 | __le32 len_h; | |
959 | __le32 lkey; | |
960 | __le32 va_l; | |
961 | __le32 va_h; | |
962 | __le32 pbl_size; | |
963 | __le32 pbl_ba_l; | |
964 | __le32 byte_48_mode_ba; | |
965 | __le32 pa0_l; | |
966 | __le32 byte_56_pa0_h; | |
967 | __le32 pa1_l; | |
968 | __le32 byte_64_buf_pa1; | |
969 | }; | |
970 | ||
971 | #define V2_MPT_BYTE_4_MPT_ST_S 0 | |
972 | #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0) | |
973 | ||
974 | #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2 | |
975 | #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2) | |
976 | ||
977 | #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4 | |
978 | #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4) | |
979 | ||
980 | #define V2_MPT_BYTE_4_PD_S 8 | |
981 | #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8) | |
982 | ||
983 | #define V2_MPT_BYTE_8_RA_EN_S 0 | |
984 | ||
985 | #define V2_MPT_BYTE_8_R_INV_EN_S 1 | |
986 | ||
987 | #define V2_MPT_BYTE_8_L_INV_EN_S 2 | |
988 | ||
989 | #define V2_MPT_BYTE_8_BIND_EN_S 3 | |
990 | ||
991 | #define V2_MPT_BYTE_8_ATOMIC_EN_S 4 | |
992 | ||
993 | #define V2_MPT_BYTE_8_RR_EN_S 5 | |
994 | ||
995 | #define V2_MPT_BYTE_8_RW_EN_S 6 | |
996 | ||
997 | #define V2_MPT_BYTE_8_LW_EN_S 7 | |
998 | ||
c7c28191 YL |
999 | #define V2_MPT_BYTE_8_MW_CNT_S 8 |
1000 | #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8) | |
1001 | ||
68a997c5 YL |
1002 | #define V2_MPT_BYTE_12_FRE_S 0 |
1003 | ||
3958cc56 WHX |
1004 | #define V2_MPT_BYTE_12_PA_S 1 |
1005 | ||
c7c28191 YL |
1006 | #define V2_MPT_BYTE_12_MR_MW_S 4 |
1007 | ||
1008 | #define V2_MPT_BYTE_12_BPD_S 5 | |
1009 | ||
1010 | #define V2_MPT_BYTE_12_BQP_S 6 | |
1011 | ||
3958cc56 WHX |
1012 | #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7 |
1013 | ||
1014 | #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8 | |
1015 | #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8) | |
1016 | ||
1017 | #define V2_MPT_BYTE_48_PBL_BA_H_S 0 | |
1018 | #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0) | |
1019 | ||
1020 | #define V2_MPT_BYTE_48_BLK_MODE_S 29 | |
1021 | ||
1022 | #define V2_MPT_BYTE_56_PA0_H_S 0 | |
1023 | #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0) | |
1024 | ||
1025 | #define V2_MPT_BYTE_64_PA1_H_S 0 | |
1026 | #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0) | |
1027 | ||
1028 | #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28 | |
1029 | #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28) | |
1030 | ||
93aa2187 WHX |
1031 | #define V2_DB_BYTE_4_TAG_S 0 |
1032 | #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0) | |
1033 | ||
1034 | #define V2_DB_BYTE_4_CMD_S 24 | |
1035 | #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) | |
1036 | ||
cc3391cb | 1037 | #define V2_DB_PARAMETER_IDX_S 0 |
1038 | #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0) | |
2d407888 WHX |
1039 | |
1040 | #define V2_DB_PARAMETER_SL_S 16 | |
1041 | #define V2_DB_PARAMETER_SL_M GENMASK(18, 16) | |
1042 | ||
93aa2187 | 1043 | struct hns_roce_v2_cq_db { |
8b9b8d14 | 1044 | __le32 byte_4; |
1045 | __le32 parameter; | |
93aa2187 WHX |
1046 | }; |
1047 | ||
1048 | #define V2_CQ_DB_BYTE_4_TAG_S 0 | |
1049 | #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0) | |
1050 | ||
1051 | #define V2_CQ_DB_BYTE_4_CMD_S 24 | |
1052 | #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24) | |
1053 | ||
1054 | #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0 | |
1055 | #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0) | |
1056 | ||
1057 | #define V2_CQ_DB_PARAMETER_CMD_SN_S 25 | |
1058 | #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25) | |
1059 | ||
1060 | #define V2_CQ_DB_PARAMETER_NOTIFY_S 24 | |
1061 | ||
7bdee415 | 1062 | struct hns_roce_v2_ud_send_wqe { |
8b9b8d14 | 1063 | __le32 byte_4; |
1064 | __le32 msg_len; | |
0c4a0e29 | 1065 | __le32 immtdata; |
8b9b8d14 | 1066 | __le32 byte_16; |
1067 | __le32 byte_20; | |
1068 | __le32 byte_24; | |
1069 | __le32 qkey; | |
1070 | __le32 byte_32; | |
1071 | __le32 byte_36; | |
1072 | __le32 byte_40; | |
1073 | __le32 dmac; | |
1074 | __le32 byte_48; | |
7bdee415 | 1075 | u8 dgid[GID_LEN_V2]; |
1076 | ||
1077 | }; | |
1078 | #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0 | |
1079 | #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
1080 | ||
1081 | #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7 | |
1082 | ||
1083 | #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8 | |
1084 | ||
1085 | #define V2_UD_SEND_WQE_BYTE_4_SE_S 11 | |
1086 | ||
1087 | #define V2_UD_SEND_WQE_BYTE_16_PD_S 0 | |
1088 | #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0) | |
1089 | ||
1090 | #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24 | |
1091 | #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) | |
1092 | ||
1093 | #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 | |
1094 | #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) | |
1095 | ||
1096 | #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16 | |
1097 | #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16) | |
1098 | ||
1099 | #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0 | |
1100 | #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0) | |
1101 | ||
1102 | #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0 | |
1103 | #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0) | |
1104 | ||
1105 | #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16 | |
1106 | #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16) | |
1107 | ||
1108 | #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24 | |
1109 | #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24) | |
1110 | ||
1111 | #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0 | |
1112 | #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0) | |
1113 | ||
1114 | #define V2_UD_SEND_WQE_BYTE_40_SL_S 20 | |
1115 | #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20) | |
1116 | ||
1117 | #define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24 | |
1118 | #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24) | |
1119 | ||
8320deb8 LO |
1120 | #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30 |
1121 | ||
7bdee415 | 1122 | #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31 |
1123 | ||
1124 | #define V2_UD_SEND_WQE_DMAC_0_S 0 | |
1125 | #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0) | |
1126 | ||
1127 | #define V2_UD_SEND_WQE_DMAC_1_S 8 | |
1128 | #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8) | |
1129 | ||
1130 | #define V2_UD_SEND_WQE_DMAC_2_S 16 | |
1131 | #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16) | |
1132 | ||
1133 | #define V2_UD_SEND_WQE_DMAC_3_S 24 | |
1134 | #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24) | |
1135 | ||
1136 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0 | |
1137 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0) | |
1138 | ||
1139 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8 | |
1140 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8) | |
1141 | ||
1142 | #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16 | |
1143 | #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16) | |
1144 | ||
1145 | #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24 | |
1146 | #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24) | |
1147 | ||
2d407888 | 1148 | struct hns_roce_v2_rc_send_wqe { |
8b9b8d14 | 1149 | __le32 byte_4; |
1150 | __le32 msg_len; | |
1151 | union { | |
1152 | __le32 inv_key; | |
0c4a0e29 | 1153 | __le32 immtdata; |
8b9b8d14 | 1154 | }; |
1155 | __le32 byte_16; | |
1156 | __le32 byte_20; | |
1157 | __le32 rkey; | |
1158 | __le64 va; | |
2d407888 WHX |
1159 | }; |
1160 | ||
1161 | #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 | |
1162 | #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
1163 | ||
1164 | #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 | |
1165 | ||
1166 | #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 | |
1167 | ||
1168 | #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9 | |
1169 | ||
1170 | #define V2_RC_SEND_WQE_BYTE_4_SO_S 10 | |
1171 | ||
1172 | #define V2_RC_SEND_WQE_BYTE_4_SE_S 11 | |
1173 | ||
1174 | #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 | |
1175 | ||
68a997c5 YL |
1176 | #define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19 |
1177 | ||
1178 | #define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20 | |
1179 | ||
1180 | #define V2_RC_FRMR_WQE_BYTE_4_RR_S 21 | |
1181 | ||
1182 | #define V2_RC_FRMR_WQE_BYTE_4_RW_S 22 | |
1183 | ||
1184 | #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23 | |
1185 | ||
2d407888 WHX |
1186 | #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 |
1187 | #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) | |
1188 | ||
1189 | #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24 | |
1190 | #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) | |
1191 | ||
1192 | #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 | |
1193 | #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) | |
1194 | ||
68a997c5 YL |
1195 | struct hns_roce_wqe_frmr_seg { |
1196 | __le32 pbl_size; | |
1197 | __le32 mode_buf_pg_sz; | |
1198 | }; | |
1199 | ||
1200 | #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4 | |
1201 | #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4) | |
1202 | ||
1203 | #define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8 | |
1204 | ||
2d407888 | 1205 | struct hns_roce_v2_wqe_data_seg { |
8b9b8d14 | 1206 | __le32 len; |
1207 | __le32 lkey; | |
1208 | __le64 addr; | |
2d407888 WHX |
1209 | }; |
1210 | ||
1211 | struct hns_roce_v2_db { | |
8b9b8d14 | 1212 | __le32 byte_4; |
1213 | __le32 parameter; | |
2d407888 WHX |
1214 | }; |
1215 | ||
cfc85f3e WHX |
1216 | struct hns_roce_query_version { |
1217 | __le16 rocee_vendor_id; | |
1218 | __le16 rocee_hw_version; | |
1219 | __le32 rsv[5]; | |
1220 | }; | |
1221 | ||
3a63c964 LO |
1222 | struct hns_roce_query_fw_info { |
1223 | __le32 fw_ver; | |
1224 | __le32 rsv[5]; | |
1225 | }; | |
1226 | ||
6b63597d | 1227 | struct hns_roce_cfg_llm_a { |
1228 | __le32 base_addr_l; | |
1229 | __le32 base_addr_h; | |
1230 | __le32 depth_pgsz_init_en; | |
1231 | __le32 head_ba_l; | |
1232 | __le32 head_ba_h_nxtptr; | |
1233 | __le32 head_ptr; | |
1234 | }; | |
1235 | ||
1236 | #define CFG_LLM_QUE_DEPTH_S 0 | |
1237 | #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0) | |
1238 | ||
1239 | #define CFG_LLM_QUE_PGSZ_S 16 | |
1240 | #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16) | |
1241 | ||
1242 | #define CFG_LLM_INIT_EN_S 20 | |
1243 | #define CFG_LLM_INIT_EN_M GENMASK(20, 20) | |
1244 | ||
1245 | #define CFG_LLM_HEAD_PTR_S 0 | |
1246 | #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0) | |
1247 | ||
1248 | struct hns_roce_cfg_llm_b { | |
1249 | __le32 tail_ba_l; | |
1250 | __le32 tail_ba_h; | |
1251 | __le32 tail_ptr; | |
1252 | __le32 rsv[3]; | |
1253 | }; | |
1254 | ||
1255 | #define CFG_LLM_TAIL_BA_H_S 0 | |
1256 | #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0) | |
1257 | ||
1258 | #define CFG_LLM_TAIL_PTR_S 0 | |
1259 | #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0) | |
1260 | ||
cfc85f3e WHX |
1261 | struct hns_roce_cfg_global_param { |
1262 | __le32 time_cfg_udp_port; | |
1263 | __le32 rsv[5]; | |
1264 | }; | |
1265 | ||
1266 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0 | |
1267 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0) | |
1268 | ||
1269 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16 | |
1270 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16) | |
1271 | ||
6b63597d | 1272 | struct hns_roce_pf_res_a { |
cfc85f3e WHX |
1273 | __le32 rsv; |
1274 | __le32 qpc_bt_idx_num; | |
1275 | __le32 srqc_bt_idx_num; | |
1276 | __le32 cqc_bt_idx_num; | |
1277 | __le32 mpt_bt_idx_num; | |
1278 | __le32 eqc_bt_idx_num; | |
1279 | }; | |
1280 | ||
1281 | #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0 | |
1282 | #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0) | |
1283 | ||
1284 | #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16 | |
1285 | #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16) | |
1286 | ||
1287 | #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0 | |
1288 | #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0) | |
1289 | ||
1290 | #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16 | |
1291 | #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16) | |
1292 | ||
1293 | #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0 | |
1294 | #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0) | |
1295 | ||
1296 | #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16 | |
1297 | #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16) | |
1298 | ||
1299 | #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0 | |
1300 | #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0) | |
1301 | ||
1302 | #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16 | |
1303 | #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16) | |
1304 | ||
1305 | #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0 | |
1306 | #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0) | |
1307 | ||
1308 | #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16 | |
1309 | #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16) | |
1310 | ||
6b63597d | 1311 | struct hns_roce_pf_res_b { |
1312 | __le32 rsv0; | |
1313 | __le32 smac_idx_num; | |
1314 | __le32 sgid_idx_num; | |
1315 | __le32 qid_idx_sl_num; | |
6a157f7d YL |
1316 | __le32 sccc_bt_idx_num; |
1317 | __le32 rsv; | |
6b63597d | 1318 | }; |
1319 | ||
1320 | #define PF_RES_DATA_1_PF_SMAC_IDX_S 0 | |
1321 | #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0) | |
1322 | ||
1323 | #define PF_RES_DATA_1_PF_SMAC_NUM_S 8 | |
1324 | #define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8) | |
1325 | ||
1326 | #define PF_RES_DATA_2_PF_SGID_IDX_S 0 | |
1327 | #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0) | |
1328 | ||
1329 | #define PF_RES_DATA_2_PF_SGID_NUM_S 8 | |
1330 | #define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8) | |
1331 | ||
1332 | #define PF_RES_DATA_3_PF_QID_IDX_S 0 | |
1333 | #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0) | |
1334 | ||
1335 | #define PF_RES_DATA_3_PF_SL_NUM_S 16 | |
1336 | #define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16) | |
1337 | ||
6a157f7d YL |
1338 | #define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0 |
1339 | #define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0) | |
1340 | ||
1341 | #define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9 | |
1342 | #define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9) | |
1343 | ||
0e40dc2f YL |
1344 | struct hns_roce_pf_timer_res_a { |
1345 | __le32 rsv0; | |
1346 | __le32 qpc_timer_bt_idx_num; | |
1347 | __le32 cqc_timer_bt_idx_num; | |
1348 | __le32 rsv[3]; | |
1349 | }; | |
1350 | ||
1351 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0 | |
1352 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0) | |
1353 | ||
1354 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16 | |
1355 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16) | |
1356 | ||
1357 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0 | |
1358 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0) | |
1359 | ||
1360 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16 | |
1361 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16) | |
1362 | ||
cfc85f3e | 1363 | struct hns_roce_vf_res_a { |
8b9b8d14 | 1364 | __le32 vf_id; |
1365 | __le32 vf_qpc_bt_idx_num; | |
1366 | __le32 vf_srqc_bt_idx_num; | |
1367 | __le32 vf_cqc_bt_idx_num; | |
1368 | __le32 vf_mpt_bt_idx_num; | |
1369 | __le32 vf_eqc_bt_idx_num; | |
cfc85f3e WHX |
1370 | }; |
1371 | ||
1372 | #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0 | |
1373 | #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0) | |
1374 | ||
1375 | #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16 | |
1376 | #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16) | |
1377 | ||
1378 | #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0 | |
1379 | #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0) | |
1380 | ||
1381 | #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16 | |
1382 | #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16) | |
1383 | ||
1384 | #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0 | |
1385 | #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0) | |
1386 | ||
1387 | #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16 | |
1388 | #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16) | |
1389 | ||
1390 | #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0 | |
1391 | #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0) | |
1392 | ||
1393 | #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16 | |
1394 | #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16) | |
1395 | ||
1396 | #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0 | |
1397 | #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0) | |
1398 | ||
1399 | #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16 | |
1400 | #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16) | |
1401 | ||
1402 | struct hns_roce_vf_res_b { | |
8b9b8d14 | 1403 | __le32 rsv0; |
1404 | __le32 vf_smac_idx_num; | |
1405 | __le32 vf_sgid_idx_num; | |
1406 | __le32 vf_qid_idx_sl_num; | |
6a157f7d YL |
1407 | __le32 vf_sccc_idx_num; |
1408 | __le32 rsv1; | |
cfc85f3e WHX |
1409 | }; |
1410 | ||
1411 | #define VF_RES_B_DATA_0_VF_ID_S 0 | |
1412 | #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0) | |
1413 | ||
1414 | #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0 | |
1415 | #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0) | |
1416 | ||
1417 | #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8 | |
1418 | #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8) | |
1419 | ||
1420 | #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0 | |
1421 | #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0) | |
1422 | ||
1423 | #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8 | |
1424 | #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8) | |
1425 | ||
1426 | #define VF_RES_B_DATA_3_VF_QID_IDX_S 0 | |
1427 | #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0) | |
1428 | ||
1429 | #define VF_RES_B_DATA_3_VF_SL_NUM_S 16 | |
1430 | #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16) | |
1431 | ||
6a157f7d YL |
1432 | #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0 |
1433 | #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0) | |
1434 | ||
1435 | #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9 | |
1436 | #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9) | |
1437 | ||
0c1c3880 LO |
1438 | struct hns_roce_vf_switch { |
1439 | __le32 rocee_sel; | |
1440 | __le32 fun_id; | |
1441 | __le32 cfg; | |
1442 | __le32 resv1; | |
1443 | __le32 resv2; | |
1444 | __le32 resv3; | |
1445 | }; | |
1446 | ||
1447 | #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3 | |
1448 | #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3) | |
1449 | ||
1450 | #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1 | |
1451 | #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2 | |
1452 | #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3 | |
1453 | ||
f747b689 LO |
1454 | struct hns_roce_post_mbox { |
1455 | __le32 in_param_l; | |
1456 | __le32 in_param_h; | |
1457 | __le32 out_param_l; | |
1458 | __le32 out_param_h; | |
1459 | __le32 cmd_tag; | |
1460 | __le32 token_event_en; | |
1461 | }; | |
1462 | ||
1463 | struct hns_roce_mbox_status { | |
1464 | __le32 mb_status_hw_run; | |
1465 | __le32 rsv[5]; | |
1466 | }; | |
1467 | ||
a81fba28 | 1468 | struct hns_roce_cfg_bt_attr { |
8b9b8d14 | 1469 | __le32 vf_qpc_cfg; |
1470 | __le32 vf_srqc_cfg; | |
1471 | __le32 vf_cqc_cfg; | |
1472 | __le32 vf_mpt_cfg; | |
6a157f7d YL |
1473 | __le32 vf_sccc_cfg; |
1474 | __le32 rsv; | |
a81fba28 WHX |
1475 | }; |
1476 | ||
1477 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0 | |
1478 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0) | |
1479 | ||
1480 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4 | |
1481 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4) | |
1482 | ||
1483 | #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8 | |
1484 | #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8) | |
1485 | ||
1486 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0 | |
1487 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0) | |
1488 | ||
1489 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4 | |
1490 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4) | |
1491 | ||
1492 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8 | |
1493 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8) | |
1494 | ||
1495 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0 | |
1496 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0) | |
1497 | ||
1498 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4 | |
1499 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4) | |
1500 | ||
1501 | #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8 | |
1502 | #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8) | |
1503 | ||
1504 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0 | |
1505 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0) | |
1506 | ||
1507 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4 | |
1508 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4) | |
1509 | ||
1510 | #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8 | |
1511 | #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8) | |
1512 | ||
6a157f7d YL |
1513 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0 |
1514 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0) | |
1515 | ||
1516 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4 | |
1517 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4) | |
1518 | ||
1519 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8 | |
1520 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8) | |
1521 | ||
4db134a3 | 1522 | struct hns_roce_cfg_sgid_tb { |
1523 | __le32 table_idx_rsv; | |
1524 | __le32 vf_sgid_l; | |
1525 | __le32 vf_sgid_ml; | |
1526 | __le32 vf_sgid_mh; | |
1527 | __le32 vf_sgid_h; | |
1528 | __le32 vf_sgid_type_rsv; | |
1529 | }; | |
1530 | #define CFG_SGID_TB_TABLE_IDX_S 0 | |
1531 | #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0) | |
1532 | ||
1533 | #define CFG_SGID_TB_VF_SGID_TYPE_S 0 | |
1534 | #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0) | |
1535 | ||
e8e8b652 | 1536 | struct hns_roce_cfg_smac_tb { |
1537 | __le32 tb_idx_rsv; | |
1538 | __le32 vf_smac_l; | |
1539 | __le32 vf_smac_h_rsv; | |
1540 | __le32 rsv[3]; | |
1541 | }; | |
1542 | #define CFG_SMAC_TB_IDX_S 0 | |
1543 | #define CFG_SMAC_TB_IDX_M GENMASK(7, 0) | |
1544 | ||
1545 | #define CFG_SMAC_TB_VF_SMAC_H_S 0 | |
1546 | #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0) | |
1547 | ||
a04ff739 | 1548 | struct hns_roce_cmq_desc { |
8b9b8d14 | 1549 | __le16 opcode; |
1550 | __le16 flag; | |
1551 | __le16 retval; | |
1552 | __le16 rsv; | |
1553 | __le32 data[6]; | |
a04ff739 WHX |
1554 | }; |
1555 | ||
a680f2f3 WHX |
1556 | #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000 |
1557 | ||
1558 | #define HNS_ROCE_HW_RUN_BIT_SHIFT 31 | |
1559 | #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF | |
1560 | ||
a04ff739 WHX |
1561 | struct hns_roce_v2_cmq_ring { |
1562 | dma_addr_t desc_dma_addr; | |
1563 | struct hns_roce_cmq_desc *desc; | |
1564 | u32 head; | |
1565 | u32 tail; | |
1566 | ||
1567 | u16 buf_size; | |
1568 | u16 desc_num; | |
1569 | int next_to_use; | |
1570 | int next_to_clean; | |
1571 | u8 flag; | |
1572 | spinlock_t lock; /* command queue lock */ | |
1573 | }; | |
1574 | ||
1575 | struct hns_roce_v2_cmq { | |
1576 | struct hns_roce_v2_cmq_ring csq; | |
1577 | struct hns_roce_v2_cmq_ring crq; | |
1578 | u16 tx_timeout; | |
1579 | u16 last_status; | |
1580 | }; | |
1581 | ||
6b63597d | 1582 | enum hns_roce_link_table_type { |
1583 | TSQ_LINK_TABLE, | |
ded58ff9 | 1584 | TPQ_LINK_TABLE, |
6b63597d | 1585 | }; |
1586 | ||
1587 | struct hns_roce_link_table { | |
1588 | struct hns_roce_buf_list table; | |
1589 | struct hns_roce_buf_list *pg_list; | |
1590 | u32 npages; | |
1591 | u32 pg_sz; | |
1592 | }; | |
1593 | ||
1594 | struct hns_roce_link_table_entry { | |
1595 | u32 blk_ba0; | |
1596 | u32 blk_ba1_nxt_ptr; | |
1597 | }; | |
1598 | #define HNS_ROCE_LINK_TABLE_BA1_S 0 | |
1599 | #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0) | |
1600 | ||
1601 | #define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20 | |
1602 | #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20) | |
1603 | ||
a04ff739 | 1604 | struct hns_roce_v2_priv { |
d061effc | 1605 | struct hnae3_handle *handle; |
a04ff739 | 1606 | struct hns_roce_v2_cmq cmq; |
6b63597d | 1607 | struct hns_roce_link_table tsq; |
ded58ff9 | 1608 | struct hns_roce_link_table tpq; |
a04ff739 WHX |
1609 | }; |
1610 | ||
a5073d60 | 1611 | struct hns_roce_eq_context { |
8b9b8d14 | 1612 | __le32 byte_4; |
1613 | __le32 byte_8; | |
1614 | __le32 byte_12; | |
1615 | __le32 eqe_report_timer; | |
1616 | __le32 eqe_ba0; | |
1617 | __le32 eqe_ba1; | |
1618 | __le32 byte_28; | |
1619 | __le32 byte_32; | |
1620 | __le32 byte_36; | |
1621 | __le32 nxt_eqe_ba0; | |
1622 | __le32 nxt_eqe_ba1; | |
1623 | __le32 rsv[5]; | |
a5073d60 YL |
1624 | }; |
1625 | ||
1626 | #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0 | |
1627 | #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0 | |
1628 | #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0 | |
1629 | #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0 | |
1630 | ||
1631 | #define HNS_ROCE_V2_EQ_STATE_INVALID 0 | |
1632 | #define HNS_ROCE_V2_EQ_STATE_VALID 1 | |
1633 | #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2 | |
1634 | #define HNS_ROCE_V2_EQ_STATE_FAILURE 3 | |
1635 | ||
1636 | #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0 | |
1637 | #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1 | |
1638 | ||
1639 | #define HNS_ROCE_V2_EQ_COALESCE_0 0 | |
1640 | #define HNS_ROCE_V2_EQ_COALESCE_1 1 | |
1641 | ||
1642 | #define HNS_ROCE_V2_EQ_FIRED 0 | |
1643 | #define HNS_ROCE_V2_EQ_ARMED 1 | |
1644 | #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3 | |
1645 | ||
1646 | #define HNS_ROCE_EQ_INIT_EQE_CNT 0 | |
1647 | #define HNS_ROCE_EQ_INIT_PROD_IDX 0 | |
1648 | #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0 | |
1649 | #define HNS_ROCE_EQ_INIT_MSI_IDX 0 | |
1650 | #define HNS_ROCE_EQ_INIT_CONS_IDX 0 | |
1651 | #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0 | |
1652 | ||
1653 | #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31 | |
1654 | #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31 | |
1655 | ||
1656 | #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000 | |
1657 | #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000 | |
1658 | ||
1659 | #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0 | |
1660 | #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1 | |
1661 | #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2 | |
1662 | ||
1663 | #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0 | |
1664 | #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1 | |
1665 | #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2 | |
1666 | #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3 | |
1667 | ||
1668 | #define EQ_ENABLE 1 | |
1669 | #define EQ_DISABLE 0 | |
1670 | ||
1671 | #define EQ_REG_OFFSET 0x4 | |
1672 | ||
1673 | #define HNS_ROCE_INT_NAME_LEN 32 | |
1674 | #define HNS_ROCE_V2_EQN_M GENMASK(23, 0) | |
1675 | ||
1676 | #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0) | |
1677 | ||
1678 | #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0 | |
1679 | #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0) | |
1680 | #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0) | |
1681 | #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0) | |
1682 | #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0) | |
1683 | ||
1684 | /* WORD0 */ | |
1685 | #define HNS_ROCE_EQC_EQ_ST_S 0 | |
1686 | #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0) | |
1687 | ||
1688 | #define HNS_ROCE_EQC_HOP_NUM_S 2 | |
1689 | #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2) | |
1690 | ||
1691 | #define HNS_ROCE_EQC_OVER_IGNORE_S 4 | |
1692 | #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4) | |
1693 | ||
1694 | #define HNS_ROCE_EQC_COALESCE_S 5 | |
1695 | #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5) | |
1696 | ||
1697 | #define HNS_ROCE_EQC_ARM_ST_S 6 | |
1698 | #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6) | |
1699 | ||
1700 | #define HNS_ROCE_EQC_EQN_S 8 | |
1701 | #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8) | |
1702 | ||
1703 | #define HNS_ROCE_EQC_EQE_CNT_S 16 | |
1704 | #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16) | |
1705 | ||
1706 | /* WORD1 */ | |
1707 | #define HNS_ROCE_EQC_BA_PG_SZ_S 0 | |
1708 | #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0) | |
1709 | ||
1710 | #define HNS_ROCE_EQC_BUF_PG_SZ_S 4 | |
1711 | #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4) | |
1712 | ||
1713 | #define HNS_ROCE_EQC_PROD_INDX_S 8 | |
1714 | #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8) | |
1715 | ||
1716 | /* WORD2 */ | |
1717 | #define HNS_ROCE_EQC_MAX_CNT_S 0 | |
1718 | #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0) | |
1719 | ||
1720 | #define HNS_ROCE_EQC_PERIOD_S 16 | |
1721 | #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16) | |
1722 | ||
1723 | /* WORD3 */ | |
1724 | #define HNS_ROCE_EQC_REPORT_TIMER_S 0 | |
1725 | #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0) | |
1726 | ||
1727 | /* WORD4 */ | |
1728 | #define HNS_ROCE_EQC_EQE_BA_L_S 0 | |
1729 | #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0) | |
1730 | ||
1731 | /* WORD5 */ | |
1732 | #define HNS_ROCE_EQC_EQE_BA_H_S 0 | |
1733 | #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0) | |
1734 | ||
1735 | /* WORD6 */ | |
1736 | #define HNS_ROCE_EQC_SHIFT_S 0 | |
1737 | #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0) | |
1738 | ||
1739 | #define HNS_ROCE_EQC_MSI_INDX_S 8 | |
1740 | #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8) | |
1741 | ||
1742 | #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16 | |
1743 | #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16) | |
1744 | ||
1745 | /* WORD7 */ | |
1746 | #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0 | |
1747 | #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0) | |
1748 | ||
1749 | /* WORD8 */ | |
1750 | #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0 | |
1751 | #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0) | |
1752 | ||
1753 | #define HNS_ROCE_EQC_CONS_INDX_S 8 | |
1754 | #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8) | |
1755 | ||
1756 | /* WORD9 */ | |
1757 | #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0 | |
1758 | #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0) | |
1759 | ||
1760 | /* WORD10 */ | |
1761 | #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0 | |
1762 | #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0) | |
1763 | ||
1764 | #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0 | |
1765 | #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0) | |
1766 | ||
1767 | #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0 | |
1768 | #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0) | |
1769 | ||
1770 | #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8 | |
1771 | #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8) | |
1772 | ||
1773 | #define HNS_ROCE_V2_EQ_DB_CMD_S 16 | |
1774 | #define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16) | |
1775 | ||
1776 | #define HNS_ROCE_V2_EQ_DB_TAG_S 0 | |
1777 | #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0) | |
1778 | ||
1779 | #define HNS_ROCE_V2_EQ_DB_PARA_S 0 | |
1780 | #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0) | |
1781 | ||
1782 | #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0 | |
1783 | #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0) | |
1784 | ||
384f8818 LO |
1785 | struct hns_roce_wqe_atomic_seg { |
1786 | __le64 fetchadd_swap_data; | |
1787 | __le64 cmp_data; | |
1788 | }; | |
1789 | ||
aa84fa18 YL |
1790 | struct hns_roce_sccc_clr { |
1791 | __le32 qpn; | |
1792 | __le32 rsv[5]; | |
1793 | }; | |
1794 | ||
1795 | struct hns_roce_sccc_clr_done { | |
1796 | __le32 clr_done; | |
1797 | __le32 rsv[5]; | |
1798 | }; | |
1799 | ||
a04ff739 | 1800 | #endif |