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a04ff739 WHX |
1 | /* |
2 | * Copyright (c) 2016-2017 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef _HNS_ROCE_HW_V2_H | |
34 | #define _HNS_ROCE_HW_V2_H | |
35 | ||
cfc85f3e WHX |
36 | #include <linux/bitops.h> |
37 | ||
38 | #define HNS_ROCE_VF_QPC_BT_NUM 256 | |
6a157f7d | 39 | #define HNS_ROCE_VF_SCCC_BT_NUM 64 |
cfc85f3e WHX |
40 | #define HNS_ROCE_VF_SRQC_BT_NUM 64 |
41 | #define HNS_ROCE_VF_CQC_BT_NUM 64 | |
42 | #define HNS_ROCE_VF_MPT_BT_NUM 64 | |
43 | #define HNS_ROCE_VF_EQC_NUM 64 | |
44 | #define HNS_ROCE_VF_SMAC_NUM 32 | |
45 | #define HNS_ROCE_VF_SGID_NUM 32 | |
46 | #define HNS_ROCE_VF_SL_NUM 8 | |
47 | ||
3e394f94 LO |
48 | #define HNS_ROCE_V2_MAX_QP_NUM 0x100000 |
49 | #define HNS_ROCE_V2_MAX_QPC_TIMER_NUM 0x200 | |
cfc85f3e | 50 | #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000 |
d16da119 LO |
51 | #define HNS_ROCE_V2_MAX_SRQ 0x100000 |
52 | #define HNS_ROCE_V2_MAX_SRQ_WR 0x8000 | |
019cd05c | 53 | #define HNS_ROCE_V2_MAX_SRQ_SGE 64 |
3e394f94 LO |
54 | #define HNS_ROCE_V2_MAX_CQ_NUM 0x100000 |
55 | #define HNS_ROCE_V2_MAX_CQC_TIMER_NUM 0x100 | |
5c1f167a | 56 | #define HNS_ROCE_V2_MAX_SRQ_NUM 0x100000 |
0502849d | 57 | #define HNS_ROCE_V2_MAX_CQE_NUM 0x400000 |
5c1f167a | 58 | #define HNS_ROCE_V2_MAX_SRQWQE_NUM 0x8000 |
019cd05c LC |
59 | #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 64 |
60 | #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 64 | |
05ad5482 | 61 | #define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM 0x200000 |
cfc85f3e WHX |
62 | #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 |
63 | #define HNS_ROCE_V2_UAR_NUM 256 | |
64 | #define HNS_ROCE_V2_PHY_UAR_NUM 1 | |
a5073d60 YL |
65 | #define HNS_ROCE_V2_MAX_IRQ_NUM 65 |
66 | #define HNS_ROCE_V2_COMP_VEC_NUM 63 | |
67 | #define HNS_ROCE_V2_AEQE_VEC_NUM 1 | |
68 | #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1 | |
3e394f94 | 69 | #define HNS_ROCE_V2_MAX_MTPT_NUM 0x100000 |
3180236c WHX |
70 | #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000 |
71 | #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000 | |
5c1f167a LO |
72 | #define HNS_ROCE_V2_MAX_SRQWQE_SEGS 0x1000000 |
73 | #define HNS_ROCE_V2_MAX_IDX_SEGS 0x1000000 | |
3180236c | 74 | #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 |
cfc85f3e WHX |
75 | #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 |
76 | #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 | |
77 | #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 | |
78 | #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16 | |
79 | #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64 | |
80 | #define HNS_ROCE_V2_QPC_ENTRY_SZ 256 | |
81 | #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64 | |
e92f2c18 | 82 | #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48 |
7db82697 | 83 | #define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ 100 |
cfc85f3e | 84 | #define HNS_ROCE_V2_CQC_ENTRY_SZ 64 |
5c1f167a | 85 | #define HNS_ROCE_V2_SRQC_ENTRY_SZ 64 |
cfc85f3e WHX |
86 | #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64 |
87 | #define HNS_ROCE_V2_MTT_ENTRY_SZ 64 | |
ba6bb7e9 | 88 | #define HNS_ROCE_V2_IDX_ENTRY_SZ 4 |
cfc85f3e | 89 | #define HNS_ROCE_V2_CQE_ENTRY_SIZE 32 |
6a157f7d | 90 | #define HNS_ROCE_V2_SCCC_ENTRY_SZ 32 |
887803db YL |
91 | #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ PAGE_SIZE |
92 | #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE | |
cfc85f3e WHX |
93 | #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 |
94 | #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 | |
6da06c62 | 95 | #define HNS_ROCE_INVALID_LKEY 0x100 |
d59fcacc | 96 | #define HNS_ROCE_CMQ_TX_TIMEOUT 30000 |
0b25c9cc | 97 | #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2 |
06ef0ee4 | 98 | #define HNS_ROCE_V2_RSV_QPS 8 |
a04ff739 | 99 | |
90c559b1 LO |
100 | #define HNS_ROCE_V2_HW_RST_TIMEOUT 1000 |
101 | #define HNS_ROCE_V2_HW_RST_UNINT_DELAY 100 | |
6a04aed6 | 102 | |
e075da5e LC |
103 | #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT 20 |
104 | ||
a25d13cb | 105 | #define HNS_ROCE_CONTEXT_HOP_NUM 1 |
6a157f7d | 106 | #define HNS_ROCE_SCCC_HOP_NUM 1 |
a25d13cb | 107 | #define HNS_ROCE_MTT_HOP_NUM 1 |
6a93c77a | 108 | #define HNS_ROCE_CQE_HOP_NUM 1 |
c7bcb134 | 109 | #define HNS_ROCE_SRQWQE_HOP_NUM 1 |
ff795f71 | 110 | #define HNS_ROCE_PBL_HOP_NUM 2 |
a5073d60 | 111 | #define HNS_ROCE_EQE_HOP_NUM 2 |
c7bcb134 | 112 | #define HNS_ROCE_IDX_HOP_NUM 1 |
ba6bb7e9 LO |
113 | #define HNS_ROCE_SQWQE_HOP_NUM 2 |
114 | #define HNS_ROCE_EXT_SGE_HOP_NUM 1 | |
115 | #define HNS_ROCE_RQWQE_HOP_NUM 2 | |
a5073d60 | 116 | |
80a78570 LO |
117 | #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K 6 |
118 | #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K 2 | |
b5ff0f61 | 119 | #define HNS_ROCE_V2_GID_INDEX_NUM 256 |
a25d13cb | 120 | |
29a1fe5d WHX |
121 | #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18) |
122 | ||
a04ff739 WHX |
123 | #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0 |
124 | #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1 | |
125 | #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2 | |
126 | #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3 | |
127 | #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4 | |
128 | #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5 | |
129 | ||
130 | #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT) | |
131 | #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT) | |
132 | #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT) | |
133 | #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT) | |
134 | #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT) | |
135 | #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT) | |
136 | ||
137 | #define HNS_ROCE_CMQ_DESC_NUM_S 3 | |
a04ff739 | 138 | |
aa84fa18 YL |
139 | #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT 5 |
140 | ||
a81fba28 WHX |
141 | #define check_whether_last_step(hop_num, step_idx) \ |
142 | ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \ | |
143 | (step_idx == 1 && hop_num == 1) || \ | |
144 | (step_idx == 2 && hop_num == 2)) | |
0c1c3880 LO |
145 | #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT 0 |
146 | #define HNS_ICL_SWITCH_CMD_ROCEE_SEL BIT(HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT) | |
a81fba28 | 147 | |
426c4146 LO |
148 | #define CMD_CSQ_DESC_NUM 1024 |
149 | #define CMD_CRQ_DESC_NUM 1024 | |
150 | ||
a5073d60 YL |
151 | enum { |
152 | NO_ARMED = 0x0, | |
153 | REG_NXT_CEQE = 0x2, | |
154 | REG_NXT_SE_CEQE = 0x3 | |
155 | }; | |
156 | ||
93aa2187 WHX |
157 | #define V2_CQ_DB_REQ_NOT_SOL 0 |
158 | #define V2_CQ_DB_REQ_NOT 1 | |
159 | ||
160 | #define V2_CQ_STATE_VALID 1 | |
926a01dc WHX |
161 | #define V2_QKEY_VAL 0x80010000 |
162 | ||
163 | #define GID_LEN_V2 16 | |
93aa2187 | 164 | |
90e735ae | 165 | #define HNS_ROCE_V2_CQE_QPN_MASK 0xfffff |
93aa2187 | 166 | |
2d407888 WHX |
167 | enum { |
168 | HNS_ROCE_V2_WQE_OP_SEND = 0x0, | |
169 | HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1, | |
170 | HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2, | |
171 | HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3, | |
172 | HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4, | |
173 | HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5, | |
174 | HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6, | |
175 | HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7, | |
176 | HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8, | |
177 | HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9, | |
178 | HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa, | |
179 | HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb, | |
57005c96 | 180 | HNS_ROCE_V2_WQE_OP_BIND_MW = 0xc, |
2d407888 WHX |
181 | HNS_ROCE_V2_WQE_OP_MASK = 0x1f, |
182 | }; | |
183 | ||
93aa2187 WHX |
184 | enum { |
185 | /* rq operations */ | |
186 | HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0, | |
187 | HNS_ROCE_V2_OPCODE_SEND = 0x1, | |
188 | HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2, | |
189 | HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3, | |
190 | }; | |
191 | ||
192 | enum { | |
2d407888 WHX |
193 | HNS_ROCE_V2_SQ_DB = 0x0, |
194 | HNS_ROCE_V2_RQ_DB = 0x1, | |
195 | HNS_ROCE_V2_SRQ_DB = 0x2, | |
93aa2187 WHX |
196 | HNS_ROCE_V2_CQ_DB_PTR = 0x3, |
197 | HNS_ROCE_V2_CQ_DB_NTR = 0x4, | |
198 | }; | |
199 | ||
200 | enum { | |
201 | HNS_ROCE_CQE_V2_SUCCESS = 0x00, | |
202 | HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01, | |
203 | HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02, | |
204 | HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04, | |
205 | HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05, | |
206 | HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06, | |
207 | HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10, | |
208 | HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11, | |
209 | HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12, | |
210 | HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13, | |
211 | HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14, | |
212 | HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15, | |
213 | HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16, | |
214 | HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22, | |
395f2e8f | 215 | HNS_ROCE_CQE_V2_GENERAL_ERR = 0x23, |
93aa2187 WHX |
216 | |
217 | HNS_ROCE_V2_CQE_STATUS_MASK = 0xff, | |
218 | }; | |
219 | ||
a04ff739 WHX |
220 | /* CMQ command */ |
221 | enum hns_roce_opcode_type { | |
3a63c964 | 222 | HNS_QUERY_FW_VER = 0x0001, |
a04ff739 WHX |
223 | HNS_ROCE_OPC_QUERY_HW_VER = 0x8000, |
224 | HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001, | |
225 | HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004, | |
226 | HNS_ROCE_OPC_QUERY_PF_RES = 0x8400, | |
227 | HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401, | |
6b63597d | 228 | HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403, |
ded58ff9 | 229 | HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404, |
0e40dc2f | 230 | HNS_ROCE_OPC_QUERY_PF_TIMER_RES = 0x8406, |
ba6bb7e9 | 231 | HNS_ROCE_OPC_QUERY_PF_CAPS_NUM = 0x8408, |
4db134a3 | 232 | HNS_ROCE_OPC_CFG_SGID_TB = 0x8500, |
e8e8b652 | 233 | HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501, |
f747b689 LO |
234 | HNS_ROCE_OPC_POST_MB = 0x8504, |
235 | HNS_ROCE_OPC_QUERY_MB_ST = 0x8505, | |
a04ff739 | 236 | HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506, |
89a6da3c | 237 | HNS_ROCE_OPC_FUNC_CLEAR = 0x8508, |
aa84fa18 YL |
238 | HNS_ROCE_OPC_CLR_SCCC = 0x8509, |
239 | HNS_ROCE_OPC_QUERY_SCCC = 0x850a, | |
240 | HNS_ROCE_OPC_RESET_SCCC = 0x850b, | |
0c1c3880 | 241 | HNS_SWITCH_PARAMETER_CFG = 0x1033, |
a04ff739 WHX |
242 | }; |
243 | ||
244 | enum { | |
245 | TYPE_CRQ, | |
246 | TYPE_CSQ, | |
247 | }; | |
248 | ||
249 | enum hns_roce_cmd_return_status { | |
250 | CMD_EXEC_SUCCESS = 0, | |
251 | CMD_NO_AUTH = 1, | |
252 | CMD_NOT_EXEC = 2, | |
253 | CMD_QUEUE_FULL = 3, | |
254 | }; | |
255 | ||
b5ff0f61 WHX |
256 | enum hns_roce_sgid_type { |
257 | GID_TYPE_FLAG_ROCE_V1 = 0, | |
258 | GID_TYPE_FLAG_ROCE_V2_IPV4, | |
259 | GID_TYPE_FLAG_ROCE_V2_IPV6, | |
260 | }; | |
261 | ||
93aa2187 | 262 | struct hns_roce_v2_cq_context { |
8b9b8d14 | 263 | __le32 byte_4_pg_ceqn; |
264 | __le32 byte_8_cqn; | |
265 | __le32 cqe_cur_blk_addr; | |
266 | __le32 byte_16_hop_addr; | |
267 | __le32 cqe_nxt_blk_addr; | |
268 | __le32 byte_24_pgsz_addr; | |
269 | __le32 byte_28_cq_pi; | |
270 | __le32 byte_32_cq_ci; | |
271 | __le32 cqe_ba; | |
272 | __le32 byte_40_cqe_ba; | |
273 | __le32 byte_44_db_record; | |
274 | __le32 db_record_addr; | |
275 | __le32 byte_52_cqe_cnt; | |
276 | __le32 byte_56_cqe_period_maxcnt; | |
277 | __le32 cqe_report_timer; | |
278 | __le32 byte_64_se_cqe_idx; | |
93aa2187 | 279 | }; |
a5073d60 YL |
280 | #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0 |
281 | #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0 | |
282 | ||
93aa2187 WHX |
283 | #define V2_CQC_BYTE_4_CQ_ST_S 0 |
284 | #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0) | |
285 | ||
286 | #define V2_CQC_BYTE_4_POLL_S 2 | |
287 | ||
288 | #define V2_CQC_BYTE_4_SE_S 3 | |
289 | ||
290 | #define V2_CQC_BYTE_4_OVER_IGNORE_S 4 | |
291 | ||
292 | #define V2_CQC_BYTE_4_COALESCE_S 5 | |
293 | ||
294 | #define V2_CQC_BYTE_4_ARM_ST_S 6 | |
295 | #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6) | |
296 | ||
297 | #define V2_CQC_BYTE_4_SHIFT_S 8 | |
298 | #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8) | |
299 | ||
300 | #define V2_CQC_BYTE_4_CMD_SN_S 13 | |
301 | #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13) | |
302 | ||
303 | #define V2_CQC_BYTE_4_CEQN_S 15 | |
304 | #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15) | |
305 | ||
306 | #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24 | |
307 | #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24) | |
308 | ||
309 | #define V2_CQC_BYTE_8_CQN_S 0 | |
310 | #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0) | |
311 | ||
312 | #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0 | |
313 | #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0) | |
314 | ||
315 | #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30 | |
316 | #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30) | |
317 | ||
318 | #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0 | |
319 | #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0) | |
320 | ||
321 | #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24 | |
322 | #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24) | |
323 | ||
324 | #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28 | |
325 | #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28) | |
326 | ||
327 | #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0 | |
328 | #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0) | |
329 | ||
330 | #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0 | |
331 | #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0) | |
332 | ||
333 | #define V2_CQC_BYTE_40_CQE_BA_S 0 | |
334 | #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0) | |
335 | ||
336 | #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0 | |
337 | ||
9b44703d YL |
338 | #define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1 |
339 | #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1) | |
340 | ||
93aa2187 WHX |
341 | #define V2_CQC_BYTE_52_CQE_CNT_S 0 |
342 | #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0) | |
343 | ||
344 | #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0 | |
345 | #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0) | |
346 | ||
347 | #define V2_CQC_BYTE_56_CQ_PERIOD_S 16 | |
348 | #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16) | |
349 | ||
350 | #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0 | |
351 | #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0) | |
352 | ||
c7bcb134 LO |
353 | struct hns_roce_srq_context { |
354 | __le32 byte_4_srqn_srqst; | |
355 | __le32 byte_8_limit_wl; | |
356 | __le32 byte_12_xrcd; | |
357 | __le32 byte_16_pi_ci; | |
358 | __le32 wqe_bt_ba; | |
359 | __le32 byte_24_wqe_bt_ba; | |
360 | __le32 byte_28_rqws_pd; | |
361 | __le32 idx_bt_ba; | |
362 | __le32 rsv_idx_bt_ba; | |
363 | __le32 idx_cur_blk_addr; | |
364 | __le32 byte_44_idxbufpgsz_addr; | |
365 | __le32 idx_nxt_blk_addr; | |
366 | __le32 rsv_idxnxtblkaddr; | |
367 | __le32 byte_56_xrc_cqn; | |
368 | __le32 db_record_addr_record_en; | |
369 | __le32 db_record_addr; | |
370 | }; | |
371 | ||
372 | #define SRQC_BYTE_4_SRQ_ST_S 0 | |
373 | #define SRQC_BYTE_4_SRQ_ST_M GENMASK(1, 0) | |
374 | ||
375 | #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S 2 | |
376 | #define SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M GENMASK(3, 2) | |
377 | ||
378 | #define SRQC_BYTE_4_SRQ_SHIFT_S 4 | |
379 | #define SRQC_BYTE_4_SRQ_SHIFT_M GENMASK(7, 4) | |
380 | ||
381 | #define SRQC_BYTE_4_SRQN_S 8 | |
382 | #define SRQC_BYTE_4_SRQN_M GENMASK(31, 8) | |
383 | ||
384 | #define SRQC_BYTE_8_SRQ_LIMIT_WL_S 0 | |
385 | #define SRQC_BYTE_8_SRQ_LIMIT_WL_M GENMASK(15, 0) | |
386 | ||
387 | #define SRQC_BYTE_12_SRQ_XRCD_S 0 | |
388 | #define SRQC_BYTE_12_SRQ_XRCD_M GENMASK(23, 0) | |
389 | ||
390 | #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_S 0 | |
391 | #define SRQC_BYTE_16_SRQ_PRODUCER_IDX_M GENMASK(15, 0) | |
392 | ||
393 | #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_S 0 | |
394 | #define SRQC_BYTE_16_SRQ_CONSUMER_IDX_M GENMASK(31, 16) | |
395 | ||
396 | #define SRQC_BYTE_24_SRQ_WQE_BT_BA_S 0 | |
397 | #define SRQC_BYTE_24_SRQ_WQE_BT_BA_M GENMASK(28, 0) | |
398 | ||
399 | #define SRQC_BYTE_28_PD_S 0 | |
400 | #define SRQC_BYTE_28_PD_M GENMASK(23, 0) | |
401 | ||
402 | #define SRQC_BYTE_28_RQWS_S 24 | |
403 | #define SRQC_BYTE_28_RQWS_M GENMASK(27, 24) | |
404 | ||
405 | #define SRQC_BYTE_36_SRQ_IDX_BT_BA_S 0 | |
406 | #define SRQC_BYTE_36_SRQ_IDX_BT_BA_M GENMASK(28, 0) | |
407 | ||
408 | #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S 0 | |
409 | #define SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M GENMASK(19, 0) | |
410 | ||
411 | #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S 22 | |
412 | #define SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M GENMASK(23, 22) | |
413 | ||
414 | #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S 24 | |
415 | #define SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M GENMASK(27, 24) | |
416 | ||
417 | #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S 28 | |
418 | #define SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M GENMASK(31, 28) | |
419 | ||
420 | #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S 0 | |
421 | #define SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M GENMASK(19, 0) | |
422 | ||
423 | #define SRQC_BYTE_56_SRQ_XRC_CQN_S 0 | |
424 | #define SRQC_BYTE_56_SRQ_XRC_CQN_M GENMASK(23, 0) | |
425 | ||
426 | #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S 24 | |
427 | #define SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M GENMASK(27, 24) | |
428 | ||
429 | #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S 28 | |
430 | #define SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M GENMASK(31, 28) | |
431 | ||
432 | #define SRQC_BYTE_60_SRQ_RECORD_EN_S 0 | |
433 | ||
434 | #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_S 1 | |
435 | #define SRQC_BYTE_60_SRQ_DB_RECORD_ADDR_M GENMASK(31, 1) | |
436 | ||
926a01dc WHX |
437 | enum{ |
438 | V2_MPT_ST_VALID = 0x1, | |
c7c28191 | 439 | V2_MPT_ST_FREE = 0x2, |
926a01dc WHX |
440 | }; |
441 | ||
442 | enum hns_roce_v2_qp_state { | |
443 | HNS_ROCE_QP_ST_RST, | |
444 | HNS_ROCE_QP_ST_INIT, | |
445 | HNS_ROCE_QP_ST_RTR, | |
446 | HNS_ROCE_QP_ST_RTS, | |
926a01dc | 447 | HNS_ROCE_QP_ST_SQD, |
fd72926c | 448 | HNS_ROCE_QP_ST_SQER, |
926a01dc WHX |
449 | HNS_ROCE_QP_ST_ERR, |
450 | HNS_ROCE_QP_ST_SQ_DRAINING, | |
451 | HNS_ROCE_QP_NUM_ST | |
452 | }; | |
453 | ||
454 | struct hns_roce_v2_qp_context { | |
8b9b8d14 | 455 | __le32 byte_4_sqpn_tst; |
456 | __le32 wqe_sge_ba; | |
457 | __le32 byte_12_sq_hop; | |
458 | __le32 byte_16_buf_ba_pg_sz; | |
459 | __le32 byte_20_smac_sgid_idx; | |
460 | __le32 byte_24_mtu_tc; | |
461 | __le32 byte_28_at_fl; | |
926a01dc | 462 | u8 dgid[GID_LEN_V2]; |
8b9b8d14 | 463 | __le32 dmac; |
464 | __le32 byte_52_udpspn_dmac; | |
465 | __le32 byte_56_dqpn_err; | |
2362ccee | 466 | __le32 byte_60_qpst_tempid; |
8b9b8d14 | 467 | __le32 qkey_xrcd; |
468 | __le32 byte_68_rq_db; | |
469 | __le32 rq_db_record_addr; | |
470 | __le32 byte_76_srqn_op_en; | |
471 | __le32 byte_80_rnr_rx_cqn; | |
472 | __le32 byte_84_rq_ci_pi; | |
473 | __le32 rq_cur_blk_addr; | |
474 | __le32 byte_92_srq_info; | |
475 | __le32 byte_96_rx_reqmsn; | |
476 | __le32 rq_nxt_blk_addr; | |
477 | __le32 byte_104_rq_sge; | |
478 | __le32 byte_108_rx_reqepsn; | |
479 | __le32 rq_rnr_timer; | |
480 | __le32 rx_msg_len; | |
481 | __le32 rx_rkey_pkt_info; | |
482 | __le64 rx_va; | |
483 | __le32 byte_132_trrl; | |
484 | __le32 trrl_ba; | |
485 | __le32 byte_140_raq; | |
486 | __le32 byte_144_raq; | |
487 | __le32 byte_148_raq; | |
488 | __le32 byte_152_raq; | |
489 | __le32 byte_156_raq; | |
490 | __le32 byte_160_sq_ci_pi; | |
491 | __le32 sq_cur_blk_addr; | |
492 | __le32 byte_168_irrl_idx; | |
493 | __le32 byte_172_sq_psn; | |
494 | __le32 byte_176_msg_pktn; | |
495 | __le32 sq_cur_sge_blk_addr; | |
496 | __le32 byte_184_irrl_idx; | |
497 | __le32 cur_sge_offset; | |
498 | __le32 byte_192_ext_sge; | |
499 | __le32 byte_196_sq_psn; | |
500 | __le32 byte_200_sq_max; | |
501 | __le32 irrl_ba; | |
502 | __le32 byte_208_irrl; | |
503 | __le32 byte_212_lsn; | |
504 | __le32 sq_timer; | |
505 | __le32 byte_220_retry_psn_msn; | |
506 | __le32 byte_224_retry_msg; | |
507 | __le32 rx_sq_cur_blk_addr; | |
508 | __le32 byte_232_irrl_sge; | |
509 | __le32 irrl_cur_sge_offset; | |
510 | __le32 byte_240_irrl_tail; | |
511 | __le32 byte_244_rnr_rxack; | |
512 | __le32 byte_248_ack_psn; | |
513 | __le32 byte_252_err_txcqn; | |
514 | __le32 byte_256_sqflush_rqcqe; | |
926a01dc WHX |
515 | }; |
516 | ||
517 | #define V2_QPC_BYTE_4_TST_S 0 | |
518 | #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0) | |
519 | ||
520 | #define V2_QPC_BYTE_4_SGE_SHIFT_S 3 | |
521 | #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3) | |
522 | ||
523 | #define V2_QPC_BYTE_4_SQPN_S 8 | |
524 | #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8) | |
525 | ||
526 | #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0 | |
527 | #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0) | |
528 | ||
529 | #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29 | |
530 | #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29) | |
531 | ||
532 | #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31 | |
533 | ||
534 | #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0 | |
535 | #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0) | |
536 | ||
537 | #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4 | |
538 | #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4) | |
539 | ||
540 | #define V2_QPC_BYTE_16_PD_S 8 | |
541 | #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8) | |
542 | ||
543 | #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0 | |
544 | #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0) | |
545 | ||
546 | #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2 | |
547 | #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2) | |
548 | ||
549 | #define V2_QPC_BYTE_20_RQWS_S 4 | |
550 | #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4) | |
551 | ||
552 | #define V2_QPC_BYTE_20_SQ_SHIFT_S 8 | |
553 | #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8) | |
554 | ||
555 | #define V2_QPC_BYTE_20_RQ_SHIFT_S 12 | |
556 | #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12) | |
557 | ||
558 | #define V2_QPC_BYTE_20_SGID_IDX_S 16 | |
559 | #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16) | |
560 | ||
561 | #define V2_QPC_BYTE_20_SMAC_IDX_S 24 | |
562 | #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24) | |
563 | ||
564 | #define V2_QPC_BYTE_24_HOP_LIMIT_S 0 | |
565 | #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0) | |
566 | ||
567 | #define V2_QPC_BYTE_24_TC_S 8 | |
568 | #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8) | |
569 | ||
c8e46f8d LO |
570 | #define V2_QPC_BYTE_24_VLAN_ID_S 16 |
571 | #define V2_QPC_BYTE_24_VLAN_ID_M GENMASK(27, 16) | |
926a01dc WHX |
572 | |
573 | #define V2_QPC_BYTE_24_MTU_S 28 | |
574 | #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28) | |
575 | ||
576 | #define V2_QPC_BYTE_28_FL_S 0 | |
577 | #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0) | |
578 | ||
579 | #define V2_QPC_BYTE_28_SL_S 20 | |
580 | #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20) | |
581 | ||
582 | #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24 | |
583 | ||
584 | #define V2_QPC_BYTE_28_CE_FLAG_S 25 | |
585 | ||
586 | #define V2_QPC_BYTE_28_LBI_S 26 | |
587 | ||
588 | #define V2_QPC_BYTE_28_AT_S 27 | |
589 | #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27) | |
590 | ||
591 | #define V2_QPC_BYTE_52_DMAC_S 0 | |
592 | #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0) | |
593 | ||
594 | #define V2_QPC_BYTE_52_UDPSPN_S 16 | |
595 | #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16) | |
596 | ||
597 | #define V2_QPC_BYTE_56_DQPN_S 0 | |
598 | #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0) | |
599 | ||
600 | #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24 | |
601 | #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25 | |
602 | #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26 | |
603 | #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27 | |
604 | ||
605 | #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28 | |
606 | #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28) | |
607 | ||
2362ccee LO |
608 | #define V2_QPC_BYTE_60_TEMPID_S 0 |
609 | #define V2_QPC_BYTE_60_TEMPID_M GENMASK(7, 0) | |
926a01dc | 610 | |
2362ccee LO |
611 | #define V2_QPC_BYTE_60_SCC_TOKEN_S 8 |
612 | #define V2_QPC_BYTE_60_SCC_TOKEN_M GENMASK(26, 8) | |
926a01dc | 613 | |
2362ccee | 614 | #define V2_QPC_BYTE_60_SQ_DB_DOING_S 27 |
926a01dc | 615 | |
2362ccee | 616 | #define V2_QPC_BYTE_60_RQ_DB_DOING_S 28 |
926a01dc WHX |
617 | |
618 | #define V2_QPC_BYTE_60_QP_ST_S 29 | |
619 | #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29) | |
620 | ||
621 | #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0 | |
622 | ||
623 | #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1 | |
624 | #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1) | |
625 | ||
626 | #define V2_QPC_BYTE_76_SRQN_S 0 | |
627 | #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0) | |
628 | ||
629 | #define V2_QPC_BYTE_76_SRQ_EN_S 24 | |
630 | ||
631 | #define V2_QPC_BYTE_76_RRE_S 25 | |
632 | ||
633 | #define V2_QPC_BYTE_76_RWE_S 26 | |
634 | ||
635 | #define V2_QPC_BYTE_76_ATE_S 27 | |
636 | ||
637 | #define V2_QPC_BYTE_76_RQIE_S 28 | |
7db82697 | 638 | #define V2_QPC_BYTE_76_EXT_ATE_S 29 |
caf3e406 | 639 | #define V2_QPC_BYTE_76_RQ_VLAN_EN_S 30 |
926a01dc WHX |
640 | #define V2_QPC_BYTE_80_RX_CQN_S 0 |
641 | #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0) | |
642 | ||
643 | #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27 | |
644 | #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27) | |
645 | ||
646 | #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0 | |
647 | #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0) | |
648 | ||
649 | #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16 | |
650 | #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16) | |
651 | ||
652 | #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0 | |
653 | #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
654 | ||
655 | #define V2_QPC_BYTE_92_SRQ_INFO_S 20 | |
656 | #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20) | |
657 | ||
658 | #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0 | |
659 | #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0) | |
660 | ||
661 | #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0 | |
662 | #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0) | |
663 | ||
664 | #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24 | |
665 | #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24) | |
666 | ||
667 | #define V2_QPC_BYTE_108_INV_CREDIT_S 0 | |
668 | ||
669 | #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3 | |
670 | ||
671 | #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4 | |
672 | #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4) | |
673 | ||
674 | #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7 | |
675 | ||
676 | #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8 | |
677 | #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8) | |
678 | ||
679 | #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0 | |
680 | #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0) | |
681 | ||
682 | #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8 | |
683 | #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8) | |
684 | ||
685 | #define V2_QPC_BYTE_132_TRRL_BA_S 16 | |
686 | #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16) | |
687 | ||
688 | #define V2_QPC_BYTE_140_TRRL_BA_S 0 | |
689 | #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0) | |
690 | ||
691 | #define V2_QPC_BYTE_140_RR_MAX_S 12 | |
692 | #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12) | |
693 | ||
2362ccee | 694 | #define V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S 15 |
926a01dc WHX |
695 | |
696 | #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16 | |
697 | #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16) | |
698 | ||
699 | #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24 | |
700 | #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24) | |
701 | ||
702 | #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0 | |
703 | #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0) | |
704 | ||
926a01dc WHX |
705 | #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25 |
706 | #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25) | |
707 | ||
708 | #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31 | |
709 | ||
710 | #define V2_QPC_BYTE_148_RQ_MSN_S 0 | |
711 | #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0) | |
712 | ||
713 | #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24 | |
714 | #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24) | |
715 | ||
834fa8cf LO |
716 | #define V2_QPC_BYTE_152_RAQ_PSN_S 0 |
717 | #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(23, 0) | |
926a01dc WHX |
718 | |
719 | #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24 | |
720 | #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24) | |
721 | ||
722 | #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0 | |
723 | #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0) | |
724 | ||
725 | #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0 | |
726 | #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0) | |
727 | ||
728 | #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16 | |
729 | #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16) | |
730 | ||
731 | #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0 | |
732 | #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
733 | ||
734 | #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20 | |
735 | ||
b5fddb7c | 736 | #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21 |
737 | ||
738 | #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22 | |
739 | #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22) | |
926a01dc | 740 | |
caf3e406 | 741 | #define V2_QPC_BYTE_168_SQ_VLAN_EN_S 24 |
2362ccee LO |
742 | #define V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S 25 |
743 | #define V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S 26 | |
744 | #define V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S 27 | |
926a01dc WHX |
745 | #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28 |
746 | #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28) | |
747 | ||
748 | #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0 | |
749 | #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0) | |
750 | ||
751 | #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6 | |
752 | ||
753 | #define V2_QPC_BYTE_172_FRE_S 7 | |
754 | ||
755 | #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8 | |
756 | #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8) | |
757 | ||
758 | #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0 | |
759 | #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0) | |
760 | ||
761 | #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24 | |
762 | #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24) | |
763 | ||
764 | #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0 | |
765 | #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0) | |
766 | ||
767 | #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20 | |
768 | #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20) | |
769 | ||
770 | #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0 | |
771 | #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0) | |
772 | ||
773 | #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24 | |
774 | #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24) | |
775 | ||
776 | #define V2_QPC_BYTE_196_IRRL_HEAD_S 0 | |
777 | #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0) | |
778 | ||
779 | #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8 | |
780 | #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8) | |
781 | ||
782 | #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0 | |
783 | #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0) | |
784 | ||
785 | #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16 | |
786 | #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16) | |
787 | ||
788 | #define V2_QPC_BYTE_208_IRRL_BA_S 0 | |
789 | #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0) | |
790 | ||
791 | #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26 | |
792 | ||
793 | #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27 | |
794 | ||
795 | #define V2_QPC_BYTE_208_RMT_E2E_S 28 | |
796 | ||
797 | #define V2_QPC_BYTE_208_SR_MAX_S 29 | |
798 | #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29) | |
799 | ||
800 | #define V2_QPC_BYTE_212_LSN_S 0 | |
801 | #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0) | |
802 | ||
803 | #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24 | |
804 | #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24) | |
805 | ||
806 | #define V2_QPC_BYTE_212_CHECK_FLG_S 27 | |
807 | #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27) | |
808 | ||
809 | #define V2_QPC_BYTE_212_RETRY_CNT_S 29 | |
810 | #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29) | |
811 | ||
812 | #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0 | |
813 | #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0) | |
814 | ||
815 | #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16 | |
816 | #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16) | |
817 | ||
818 | #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0 | |
819 | #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0) | |
820 | ||
821 | #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8 | |
822 | #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8) | |
823 | ||
824 | #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0 | |
825 | #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
826 | ||
827 | #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20 | |
828 | #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20) | |
829 | ||
2362ccee LO |
830 | #define V2_QPC_BYTE_232_SO_LP_VLD_S 29 |
831 | #define V2_QPC_BYTE_232_FENCE_LP_VLD_S 30 | |
832 | #define V2_QPC_BYTE_232_IRRL_LP_VLD_S 31 | |
833 | ||
926a01dc WHX |
834 | #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0 |
835 | #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0) | |
836 | ||
837 | #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8 | |
838 | #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8) | |
839 | ||
840 | #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16 | |
841 | #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16) | |
842 | ||
843 | #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0 | |
844 | #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0) | |
845 | ||
846 | #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24 | |
847 | #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24) | |
848 | ||
849 | #define V2_QPC_BYTE_244_RNR_CNT_S 27 | |
850 | #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27) | |
851 | ||
2362ccee LO |
852 | #define V2_QPC_BYTE_244_LCL_OP_FLG_S 30 |
853 | #define V2_QPC_BYTE_244_IRRL_RD_FLG_S 31 | |
854 | ||
926a01dc WHX |
855 | #define V2_QPC_BYTE_248_IRRL_PSN_S 0 |
856 | #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0) | |
857 | ||
858 | #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24 | |
859 | ||
860 | #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25 | |
861 | #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25) | |
862 | ||
863 | #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27 | |
864 | ||
865 | #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28 | |
866 | ||
867 | #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31 | |
868 | ||
869 | #define V2_QPC_BYTE_252_TX_CQN_S 0 | |
870 | #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0) | |
871 | ||
872 | #define V2_QPC_BYTE_252_SIG_TYPE_S 24 | |
873 | ||
874 | #define V2_QPC_BYTE_252_ERR_TYPE_S 25 | |
875 | #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25) | |
876 | ||
877 | #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0 | |
878 | #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0) | |
879 | ||
880 | #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16 | |
881 | #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16) | |
882 | ||
2a3d923f LO |
883 | #define V2_QP_RWE_S 1 /* rdma write enable */ |
884 | #define V2_QP_RRE_S 2 /* rdma read enable */ | |
885 | #define V2_QP_ATE_S 3 /* rdma atomic enable */ | |
886 | ||
93aa2187 | 887 | struct hns_roce_v2_cqe { |
8b9b8d14 | 888 | __le32 byte_4; |
ccb8a29e JG |
889 | union { |
890 | __le32 rkey; | |
0c4a0e29 | 891 | __le32 immtdata; |
ccb8a29e | 892 | }; |
8b9b8d14 | 893 | __le32 byte_12; |
894 | __le32 byte_16; | |
895 | __le32 byte_cnt; | |
2eade675 | 896 | u8 smac[4]; |
8b9b8d14 | 897 | __le32 byte_28; |
898 | __le32 byte_32; | |
93aa2187 WHX |
899 | }; |
900 | ||
901 | #define V2_CQE_BYTE_4_OPCODE_S 0 | |
902 | #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
903 | ||
904 | #define V2_CQE_BYTE_4_RQ_INLINE_S 5 | |
905 | ||
906 | #define V2_CQE_BYTE_4_S_R_S 6 | |
907 | ||
908 | #define V2_CQE_BYTE_4_OWNER_S 7 | |
909 | ||
910 | #define V2_CQE_BYTE_4_STATUS_S 8 | |
911 | #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8) | |
912 | ||
913 | #define V2_CQE_BYTE_4_WQE_INDX_S 16 | |
914 | #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16) | |
915 | ||
916 | #define V2_CQE_BYTE_12_XRC_SRQN_S 0 | |
917 | #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0) | |
918 | ||
919 | #define V2_CQE_BYTE_16_LCL_QPN_S 0 | |
920 | #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0) | |
921 | ||
922 | #define V2_CQE_BYTE_16_SUB_STATUS_S 24 | |
923 | #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24) | |
924 | ||
925 | #define V2_CQE_BYTE_28_SMAC_4_S 0 | |
926 | #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0) | |
927 | ||
928 | #define V2_CQE_BYTE_28_SMAC_5_S 8 | |
929 | #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8) | |
930 | ||
931 | #define V2_CQE_BYTE_28_PORT_TYPE_S 16 | |
932 | #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16) | |
933 | ||
944e6409 LO |
934 | #define V2_CQE_BYTE_28_VID_S 18 |
935 | #define V2_CQE_BYTE_28_VID_M GENMASK(29, 18) | |
936 | ||
937 | #define V2_CQE_BYTE_28_VID_VLD_S 30 | |
938 | ||
93aa2187 WHX |
939 | #define V2_CQE_BYTE_32_RMT_QPN_S 0 |
940 | #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0) | |
941 | ||
942 | #define V2_CQE_BYTE_32_SL_S 24 | |
943 | #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24) | |
944 | ||
945 | #define V2_CQE_BYTE_32_PORTN_S 27 | |
946 | #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27) | |
947 | ||
948 | #define V2_CQE_BYTE_32_GRH_S 30 | |
949 | ||
950 | #define V2_CQE_BYTE_32_LPK_S 31 | |
951 | ||
3958cc56 WHX |
952 | struct hns_roce_v2_mpt_entry { |
953 | __le32 byte_4_pd_hop_st; | |
954 | __le32 byte_8_mw_cnt_en; | |
955 | __le32 byte_12_mw_pa; | |
956 | __le32 bound_lkey; | |
957 | __le32 len_l; | |
958 | __le32 len_h; | |
959 | __le32 lkey; | |
960 | __le32 va_l; | |
961 | __le32 va_h; | |
962 | __le32 pbl_size; | |
963 | __le32 pbl_ba_l; | |
964 | __le32 byte_48_mode_ba; | |
965 | __le32 pa0_l; | |
966 | __le32 byte_56_pa0_h; | |
967 | __le32 pa1_l; | |
968 | __le32 byte_64_buf_pa1; | |
969 | }; | |
970 | ||
971 | #define V2_MPT_BYTE_4_MPT_ST_S 0 | |
972 | #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0) | |
973 | ||
974 | #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2 | |
975 | #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2) | |
976 | ||
977 | #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4 | |
978 | #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4) | |
979 | ||
980 | #define V2_MPT_BYTE_4_PD_S 8 | |
981 | #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8) | |
982 | ||
983 | #define V2_MPT_BYTE_8_RA_EN_S 0 | |
984 | ||
985 | #define V2_MPT_BYTE_8_R_INV_EN_S 1 | |
986 | ||
987 | #define V2_MPT_BYTE_8_L_INV_EN_S 2 | |
988 | ||
989 | #define V2_MPT_BYTE_8_BIND_EN_S 3 | |
990 | ||
991 | #define V2_MPT_BYTE_8_ATOMIC_EN_S 4 | |
992 | ||
993 | #define V2_MPT_BYTE_8_RR_EN_S 5 | |
994 | ||
995 | #define V2_MPT_BYTE_8_RW_EN_S 6 | |
996 | ||
997 | #define V2_MPT_BYTE_8_LW_EN_S 7 | |
998 | ||
c7c28191 YL |
999 | #define V2_MPT_BYTE_8_MW_CNT_S 8 |
1000 | #define V2_MPT_BYTE_8_MW_CNT_M GENMASK(31, 8) | |
1001 | ||
68a997c5 YL |
1002 | #define V2_MPT_BYTE_12_FRE_S 0 |
1003 | ||
3958cc56 WHX |
1004 | #define V2_MPT_BYTE_12_PA_S 1 |
1005 | ||
c7c28191 YL |
1006 | #define V2_MPT_BYTE_12_MR_MW_S 4 |
1007 | ||
1008 | #define V2_MPT_BYTE_12_BPD_S 5 | |
1009 | ||
1010 | #define V2_MPT_BYTE_12_BQP_S 6 | |
1011 | ||
3958cc56 WHX |
1012 | #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7 |
1013 | ||
1014 | #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8 | |
1015 | #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8) | |
1016 | ||
1017 | #define V2_MPT_BYTE_48_PBL_BA_H_S 0 | |
1018 | #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0) | |
1019 | ||
1020 | #define V2_MPT_BYTE_48_BLK_MODE_S 29 | |
1021 | ||
1022 | #define V2_MPT_BYTE_56_PA0_H_S 0 | |
1023 | #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0) | |
1024 | ||
1025 | #define V2_MPT_BYTE_64_PA1_H_S 0 | |
1026 | #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0) | |
1027 | ||
1028 | #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28 | |
1029 | #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28) | |
1030 | ||
93aa2187 WHX |
1031 | #define V2_DB_BYTE_4_TAG_S 0 |
1032 | #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0) | |
1033 | ||
1034 | #define V2_DB_BYTE_4_CMD_S 24 | |
1035 | #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) | |
1036 | ||
cc3391cb | 1037 | #define V2_DB_PARAMETER_IDX_S 0 |
1038 | #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0) | |
2d407888 WHX |
1039 | |
1040 | #define V2_DB_PARAMETER_SL_S 16 | |
1041 | #define V2_DB_PARAMETER_SL_M GENMASK(18, 16) | |
1042 | ||
93aa2187 WHX |
1043 | #define V2_CQ_DB_BYTE_4_TAG_S 0 |
1044 | #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0) | |
1045 | ||
1046 | #define V2_CQ_DB_BYTE_4_CMD_S 24 | |
1047 | #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24) | |
1048 | ||
1049 | #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0 | |
1050 | #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0) | |
1051 | ||
1052 | #define V2_CQ_DB_PARAMETER_CMD_SN_S 25 | |
1053 | #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25) | |
1054 | ||
1055 | #define V2_CQ_DB_PARAMETER_NOTIFY_S 24 | |
1056 | ||
7bdee415 | 1057 | struct hns_roce_v2_ud_send_wqe { |
8b9b8d14 | 1058 | __le32 byte_4; |
1059 | __le32 msg_len; | |
0c4a0e29 | 1060 | __le32 immtdata; |
8b9b8d14 | 1061 | __le32 byte_16; |
1062 | __le32 byte_20; | |
1063 | __le32 byte_24; | |
1064 | __le32 qkey; | |
1065 | __le32 byte_32; | |
1066 | __le32 byte_36; | |
1067 | __le32 byte_40; | |
1068 | __le32 dmac; | |
1069 | __le32 byte_48; | |
7bdee415 | 1070 | u8 dgid[GID_LEN_V2]; |
1071 | ||
1072 | }; | |
1073 | #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0 | |
1074 | #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
1075 | ||
1076 | #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7 | |
1077 | ||
1078 | #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8 | |
1079 | ||
1080 | #define V2_UD_SEND_WQE_BYTE_4_SE_S 11 | |
1081 | ||
1082 | #define V2_UD_SEND_WQE_BYTE_16_PD_S 0 | |
1083 | #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0) | |
1084 | ||
1085 | #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24 | |
1086 | #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) | |
1087 | ||
1088 | #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 | |
1089 | #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) | |
1090 | ||
1091 | #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16 | |
1092 | #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16) | |
1093 | ||
1094 | #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0 | |
1095 | #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0) | |
1096 | ||
1097 | #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0 | |
1098 | #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0) | |
1099 | ||
1100 | #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16 | |
1101 | #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16) | |
1102 | ||
1103 | #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24 | |
1104 | #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24) | |
1105 | ||
1106 | #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0 | |
1107 | #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0) | |
1108 | ||
1109 | #define V2_UD_SEND_WQE_BYTE_40_SL_S 20 | |
1110 | #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20) | |
1111 | ||
1112 | #define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24 | |
1113 | #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24) | |
1114 | ||
8320deb8 LO |
1115 | #define V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S 30 |
1116 | ||
7bdee415 | 1117 | #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31 |
1118 | ||
1119 | #define V2_UD_SEND_WQE_DMAC_0_S 0 | |
1120 | #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0) | |
1121 | ||
1122 | #define V2_UD_SEND_WQE_DMAC_1_S 8 | |
1123 | #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8) | |
1124 | ||
1125 | #define V2_UD_SEND_WQE_DMAC_2_S 16 | |
1126 | #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16) | |
1127 | ||
1128 | #define V2_UD_SEND_WQE_DMAC_3_S 24 | |
1129 | #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24) | |
1130 | ||
1131 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0 | |
1132 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0) | |
1133 | ||
1134 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8 | |
1135 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8) | |
1136 | ||
1137 | #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16 | |
1138 | #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16) | |
1139 | ||
1140 | #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24 | |
1141 | #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24) | |
1142 | ||
2d407888 | 1143 | struct hns_roce_v2_rc_send_wqe { |
8b9b8d14 | 1144 | __le32 byte_4; |
1145 | __le32 msg_len; | |
1146 | union { | |
1147 | __le32 inv_key; | |
0c4a0e29 | 1148 | __le32 immtdata; |
8b9b8d14 | 1149 | }; |
1150 | __le32 byte_16; | |
1151 | __le32 byte_20; | |
1152 | __le32 rkey; | |
1153 | __le64 va; | |
2d407888 WHX |
1154 | }; |
1155 | ||
1156 | #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 | |
1157 | #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
1158 | ||
1159 | #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 | |
1160 | ||
1161 | #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 | |
1162 | ||
1163 | #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9 | |
1164 | ||
1165 | #define V2_RC_SEND_WQE_BYTE_4_SO_S 10 | |
1166 | ||
1167 | #define V2_RC_SEND_WQE_BYTE_4_SE_S 11 | |
1168 | ||
1169 | #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 | |
1170 | ||
68a997c5 YL |
1171 | #define V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S 19 |
1172 | ||
1173 | #define V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S 20 | |
1174 | ||
1175 | #define V2_RC_FRMR_WQE_BYTE_4_RR_S 21 | |
1176 | ||
1177 | #define V2_RC_FRMR_WQE_BYTE_4_RW_S 22 | |
1178 | ||
1179 | #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23 | |
1180 | ||
2d407888 WHX |
1181 | #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 |
1182 | #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) | |
1183 | ||
1184 | #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24 | |
1185 | #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) | |
1186 | ||
1187 | #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 | |
1188 | #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) | |
1189 | ||
68a997c5 YL |
1190 | struct hns_roce_wqe_frmr_seg { |
1191 | __le32 pbl_size; | |
1192 | __le32 mode_buf_pg_sz; | |
1193 | }; | |
1194 | ||
1195 | #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S 4 | |
1196 | #define V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M GENMASK(7, 4) | |
1197 | ||
1198 | #define V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S 8 | |
1199 | ||
2d407888 | 1200 | struct hns_roce_v2_wqe_data_seg { |
8b9b8d14 | 1201 | __le32 len; |
1202 | __le32 lkey; | |
1203 | __le64 addr; | |
2d407888 WHX |
1204 | }; |
1205 | ||
1206 | struct hns_roce_v2_db { | |
8b9b8d14 | 1207 | __le32 byte_4; |
1208 | __le32 parameter; | |
2d407888 WHX |
1209 | }; |
1210 | ||
cfc85f3e WHX |
1211 | struct hns_roce_query_version { |
1212 | __le16 rocee_vendor_id; | |
1213 | __le16 rocee_hw_version; | |
1214 | __le32 rsv[5]; | |
1215 | }; | |
1216 | ||
3a63c964 LO |
1217 | struct hns_roce_query_fw_info { |
1218 | __le32 fw_ver; | |
1219 | __le32 rsv[5]; | |
1220 | }; | |
1221 | ||
89a6da3c LC |
1222 | struct hns_roce_func_clear { |
1223 | __le32 rst_funcid_en; | |
1224 | __le32 func_done; | |
1225 | __le32 rsv[4]; | |
1226 | }; | |
1227 | ||
1228 | #define FUNC_CLEAR_RST_FUN_DONE_S 0 | |
23190b8f WL |
1229 | /* Each physical function manages up to 248 virtual functions, it takes up to |
1230 | * 100ms for each function to execute clear. If an abnormal reset occurs, it is | |
1231 | * executed twice at most, so it takes up to 249 * 2 * 100ms. | |
89a6da3c LC |
1232 | */ |
1233 | #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS (249 * 2 * 100) | |
1234 | #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL 40 | |
1235 | #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT 20 | |
1236 | ||
6b63597d | 1237 | struct hns_roce_cfg_llm_a { |
1238 | __le32 base_addr_l; | |
1239 | __le32 base_addr_h; | |
1240 | __le32 depth_pgsz_init_en; | |
1241 | __le32 head_ba_l; | |
1242 | __le32 head_ba_h_nxtptr; | |
1243 | __le32 head_ptr; | |
1244 | }; | |
1245 | ||
1246 | #define CFG_LLM_QUE_DEPTH_S 0 | |
1247 | #define CFG_LLM_QUE_DEPTH_M GENMASK(12, 0) | |
1248 | ||
1249 | #define CFG_LLM_QUE_PGSZ_S 16 | |
1250 | #define CFG_LLM_QUE_PGSZ_M GENMASK(19, 16) | |
1251 | ||
1252 | #define CFG_LLM_INIT_EN_S 20 | |
1253 | #define CFG_LLM_INIT_EN_M GENMASK(20, 20) | |
1254 | ||
1255 | #define CFG_LLM_HEAD_PTR_S 0 | |
1256 | #define CFG_LLM_HEAD_PTR_M GENMASK(11, 0) | |
1257 | ||
1258 | struct hns_roce_cfg_llm_b { | |
1259 | __le32 tail_ba_l; | |
1260 | __le32 tail_ba_h; | |
1261 | __le32 tail_ptr; | |
1262 | __le32 rsv[3]; | |
1263 | }; | |
1264 | ||
1265 | #define CFG_LLM_TAIL_BA_H_S 0 | |
1266 | #define CFG_LLM_TAIL_BA_H_M GENMASK(19, 0) | |
1267 | ||
1268 | #define CFG_LLM_TAIL_PTR_S 0 | |
1269 | #define CFG_LLM_TAIL_PTR_M GENMASK(11, 0) | |
1270 | ||
cfc85f3e WHX |
1271 | struct hns_roce_cfg_global_param { |
1272 | __le32 time_cfg_udp_port; | |
1273 | __le32 rsv[5]; | |
1274 | }; | |
1275 | ||
1276 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0 | |
1277 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0) | |
1278 | ||
1279 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16 | |
1280 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16) | |
1281 | ||
6b63597d | 1282 | struct hns_roce_pf_res_a { |
cfc85f3e WHX |
1283 | __le32 rsv; |
1284 | __le32 qpc_bt_idx_num; | |
1285 | __le32 srqc_bt_idx_num; | |
1286 | __le32 cqc_bt_idx_num; | |
1287 | __le32 mpt_bt_idx_num; | |
1288 | __le32 eqc_bt_idx_num; | |
1289 | }; | |
1290 | ||
1291 | #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0 | |
1292 | #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0) | |
1293 | ||
1294 | #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16 | |
1295 | #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16) | |
1296 | ||
1297 | #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0 | |
1298 | #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0) | |
1299 | ||
1300 | #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16 | |
1301 | #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16) | |
1302 | ||
1303 | #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0 | |
1304 | #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0) | |
1305 | ||
1306 | #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16 | |
1307 | #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16) | |
1308 | ||
1309 | #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0 | |
1310 | #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0) | |
1311 | ||
1312 | #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16 | |
1313 | #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16) | |
1314 | ||
1315 | #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0 | |
1316 | #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0) | |
1317 | ||
1318 | #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16 | |
1319 | #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16) | |
1320 | ||
6b63597d | 1321 | struct hns_roce_pf_res_b { |
1322 | __le32 rsv0; | |
1323 | __le32 smac_idx_num; | |
1324 | __le32 sgid_idx_num; | |
1325 | __le32 qid_idx_sl_num; | |
6a157f7d YL |
1326 | __le32 sccc_bt_idx_num; |
1327 | __le32 rsv; | |
6b63597d | 1328 | }; |
1329 | ||
1330 | #define PF_RES_DATA_1_PF_SMAC_IDX_S 0 | |
1331 | #define PF_RES_DATA_1_PF_SMAC_IDX_M GENMASK(7, 0) | |
1332 | ||
1333 | #define PF_RES_DATA_1_PF_SMAC_NUM_S 8 | |
1334 | #define PF_RES_DATA_1_PF_SMAC_NUM_M GENMASK(16, 8) | |
1335 | ||
1336 | #define PF_RES_DATA_2_PF_SGID_IDX_S 0 | |
1337 | #define PF_RES_DATA_2_PF_SGID_IDX_M GENMASK(7, 0) | |
1338 | ||
1339 | #define PF_RES_DATA_2_PF_SGID_NUM_S 8 | |
1340 | #define PF_RES_DATA_2_PF_SGID_NUM_M GENMASK(16, 8) | |
1341 | ||
1342 | #define PF_RES_DATA_3_PF_QID_IDX_S 0 | |
1343 | #define PF_RES_DATA_3_PF_QID_IDX_M GENMASK(9, 0) | |
1344 | ||
1345 | #define PF_RES_DATA_3_PF_SL_NUM_S 16 | |
1346 | #define PF_RES_DATA_3_PF_SL_NUM_M GENMASK(26, 16) | |
1347 | ||
6a157f7d YL |
1348 | #define PF_RES_DATA_4_PF_SCCC_BT_IDX_S 0 |
1349 | #define PF_RES_DATA_4_PF_SCCC_BT_IDX_M GENMASK(8, 0) | |
1350 | ||
1351 | #define PF_RES_DATA_4_PF_SCCC_BT_NUM_S 9 | |
1352 | #define PF_RES_DATA_4_PF_SCCC_BT_NUM_M GENMASK(17, 9) | |
1353 | ||
0e40dc2f YL |
1354 | struct hns_roce_pf_timer_res_a { |
1355 | __le32 rsv0; | |
1356 | __le32 qpc_timer_bt_idx_num; | |
1357 | __le32 cqc_timer_bt_idx_num; | |
1358 | __le32 rsv[3]; | |
1359 | }; | |
1360 | ||
1361 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S 0 | |
1362 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M GENMASK(11, 0) | |
1363 | ||
1364 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S 16 | |
1365 | #define PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M GENMASK(28, 16) | |
1366 | ||
1367 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S 0 | |
1368 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M GENMASK(10, 0) | |
1369 | ||
1370 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S 16 | |
1371 | #define PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M GENMASK(27, 16) | |
1372 | ||
cfc85f3e | 1373 | struct hns_roce_vf_res_a { |
8b9b8d14 | 1374 | __le32 vf_id; |
1375 | __le32 vf_qpc_bt_idx_num; | |
1376 | __le32 vf_srqc_bt_idx_num; | |
1377 | __le32 vf_cqc_bt_idx_num; | |
1378 | __le32 vf_mpt_bt_idx_num; | |
1379 | __le32 vf_eqc_bt_idx_num; | |
cfc85f3e WHX |
1380 | }; |
1381 | ||
1382 | #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0 | |
1383 | #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0) | |
1384 | ||
1385 | #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16 | |
1386 | #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16) | |
1387 | ||
1388 | #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0 | |
1389 | #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0) | |
1390 | ||
1391 | #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16 | |
1392 | #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16) | |
1393 | ||
1394 | #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0 | |
1395 | #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0) | |
1396 | ||
1397 | #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16 | |
1398 | #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16) | |
1399 | ||
1400 | #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0 | |
1401 | #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0) | |
1402 | ||
1403 | #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16 | |
1404 | #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16) | |
1405 | ||
1406 | #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0 | |
1407 | #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0) | |
1408 | ||
1409 | #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16 | |
1410 | #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16) | |
1411 | ||
1412 | struct hns_roce_vf_res_b { | |
8b9b8d14 | 1413 | __le32 rsv0; |
1414 | __le32 vf_smac_idx_num; | |
1415 | __le32 vf_sgid_idx_num; | |
1416 | __le32 vf_qid_idx_sl_num; | |
6a157f7d YL |
1417 | __le32 vf_sccc_idx_num; |
1418 | __le32 rsv1; | |
cfc85f3e WHX |
1419 | }; |
1420 | ||
1421 | #define VF_RES_B_DATA_0_VF_ID_S 0 | |
1422 | #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0) | |
1423 | ||
1424 | #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0 | |
1425 | #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0) | |
1426 | ||
1427 | #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8 | |
1428 | #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8) | |
1429 | ||
1430 | #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0 | |
1431 | #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0) | |
1432 | ||
1433 | #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8 | |
1434 | #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8) | |
1435 | ||
1436 | #define VF_RES_B_DATA_3_VF_QID_IDX_S 0 | |
1437 | #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0) | |
1438 | ||
1439 | #define VF_RES_B_DATA_3_VF_SL_NUM_S 16 | |
1440 | #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16) | |
1441 | ||
6a157f7d YL |
1442 | #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S 0 |
1443 | #define VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M GENMASK(8, 0) | |
1444 | ||
1445 | #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S 9 | |
1446 | #define VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M GENMASK(17, 9) | |
1447 | ||
0c1c3880 LO |
1448 | struct hns_roce_vf_switch { |
1449 | __le32 rocee_sel; | |
1450 | __le32 fun_id; | |
1451 | __le32 cfg; | |
1452 | __le32 resv1; | |
1453 | __le32 resv2; | |
1454 | __le32 resv3; | |
1455 | }; | |
1456 | ||
1457 | #define VF_SWITCH_DATA_FUN_ID_VF_ID_S 3 | |
1458 | #define VF_SWITCH_DATA_FUN_ID_VF_ID_M GENMASK(10, 3) | |
1459 | ||
1460 | #define VF_SWITCH_DATA_CFG_ALW_LPBK_S 1 | |
1461 | #define VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S 2 | |
1462 | #define VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S 3 | |
1463 | ||
f747b689 LO |
1464 | struct hns_roce_post_mbox { |
1465 | __le32 in_param_l; | |
1466 | __le32 in_param_h; | |
1467 | __le32 out_param_l; | |
1468 | __le32 out_param_h; | |
1469 | __le32 cmd_tag; | |
1470 | __le32 token_event_en; | |
1471 | }; | |
1472 | ||
1473 | struct hns_roce_mbox_status { | |
1474 | __le32 mb_status_hw_run; | |
1475 | __le32 rsv[5]; | |
1476 | }; | |
1477 | ||
a81fba28 | 1478 | struct hns_roce_cfg_bt_attr { |
8b9b8d14 | 1479 | __le32 vf_qpc_cfg; |
1480 | __le32 vf_srqc_cfg; | |
1481 | __le32 vf_cqc_cfg; | |
1482 | __le32 vf_mpt_cfg; | |
6a157f7d YL |
1483 | __le32 vf_sccc_cfg; |
1484 | __le32 rsv; | |
a81fba28 WHX |
1485 | }; |
1486 | ||
1487 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0 | |
1488 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0) | |
1489 | ||
1490 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4 | |
1491 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4) | |
1492 | ||
1493 | #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8 | |
1494 | #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8) | |
1495 | ||
1496 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0 | |
1497 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0) | |
1498 | ||
1499 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4 | |
1500 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4) | |
1501 | ||
1502 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8 | |
1503 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8) | |
1504 | ||
1505 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0 | |
1506 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0) | |
1507 | ||
1508 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4 | |
1509 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4) | |
1510 | ||
1511 | #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8 | |
1512 | #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8) | |
1513 | ||
1514 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0 | |
1515 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0) | |
1516 | ||
1517 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4 | |
1518 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4) | |
1519 | ||
1520 | #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8 | |
1521 | #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8) | |
1522 | ||
6a157f7d YL |
1523 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S 0 |
1524 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M GENMASK(3, 0) | |
1525 | ||
1526 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S 4 | |
1527 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M GENMASK(7, 4) | |
1528 | ||
1529 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S 8 | |
1530 | #define CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M GENMASK(9, 8) | |
1531 | ||
4db134a3 | 1532 | struct hns_roce_cfg_sgid_tb { |
1533 | __le32 table_idx_rsv; | |
1534 | __le32 vf_sgid_l; | |
1535 | __le32 vf_sgid_ml; | |
1536 | __le32 vf_sgid_mh; | |
1537 | __le32 vf_sgid_h; | |
1538 | __le32 vf_sgid_type_rsv; | |
1539 | }; | |
1540 | #define CFG_SGID_TB_TABLE_IDX_S 0 | |
1541 | #define CFG_SGID_TB_TABLE_IDX_M GENMASK(7, 0) | |
1542 | ||
1543 | #define CFG_SGID_TB_VF_SGID_TYPE_S 0 | |
1544 | #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0) | |
1545 | ||
e8e8b652 | 1546 | struct hns_roce_cfg_smac_tb { |
1547 | __le32 tb_idx_rsv; | |
1548 | __le32 vf_smac_l; | |
1549 | __le32 vf_smac_h_rsv; | |
1550 | __le32 rsv[3]; | |
1551 | }; | |
1552 | #define CFG_SMAC_TB_IDX_S 0 | |
1553 | #define CFG_SMAC_TB_IDX_M GENMASK(7, 0) | |
1554 | ||
1555 | #define CFG_SMAC_TB_VF_SMAC_H_S 0 | |
1556 | #define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0) | |
1557 | ||
ba6bb7e9 LO |
1558 | #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM 5 |
1559 | struct hns_roce_query_pf_caps_a { | |
1560 | u8 number_ports; | |
1561 | u8 local_ca_ack_delay; | |
1562 | __le16 max_sq_sg; | |
1563 | __le16 max_sq_inline; | |
1564 | __le16 max_rq_sg; | |
1565 | __le32 max_extend_sg; | |
1566 | __le16 num_qpc_timer; | |
1567 | __le16 num_cqc_timer; | |
1568 | __le16 max_srq_sges; | |
1569 | u8 num_aeq_vectors; | |
1570 | u8 num_other_vectors; | |
1571 | u8 max_sq_desc_sz; | |
1572 | u8 max_rq_desc_sz; | |
1573 | u8 max_srq_desc_sz; | |
1574 | u8 cq_entry_sz; | |
1575 | }; | |
1576 | ||
1577 | struct hns_roce_query_pf_caps_b { | |
1578 | u8 mtpt_entry_sz; | |
1579 | u8 irrl_entry_sz; | |
1580 | u8 trrl_entry_sz; | |
1581 | u8 cqc_entry_sz; | |
1582 | u8 srqc_entry_sz; | |
1583 | u8 idx_entry_sz; | |
1584 | u8 scc_ctx_entry_sz; | |
1585 | u8 max_mtu; | |
1586 | __le16 qpc_entry_sz; | |
1587 | __le16 qpc_timer_entry_sz; | |
1588 | __le16 cqc_timer_entry_sz; | |
1589 | u8 min_cqes; | |
1590 | u8 min_wqes; | |
1591 | __le32 page_size_cap; | |
1592 | u8 pkey_table_len; | |
1593 | u8 phy_num_uars; | |
1594 | u8 ctx_hop_num; | |
1595 | u8 pbl_hop_num; | |
1596 | }; | |
1597 | ||
1598 | struct hns_roce_query_pf_caps_c { | |
1599 | __le32 cap_flags_num_pds; | |
1600 | __le32 max_gid_num_cqs; | |
1601 | __le32 cq_depth; | |
1602 | __le32 num_mrws; | |
1603 | __le32 ord_num_qps; | |
1604 | __le16 sq_depth; | |
1605 | __le16 rq_depth; | |
1606 | }; | |
1607 | ||
1608 | #define V2_QUERY_PF_CAPS_C_NUM_PDS_S 0 | |
1609 | #define V2_QUERY_PF_CAPS_C_NUM_PDS_M GENMASK(19, 0) | |
1610 | ||
1611 | #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_S 20 | |
1612 | #define V2_QUERY_PF_CAPS_C_CAP_FLAGS_M GENMASK(31, 20) | |
1613 | ||
1614 | #define V2_QUERY_PF_CAPS_C_NUM_CQS_S 0 | |
1615 | #define V2_QUERY_PF_CAPS_C_NUM_CQS_M GENMASK(19, 0) | |
1616 | ||
1617 | #define V2_QUERY_PF_CAPS_C_MAX_GID_S 20 | |
1618 | #define V2_QUERY_PF_CAPS_C_MAX_GID_M GENMASK(28, 20) | |
1619 | ||
1620 | #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_S 0 | |
1621 | #define V2_QUERY_PF_CAPS_C_CQ_DEPTH_M GENMASK(22, 0) | |
1622 | ||
1623 | #define V2_QUERY_PF_CAPS_C_NUM_MRWS_S 0 | |
1624 | #define V2_QUERY_PF_CAPS_C_NUM_MRWS_M GENMASK(19, 0) | |
1625 | ||
1626 | #define V2_QUERY_PF_CAPS_C_NUM_QPS_S 0 | |
1627 | #define V2_QUERY_PF_CAPS_C_NUM_QPS_M GENMASK(19, 0) | |
1628 | ||
1629 | #define V2_QUERY_PF_CAPS_C_MAX_ORD_S 20 | |
1630 | #define V2_QUERY_PF_CAPS_C_MAX_ORD_M GENMASK(27, 20) | |
1631 | ||
1632 | struct hns_roce_query_pf_caps_d { | |
1633 | __le32 wq_hop_num_max_srqs; | |
1634 | __le16 srq_depth; | |
30661322 | 1635 | __le16 cap_flags_ex; |
ba6bb7e9 LO |
1636 | __le32 num_ceqs_ceq_depth; |
1637 | __le32 arm_st_aeq_depth; | |
1638 | __le32 num_uars_rsv_pds; | |
1639 | __le32 rsv_uars_rsv_qps; | |
1640 | }; | |
1641 | #define V2_QUERY_PF_CAPS_D_NUM_SRQS_S 0 | |
1642 | #define V2_QUERY_PF_CAPS_D_NUM_SRQS_M GENMASK(20, 0) | |
1643 | ||
1644 | #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S 20 | |
1645 | #define V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M GENMASK(21, 20) | |
1646 | ||
1647 | #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S 22 | |
1648 | #define V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M GENMASK(23, 22) | |
1649 | ||
1650 | #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S 24 | |
1651 | #define V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M GENMASK(25, 24) | |
1652 | ||
1653 | ||
1654 | #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S 0 | |
1655 | #define V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M GENMASK(21, 0) | |
1656 | ||
1657 | #define V2_QUERY_PF_CAPS_D_NUM_CEQS_S 22 | |
1658 | #define V2_QUERY_PF_CAPS_D_NUM_CEQS_M GENMASK(31, 22) | |
1659 | ||
1660 | #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S 0 | |
1661 | #define V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M GENMASK(21, 0) | |
1662 | ||
1663 | #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S 22 | |
1664 | #define V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M GENMASK(23, 22) | |
1665 | ||
1666 | #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S 24 | |
1667 | #define V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M GENMASK(25, 24) | |
1668 | ||
1669 | #define V2_QUERY_PF_CAPS_D_RSV_PDS_S 0 | |
1670 | #define V2_QUERY_PF_CAPS_D_RSV_PDS_M GENMASK(19, 0) | |
1671 | ||
1672 | #define V2_QUERY_PF_CAPS_D_NUM_UARS_S 20 | |
1673 | #define V2_QUERY_PF_CAPS_D_NUM_UARS_M GENMASK(27, 20) | |
1674 | ||
1675 | #define V2_QUERY_PF_CAPS_D_RSV_QPS_S 0 | |
1676 | #define V2_QUERY_PF_CAPS_D_RSV_QPS_M GENMASK(19, 0) | |
1677 | ||
1678 | #define V2_QUERY_PF_CAPS_D_RSV_UARS_S 20 | |
1679 | #define V2_QUERY_PF_CAPS_D_RSV_UARS_M GENMASK(27, 20) | |
1680 | ||
1681 | struct hns_roce_query_pf_caps_e { | |
1682 | __le32 chunk_size_shift_rsv_mrws; | |
1683 | __le32 rsv_cqs; | |
1684 | __le32 rsv_srqs; | |
1685 | __le32 rsv_lkey; | |
1686 | __le16 ceq_max_cnt; | |
1687 | __le16 ceq_period; | |
1688 | __le16 aeq_max_cnt; | |
1689 | __le16 aeq_period; | |
1690 | }; | |
1691 | ||
1692 | #define V2_QUERY_PF_CAPS_E_RSV_MRWS_S 0 | |
1693 | #define V2_QUERY_PF_CAPS_E_RSV_MRWS_M GENMASK(19, 0) | |
1694 | ||
1695 | #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S 20 | |
1696 | #define V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M GENMASK(31, 20) | |
1697 | ||
1698 | #define V2_QUERY_PF_CAPS_E_RSV_CQS_S 0 | |
1699 | #define V2_QUERY_PF_CAPS_E_RSV_CQS_M GENMASK(19, 0) | |
1700 | ||
1701 | #define V2_QUERY_PF_CAPS_E_RSV_SRQS_S 0 | |
1702 | #define V2_QUERY_PF_CAPS_E_RSV_SRQS_M GENMASK(19, 0) | |
1703 | ||
1704 | #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_S 0 | |
1705 | #define V2_QUERY_PF_CAPS_E_RSV_LKEYS_M GENMASK(19, 0) | |
1706 | ||
a04ff739 | 1707 | struct hns_roce_cmq_desc { |
8b9b8d14 | 1708 | __le16 opcode; |
1709 | __le16 flag; | |
1710 | __le16 retval; | |
1711 | __le16 rsv; | |
1712 | __le32 data[6]; | |
a04ff739 WHX |
1713 | }; |
1714 | ||
a680f2f3 WHX |
1715 | #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000 |
1716 | ||
1717 | #define HNS_ROCE_HW_RUN_BIT_SHIFT 31 | |
1718 | #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF | |
1719 | ||
a04ff739 WHX |
1720 | struct hns_roce_v2_cmq_ring { |
1721 | dma_addr_t desc_dma_addr; | |
1722 | struct hns_roce_cmq_desc *desc; | |
1723 | u32 head; | |
1724 | u32 tail; | |
1725 | ||
1726 | u16 buf_size; | |
1727 | u16 desc_num; | |
1728 | int next_to_use; | |
1729 | int next_to_clean; | |
1730 | u8 flag; | |
1731 | spinlock_t lock; /* command queue lock */ | |
1732 | }; | |
1733 | ||
1734 | struct hns_roce_v2_cmq { | |
1735 | struct hns_roce_v2_cmq_ring csq; | |
1736 | struct hns_roce_v2_cmq_ring crq; | |
1737 | u16 tx_timeout; | |
1738 | u16 last_status; | |
1739 | }; | |
1740 | ||
6b63597d | 1741 | enum hns_roce_link_table_type { |
1742 | TSQ_LINK_TABLE, | |
ded58ff9 | 1743 | TPQ_LINK_TABLE, |
6b63597d | 1744 | }; |
1745 | ||
1746 | struct hns_roce_link_table { | |
1747 | struct hns_roce_buf_list table; | |
1748 | struct hns_roce_buf_list *pg_list; | |
1749 | u32 npages; | |
1750 | u32 pg_sz; | |
1751 | }; | |
1752 | ||
1753 | struct hns_roce_link_table_entry { | |
1754 | u32 blk_ba0; | |
1755 | u32 blk_ba1_nxt_ptr; | |
1756 | }; | |
1757 | #define HNS_ROCE_LINK_TABLE_BA1_S 0 | |
1758 | #define HNS_ROCE_LINK_TABLE_BA1_M GENMASK(19, 0) | |
1759 | ||
1760 | #define HNS_ROCE_LINK_TABLE_NXT_PTR_S 20 | |
1761 | #define HNS_ROCE_LINK_TABLE_NXT_PTR_M GENMASK(31, 20) | |
1762 | ||
a04ff739 | 1763 | struct hns_roce_v2_priv { |
d061effc | 1764 | struct hnae3_handle *handle; |
a04ff739 | 1765 | struct hns_roce_v2_cmq cmq; |
6b63597d | 1766 | struct hns_roce_link_table tsq; |
ded58ff9 | 1767 | struct hns_roce_link_table tpq; |
a04ff739 WHX |
1768 | }; |
1769 | ||
a5073d60 | 1770 | struct hns_roce_eq_context { |
8b9b8d14 | 1771 | __le32 byte_4; |
1772 | __le32 byte_8; | |
1773 | __le32 byte_12; | |
1774 | __le32 eqe_report_timer; | |
1775 | __le32 eqe_ba0; | |
1776 | __le32 eqe_ba1; | |
1777 | __le32 byte_28; | |
1778 | __le32 byte_32; | |
1779 | __le32 byte_36; | |
1780 | __le32 nxt_eqe_ba0; | |
1781 | __le32 nxt_eqe_ba1; | |
1782 | __le32 rsv[5]; | |
a5073d60 YL |
1783 | }; |
1784 | ||
1785 | #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0 | |
1786 | #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0 | |
1787 | #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0 | |
1788 | #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0 | |
1789 | ||
1790 | #define HNS_ROCE_V2_EQ_STATE_INVALID 0 | |
1791 | #define HNS_ROCE_V2_EQ_STATE_VALID 1 | |
1792 | #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2 | |
1793 | #define HNS_ROCE_V2_EQ_STATE_FAILURE 3 | |
1794 | ||
1795 | #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0 | |
1796 | #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1 | |
1797 | ||
1798 | #define HNS_ROCE_V2_EQ_COALESCE_0 0 | |
1799 | #define HNS_ROCE_V2_EQ_COALESCE_1 1 | |
1800 | ||
1801 | #define HNS_ROCE_V2_EQ_FIRED 0 | |
1802 | #define HNS_ROCE_V2_EQ_ARMED 1 | |
1803 | #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3 | |
1804 | ||
1805 | #define HNS_ROCE_EQ_INIT_EQE_CNT 0 | |
1806 | #define HNS_ROCE_EQ_INIT_PROD_IDX 0 | |
1807 | #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0 | |
1808 | #define HNS_ROCE_EQ_INIT_MSI_IDX 0 | |
1809 | #define HNS_ROCE_EQ_INIT_CONS_IDX 0 | |
1810 | #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0 | |
1811 | ||
1812 | #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31 | |
1813 | #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31 | |
1814 | ||
1815 | #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000 | |
1816 | #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000 | |
1817 | ||
1818 | #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0 | |
1819 | #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1 | |
1820 | #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2 | |
1821 | ||
1822 | #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0 | |
1823 | #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1 | |
1824 | #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2 | |
1825 | #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3 | |
1826 | ||
1827 | #define EQ_ENABLE 1 | |
1828 | #define EQ_DISABLE 0 | |
1829 | ||
1830 | #define EQ_REG_OFFSET 0x4 | |
1831 | ||
1832 | #define HNS_ROCE_INT_NAME_LEN 32 | |
1833 | #define HNS_ROCE_V2_EQN_M GENMASK(23, 0) | |
1834 | ||
1835 | #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0) | |
1836 | ||
1837 | #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0 | |
1838 | #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0) | |
1839 | #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0) | |
1840 | #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0) | |
1841 | #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0) | |
1842 | ||
1843 | /* WORD0 */ | |
1844 | #define HNS_ROCE_EQC_EQ_ST_S 0 | |
1845 | #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0) | |
1846 | ||
1847 | #define HNS_ROCE_EQC_HOP_NUM_S 2 | |
1848 | #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2) | |
1849 | ||
1850 | #define HNS_ROCE_EQC_OVER_IGNORE_S 4 | |
1851 | #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4) | |
1852 | ||
1853 | #define HNS_ROCE_EQC_COALESCE_S 5 | |
1854 | #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5) | |
1855 | ||
1856 | #define HNS_ROCE_EQC_ARM_ST_S 6 | |
1857 | #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6) | |
1858 | ||
1859 | #define HNS_ROCE_EQC_EQN_S 8 | |
1860 | #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8) | |
1861 | ||
1862 | #define HNS_ROCE_EQC_EQE_CNT_S 16 | |
1863 | #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16) | |
1864 | ||
1865 | /* WORD1 */ | |
1866 | #define HNS_ROCE_EQC_BA_PG_SZ_S 0 | |
1867 | #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0) | |
1868 | ||
1869 | #define HNS_ROCE_EQC_BUF_PG_SZ_S 4 | |
1870 | #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4) | |
1871 | ||
1872 | #define HNS_ROCE_EQC_PROD_INDX_S 8 | |
1873 | #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8) | |
1874 | ||
1875 | /* WORD2 */ | |
1876 | #define HNS_ROCE_EQC_MAX_CNT_S 0 | |
1877 | #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0) | |
1878 | ||
1879 | #define HNS_ROCE_EQC_PERIOD_S 16 | |
1880 | #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16) | |
1881 | ||
1882 | /* WORD3 */ | |
1883 | #define HNS_ROCE_EQC_REPORT_TIMER_S 0 | |
1884 | #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0) | |
1885 | ||
1886 | /* WORD4 */ | |
1887 | #define HNS_ROCE_EQC_EQE_BA_L_S 0 | |
1888 | #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0) | |
1889 | ||
1890 | /* WORD5 */ | |
1891 | #define HNS_ROCE_EQC_EQE_BA_H_S 0 | |
1892 | #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0) | |
1893 | ||
1894 | /* WORD6 */ | |
1895 | #define HNS_ROCE_EQC_SHIFT_S 0 | |
1896 | #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0) | |
1897 | ||
1898 | #define HNS_ROCE_EQC_MSI_INDX_S 8 | |
1899 | #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8) | |
1900 | ||
1901 | #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16 | |
1902 | #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16) | |
1903 | ||
1904 | /* WORD7 */ | |
1905 | #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0 | |
1906 | #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0) | |
1907 | ||
1908 | /* WORD8 */ | |
1909 | #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0 | |
1910 | #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0) | |
1911 | ||
1912 | #define HNS_ROCE_EQC_CONS_INDX_S 8 | |
1913 | #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8) | |
1914 | ||
1915 | /* WORD9 */ | |
1916 | #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0 | |
1917 | #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0) | |
1918 | ||
1919 | /* WORD10 */ | |
1920 | #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0 | |
1921 | #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0) | |
1922 | ||
1923 | #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0 | |
1924 | #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0) | |
1925 | ||
1926 | #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0 | |
1927 | #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0) | |
1928 | ||
1929 | #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8 | |
1930 | #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8) | |
1931 | ||
1932 | #define HNS_ROCE_V2_EQ_DB_CMD_S 16 | |
1933 | #define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16) | |
1934 | ||
1935 | #define HNS_ROCE_V2_EQ_DB_TAG_S 0 | |
1936 | #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0) | |
1937 | ||
1938 | #define HNS_ROCE_V2_EQ_DB_PARA_S 0 | |
1939 | #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0) | |
1940 | ||
1941 | #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0 | |
1942 | #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0) | |
1943 | ||
384f8818 LO |
1944 | struct hns_roce_wqe_atomic_seg { |
1945 | __le64 fetchadd_swap_data; | |
1946 | __le64 cmp_data; | |
1947 | }; | |
1948 | ||
aa84fa18 YL |
1949 | struct hns_roce_sccc_clr { |
1950 | __le32 qpn; | |
1951 | __le32 rsv[5]; | |
1952 | }; | |
1953 | ||
1954 | struct hns_roce_sccc_clr_done { | |
1955 | __le32 clr_done; | |
1956 | __le32 rsv[5]; | |
1957 | }; | |
1958 | ||
e1c9a0dc LO |
1959 | int hns_roce_v2_query_cqc_info(struct hns_roce_dev *hr_dev, u32 cqn, |
1960 | int *buffer); | |
1961 | ||
d3743fa9 WHX |
1962 | static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2], |
1963 | void __iomem *dest) | |
1964 | { | |
14ba8730 | 1965 | struct hns_roce_v2_priv *priv = hr_dev->priv; |
d3743fa9 WHX |
1966 | struct hnae3_handle *handle = priv->handle; |
1967 | const struct hnae3_ae_ops *ops = handle->ae_algo->ops; | |
1968 | ||
1969 | if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) | |
1970 | hns_roce_write64_k(val, dest); | |
1971 | } | |
1972 | ||
a04ff739 | 1973 | #endif |