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a04ff739 WHX |
1 | /* |
2 | * Copyright (c) 2016-2017 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef _HNS_ROCE_HW_V2_H | |
34 | #define _HNS_ROCE_HW_V2_H | |
35 | ||
cfc85f3e WHX |
36 | #include <linux/bitops.h> |
37 | ||
38 | #define HNS_ROCE_VF_QPC_BT_NUM 256 | |
39 | #define HNS_ROCE_VF_SRQC_BT_NUM 64 | |
40 | #define HNS_ROCE_VF_CQC_BT_NUM 64 | |
41 | #define HNS_ROCE_VF_MPT_BT_NUM 64 | |
42 | #define HNS_ROCE_VF_EQC_NUM 64 | |
43 | #define HNS_ROCE_VF_SMAC_NUM 32 | |
44 | #define HNS_ROCE_VF_SGID_NUM 32 | |
45 | #define HNS_ROCE_VF_SL_NUM 8 | |
46 | ||
47 | #define HNS_ROCE_V2_MAX_QP_NUM 0x2000 | |
48 | #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000 | |
49 | #define HNS_ROCE_V2_MAX_CQ_NUM 0x8000 | |
3180236c | 50 | #define HNS_ROCE_V2_MAX_CQE_NUM 0x10000 |
cfc85f3e WHX |
51 | #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100 |
52 | #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff | |
53 | #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 | |
54 | #define HNS_ROCE_V2_UAR_NUM 256 | |
55 | #define HNS_ROCE_V2_PHY_UAR_NUM 1 | |
a5073d60 YL |
56 | #define HNS_ROCE_V2_MAX_IRQ_NUM 65 |
57 | #define HNS_ROCE_V2_COMP_VEC_NUM 63 | |
58 | #define HNS_ROCE_V2_AEQE_VEC_NUM 1 | |
59 | #define HNS_ROCE_V2_ABNORMAL_VEC_NUM 1 | |
cfc85f3e | 60 | #define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000 |
3180236c WHX |
61 | #define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000 |
62 | #define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000 | |
63 | #define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 | |
cfc85f3e WHX |
64 | #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 |
65 | #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 | |
66 | #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 | |
67 | #define HNS_ROCE_V2_MAX_RQ_DESC_SZ 16 | |
68 | #define HNS_ROCE_V2_MAX_SRQ_DESC_SZ 64 | |
69 | #define HNS_ROCE_V2_QPC_ENTRY_SZ 256 | |
70 | #define HNS_ROCE_V2_IRRL_ENTRY_SZ 64 | |
e92f2c18 | 71 | #define HNS_ROCE_V2_TRRL_ENTRY_SZ 48 |
cfc85f3e WHX |
72 | #define HNS_ROCE_V2_CQC_ENTRY_SZ 64 |
73 | #define HNS_ROCE_V2_MTPT_ENTRY_SZ 64 | |
74 | #define HNS_ROCE_V2_MTT_ENTRY_SZ 64 | |
75 | #define HNS_ROCE_V2_CQE_ENTRY_SIZE 32 | |
76 | #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000 | |
77 | #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2 | |
2d407888 | 78 | #define HNS_ROCE_INVALID_LKEY 0x100 |
d59fcacc | 79 | #define HNS_ROCE_CMQ_TX_TIMEOUT 30000 |
0b25c9cc | 80 | #define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2 |
a04ff739 | 81 | |
a25d13cb SX |
82 | #define HNS_ROCE_CONTEXT_HOP_NUM 1 |
83 | #define HNS_ROCE_MTT_HOP_NUM 1 | |
6a93c77a | 84 | #define HNS_ROCE_CQE_HOP_NUM 1 |
ff795f71 | 85 | #define HNS_ROCE_PBL_HOP_NUM 2 |
a5073d60 YL |
86 | #define HNS_ROCE_EQE_HOP_NUM 2 |
87 | ||
b5ff0f61 | 88 | #define HNS_ROCE_V2_GID_INDEX_NUM 256 |
a25d13cb | 89 | |
29a1fe5d WHX |
90 | #define HNS_ROCE_V2_TABLE_CHUNK_SIZE (1 << 18) |
91 | ||
a04ff739 WHX |
92 | #define HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT 0 |
93 | #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1 | |
94 | #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2 | |
95 | #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3 | |
96 | #define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4 | |
97 | #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5 | |
98 | ||
99 | #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT) | |
100 | #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT) | |
101 | #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT) | |
102 | #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT) | |
103 | #define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT) | |
104 | #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT) | |
105 | ||
106 | #define HNS_ROCE_CMQ_DESC_NUM_S 3 | |
107 | #define HNS_ROCE_CMQ_EN_B 16 | |
108 | #define HNS_ROCE_CMQ_ENABLE BIT(HNS_ROCE_CMQ_EN_B) | |
109 | ||
a81fba28 WHX |
110 | #define check_whether_last_step(hop_num, step_idx) \ |
111 | ((step_idx == 0 && hop_num == HNS_ROCE_HOP_NUM_0) || \ | |
112 | (step_idx == 1 && hop_num == 1) || \ | |
113 | (step_idx == 2 && hop_num == 2)) | |
114 | ||
a5073d60 YL |
115 | enum { |
116 | NO_ARMED = 0x0, | |
117 | REG_NXT_CEQE = 0x2, | |
118 | REG_NXT_SE_CEQE = 0x3 | |
119 | }; | |
120 | ||
93aa2187 WHX |
121 | #define V2_CQ_DB_REQ_NOT_SOL 0 |
122 | #define V2_CQ_DB_REQ_NOT 1 | |
123 | ||
124 | #define V2_CQ_STATE_VALID 1 | |
926a01dc WHX |
125 | #define V2_QKEY_VAL 0x80010000 |
126 | ||
127 | #define GID_LEN_V2 16 | |
93aa2187 WHX |
128 | |
129 | #define HNS_ROCE_V2_CQE_QPN_MASK 0x3ffff | |
130 | ||
2d407888 WHX |
131 | enum { |
132 | HNS_ROCE_V2_WQE_OP_SEND = 0x0, | |
133 | HNS_ROCE_V2_WQE_OP_SEND_WITH_INV = 0x1, | |
134 | HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM = 0x2, | |
135 | HNS_ROCE_V2_WQE_OP_RDMA_WRITE = 0x3, | |
136 | HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM = 0x4, | |
137 | HNS_ROCE_V2_WQE_OP_RDMA_READ = 0x5, | |
138 | HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP = 0x6, | |
139 | HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD = 0x7, | |
140 | HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP = 0x8, | |
141 | HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD = 0x9, | |
142 | HNS_ROCE_V2_WQE_OP_FAST_REG_PMR = 0xa, | |
143 | HNS_ROCE_V2_WQE_OP_LOCAL_INV = 0xb, | |
144 | HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE = 0xc, | |
145 | HNS_ROCE_V2_WQE_OP_MASK = 0x1f, | |
146 | }; | |
147 | ||
93aa2187 WHX |
148 | enum { |
149 | HNS_ROCE_SQ_OPCODE_SEND = 0x0, | |
150 | HNS_ROCE_SQ_OPCODE_SEND_WITH_INV = 0x1, | |
151 | HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM = 0x2, | |
152 | HNS_ROCE_SQ_OPCODE_RDMA_WRITE = 0x3, | |
153 | HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM = 0x4, | |
154 | HNS_ROCE_SQ_OPCODE_RDMA_READ = 0x5, | |
155 | HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP = 0x6, | |
156 | HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD = 0x7, | |
157 | HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP = 0x8, | |
158 | HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD = 0x9, | |
159 | HNS_ROCE_SQ_OPCODE_FAST_REG_WR = 0xa, | |
160 | HNS_ROCE_SQ_OPCODE_LOCAL_INV = 0xb, | |
161 | HNS_ROCE_SQ_OPCODE_BIND_MW = 0xc, | |
162 | }; | |
163 | ||
164 | enum { | |
165 | /* rq operations */ | |
166 | HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM = 0x0, | |
167 | HNS_ROCE_V2_OPCODE_SEND = 0x1, | |
168 | HNS_ROCE_V2_OPCODE_SEND_WITH_IMM = 0x2, | |
169 | HNS_ROCE_V2_OPCODE_SEND_WITH_INV = 0x3, | |
170 | }; | |
171 | ||
172 | enum { | |
2d407888 WHX |
173 | HNS_ROCE_V2_SQ_DB = 0x0, |
174 | HNS_ROCE_V2_RQ_DB = 0x1, | |
175 | HNS_ROCE_V2_SRQ_DB = 0x2, | |
93aa2187 WHX |
176 | HNS_ROCE_V2_CQ_DB_PTR = 0x3, |
177 | HNS_ROCE_V2_CQ_DB_NTR = 0x4, | |
178 | }; | |
179 | ||
180 | enum { | |
181 | HNS_ROCE_CQE_V2_SUCCESS = 0x00, | |
182 | HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR = 0x01, | |
183 | HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR = 0x02, | |
184 | HNS_ROCE_CQE_V2_LOCAL_PROT_ERR = 0x04, | |
185 | HNS_ROCE_CQE_V2_WR_FLUSH_ERR = 0x05, | |
186 | HNS_ROCE_CQE_V2_MW_BIND_ERR = 0x06, | |
187 | HNS_ROCE_CQE_V2_BAD_RESP_ERR = 0x10, | |
188 | HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR = 0x11, | |
189 | HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR = 0x12, | |
190 | HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR = 0x13, | |
191 | HNS_ROCE_CQE_V2_REMOTE_OP_ERR = 0x14, | |
192 | HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR = 0x15, | |
193 | HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR = 0x16, | |
194 | HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR = 0x22, | |
195 | ||
196 | HNS_ROCE_V2_CQE_STATUS_MASK = 0xff, | |
197 | }; | |
198 | ||
a04ff739 WHX |
199 | /* CMQ command */ |
200 | enum hns_roce_opcode_type { | |
201 | HNS_ROCE_OPC_QUERY_HW_VER = 0x8000, | |
202 | HNS_ROCE_OPC_CFG_GLOBAL_PARAM = 0x8001, | |
203 | HNS_ROCE_OPC_ALLOC_PF_RES = 0x8004, | |
204 | HNS_ROCE_OPC_QUERY_PF_RES = 0x8400, | |
205 | HNS_ROCE_OPC_ALLOC_VF_RES = 0x8401, | |
206 | HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506, | |
207 | }; | |
208 | ||
209 | enum { | |
210 | TYPE_CRQ, | |
211 | TYPE_CSQ, | |
212 | }; | |
213 | ||
214 | enum hns_roce_cmd_return_status { | |
215 | CMD_EXEC_SUCCESS = 0, | |
216 | CMD_NO_AUTH = 1, | |
217 | CMD_NOT_EXEC = 2, | |
218 | CMD_QUEUE_FULL = 3, | |
219 | }; | |
220 | ||
b5ff0f61 WHX |
221 | enum hns_roce_sgid_type { |
222 | GID_TYPE_FLAG_ROCE_V1 = 0, | |
223 | GID_TYPE_FLAG_ROCE_V2_IPV4, | |
224 | GID_TYPE_FLAG_ROCE_V2_IPV6, | |
225 | }; | |
226 | ||
93aa2187 | 227 | struct hns_roce_v2_cq_context { |
8b9b8d14 | 228 | __le32 byte_4_pg_ceqn; |
229 | __le32 byte_8_cqn; | |
230 | __le32 cqe_cur_blk_addr; | |
231 | __le32 byte_16_hop_addr; | |
232 | __le32 cqe_nxt_blk_addr; | |
233 | __le32 byte_24_pgsz_addr; | |
234 | __le32 byte_28_cq_pi; | |
235 | __le32 byte_32_cq_ci; | |
236 | __le32 cqe_ba; | |
237 | __le32 byte_40_cqe_ba; | |
238 | __le32 byte_44_db_record; | |
239 | __le32 db_record_addr; | |
240 | __le32 byte_52_cqe_cnt; | |
241 | __le32 byte_56_cqe_period_maxcnt; | |
242 | __le32 cqe_report_timer; | |
243 | __le32 byte_64_se_cqe_idx; | |
93aa2187 | 244 | }; |
a5073d60 YL |
245 | #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM 0x0 |
246 | #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL 0x0 | |
247 | ||
93aa2187 WHX |
248 | #define V2_CQC_BYTE_4_CQ_ST_S 0 |
249 | #define V2_CQC_BYTE_4_CQ_ST_M GENMASK(1, 0) | |
250 | ||
251 | #define V2_CQC_BYTE_4_POLL_S 2 | |
252 | ||
253 | #define V2_CQC_BYTE_4_SE_S 3 | |
254 | ||
255 | #define V2_CQC_BYTE_4_OVER_IGNORE_S 4 | |
256 | ||
257 | #define V2_CQC_BYTE_4_COALESCE_S 5 | |
258 | ||
259 | #define V2_CQC_BYTE_4_ARM_ST_S 6 | |
260 | #define V2_CQC_BYTE_4_ARM_ST_M GENMASK(7, 6) | |
261 | ||
262 | #define V2_CQC_BYTE_4_SHIFT_S 8 | |
263 | #define V2_CQC_BYTE_4_SHIFT_M GENMASK(12, 8) | |
264 | ||
265 | #define V2_CQC_BYTE_4_CMD_SN_S 13 | |
266 | #define V2_CQC_BYTE_4_CMD_SN_M GENMASK(14, 13) | |
267 | ||
268 | #define V2_CQC_BYTE_4_CEQN_S 15 | |
269 | #define V2_CQC_BYTE_4_CEQN_M GENMASK(23, 15) | |
270 | ||
271 | #define V2_CQC_BYTE_4_PAGE_OFFSET_S 24 | |
272 | #define V2_CQC_BYTE_4_PAGE_OFFSET_M GENMASK(31, 24) | |
273 | ||
274 | #define V2_CQC_BYTE_8_CQN_S 0 | |
275 | #define V2_CQC_BYTE_8_CQN_M GENMASK(23, 0) | |
276 | ||
277 | #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S 0 | |
278 | #define V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M GENMASK(19, 0) | |
279 | ||
280 | #define V2_CQC_BYTE_16_CQE_HOP_NUM_S 30 | |
281 | #define V2_CQC_BYTE_16_CQE_HOP_NUM_M GENMASK(31, 30) | |
282 | ||
283 | #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S 0 | |
284 | #define V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M GENMASK(19, 0) | |
285 | ||
286 | #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_S 24 | |
287 | #define V2_CQC_BYTE_24_CQE_BA_PG_SZ_M GENMASK(27, 24) | |
288 | ||
289 | #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S 28 | |
290 | #define V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M GENMASK(31, 28) | |
291 | ||
292 | #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S 0 | |
293 | #define V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M GENMASK(23, 0) | |
294 | ||
295 | #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S 0 | |
296 | #define V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M GENMASK(23, 0) | |
297 | ||
298 | #define V2_CQC_BYTE_40_CQE_BA_S 0 | |
299 | #define V2_CQC_BYTE_40_CQE_BA_M GENMASK(28, 0) | |
300 | ||
301 | #define V2_CQC_BYTE_44_DB_RECORD_EN_S 0 | |
302 | ||
9b44703d YL |
303 | #define V2_CQC_BYTE_44_DB_RECORD_ADDR_S 1 |
304 | #define V2_CQC_BYTE_44_DB_RECORD_ADDR_M GENMASK(31, 1) | |
305 | ||
93aa2187 WHX |
306 | #define V2_CQC_BYTE_52_CQE_CNT_S 0 |
307 | #define V2_CQC_BYTE_52_CQE_CNT_M GENMASK(23, 0) | |
308 | ||
309 | #define V2_CQC_BYTE_56_CQ_MAX_CNT_S 0 | |
310 | #define V2_CQC_BYTE_56_CQ_MAX_CNT_M GENMASK(15, 0) | |
311 | ||
312 | #define V2_CQC_BYTE_56_CQ_PERIOD_S 16 | |
313 | #define V2_CQC_BYTE_56_CQ_PERIOD_M GENMASK(31, 16) | |
314 | ||
315 | #define V2_CQC_BYTE_64_SE_CQE_IDX_S 0 | |
316 | #define V2_CQC_BYTE_64_SE_CQE_IDX_M GENMASK(23, 0) | |
317 | ||
926a01dc WHX |
318 | enum{ |
319 | V2_MPT_ST_VALID = 0x1, | |
320 | }; | |
321 | ||
322 | enum hns_roce_v2_qp_state { | |
323 | HNS_ROCE_QP_ST_RST, | |
324 | HNS_ROCE_QP_ST_INIT, | |
325 | HNS_ROCE_QP_ST_RTR, | |
326 | HNS_ROCE_QP_ST_RTS, | |
327 | HNS_ROCE_QP_ST_SQER, | |
328 | HNS_ROCE_QP_ST_SQD, | |
329 | HNS_ROCE_QP_ST_ERR, | |
330 | HNS_ROCE_QP_ST_SQ_DRAINING, | |
331 | HNS_ROCE_QP_NUM_ST | |
332 | }; | |
333 | ||
334 | struct hns_roce_v2_qp_context { | |
8b9b8d14 | 335 | __le32 byte_4_sqpn_tst; |
336 | __le32 wqe_sge_ba; | |
337 | __le32 byte_12_sq_hop; | |
338 | __le32 byte_16_buf_ba_pg_sz; | |
339 | __le32 byte_20_smac_sgid_idx; | |
340 | __le32 byte_24_mtu_tc; | |
341 | __le32 byte_28_at_fl; | |
926a01dc | 342 | u8 dgid[GID_LEN_V2]; |
8b9b8d14 | 343 | __le32 dmac; |
344 | __le32 byte_52_udpspn_dmac; | |
345 | __le32 byte_56_dqpn_err; | |
346 | __le32 byte_60_qpst_mapid; | |
347 | __le32 qkey_xrcd; | |
348 | __le32 byte_68_rq_db; | |
349 | __le32 rq_db_record_addr; | |
350 | __le32 byte_76_srqn_op_en; | |
351 | __le32 byte_80_rnr_rx_cqn; | |
352 | __le32 byte_84_rq_ci_pi; | |
353 | __le32 rq_cur_blk_addr; | |
354 | __le32 byte_92_srq_info; | |
355 | __le32 byte_96_rx_reqmsn; | |
356 | __le32 rq_nxt_blk_addr; | |
357 | __le32 byte_104_rq_sge; | |
358 | __le32 byte_108_rx_reqepsn; | |
359 | __le32 rq_rnr_timer; | |
360 | __le32 rx_msg_len; | |
361 | __le32 rx_rkey_pkt_info; | |
362 | __le64 rx_va; | |
363 | __le32 byte_132_trrl; | |
364 | __le32 trrl_ba; | |
365 | __le32 byte_140_raq; | |
366 | __le32 byte_144_raq; | |
367 | __le32 byte_148_raq; | |
368 | __le32 byte_152_raq; | |
369 | __le32 byte_156_raq; | |
370 | __le32 byte_160_sq_ci_pi; | |
371 | __le32 sq_cur_blk_addr; | |
372 | __le32 byte_168_irrl_idx; | |
373 | __le32 byte_172_sq_psn; | |
374 | __le32 byte_176_msg_pktn; | |
375 | __le32 sq_cur_sge_blk_addr; | |
376 | __le32 byte_184_irrl_idx; | |
377 | __le32 cur_sge_offset; | |
378 | __le32 byte_192_ext_sge; | |
379 | __le32 byte_196_sq_psn; | |
380 | __le32 byte_200_sq_max; | |
381 | __le32 irrl_ba; | |
382 | __le32 byte_208_irrl; | |
383 | __le32 byte_212_lsn; | |
384 | __le32 sq_timer; | |
385 | __le32 byte_220_retry_psn_msn; | |
386 | __le32 byte_224_retry_msg; | |
387 | __le32 rx_sq_cur_blk_addr; | |
388 | __le32 byte_232_irrl_sge; | |
389 | __le32 irrl_cur_sge_offset; | |
390 | __le32 byte_240_irrl_tail; | |
391 | __le32 byte_244_rnr_rxack; | |
392 | __le32 byte_248_ack_psn; | |
393 | __le32 byte_252_err_txcqn; | |
394 | __le32 byte_256_sqflush_rqcqe; | |
926a01dc WHX |
395 | }; |
396 | ||
397 | #define V2_QPC_BYTE_4_TST_S 0 | |
398 | #define V2_QPC_BYTE_4_TST_M GENMASK(2, 0) | |
399 | ||
400 | #define V2_QPC_BYTE_4_SGE_SHIFT_S 3 | |
401 | #define V2_QPC_BYTE_4_SGE_SHIFT_M GENMASK(7, 3) | |
402 | ||
403 | #define V2_QPC_BYTE_4_SQPN_S 8 | |
404 | #define V2_QPC_BYTE_4_SQPN_M GENMASK(31, 8) | |
405 | ||
406 | #define V2_QPC_BYTE_12_WQE_SGE_BA_S 0 | |
407 | #define V2_QPC_BYTE_12_WQE_SGE_BA_M GENMASK(28, 0) | |
408 | ||
409 | #define V2_QPC_BYTE_12_SQ_HOP_NUM_S 29 | |
410 | #define V2_QPC_BYTE_12_SQ_HOP_NUM_M GENMASK(30, 29) | |
411 | ||
412 | #define V2_QPC_BYTE_12_RSVD_LKEY_EN_S 31 | |
413 | ||
414 | #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S 0 | |
415 | #define V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M GENMASK(3, 0) | |
416 | ||
417 | #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S 4 | |
418 | #define V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M GENMASK(7, 4) | |
419 | ||
420 | #define V2_QPC_BYTE_16_PD_S 8 | |
421 | #define V2_QPC_BYTE_16_PD_M GENMASK(31, 8) | |
422 | ||
423 | #define V2_QPC_BYTE_20_RQ_HOP_NUM_S 0 | |
424 | #define V2_QPC_BYTE_20_RQ_HOP_NUM_M GENMASK(1, 0) | |
425 | ||
426 | #define V2_QPC_BYTE_20_SGE_HOP_NUM_S 2 | |
427 | #define V2_QPC_BYTE_20_SGE_HOP_NUM_M GENMASK(3, 2) | |
428 | ||
429 | #define V2_QPC_BYTE_20_RQWS_S 4 | |
430 | #define V2_QPC_BYTE_20_RQWS_M GENMASK(7, 4) | |
431 | ||
432 | #define V2_QPC_BYTE_20_SQ_SHIFT_S 8 | |
433 | #define V2_QPC_BYTE_20_SQ_SHIFT_M GENMASK(11, 8) | |
434 | ||
435 | #define V2_QPC_BYTE_20_RQ_SHIFT_S 12 | |
436 | #define V2_QPC_BYTE_20_RQ_SHIFT_M GENMASK(15, 12) | |
437 | ||
438 | #define V2_QPC_BYTE_20_SGID_IDX_S 16 | |
439 | #define V2_QPC_BYTE_20_SGID_IDX_M GENMASK(23, 16) | |
440 | ||
441 | #define V2_QPC_BYTE_20_SMAC_IDX_S 24 | |
442 | #define V2_QPC_BYTE_20_SMAC_IDX_M GENMASK(31, 24) | |
443 | ||
444 | #define V2_QPC_BYTE_24_HOP_LIMIT_S 0 | |
445 | #define V2_QPC_BYTE_24_HOP_LIMIT_M GENMASK(7, 0) | |
446 | ||
447 | #define V2_QPC_BYTE_24_TC_S 8 | |
448 | #define V2_QPC_BYTE_24_TC_M GENMASK(15, 8) | |
449 | ||
450 | #define V2_QPC_BYTE_24_VLAN_IDX_S 16 | |
451 | #define V2_QPC_BYTE_24_VLAN_IDX_M GENMASK(27, 16) | |
452 | ||
453 | #define V2_QPC_BYTE_24_MTU_S 28 | |
454 | #define V2_QPC_BYTE_24_MTU_M GENMASK(31, 28) | |
455 | ||
456 | #define V2_QPC_BYTE_28_FL_S 0 | |
457 | #define V2_QPC_BYTE_28_FL_M GENMASK(19, 0) | |
458 | ||
459 | #define V2_QPC_BYTE_28_SL_S 20 | |
460 | #define V2_QPC_BYTE_28_SL_M GENMASK(23, 20) | |
461 | ||
462 | #define V2_QPC_BYTE_28_CNP_TX_FLAG_S 24 | |
463 | ||
464 | #define V2_QPC_BYTE_28_CE_FLAG_S 25 | |
465 | ||
466 | #define V2_QPC_BYTE_28_LBI_S 26 | |
467 | ||
468 | #define V2_QPC_BYTE_28_AT_S 27 | |
469 | #define V2_QPC_BYTE_28_AT_M GENMASK(31, 27) | |
470 | ||
471 | #define V2_QPC_BYTE_52_DMAC_S 0 | |
472 | #define V2_QPC_BYTE_52_DMAC_M GENMASK(15, 0) | |
473 | ||
474 | #define V2_QPC_BYTE_52_UDPSPN_S 16 | |
475 | #define V2_QPC_BYTE_52_UDPSPN_M GENMASK(31, 16) | |
476 | ||
477 | #define V2_QPC_BYTE_56_DQPN_S 0 | |
478 | #define V2_QPC_BYTE_56_DQPN_M GENMASK(23, 0) | |
479 | ||
480 | #define V2_QPC_BYTE_56_SQ_TX_ERR_S 24 | |
481 | #define V2_QPC_BYTE_56_SQ_RX_ERR_S 25 | |
482 | #define V2_QPC_BYTE_56_RQ_TX_ERR_S 26 | |
483 | #define V2_QPC_BYTE_56_RQ_RX_ERR_S 27 | |
484 | ||
485 | #define V2_QPC_BYTE_56_LP_PKTN_INI_S 28 | |
486 | #define V2_QPC_BYTE_56_LP_PKTN_INI_M GENMASK(31, 28) | |
487 | ||
488 | #define V2_QPC_BYTE_60_MAPID_S 0 | |
489 | #define V2_QPC_BYTE_60_MAPID_M GENMASK(12, 0) | |
490 | ||
491 | #define V2_QPC_BYTE_60_INNER_MAP_IND_S 13 | |
492 | ||
493 | #define V2_QPC_BYTE_60_SQ_MAP_IND_S 14 | |
494 | ||
495 | #define V2_QPC_BYTE_60_RQ_MAP_IND_S 15 | |
496 | ||
497 | #define V2_QPC_BYTE_60_TEMPID_S 16 | |
498 | #define V2_QPC_BYTE_60_TEMPID_M GENMASK(22, 16) | |
499 | ||
500 | #define V2_QPC_BYTE_60_EXT_MAP_IND_S 23 | |
501 | ||
502 | #define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S 24 | |
503 | #define V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M GENMASK(26, 24) | |
504 | ||
505 | #define V2_QPC_BYTE_60_SQ_RLS_IND_S 27 | |
506 | ||
507 | #define V2_QPC_BYTE_60_SQ_EXT_IND_S 28 | |
508 | ||
509 | #define V2_QPC_BYTE_60_QP_ST_S 29 | |
510 | #define V2_QPC_BYTE_60_QP_ST_M GENMASK(31, 29) | |
511 | ||
512 | #define V2_QPC_BYTE_68_RQ_RECORD_EN_S 0 | |
513 | ||
514 | #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S 1 | |
515 | #define V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M GENMASK(31, 1) | |
516 | ||
517 | #define V2_QPC_BYTE_76_SRQN_S 0 | |
518 | #define V2_QPC_BYTE_76_SRQN_M GENMASK(23, 0) | |
519 | ||
520 | #define V2_QPC_BYTE_76_SRQ_EN_S 24 | |
521 | ||
522 | #define V2_QPC_BYTE_76_RRE_S 25 | |
523 | ||
524 | #define V2_QPC_BYTE_76_RWE_S 26 | |
525 | ||
526 | #define V2_QPC_BYTE_76_ATE_S 27 | |
527 | ||
528 | #define V2_QPC_BYTE_76_RQIE_S 28 | |
529 | ||
530 | #define V2_QPC_BYTE_80_RX_CQN_S 0 | |
531 | #define V2_QPC_BYTE_80_RX_CQN_M GENMASK(23, 0) | |
532 | ||
533 | #define V2_QPC_BYTE_80_MIN_RNR_TIME_S 27 | |
534 | #define V2_QPC_BYTE_80_MIN_RNR_TIME_M GENMASK(31, 27) | |
535 | ||
536 | #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S 0 | |
537 | #define V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M GENMASK(15, 0) | |
538 | ||
539 | #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S 16 | |
540 | #define V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M GENMASK(31, 16) | |
541 | ||
542 | #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S 0 | |
543 | #define V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
544 | ||
545 | #define V2_QPC_BYTE_92_SRQ_INFO_S 20 | |
546 | #define V2_QPC_BYTE_92_SRQ_INFO_M GENMASK(31, 20) | |
547 | ||
548 | #define V2_QPC_BYTE_96_RX_REQ_MSN_S 0 | |
549 | #define V2_QPC_BYTE_96_RX_REQ_MSN_M GENMASK(23, 0) | |
550 | ||
551 | #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S 0 | |
552 | #define V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M GENMASK(19, 0) | |
553 | ||
554 | #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S 24 | |
555 | #define V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M GENMASK(31, 24) | |
556 | ||
557 | #define V2_QPC_BYTE_108_INV_CREDIT_S 0 | |
558 | ||
559 | #define V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S 3 | |
560 | ||
561 | #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S 4 | |
562 | #define V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M GENMASK(6, 4) | |
563 | ||
564 | #define V2_QPC_BYTE_108_RX_REQ_RNR_S 7 | |
565 | ||
566 | #define V2_QPC_BYTE_108_RX_REQ_EPSN_S 8 | |
567 | #define V2_QPC_BYTE_108_RX_REQ_EPSN_M GENMASK(31, 8) | |
568 | ||
569 | #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_S 0 | |
570 | #define V2_QPC_BYTE_132_TRRL_HEAD_MAX_M GENMASK(7, 0) | |
571 | ||
572 | #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_S 8 | |
573 | #define V2_QPC_BYTE_132_TRRL_TAIL_MAX_M GENMASK(15, 8) | |
574 | ||
575 | #define V2_QPC_BYTE_132_TRRL_BA_S 16 | |
576 | #define V2_QPC_BYTE_132_TRRL_BA_M GENMASK(31, 16) | |
577 | ||
578 | #define V2_QPC_BYTE_140_TRRL_BA_S 0 | |
579 | #define V2_QPC_BYTE_140_TRRL_BA_M GENMASK(11, 0) | |
580 | ||
581 | #define V2_QPC_BYTE_140_RR_MAX_S 12 | |
582 | #define V2_QPC_BYTE_140_RR_MAX_M GENMASK(14, 12) | |
583 | ||
584 | #define V2_QPC_BYTE_140_RSVD_RAQ_MAP_S 15 | |
585 | ||
586 | #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S 16 | |
587 | #define V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M GENMASK(23, 16) | |
588 | ||
589 | #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S 24 | |
590 | #define V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M GENMASK(31, 24) | |
591 | ||
592 | #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S 0 | |
593 | #define V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M GENMASK(23, 0) | |
594 | ||
595 | #define V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S 24 | |
596 | ||
597 | #define V2_QPC_BYTE_144_RAQ_CREDIT_S 25 | |
598 | #define V2_QPC_BYTE_144_RAQ_CREDIT_M GENMASK(29, 25) | |
599 | ||
600 | #define V2_QPC_BYTE_144_RESP_RTY_FLG_S 31 | |
601 | ||
602 | #define V2_QPC_BYTE_148_RQ_MSN_S 0 | |
603 | #define V2_QPC_BYTE_148_RQ_MSN_M GENMASK(23, 0) | |
604 | ||
605 | #define V2_QPC_BYTE_148_RAQ_SYNDROME_S 24 | |
606 | #define V2_QPC_BYTE_148_RAQ_SYNDROME_M GENMASK(31, 24) | |
607 | ||
608 | #define V2_QPC_BYTE_152_RAQ_PSN_S 8 | |
609 | #define V2_QPC_BYTE_152_RAQ_PSN_M GENMASK(31, 8) | |
610 | ||
611 | #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S 24 | |
612 | #define V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M GENMASK(31, 24) | |
613 | ||
614 | #define V2_QPC_BYTE_156_RAQ_USE_PKTN_S 0 | |
615 | #define V2_QPC_BYTE_156_RAQ_USE_PKTN_M GENMASK(23, 0) | |
616 | ||
617 | #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S 0 | |
618 | #define V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M GENMASK(15, 0) | |
619 | ||
620 | #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S 16 | |
621 | #define V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M GENMASK(31, 16) | |
622 | ||
623 | #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S 0 | |
624 | #define V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
625 | ||
626 | #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20 | |
627 | ||
b5fddb7c | 628 | #define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21 |
629 | ||
630 | #define V2_QPC_BYTE_168_LP_SGEN_INI_S 22 | |
631 | #define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22) | |
926a01dc WHX |
632 | |
633 | #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24 | |
634 | #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24) | |
635 | ||
636 | #define V2_QPC_BYTE_168_IRRL_IDX_LSB_S 28 | |
637 | #define V2_QPC_BYTE_168_IRRL_IDX_LSB_M GENMASK(31, 28) | |
638 | ||
639 | #define V2_QPC_BYTE_172_ACK_REQ_FREQ_S 0 | |
640 | #define V2_QPC_BYTE_172_ACK_REQ_FREQ_M GENMASK(5, 0) | |
641 | ||
642 | #define V2_QPC_BYTE_172_MSG_RNR_FLG_S 6 | |
643 | ||
644 | #define V2_QPC_BYTE_172_FRE_S 7 | |
645 | ||
646 | #define V2_QPC_BYTE_172_SQ_CUR_PSN_S 8 | |
647 | #define V2_QPC_BYTE_172_SQ_CUR_PSN_M GENMASK(31, 8) | |
648 | ||
649 | #define V2_QPC_BYTE_176_MSG_USE_PKTN_S 0 | |
650 | #define V2_QPC_BYTE_176_MSG_USE_PKTN_M GENMASK(23, 0) | |
651 | ||
652 | #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_S 24 | |
653 | #define V2_QPC_BYTE_176_IRRL_HEAD_PRE_M GENMASK(31, 24) | |
654 | ||
655 | #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S 0 | |
656 | #define V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M GENMASK(19, 0) | |
657 | ||
658 | #define V2_QPC_BYTE_184_IRRL_IDX_MSB_S 20 | |
659 | #define V2_QPC_BYTE_184_IRRL_IDX_MSB_M GENMASK(31, 20) | |
660 | ||
661 | #define V2_QPC_BYTE_192_CUR_SGE_IDX_S 0 | |
662 | #define V2_QPC_BYTE_192_CUR_SGE_IDX_M GENMASK(23, 0) | |
663 | ||
664 | #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S 24 | |
665 | #define V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M GENMASK(31, 24) | |
666 | ||
667 | #define V2_QPC_BYTE_196_IRRL_HEAD_S 0 | |
668 | #define V2_QPC_BYTE_196_IRRL_HEAD_M GENMASK(7, 0) | |
669 | ||
670 | #define V2_QPC_BYTE_196_SQ_MAX_PSN_S 8 | |
671 | #define V2_QPC_BYTE_196_SQ_MAX_PSN_M GENMASK(31, 8) | |
672 | ||
673 | #define V2_QPC_BYTE_200_SQ_MAX_IDX_S 0 | |
674 | #define V2_QPC_BYTE_200_SQ_MAX_IDX_M GENMASK(15, 0) | |
675 | ||
676 | #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_S 16 | |
677 | #define V2_QPC_BYTE_200_LCL_OPERATED_CNT_M GENMASK(31, 16) | |
678 | ||
679 | #define V2_QPC_BYTE_208_IRRL_BA_S 0 | |
680 | #define V2_QPC_BYTE_208_IRRL_BA_M GENMASK(25, 0) | |
681 | ||
682 | #define V2_QPC_BYTE_208_PKT_RNR_FLG_S 26 | |
683 | ||
684 | #define V2_QPC_BYTE_208_PKT_RTY_FLG_S 27 | |
685 | ||
686 | #define V2_QPC_BYTE_208_RMT_E2E_S 28 | |
687 | ||
688 | #define V2_QPC_BYTE_208_SR_MAX_S 29 | |
689 | #define V2_QPC_BYTE_208_SR_MAX_M GENMASK(31, 29) | |
690 | ||
691 | #define V2_QPC_BYTE_212_LSN_S 0 | |
692 | #define V2_QPC_BYTE_212_LSN_M GENMASK(23, 0) | |
693 | ||
694 | #define V2_QPC_BYTE_212_RETRY_NUM_INIT_S 24 | |
695 | #define V2_QPC_BYTE_212_RETRY_NUM_INIT_M GENMASK(26, 24) | |
696 | ||
697 | #define V2_QPC_BYTE_212_CHECK_FLG_S 27 | |
698 | #define V2_QPC_BYTE_212_CHECK_FLG_M GENMASK(28, 27) | |
699 | ||
700 | #define V2_QPC_BYTE_212_RETRY_CNT_S 29 | |
701 | #define V2_QPC_BYTE_212_RETRY_CNT_M GENMASK(31, 29) | |
702 | ||
703 | #define V2_QPC_BYTE_220_RETRY_MSG_MSN_S 0 | |
704 | #define V2_QPC_BYTE_220_RETRY_MSG_MSN_M GENMASK(15, 0) | |
705 | ||
706 | #define V2_QPC_BYTE_220_RETRY_MSG_PSN_S 16 | |
707 | #define V2_QPC_BYTE_220_RETRY_MSG_PSN_M GENMASK(31, 16) | |
708 | ||
709 | #define V2_QPC_BYTE_224_RETRY_MSG_PSN_S 0 | |
710 | #define V2_QPC_BYTE_224_RETRY_MSG_PSN_M GENMASK(7, 0) | |
711 | ||
712 | #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S 8 | |
713 | #define V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M GENMASK(31, 8) | |
714 | ||
715 | #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S 0 | |
716 | #define V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M GENMASK(19, 0) | |
717 | ||
718 | #define V2_QPC_BYTE_232_IRRL_SGE_IDX_S 20 | |
719 | #define V2_QPC_BYTE_232_IRRL_SGE_IDX_M GENMASK(28, 20) | |
720 | ||
721 | #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_S 0 | |
722 | #define V2_QPC_BYTE_240_IRRL_TAIL_REAL_M GENMASK(7, 0) | |
723 | ||
724 | #define V2_QPC_BYTE_240_IRRL_TAIL_RD_S 8 | |
725 | #define V2_QPC_BYTE_240_IRRL_TAIL_RD_M GENMASK(15, 8) | |
726 | ||
727 | #define V2_QPC_BYTE_240_RX_ACK_MSN_S 16 | |
728 | #define V2_QPC_BYTE_240_RX_ACK_MSN_M GENMASK(31, 16) | |
729 | ||
730 | #define V2_QPC_BYTE_244_RX_ACK_EPSN_S 0 | |
731 | #define V2_QPC_BYTE_244_RX_ACK_EPSN_M GENMASK(23, 0) | |
732 | ||
733 | #define V2_QPC_BYTE_244_RNR_NUM_INIT_S 24 | |
734 | #define V2_QPC_BYTE_244_RNR_NUM_INIT_M GENMASK(26, 24) | |
735 | ||
736 | #define V2_QPC_BYTE_244_RNR_CNT_S 27 | |
737 | #define V2_QPC_BYTE_244_RNR_CNT_M GENMASK(29, 27) | |
738 | ||
739 | #define V2_QPC_BYTE_248_IRRL_PSN_S 0 | |
740 | #define V2_QPC_BYTE_248_IRRL_PSN_M GENMASK(23, 0) | |
741 | ||
742 | #define V2_QPC_BYTE_248_ACK_PSN_ERR_S 24 | |
743 | ||
744 | #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S 25 | |
745 | #define V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M GENMASK(26, 25) | |
746 | ||
747 | #define V2_QPC_BYTE_248_IRRL_PSN_VLD_S 27 | |
748 | ||
749 | #define V2_QPC_BYTE_248_RNR_RETRY_FLAG_S 28 | |
750 | ||
751 | #define V2_QPC_BYTE_248_CQ_ERR_IND_S 31 | |
752 | ||
753 | #define V2_QPC_BYTE_252_TX_CQN_S 0 | |
754 | #define V2_QPC_BYTE_252_TX_CQN_M GENMASK(23, 0) | |
755 | ||
756 | #define V2_QPC_BYTE_252_SIG_TYPE_S 24 | |
757 | ||
758 | #define V2_QPC_BYTE_252_ERR_TYPE_S 25 | |
759 | #define V2_QPC_BYTE_252_ERR_TYPE_M GENMASK(31, 25) | |
760 | ||
761 | #define V2_QPC_BYTE_256_RQ_CQE_IDX_S 0 | |
762 | #define V2_QPC_BYTE_256_RQ_CQE_IDX_M GENMASK(15, 0) | |
763 | ||
764 | #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16 | |
765 | #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16) | |
766 | ||
93aa2187 | 767 | struct hns_roce_v2_cqe { |
8b9b8d14 | 768 | __le32 byte_4; |
ccb8a29e JG |
769 | union { |
770 | __le32 rkey; | |
771 | __be32 immtdata; | |
772 | }; | |
8b9b8d14 | 773 | __le32 byte_12; |
774 | __le32 byte_16; | |
775 | __le32 byte_cnt; | |
2eade675 | 776 | u8 smac[4]; |
8b9b8d14 | 777 | __le32 byte_28; |
778 | __le32 byte_32; | |
93aa2187 WHX |
779 | }; |
780 | ||
781 | #define V2_CQE_BYTE_4_OPCODE_S 0 | |
782 | #define V2_CQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
783 | ||
784 | #define V2_CQE_BYTE_4_RQ_INLINE_S 5 | |
785 | ||
786 | #define V2_CQE_BYTE_4_S_R_S 6 | |
787 | ||
788 | #define V2_CQE_BYTE_4_OWNER_S 7 | |
789 | ||
790 | #define V2_CQE_BYTE_4_STATUS_S 8 | |
791 | #define V2_CQE_BYTE_4_STATUS_M GENMASK(15, 8) | |
792 | ||
793 | #define V2_CQE_BYTE_4_WQE_INDX_S 16 | |
794 | #define V2_CQE_BYTE_4_WQE_INDX_M GENMASK(31, 16) | |
795 | ||
796 | #define V2_CQE_BYTE_12_XRC_SRQN_S 0 | |
797 | #define V2_CQE_BYTE_12_XRC_SRQN_M GENMASK(23, 0) | |
798 | ||
799 | #define V2_CQE_BYTE_16_LCL_QPN_S 0 | |
800 | #define V2_CQE_BYTE_16_LCL_QPN_M GENMASK(23, 0) | |
801 | ||
802 | #define V2_CQE_BYTE_16_SUB_STATUS_S 24 | |
803 | #define V2_CQE_BYTE_16_SUB_STATUS_M GENMASK(31, 24) | |
804 | ||
805 | #define V2_CQE_BYTE_28_SMAC_4_S 0 | |
806 | #define V2_CQE_BYTE_28_SMAC_4_M GENMASK(7, 0) | |
807 | ||
808 | #define V2_CQE_BYTE_28_SMAC_5_S 8 | |
809 | #define V2_CQE_BYTE_28_SMAC_5_M GENMASK(15, 8) | |
810 | ||
811 | #define V2_CQE_BYTE_28_PORT_TYPE_S 16 | |
812 | #define V2_CQE_BYTE_28_PORT_TYPE_M GENMASK(17, 16) | |
813 | ||
814 | #define V2_CQE_BYTE_32_RMT_QPN_S 0 | |
815 | #define V2_CQE_BYTE_32_RMT_QPN_M GENMASK(23, 0) | |
816 | ||
817 | #define V2_CQE_BYTE_32_SL_S 24 | |
818 | #define V2_CQE_BYTE_32_SL_M GENMASK(26, 24) | |
819 | ||
820 | #define V2_CQE_BYTE_32_PORTN_S 27 | |
821 | #define V2_CQE_BYTE_32_PORTN_M GENMASK(29, 27) | |
822 | ||
823 | #define V2_CQE_BYTE_32_GRH_S 30 | |
824 | ||
825 | #define V2_CQE_BYTE_32_LPK_S 31 | |
826 | ||
3958cc56 WHX |
827 | struct hns_roce_v2_mpt_entry { |
828 | __le32 byte_4_pd_hop_st; | |
829 | __le32 byte_8_mw_cnt_en; | |
830 | __le32 byte_12_mw_pa; | |
831 | __le32 bound_lkey; | |
832 | __le32 len_l; | |
833 | __le32 len_h; | |
834 | __le32 lkey; | |
835 | __le32 va_l; | |
836 | __le32 va_h; | |
837 | __le32 pbl_size; | |
838 | __le32 pbl_ba_l; | |
839 | __le32 byte_48_mode_ba; | |
840 | __le32 pa0_l; | |
841 | __le32 byte_56_pa0_h; | |
842 | __le32 pa1_l; | |
843 | __le32 byte_64_buf_pa1; | |
844 | }; | |
845 | ||
846 | #define V2_MPT_BYTE_4_MPT_ST_S 0 | |
847 | #define V2_MPT_BYTE_4_MPT_ST_M GENMASK(1, 0) | |
848 | ||
849 | #define V2_MPT_BYTE_4_PBL_HOP_NUM_S 2 | |
850 | #define V2_MPT_BYTE_4_PBL_HOP_NUM_M GENMASK(3, 2) | |
851 | ||
852 | #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S 4 | |
853 | #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M GENMASK(7, 4) | |
854 | ||
855 | #define V2_MPT_BYTE_4_PD_S 8 | |
856 | #define V2_MPT_BYTE_4_PD_M GENMASK(31, 8) | |
857 | ||
858 | #define V2_MPT_BYTE_8_RA_EN_S 0 | |
859 | ||
860 | #define V2_MPT_BYTE_8_R_INV_EN_S 1 | |
861 | ||
862 | #define V2_MPT_BYTE_8_L_INV_EN_S 2 | |
863 | ||
864 | #define V2_MPT_BYTE_8_BIND_EN_S 3 | |
865 | ||
866 | #define V2_MPT_BYTE_8_ATOMIC_EN_S 4 | |
867 | ||
868 | #define V2_MPT_BYTE_8_RR_EN_S 5 | |
869 | ||
870 | #define V2_MPT_BYTE_8_RW_EN_S 6 | |
871 | ||
872 | #define V2_MPT_BYTE_8_LW_EN_S 7 | |
873 | ||
874 | #define V2_MPT_BYTE_12_PA_S 1 | |
875 | ||
876 | #define V2_MPT_BYTE_12_INNER_PA_VLD_S 7 | |
877 | ||
878 | #define V2_MPT_BYTE_12_MW_BIND_QPN_S 8 | |
879 | #define V2_MPT_BYTE_12_MW_BIND_QPN_M GENMASK(31, 8) | |
880 | ||
881 | #define V2_MPT_BYTE_48_PBL_BA_H_S 0 | |
882 | #define V2_MPT_BYTE_48_PBL_BA_H_M GENMASK(28, 0) | |
883 | ||
884 | #define V2_MPT_BYTE_48_BLK_MODE_S 29 | |
885 | ||
886 | #define V2_MPT_BYTE_56_PA0_H_S 0 | |
887 | #define V2_MPT_BYTE_56_PA0_H_M GENMASK(25, 0) | |
888 | ||
889 | #define V2_MPT_BYTE_64_PA1_H_S 0 | |
890 | #define V2_MPT_BYTE_64_PA1_H_M GENMASK(25, 0) | |
891 | ||
892 | #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S 28 | |
893 | #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M GENMASK(31, 28) | |
894 | ||
93aa2187 WHX |
895 | #define V2_DB_BYTE_4_TAG_S 0 |
896 | #define V2_DB_BYTE_4_TAG_M GENMASK(23, 0) | |
897 | ||
898 | #define V2_DB_BYTE_4_CMD_S 24 | |
899 | #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) | |
900 | ||
cc3391cb | 901 | #define V2_DB_PARAMETER_IDX_S 0 |
902 | #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0) | |
2d407888 WHX |
903 | |
904 | #define V2_DB_PARAMETER_SL_S 16 | |
905 | #define V2_DB_PARAMETER_SL_M GENMASK(18, 16) | |
906 | ||
93aa2187 | 907 | struct hns_roce_v2_cq_db { |
8b9b8d14 | 908 | __le32 byte_4; |
909 | __le32 parameter; | |
93aa2187 WHX |
910 | }; |
911 | ||
912 | #define V2_CQ_DB_BYTE_4_TAG_S 0 | |
913 | #define V2_CQ_DB_BYTE_4_TAG_M GENMASK(23, 0) | |
914 | ||
915 | #define V2_CQ_DB_BYTE_4_CMD_S 24 | |
916 | #define V2_CQ_DB_BYTE_4_CMD_M GENMASK(27, 24) | |
917 | ||
918 | #define V2_CQ_DB_PARAMETER_CONS_IDX_S 0 | |
919 | #define V2_CQ_DB_PARAMETER_CONS_IDX_M GENMASK(23, 0) | |
920 | ||
921 | #define V2_CQ_DB_PARAMETER_CMD_SN_S 25 | |
922 | #define V2_CQ_DB_PARAMETER_CMD_SN_M GENMASK(26, 25) | |
923 | ||
924 | #define V2_CQ_DB_PARAMETER_NOTIFY_S 24 | |
925 | ||
7bdee415 | 926 | struct hns_roce_v2_ud_send_wqe { |
8b9b8d14 | 927 | __le32 byte_4; |
928 | __le32 msg_len; | |
929 | __be32 immtdata; | |
930 | __le32 byte_16; | |
931 | __le32 byte_20; | |
932 | __le32 byte_24; | |
933 | __le32 qkey; | |
934 | __le32 byte_32; | |
935 | __le32 byte_36; | |
936 | __le32 byte_40; | |
937 | __le32 dmac; | |
938 | __le32 byte_48; | |
7bdee415 | 939 | u8 dgid[GID_LEN_V2]; |
940 | ||
941 | }; | |
942 | #define V2_UD_SEND_WQE_BYTE_4_OPCODE_S 0 | |
943 | #define V2_UD_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
944 | ||
945 | #define V2_UD_SEND_WQE_BYTE_4_OWNER_S 7 | |
946 | ||
947 | #define V2_UD_SEND_WQE_BYTE_4_CQE_S 8 | |
948 | ||
949 | #define V2_UD_SEND_WQE_BYTE_4_SE_S 11 | |
950 | ||
951 | #define V2_UD_SEND_WQE_BYTE_16_PD_S 0 | |
952 | #define V2_UD_SEND_WQE_BYTE_16_PD_M GENMASK(23, 0) | |
953 | ||
954 | #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S 24 | |
955 | #define V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) | |
956 | ||
957 | #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 | |
958 | #define V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) | |
959 | ||
960 | #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_S 16 | |
961 | #define V2_UD_SEND_WQE_BYTE_24_UDPSPN_M GENMASK(31, 16) | |
962 | ||
963 | #define V2_UD_SEND_WQE_BYTE_32_DQPN_S 0 | |
964 | #define V2_UD_SEND_WQE_BYTE_32_DQPN_M GENMASK(23, 0) | |
965 | ||
966 | #define V2_UD_SEND_WQE_BYTE_36_VLAN_S 0 | |
967 | #define V2_UD_SEND_WQE_BYTE_36_VLAN_M GENMASK(15, 0) | |
968 | ||
969 | #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S 16 | |
970 | #define V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M GENMASK(23, 16) | |
971 | ||
972 | #define V2_UD_SEND_WQE_BYTE_36_TCLASS_S 24 | |
973 | #define V2_UD_SEND_WQE_BYTE_36_TCLASS_M GENMASK(31, 24) | |
974 | ||
975 | #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S 0 | |
976 | #define V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M GENMASK(19, 0) | |
977 | ||
978 | #define V2_UD_SEND_WQE_BYTE_40_SL_S 20 | |
979 | #define V2_UD_SEND_WQE_BYTE_40_SL_M GENMASK(23, 20) | |
980 | ||
981 | #define V2_UD_SEND_WQE_BYTE_40_PORTN_S 24 | |
982 | #define V2_UD_SEND_WQE_BYTE_40_PORTN_M GENMASK(26, 24) | |
983 | ||
984 | #define V2_UD_SEND_WQE_BYTE_40_LBI_S 31 | |
985 | ||
986 | #define V2_UD_SEND_WQE_DMAC_0_S 0 | |
987 | #define V2_UD_SEND_WQE_DMAC_0_M GENMASK(7, 0) | |
988 | ||
989 | #define V2_UD_SEND_WQE_DMAC_1_S 8 | |
990 | #define V2_UD_SEND_WQE_DMAC_1_M GENMASK(15, 8) | |
991 | ||
992 | #define V2_UD_SEND_WQE_DMAC_2_S 16 | |
993 | #define V2_UD_SEND_WQE_DMAC_2_M GENMASK(23, 16) | |
994 | ||
995 | #define V2_UD_SEND_WQE_DMAC_3_S 24 | |
996 | #define V2_UD_SEND_WQE_DMAC_3_M GENMASK(31, 24) | |
997 | ||
998 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_S 0 | |
999 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_4_M GENMASK(7, 0) | |
1000 | ||
1001 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_S 8 | |
1002 | #define V2_UD_SEND_WQE_BYTE_48_DMAC_5_M GENMASK(15, 8) | |
1003 | ||
1004 | #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S 16 | |
1005 | #define V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M GENMASK(23, 16) | |
1006 | ||
1007 | #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S 24 | |
1008 | #define V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M GENMASK(31, 24) | |
1009 | ||
2d407888 | 1010 | struct hns_roce_v2_rc_send_wqe { |
8b9b8d14 | 1011 | __le32 byte_4; |
1012 | __le32 msg_len; | |
1013 | union { | |
1014 | __le32 inv_key; | |
1015 | __be32 immtdata; | |
1016 | }; | |
1017 | __le32 byte_16; | |
1018 | __le32 byte_20; | |
1019 | __le32 rkey; | |
1020 | __le64 va; | |
2d407888 WHX |
1021 | }; |
1022 | ||
1023 | #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 | |
1024 | #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) | |
1025 | ||
1026 | #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 | |
1027 | ||
1028 | #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 | |
1029 | ||
1030 | #define V2_RC_SEND_WQE_BYTE_4_FENCE_S 9 | |
1031 | ||
1032 | #define V2_RC_SEND_WQE_BYTE_4_SO_S 10 | |
1033 | ||
1034 | #define V2_RC_SEND_WQE_BYTE_4_SE_S 11 | |
1035 | ||
1036 | #define V2_RC_SEND_WQE_BYTE_4_INLINE_S 12 | |
1037 | ||
1038 | #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 | |
1039 | #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) | |
1040 | ||
1041 | #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S 24 | |
1042 | #define V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M GENMASK(31, 24) | |
1043 | ||
1044 | #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S 0 | |
1045 | #define V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M GENMASK(23, 0) | |
1046 | ||
1047 | struct hns_roce_v2_wqe_data_seg { | |
8b9b8d14 | 1048 | __le32 len; |
1049 | __le32 lkey; | |
1050 | __le64 addr; | |
2d407888 WHX |
1051 | }; |
1052 | ||
1053 | struct hns_roce_v2_db { | |
8b9b8d14 | 1054 | __le32 byte_4; |
1055 | __le32 parameter; | |
2d407888 WHX |
1056 | }; |
1057 | ||
cfc85f3e WHX |
1058 | struct hns_roce_query_version { |
1059 | __le16 rocee_vendor_id; | |
1060 | __le16 rocee_hw_version; | |
1061 | __le32 rsv[5]; | |
1062 | }; | |
1063 | ||
1064 | struct hns_roce_cfg_global_param { | |
1065 | __le32 time_cfg_udp_port; | |
1066 | __le32 rsv[5]; | |
1067 | }; | |
1068 | ||
1069 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S 0 | |
1070 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M GENMASK(9, 0) | |
1071 | ||
1072 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S 16 | |
1073 | #define CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M GENMASK(31, 16) | |
1074 | ||
1075 | struct hns_roce_pf_res { | |
1076 | __le32 rsv; | |
1077 | __le32 qpc_bt_idx_num; | |
1078 | __le32 srqc_bt_idx_num; | |
1079 | __le32 cqc_bt_idx_num; | |
1080 | __le32 mpt_bt_idx_num; | |
1081 | __le32 eqc_bt_idx_num; | |
1082 | }; | |
1083 | ||
1084 | #define PF_RES_DATA_1_PF_QPC_BT_IDX_S 0 | |
1085 | #define PF_RES_DATA_1_PF_QPC_BT_IDX_M GENMASK(10, 0) | |
1086 | ||
1087 | #define PF_RES_DATA_1_PF_QPC_BT_NUM_S 16 | |
1088 | #define PF_RES_DATA_1_PF_QPC_BT_NUM_M GENMASK(27, 16) | |
1089 | ||
1090 | #define PF_RES_DATA_2_PF_SRQC_BT_IDX_S 0 | |
1091 | #define PF_RES_DATA_2_PF_SRQC_BT_IDX_M GENMASK(8, 0) | |
1092 | ||
1093 | #define PF_RES_DATA_2_PF_SRQC_BT_NUM_S 16 | |
1094 | #define PF_RES_DATA_2_PF_SRQC_BT_NUM_M GENMASK(25, 16) | |
1095 | ||
1096 | #define PF_RES_DATA_3_PF_CQC_BT_IDX_S 0 | |
1097 | #define PF_RES_DATA_3_PF_CQC_BT_IDX_M GENMASK(8, 0) | |
1098 | ||
1099 | #define PF_RES_DATA_3_PF_CQC_BT_NUM_S 16 | |
1100 | #define PF_RES_DATA_3_PF_CQC_BT_NUM_M GENMASK(25, 16) | |
1101 | ||
1102 | #define PF_RES_DATA_4_PF_MPT_BT_IDX_S 0 | |
1103 | #define PF_RES_DATA_4_PF_MPT_BT_IDX_M GENMASK(8, 0) | |
1104 | ||
1105 | #define PF_RES_DATA_4_PF_MPT_BT_NUM_S 16 | |
1106 | #define PF_RES_DATA_4_PF_MPT_BT_NUM_M GENMASK(25, 16) | |
1107 | ||
1108 | #define PF_RES_DATA_5_PF_EQC_BT_IDX_S 0 | |
1109 | #define PF_RES_DATA_5_PF_EQC_BT_IDX_M GENMASK(8, 0) | |
1110 | ||
1111 | #define PF_RES_DATA_5_PF_EQC_BT_NUM_S 16 | |
1112 | #define PF_RES_DATA_5_PF_EQC_BT_NUM_M GENMASK(25, 16) | |
1113 | ||
1114 | struct hns_roce_vf_res_a { | |
8b9b8d14 | 1115 | __le32 vf_id; |
1116 | __le32 vf_qpc_bt_idx_num; | |
1117 | __le32 vf_srqc_bt_idx_num; | |
1118 | __le32 vf_cqc_bt_idx_num; | |
1119 | __le32 vf_mpt_bt_idx_num; | |
1120 | __le32 vf_eqc_bt_idx_num; | |
cfc85f3e WHX |
1121 | }; |
1122 | ||
1123 | #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_S 0 | |
1124 | #define VF_RES_A_DATA_1_VF_QPC_BT_IDX_M GENMASK(10, 0) | |
1125 | ||
1126 | #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_S 16 | |
1127 | #define VF_RES_A_DATA_1_VF_QPC_BT_NUM_M GENMASK(27, 16) | |
1128 | ||
1129 | #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S 0 | |
1130 | #define VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M GENMASK(8, 0) | |
1131 | ||
1132 | #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S 16 | |
1133 | #define VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M GENMASK(25, 16) | |
1134 | ||
1135 | #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_S 0 | |
1136 | #define VF_RES_A_DATA_3_VF_CQC_BT_IDX_M GENMASK(8, 0) | |
1137 | ||
1138 | #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_S 16 | |
1139 | #define VF_RES_A_DATA_3_VF_CQC_BT_NUM_M GENMASK(25, 16) | |
1140 | ||
1141 | #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_S 0 | |
1142 | #define VF_RES_A_DATA_4_VF_MPT_BT_IDX_M GENMASK(8, 0) | |
1143 | ||
1144 | #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_S 16 | |
1145 | #define VF_RES_A_DATA_4_VF_MPT_BT_NUM_M GENMASK(25, 16) | |
1146 | ||
1147 | #define VF_RES_A_DATA_5_VF_EQC_IDX_S 0 | |
1148 | #define VF_RES_A_DATA_5_VF_EQC_IDX_M GENMASK(8, 0) | |
1149 | ||
1150 | #define VF_RES_A_DATA_5_VF_EQC_NUM_S 16 | |
1151 | #define VF_RES_A_DATA_5_VF_EQC_NUM_M GENMASK(25, 16) | |
1152 | ||
1153 | struct hns_roce_vf_res_b { | |
8b9b8d14 | 1154 | __le32 rsv0; |
1155 | __le32 vf_smac_idx_num; | |
1156 | __le32 vf_sgid_idx_num; | |
1157 | __le32 vf_qid_idx_sl_num; | |
1158 | __le32 rsv[2]; | |
cfc85f3e WHX |
1159 | }; |
1160 | ||
1161 | #define VF_RES_B_DATA_0_VF_ID_S 0 | |
1162 | #define VF_RES_B_DATA_0_VF_ID_M GENMASK(7, 0) | |
1163 | ||
1164 | #define VF_RES_B_DATA_1_VF_SMAC_IDX_S 0 | |
1165 | #define VF_RES_B_DATA_1_VF_SMAC_IDX_M GENMASK(7, 0) | |
1166 | ||
1167 | #define VF_RES_B_DATA_1_VF_SMAC_NUM_S 8 | |
1168 | #define VF_RES_B_DATA_1_VF_SMAC_NUM_M GENMASK(16, 8) | |
1169 | ||
1170 | #define VF_RES_B_DATA_2_VF_SGID_IDX_S 0 | |
1171 | #define VF_RES_B_DATA_2_VF_SGID_IDX_M GENMASK(7, 0) | |
1172 | ||
1173 | #define VF_RES_B_DATA_2_VF_SGID_NUM_S 8 | |
1174 | #define VF_RES_B_DATA_2_VF_SGID_NUM_M GENMASK(16, 8) | |
1175 | ||
1176 | #define VF_RES_B_DATA_3_VF_QID_IDX_S 0 | |
1177 | #define VF_RES_B_DATA_3_VF_QID_IDX_M GENMASK(9, 0) | |
1178 | ||
1179 | #define VF_RES_B_DATA_3_VF_SL_NUM_S 16 | |
1180 | #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16) | |
1181 | ||
7afddafa WHX |
1182 | /* Reg field definition */ |
1183 | #define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0 | |
1184 | #define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0) | |
1185 | ||
1186 | #define ROCEE_VF_SGID_CFG4_SGID_TYPE_S 0 | |
1187 | #define ROCEE_VF_SGID_CFG4_SGID_TYPE_M GENMASK(1, 0) | |
1188 | ||
a81fba28 | 1189 | struct hns_roce_cfg_bt_attr { |
8b9b8d14 | 1190 | __le32 vf_qpc_cfg; |
1191 | __le32 vf_srqc_cfg; | |
1192 | __le32 vf_cqc_cfg; | |
1193 | __le32 vf_mpt_cfg; | |
1194 | __le32 rsv[2]; | |
a81fba28 WHX |
1195 | }; |
1196 | ||
1197 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S 0 | |
1198 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M GENMASK(3, 0) | |
1199 | ||
1200 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S 4 | |
1201 | #define CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M GENMASK(7, 4) | |
1202 | ||
1203 | #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S 8 | |
1204 | #define CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M GENMASK(9, 8) | |
1205 | ||
1206 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S 0 | |
1207 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M GENMASK(3, 0) | |
1208 | ||
1209 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S 4 | |
1210 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M GENMASK(7, 4) | |
1211 | ||
1212 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S 8 | |
1213 | #define CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M GENMASK(9, 8) | |
1214 | ||
1215 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S 0 | |
1216 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M GENMASK(3, 0) | |
1217 | ||
1218 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S 4 | |
1219 | #define CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M GENMASK(7, 4) | |
1220 | ||
1221 | #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S 8 | |
1222 | #define CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M GENMASK(9, 8) | |
1223 | ||
1224 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S 0 | |
1225 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M GENMASK(3, 0) | |
1226 | ||
1227 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S 4 | |
1228 | #define CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M GENMASK(7, 4) | |
1229 | ||
1230 | #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S 8 | |
1231 | #define CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M GENMASK(9, 8) | |
1232 | ||
a04ff739 | 1233 | struct hns_roce_cmq_desc { |
8b9b8d14 | 1234 | __le16 opcode; |
1235 | __le16 flag; | |
1236 | __le16 retval; | |
1237 | __le16 rsv; | |
1238 | __le32 data[6]; | |
a04ff739 WHX |
1239 | }; |
1240 | ||
a680f2f3 WHX |
1241 | #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS 10000 |
1242 | ||
1243 | #define HNS_ROCE_HW_RUN_BIT_SHIFT 31 | |
1244 | #define HNS_ROCE_HW_MB_STATUS_MASK 0xFF | |
1245 | ||
1246 | #define HNS_ROCE_VF_MB4_TAG_MASK 0xFFFFFF00 | |
1247 | #define HNS_ROCE_VF_MB4_TAG_SHIFT 8 | |
1248 | ||
1249 | #define HNS_ROCE_VF_MB4_CMD_MASK 0xFF | |
1250 | #define HNS_ROCE_VF_MB4_CMD_SHIFT 0 | |
1251 | ||
1252 | #define HNS_ROCE_VF_MB5_EVENT_MASK 0x10000 | |
1253 | #define HNS_ROCE_VF_MB5_EVENT_SHIFT 16 | |
1254 | ||
1255 | #define HNS_ROCE_VF_MB5_TOKEN_MASK 0xFFFF | |
1256 | #define HNS_ROCE_VF_MB5_TOKEN_SHIFT 0 | |
1257 | ||
a04ff739 WHX |
1258 | struct hns_roce_v2_cmq_ring { |
1259 | dma_addr_t desc_dma_addr; | |
1260 | struct hns_roce_cmq_desc *desc; | |
1261 | u32 head; | |
1262 | u32 tail; | |
1263 | ||
1264 | u16 buf_size; | |
1265 | u16 desc_num; | |
1266 | int next_to_use; | |
1267 | int next_to_clean; | |
1268 | u8 flag; | |
1269 | spinlock_t lock; /* command queue lock */ | |
1270 | }; | |
1271 | ||
1272 | struct hns_roce_v2_cmq { | |
1273 | struct hns_roce_v2_cmq_ring csq; | |
1274 | struct hns_roce_v2_cmq_ring crq; | |
1275 | u16 tx_timeout; | |
1276 | u16 last_status; | |
1277 | }; | |
1278 | ||
1279 | struct hns_roce_v2_priv { | |
1280 | struct hns_roce_v2_cmq cmq; | |
1281 | }; | |
1282 | ||
a5073d60 | 1283 | struct hns_roce_eq_context { |
8b9b8d14 | 1284 | __le32 byte_4; |
1285 | __le32 byte_8; | |
1286 | __le32 byte_12; | |
1287 | __le32 eqe_report_timer; | |
1288 | __le32 eqe_ba0; | |
1289 | __le32 eqe_ba1; | |
1290 | __le32 byte_28; | |
1291 | __le32 byte_32; | |
1292 | __le32 byte_36; | |
1293 | __le32 nxt_eqe_ba0; | |
1294 | __le32 nxt_eqe_ba1; | |
1295 | __le32 rsv[5]; | |
a5073d60 YL |
1296 | }; |
1297 | ||
1298 | #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM 0x0 | |
1299 | #define HNS_ROCE_AEQ_DEFAULT_INTERVAL 0x0 | |
1300 | #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x0 | |
1301 | #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x0 | |
1302 | ||
1303 | #define HNS_ROCE_V2_EQ_STATE_INVALID 0 | |
1304 | #define HNS_ROCE_V2_EQ_STATE_VALID 1 | |
1305 | #define HNS_ROCE_V2_EQ_STATE_OVERFLOW 2 | |
1306 | #define HNS_ROCE_V2_EQ_STATE_FAILURE 3 | |
1307 | ||
1308 | #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 0 | |
1309 | #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 1 | |
1310 | ||
1311 | #define HNS_ROCE_V2_EQ_COALESCE_0 0 | |
1312 | #define HNS_ROCE_V2_EQ_COALESCE_1 1 | |
1313 | ||
1314 | #define HNS_ROCE_V2_EQ_FIRED 0 | |
1315 | #define HNS_ROCE_V2_EQ_ARMED 1 | |
1316 | #define HNS_ROCE_V2_EQ_ALWAYS_ARMED 3 | |
1317 | ||
1318 | #define HNS_ROCE_EQ_INIT_EQE_CNT 0 | |
1319 | #define HNS_ROCE_EQ_INIT_PROD_IDX 0 | |
1320 | #define HNS_ROCE_EQ_INIT_REPORT_TIMER 0 | |
1321 | #define HNS_ROCE_EQ_INIT_MSI_IDX 0 | |
1322 | #define HNS_ROCE_EQ_INIT_CONS_IDX 0 | |
1323 | #define HNS_ROCE_EQ_INIT_NXT_EQE_BA 0 | |
1324 | ||
1325 | #define HNS_ROCE_V2_CEQ_CEQE_OWNER_S 31 | |
1326 | #define HNS_ROCE_V2_AEQ_AEQE_OWNER_S 31 | |
1327 | ||
1328 | #define HNS_ROCE_V2_COMP_EQE_NUM 0x1000 | |
1329 | #define HNS_ROCE_V2_ASYNC_EQE_NUM 0x1000 | |
1330 | ||
1331 | #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S 0 | |
1332 | #define HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S 1 | |
1333 | #define HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S 2 | |
1334 | ||
1335 | #define HNS_ROCE_EQ_DB_CMD_AEQ 0x0 | |
1336 | #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED 0x1 | |
1337 | #define HNS_ROCE_EQ_DB_CMD_CEQ 0x2 | |
1338 | #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED 0x3 | |
1339 | ||
1340 | #define EQ_ENABLE 1 | |
1341 | #define EQ_DISABLE 0 | |
1342 | ||
1343 | #define EQ_REG_OFFSET 0x4 | |
1344 | ||
1345 | #define HNS_ROCE_INT_NAME_LEN 32 | |
1346 | #define HNS_ROCE_V2_EQN_M GENMASK(23, 0) | |
1347 | ||
1348 | #define HNS_ROCE_V2_CONS_IDX_M GENMASK(23, 0) | |
1349 | ||
1350 | #define HNS_ROCE_V2_VF_ABN_INT_EN_S 0 | |
1351 | #define HNS_ROCE_V2_VF_ABN_INT_EN_M GENMASK(0, 0) | |
1352 | #define HNS_ROCE_V2_VF_ABN_INT_ST_M GENMASK(2, 0) | |
1353 | #define HNS_ROCE_V2_VF_ABN_INT_CFG_M GENMASK(2, 0) | |
1354 | #define HNS_ROCE_V2_VF_EVENT_INT_EN_M GENMASK(0, 0) | |
1355 | ||
1356 | /* WORD0 */ | |
1357 | #define HNS_ROCE_EQC_EQ_ST_S 0 | |
1358 | #define HNS_ROCE_EQC_EQ_ST_M GENMASK(1, 0) | |
1359 | ||
1360 | #define HNS_ROCE_EQC_HOP_NUM_S 2 | |
1361 | #define HNS_ROCE_EQC_HOP_NUM_M GENMASK(3, 2) | |
1362 | ||
1363 | #define HNS_ROCE_EQC_OVER_IGNORE_S 4 | |
1364 | #define HNS_ROCE_EQC_OVER_IGNORE_M GENMASK(4, 4) | |
1365 | ||
1366 | #define HNS_ROCE_EQC_COALESCE_S 5 | |
1367 | #define HNS_ROCE_EQC_COALESCE_M GENMASK(5, 5) | |
1368 | ||
1369 | #define HNS_ROCE_EQC_ARM_ST_S 6 | |
1370 | #define HNS_ROCE_EQC_ARM_ST_M GENMASK(7, 6) | |
1371 | ||
1372 | #define HNS_ROCE_EQC_EQN_S 8 | |
1373 | #define HNS_ROCE_EQC_EQN_M GENMASK(15, 8) | |
1374 | ||
1375 | #define HNS_ROCE_EQC_EQE_CNT_S 16 | |
1376 | #define HNS_ROCE_EQC_EQE_CNT_M GENMASK(31, 16) | |
1377 | ||
1378 | /* WORD1 */ | |
1379 | #define HNS_ROCE_EQC_BA_PG_SZ_S 0 | |
1380 | #define HNS_ROCE_EQC_BA_PG_SZ_M GENMASK(3, 0) | |
1381 | ||
1382 | #define HNS_ROCE_EQC_BUF_PG_SZ_S 4 | |
1383 | #define HNS_ROCE_EQC_BUF_PG_SZ_M GENMASK(7, 4) | |
1384 | ||
1385 | #define HNS_ROCE_EQC_PROD_INDX_S 8 | |
1386 | #define HNS_ROCE_EQC_PROD_INDX_M GENMASK(31, 8) | |
1387 | ||
1388 | /* WORD2 */ | |
1389 | #define HNS_ROCE_EQC_MAX_CNT_S 0 | |
1390 | #define HNS_ROCE_EQC_MAX_CNT_M GENMASK(15, 0) | |
1391 | ||
1392 | #define HNS_ROCE_EQC_PERIOD_S 16 | |
1393 | #define HNS_ROCE_EQC_PERIOD_M GENMASK(31, 16) | |
1394 | ||
1395 | /* WORD3 */ | |
1396 | #define HNS_ROCE_EQC_REPORT_TIMER_S 0 | |
1397 | #define HNS_ROCE_EQC_REPORT_TIMER_M GENMASK(31, 0) | |
1398 | ||
1399 | /* WORD4 */ | |
1400 | #define HNS_ROCE_EQC_EQE_BA_L_S 0 | |
1401 | #define HNS_ROCE_EQC_EQE_BA_L_M GENMASK(31, 0) | |
1402 | ||
1403 | /* WORD5 */ | |
1404 | #define HNS_ROCE_EQC_EQE_BA_H_S 0 | |
1405 | #define HNS_ROCE_EQC_EQE_BA_H_M GENMASK(28, 0) | |
1406 | ||
1407 | /* WORD6 */ | |
1408 | #define HNS_ROCE_EQC_SHIFT_S 0 | |
1409 | #define HNS_ROCE_EQC_SHIFT_M GENMASK(7, 0) | |
1410 | ||
1411 | #define HNS_ROCE_EQC_MSI_INDX_S 8 | |
1412 | #define HNS_ROCE_EQC_MSI_INDX_M GENMASK(15, 8) | |
1413 | ||
1414 | #define HNS_ROCE_EQC_CUR_EQE_BA_L_S 16 | |
1415 | #define HNS_ROCE_EQC_CUR_EQE_BA_L_M GENMASK(31, 16) | |
1416 | ||
1417 | /* WORD7 */ | |
1418 | #define HNS_ROCE_EQC_CUR_EQE_BA_M_S 0 | |
1419 | #define HNS_ROCE_EQC_CUR_EQE_BA_M_M GENMASK(31, 0) | |
1420 | ||
1421 | /* WORD8 */ | |
1422 | #define HNS_ROCE_EQC_CUR_EQE_BA_H_S 0 | |
1423 | #define HNS_ROCE_EQC_CUR_EQE_BA_H_M GENMASK(3, 0) | |
1424 | ||
1425 | #define HNS_ROCE_EQC_CONS_INDX_S 8 | |
1426 | #define HNS_ROCE_EQC_CONS_INDX_M GENMASK(31, 8) | |
1427 | ||
1428 | /* WORD9 */ | |
1429 | #define HNS_ROCE_EQC_NXT_EQE_BA_L_S 0 | |
1430 | #define HNS_ROCE_EQC_NXT_EQE_BA_L_M GENMASK(31, 0) | |
1431 | ||
1432 | /* WORD10 */ | |
1433 | #define HNS_ROCE_EQC_NXT_EQE_BA_H_S 0 | |
1434 | #define HNS_ROCE_EQC_NXT_EQE_BA_H_M GENMASK(19, 0) | |
1435 | ||
1436 | #define HNS_ROCE_V2_CEQE_COMP_CQN_S 0 | |
1437 | #define HNS_ROCE_V2_CEQE_COMP_CQN_M GENMASK(23, 0) | |
1438 | ||
1439 | #define HNS_ROCE_V2_AEQE_EVENT_TYPE_S 0 | |
1440 | #define HNS_ROCE_V2_AEQE_EVENT_TYPE_M GENMASK(7, 0) | |
1441 | ||
1442 | #define HNS_ROCE_V2_AEQE_SUB_TYPE_S 8 | |
1443 | #define HNS_ROCE_V2_AEQE_SUB_TYPE_M GENMASK(15, 8) | |
1444 | ||
1445 | #define HNS_ROCE_V2_EQ_DB_CMD_S 16 | |
1446 | #define HNS_ROCE_V2_EQ_DB_CMD_M GENMASK(17, 16) | |
1447 | ||
1448 | #define HNS_ROCE_V2_EQ_DB_TAG_S 0 | |
1449 | #define HNS_ROCE_V2_EQ_DB_TAG_M GENMASK(7, 0) | |
1450 | ||
1451 | #define HNS_ROCE_V2_EQ_DB_PARA_S 0 | |
1452 | #define HNS_ROCE_V2_EQ_DB_PARA_M GENMASK(23, 0) | |
1453 | ||
1454 | #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S 0 | |
1455 | #define HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M GENMASK(23, 0) | |
1456 | ||
a04ff739 | 1457 | #endif |