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RDMA/hns: Add vlan enable bit for hip08
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
dd74282d
WHX		 40#include <rdma/ib_umem.h>
41
42#include "hnae3.h"
43#include "hns_roce_common.h"
44#include "hns_roce_device.h"
45#include "hns_roce_cmd.h"
46#include "hns_roce_hem.h"
a04ff739 47#include "hns_roce_hw_v2.h"
dd74282d 48
2d407888
WHX		 49static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
50 struct ib_sge *sg)
51{
52 dseg->lkey = cpu_to_le32(sg->lkey);
53 dseg->addr = cpu_to_le64(sg->addr);
54 dseg->len = cpu_to_le32(sg->length);
55}
56
384f8818
LO		 57static void set_atomic_seg(struct hns_roce_wqe_atomic_seg *aseg,
58 const struct ib_atomic_wr *wr)
59{
60 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
61 aseg->fetchadd_swap_data = cpu_to_le64(wr->swap);
62 aseg->cmp_data = cpu_to_le64(wr->compare_add);
63 } else {
64 aseg->fetchadd_swap_data = cpu_to_le64(wr->compare_add);
65 aseg->cmp_data = 0;
66 }
67}
68
f696bf6d 69static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
0b25c9cc
WHX		 70 unsigned int *sge_ind)
71{
72 struct hns_roce_v2_wqe_data_seg *dseg;
73 struct ib_sge *sg;
74 int num_in_wqe = 0;
75 int extend_sge_num;
76 int fi_sge_num;
77 int se_sge_num;
78 int shift;
79 int i;
80
81 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
82 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
83 extend_sge_num = wr->num_sge - num_in_wqe;
84 sg = wr->sg_list + num_in_wqe;
85 shift = qp->hr_buf.page_shift;
86
87 /*
88 * Check whether wr->num_sge sges are in the same page. If not, we
89 * should calculate how many sges in the first page and the second
90 * page.
91 */
92 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
93 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
94 (uintptr_t)dseg) /
95 sizeof(struct hns_roce_v2_wqe_data_seg);
96 if (extend_sge_num > fi_sge_num) {
97 se_sge_num = extend_sge_num - fi_sge_num;
98 for (i = 0; i < fi_sge_num; i++) {
99 set_data_seg_v2(dseg++, sg + i);
100 (*sge_ind)++;
101 }
102 dseg = get_send_extend_sge(qp,
103 (*sge_ind) & (qp->sge.sge_cnt - 1));
104 for (i = 0; i < se_sge_num; i++) {
105 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
106 (*sge_ind)++;
107 }
108 } else {
109 for (i = 0; i < extend_sge_num; i++) {
110 set_data_seg_v2(dseg++, sg + i);
111 (*sge_ind)++;
112 }
113 }
114}
115
f696bf6d 116static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 117 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
118 void *wqe, unsigned int *sge_ind,
d34ac5cd 119 const struct ib_send_wr **bad_wr)
7bdee415 120{
121 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
122 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
123 struct hns_roce_qp *qp = to_hr_qp(ibqp);
124 int i;
125
126 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 127 if (le32_to_cpu(rc_sq_wqe->msg_len) >
128 hr_dev->caps.max_sq_inline) {
7bdee415 129 *bad_wr = wr;
130 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
131 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
132 return -EINVAL;
133 }
134
328d405b 135 if (wr->opcode == IB_WR_RDMA_READ) {
c80e0661 136 *bad_wr = wr;
328d405b 137 dev_err(hr_dev->dev, "Not support inline data!\n");
138 return -EINVAL;
139 }
140
7bdee415 141 for (i = 0; i < wr->num_sge; i++) {
142 memcpy(wqe, ((void *)wr->sg_list[i].addr),
143 wr->sg_list[i].length);
144 wqe += wr->sg_list[i].length;
145 }
146
147 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
148 1);
149 } else {
0b25c9cc 150 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 151 for (i = 0; i < wr->num_sge; i++) {
152 if (likely(wr->sg_list[i].length)) {
153 set_data_seg_v2(dseg, wr->sg_list + i);
154 dseg++;
155 }
156 }
157 } else {
158 roce_set_field(rc_sq_wqe->byte_20,
159 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
160 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
161 (*sge_ind) & (qp->sge.sge_cnt - 1));
162
0b25c9cc 163 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 164 if (likely(wr->sg_list[i].length)) {
165 set_data_seg_v2(dseg, wr->sg_list + i);
166 dseg++;
167 }
168 }
169
0b25c9cc 170 set_extend_sge(qp, wr, sge_ind);
7bdee415 171 }
172
173 roce_set_field(rc_sq_wqe->byte_16,
174 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
175 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
176 }
177
178 return 0;
179}
180
0425e3e6
YL		 181static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
182 const struct ib_qp_attr *attr,
183 int attr_mask, enum ib_qp_state cur_state,
184 enum ib_qp_state new_state);
185
d34ac5cd
BVA		 186static int hns_roce_v2_post_send(struct ib_qp *ibqp,
187 const struct ib_send_wr *wr,
188 const struct ib_send_wr **bad_wr)
2d407888
WHX		 189{
190 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
7bdee415 191 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
192 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
2d407888
WHX		 193 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
194 struct hns_roce_qp *qp = to_hr_qp(ibqp);
2d407888
WHX		 195 struct device *dev = hr_dev->dev;
196 struct hns_roce_v2_db sq_db;
0425e3e6 197 struct ib_qp_attr attr;
2d407888 198 unsigned int sge_ind = 0;
e8d18533 199 unsigned int owner_bit;
2d407888
WHX		 200 unsigned long flags;
201 unsigned int ind;
202 void *wqe = NULL;
7bdee415 203 bool loopback;
0425e3e6 204 int attr_mask;
55ba49cb 205 u32 tmp_len;
2d407888 206 int ret = 0;
b9c1ea40 207 u32 hr_op;
7bdee415 208 u8 *smac;
2d407888
WHX		 209 int nreq;
210 int i;
211
7bdee415 212 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
213 ibqp->qp_type != IB_QPT_GSI &&
214 ibqp->qp_type != IB_QPT_UD)) {
2d407888 215 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
137ae320 216 *bad_wr = wr;
2d407888
WHX		 217 return -EOPNOTSUPP;
218 }
219
10bd2ade
YL		 220 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT ||
221 qp->state == IB_QPS_RTR)) {
2d407888
WHX		 222 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
223 *bad_wr = wr;
224 return -EINVAL;
225 }
226
227 spin_lock_irqsave(&qp->sq.lock, flags);
228 ind = qp->sq_next_wqe;
229 sge_ind = qp->next_sge;
230
231 for (nreq = 0; wr; ++nreq, wr = wr->next) {
232 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
233 ret = -ENOMEM;
234 *bad_wr = wr;
235 goto out;
236 }
237
238 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
239 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
240 wr->num_sge, qp->sq.max_gs);
241 ret = -EINVAL;
242 *bad_wr = wr;
243 goto out;
244 }
245
246 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
247 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
248 wr->wr_id;
249
634f6390 250 owner_bit =
251 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
55ba49cb 252 tmp_len = 0;
2d407888 253
7bdee415 254 /* Corresponding to the QP type, wqe process separately */
255 if (ibqp->qp_type == IB_QPT_GSI) {
256 ud_sq_wqe = wqe;
257 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
258
259 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
260 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
261 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
262 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
263 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
264 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
265 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
266 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
267 roce_set_field(ud_sq_wqe->byte_48,
268 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
269 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
270 ah->av.mac[4]);
271 roce_set_field(ud_sq_wqe->byte_48,
272 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
273 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
274 ah->av.mac[5]);
275
276 /* MAC loopback */
277 smac = (u8 *)hr_dev->dev_addr[qp->port];
278 loopback = ether_addr_equal_unaligned(ah->av.mac,
279 smac) ? 1 : 0;
280
281 roce_set_bit(ud_sq_wqe->byte_40,
282 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
283
284 roce_set_field(ud_sq_wqe->byte_4,
285 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
286 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
287 HNS_ROCE_V2_WQE_OP_SEND);
2d407888 288
7bdee415 289 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 290 tmp_len += wr->sg_list[i].length;
492b2bd0 291
8b9b8d14 292 ud_sq_wqe->msg_len =
293 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len);
294
295 switch (wr->opcode) {
296 case IB_WR_SEND_WITH_IMM:
297 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 298 ud_sq_wqe->immtdata =
299 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 300 break;
301 default:
302 ud_sq_wqe->immtdata = 0;
303 break;
304 }
651487c2 305
7bdee415 306 /* Set sig attr */
307 roce_set_bit(ud_sq_wqe->byte_4,
308 V2_UD_SEND_WQE_BYTE_4_CQE_S,
309 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
a49d761f 310
7bdee415 311 /* Set se attr */
312 roce_set_bit(ud_sq_wqe->byte_4,
313 V2_UD_SEND_WQE_BYTE_4_SE_S,
314 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
e8d18533 315
7bdee415 316 roce_set_bit(ud_sq_wqe->byte_4,
317 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
318
319 roce_set_field(ud_sq_wqe->byte_16,
320 V2_UD_SEND_WQE_BYTE_16_PD_M,
321 V2_UD_SEND_WQE_BYTE_16_PD_S,
322 to_hr_pd(ibqp->pd)->pdn);
323
324 roce_set_field(ud_sq_wqe->byte_16,
325 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
326 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
327 wr->num_sge);
328
329 roce_set_field(ud_sq_wqe->byte_20,
330 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
331 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
332 sge_ind & (qp->sge.sge_cnt - 1));
333
334 roce_set_field(ud_sq_wqe->byte_24,
335 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
336 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
337 ud_sq_wqe->qkey =
8b9b8d14 338 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
339 qp->qkey : ud_wr(wr)->remote_qkey);
7bdee415 340 roce_set_field(ud_sq_wqe->byte_32,
341 V2_UD_SEND_WQE_BYTE_32_DQPN_M,
342 V2_UD_SEND_WQE_BYTE_32_DQPN_S,
343 ud_wr(wr)->remote_qpn);
344
345 roce_set_field(ud_sq_wqe->byte_36,
346 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
347 V2_UD_SEND_WQE_BYTE_36_VLAN_S,
8b9b8d14 348 le16_to_cpu(ah->av.vlan));
7bdee415 349 roce_set_field(ud_sq_wqe->byte_36,
350 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
351 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
352 ah->av.hop_limit);
353 roce_set_field(ud_sq_wqe->byte_36,
354 V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
355 V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
cdfa4ad5
LO		 356 ah->av.sl_tclass_flowlabel >>
357 HNS_ROCE_TCLASS_SHIFT);
7bdee415 358 roce_set_field(ud_sq_wqe->byte_40,
359 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
cdfa4ad5
LO		 360 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
361 ah->av.sl_tclass_flowlabel &
362 HNS_ROCE_FLOW_LABEL_MASK);
7bdee415 363 roce_set_field(ud_sq_wqe->byte_40,
364 V2_UD_SEND_WQE_BYTE_40_SL_M,
365 V2_UD_SEND_WQE_BYTE_40_SL_S,
8b9b8d14 366 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
367 HNS_ROCE_SL_SHIFT);
7bdee415 368 roce_set_field(ud_sq_wqe->byte_40,
369 V2_UD_SEND_WQE_BYTE_40_PORTN_M,
370 V2_UD_SEND_WQE_BYTE_40_PORTN_S,
371 qp->port);
372
8320deb8
LO		 373 roce_set_bit(ud_sq_wqe->byte_40,
374 V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
375 ah->av.vlan_en ? 1 : 0);
7bdee415 376 roce_set_field(ud_sq_wqe->byte_48,
377 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
378 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
379 hns_get_gid_index(hr_dev, qp->phy_port,
380 ah->av.gid_index));
381
382 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
383 GID_LEN_V2);
384
0b25c9cc 385 set_extend_sge(qp, wr, &sge_ind);
7bdee415 386 ind++;
387 } else if (ibqp->qp_type == IB_QPT_RC) {
388 rc_sq_wqe = wqe;
389 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
390 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 391 tmp_len += wr->sg_list[i].length;
392
393 rc_sq_wqe->msg_len =
394 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len);
7bdee415 395
8b9b8d14 396 switch (wr->opcode) {
397 case IB_WR_SEND_WITH_IMM:
398 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 399 rc_sq_wqe->immtdata =
400 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 401 break;
402 case IB_WR_SEND_WITH_INV:
403 rc_sq_wqe->inv_key =
404 cpu_to_le32(wr->ex.invalidate_rkey);
405 break;
406 default:
407 rc_sq_wqe->immtdata = 0;
408 break;
409 }
7bdee415 410
411 roce_set_bit(rc_sq_wqe->byte_4,
412 V2_RC_SEND_WQE_BYTE_4_FENCE_S,
413 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
414
415 roce_set_bit(rc_sq_wqe->byte_4,
416 V2_RC_SEND_WQE_BYTE_4_SE_S,
417 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
418
419 roce_set_bit(rc_sq_wqe->byte_4,
420 V2_RC_SEND_WQE_BYTE_4_CQE_S,
421 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
422
423 roce_set_bit(rc_sq_wqe->byte_4,
424 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
425
384f8818 426 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
7bdee415 427 switch (wr->opcode) {
428 case IB_WR_RDMA_READ:
b9c1ea40 429 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
7bdee415 430 rc_sq_wqe->rkey =
431 cpu_to_le32(rdma_wr(wr)->rkey);
432 rc_sq_wqe->va =
433 cpu_to_le64(rdma_wr(wr)->remote_addr);
434 break;
435 case IB_WR_RDMA_WRITE:
b9c1ea40 436 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
7bdee415 437 rc_sq_wqe->rkey =
438 cpu_to_le32(rdma_wr(wr)->rkey);
439 rc_sq_wqe->va =
440 cpu_to_le64(rdma_wr(wr)->remote_addr);
441 break;
442 case IB_WR_RDMA_WRITE_WITH_IMM:
b9c1ea40 443 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
7bdee415 444 rc_sq_wqe->rkey =
445 cpu_to_le32(rdma_wr(wr)->rkey);
446 rc_sq_wqe->va =
447 cpu_to_le64(rdma_wr(wr)->remote_addr);
448 break;
449 case IB_WR_SEND:
b9c1ea40 450 hr_op = HNS_ROCE_V2_WQE_OP_SEND;
7bdee415 451 break;
452 case IB_WR_SEND_WITH_INV:
b9c1ea40 453 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
7bdee415 454 break;
455 case IB_WR_SEND_WITH_IMM:
b9c1ea40 456 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
7bdee415 457 break;
458 case IB_WR_LOCAL_INV:
b9c1ea40 459 hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
e93df010
LO		 460 roce_set_bit(rc_sq_wqe->byte_4,
461 V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
462 rc_sq_wqe->inv_key =
463 cpu_to_le32(wr->ex.invalidate_rkey);
7bdee415 464 break;
465 case IB_WR_ATOMIC_CMP_AND_SWP:
b9c1ea40 466 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
384f8818
LO		 467 rc_sq_wqe->rkey =
468 cpu_to_le32(atomic_wr(wr)->rkey);
469 rc_sq_wqe->va =
470 cpu_to_le32(atomic_wr(wr)->remote_addr);
471 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
472 set_atomic_seg(wqe, atomic_wr(wr));
7bdee415 473 break;
474 case IB_WR_ATOMIC_FETCH_AND_ADD:
b9c1ea40 475 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
384f8818
LO		 476 rc_sq_wqe->rkey =
477 cpu_to_le32(atomic_wr(wr)->rkey);
478 rc_sq_wqe->va =
479 cpu_to_le32(atomic_wr(wr)->remote_addr);
480 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
481 set_atomic_seg(wqe, atomic_wr(wr));
7bdee415 482 break;
483 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
b9c1ea40
LO		 484 hr_op =
485 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
7bdee415 486 break;
487 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
b9c1ea40
LO		 488 hr_op =
489 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
7bdee415 490 break;
491 default:
b9c1ea40 492 hr_op = HNS_ROCE_V2_WQE_OP_MASK;
7bdee415 493 break;
2d407888
WHX		 494 }
495
b9c1ea40
LO		 496 roce_set_field(rc_sq_wqe->byte_4,
497 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
498 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
2d407888 499
7bdee415 500 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe,
501 &sge_ind, bad_wr);
502 if (ret)
503 goto out;
504 ind++;
2d407888 505 } else {
7bdee415 506 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
507 spin_unlock_irqrestore(&qp->sq.lock, flags);
137ae320 508 *bad_wr = wr;
7bdee415 509 return -EOPNOTSUPP;
2d407888 510 }
2d407888
WHX		 511 }
512
513out:
514 if (likely(nreq)) {
515 qp->sq.head += nreq;
516 /* Memory barrier */
517 wmb();
518
519 sq_db.byte_4 = 0;
520 sq_db.parameter = 0;
521
522 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
523 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
524 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
525 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
cc3391cb 526 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
527 V2_DB_PARAMETER_IDX_S,
2d407888
WHX		 528 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
529 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
530 V2_DB_PARAMETER_SL_S, qp->sl);
531
8b9b8d14 532 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l);
2d407888
WHX		 533
534 qp->sq_next_wqe = ind;
535 qp->next_sge = sge_ind;
0425e3e6
YL		 536
537 if (qp->state == IB_QPS_ERR) {
538 attr_mask = IB_QP_STATE;
539 attr.qp_state = IB_QPS_ERR;
540
541 ret = hns_roce_v2_modify_qp(&qp->ibqp, &attr, attr_mask,
542 qp->state, IB_QPS_ERR);
543 if (ret) {
544 spin_unlock_irqrestore(&qp->sq.lock, flags);
545 *bad_wr = wr;
546 return ret;
547 }
548 }
2d407888
WHX		 549 }
550
551 spin_unlock_irqrestore(&qp->sq.lock, flags);
552
553 return ret;
554}
555
d34ac5cd
BVA		 556static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
557 const struct ib_recv_wr *wr,
558 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 559{
560 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
561 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
562 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 563 struct hns_roce_rinl_sge *sge_list;
2d407888 564 struct device *dev = hr_dev->dev;
0425e3e6 565 struct ib_qp_attr attr;
2d407888
WHX		 566 unsigned long flags;
567 void *wqe = NULL;
0425e3e6 568 int attr_mask;
2d407888
WHX		 569 int ret = 0;
570 int nreq;
571 int ind;
572 int i;
573
574 spin_lock_irqsave(&hr_qp->rq.lock, flags);
575 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
576
ced07769 577 if (hr_qp->state == IB_QPS_RESET) {
2d407888
WHX		 578 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
579 *bad_wr = wr;
580 return -EINVAL;
581 }
582
583 for (nreq = 0; wr; ++nreq, wr = wr->next) {
584 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
585 hr_qp->ibqp.recv_cq)) {
586 ret = -ENOMEM;
587 *bad_wr = wr;
588 goto out;
589 }
590
591 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
592 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
593 wr->num_sge, hr_qp->rq.max_gs);
594 ret = -EINVAL;
595 *bad_wr = wr;
596 goto out;
597 }
598
599 wqe = get_recv_wqe(hr_qp, ind);
600 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
601 for (i = 0; i < wr->num_sge; i++) {
602 if (!wr->sg_list[i].length)
603 continue;
604 set_data_seg_v2(dseg, wr->sg_list + i);
605 dseg++;
606 }
607
608 if (i < hr_qp->rq.max_gs) {
778cc5a8 609 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
610 dseg->addr = 0;
2d407888
WHX		 611 }
612
0009c2db 613 /* rq support inline data */
ecaaf1e2 614 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
615 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
616 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
617 (u32)wr->num_sge;
618 for (i = 0; i < wr->num_sge; i++) {
619 sge_list[i].addr =
620 (void *)(u64)wr->sg_list[i].addr;
621 sge_list[i].len = wr->sg_list[i].length;
622 }
0009c2db 623 }
624
2d407888
WHX		 625 hr_qp->rq.wrid[ind] = wr->wr_id;
626
627 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
628 }
629
630out:
631 if (likely(nreq)) {
632 hr_qp->rq.head += nreq;
633 /* Memory barrier */
634 wmb();
635
472bc0fb 636 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
0425e3e6
YL		 637
638 if (hr_qp->state == IB_QPS_ERR) {
639 attr_mask = IB_QP_STATE;
640 attr.qp_state = IB_QPS_ERR;
641
642 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr,
643 attr_mask, hr_qp->state,
644 IB_QPS_ERR);
645 if (ret) {
646 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
647 *bad_wr = wr;
648 return ret;
649 }
650 }
2d407888
WHX		 651 }
652 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
653
654 return ret;
655}
656
a04ff739
WHX		 657static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
658{
659 int ntu = ring->next_to_use;
660 int ntc = ring->next_to_clean;
661 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
662
663 return ring->desc_num - used - 1;
664}
665
666static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
667 struct hns_roce_v2_cmq_ring *ring)
668{
669 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
670
671 ring->desc = kzalloc(size, GFP_KERNEL);
672 if (!ring->desc)
673 return -ENOMEM;
674
675 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
676 DMA_BIDIRECTIONAL);
677 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
678 ring->desc_dma_addr = 0;
679 kfree(ring->desc);
680 ring->desc = NULL;
681 return -ENOMEM;
682 }
683
684 return 0;
685}
686
687static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
688 struct hns_roce_v2_cmq_ring *ring)
689{
690 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
691 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
692 DMA_BIDIRECTIONAL);
90e7a4d5 693
694 ring->desc_dma_addr = 0;
a04ff739
WHX		 695 kfree(ring->desc);
696}
697
698static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
699{
700 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
701 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
702 &priv->cmq.csq : &priv->cmq.crq;
703
704 ring->flag = ring_type;
705 ring->next_to_clean = 0;
706 ring->next_to_use = 0;
707
708 return hns_roce_alloc_cmq_desc(hr_dev, ring);
709}
710
711static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
712{
713 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
714 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
715 &priv->cmq.csq : &priv->cmq.crq;
716 dma_addr_t dma = ring->desc_dma_addr;
717
718 if (ring_type == TYPE_CSQ) {
719 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
720 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
721 upper_32_bits(dma));
722 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
723 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
724 HNS_ROCE_CMQ_ENABLE);
725 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
726 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
727 } else {
728 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
729 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
730 upper_32_bits(dma));
731 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
732 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
733 HNS_ROCE_CMQ_ENABLE);
734 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
735 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
736 }
737}
738
739static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
740{
741 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
742 int ret;
743
744 /* Setup the queue entries for command queue */
426c4146
LO		 745 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
746 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 747
748 /* Setup the lock for command queue */
749 spin_lock_init(&priv->cmq.csq.lock);
750 spin_lock_init(&priv->cmq.crq.lock);
751
752 /* Setup Tx write back timeout */
753 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
754
755 /* Init CSQ */
756 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
757 if (ret) {
758 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
759 return ret;
760 }
761
762 /* Init CRQ */
763 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
764 if (ret) {
765 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
766 goto err_crq;
767 }
768
769 /* Init CSQ REG */
770 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
771
772 /* Init CRQ REG */
773 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
774
775 return 0;
776
777err_crq:
778 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
779
780 return ret;
781}
782
783static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
784{
785 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
786
787 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
788 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
789}
790
281d0ccf
CIK		 791static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
792 enum hns_roce_opcode_type opcode,
793 bool is_read)
a04ff739
WHX		 794{
795 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
796 desc->opcode = cpu_to_le16(opcode);
797 desc->flag =
798 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
799 if (is_read)
800 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
801 else
802 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
803}
804
805static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
806{
807 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
808 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
809
810 return head == priv->cmq.csq.next_to_use;
811}
812
813static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
814{
815 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
816 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
817 struct hns_roce_cmq_desc *desc;
818 u16 ntc = csq->next_to_clean;
819 u32 head;
820 int clean = 0;
821
822 desc = &csq->desc[ntc];
823 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
824 while (head != ntc) {
825 memset(desc, 0, sizeof(*desc));
826 ntc++;
827 if (ntc == csq->desc_num)
828 ntc = 0;
829 desc = &csq->desc[ntc];
830 clean++;
831 }
832 csq->next_to_clean = ntc;
833
834 return clean;
835}
836
281d0ccf
CIK		 837static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
838 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 839{
840 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
841 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
842 struct hns_roce_cmq_desc *desc_to_use;
843 bool complete = false;
844 u32 timeout = 0;
845 int handle = 0;
846 u16 desc_ret;
847 int ret = 0;
848 int ntc;
849
cb7a94c9
WHX		 850 if (hr_dev->is_reset)
851 return 0;
852
a04ff739
WHX		 853 spin_lock_bh(&csq->lock);
854
855 if (num > hns_roce_cmq_space(csq)) {
856 spin_unlock_bh(&csq->lock);
857 return -EBUSY;
858 }
859
860 /*
861 * Record the location of desc in the cmq for this time
862 * which will be use for hardware to write back
863 */
864 ntc = csq->next_to_use;
865
866 while (handle < num) {
867 desc_to_use = &csq->desc[csq->next_to_use];
868 *desc_to_use = desc[handle];
869 dev_dbg(hr_dev->dev, "set cmq desc:\n");
870 csq->next_to_use++;
871 if (csq->next_to_use == csq->desc_num)
872 csq->next_to_use = 0;
873 handle++;
874 }
875
876 /* Write to hardware */
877 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
878
879 /*
880 * If the command is sync, wait for the firmware to write back,
881 * if multi descriptors to be sent, use the first one to check
882 */
883 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
884 do {
885 if (hns_roce_cmq_csq_done(hr_dev))
886 break;
988e175b 887 udelay(1);
a04ff739
WHX		 888 timeout++;
889 } while (timeout < priv->cmq.tx_timeout);
890 }
891
892 if (hns_roce_cmq_csq_done(hr_dev)) {
893 complete = true;
894 handle = 0;
895 while (handle < num) {
896 /* get the result of hardware write back */
897 desc_to_use = &csq->desc[ntc];
898 desc[handle] = *desc_to_use;
899 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
900 desc_ret = desc[handle].retval;
901 if (desc_ret == CMD_EXEC_SUCCESS)
902 ret = 0;
903 else
904 ret = -EIO;
905 priv->cmq.last_status = desc_ret;
906 ntc++;
907 handle++;
908 if (ntc == csq->desc_num)
909 ntc = 0;
910 }
911 }
912
913 if (!complete)
914 ret = -EAGAIN;
915
916 /* clean the command send queue */
917 handle = hns_roce_cmq_csq_clean(hr_dev);
918 if (handle != num)
919 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
920 handle, num);
921
922 spin_unlock_bh(&csq->lock);
923
924 return ret;
925}
926
281d0ccf 927static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 928{
929 struct hns_roce_query_version *resp;
930 struct hns_roce_cmq_desc desc;
931 int ret;
932
933 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
934 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
935 if (ret)
936 return ret;
937
938 resp = (struct hns_roce_query_version *)desc.data;
939 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 940 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
941
942 return 0;
943}
944
945static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
946{
947 struct hns_roce_query_fw_info *resp;
948 struct hns_roce_cmq_desc desc;
949 int ret;
950
951 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
952 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
953 if (ret)
954 return ret;
955
956 resp = (struct hns_roce_query_fw_info *)desc.data;
957 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 958
959 return 0;
960}
961
962static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
963{
964 struct hns_roce_cfg_global_param *req;
965 struct hns_roce_cmq_desc desc;
966
967 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
968 false);
969
970 req = (struct hns_roce_cfg_global_param *)desc.data;
971 memset(req, 0, sizeof(*req));
972 roce_set_field(req->time_cfg_udp_port,
973 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
974 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
975 roce_set_field(req->time_cfg_udp_port,
976 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
977 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
978
979 return hns_roce_cmq_send(hr_dev, &desc, 1);
980}
981
982static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
983{
984 struct hns_roce_cmq_desc desc[2];
6b63597d 985 struct hns_roce_pf_res_a *req_a;
986 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 987 int ret;
988 int i;
989
990 for (i = 0; i < 2; i++) {
991 hns_roce_cmq_setup_basic_desc(&desc[i],
992 HNS_ROCE_OPC_QUERY_PF_RES, true);
993
994 if (i == 0)
995 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
996 else
997 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
998 }
999
1000 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1001 if (ret)
1002 return ret;
1003
6b63597d 1004 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1005 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1006
6b63597d 1007 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1008 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1009 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1010 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1011 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1012 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1013 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1014 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1015 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1016 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1017 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1018 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1019
6b63597d 1020 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1021 PF_RES_DATA_3_PF_SL_NUM_M,
1022 PF_RES_DATA_3_PF_SL_NUM_S);
1023
cfc85f3e
WHX		 1024 return 0;
1025}
1026
1027static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1028{
1029 struct hns_roce_cmq_desc desc[2];
1030 struct hns_roce_vf_res_a *req_a;
1031 struct hns_roce_vf_res_b *req_b;
1032 int i;
1033
1034 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1035 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1036 memset(req_a, 0, sizeof(*req_a));
1037 memset(req_b, 0, sizeof(*req_b));
1038 for (i = 0; i < 2; i++) {
1039 hns_roce_cmq_setup_basic_desc(&desc[i],
1040 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1041
1042 if (i == 0)
1043 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1044 else
1045 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1046
1047 if (i == 0) {
1048 roce_set_field(req_a->vf_qpc_bt_idx_num,
1049 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1050 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1051 roce_set_field(req_a->vf_qpc_bt_idx_num,
1052 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1053 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
1054 HNS_ROCE_VF_QPC_BT_NUM);
1055
1056 roce_set_field(req_a->vf_srqc_bt_idx_num,
1057 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1058 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1059 roce_set_field(req_a->vf_srqc_bt_idx_num,
1060 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1061 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1062 HNS_ROCE_VF_SRQC_BT_NUM);
1063
1064 roce_set_field(req_a->vf_cqc_bt_idx_num,
1065 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1066 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1067 roce_set_field(req_a->vf_cqc_bt_idx_num,
1068 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1069 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
1070 HNS_ROCE_VF_CQC_BT_NUM);
1071
1072 roce_set_field(req_a->vf_mpt_bt_idx_num,
1073 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1074 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1075 roce_set_field(req_a->vf_mpt_bt_idx_num,
1076 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1077 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
1078 HNS_ROCE_VF_MPT_BT_NUM);
1079
1080 roce_set_field(req_a->vf_eqc_bt_idx_num,
1081 VF_RES_A_DATA_5_VF_EQC_IDX_M,
1082 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1083 roce_set_field(req_a->vf_eqc_bt_idx_num,
1084 VF_RES_A_DATA_5_VF_EQC_NUM_M,
1085 VF_RES_A_DATA_5_VF_EQC_NUM_S,
1086 HNS_ROCE_VF_EQC_NUM);
1087 } else {
1088 roce_set_field(req_b->vf_smac_idx_num,
1089 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1090 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1091 roce_set_field(req_b->vf_smac_idx_num,
1092 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1093 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
1094 HNS_ROCE_VF_SMAC_NUM);
1095
1096 roce_set_field(req_b->vf_sgid_idx_num,
1097 VF_RES_B_DATA_2_VF_SGID_IDX_M,
1098 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1099 roce_set_field(req_b->vf_sgid_idx_num,
1100 VF_RES_B_DATA_2_VF_SGID_NUM_M,
1101 VF_RES_B_DATA_2_VF_SGID_NUM_S,
1102 HNS_ROCE_VF_SGID_NUM);
1103
1104 roce_set_field(req_b->vf_qid_idx_sl_num,
1105 VF_RES_B_DATA_3_VF_QID_IDX_M,
1106 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1107 roce_set_field(req_b->vf_qid_idx_sl_num,
1108 VF_RES_B_DATA_3_VF_SL_NUM_M,
1109 VF_RES_B_DATA_3_VF_SL_NUM_S,
1110 HNS_ROCE_VF_SL_NUM);
1111 }
1112 }
1113
1114 return hns_roce_cmq_send(hr_dev, desc, 2);
1115}
1116
a81fba28
WHX		 1117static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1118{
1119 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1120 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1121 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1122 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
1123 struct hns_roce_cfg_bt_attr *req;
1124 struct hns_roce_cmq_desc desc;
1125
1126 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1127 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1128 memset(req, 0, sizeof(*req));
1129
1130 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1131 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1132 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1133 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1134 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1135 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1136 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1137 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1138 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1139
1140 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1141 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1142 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1143 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1144 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1145 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1146 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1147 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1148 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1149
1150 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1151 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1152 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1153 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1154 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1155 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1156 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1157 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1158 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1159
1160 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1161 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1162 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1163 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1164 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1165 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1166 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1167 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1168 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1169
1170 return hns_roce_cmq_send(hr_dev, &desc, 1);
1171}
1172
cfc85f3e
WHX		 1173static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1174{
1175 struct hns_roce_caps *caps = &hr_dev->caps;
1176 int ret;
1177
1178 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 1179 if (ret) {
1180 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
1181 ret);
1182 return ret;
1183 }
1184
1185 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 1186 if (ret) {
1187 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1188 ret);
1189 return ret;
1190 }
1191
1192 ret = hns_roce_config_global_param(hr_dev);
1193 if (ret) {
1194 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1195 ret);
2349fdd4 1196 return ret;
cfc85f3e
WHX		 1197 }
1198
1199 /* Get pf resource owned by every pf */
1200 ret = hns_roce_query_pf_resource(hr_dev);
1201 if (ret) {
1202 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1203 ret);
1204 return ret;
1205 }
1206
1207 ret = hns_roce_alloc_vf_resource(hr_dev);
1208 if (ret) {
1209 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
1210 ret);
1211 return ret;
1212 }
1213
3a63c964
LO		 1214
1215 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
1216 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e
WHX		 1217
1218 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1219 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1220 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1221 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1222 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
05ad5482 1223 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
cfc85f3e
WHX		 1224 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1225 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1226 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1227 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
a5073d60
YL		 1228 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1229 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1230 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
cfc85f3e
WHX		 1231 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1232 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1233 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1234 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1235 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1236 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1237 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1238 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1239 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1240 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1241 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 1242 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e
WHX		 1243 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1244 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1245 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1246 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1247 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1248 caps->reserved_lkey = 0;
1249 caps->reserved_pds = 0;
1250 caps->reserved_mrws = 1;
1251 caps->reserved_uars = 0;
1252 caps->reserved_cqs = 0;
06ef0ee4 1253 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
cfc85f3e 1254
a25d13cb
SX		 1255 caps->qpc_ba_pg_sz = 0;
1256 caps->qpc_buf_pg_sz = 0;
1257 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1258 caps->srqc_ba_pg_sz = 0;
1259 caps->srqc_buf_pg_sz = 0;
1260 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
1261 caps->cqc_ba_pg_sz = 0;
1262 caps->cqc_buf_pg_sz = 0;
1263 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1264 caps->mpt_ba_pg_sz = 0;
1265 caps->mpt_buf_pg_sz = 0;
1266 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
ff795f71
WHX		 1267 caps->pbl_ba_pg_sz = 0;
1268 caps->pbl_buf_pg_sz = 0;
1269 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 1270 caps->mtt_ba_pg_sz = 0;
1271 caps->mtt_buf_pg_sz = 0;
1272 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1273 caps->cqe_ba_pg_sz = 0;
1274 caps->cqe_buf_pg_sz = 0;
1275 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
a5073d60
YL		 1276 caps->eqe_ba_pg_sz = 0;
1277 caps->eqe_buf_pg_sz = 0;
1278 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1279 caps->tsq_buf_pg_sz = 0;
29a1fe5d 1280 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 1281
023c1477 1282 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
0009c2db 1283 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
e088a685 1284 HNS_ROCE_CAP_FLAG_RQ_INLINE |
0425e3e6
YL		 1285 HNS_ROCE_CAP_FLAG_RECORD_DB |
1286 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
c7c28191
YL		 1287
1288 if (hr_dev->pci_dev->revision == 0x21)
1289 caps->flags |= HNS_ROCE_CAP_FLAG_MW;
1290
cfc85f3e 1291 caps->pkey_table_len[0] = 1;
b5ff0f61 1292 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
a5073d60
YL		 1293 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1294 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
cfc85f3e
WHX		 1295 caps->local_ca_ack_delay = 0;
1296 caps->max_mtu = IB_MTU_4096;
1297
384f8818
LO		 1298 if (hr_dev->pci_dev->revision == 0x21)
1299 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC;
1300
a81fba28
WHX		 1301 ret = hns_roce_v2_set_bt(hr_dev);
1302 if (ret)
1303 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
1304 ret);
1305
1306 return ret;
cfc85f3e
WHX		 1307}
1308
6b63597d 1309static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
1310 enum hns_roce_link_table_type type)
1311{
1312 struct hns_roce_cmq_desc desc[2];
1313 struct hns_roce_cfg_llm_a *req_a =
1314 (struct hns_roce_cfg_llm_a *)desc[0].data;
1315 struct hns_roce_cfg_llm_b *req_b =
1316 (struct hns_roce_cfg_llm_b *)desc[1].data;
1317 struct hns_roce_v2_priv *priv = hr_dev->priv;
1318 struct hns_roce_link_table *link_tbl;
1319 struct hns_roce_link_table_entry *entry;
1320 enum hns_roce_opcode_type opcode;
1321 u32 page_num;
1322 int i;
1323
1324 switch (type) {
1325 case TSQ_LINK_TABLE:
1326 link_tbl = &priv->tsq;
1327 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
1328 break;
ded58ff9 1329 case TPQ_LINK_TABLE:
1330 link_tbl = &priv->tpq;
1331 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
1332 break;
6b63597d 1333 default:
1334 return -EINVAL;
1335 }
1336
1337 page_num = link_tbl->npages;
1338 entry = link_tbl->table.buf;
1339 memset(req_a, 0, sizeof(*req_a));
1340 memset(req_b, 0, sizeof(*req_b));
1341
1342 for (i = 0; i < 2; i++) {
1343 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
1344
1345 if (i == 0)
1346 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1347 else
1348 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1349
1350 if (i == 0) {
1351 req_a->base_addr_l = link_tbl->table.map & 0xffffffff;
1352 req_a->base_addr_h = (link_tbl->table.map >> 32) &
1353 0xffffffff;
1354 roce_set_field(req_a->depth_pgsz_init_en,
1355 CFG_LLM_QUE_DEPTH_M,
1356 CFG_LLM_QUE_DEPTH_S,
1357 link_tbl->npages);
1358 roce_set_field(req_a->depth_pgsz_init_en,
1359 CFG_LLM_QUE_PGSZ_M,
1360 CFG_LLM_QUE_PGSZ_S,
1361 link_tbl->pg_sz);
1362 req_a->head_ba_l = entry[0].blk_ba0;
1363 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr;
1364 roce_set_field(req_a->head_ptr,
1365 CFG_LLM_HEAD_PTR_M,
1366 CFG_LLM_HEAD_PTR_S, 0);
1367 } else {
1368 req_b->tail_ba_l = entry[page_num - 1].blk_ba0;
1369 roce_set_field(req_b->tail_ba_h,
1370 CFG_LLM_TAIL_BA_H_M,
1371 CFG_LLM_TAIL_BA_H_S,
1372 entry[page_num - 1].blk_ba1_nxt_ptr &
1373 HNS_ROCE_LINK_TABLE_BA1_M);
1374 roce_set_field(req_b->tail_ptr,
1375 CFG_LLM_TAIL_PTR_M,
1376 CFG_LLM_TAIL_PTR_S,
1377 (entry[page_num - 2].blk_ba1_nxt_ptr &
1378 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
1379 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
1380 }
1381 }
1382 roce_set_field(req_a->depth_pgsz_init_en,
1383 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1);
1384
1385 return hns_roce_cmq_send(hr_dev, desc, 2);
1386}
1387
1388static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
1389 enum hns_roce_link_table_type type)
1390{
1391 struct hns_roce_v2_priv *priv = hr_dev->priv;
1392 struct hns_roce_link_table *link_tbl;
1393 struct hns_roce_link_table_entry *entry;
1394 struct device *dev = hr_dev->dev;
1395 u32 buf_chk_sz;
1396 dma_addr_t t;
ded58ff9 1397 int func_num = 1;
6b63597d 1398 int pg_num_a;
1399 int pg_num_b;
1400 int pg_num;
1401 int size;
1402 int i;
1403
1404 switch (type) {
1405 case TSQ_LINK_TABLE:
1406 link_tbl = &priv->tsq;
1407 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
1408 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
1409 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
1410 break;
ded58ff9 1411 case TPQ_LINK_TABLE:
1412 link_tbl = &priv->tpq;
1413 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
1414 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
1415 pg_num_b = 2 * 4 * func_num + 2;
1416 break;
6b63597d 1417 default:
1418 return -EINVAL;
1419 }
1420
1421 pg_num = max(pg_num_a, pg_num_b);
1422 size = pg_num * sizeof(struct hns_roce_link_table_entry);
1423
1424 link_tbl->table.buf = dma_alloc_coherent(dev, size,
1425 &link_tbl->table.map,
1426 GFP_KERNEL);
1427 if (!link_tbl->table.buf)
1428 goto out;
1429
1430 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
1431 GFP_KERNEL);
1432 if (!link_tbl->pg_list)
1433 goto err_kcalloc_failed;
1434
1435 entry = link_tbl->table.buf;
1436 for (i = 0; i < pg_num; ++i) {
1437 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
1438 &t, GFP_KERNEL);
1439 if (!link_tbl->pg_list[i].buf)
1440 goto err_alloc_buf_failed;
1441
1442 link_tbl->pg_list[i].map = t;
1443 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz);
1444
1445 entry[i].blk_ba0 = (t >> 12) & 0xffffffff;
1446 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1447 HNS_ROCE_LINK_TABLE_BA1_M,
1448 HNS_ROCE_LINK_TABLE_BA1_S,
1449 t >> 44);
1450
1451 if (i < (pg_num - 1))
1452 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1453 HNS_ROCE_LINK_TABLE_NXT_PTR_M,
1454 HNS_ROCE_LINK_TABLE_NXT_PTR_S,
1455 i + 1);
1456 }
1457 link_tbl->npages = pg_num;
1458 link_tbl->pg_sz = buf_chk_sz;
1459
1460 return hns_roce_config_link_table(hr_dev, type);
1461
1462err_alloc_buf_failed:
1463 for (i -= 1; i >= 0; i--)
1464 dma_free_coherent(dev, buf_chk_sz,
1465 link_tbl->pg_list[i].buf,
1466 link_tbl->pg_list[i].map);
1467 kfree(link_tbl->pg_list);
1468
1469err_kcalloc_failed:
1470 dma_free_coherent(dev, size, link_tbl->table.buf,
1471 link_tbl->table.map);
1472
1473out:
1474 return -ENOMEM;
1475}
1476
1477static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
1478 struct hns_roce_link_table *link_tbl)
1479{
1480 struct device *dev = hr_dev->dev;
1481 int size;
1482 int i;
1483
1484 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
1485
1486 for (i = 0; i < link_tbl->npages; ++i)
1487 if (link_tbl->pg_list[i].buf)
1488 dma_free_coherent(dev, link_tbl->pg_sz,
1489 link_tbl->pg_list[i].buf,
1490 link_tbl->pg_list[i].map);
1491 kfree(link_tbl->pg_list);
1492
1493 dma_free_coherent(dev, size, link_tbl->table.buf,
1494 link_tbl->table.map);
1495}
1496
1497static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
1498{
ded58ff9 1499 struct hns_roce_v2_priv *priv = hr_dev->priv;
6b63597d 1500 int ret;
1501
1502 /* TSQ includes SQ doorbell and ack doorbell */
1503 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 1504 if (ret) {
6b63597d 1505 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 1506 return ret;
1507 }
1508
1509 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
1510 if (ret) {
1511 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
1512 goto err_tpq_init_failed;
1513 }
1514
1515 return 0;
1516
1517err_tpq_init_failed:
1518 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 1519
1520 return ret;
1521}
1522
1523static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
1524{
1525 struct hns_roce_v2_priv *priv = hr_dev->priv;
1526
ded58ff9 1527 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 1528 hns_roce_free_link_table(hr_dev, &priv->tsq);
1529}
1530
a680f2f3
WHX		 1531static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
1532{
1533 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1534
1535 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
1536}
1537
1538static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
1539{
1540 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1541
1542 return status & HNS_ROCE_HW_MB_STATUS_MASK;
1543}
1544
1545static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1546 u64 out_param, u32 in_modifier, u8 op_modifier,
1547 u16 op, u16 token, int event)
1548{
1549 struct device *dev = hr_dev->dev;
cc4ed08b
BVA		 1550 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base +
1551 ROCEE_VF_MB_CFG0_REG);
a680f2f3
WHX		 1552 unsigned long end;
1553 u32 val0 = 0;
1554 u32 val1 = 0;
1555
1556 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1557 while (hns_roce_v2_cmd_pending(hr_dev)) {
1558 if (time_after(jiffies, end)) {
1559 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1560 (int)end);
1561 return -EAGAIN;
1562 }
1563 cond_resched();
1564 }
1565
1566 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK,
1567 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier);
1568 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK,
1569 HNS_ROCE_VF_MB4_CMD_SHIFT, op);
1570 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK,
1571 HNS_ROCE_VF_MB5_EVENT_SHIFT, event);
1572 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK,
1573 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token);
1574
71591d12
AS		 1575 writeq(in_param, hcr + 0);
1576 writeq(out_param, hcr + 2);
a680f2f3
WHX		 1577
1578 /* Memory barrier */
1579 wmb();
1580
71591d12
AS		 1581 writel(val0, hcr + 4);
1582 writel(val1, hcr + 5);
a680f2f3
WHX		 1583
1584 mmiowb();
1585
1586 return 0;
1587}
1588
1589static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1590 unsigned long timeout)
1591{
1592 struct device *dev = hr_dev->dev;
1593 unsigned long end = 0;
1594 u32 status;
1595
1596 end = msecs_to_jiffies(timeout) + jiffies;
1597 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1598 cond_resched();
1599
1600 if (hns_roce_v2_cmd_pending(hr_dev)) {
1601 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1602 return -ETIMEDOUT;
1603 }
1604
1605 status = hns_roce_v2_cmd_complete(hr_dev);
1606 if (status != 0x1) {
1607 dev_err(dev, "mailbox status 0x%x!\n", status);
1608 return -EBUSY;
1609 }
1610
1611 return 0;
1612}
1613
4db134a3 1614static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
1615 int gid_index, const union ib_gid *gid,
1616 enum hns_roce_sgid_type sgid_type)
1617{
1618 struct hns_roce_cmq_desc desc;
1619 struct hns_roce_cfg_sgid_tb *sgid_tb =
1620 (struct hns_roce_cfg_sgid_tb *)desc.data;
1621 u32 *p;
1622
1623 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
1624
1625 roce_set_field(sgid_tb->table_idx_rsv,
1626 CFG_SGID_TB_TABLE_IDX_M,
1627 CFG_SGID_TB_TABLE_IDX_S, gid_index);
1628 roce_set_field(sgid_tb->vf_sgid_type_rsv,
1629 CFG_SGID_TB_VF_SGID_TYPE_M,
1630 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
1631
1632 p = (u32 *)&gid->raw[0];
1633 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
1634
1635 p = (u32 *)&gid->raw[4];
1636 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
1637
1638 p = (u32 *)&gid->raw[8];
1639 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
1640
1641 p = (u32 *)&gid->raw[0xc];
1642 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
1643
1644 return hns_roce_cmq_send(hr_dev, &desc, 1);
1645}
1646
b5ff0f61 1647static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 1648 int gid_index, const union ib_gid *gid,
b5ff0f61 1649 const struct ib_gid_attr *attr)
7afddafa 1650{
b5ff0f61 1651 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 1652 int ret;
7afddafa 1653
b5ff0f61
WHX		 1654 if (!gid || !attr)
1655 return -EINVAL;
1656
1657 if (attr->gid_type == IB_GID_TYPE_ROCE)
1658 sgid_type = GID_TYPE_FLAG_ROCE_V1;
1659
1660 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
1661 if (ipv6_addr_v4mapped((void *)gid))
1662 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
1663 else
1664 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
1665 }
1666
4db134a3 1667 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
1668 if (ret)
1669 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);
b5ff0f61 1670
4db134a3 1671 return ret;
7afddafa
WHX		 1672}
1673
a74dc41d
WHX		 1674static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1675 u8 *addr)
7afddafa 1676{
e8e8b652 1677 struct hns_roce_cmq_desc desc;
1678 struct hns_roce_cfg_smac_tb *smac_tb =
1679 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 1680 u16 reg_smac_h;
1681 u32 reg_smac_l;
e8e8b652 1682
1683 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 1684
1685 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 1686 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 1687
e8e8b652 1688 memset(smac_tb, 0, sizeof(*smac_tb));
1689 roce_set_field(smac_tb->tb_idx_rsv,
1690 CFG_SMAC_TB_IDX_M,
1691 CFG_SMAC_TB_IDX_S, phy_port);
1692 roce_set_field(smac_tb->vf_smac_h_rsv,
1693 CFG_SMAC_TB_VF_SMAC_H_M,
1694 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
1695 smac_tb->vf_smac_l = reg_smac_l;
a74dc41d 1696
e8e8b652 1697 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 1698}
1699
3958cc56
WHX		 1700static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1701 unsigned long mtpt_idx)
1702{
1703 struct hns_roce_v2_mpt_entry *mpt_entry;
1704 struct scatterlist *sg;
db270c41 1705 u64 page_addr;
3958cc56 1706 u64 *pages;
db270c41
WHX		 1707 int i, j;
1708 int len;
3958cc56 1709 int entry;
3958cc56
WHX		 1710
1711 mpt_entry = mb_buf;
1712 memset(mpt_entry, 0, sizeof(*mpt_entry));
1713
1714 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1715 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
1716 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1717 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
1718 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
1719 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1720 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 1721 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1722 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1723 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1724 V2_MPT_BYTE_4_PD_S, mr->pd);
1725 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
1726
1727 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
1728 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
e93df010 1729 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 1730 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
1731 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 1732 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
1733 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 1734 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1735 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1736 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1737 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1738 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1739 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1740 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
1741
1742 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
1743 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 1744 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
1745 1);
3958cc56
WHX		 1746 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
1747
1748 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
1749 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
1750 mpt_entry->lkey = cpu_to_le32(mr->key);
1751 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
1752 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
1753
1754 if (mr->type == MR_TYPE_DMA)
1755 return 0;
1756
1757 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1758
1759 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1760 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1761 V2_MPT_BYTE_48_PBL_BA_H_S,
1762 upper_32_bits(mr->pbl_ba >> 3));
1763 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
1764
1765 pages = (u64 *)__get_free_page(GFP_KERNEL);
1766 if (!pages)
1767 return -ENOMEM;
1768
1769 i = 0;
1770 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
db270c41
WHX		 1771 len = sg_dma_len(sg) >> PAGE_SHIFT;
1772 for (j = 0; j < len; ++j) {
1773 page_addr = sg_dma_address(sg) +
1774 (j << mr->umem->page_shift);
1775 pages[i] = page_addr >> 6;
1776
1777 /* Record the first 2 entry directly to MTPT table */
1778 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1779 goto found;
1780 i++;
1781 }
3958cc56
WHX		 1782 }
1783
db270c41 1784found:
3958cc56
WHX		 1785 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1786 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1787 V2_MPT_BYTE_56_PA0_H_S,
1788 upper_32_bits(pages[0]));
1789 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
1790
1791 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
1792 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
1793 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
1794
1795 free_page((unsigned long)pages);
1796
1797 roce_set_field(mpt_entry->byte_64_buf_pa1,
1798 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
5e6e78db
YL		 1799 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1800 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1801 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
1802
1803 return 0;
1804}
1805
a2c80b7b
WHX		 1806static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
1807 struct hns_roce_mr *mr, int flags,
1808 u32 pdn, int mr_access_flags, u64 iova,
1809 u64 size, void *mb_buf)
1810{
1811 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
1812
1813 if (flags & IB_MR_REREG_PD) {
1814 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1815 V2_MPT_BYTE_4_PD_S, pdn);
1816 mr->pd = pdn;
1817 }
1818
1819 if (flags & IB_MR_REREG_ACCESS) {
1820 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1821 V2_MPT_BYTE_8_BIND_EN_S,
1822 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
1823 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1824 V2_MPT_BYTE_8_ATOMIC_EN_S,
1825 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
1826 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1827 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
1828 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1829 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1830 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1831 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1832 }
1833
1834 if (flags & IB_MR_REREG_TRANS) {
1835 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
1836 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
1837 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
1838 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
1839
1840 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1841 mpt_entry->pbl_ba_l =
1842 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1843 roce_set_field(mpt_entry->byte_48_mode_ba,
1844 V2_MPT_BYTE_48_PBL_BA_H_M,
1845 V2_MPT_BYTE_48_PBL_BA_H_S,
1846 upper_32_bits(mr->pbl_ba >> 3));
1847 mpt_entry->byte_48_mode_ba =
1848 cpu_to_le32(mpt_entry->byte_48_mode_ba);
1849
1850 mr->iova = iova;
1851 mr->size = size;
1852 }
1853
1854 return 0;
1855}
1856
c7c28191
YL		 1857static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
1858{
1859 struct hns_roce_v2_mpt_entry *mpt_entry;
1860
1861 mpt_entry = mb_buf;
1862 memset(mpt_entry, 0, sizeof(*mpt_entry));
1863
1864 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1865 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
1866 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1867 V2_MPT_BYTE_4_PD_S, mw->pdn);
1868 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1869 V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1870 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
1871 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ?
1872 0 : mw->pbl_hop_num);
1873 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1874 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1875 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1876 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
1877
1878 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1879 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
1880
1881 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
1882 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
1883 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
1884 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
1885 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
1886
1887 roce_set_field(mpt_entry->byte_64_buf_pa1,
1888 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
1889 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1890 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
1891
1892 mpt_entry->lkey = cpu_to_le32(mw->rkey);
1893
1894 return 0;
1895}
1896
93aa2187
WHX		 1897static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1898{
1899 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1900 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
1901}
1902
1903static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1904{
1905 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
1906
1907 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1908 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
1909 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
1910}
1911
1912static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
1913{
1914 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
1915}
1916
1917static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1918{
86188a88 1919 *hr_cq->set_ci_db = cons_index & 0xffffff;
93aa2187
WHX		 1920}
1921
926a01dc
WHX		 1922static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1923 struct hns_roce_srq *srq)
1924{
1925 struct hns_roce_v2_cqe *cqe, *dest;
1926 u32 prod_index;
1927 int nfreed = 0;
1928 u8 owner_bit;
1929
1930 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
1931 ++prod_index) {
1932 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1933 break;
1934 }
1935
1936 /*
1937 * Now backwards through the CQ, removing CQ entries
1938 * that match our QP by overwriting them with next entries.
1939 */
1940 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1941 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1942 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
1943 V2_CQE_BYTE_16_LCL_QPN_S) &
1944 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
1945 /* In v1 engine, not support SRQ */
1946 ++nfreed;
1947 } else if (nfreed) {
1948 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
1949 hr_cq->ib_cq.cqe);
1950 owner_bit = roce_get_bit(dest->byte_4,
1951 V2_CQE_BYTE_4_OWNER_S);
1952 memcpy(dest, cqe, sizeof(*cqe));
1953 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
1954 owner_bit);
1955 }
1956 }
1957
1958 if (nfreed) {
1959 hr_cq->cons_index += nfreed;
1960 /*
1961 * Make sure update of buffer contents is done before
1962 * updating consumer index.
1963 */
1964 wmb();
1965 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
1966 }
1967}
1968
1969static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1970 struct hns_roce_srq *srq)
1971{
1972 spin_lock_irq(&hr_cq->lock);
1973 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
1974 spin_unlock_irq(&hr_cq->lock);
1975}
1976
93aa2187
WHX		 1977static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
1978 struct hns_roce_cq *hr_cq, void *mb_buf,
1979 u64 *mtts, dma_addr_t dma_handle, int nent,
1980 u32 vector)
1981{
1982 struct hns_roce_v2_cq_context *cq_context;
1983
1984 cq_context = mb_buf;
1985 memset(cq_context, 0, sizeof(*cq_context));
1986
1987 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
1988 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 1989 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
1990 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187
WHX		 1991 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
1992 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
1993 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
1994 V2_CQC_BYTE_4_CEQN_S, vector);
1995 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
1996
1997 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
1998 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
1999
2000 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2001 cq_context->cqe_cur_blk_addr =
2002 cpu_to_le32(cq_context->cqe_cur_blk_addr);
2003
2004 roce_set_field(cq_context->byte_16_hop_addr,
2005 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2006 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
2007 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
2008 roce_set_field(cq_context->byte_16_hop_addr,
2009 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2010 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2011 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2012
2013 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
2014 roce_set_field(cq_context->byte_24_pgsz_addr,
2015 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2016 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
2017 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
2018 roce_set_field(cq_context->byte_24_pgsz_addr,
2019 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2020 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 2021 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2022 roce_set_field(cq_context->byte_24_pgsz_addr,
2023 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2024 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 2025 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2026
2027 cq_context->cqe_ba = (u32)(dma_handle >> 3);
2028
2029 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2030 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2031
9b44703d
YL		 2032 if (hr_cq->db_en)
2033 roce_set_bit(cq_context->byte_44_db_record,
2034 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
2035
2036 roce_set_field(cq_context->byte_44_db_record,
2037 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2038 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2039 ((u32)hr_cq->db.dma) >> 1);
2040 cq_context->db_record_addr = hr_cq->db.dma >> 32;
2041
a5073d60
YL		 2042 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2043 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2044 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2045 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2046 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2047 V2_CQC_BYTE_56_CQ_PERIOD_M,
2048 V2_CQC_BYTE_56_CQ_PERIOD_S,
2049 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2050}
2051
2052static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2053 enum ib_cq_notify_flags flags)
2054{
2055 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2056 u32 notification_flag;
2057 u32 doorbell[2];
2058
2059 doorbell[0] = 0;
2060 doorbell[1] = 0;
2061
2062 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2063 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2064 /*
2065 * flags = 0; Notification Flag = 1, next
2066 * flags = 1; Notification Flag = 0, solocited
2067 */
2068 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2069 hr_cq->cqn);
2070 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2071 HNS_ROCE_V2_CQ_DB_NTR);
2072 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2073 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2074 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2075 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2076 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2077 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2078 notification_flag);
2079
2080 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2081
2082 return 0;
2083}
2084
0009c2db 2085static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2086 struct hns_roce_qp **cur_qp,
2087 struct ib_wc *wc)
2088{
2089 struct hns_roce_rinl_sge *sge_list;
2090 u32 wr_num, wr_cnt, sge_num;
2091 u32 sge_cnt, data_len, size;
2092 void *wqe_buf;
2093
2094 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2095 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2096 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2097
2098 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2099 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
2100 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt);
2101 data_len = wc->byte_len;
2102
2103 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2104 size = min(sge_list[sge_cnt].len, data_len);
2105 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2106
2107 data_len -= size;
2108 wqe_buf += size;
2109 }
2110
2111 if (data_len) {
2112 wc->status = IB_WC_LOC_LEN_ERR;
2113 return -EAGAIN;
2114 }
2115
2116 return 0;
2117}
2118
93aa2187
WHX		 2119static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2120 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2121{
2122 struct hns_roce_dev *hr_dev;
2123 struct hns_roce_v2_cqe *cqe;
2124 struct hns_roce_qp *hr_qp;
2125 struct hns_roce_wq *wq;
0425e3e6
YL		 2126 struct ib_qp_attr attr;
2127 int attr_mask;
93aa2187
WHX		 2128 int is_send;
2129 u16 wqe_ctr;
2130 u32 opcode;
2131 u32 status;
2132 int qpn;
0009c2db 2133 int ret;
93aa2187
WHX		 2134
2135 /* Find cqe according to consumer index */
2136 cqe = next_cqe_sw_v2(hr_cq);
2137 if (!cqe)
2138 return -EAGAIN;
2139
2140 ++hr_cq->cons_index;
2141 /* Memory barrier */
2142 rmb();
2143
2144 /* 0->SQ, 1->RQ */
2145 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2146
2147 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2148 V2_CQE_BYTE_16_LCL_QPN_S);
2149
2150 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2151 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2152 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2153 if (unlikely(!hr_qp)) {
2154 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
2155 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
2156 return -EINVAL;
2157 }
2158 *cur_qp = hr_qp;
2159 }
2160
2161 wc->qp = &(*cur_qp)->ibqp;
2162 wc->vendor_err = 0;
2163
2164 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
2165 V2_CQE_BYTE_4_STATUS_S);
2166 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
2167 case HNS_ROCE_CQE_V2_SUCCESS:
2168 wc->status = IB_WC_SUCCESS;
2169 break;
2170 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
2171 wc->status = IB_WC_LOC_LEN_ERR;
2172 break;
2173 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
2174 wc->status = IB_WC_LOC_QP_OP_ERR;
2175 break;
2176 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
2177 wc->status = IB_WC_LOC_PROT_ERR;
2178 break;
2179 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
2180 wc->status = IB_WC_WR_FLUSH_ERR;
2181 break;
2182 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
2183 wc->status = IB_WC_MW_BIND_ERR;
2184 break;
2185 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
2186 wc->status = IB_WC_BAD_RESP_ERR;
2187 break;
2188 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
2189 wc->status = IB_WC_LOC_ACCESS_ERR;
2190 break;
2191 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
2192 wc->status = IB_WC_REM_INV_REQ_ERR;
2193 break;
2194 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
2195 wc->status = IB_WC_REM_ACCESS_ERR;
2196 break;
2197 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
2198 wc->status = IB_WC_REM_OP_ERR;
2199 break;
2200 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
2201 wc->status = IB_WC_RETRY_EXC_ERR;
2202 break;
2203 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
2204 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2205 break;
2206 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
2207 wc->status = IB_WC_REM_ABORT_ERR;
2208 break;
2209 default:
2210 wc->status = IB_WC_GENERAL_ERR;
2211 break;
2212 }
2213
0425e3e6
YL		 2214 /* flush cqe if wc status is error, excluding flush error */
2215 if ((wc->status != IB_WC_SUCCESS) &&
2216 (wc->status != IB_WC_WR_FLUSH_ERR)) {
2217 attr_mask = IB_QP_STATE;
2218 attr.qp_state = IB_QPS_ERR;
2219 return hns_roce_v2_modify_qp(&(*cur_qp)->ibqp,
2220 &attr, attr_mask,
2221 (*cur_qp)->state, IB_QPS_ERR);
2222 }
2223
2224 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 2225 return 0;
2226
2227 if (is_send) {
2228 wc->wc_flags = 0;
2229 /* SQ corresponding to CQE */
2230 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2231 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
2232 case HNS_ROCE_SQ_OPCODE_SEND:
2233 wc->opcode = IB_WC_SEND;
2234 break;
2235 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
2236 wc->opcode = IB_WC_SEND;
2237 break;
2238 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
2239 wc->opcode = IB_WC_SEND;
2240 wc->wc_flags |= IB_WC_WITH_IMM;
2241 break;
2242 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
2243 wc->opcode = IB_WC_RDMA_READ;
2244 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2245 break;
2246 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
2247 wc->opcode = IB_WC_RDMA_WRITE;
2248 break;
2249 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
2250 wc->opcode = IB_WC_RDMA_WRITE;
2251 wc->wc_flags |= IB_WC_WITH_IMM;
2252 break;
2253 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
2254 wc->opcode = IB_WC_LOCAL_INV;
2255 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2256 break;
2257 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
2258 wc->opcode = IB_WC_COMP_SWAP;
2259 wc->byte_len = 8;
2260 break;
2261 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
2262 wc->opcode = IB_WC_FETCH_ADD;
2263 wc->byte_len = 8;
2264 break;
2265 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
2266 wc->opcode = IB_WC_MASKED_COMP_SWAP;
2267 wc->byte_len = 8;
2268 break;
2269 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
2270 wc->opcode = IB_WC_MASKED_FETCH_ADD;
2271 wc->byte_len = 8;
2272 break;
2273 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
2274 wc->opcode = IB_WC_REG_MR;
2275 break;
2276 case HNS_ROCE_SQ_OPCODE_BIND_MW:
2277 wc->opcode = IB_WC_REG_MR;
2278 break;
2279 default:
2280 wc->status = IB_WC_GENERAL_ERR;
2281 break;
2282 }
2283
2284 wq = &(*cur_qp)->sq;
2285 if ((*cur_qp)->sq_signal_bits) {
2286 /*
2287 * If sg_signal_bit is 1,
2288 * firstly tail pointer updated to wqe
2289 * which current cqe correspond to
2290 */
2291 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
2292 V2_CQE_BYTE_4_WQE_INDX_M,
2293 V2_CQE_BYTE_4_WQE_INDX_S);
2294 wq->tail += (wqe_ctr - (u16)wq->tail) &
2295 (wq->wqe_cnt - 1);
2296 }
2297
2298 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2299 ++wq->tail;
2300 } else {
2301 /* RQ correspond to CQE */
2302 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2303
2304 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2305 V2_CQE_BYTE_4_OPCODE_S);
2306 switch (opcode & 0x1f) {
2307 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
2308 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2309 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2310 wc->ex.imm_data =
2311 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2312 break;
2313 case HNS_ROCE_V2_OPCODE_SEND:
2314 wc->opcode = IB_WC_RECV;
2315 wc->wc_flags = 0;
2316 break;
2317 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
2318 wc->opcode = IB_WC_RECV;
2319 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2320 wc->ex.imm_data =
2321 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2322 break;
2323 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
2324 wc->opcode = IB_WC_RECV;
2325 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 2326 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 2327 break;
2328 default:
2329 wc->status = IB_WC_GENERAL_ERR;
2330 break;
2331 }
2332
0009c2db 2333 if ((wc->qp->qp_type == IB_QPT_RC ||
2334 wc->qp->qp_type == IB_QPT_UC) &&
2335 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
2336 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
2337 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
2338 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
2339 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
2340 if (ret)
2341 return -EAGAIN;
2342 }
2343
93aa2187
WHX		 2344 /* Update tail pointer, record wr_id */
2345 wq = &(*cur_qp)->rq;
2346 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2347 ++wq->tail;
2348
2349 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
2350 V2_CQE_BYTE_32_SL_S);
2351 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
2352 V2_CQE_BYTE_32_RMT_QPN_M,
2353 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 2354 wc->slid = 0;
93aa2187
WHX		 2355 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
2356 V2_CQE_BYTE_32_GRH_S) ?
2357 IB_WC_GRH : 0);
6c1f08b3 2358 wc->port_num = roce_get_field(cqe->byte_32,
2359 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
2360 wc->pkey_index = 0;
2eade675 2361 memcpy(wc->smac, cqe->smac, 4);
2362 wc->smac[4] = roce_get_field(cqe->byte_28,
2363 V2_CQE_BYTE_28_SMAC_4_M,
2364 V2_CQE_BYTE_28_SMAC_4_S);
2365 wc->smac[5] = roce_get_field(cqe->byte_28,
2366 V2_CQE_BYTE_28_SMAC_5_M,
2367 V2_CQE_BYTE_28_SMAC_5_S);
944e6409
LO		 2368 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
2369 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
2370 V2_CQE_BYTE_28_VID_M,
2371 V2_CQE_BYTE_28_VID_S);
2372 } else {
2373 wc->vlan_id = 0xffff;
2374 }
2375
2eade675 2376 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
2377 wc->network_hdr_type = roce_get_field(cqe->byte_28,
2378 V2_CQE_BYTE_28_PORT_TYPE_M,
2379 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 2380 }
2381
2382 return 0;
2383}
2384
2385static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
2386 struct ib_wc *wc)
2387{
2388 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2389 struct hns_roce_qp *cur_qp = NULL;
2390 unsigned long flags;
2391 int npolled;
2392
2393 spin_lock_irqsave(&hr_cq->lock, flags);
2394
2395 for (npolled = 0; npolled < num_entries; ++npolled) {
2396 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
2397 break;
2398 }
2399
2400 if (npolled) {
2401 /* Memory barrier */
2402 wmb();
2403 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2404 }
2405
2406 spin_unlock_irqrestore(&hr_cq->lock, flags);
2407
2408 return npolled;
2409}
2410
a81fba28
WHX		 2411static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
2412 struct hns_roce_hem_table *table, int obj,
2413 int step_idx)
2414{
2415 struct device *dev = hr_dev->dev;
2416 struct hns_roce_cmd_mailbox *mailbox;
2417 struct hns_roce_hem_iter iter;
2418 struct hns_roce_hem_mhop mhop;
2419 struct hns_roce_hem *hem;
2420 unsigned long mhop_obj = obj;
2421 int i, j, k;
2422 int ret = 0;
2423 u64 hem_idx = 0;
2424 u64 l1_idx = 0;
2425 u64 bt_ba = 0;
2426 u32 chunk_ba_num;
2427 u32 hop_num;
2428 u16 op = 0xff;
2429
2430 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2431 return 0;
2432
2433 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
2434 i = mhop.l0_idx;
2435 j = mhop.l1_idx;
2436 k = mhop.l2_idx;
2437 hop_num = mhop.hop_num;
2438 chunk_ba_num = mhop.bt_chunk_size / 8;
2439
2440 if (hop_num == 2) {
2441 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
2442 k;
2443 l1_idx = i * chunk_ba_num + j;
2444 } else if (hop_num == 1) {
2445 hem_idx = i * chunk_ba_num + j;
2446 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
2447 hem_idx = i;
2448 }
2449
2450 switch (table->type) {
2451 case HEM_TYPE_QPC:
2452 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
2453 break;
2454 case HEM_TYPE_MTPT:
2455 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
2456 break;
2457 case HEM_TYPE_CQC:
2458 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
2459 break;
2460 case HEM_TYPE_SRQC:
2461 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
2462 break;
2463 default:
2464 dev_warn(dev, "Table %d not to be written by mailbox!\n",
2465 table->type);
2466 return 0;
2467 }
2468 op += step_idx;
2469
2470 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2471 if (IS_ERR(mailbox))
2472 return PTR_ERR(mailbox);
2473
2474 if (check_whether_last_step(hop_num, step_idx)) {
2475 hem = table->hem[hem_idx];
2476 for (hns_roce_hem_first(hem, &iter);
2477 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
2478 bt_ba = hns_roce_hem_addr(&iter);
2479
2480 /* configure the ba, tag, and op */
2481 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
2482 obj, 0, op,
2483 HNS_ROCE_CMD_TIMEOUT_MSECS);
2484 }
2485 } else {
2486 if (step_idx == 0)
2487 bt_ba = table->bt_l0_dma_addr[i];
2488 else if (step_idx == 1 && hop_num == 2)
2489 bt_ba = table->bt_l1_dma_addr[l1_idx];
2490
2491 /* configure the ba, tag, and op */
2492 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
2493 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
2494 }
2495
2496 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2497 return ret;
2498}
2499
2500static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
2501 struct hns_roce_hem_table *table, int obj,
2502 int step_idx)
2503{
2504 struct device *dev = hr_dev->dev;
2505 struct hns_roce_cmd_mailbox *mailbox;
2506 int ret = 0;
2507 u16 op = 0xff;
2508
2509 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2510 return 0;
2511
2512 switch (table->type) {
2513 case HEM_TYPE_QPC:
2514 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
2515 break;
2516 case HEM_TYPE_MTPT:
2517 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
2518 break;
2519 case HEM_TYPE_CQC:
2520 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
2521 break;
2522 case HEM_TYPE_SRQC:
2523 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
2524 break;
2525 default:
2526 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
2527 table->type);
2528 return 0;
2529 }
2530 op += step_idx;
2531
2532 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2533 if (IS_ERR(mailbox))
2534 return PTR_ERR(mailbox);
2535
2536 /* configure the tag and op */
2537 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
2538 HNS_ROCE_CMD_TIMEOUT_MSECS);
2539
2540 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2541 return ret;
2542}
2543
926a01dc
WHX		 2544static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
2545 struct hns_roce_mtt *mtt,
2546 enum ib_qp_state cur_state,
2547 enum ib_qp_state new_state,
2548 struct hns_roce_v2_qp_context *context,
2549 struct hns_roce_qp *hr_qp)
2550{
2551 struct hns_roce_cmd_mailbox *mailbox;
2552 int ret;
2553
2554 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2555 if (IS_ERR(mailbox))
2556 return PTR_ERR(mailbox);
2557
2558 memcpy(mailbox->buf, context, sizeof(*context) * 2);
2559
2560 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2561 HNS_ROCE_CMD_MODIFY_QPC,
2562 HNS_ROCE_CMD_TIMEOUT_MSECS);
2563
2564 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2565
2566 return ret;
2567}
2568
ace1c541 2569static void set_access_flags(struct hns_roce_qp *hr_qp,
2570 struct hns_roce_v2_qp_context *context,
2571 struct hns_roce_v2_qp_context *qpc_mask,
2572 const struct ib_qp_attr *attr, int attr_mask)
2573{
2574 u8 dest_rd_atomic;
2575 u32 access_flags;
2576
c2799119 2577 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 2578 attr->max_dest_rd_atomic : hr_qp->resp_depth;
2579
c2799119 2580 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 2581 attr->qp_access_flags : hr_qp->atomic_rd_en;
2582
2583 if (!dest_rd_atomic)
2584 access_flags &= IB_ACCESS_REMOTE_WRITE;
2585
2586 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2587 !!(access_flags & IB_ACCESS_REMOTE_READ));
2588 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
2589
2590 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2591 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
2592 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
2593
2594 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2595 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
2596 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
2597}
2598
926a01dc
WHX		 2599static void modify_qp_reset_to_init(struct ib_qp *ibqp,
2600 const struct ib_qp_attr *attr,
0fa95a9a 2601 int attr_mask,
926a01dc
WHX		 2602 struct hns_roce_v2_qp_context *context,
2603 struct hns_roce_v2_qp_context *qpc_mask)
2604{
ecaaf1e2 2605 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 2606 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2607
2608 /*
2609 * In v2 engine, software pass context and context mask to hardware
2610 * when modifying qp. If software need modify some fields in context,
2611 * we should set all bits of the relevant fields in context mask to
2612 * 0 at the same time, else set them to 0x1.
2613 */
2614 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2615 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2616 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2617 V2_QPC_BYTE_4_TST_S, 0);
2618
0fa95a9a 2619 if (ibqp->qp_type == IB_QPT_GSI)
2620 roce_set_field(context->byte_4_sqpn_tst,
2621 V2_QPC_BYTE_4_SGE_SHIFT_M,
2622 V2_QPC_BYTE_4_SGE_SHIFT_S,
2623 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2624 else
2625 roce_set_field(context->byte_4_sqpn_tst,
2626 V2_QPC_BYTE_4_SGE_SHIFT_M,
2627 V2_QPC_BYTE_4_SGE_SHIFT_S,
2628 hr_qp->sq.max_gs > 2 ?
2629 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2630
926a01dc
WHX		 2631 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2632 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2633
2634 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2635 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2636 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2637 V2_QPC_BYTE_4_SQPN_S, 0);
2638
2639 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2640 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2641 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2642 V2_QPC_BYTE_16_PD_S, 0);
2643
2644 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2645 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
2646 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2647 V2_QPC_BYTE_20_RQWS_S, 0);
2648
2649 roce_set_field(context->byte_20_smac_sgid_idx,
2650 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2651 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2652 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2653 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2654
2655 roce_set_field(context->byte_20_smac_sgid_idx,
2656 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2657 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2658 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2659 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2660
2661 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 2662 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2663 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
2664 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2665 V2_QPC_BYTE_24_VLAN_ID_S, 0);
926a01dc
WHX		 2666
2667 /*
2668 * Set some fields in context to zero, Because the default values
2669 * of all fields in context are zero, we need not set them to 0 again.
2670 * but we should set the relevant fields of context mask to 0.
2671 */
2672 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
2673 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
2674 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
2675 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
2676
2362ccee
LO		 2677 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_TEMPID_M,
2678 V2_QPC_BYTE_60_TEMPID_S, 0);
2679
2680 roce_set_field(qpc_mask->byte_60_qpst_tempid,
2681 V2_QPC_BYTE_60_SCC_TOKEN_M, V2_QPC_BYTE_60_SCC_TOKEN_S,
2682 0);
2683 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2684 V2_QPC_BYTE_60_SQ_DB_DOING_S, 0);
2685 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2686 V2_QPC_BYTE_60_RQ_DB_DOING_S, 0);
926a01dc
WHX		 2687 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
2688 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
2689
0fa95a9a 2690 if (attr_mask & IB_QP_QKEY) {
2691 context->qkey_xrcd = attr->qkey;
2692 qpc_mask->qkey_xrcd = 0;
2693 hr_qp->qkey = attr->qkey;
2694 }
2695
e088a685
YL		 2696 if (hr_qp->rdb_en) {
2697 roce_set_bit(context->byte_68_rq_db,
2698 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
2699 roce_set_bit(qpc_mask->byte_68_rq_db,
2700 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0);
2701 }
2702
2703 roce_set_field(context->byte_68_rq_db,
2704 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2705 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
2706 ((u32)hr_qp->rdb.dma) >> 1);
2707 roce_set_field(qpc_mask->byte_68_rq_db,
2708 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2709 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0);
2710 context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
2711 qpc_mask->rq_db_record_addr = 0;
2712
ecaaf1e2 2713 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
2714 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 2715 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
2716
2717 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2718 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2719 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2720 V2_QPC_BYTE_80_RX_CQN_S, 0);
2721 if (ibqp->srq) {
2722 roce_set_field(context->byte_76_srqn_op_en,
2723 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2724 to_hr_srq(ibqp->srq)->srqn);
2725 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2726 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2727 roce_set_bit(context->byte_76_srqn_op_en,
2728 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2729 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2730 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2731 }
2732
2733 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2734 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2735 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
2736 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2737 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
2738 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
2739
2740 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
2741 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
2742
2743 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
2744 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
2745
2746 roce_set_field(qpc_mask->byte_104_rq_sge,
2747 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
2748 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
2749
2750 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2751 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
2752 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2753 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
2754 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
2755 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2756 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
2757
2758 qpc_mask->rq_rnr_timer = 0;
2759 qpc_mask->rx_msg_len = 0;
2760 qpc_mask->rx_rkey_pkt_info = 0;
2761 qpc_mask->rx_va = 0;
2762
2763 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2764 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2765 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2766 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2767
2362ccee
LO		 2768 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S,
2769 0);
926a01dc
WHX		 2770 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
2771 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
2772 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
2773 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
2774
2775 roce_set_field(qpc_mask->byte_144_raq,
2776 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
2777 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
926a01dc
WHX		 2778 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
2779 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
2780 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
2781
2782 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
2783 V2_QPC_BYTE_148_RQ_MSN_S, 0);
2784 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
2785 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
2786
2787 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2788 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2789 roce_set_field(qpc_mask->byte_152_raq,
2790 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
2791 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
2792
2793 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
2794 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
2795
2796 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2797 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
2798 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
2799 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2800 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
2801 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
2802
2362ccee
LO		 2803 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2804 V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S, 0);
2805 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2806 V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S, 0);
2807 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2808 V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S, 0);
926a01dc
WHX		 2809 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2810 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 2811 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2812 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 2813 roce_set_field(qpc_mask->byte_168_irrl_idx,
2814 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
2815 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
2816
2817 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2818 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
2819 roce_set_field(qpc_mask->byte_172_sq_psn,
2820 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2821 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
2822
2823 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
2824 0);
2825
2826 roce_set_field(qpc_mask->byte_176_msg_pktn,
2827 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
2828 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
2829 roce_set_field(qpc_mask->byte_176_msg_pktn,
2830 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
2831 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
2832
2833 roce_set_field(qpc_mask->byte_184_irrl_idx,
2834 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
2835 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
2836
2837 qpc_mask->cur_sge_offset = 0;
2838
2839 roce_set_field(qpc_mask->byte_192_ext_sge,
2840 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
2841 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
2842 roce_set_field(qpc_mask->byte_192_ext_sge,
2843 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
2844 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
2845
2846 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2847 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2848
2849 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
2850 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
2851 roce_set_field(qpc_mask->byte_200_sq_max,
2852 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
2853 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
2854
2855 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
2856 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
2857
2858 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2859 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2860
2861 qpc_mask->sq_timer = 0;
2862
2863 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2864 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2865 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2866 roce_set_field(qpc_mask->byte_232_irrl_sge,
2867 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2868 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2869
2362ccee
LO		 2870 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_SO_LP_VLD_S,
2871 0);
2872 roce_set_bit(qpc_mask->byte_232_irrl_sge,
2873 V2_QPC_BYTE_232_FENCE_LP_VLD_S, 0);
2874 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_IRRL_LP_VLD_S,
2875 0);
2876
926a01dc
WHX		 2877 qpc_mask->irrl_cur_sge_offset = 0;
2878
2879 roce_set_field(qpc_mask->byte_240_irrl_tail,
2880 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2881 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2882 roce_set_field(qpc_mask->byte_240_irrl_tail,
2883 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
2884 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
2885 roce_set_field(qpc_mask->byte_240_irrl_tail,
2886 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2887 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2888
2889 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
2890 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2891 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
2892 0);
2893 roce_set_field(qpc_mask->byte_248_ack_psn,
2894 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2895 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
2896 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
2897 0);
2898 roce_set_bit(qpc_mask->byte_248_ack_psn,
2899 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
2900 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
2901 0);
2902
2903 hr_qp->access_flags = attr->qp_access_flags;
2904 hr_qp->pkey_index = attr->pkey_index;
2905 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2906 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
2907 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2908 V2_QPC_BYTE_252_TX_CQN_S, 0);
2909
2910 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
2911 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
2912
2913 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2914 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
2915 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
2916 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2917 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
2918 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
2919}
2920
2921static void modify_qp_init_to_init(struct ib_qp *ibqp,
2922 const struct ib_qp_attr *attr, int attr_mask,
2923 struct hns_roce_v2_qp_context *context,
2924 struct hns_roce_v2_qp_context *qpc_mask)
2925{
2926 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2927
2928 /*
2929 * In v2 engine, software pass context and context mask to hardware
2930 * when modifying qp. If software need modify some fields in context,
2931 * we should set all bits of the relevant fields in context mask to
2932 * 0 at the same time, else set them to 0x1.
2933 */
2934 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2935 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2936 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2937 V2_QPC_BYTE_4_TST_S, 0);
2938
0fa95a9a 2939 if (ibqp->qp_type == IB_QPT_GSI)
2940 roce_set_field(context->byte_4_sqpn_tst,
2941 V2_QPC_BYTE_4_SGE_SHIFT_M,
2942 V2_QPC_BYTE_4_SGE_SHIFT_S,
2943 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2944 else
2945 roce_set_field(context->byte_4_sqpn_tst,
2946 V2_QPC_BYTE_4_SGE_SHIFT_M,
2947 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
2948 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2949
926a01dc
WHX		 2950 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2951 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2952
2953 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2954 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2955 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2956 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2957 0);
2958
2959 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2960 !!(attr->qp_access_flags &
2961 IB_ACCESS_REMOTE_WRITE));
2962 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2963 0);
2964
2965 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2966 !!(attr->qp_access_flags &
2967 IB_ACCESS_REMOTE_ATOMIC));
2968 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2969 0);
2970 } else {
2971 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2972 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
2973 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2974 0);
2975
2976 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2977 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
2978 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2979 0);
2980
2981 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2982 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
2983 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2984 0);
2985 }
2986
2987 roce_set_field(context->byte_20_smac_sgid_idx,
2988 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2989 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2990 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2991 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2992
2993 roce_set_field(context->byte_20_smac_sgid_idx,
2994 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2995 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2996 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2997 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2998
2999 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3000 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3001 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3002 V2_QPC_BYTE_16_PD_S, 0);
3003
3004 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3005 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3006 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3007 V2_QPC_BYTE_80_RX_CQN_S, 0);
3008
3009 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3010 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3011 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3012 V2_QPC_BYTE_252_TX_CQN_S, 0);
3013
3014 if (ibqp->srq) {
3015 roce_set_bit(context->byte_76_srqn_op_en,
3016 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3017 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3018 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3019 roce_set_field(context->byte_76_srqn_op_en,
3020 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3021 to_hr_srq(ibqp->srq)->srqn);
3022 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3023 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3024 }
3025
0fa95a9a 3026 if (attr_mask & IB_QP_QKEY) {
3027 context->qkey_xrcd = attr->qkey;
3028 qpc_mask->qkey_xrcd = 0;
3029 }
926a01dc
WHX		 3030
3031 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3032 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3033 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3034 V2_QPC_BYTE_4_SQPN_S, 0);
3035
b6dd9b34 3036 if (attr_mask & IB_QP_DEST_QPN) {
3037 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3038 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3039 roce_set_field(qpc_mask->byte_56_dqpn_err,
3040 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3041 }
926a01dc
WHX		 3042}
3043
3044static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3045 const struct ib_qp_attr *attr, int attr_mask,
3046 struct hns_roce_v2_qp_context *context,
3047 struct hns_roce_v2_qp_context *qpc_mask)
3048{
3049 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3050 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3051 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3052 struct device *dev = hr_dev->dev;
e92f2c18 3053 dma_addr_t dma_handle_3;
926a01dc
WHX		 3054 dma_addr_t dma_handle_2;
3055 dma_addr_t dma_handle;
3056 u32 page_size;
3057 u8 port_num;
e92f2c18 3058 u64 *mtts_3;
926a01dc
WHX		 3059 u64 *mtts_2;
3060 u64 *mtts;
3061 u8 *dmac;
3062 u8 *smac;
3063 int port;
3064
3065 /* Search qp buf's mtts */
3066 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3067 hr_qp->mtt.first_seg, &dma_handle);
3068 if (!mtts) {
3069 dev_err(dev, "qp buf pa find failed\n");
3070 return -EINVAL;
3071 }
3072
3073 /* Search IRRL's mtts */
3074 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3075 hr_qp->qpn, &dma_handle_2);
3076 if (!mtts_2) {
3077 dev_err(dev, "qp irrl_table find failed\n");
3078 return -EINVAL;
3079 }
3080
e92f2c18 3081 /* Search TRRL's mtts */
3082 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3083 hr_qp->qpn, &dma_handle_3);
3084 if (!mtts_3) {
3085 dev_err(dev, "qp trrl_table find failed\n");
3086 return -EINVAL;
3087 }
3088
734f3863 3089 if (attr_mask & IB_QP_ALT_PATH) {
926a01dc
WHX		 3090 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
3091 return -EINVAL;
3092 }
3093
3094 dmac = (u8 *)attr->ah_attr.roce.dmac;
3095 context->wqe_sge_ba = (u32)(dma_handle >> 3);
3096 qpc_mask->wqe_sge_ba = 0;
3097
3098 /*
3099 * In v2 engine, software pass context and context mask to hardware
3100 * when modifying qp. If software need modify some fields in context,
3101 * we should set all bits of the relevant fields in context mask to
3102 * 0 at the same time, else set them to 0x1.
3103 */
3104 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3105 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
3106 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3107 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3108
3109 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3110 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
3111 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3112 0 : hr_dev->caps.mtt_hop_num);
3113 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3114 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3115
3116 roce_set_field(context->byte_20_smac_sgid_idx,
3117 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3118 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
0fa95a9a 3119 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
3120 hr_dev->caps.mtt_hop_num : 0);
926a01dc
WHX		 3121 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3122 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3123 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3124
3125 roce_set_field(context->byte_20_smac_sgid_idx,
3126 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3127 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
3128 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3129 0 : hr_dev->caps.mtt_hop_num);
3130 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3131 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3132 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3133
3134 roce_set_field(context->byte_16_buf_ba_pg_sz,
3135 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3136 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
5e6e78db 3137 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3138 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3139 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3140 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3141
3142 roce_set_field(context->byte_16_buf_ba_pg_sz,
3143 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3144 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
5e6e78db 3145 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3146 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3147 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3148 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3149
3150 roce_set_field(context->byte_80_rnr_rx_cqn,
3151 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3152 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
3153 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
3154 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3155 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
3156
3157 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
3158 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
3159 >> PAGE_ADDR_SHIFT);
3160 qpc_mask->rq_cur_blk_addr = 0;
3161
3162 roce_set_field(context->byte_92_srq_info,
3163 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3164 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
3165 mtts[hr_qp->rq.offset / page_size]
3166 >> (32 + PAGE_ADDR_SHIFT));
3167 roce_set_field(qpc_mask->byte_92_srq_info,
3168 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3169 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3170
3171 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
3172 >> PAGE_ADDR_SHIFT);
3173 qpc_mask->rq_nxt_blk_addr = 0;
3174
3175 roce_set_field(context->byte_104_rq_sge,
3176 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3177 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
3178 mtts[hr_qp->rq.offset / page_size + 1]
3179 >> (32 + PAGE_ADDR_SHIFT));
3180 roce_set_field(qpc_mask->byte_104_rq_sge,
3181 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3182 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3183
3184 roce_set_field(context->byte_108_rx_reqepsn,
3185 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3186 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
3187 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3188 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3189 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
3190
e92f2c18 3191 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3192 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3193 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3194 V2_QPC_BYTE_132_TRRL_BA_S, 0);
3195 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
3196 qpc_mask->trrl_ba = 0;
3197 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3198 V2_QPC_BYTE_140_TRRL_BA_S,
3199 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3200 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3201 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3202
d5514246 3203 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 3204 qpc_mask->irrl_ba = 0;
3205 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3206 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3207 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3208 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3209 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3210
3211 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3212 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3213
3214 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3215 hr_qp->sq_signal_bits);
3216 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3217 0);
3218
3219 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3220
3221 smac = (u8 *)hr_dev->dev_addr[port];
3222 /* when dmac equals smac or loop_idc is 1, it should loopback */
3223 if (ether_addr_equal_unaligned(dmac, smac) ||
3224 hr_dev->loop_idc == 0x1) {
3225 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3226 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3227 }
3228
4f3f7a70 3229 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
3230 attr->max_dest_rd_atomic) {
3231 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3232 V2_QPC_BYTE_140_RR_MAX_S,
3233 fls(attr->max_dest_rd_atomic - 1));
3234 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3235 V2_QPC_BYTE_140_RR_MAX_S, 0);
3236 }
926a01dc 3237
b6dd9b34 3238 if (attr_mask & IB_QP_DEST_QPN) {
3239 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3240 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3241 roce_set_field(qpc_mask->byte_56_dqpn_err,
3242 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3243 }
926a01dc
WHX		 3244
3245 /* Configure GID index */
3246 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3247 roce_set_field(context->byte_20_smac_sgid_idx,
3248 V2_QPC_BYTE_20_SGID_IDX_M,
3249 V2_QPC_BYTE_20_SGID_IDX_S,
3250 hns_get_gid_index(hr_dev, port_num - 1,
3251 grh->sgid_index));
3252 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3253 V2_QPC_BYTE_20_SGID_IDX_M,
3254 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3255 memcpy(&(context->dmac), dmac, 4);
3256 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3257 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3258 qpc_mask->dmac = 0;
3259 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3260 V2_QPC_BYTE_52_DMAC_S, 0);
3261
3262 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3263 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
3264 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3265 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3266
0fa95a9a 3267 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3268 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3269 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3270 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3271 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3272 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3273
926a01dc
WHX		 3274 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3275 V2_QPC_BYTE_24_MTU_S, 0);
3276
926a01dc
WHX		 3277 roce_set_field(context->byte_84_rq_ci_pi,
3278 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3279 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3280 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3281 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3282 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3283
3284 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3285 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3286 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3287 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3288 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3289 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3290 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3291 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3292 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3293 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3294
3295 context->rq_rnr_timer = 0;
3296 qpc_mask->rq_rnr_timer = 0;
3297
3298 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3299 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
3300 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3301 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3302
3303 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3304 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3305 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3306 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3307
3308 roce_set_field(context->byte_168_irrl_idx,
3309 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3310 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3311 roce_set_field(qpc_mask->byte_168_irrl_idx,
3312 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3313 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3314
926a01dc
WHX		 3315 return 0;
3316}
3317
3318static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3319 const struct ib_qp_attr *attr, int attr_mask,
3320 struct hns_roce_v2_qp_context *context,
3321 struct hns_roce_v2_qp_context *qpc_mask)
3322{
3323 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3324 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3325 struct device *dev = hr_dev->dev;
3326 dma_addr_t dma_handle;
befb63b4 3327 u32 page_size;
926a01dc
WHX		 3328 u64 *mtts;
3329
3330 /* Search qp buf's mtts */
3331 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3332 hr_qp->mtt.first_seg, &dma_handle);
3333 if (!mtts) {
3334 dev_err(dev, "qp buf pa find failed\n");
3335 return -EINVAL;
3336 }
3337
734f3863 3338 /* Not support alternate path and path migration */
3339 if ((attr_mask & IB_QP_ALT_PATH) ||
3340 (attr_mask & IB_QP_PATH_MIG_STATE)) {
926a01dc
WHX		 3341 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
3342 return -EINVAL;
3343 }
3344
3345 /*
3346 * In v2 engine, software pass context and context mask to hardware
3347 * when modifying qp. If software need modify some fields in context,
3348 * we should set all bits of the relevant fields in context mask to
3349 * 0 at the same time, else set them to 0x1.
3350 */
926a01dc
WHX		 3351 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3352 roce_set_field(context->byte_168_irrl_idx,
3353 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3354 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3355 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3356 qpc_mask->sq_cur_blk_addr = 0;
3357 roce_set_field(qpc_mask->byte_168_irrl_idx,
3358 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3359 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3360
befb63b4 3361 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
0fa95a9a 3362 context->sq_cur_sge_blk_addr =
3363 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3364 ((u32)(mtts[hr_qp->sge.offset / page_size]
3365 >> PAGE_ADDR_SHIFT)) : 0;
3366 roce_set_field(context->byte_184_irrl_idx,
3367 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3368 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
0fa95a9a 3369 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3370 (mtts[hr_qp->sge.offset / page_size] >>
3371 (32 + PAGE_ADDR_SHIFT)) : 0);
3372 qpc_mask->sq_cur_sge_blk_addr = 0;
3373 roce_set_field(qpc_mask->byte_184_irrl_idx,
3374 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3375 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3376
926a01dc
WHX		 3377 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3378 roce_set_field(context->byte_232_irrl_sge,
3379 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3380 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3381 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3382 qpc_mask->rx_sq_cur_blk_addr = 0;
3383 roce_set_field(qpc_mask->byte_232_irrl_sge,
3384 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3385 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3386
3387 /*
3388 * Set some fields in context to zero, Because the default values
3389 * of all fields in context are zero, we need not set them to 0 again.
3390 * but we should set the relevant fields of context mask to 0.
3391 */
3392 roce_set_field(qpc_mask->byte_232_irrl_sge,
3393 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3394 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3395
3396 roce_set_field(qpc_mask->byte_240_irrl_tail,
3397 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3398 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3399
3400 roce_set_field(context->byte_244_rnr_rxack,
3401 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3402 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
3403 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3404 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3405 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
3406
3407 roce_set_field(qpc_mask->byte_248_ack_psn,
3408 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3409 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3410 roce_set_bit(qpc_mask->byte_248_ack_psn,
3411 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
3412 roce_set_field(qpc_mask->byte_248_ack_psn,
3413 V2_QPC_BYTE_248_IRRL_PSN_M,
3414 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3415
3416 roce_set_field(qpc_mask->byte_240_irrl_tail,
3417 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3418 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3419
3420 roce_set_field(context->byte_220_retry_psn_msn,
3421 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3422 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
3423 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3424 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3425 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
3426
3427 roce_set_field(context->byte_224_retry_msg,
3428 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3429 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
3430 roce_set_field(qpc_mask->byte_224_retry_msg,
3431 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3432 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
3433
3434 roce_set_field(context->byte_224_retry_msg,
3435 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3436 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
3437 roce_set_field(qpc_mask->byte_224_retry_msg,
3438 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3439 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
3440
3441 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3442 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3443 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3444
3445 roce_set_bit(qpc_mask->byte_248_ack_psn,
3446 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3447
3448 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3449 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3450
3451 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3452 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
3453 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3454 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
3455
3456 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3457 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
3458 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3459 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
3460
3461 roce_set_field(context->byte_244_rnr_rxack,
3462 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3463 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
3464 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3465 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3466 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
3467
3468 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3469 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
3470 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3471 V2_QPC_BYTE_244_RNR_CNT_S, 0);
3472
3473 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3474 V2_QPC_BYTE_212_LSN_S, 0x100);
3475 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3476 V2_QPC_BYTE_212_LSN_S, 0);
3477
28726461 3478 if (attr_mask & IB_QP_TIMEOUT) {
926a01dc
WHX		 3479 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3480 V2_QPC_BYTE_28_AT_S, attr->timeout);
28726461 3481 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3482 V2_QPC_BYTE_28_AT_S, 0);
3483 }
926a01dc 3484
926a01dc
WHX		 3485 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3486 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
3487 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3488 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
3489
3490 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3491 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3492 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3493 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
3494 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3495 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
3496
4f3f7a70 3497 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
3498 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
3499 V2_QPC_BYTE_208_SR_MAX_S,
3500 fls(attr->max_rd_atomic - 1));
3501 roce_set_field(qpc_mask->byte_208_irrl,
3502 V2_QPC_BYTE_208_SR_MAX_M,
3503 V2_QPC_BYTE_208_SR_MAX_S, 0);
3504 }
926a01dc
WHX		 3505 return 0;
3506}
3507
3508static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
3509 const struct ib_qp_attr *attr,
3510 int attr_mask, enum ib_qp_state cur_state,
3511 enum ib_qp_state new_state)
3512{
3513 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3514 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3515 struct hns_roce_v2_qp_context *context;
3516 struct hns_roce_v2_qp_context *qpc_mask;
3517 struct device *dev = hr_dev->dev;
3518 int ret = -EINVAL;
3519
6396bb22 3520 context = kcalloc(2, sizeof(*context), GFP_KERNEL);
926a01dc
WHX		 3521 if (!context)
3522 return -ENOMEM;
3523
3524 qpc_mask = context + 1;
3525 /*
3526 * In v2 engine, software pass context and context mask to hardware
3527 * when modifying qp. If software need modify some fields in context,
3528 * we should set all bits of the relevant fields in context mask to
3529 * 0 at the same time, else set them to 0x1.
3530 */
3531 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
3532 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0fa95a9a 3533 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
3534 qpc_mask);
926a01dc
WHX		 3535 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3536 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
3537 qpc_mask);
3538 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3539 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
3540 qpc_mask);
3541 if (ret)
3542 goto out;
3543 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3544 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
3545 qpc_mask);
3546 if (ret)
3547 goto out;
3548 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) ||
3549 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) ||
3550 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) ||
3551 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) ||
3552 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) ||
3553 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3554 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3555 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3556 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3557 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3558 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3559 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3560 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) ||
6e1a7094 3561 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) ||
3562 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) {
926a01dc
WHX		 3563 /* Nothing */
3564 ;
3565 } else {
3566 dev_err(dev, "Illegal state for QP!\n");
ac7cbf96 3567 ret = -EINVAL;
926a01dc
WHX		 3568 goto out;
3569 }
3570
0425e3e6
YL		 3571 /* When QP state is err, SQ and RQ WQE should be flushed */
3572 if (new_state == IB_QPS_ERR) {
3573 roce_set_field(context->byte_160_sq_ci_pi,
3574 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3575 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
3576 hr_qp->sq.head);
3577 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3578 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3579 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
3580 roce_set_field(context->byte_84_rq_ci_pi,
3581 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3582 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
3583 hr_qp->rq.head);
3584 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3585 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3586 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3587 }
3588
610b8967
LO		 3589 if (attr_mask & IB_QP_AV) {
3590 const struct ib_global_route *grh =
3591 rdma_ah_read_grh(&attr->ah_attr);
3592 const struct ib_gid_attr *gid_attr = NULL;
3593 u8 src_mac[ETH_ALEN];
3594 int is_roce_protocol;
3595 u16 vlan = 0xffff;
3596 u8 ib_port;
3597 u8 hr_port;
3598
3599 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num :
3600 hr_qp->port + 1;
3601 hr_port = ib_port - 1;
3602 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
3603 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
3604
3605 if (is_roce_protocol) {
3606 gid_attr = attr->ah_attr.grh.sgid_attr;
3607 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
3608 memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN);
3609 }
3610
caf3e406
LO		 3611 if (is_vlan_dev(gid_attr->ndev)) {
3612 roce_set_bit(context->byte_76_srqn_op_en,
3613 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
3614 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3615 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
3616 roce_set_bit(context->byte_168_irrl_idx,
3617 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
3618 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3619 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
3620 }
3621
c8e46f8d
LO		 3622 roce_set_field(context->byte_24_mtu_tc,
3623 V2_QPC_BYTE_24_VLAN_ID_M,
3624 V2_QPC_BYTE_24_VLAN_ID_S, vlan);
3625 roce_set_field(qpc_mask->byte_24_mtu_tc,
3626 V2_QPC_BYTE_24_VLAN_ID_M,
3627 V2_QPC_BYTE_24_VLAN_ID_S, 0);
3628
610b8967
LO		 3629 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
3630 dev_err(hr_dev->dev,
3631 "sgid_index(%u) too large. max is %d\n",
3632 grh->sgid_index,
3633 hr_dev->caps.gid_table_len[hr_port]);
3634 ret = -EINVAL;
3635 goto out;
3636 }
3637
3638 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
3639 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n");
3640 ret = -EINVAL;
3641 goto out;
3642 }
3643
3644 roce_set_field(context->byte_52_udpspn_dmac,
3645 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S,
3646 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3647 0 : 0x12b7);
3648
3649 roce_set_field(qpc_mask->byte_52_udpspn_dmac,
3650 V2_QPC_BYTE_52_UDPSPN_M,
3651 V2_QPC_BYTE_52_UDPSPN_S, 0);
3652
3653 roce_set_field(context->byte_20_smac_sgid_idx,
3654 V2_QPC_BYTE_20_SGID_IDX_M,
3655 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index);
3656
3657 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3658 V2_QPC_BYTE_20_SGID_IDX_M,
3659 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3660
3661 roce_set_field(context->byte_24_mtu_tc,
3662 V2_QPC_BYTE_24_HOP_LIMIT_M,
3663 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
3664 roce_set_field(qpc_mask->byte_24_mtu_tc,
3665 V2_QPC_BYTE_24_HOP_LIMIT_M,
3666 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
3667
157b52a0
LO		 3668 if (hr_dev->pci_dev->revision == 0x21 &&
3669 gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3670 roce_set_field(context->byte_24_mtu_tc,
3671 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
3672 grh->traffic_class >> 2);
3673 else
3674 roce_set_field(context->byte_24_mtu_tc,
3675 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
3676 grh->traffic_class);
610b8967
LO		 3677 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
3678 V2_QPC_BYTE_24_TC_S, 0);
3679 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3680 V2_QPC_BYTE_28_FL_S, grh->flow_label);
3681 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3682 V2_QPC_BYTE_28_FL_S, 0);
3683 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
3684 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
3685 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3686 V2_QPC_BYTE_28_SL_S,
3687 rdma_ah_get_sl(&attr->ah_attr));
3688 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3689 V2_QPC_BYTE_28_SL_S, 0);
3690 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3691 }
3692
ace1c541 3693 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3694 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
3695
926a01dc 3696 /* Every status migrate must change state */
2362ccee 3697 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 3698 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 3699 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 3700 V2_QPC_BYTE_60_QP_ST_S, 0);
3701
3702 /* SW pass context to HW */
3703 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
3704 context, hr_qp);
3705 if (ret) {
3706 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
3707 goto out;
3708 }
3709
3710 hr_qp->state = new_state;
3711
ace1c541 3712 if (attr_mask & IB_QP_ACCESS_FLAGS)
3713 hr_qp->atomic_rd_en = attr->qp_access_flags;
3714
926a01dc
WHX		 3715 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3716 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3717 if (attr_mask & IB_QP_PORT) {
3718 hr_qp->port = attr->port_num - 1;
3719 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3720 }
3721
3722 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3723 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3724 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3725 if (ibqp->send_cq != ibqp->recv_cq)
3726 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
3727 hr_qp->qpn, NULL);
3728
3729 hr_qp->rq.head = 0;
3730 hr_qp->rq.tail = 0;
3731 hr_qp->sq.head = 0;
3732 hr_qp->sq.tail = 0;
3733 hr_qp->sq_next_wqe = 0;
3734 hr_qp->next_sge = 0;
e088a685
YL		 3735 if (hr_qp->rq.wqe_cnt)
3736 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 3737 }
3738
3739out:
3740 kfree(context);
3741 return ret;
3742}
3743
3744static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
3745{
3746 switch (state) {
3747 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
3748 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
3749 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
3750 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
3751 case HNS_ROCE_QP_ST_SQ_DRAINING:
3752 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
3753 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
3754 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
3755 default: return -1;
3756 }
3757}
3758
3759static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
3760 struct hns_roce_qp *hr_qp,
3761 struct hns_roce_v2_qp_context *hr_context)
3762{
3763 struct hns_roce_cmd_mailbox *mailbox;
3764 int ret;
3765
3766 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3767 if (IS_ERR(mailbox))
3768 return PTR_ERR(mailbox);
3769
3770 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3771 HNS_ROCE_CMD_QUERY_QPC,
3772 HNS_ROCE_CMD_TIMEOUT_MSECS);
3773 if (ret) {
3774 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
3775 goto out;
3776 }
3777
3778 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3779
3780out:
3781 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3782 return ret;
3783}
3784
3785static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3786 int qp_attr_mask,
3787 struct ib_qp_init_attr *qp_init_attr)
3788{
3789 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3790 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3791 struct hns_roce_v2_qp_context *context;
3792 struct device *dev = hr_dev->dev;
3793 int tmp_qp_state;
3794 int state;
3795 int ret;
3796
3797 context = kzalloc(sizeof(*context), GFP_KERNEL);
3798 if (!context)
3799 return -ENOMEM;
3800
3801 memset(qp_attr, 0, sizeof(*qp_attr));
3802 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3803
3804 mutex_lock(&hr_qp->mutex);
3805
3806 if (hr_qp->state == IB_QPS_RESET) {
3807 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 3808 ret = 0;
926a01dc
WHX		 3809 goto done;
3810 }
3811
3812 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
3813 if (ret) {
3814 dev_err(dev, "query qpc error\n");
3815 ret = -EINVAL;
3816 goto out;
3817 }
3818
2362ccee 3819 state = roce_get_field(context->byte_60_qpst_tempid,
926a01dc
WHX		 3820 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
3821 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
3822 if (tmp_qp_state == -1) {
3823 dev_err(dev, "Illegal ib_qp_state\n");
3824 ret = -EINVAL;
3825 goto out;
3826 }
3827 hr_qp->state = (u8)tmp_qp_state;
3828 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3829 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
3830 V2_QPC_BYTE_24_MTU_M,
3831 V2_QPC_BYTE_24_MTU_S);
3832 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 3833 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 3834 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3835 qp_attr->qkey = V2_QKEY_VAL;
3836
3837 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
3838 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3839 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
3840 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
3841 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3842 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
3843 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
3844 V2_QPC_BYTE_56_DQPN_M,
3845 V2_QPC_BYTE_56_DQPN_S);
3846 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
3847 V2_QPC_BYTE_76_RRE_S)) << 2) |
3848 ((roce_get_bit(context->byte_76_srqn_op_en,
3849 V2_QPC_BYTE_76_RWE_S)) << 1) |
3850 ((roce_get_bit(context->byte_76_srqn_op_en,
3851 V2_QPC_BYTE_76_ATE_S)) << 3);
3852 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3853 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3854 struct ib_global_route *grh =
3855 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3856
3857 rdma_ah_set_sl(&qp_attr->ah_attr,
3858 roce_get_field(context->byte_28_at_fl,
3859 V2_QPC_BYTE_28_SL_M,
3860 V2_QPC_BYTE_28_SL_S));
3861 grh->flow_label = roce_get_field(context->byte_28_at_fl,
3862 V2_QPC_BYTE_28_FL_M,
3863 V2_QPC_BYTE_28_FL_S);
3864 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
3865 V2_QPC_BYTE_20_SGID_IDX_M,
3866 V2_QPC_BYTE_20_SGID_IDX_S);
3867 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
3868 V2_QPC_BYTE_24_HOP_LIMIT_M,
3869 V2_QPC_BYTE_24_HOP_LIMIT_S);
3870 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
3871 V2_QPC_BYTE_24_TC_M,
3872 V2_QPC_BYTE_24_TC_S);
3873
3874 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
3875 }
3876
3877 qp_attr->port_num = hr_qp->port + 1;
3878 qp_attr->sq_draining = 0;
3879 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
3880 V2_QPC_BYTE_208_SR_MAX_M,
3881 V2_QPC_BYTE_208_SR_MAX_S);
3882 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
3883 V2_QPC_BYTE_140_RR_MAX_M,
3884 V2_QPC_BYTE_140_RR_MAX_S);
3885 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
3886 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3887 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
3888 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
3889 V2_QPC_BYTE_28_AT_M,
3890 V2_QPC_BYTE_28_AT_S);
3891 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
3892 V2_QPC_BYTE_212_RETRY_CNT_M,
3893 V2_QPC_BYTE_212_RETRY_CNT_S);
3894 qp_attr->rnr_retry = context->rq_rnr_timer;
3895
3896done:
3897 qp_attr->cur_qp_state = qp_attr->qp_state;
3898 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3899 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3900
3901 if (!ibqp->uobject) {
3902 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3903 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3904 } else {
3905 qp_attr->cap.max_send_wr = 0;
3906 qp_attr->cap.max_send_sge = 0;
3907 }
3908
3909 qp_init_attr->cap = qp_attr->cap;
3910
3911out:
3912 mutex_unlock(&hr_qp->mutex);
3913 kfree(context);
3914 return ret;
3915}
3916
3917static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
3918 struct hns_roce_qp *hr_qp,
3919 int is_user)
3920{
3921 struct hns_roce_cq *send_cq, *recv_cq;
3922 struct device *dev = hr_dev->dev;
3923 int ret;
3924
3925 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
3926 /* Modify qp to reset before destroying qp */
3927 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
3928 hr_qp->state, IB_QPS_RESET);
3929 if (ret) {
3930 dev_err(dev, "modify QP %06lx to ERR failed.\n",
3931 hr_qp->qpn);
3932 return ret;
3933 }
3934 }
3935
3936 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3937 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3938
3939 hns_roce_lock_cqs(send_cq, recv_cq);
3940
3941 if (!is_user) {
3942 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3943 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3944 if (send_cq != recv_cq)
3945 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
3946 }
3947
3948 hns_roce_qp_remove(hr_dev, hr_qp);
3949
3950 hns_roce_unlock_cqs(send_cq, recv_cq);
3951
3952 hns_roce_qp_free(hr_dev, hr_qp);
3953
3954 /* Not special_QP, free their QPN */
3955 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
3956 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
3957 (hr_qp->ibqp.qp_type == IB_QPT_UD))
3958 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3959
3960 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3961
3962 if (is_user) {
0425e3e6
YL		 3963 if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1))
3964 hns_roce_db_unmap_user(
3965 to_hr_ucontext(hr_qp->ibqp.uobject->context),
3966 &hr_qp->sdb);
3967
e088a685
YL		 3968 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1))
3969 hns_roce_db_unmap_user(
3970 to_hr_ucontext(hr_qp->ibqp.uobject->context),
3971 &hr_qp->rdb);
926a01dc
WHX		 3972 ib_umem_release(hr_qp->umem);
3973 } else {
3974 kfree(hr_qp->sq.wrid);
3975 kfree(hr_qp->rq.wrid);
3976 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
472bc0fb
YL		 3977 if (hr_qp->rq.wqe_cnt)
3978 hns_roce_free_db(hr_dev, &hr_qp->rdb);
926a01dc
WHX		 3979 }
3980
0009c2db 3981 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
3982 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
3983 kfree(hr_qp->rq_inl_buf.wqe_list);
3984 }
3985
926a01dc
WHX		 3986 return 0;
3987}
3988
3989static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
3990{
3991 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3992 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3993 int ret;
3994
3995 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
3996 if (ret) {
3997 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
3998 return ret;
3999 }
4000
4001 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
4002 kfree(hr_to_hr_sqp(hr_qp));
4003 else
4004 kfree(hr_qp);
4005
4006 return 0;
4007}
4008
b156269d 4009static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
4010{
4011 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
4012 struct hns_roce_v2_cq_context *cq_context;
4013 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
4014 struct hns_roce_v2_cq_context *cqc_mask;
4015 struct hns_roce_cmd_mailbox *mailbox;
4016 int ret;
4017
4018 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4019 if (IS_ERR(mailbox))
4020 return PTR_ERR(mailbox);
4021
4022 cq_context = mailbox->buf;
4023 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
4024
4025 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
4026
4027 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4028 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4029 cq_count);
4030 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4031 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4032 0);
4033 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4034 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4035 cq_period);
4036 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4037 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4038 0);
4039
4040 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
4041 HNS_ROCE_CMD_MODIFY_CQC,
4042 HNS_ROCE_CMD_TIMEOUT_MSECS);
4043 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4044 if (ret)
4045 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
4046
4047 return ret;
4048}
4049
0425e3e6
YL		 4050static void hns_roce_set_qps_to_err(struct hns_roce_dev *hr_dev, u32 qpn)
4051{
4052 struct hns_roce_qp *hr_qp;
4053 struct ib_qp_attr attr;
4054 int attr_mask;
4055 int ret;
4056
4057 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
4058 if (!hr_qp) {
4059 dev_warn(hr_dev->dev, "no hr_qp can be found!\n");
4060 return;
4061 }
4062
4063 if (hr_qp->ibqp.uobject) {
4064 if (hr_qp->sdb_en == 1) {
4065 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
4066 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
4067 } else {
4068 dev_warn(hr_dev->dev, "flush cqe is unsupported in userspace!\n");
4069 return;
4070 }
4071 }
4072
4073 attr_mask = IB_QP_STATE;
4074 attr.qp_state = IB_QPS_ERR;
4075 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, attr_mask,
4076 hr_qp->state, IB_QPS_ERR);
4077 if (ret)
4078 dev_err(hr_dev->dev, "failed to modify qp %d to err state.\n",
4079 qpn);
4080}
4081
4082static void hns_roce_irq_work_handle(struct work_struct *work)
4083{
4084 struct hns_roce_work *irq_work =
4085 container_of(work, struct hns_roce_work, work);
b00a92c8 4086 struct device *dev = irq_work->hr_dev->dev;
0425e3e6 4087 u32 qpn = irq_work->qpn;
b00a92c8 4088 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4089
4090 switch (irq_work->event_type) {
b00a92c8 4091 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4092 dev_info(dev, "Path migrated succeeded.\n");
4093 break;
4094 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4095 dev_warn(dev, "Path migration failed.\n");
4096 break;
4097 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4098 dev_info(dev, "Communication established.\n");
4099 break;
4100 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4101 dev_warn(dev, "Send queue drained.\n");
4102 break;
0425e3e6 4103 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
b00a92c8 4104 dev_err(dev, "Local work queue catastrophic error.\n");
4105 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4106 switch (irq_work->sub_type) {
4107 case HNS_ROCE_LWQCE_QPC_ERROR:
4108 dev_err(dev, "QP %d, QPC error.\n", qpn);
4109 break;
4110 case HNS_ROCE_LWQCE_MTU_ERROR:
4111 dev_err(dev, "QP %d, MTU error.\n", qpn);
4112 break;
4113 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4114 dev_err(dev, "QP %d, WQE BA addr error.\n", qpn);
4115 break;
4116 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4117 dev_err(dev, "QP %d, WQE addr error.\n", qpn);
4118 break;
4119 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4120 dev_err(dev, "QP %d, WQE shift error.\n", qpn);
4121 break;
4122 default:
4123 dev_err(dev, "Unhandled sub_event type %d.\n",
4124 irq_work->sub_type);
4125 break;
4126 }
4127 break;
0425e3e6 4128 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
b00a92c8 4129 dev_err(dev, "Invalid request local work queue error.\n");
4130 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4131 break;
0425e3e6 4132 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4133 dev_err(dev, "Local access violation work queue error.\n");
0425e3e6 4134 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
b00a92c8 4135 switch (irq_work->sub_type) {
4136 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4137 dev_err(dev, "QP %d, R_key violation.\n", qpn);
4138 break;
4139 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4140 dev_err(dev, "QP %d, length error.\n", qpn);
4141 break;
4142 case HNS_ROCE_LAVWQE_VA_ERROR:
4143 dev_err(dev, "QP %d, VA error.\n", qpn);
4144 break;
4145 case HNS_ROCE_LAVWQE_PD_ERROR:
4146 dev_err(dev, "QP %d, PD error.\n", qpn);
4147 break;
4148 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4149 dev_err(dev, "QP %d, rw acc error.\n", qpn);
4150 break;
4151 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4152 dev_err(dev, "QP %d, key state error.\n", qpn);
4153 break;
4154 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4155 dev_err(dev, "QP %d, MR operation error.\n", qpn);
4156 break;
4157 default:
4158 dev_err(dev, "Unhandled sub_event type %d.\n",
4159 irq_work->sub_type);
4160 break;
4161 }
4162 break;
4163 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4164 dev_warn(dev, "SRQ limit reach.\n");
4165 break;
4166 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4167 dev_warn(dev, "SRQ last wqe reach.\n");
4168 break;
4169 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4170 dev_err(dev, "SRQ catas error.\n");
4171 break;
4172 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4173 dev_err(dev, "CQ 0x%x access err.\n", cqn);
4174 break;
4175 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4176 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4177 break;
4178 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4179 dev_warn(dev, "DB overflow.\n");
4180 break;
4181 case HNS_ROCE_EVENT_TYPE_FLR:
4182 dev_warn(dev, "Function level reset.\n");
0425e3e6
YL		 4183 break;
4184 default:
4185 break;
4186 }
4187
4188 kfree(irq_work);
4189}
4190
4191static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4192 struct hns_roce_eq *eq,
4193 u32 qpn, u32 cqn)
0425e3e6
YL		 4194{
4195 struct hns_roce_work *irq_work;
4196
4197 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4198 if (!irq_work)
4199 return;
4200
4201 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4202 irq_work->hr_dev = hr_dev;
4203 irq_work->qpn = qpn;
b00a92c8 4204 irq_work->cqn = cqn;
0425e3e6
YL		 4205 irq_work->event_type = eq->event_type;
4206 irq_work->sub_type = eq->sub_type;
4207 queue_work(hr_dev->irq_workq, &(irq_work->work));
4208}
4209
a5073d60
YL		 4210static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4211{
4212 u32 doorbell[2];
4213
4214 doorbell[0] = 0;
4215 doorbell[1] = 0;
4216
4217 if (eq->type_flag == HNS_ROCE_AEQ) {
4218 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4219 HNS_ROCE_V2_EQ_DB_CMD_S,
4220 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4221 HNS_ROCE_EQ_DB_CMD_AEQ :
4222 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4223 } else {
4224 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4225 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4226
4227 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4228 HNS_ROCE_V2_EQ_DB_CMD_S,
4229 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4230 HNS_ROCE_EQ_DB_CMD_CEQ :
4231 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4232 }
4233
4234 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4235 HNS_ROCE_V2_EQ_DB_PARA_S,
4236 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4237
4238 hns_roce_write64_k(doorbell, eq->doorbell);
a5073d60
YL		 4239}
4240
a5073d60
YL		 4241static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry)
4242{
4243 u32 buf_chk_sz;
4244 unsigned long off;
4245
4246 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4247 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4248
4249 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) +
4250 off % buf_chk_sz);
4251}
4252
4253static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry)
4254{
4255 u32 buf_chk_sz;
4256 unsigned long off;
4257
4258 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4259
4260 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4261
4262 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4263 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) +
4264 off % buf_chk_sz);
4265 else
4266 return (struct hns_roce_aeqe *)((u8 *)
4267 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz);
4268}
4269
4270static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4271{
4272 struct hns_roce_aeqe *aeqe;
4273
4274 if (!eq->hop_num)
4275 aeqe = get_aeqe_v2(eq, eq->cons_index);
4276 else
4277 aeqe = mhop_get_aeqe(eq, eq->cons_index);
4278
4279 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4280 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4281}
4282
4283static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4284 struct hns_roce_eq *eq)
4285{
4286 struct device *dev = hr_dev->dev;
4287 struct hns_roce_aeqe *aeqe;
4288 int aeqe_found = 0;
4289 int event_type;
0425e3e6
YL		 4290 int sub_type;
4291 u32 qpn;
4292 u32 cqn;
a5073d60
YL		 4293
4294 while ((aeqe = next_aeqe_sw_v2(eq))) {
4044a3f4
YL		 4295
4296 /* Make sure we read AEQ entry after we have checked the
4297 * ownership bit
4298 */
4299 dma_rmb();
a5073d60
YL		 4300
4301 event_type = roce_get_field(aeqe->asyn,
4302 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
4303 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 4304 sub_type = roce_get_field(aeqe->asyn,
4305 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
4306 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
4307 qpn = roce_get_field(aeqe->event.qp_event.qp,
4308 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4309 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4310 cqn = roce_get_field(aeqe->event.cq_event.cq,
4311 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4312 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 4313
4314 switch (event_type) {
4315 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 4316 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 4317 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4318 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4319 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4320 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4321 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4322 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 4323 break;
4324 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4325 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4326 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
a5073d60
YL		 4327 break;
4328 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4329 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 4330 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 4331 break;
4332 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 4333 break;
4334 case HNS_ROCE_EVENT_TYPE_MB:
4335 hns_roce_cmd_event(hr_dev,
4336 le16_to_cpu(aeqe->event.cmd.token),
4337 aeqe->event.cmd.status,
4338 le64_to_cpu(aeqe->event.cmd.out_param));
4339 break;
4340 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 4341 break;
4342 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 4343 break;
4344 default:
4345 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4346 event_type, eq->eqn, eq->cons_index);
4347 break;
4348 };
4349
0425e3e6
YL		 4350 eq->event_type = event_type;
4351 eq->sub_type = sub_type;
a5073d60
YL		 4352 ++eq->cons_index;
4353 aeqe_found = 1;
4354
4355 if (eq->cons_index > (2 * eq->entries - 1)) {
4356 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4357 eq->cons_index = 0;
4358 }
b00a92c8 4359 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
a5073d60
YL		 4360 }
4361
4362 set_eq_cons_index_v2(eq);
4363 return aeqe_found;
4364}
4365
4366static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry)
4367{
4368 u32 buf_chk_sz;
4369 unsigned long off;
4370
4371 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4372 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4373
4374 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) +
4375 off % buf_chk_sz);
4376}
4377
4378static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry)
4379{
4380 u32 buf_chk_sz;
4381 unsigned long off;
4382
4383 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4384
4385 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4386
4387 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4388 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) +
4389 off % buf_chk_sz);
4390 else
4391 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off /
4392 buf_chk_sz]) + off % buf_chk_sz);
4393}
4394
4395static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
4396{
4397 struct hns_roce_ceqe *ceqe;
4398
4399 if (!eq->hop_num)
4400 ceqe = get_ceqe_v2(eq, eq->cons_index);
4401 else
4402 ceqe = mhop_get_ceqe(eq, eq->cons_index);
4403
4404 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
4405 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4406}
4407
4408static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
4409 struct hns_roce_eq *eq)
4410{
4411 struct device *dev = hr_dev->dev;
4412 struct hns_roce_ceqe *ceqe;
4413 int ceqe_found = 0;
4414 u32 cqn;
4415
4416 while ((ceqe = next_ceqe_sw_v2(eq))) {
4417
4044a3f4
YL		 4418 /* Make sure we read CEQ entry after we have checked the
4419 * ownership bit
4420 */
4421 dma_rmb();
4422
a5073d60
YL		 4423 cqn = roce_get_field(ceqe->comp,
4424 HNS_ROCE_V2_CEQE_COMP_CQN_M,
4425 HNS_ROCE_V2_CEQE_COMP_CQN_S);
4426
4427 hns_roce_cq_completion(hr_dev, cqn);
4428
4429 ++eq->cons_index;
4430 ceqe_found = 1;
4431
4432 if (eq->cons_index > (2 * eq->entries - 1)) {
4433 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4434 eq->cons_index = 0;
4435 }
4436 }
4437
4438 set_eq_cons_index_v2(eq);
4439
4440 return ceqe_found;
4441}
4442
4443static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
4444{
4445 struct hns_roce_eq *eq = eq_ptr;
4446 struct hns_roce_dev *hr_dev = eq->hr_dev;
4447 int int_work = 0;
4448
4449 if (eq->type_flag == HNS_ROCE_CEQ)
4450 /* Completion event interrupt */
4451 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
4452 else
4453 /* Asychronous event interrupt */
4454 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
4455
4456 return IRQ_RETVAL(int_work);
4457}
4458
4459static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
4460{
4461 struct hns_roce_dev *hr_dev = dev_id;
4462 struct device *dev = hr_dev->dev;
4463 int int_work = 0;
4464 u32 int_st;
4465 u32 int_en;
4466
4467 /* Abnormal interrupt */
4468 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
4469 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
4470
4471 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
4472 dev_err(dev, "AEQ overflow!\n");
4473
4474 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
4475 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4476
a5073d60
YL		 4477 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4478 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4479
4480 int_work = 1;
4481 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
4482 dev_err(dev, "BUS ERR!\n");
4483
4484 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
4485 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4486
a5073d60
YL		 4487 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4488 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4489
4490 int_work = 1;
4491 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
4492 dev_err(dev, "OTHER ERR!\n");
4493
4494 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
4495 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4496
a5073d60
YL		 4497 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4498 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4499
4500 int_work = 1;
4501 } else
4502 dev_err(dev, "There is no abnormal irq found!\n");
4503
4504 return IRQ_RETVAL(int_work);
4505}
4506
4507static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
4508 int eq_num, int enable_flag)
4509{
4510 int i;
4511
4512 if (enable_flag == EQ_ENABLE) {
4513 for (i = 0; i < eq_num; i++)
4514 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4515 i * EQ_REG_OFFSET,
4516 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
4517
4518 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4519 HNS_ROCE_V2_VF_ABN_INT_EN_M);
4520 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4521 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
4522 } else {
4523 for (i = 0; i < eq_num; i++)
4524 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4525 i * EQ_REG_OFFSET,
4526 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
4527
4528 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4529 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
4530 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4531 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
4532 }
4533}
4534
4535static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
4536{
4537 struct device *dev = hr_dev->dev;
4538 int ret;
4539
4540 if (eqn < hr_dev->caps.num_comp_vectors)
4541 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4542 0, HNS_ROCE_CMD_DESTROY_CEQC,
4543 HNS_ROCE_CMD_TIMEOUT_MSECS);
4544 else
4545 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4546 0, HNS_ROCE_CMD_DESTROY_AEQC,
4547 HNS_ROCE_CMD_TIMEOUT_MSECS);
4548 if (ret)
4549 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
4550}
4551
4552static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev,
4553 struct hns_roce_eq *eq)
4554{
4555 struct device *dev = hr_dev->dev;
4556 u64 idx;
4557 u64 size;
4558 u32 buf_chk_sz;
4559 u32 bt_chk_sz;
4560 u32 mhop_num;
4561 int eqe_alloc;
a5073d60
YL		 4562 int i = 0;
4563 int j = 0;
4564
4565 mhop_num = hr_dev->caps.eqe_hop_num;
4566 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4567 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
a5073d60
YL		 4568
4569 /* hop_num = 0 */
4570 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4571 dma_free_coherent(dev, (unsigned int)(eq->entries *
4572 eq->eqe_size), eq->bt_l0, eq->l0_dma);
4573 return;
4574 }
4575
4576 /* hop_num = 1 or hop = 2 */
4577 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4578 if (mhop_num == 1) {
4579 for (i = 0; i < eq->l0_last_num; i++) {
4580 if (i == eq->l0_last_num - 1) {
4581 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4582 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4583 dma_free_coherent(dev, size, eq->buf[i],
4584 eq->buf_dma[i]);
4585 break;
4586 }
4587 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4588 eq->buf_dma[i]);
4589 }
4590 } else if (mhop_num == 2) {
4591 for (i = 0; i < eq->l0_last_num; i++) {
4592 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4593 eq->l1_dma[i]);
4594
4595 for (j = 0; j < bt_chk_sz / 8; j++) {
4596 idx = i * (bt_chk_sz / 8) + j;
4597 if ((i == eq->l0_last_num - 1)
4598 && j == eq->l1_last_num - 1) {
4599 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4600 * idx;
4601 size = (eq->entries - eqe_alloc)
4602 * eq->eqe_size;
4603 dma_free_coherent(dev, size,
4604 eq->buf[idx],
4605 eq->buf_dma[idx]);
4606 break;
4607 }
4608 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4609 eq->buf_dma[idx]);
4610 }
4611 }
4612 }
4613 kfree(eq->buf_dma);
4614 kfree(eq->buf);
4615 kfree(eq->l1_dma);
4616 kfree(eq->bt_l1);
4617 eq->buf_dma = NULL;
4618 eq->buf = NULL;
4619 eq->l1_dma = NULL;
4620 eq->bt_l1 = NULL;
4621}
4622
4623static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev,
4624 struct hns_roce_eq *eq)
4625{
4626 u32 buf_chk_sz;
4627
4628 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4629
4630 if (hr_dev->caps.eqe_hop_num) {
4631 hns_roce_mhop_free_eq(hr_dev, eq);
4632 return;
4633 }
4634
4635 if (eq->buf_list)
4636 dma_free_coherent(hr_dev->dev, buf_chk_sz,
4637 eq->buf_list->buf, eq->buf_list->map);
4638}
4639
4640static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
4641 struct hns_roce_eq *eq,
4642 void *mb_buf)
4643{
4644 struct hns_roce_eq_context *eqc;
4645
4646 eqc = mb_buf;
4647 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
4648
4649 /* init eqc */
4650 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
4651 eq->hop_num = hr_dev->caps.eqe_hop_num;
4652 eq->cons_index = 0;
4653 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
4654 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
4655 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
4656 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz;
4657 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz;
4658 eq->shift = ilog2((unsigned int)eq->entries);
4659
4660 if (!eq->hop_num)
4661 eq->eqe_ba = eq->buf_list->map;
4662 else
4663 eq->eqe_ba = eq->l0_dma;
4664
4665 /* set eqc state */
4666 roce_set_field(eqc->byte_4,
4667 HNS_ROCE_EQC_EQ_ST_M,
4668 HNS_ROCE_EQC_EQ_ST_S,
4669 HNS_ROCE_V2_EQ_STATE_VALID);
4670
4671 /* set eqe hop num */
4672 roce_set_field(eqc->byte_4,
4673 HNS_ROCE_EQC_HOP_NUM_M,
4674 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
4675
4676 /* set eqc over_ignore */
4677 roce_set_field(eqc->byte_4,
4678 HNS_ROCE_EQC_OVER_IGNORE_M,
4679 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
4680
4681 /* set eqc coalesce */
4682 roce_set_field(eqc->byte_4,
4683 HNS_ROCE_EQC_COALESCE_M,
4684 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
4685
4686 /* set eqc arm_state */
4687 roce_set_field(eqc->byte_4,
4688 HNS_ROCE_EQC_ARM_ST_M,
4689 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
4690
4691 /* set eqn */
4692 roce_set_field(eqc->byte_4,
4693 HNS_ROCE_EQC_EQN_M,
4694 HNS_ROCE_EQC_EQN_S, eq->eqn);
4695
4696 /* set eqe_cnt */
4697 roce_set_field(eqc->byte_4,
4698 HNS_ROCE_EQC_EQE_CNT_M,
4699 HNS_ROCE_EQC_EQE_CNT_S,
4700 HNS_ROCE_EQ_INIT_EQE_CNT);
4701
4702 /* set eqe_ba_pg_sz */
4703 roce_set_field(eqc->byte_8,
4704 HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db
YL		 4705 HNS_ROCE_EQC_BA_PG_SZ_S,
4706 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4707
4708 /* set eqe_buf_pg_sz */
4709 roce_set_field(eqc->byte_8,
4710 HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db
YL		 4711 HNS_ROCE_EQC_BUF_PG_SZ_S,
4712 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4713
4714 /* set eq_producer_idx */
4715 roce_set_field(eqc->byte_8,
4716 HNS_ROCE_EQC_PROD_INDX_M,
4717 HNS_ROCE_EQC_PROD_INDX_S,
4718 HNS_ROCE_EQ_INIT_PROD_IDX);
4719
4720 /* set eq_max_cnt */
4721 roce_set_field(eqc->byte_12,
4722 HNS_ROCE_EQC_MAX_CNT_M,
4723 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
4724
4725 /* set eq_period */
4726 roce_set_field(eqc->byte_12,
4727 HNS_ROCE_EQC_PERIOD_M,
4728 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
4729
4730 /* set eqe_report_timer */
4731 roce_set_field(eqc->eqe_report_timer,
4732 HNS_ROCE_EQC_REPORT_TIMER_M,
4733 HNS_ROCE_EQC_REPORT_TIMER_S,
4734 HNS_ROCE_EQ_INIT_REPORT_TIMER);
4735
4736 /* set eqe_ba [34:3] */
4737 roce_set_field(eqc->eqe_ba0,
4738 HNS_ROCE_EQC_EQE_BA_L_M,
4739 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3);
4740
4741 /* set eqe_ba [64:35] */
4742 roce_set_field(eqc->eqe_ba1,
4743 HNS_ROCE_EQC_EQE_BA_H_M,
4744 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35);
4745
4746 /* set eq shift */
4747 roce_set_field(eqc->byte_28,
4748 HNS_ROCE_EQC_SHIFT_M,
4749 HNS_ROCE_EQC_SHIFT_S, eq->shift);
4750
4751 /* set eq MSI_IDX */
4752 roce_set_field(eqc->byte_28,
4753 HNS_ROCE_EQC_MSI_INDX_M,
4754 HNS_ROCE_EQC_MSI_INDX_S,
4755 HNS_ROCE_EQ_INIT_MSI_IDX);
4756
4757 /* set cur_eqe_ba [27:12] */
4758 roce_set_field(eqc->byte_28,
4759 HNS_ROCE_EQC_CUR_EQE_BA_L_M,
4760 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12);
4761
4762 /* set cur_eqe_ba [59:28] */
4763 roce_set_field(eqc->byte_32,
4764 HNS_ROCE_EQC_CUR_EQE_BA_M_M,
4765 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28);
4766
4767 /* set cur_eqe_ba [63:60] */
4768 roce_set_field(eqc->byte_36,
4769 HNS_ROCE_EQC_CUR_EQE_BA_H_M,
4770 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60);
4771
4772 /* set eq consumer idx */
4773 roce_set_field(eqc->byte_36,
4774 HNS_ROCE_EQC_CONS_INDX_M,
4775 HNS_ROCE_EQC_CONS_INDX_S,
4776 HNS_ROCE_EQ_INIT_CONS_IDX);
4777
4778 /* set nex_eqe_ba[43:12] */
4779 roce_set_field(eqc->nxt_eqe_ba0,
4780 HNS_ROCE_EQC_NXT_EQE_BA_L_M,
4781 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12);
4782
4783 /* set nex_eqe_ba[63:44] */
4784 roce_set_field(eqc->nxt_eqe_ba1,
4785 HNS_ROCE_EQC_NXT_EQE_BA_H_M,
4786 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44);
4787}
4788
4789static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev,
4790 struct hns_roce_eq *eq)
4791{
4792 struct device *dev = hr_dev->dev;
4793 int eq_alloc_done = 0;
4794 int eq_buf_cnt = 0;
4795 int eqe_alloc;
4796 u32 buf_chk_sz;
4797 u32 bt_chk_sz;
4798 u32 mhop_num;
4799 u64 size;
4800 u64 idx;
4801 int ba_num;
4802 int bt_num;
4803 int record_i;
4804 int record_j;
4805 int i = 0;
4806 int j = 0;
4807
4808 mhop_num = hr_dev->caps.eqe_hop_num;
4809 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4810 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
4811
4812 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1)
4813 / buf_chk_sz;
4814 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8);
4815
4816 /* hop_num = 0 */
4817 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4818 if (eq->entries > buf_chk_sz / eq->eqe_size) {
4819 dev_err(dev, "eq entries %d is larger than buf_pg_sz!",
4820 eq->entries);
4821 return -EINVAL;
4822 }
4823 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size,
4824 &(eq->l0_dma), GFP_KERNEL);
4825 if (!eq->bt_l0)
4826 return -ENOMEM;
4827
4828 eq->cur_eqe_ba = eq->l0_dma;
4829 eq->nxt_eqe_ba = 0;
4830
4831 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size);
4832
4833 return 0;
4834 }
4835
4836 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL);
4837 if (!eq->buf_dma)
4838 return -ENOMEM;
4839 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL);
4840 if (!eq->buf)
4841 goto err_kcalloc_buf;
4842
4843 if (mhop_num == 2) {
4844 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL);
4845 if (!eq->l1_dma)
4846 goto err_kcalloc_l1_dma;
4847
4848 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL);
4849 if (!eq->bt_l1)
4850 goto err_kcalloc_bt_l1;
4851 }
4852
4853 /* alloc L0 BT */
4854 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL);
4855 if (!eq->bt_l0)
4856 goto err_dma_alloc_l0;
4857
4858 if (mhop_num == 1) {
4859 if (ba_num > (bt_chk_sz / 8))
4860 dev_err(dev, "ba_num %d is too large for 1 hop\n",
4861 ba_num);
4862
4863 /* alloc buf */
4864 for (i = 0; i < bt_chk_sz / 8; i++) {
4865 if (eq_buf_cnt + 1 < ba_num) {
4866 size = buf_chk_sz;
4867 } else {
4868 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4869 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4870 }
4871 eq->buf[i] = dma_alloc_coherent(dev, size,
4872 &(eq->buf_dma[i]),
4873 GFP_KERNEL);
4874 if (!eq->buf[i])
4875 goto err_dma_alloc_buf;
4876
4877 memset(eq->buf[i], 0, size);
4878 *(eq->bt_l0 + i) = eq->buf_dma[i];
4879
4880 eq_buf_cnt++;
4881 if (eq_buf_cnt >= ba_num)
4882 break;
4883 }
4884 eq->cur_eqe_ba = eq->buf_dma[0];
4885 eq->nxt_eqe_ba = eq->buf_dma[1];
4886
4887 } else if (mhop_num == 2) {
4888 /* alloc L1 BT and buf */
4889 for (i = 0; i < bt_chk_sz / 8; i++) {
4890 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz,
4891 &(eq->l1_dma[i]),
4892 GFP_KERNEL);
4893 if (!eq->bt_l1[i])
4894 goto err_dma_alloc_l1;
4895 *(eq->bt_l0 + i) = eq->l1_dma[i];
4896
4897 for (j = 0; j < bt_chk_sz / 8; j++) {
4898 idx = i * bt_chk_sz / 8 + j;
4899 if (eq_buf_cnt + 1 < ba_num) {
4900 size = buf_chk_sz;
4901 } else {
4902 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4903 * idx;
4904 size = (eq->entries - eqe_alloc)
4905 * eq->eqe_size;
4906 }
4907 eq->buf[idx] = dma_alloc_coherent(dev, size,
4908 &(eq->buf_dma[idx]),
4909 GFP_KERNEL);
4910 if (!eq->buf[idx])
4911 goto err_dma_alloc_buf;
4912
4913 memset(eq->buf[idx], 0, size);
4914 *(eq->bt_l1[i] + j) = eq->buf_dma[idx];
4915
4916 eq_buf_cnt++;
4917 if (eq_buf_cnt >= ba_num) {
4918 eq_alloc_done = 1;
4919 break;
4920 }
4921 }
4922
4923 if (eq_alloc_done)
4924 break;
4925 }
4926 eq->cur_eqe_ba = eq->buf_dma[0];
4927 eq->nxt_eqe_ba = eq->buf_dma[1];
4928 }
4929
4930 eq->l0_last_num = i + 1;
4931 if (mhop_num == 2)
4932 eq->l1_last_num = j + 1;
4933
4934 return 0;
4935
4936err_dma_alloc_l1:
4937 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4938 eq->bt_l0 = NULL;
4939 eq->l0_dma = 0;
4940 for (i -= 1; i >= 0; i--) {
4941 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4942 eq->l1_dma[i]);
4943
4944 for (j = 0; j < bt_chk_sz / 8; j++) {
4945 idx = i * bt_chk_sz / 8 + j;
4946 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4947 eq->buf_dma[idx]);
4948 }
4949 }
4950 goto err_dma_alloc_l0;
4951
4952err_dma_alloc_buf:
4953 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4954 eq->bt_l0 = NULL;
4955 eq->l0_dma = 0;
4956
4957 if (mhop_num == 1)
38759d61 4958 for (i -= 1; i >= 0; i--)
a5073d60
YL		 4959 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4960 eq->buf_dma[i]);
4961 else if (mhop_num == 2) {
4962 record_i = i;
4963 record_j = j;
4964 for (; i >= 0; i--) {
4965 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4966 eq->l1_dma[i]);
4967
4968 for (j = 0; j < bt_chk_sz / 8; j++) {
4969 if (i == record_i && j >= record_j)
4970 break;
4971
4972 idx = i * bt_chk_sz / 8 + j;
4973 dma_free_coherent(dev, buf_chk_sz,
4974 eq->buf[idx],
4975 eq->buf_dma[idx]);
4976 }
4977 }
4978 }
4979
4980err_dma_alloc_l0:
4981 kfree(eq->bt_l1);
4982 eq->bt_l1 = NULL;
4983
4984err_kcalloc_bt_l1:
4985 kfree(eq->l1_dma);
4986 eq->l1_dma = NULL;
4987
4988err_kcalloc_l1_dma:
4989 kfree(eq->buf);
4990 eq->buf = NULL;
4991
4992err_kcalloc_buf:
4993 kfree(eq->buf_dma);
4994 eq->buf_dma = NULL;
4995
4996 return -ENOMEM;
4997}
4998
4999static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5000 struct hns_roce_eq *eq,
5001 unsigned int eq_cmd)
5002{
5003 struct device *dev = hr_dev->dev;
5004 struct hns_roce_cmd_mailbox *mailbox;
5005 u32 buf_chk_sz = 0;
5006 int ret;
5007
5008 /* Allocate mailbox memory */
5009 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5010 if (IS_ERR(mailbox))
5011 return PTR_ERR(mailbox);
5012
5013 if (!hr_dev->caps.eqe_hop_num) {
5014 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5015
5016 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list),
5017 GFP_KERNEL);
5018 if (!eq->buf_list) {
5019 ret = -ENOMEM;
5020 goto free_cmd_mbox;
5021 }
5022
5023 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz,
5024 &(eq->buf_list->map),
5025 GFP_KERNEL);
5026 if (!eq->buf_list->buf) {
5027 ret = -ENOMEM;
5028 goto err_alloc_buf;
5029 }
5030
5031 memset(eq->buf_list->buf, 0, buf_chk_sz);
5032 } else {
5033 ret = hns_roce_mhop_alloc_eq(hr_dev, eq);
5034 if (ret) {
5035 ret = -ENOMEM;
5036 goto free_cmd_mbox;
5037 }
5038 }
5039
5040 hns_roce_config_eqc(hr_dev, eq, mailbox->buf);
5041
5042 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5043 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5044 if (ret) {
ab178849 5045 dev_err(dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5046 goto err_cmd_mbox;
5047 }
5048
5049 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5050
5051 return 0;
5052
5053err_cmd_mbox:
5054 if (!hr_dev->caps.eqe_hop_num)
5055 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf,
5056 eq->buf_list->map);
5057 else {
5058 hns_roce_mhop_free_eq(hr_dev, eq);
5059 goto free_cmd_mbox;
5060 }
5061
5062err_alloc_buf:
5063 kfree(eq->buf_list);
5064
5065free_cmd_mbox:
5066 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5067
5068 return ret;
5069}
5070
5071static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5072{
5073 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5074 struct device *dev = hr_dev->dev;
5075 struct hns_roce_eq *eq;
5076 unsigned int eq_cmd;
5077 int irq_num;
5078 int eq_num;
5079 int other_num;
5080 int comp_num;
5081 int aeq_num;
5082 int i, j, k;
5083 int ret;
5084
5085 other_num = hr_dev->caps.num_other_vectors;
5086 comp_num = hr_dev->caps.num_comp_vectors;
5087 aeq_num = hr_dev->caps.num_aeq_vectors;
5088
5089 eq_num = comp_num + aeq_num;
5090 irq_num = eq_num + other_num;
5091
5092 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5093 if (!eq_table->eq)
5094 return -ENOMEM;
5095
5096 for (i = 0; i < irq_num; i++) {
5097 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5098 GFP_KERNEL);
5099 if (!hr_dev->irq_names[i]) {
5100 ret = -ENOMEM;
5101 goto err_failed_kzalloc;
5102 }
5103 }
5104
5105 /* create eq */
5106 for (j = 0; j < eq_num; j++) {
5107 eq = &eq_table->eq[j];
5108 eq->hr_dev = hr_dev;
5109 eq->eqn = j;
5110 if (j < comp_num) {
5111 /* CEQ */
5112 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5113 eq->type_flag = HNS_ROCE_CEQ;
5114 eq->entries = hr_dev->caps.ceqe_depth;
5115 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
5116 eq->irq = hr_dev->irq[j + other_num + aeq_num];
5117 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5118 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5119 } else {
5120 /* AEQ */
5121 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5122 eq->type_flag = HNS_ROCE_AEQ;
5123 eq->entries = hr_dev->caps.aeqe_depth;
5124 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
5125 eq->irq = hr_dev->irq[j - comp_num + other_num];
5126 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5127 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5128 }
5129
5130 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5131 if (ret) {
5132 dev_err(dev, "eq create failed.\n");
5133 goto err_create_eq_fail;
5134 }
5135 }
5136
5137 /* enable irq */
5138 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5139
5140 /* irq contains: abnormal + AEQ + CEQ*/
5141 for (k = 0; k < irq_num; k++)
5142 if (k < other_num)
5143 snprintf((char *)hr_dev->irq_names[k],
5144 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k);
5145 else if (k < (other_num + aeq_num))
5146 snprintf((char *)hr_dev->irq_names[k],
5147 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d",
5148 k - other_num);
5149 else
5150 snprintf((char *)hr_dev->irq_names[k],
5151 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d",
5152 k - other_num - aeq_num);
5153
5154 for (k = 0; k < irq_num; k++) {
5155 if (k < other_num)
5156 ret = request_irq(hr_dev->irq[k],
5157 hns_roce_v2_msix_interrupt_abn,
5158 0, hr_dev->irq_names[k], hr_dev);
5159
5160 else if (k < (other_num + comp_num))
5161 ret = request_irq(eq_table->eq[k - other_num].irq,
5162 hns_roce_v2_msix_interrupt_eq,
5163 0, hr_dev->irq_names[k + aeq_num],
5164 &eq_table->eq[k - other_num]);
5165 else
5166 ret = request_irq(eq_table->eq[k - other_num].irq,
5167 hns_roce_v2_msix_interrupt_eq,
5168 0, hr_dev->irq_names[k - comp_num],
5169 &eq_table->eq[k - other_num]);
5170 if (ret) {
5171 dev_err(dev, "Request irq error!\n");
5172 goto err_request_irq_fail;
5173 }
5174 }
5175
0425e3e6
YL		 5176 hr_dev->irq_workq =
5177 create_singlethread_workqueue("hns_roce_irq_workqueue");
5178 if (!hr_dev->irq_workq) {
5179 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5180 ret = -ENOMEM;
0425e3e6
YL		 5181 goto err_request_irq_fail;
5182 }
5183
a5073d60
YL		 5184 return 0;
5185
5186err_request_irq_fail:
5187 for (k -= 1; k >= 0; k--)
5188 if (k < other_num)
5189 free_irq(hr_dev->irq[k], hr_dev);
5190 else
5191 free_irq(eq_table->eq[k - other_num].irq,
5192 &eq_table->eq[k - other_num]);
5193
5194err_create_eq_fail:
5195 for (j -= 1; j >= 0; j--)
5196 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]);
5197
5198err_failed_kzalloc:
5199 for (i -= 1; i >= 0; i--)
5200 kfree(hr_dev->irq_names[i]);
5201 kfree(eq_table->eq);
5202
5203 return ret;
5204}
5205
5206static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5207{
5208 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5209 int irq_num;
5210 int eq_num;
5211 int i;
5212
5213 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5214 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5215
5216 /* Disable irq */
5217 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5218
5219 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5220 free_irq(hr_dev->irq[i], hr_dev);
5221
5222 for (i = 0; i < eq_num; i++) {
5223 hns_roce_v2_destroy_eqc(hr_dev, i);
5224
5225 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]);
5226
5227 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]);
5228 }
5229
5230 for (i = 0; i < irq_num; i++)
5231 kfree(hr_dev->irq_names[i]);
5232
5233 kfree(eq_table->eq);
0425e3e6
YL		 5234
5235 flush_workqueue(hr_dev->irq_workq);
5236 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5237}
5238
a04ff739
WHX		 5239static const struct hns_roce_hw hns_roce_hw_v2 = {
5240 .cmq_init = hns_roce_v2_cmq_init,
5241 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5242 .hw_profile = hns_roce_v2_profile,
6b63597d 5243 .hw_init = hns_roce_v2_init,
5244 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5245 .post_mbox = hns_roce_v2_post_mbox,
5246 .chk_mbox = hns_roce_v2_chk_mbox,
7afddafa
WHX		 5247 .set_gid = hns_roce_v2_set_gid,
5248 .set_mac = hns_roce_v2_set_mac,
3958cc56 5249 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5250 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
c7c28191 5251 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 5252 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5253 .set_hem = hns_roce_v2_set_hem,
5254 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5255 .modify_qp = hns_roce_v2_modify_qp,
5256 .query_qp = hns_roce_v2_query_qp,
5257 .destroy_qp = hns_roce_v2_destroy_qp,
b156269d 5258 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5259 .post_send = hns_roce_v2_post_send,
5260 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5261 .req_notify_cq = hns_roce_v2_req_notify_cq,
5262 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5263 .init_eq = hns_roce_v2_init_eq_table,
5264 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
a04ff739 5265};
dd74282d
WHX		 5266
5267static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5268 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5269 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 5270 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
5271 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 5272 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
5273 /* required last entry */
5274 {0, }
5275};
5276
f97a62c3 5277MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
5278
dd74282d
WHX		 5279static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
5280 struct hnae3_handle *handle)
5281{
5282 const struct pci_device_id *id;
a5073d60 5283 int i;
dd74282d
WHX		 5284
5285 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
5286 if (!id) {
5287 dev_err(hr_dev->dev, "device is not compatible!\n");
5288 return -ENXIO;
5289 }
5290
5291 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 5292 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
5293 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 5294
5295 /* Get info from NIC driver. */
5296 hr_dev->reg_base = handle->rinfo.roce_io_base;
5297 hr_dev->caps.num_ports = 1;
5298 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
5299 hr_dev->iboe.phy_port[0] = 0;
5300
d4994d2f 5301 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
5302 hr_dev->iboe.netdevs[0]->dev_addr);
5303
a5073d60
YL		 5304 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
5305 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
5306 i + handle->rinfo.base_vector);
5307
dd74282d 5308 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 5309 hr_dev->cmd_mod = 1;
dd74282d
WHX		 5310 hr_dev->loop_idc = 0;
5311
5312 return 0;
5313}
5314
5315static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
5316{
5317 struct hns_roce_dev *hr_dev;
5318 int ret;
5319
5320 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
5321 if (!hr_dev)
5322 return -ENOMEM;
5323
a04ff739
WHX		 5324 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
5325 if (!hr_dev->priv) {
5326 ret = -ENOMEM;
5327 goto error_failed_kzalloc;
5328 }
5329
dd74282d
WHX		 5330 hr_dev->pci_dev = handle->pdev;
5331 hr_dev->dev = &handle->pdev->dev;
5332 handle->priv = hr_dev;
5333
5334 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
5335 if (ret) {
5336 dev_err(hr_dev->dev, "Get Configuration failed!\n");
5337 goto error_failed_get_cfg;
5338 }
5339
5340 ret = hns_roce_init(hr_dev);
5341 if (ret) {
5342 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
5343 goto error_failed_get_cfg;
5344 }
5345
5346 return 0;
5347
5348error_failed_get_cfg:
a04ff739
WHX		 5349 kfree(hr_dev->priv);
5350
5351error_failed_kzalloc:
dd74282d
WHX		 5352 ib_dealloc_device(&hr_dev->ib_dev);
5353
5354 return ret;
5355}
5356
5357static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
5358 bool reset)
5359{
5360 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5361
cb7a94c9
WHX		 5362 if (!hr_dev)
5363 return;
5364
dd74282d 5365 hns_roce_exit(hr_dev);
a04ff739 5366 kfree(hr_dev->priv);
dd74282d
WHX		 5367 ib_dealloc_device(&hr_dev->ib_dev);
5368}
5369
cb7a94c9
WHX		 5370static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
5371{
5372 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5373 struct ib_event event;
5374
5375 if (!hr_dev) {
5376 dev_err(&handle->pdev->dev,
5377 "Input parameter handle->priv is NULL!\n");
5378 return -EINVAL;
5379 }
5380
5381 hr_dev->active = false;
5382 hr_dev->is_reset = true;
5383
5384 event.event = IB_EVENT_DEVICE_FATAL;
5385 event.device = &hr_dev->ib_dev;
5386 event.element.port_num = 1;
5387 ib_dispatch_event(&event);
5388
5389 return 0;
5390}
5391
5392static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
5393{
5394 int ret;
5395
5396 ret = hns_roce_hw_v2_init_instance(handle);
5397 if (ret) {
5398 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
5399 * callback function, RoCE Engine reinitialize. If RoCE reinit
5400 * failed, we should inform NIC driver.
5401 */
5402 handle->priv = NULL;
5403 dev_err(&handle->pdev->dev,
5404 "In reset process RoCE reinit failed %d.\n", ret);
5405 }
5406
5407 return ret;
5408}
5409
5410static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
5411{
5412 msleep(100);
5413 hns_roce_hw_v2_uninit_instance(handle, false);
5414 return 0;
5415}
5416
5417static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
5418 enum hnae3_reset_notify_type type)
5419{
5420 int ret = 0;
5421
5422 switch (type) {
5423 case HNAE3_DOWN_CLIENT:
5424 ret = hns_roce_hw_v2_reset_notify_down(handle);
5425 break;
5426 case HNAE3_INIT_CLIENT:
5427 ret = hns_roce_hw_v2_reset_notify_init(handle);
5428 break;
5429 case HNAE3_UNINIT_CLIENT:
5430 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
5431 break;
5432 default:
5433 break;
5434 }
5435
5436 return ret;
5437}
5438
dd74282d
WHX		 5439static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
5440 .init_instance = hns_roce_hw_v2_init_instance,
5441 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 5442 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 5443};
5444
5445static struct hnae3_client hns_roce_hw_v2_client = {
5446 .name = "hns_roce_hw_v2",
5447 .type = HNAE3_CLIENT_ROCE,
5448 .ops = &hns_roce_hw_v2_ops,
5449};
5450
5451static int __init hns_roce_hw_v2_init(void)
5452{
5453 return hnae3_register_client(&hns_roce_hw_v2_client);
5454}
5455
5456static void __exit hns_roce_hw_v2_exit(void)
5457{
5458 hnae3_unregister_client(&hns_roce_hw_v2_client);
5459}
5460
5461module_init(hns_roce_hw_v2_init);
5462module_exit(hns_roce_hw_v2_exit);
5463
5464MODULE_LICENSE("Dual BSD/GPL");
5465MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5466MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5467MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
5468MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)