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Merge branch 'mlx5-devx' into wip/dl-for-next
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
dd74282d
WHX		 40#include <rdma/ib_umem.h>
41
42#include "hnae3.h"
43#include "hns_roce_common.h"
44#include "hns_roce_device.h"
45#include "hns_roce_cmd.h"
46#include "hns_roce_hem.h"
a04ff739 47#include "hns_roce_hw_v2.h"
dd74282d 48
2d407888
WHX		 49static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
50 struct ib_sge *sg)
51{
52 dseg->lkey = cpu_to_le32(sg->lkey);
53 dseg->addr = cpu_to_le64(sg->addr);
54 dseg->len = cpu_to_le32(sg->length);
55}
56
68a997c5
YL		 57static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
58 struct hns_roce_wqe_frmr_seg *fseg,
59 const struct ib_reg_wr *wr)
60{
61 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
62
63 /* use ib_access_flags */
64 roce_set_bit(rc_sq_wqe->byte_4,
65 V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
66 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
67 roce_set_bit(rc_sq_wqe->byte_4,
68 V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
69 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
70 roce_set_bit(rc_sq_wqe->byte_4,
71 V2_RC_FRMR_WQE_BYTE_4_RR_S,
72 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
73 roce_set_bit(rc_sq_wqe->byte_4,
74 V2_RC_FRMR_WQE_BYTE_4_RW_S,
75 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
76 roce_set_bit(rc_sq_wqe->byte_4,
77 V2_RC_FRMR_WQE_BYTE_4_LW_S,
78 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
79
80 /* Data structure reuse may lead to confusion */
81 rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff);
82 rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32);
83
84 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
85 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
86 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
87 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
88
89 fseg->pbl_size = cpu_to_le32(mr->pbl_size);
90 roce_set_field(fseg->mode_buf_pg_sz,
91 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
92 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
93 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
94 roce_set_bit(fseg->mode_buf_pg_sz,
95 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
96}
97
384f8818
LO		 98static void set_atomic_seg(struct hns_roce_wqe_atomic_seg *aseg,
99 const struct ib_atomic_wr *wr)
100{
101 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
102 aseg->fetchadd_swap_data = cpu_to_le64(wr->swap);
103 aseg->cmp_data = cpu_to_le64(wr->compare_add);
104 } else {
105 aseg->fetchadd_swap_data = cpu_to_le64(wr->compare_add);
106 aseg->cmp_data = 0;
107 }
108}
109
f696bf6d 110static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
0b25c9cc
WHX		 111 unsigned int *sge_ind)
112{
113 struct hns_roce_v2_wqe_data_seg *dseg;
114 struct ib_sge *sg;
115 int num_in_wqe = 0;
116 int extend_sge_num;
117 int fi_sge_num;
118 int se_sge_num;
119 int shift;
120 int i;
121
122 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
123 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
124 extend_sge_num = wr->num_sge - num_in_wqe;
125 sg = wr->sg_list + num_in_wqe;
126 shift = qp->hr_buf.page_shift;
127
128 /*
129 * Check whether wr->num_sge sges are in the same page. If not, we
130 * should calculate how many sges in the first page and the second
131 * page.
132 */
133 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
134 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
135 (uintptr_t)dseg) /
136 sizeof(struct hns_roce_v2_wqe_data_seg);
137 if (extend_sge_num > fi_sge_num) {
138 se_sge_num = extend_sge_num - fi_sge_num;
139 for (i = 0; i < fi_sge_num; i++) {
140 set_data_seg_v2(dseg++, sg + i);
141 (*sge_ind)++;
142 }
143 dseg = get_send_extend_sge(qp,
144 (*sge_ind) & (qp->sge.sge_cnt - 1));
145 for (i = 0; i < se_sge_num; i++) {
146 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
147 (*sge_ind)++;
148 }
149 } else {
150 for (i = 0; i < extend_sge_num; i++) {
151 set_data_seg_v2(dseg++, sg + i);
152 (*sge_ind)++;
153 }
154 }
155}
156
f696bf6d 157static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 158 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
159 void *wqe, unsigned int *sge_ind,
d34ac5cd 160 const struct ib_send_wr **bad_wr)
7bdee415 161{
162 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
163 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
164 struct hns_roce_qp *qp = to_hr_qp(ibqp);
165 int i;
166
167 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 168 if (le32_to_cpu(rc_sq_wqe->msg_len) >
169 hr_dev->caps.max_sq_inline) {
7bdee415 170 *bad_wr = wr;
171 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
172 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
173 return -EINVAL;
174 }
175
328d405b 176 if (wr->opcode == IB_WR_RDMA_READ) {
c80e0661 177 *bad_wr = wr;
328d405b 178 dev_err(hr_dev->dev, "Not support inline data!\n");
179 return -EINVAL;
180 }
181
7bdee415 182 for (i = 0; i < wr->num_sge; i++) {
183 memcpy(wqe, ((void *)wr->sg_list[i].addr),
184 wr->sg_list[i].length);
185 wqe += wr->sg_list[i].length;
186 }
187
188 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
189 1);
190 } else {
0b25c9cc 191 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 192 for (i = 0; i < wr->num_sge; i++) {
193 if (likely(wr->sg_list[i].length)) {
194 set_data_seg_v2(dseg, wr->sg_list + i);
195 dseg++;
196 }
197 }
198 } else {
199 roce_set_field(rc_sq_wqe->byte_20,
200 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
201 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
202 (*sge_ind) & (qp->sge.sge_cnt - 1));
203
0b25c9cc 204 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 205 if (likely(wr->sg_list[i].length)) {
206 set_data_seg_v2(dseg, wr->sg_list + i);
207 dseg++;
208 }
209 }
210
0b25c9cc 211 set_extend_sge(qp, wr, sge_ind);
7bdee415 212 }
213
214 roce_set_field(rc_sq_wqe->byte_16,
215 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
216 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
217 }
218
219 return 0;
220}
221
0425e3e6
YL		 222static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
223 const struct ib_qp_attr *attr,
224 int attr_mask, enum ib_qp_state cur_state,
225 enum ib_qp_state new_state);
226
d34ac5cd
BVA		 227static int hns_roce_v2_post_send(struct ib_qp *ibqp,
228 const struct ib_send_wr *wr,
229 const struct ib_send_wr **bad_wr)
2d407888
WHX		 230{
231 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
7bdee415 232 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
233 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
2d407888
WHX		 234 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
235 struct hns_roce_qp *qp = to_hr_qp(ibqp);
68a997c5 236 struct hns_roce_wqe_frmr_seg *fseg;
2d407888
WHX		 237 struct device *dev = hr_dev->dev;
238 struct hns_roce_v2_db sq_db;
0425e3e6 239 struct ib_qp_attr attr;
2d407888 240 unsigned int sge_ind = 0;
e8d18533 241 unsigned int owner_bit;
2d407888
WHX		 242 unsigned long flags;
243 unsigned int ind;
244 void *wqe = NULL;
7bdee415 245 bool loopback;
0425e3e6 246 int attr_mask;
55ba49cb 247 u32 tmp_len;
2d407888 248 int ret = 0;
b9c1ea40 249 u32 hr_op;
7bdee415 250 u8 *smac;
2d407888
WHX		 251 int nreq;
252 int i;
253
7bdee415 254 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
255 ibqp->qp_type != IB_QPT_GSI &&
256 ibqp->qp_type != IB_QPT_UD)) {
2d407888 257 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
137ae320 258 *bad_wr = wr;
2d407888
WHX		 259 return -EOPNOTSUPP;
260 }
261
10bd2ade
YL		 262 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT ||
263 qp->state == IB_QPS_RTR)) {
2d407888
WHX		 264 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
265 *bad_wr = wr;
266 return -EINVAL;
267 }
268
269 spin_lock_irqsave(&qp->sq.lock, flags);
270 ind = qp->sq_next_wqe;
271 sge_ind = qp->next_sge;
272
273 for (nreq = 0; wr; ++nreq, wr = wr->next) {
274 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
275 ret = -ENOMEM;
276 *bad_wr = wr;
277 goto out;
278 }
279
280 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
281 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
282 wr->num_sge, qp->sq.max_gs);
283 ret = -EINVAL;
284 *bad_wr = wr;
285 goto out;
286 }
287
288 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
289 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
290 wr->wr_id;
291
634f6390 292 owner_bit =
293 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
55ba49cb 294 tmp_len = 0;
2d407888 295
7bdee415 296 /* Corresponding to the QP type, wqe process separately */
297 if (ibqp->qp_type == IB_QPT_GSI) {
298 ud_sq_wqe = wqe;
299 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
300
301 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
302 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
303 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
304 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
305 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
306 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
307 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
308 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
309 roce_set_field(ud_sq_wqe->byte_48,
310 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
311 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
312 ah->av.mac[4]);
313 roce_set_field(ud_sq_wqe->byte_48,
314 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
315 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
316 ah->av.mac[5]);
317
318 /* MAC loopback */
319 smac = (u8 *)hr_dev->dev_addr[qp->port];
320 loopback = ether_addr_equal_unaligned(ah->av.mac,
321 smac) ? 1 : 0;
322
323 roce_set_bit(ud_sq_wqe->byte_40,
324 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
325
326 roce_set_field(ud_sq_wqe->byte_4,
327 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
328 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
329 HNS_ROCE_V2_WQE_OP_SEND);
2d407888 330
7bdee415 331 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 332 tmp_len += wr->sg_list[i].length;
492b2bd0 333
8b9b8d14 334 ud_sq_wqe->msg_len =
335 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len);
336
337 switch (wr->opcode) {
338 case IB_WR_SEND_WITH_IMM:
339 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 340 ud_sq_wqe->immtdata =
341 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 342 break;
343 default:
344 ud_sq_wqe->immtdata = 0;
345 break;
346 }
651487c2 347
7bdee415 348 /* Set sig attr */
349 roce_set_bit(ud_sq_wqe->byte_4,
350 V2_UD_SEND_WQE_BYTE_4_CQE_S,
351 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
a49d761f 352
7bdee415 353 /* Set se attr */
354 roce_set_bit(ud_sq_wqe->byte_4,
355 V2_UD_SEND_WQE_BYTE_4_SE_S,
356 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
e8d18533 357
7bdee415 358 roce_set_bit(ud_sq_wqe->byte_4,
359 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
360
361 roce_set_field(ud_sq_wqe->byte_16,
362 V2_UD_SEND_WQE_BYTE_16_PD_M,
363 V2_UD_SEND_WQE_BYTE_16_PD_S,
364 to_hr_pd(ibqp->pd)->pdn);
365
366 roce_set_field(ud_sq_wqe->byte_16,
367 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
368 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
369 wr->num_sge);
370
371 roce_set_field(ud_sq_wqe->byte_20,
372 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
373 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
374 sge_ind & (qp->sge.sge_cnt - 1));
375
376 roce_set_field(ud_sq_wqe->byte_24,
377 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
378 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
379 ud_sq_wqe->qkey =
8b9b8d14 380 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
381 qp->qkey : ud_wr(wr)->remote_qkey);
7bdee415 382 roce_set_field(ud_sq_wqe->byte_32,
383 V2_UD_SEND_WQE_BYTE_32_DQPN_M,
384 V2_UD_SEND_WQE_BYTE_32_DQPN_S,
385 ud_wr(wr)->remote_qpn);
386
387 roce_set_field(ud_sq_wqe->byte_36,
388 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
389 V2_UD_SEND_WQE_BYTE_36_VLAN_S,
8b9b8d14 390 le16_to_cpu(ah->av.vlan));
7bdee415 391 roce_set_field(ud_sq_wqe->byte_36,
392 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
393 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
394 ah->av.hop_limit);
395 roce_set_field(ud_sq_wqe->byte_36,
396 V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
397 V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
cdfa4ad5
LO		 398 ah->av.sl_tclass_flowlabel >>
399 HNS_ROCE_TCLASS_SHIFT);
7bdee415 400 roce_set_field(ud_sq_wqe->byte_40,
401 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
cdfa4ad5
LO		 402 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
403 ah->av.sl_tclass_flowlabel &
404 HNS_ROCE_FLOW_LABEL_MASK);
7bdee415 405 roce_set_field(ud_sq_wqe->byte_40,
406 V2_UD_SEND_WQE_BYTE_40_SL_M,
407 V2_UD_SEND_WQE_BYTE_40_SL_S,
8b9b8d14 408 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
409 HNS_ROCE_SL_SHIFT);
7bdee415 410 roce_set_field(ud_sq_wqe->byte_40,
411 V2_UD_SEND_WQE_BYTE_40_PORTN_M,
412 V2_UD_SEND_WQE_BYTE_40_PORTN_S,
413 qp->port);
414
8320deb8
LO		 415 roce_set_bit(ud_sq_wqe->byte_40,
416 V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
417 ah->av.vlan_en ? 1 : 0);
7bdee415 418 roce_set_field(ud_sq_wqe->byte_48,
419 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
420 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
421 hns_get_gid_index(hr_dev, qp->phy_port,
422 ah->av.gid_index));
423
424 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
425 GID_LEN_V2);
426
0b25c9cc 427 set_extend_sge(qp, wr, &sge_ind);
7bdee415 428 ind++;
429 } else if (ibqp->qp_type == IB_QPT_RC) {
430 rc_sq_wqe = wqe;
431 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
432 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 433 tmp_len += wr->sg_list[i].length;
434
435 rc_sq_wqe->msg_len =
436 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len);
7bdee415 437
8b9b8d14 438 switch (wr->opcode) {
439 case IB_WR_SEND_WITH_IMM:
440 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 441 rc_sq_wqe->immtdata =
442 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 443 break;
444 case IB_WR_SEND_WITH_INV:
445 rc_sq_wqe->inv_key =
446 cpu_to_le32(wr->ex.invalidate_rkey);
447 break;
448 default:
449 rc_sq_wqe->immtdata = 0;
450 break;
451 }
7bdee415 452
453 roce_set_bit(rc_sq_wqe->byte_4,
454 V2_RC_SEND_WQE_BYTE_4_FENCE_S,
455 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
456
457 roce_set_bit(rc_sq_wqe->byte_4,
458 V2_RC_SEND_WQE_BYTE_4_SE_S,
459 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
460
461 roce_set_bit(rc_sq_wqe->byte_4,
462 V2_RC_SEND_WQE_BYTE_4_CQE_S,
463 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
464
465 roce_set_bit(rc_sq_wqe->byte_4,
466 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
467
384f8818 468 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
7bdee415 469 switch (wr->opcode) {
470 case IB_WR_RDMA_READ:
b9c1ea40 471 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
7bdee415 472 rc_sq_wqe->rkey =
473 cpu_to_le32(rdma_wr(wr)->rkey);
474 rc_sq_wqe->va =
475 cpu_to_le64(rdma_wr(wr)->remote_addr);
476 break;
477 case IB_WR_RDMA_WRITE:
b9c1ea40 478 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
7bdee415 479 rc_sq_wqe->rkey =
480 cpu_to_le32(rdma_wr(wr)->rkey);
481 rc_sq_wqe->va =
482 cpu_to_le64(rdma_wr(wr)->remote_addr);
483 break;
484 case IB_WR_RDMA_WRITE_WITH_IMM:
b9c1ea40 485 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
7bdee415 486 rc_sq_wqe->rkey =
487 cpu_to_le32(rdma_wr(wr)->rkey);
488 rc_sq_wqe->va =
489 cpu_to_le64(rdma_wr(wr)->remote_addr);
490 break;
491 case IB_WR_SEND:
b9c1ea40 492 hr_op = HNS_ROCE_V2_WQE_OP_SEND;
7bdee415 493 break;
494 case IB_WR_SEND_WITH_INV:
b9c1ea40 495 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
7bdee415 496 break;
497 case IB_WR_SEND_WITH_IMM:
b9c1ea40 498 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
7bdee415 499 break;
500 case IB_WR_LOCAL_INV:
b9c1ea40 501 hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
e93df010
LO		 502 roce_set_bit(rc_sq_wqe->byte_4,
503 V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
504 rc_sq_wqe->inv_key =
505 cpu_to_le32(wr->ex.invalidate_rkey);
7bdee415 506 break;
68a997c5
YL		 507 case IB_WR_REG_MR:
508 hr_op = HNS_ROCE_V2_WQE_OP_FAST_REG_PMR;
509 fseg = wqe;
510 set_frmr_seg(rc_sq_wqe, fseg, reg_wr(wr));
511 break;
7bdee415 512 case IB_WR_ATOMIC_CMP_AND_SWP:
b9c1ea40 513 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
384f8818
LO		 514 rc_sq_wqe->rkey =
515 cpu_to_le32(atomic_wr(wr)->rkey);
516 rc_sq_wqe->va =
d9581bf3 517 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 518 break;
519 case IB_WR_ATOMIC_FETCH_AND_ADD:
b9c1ea40 520 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
384f8818
LO		 521 rc_sq_wqe->rkey =
522 cpu_to_le32(atomic_wr(wr)->rkey);
523 rc_sq_wqe->va =
d9581bf3 524 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 525 break;
526 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
b9c1ea40
LO		 527 hr_op =
528 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
7bdee415 529 break;
530 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
b9c1ea40
LO		 531 hr_op =
532 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
7bdee415 533 break;
534 default:
b9c1ea40 535 hr_op = HNS_ROCE_V2_WQE_OP_MASK;
7bdee415 536 break;
2d407888
WHX		 537 }
538
b9c1ea40
LO		 539 roce_set_field(rc_sq_wqe->byte_4,
540 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
541 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
2d407888 542
d9581bf3
LO		 543 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
544 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
545 struct hns_roce_v2_wqe_data_seg *dseg;
546
547 dseg = wqe;
548 set_data_seg_v2(dseg, wr->sg_list);
549 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
550 set_atomic_seg(wqe, atomic_wr(wr));
551 roce_set_field(rc_sq_wqe->byte_16,
552 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
553 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
554 wr->num_sge);
68a997c5 555 } else if (wr->opcode != IB_WR_REG_MR) {
d9581bf3
LO		 556 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe,
557 wqe, &sge_ind, bad_wr);
558 if (ret)
559 goto out;
560 }
561
7bdee415 562 ind++;
2d407888 563 } else {
7bdee415 564 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
565 spin_unlock_irqrestore(&qp->sq.lock, flags);
137ae320 566 *bad_wr = wr;
7bdee415 567 return -EOPNOTSUPP;
2d407888 568 }
2d407888
WHX		 569 }
570
571out:
572 if (likely(nreq)) {
573 qp->sq.head += nreq;
574 /* Memory barrier */
575 wmb();
576
577 sq_db.byte_4 = 0;
578 sq_db.parameter = 0;
579
580 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
581 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
582 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
583 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
cc3391cb 584 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
585 V2_DB_PARAMETER_IDX_S,
2d407888
WHX		 586 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
587 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
588 V2_DB_PARAMETER_SL_S, qp->sl);
589
8b9b8d14 590 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l);
2d407888
WHX		 591
592 qp->sq_next_wqe = ind;
593 qp->next_sge = sge_ind;
0425e3e6
YL		 594
595 if (qp->state == IB_QPS_ERR) {
596 attr_mask = IB_QP_STATE;
597 attr.qp_state = IB_QPS_ERR;
598
599 ret = hns_roce_v2_modify_qp(&qp->ibqp, &attr, attr_mask,
600 qp->state, IB_QPS_ERR);
601 if (ret) {
602 spin_unlock_irqrestore(&qp->sq.lock, flags);
603 *bad_wr = wr;
604 return ret;
605 }
606 }
2d407888
WHX		 607 }
608
609 spin_unlock_irqrestore(&qp->sq.lock, flags);
610
611 return ret;
612}
613
d34ac5cd
BVA		 614static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
615 const struct ib_recv_wr *wr,
616 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 617{
618 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
619 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
620 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 621 struct hns_roce_rinl_sge *sge_list;
2d407888 622 struct device *dev = hr_dev->dev;
0425e3e6 623 struct ib_qp_attr attr;
2d407888
WHX		 624 unsigned long flags;
625 void *wqe = NULL;
0425e3e6 626 int attr_mask;
2d407888
WHX		 627 int ret = 0;
628 int nreq;
629 int ind;
630 int i;
631
632 spin_lock_irqsave(&hr_qp->rq.lock, flags);
633 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
634
ced07769 635 if (hr_qp->state == IB_QPS_RESET) {
2d407888
WHX		 636 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
637 *bad_wr = wr;
638 return -EINVAL;
639 }
640
641 for (nreq = 0; wr; ++nreq, wr = wr->next) {
642 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
643 hr_qp->ibqp.recv_cq)) {
644 ret = -ENOMEM;
645 *bad_wr = wr;
646 goto out;
647 }
648
649 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
650 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
651 wr->num_sge, hr_qp->rq.max_gs);
652 ret = -EINVAL;
653 *bad_wr = wr;
654 goto out;
655 }
656
657 wqe = get_recv_wqe(hr_qp, ind);
658 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
659 for (i = 0; i < wr->num_sge; i++) {
660 if (!wr->sg_list[i].length)
661 continue;
662 set_data_seg_v2(dseg, wr->sg_list + i);
663 dseg++;
664 }
665
666 if (i < hr_qp->rq.max_gs) {
778cc5a8 667 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
668 dseg->addr = 0;
2d407888
WHX		 669 }
670
0009c2db 671 /* rq support inline data */
ecaaf1e2 672 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
673 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
674 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
675 (u32)wr->num_sge;
676 for (i = 0; i < wr->num_sge; i++) {
677 sge_list[i].addr =
678 (void *)(u64)wr->sg_list[i].addr;
679 sge_list[i].len = wr->sg_list[i].length;
680 }
0009c2db 681 }
682
2d407888
WHX		 683 hr_qp->rq.wrid[ind] = wr->wr_id;
684
685 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
686 }
687
688out:
689 if (likely(nreq)) {
690 hr_qp->rq.head += nreq;
691 /* Memory barrier */
692 wmb();
693
472bc0fb 694 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
0425e3e6
YL		 695
696 if (hr_qp->state == IB_QPS_ERR) {
697 attr_mask = IB_QP_STATE;
698 attr.qp_state = IB_QPS_ERR;
699
700 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr,
701 attr_mask, hr_qp->state,
702 IB_QPS_ERR);
703 if (ret) {
704 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
705 *bad_wr = wr;
706 return ret;
707 }
708 }
2d407888
WHX		 709 }
710 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
711
712 return ret;
713}
714
a04ff739
WHX		 715static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
716{
717 int ntu = ring->next_to_use;
718 int ntc = ring->next_to_clean;
719 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
720
721 return ring->desc_num - used - 1;
722}
723
724static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
725 struct hns_roce_v2_cmq_ring *ring)
726{
727 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
728
729 ring->desc = kzalloc(size, GFP_KERNEL);
730 if (!ring->desc)
731 return -ENOMEM;
732
733 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
734 DMA_BIDIRECTIONAL);
735 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
736 ring->desc_dma_addr = 0;
737 kfree(ring->desc);
738 ring->desc = NULL;
739 return -ENOMEM;
740 }
741
742 return 0;
743}
744
745static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
746 struct hns_roce_v2_cmq_ring *ring)
747{
748 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
749 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
750 DMA_BIDIRECTIONAL);
90e7a4d5 751
752 ring->desc_dma_addr = 0;
a04ff739
WHX		 753 kfree(ring->desc);
754}
755
756static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
757{
758 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
759 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
760 &priv->cmq.csq : &priv->cmq.crq;
761
762 ring->flag = ring_type;
763 ring->next_to_clean = 0;
764 ring->next_to_use = 0;
765
766 return hns_roce_alloc_cmq_desc(hr_dev, ring);
767}
768
769static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
770{
771 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
772 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
773 &priv->cmq.csq : &priv->cmq.crq;
774 dma_addr_t dma = ring->desc_dma_addr;
775
776 if (ring_type == TYPE_CSQ) {
777 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
778 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
779 upper_32_bits(dma));
780 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
781 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
782 HNS_ROCE_CMQ_ENABLE);
783 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
784 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
785 } else {
786 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
787 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
788 upper_32_bits(dma));
789 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
790 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
791 HNS_ROCE_CMQ_ENABLE);
792 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
793 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
794 }
795}
796
797static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
798{
799 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
800 int ret;
801
802 /* Setup the queue entries for command queue */
426c4146
LO		 803 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
804 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 805
806 /* Setup the lock for command queue */
807 spin_lock_init(&priv->cmq.csq.lock);
808 spin_lock_init(&priv->cmq.crq.lock);
809
810 /* Setup Tx write back timeout */
811 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
812
813 /* Init CSQ */
814 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
815 if (ret) {
816 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
817 return ret;
818 }
819
820 /* Init CRQ */
821 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
822 if (ret) {
823 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
824 goto err_crq;
825 }
826
827 /* Init CSQ REG */
828 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
829
830 /* Init CRQ REG */
831 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
832
833 return 0;
834
835err_crq:
836 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
837
838 return ret;
839}
840
841static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
842{
843 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
844
845 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
846 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
847}
848
281d0ccf
CIK		 849static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
850 enum hns_roce_opcode_type opcode,
851 bool is_read)
a04ff739
WHX		 852{
853 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
854 desc->opcode = cpu_to_le16(opcode);
855 desc->flag =
856 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
857 if (is_read)
858 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
859 else
860 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
861}
862
863static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
864{
865 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
866 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
867
868 return head == priv->cmq.csq.next_to_use;
869}
870
871static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
872{
873 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
874 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
875 struct hns_roce_cmq_desc *desc;
876 u16 ntc = csq->next_to_clean;
877 u32 head;
878 int clean = 0;
879
880 desc = &csq->desc[ntc];
881 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
882 while (head != ntc) {
883 memset(desc, 0, sizeof(*desc));
884 ntc++;
885 if (ntc == csq->desc_num)
886 ntc = 0;
887 desc = &csq->desc[ntc];
888 clean++;
889 }
890 csq->next_to_clean = ntc;
891
892 return clean;
893}
894
281d0ccf
CIK		 895static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
896 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 897{
898 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
899 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
900 struct hns_roce_cmq_desc *desc_to_use;
901 bool complete = false;
902 u32 timeout = 0;
903 int handle = 0;
904 u16 desc_ret;
905 int ret = 0;
906 int ntc;
907
cb7a94c9
WHX		 908 if (hr_dev->is_reset)
909 return 0;
910
a04ff739
WHX		 911 spin_lock_bh(&csq->lock);
912
913 if (num > hns_roce_cmq_space(csq)) {
914 spin_unlock_bh(&csq->lock);
915 return -EBUSY;
916 }
917
918 /*
919 * Record the location of desc in the cmq for this time
920 * which will be use for hardware to write back
921 */
922 ntc = csq->next_to_use;
923
924 while (handle < num) {
925 desc_to_use = &csq->desc[csq->next_to_use];
926 *desc_to_use = desc[handle];
927 dev_dbg(hr_dev->dev, "set cmq desc:\n");
928 csq->next_to_use++;
929 if (csq->next_to_use == csq->desc_num)
930 csq->next_to_use = 0;
931 handle++;
932 }
933
934 /* Write to hardware */
935 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
936
937 /*
938 * If the command is sync, wait for the firmware to write back,
939 * if multi descriptors to be sent, use the first one to check
940 */
941 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
942 do {
943 if (hns_roce_cmq_csq_done(hr_dev))
944 break;
988e175b 945 udelay(1);
a04ff739
WHX		 946 timeout++;
947 } while (timeout < priv->cmq.tx_timeout);
948 }
949
950 if (hns_roce_cmq_csq_done(hr_dev)) {
951 complete = true;
952 handle = 0;
953 while (handle < num) {
954 /* get the result of hardware write back */
955 desc_to_use = &csq->desc[ntc];
956 desc[handle] = *desc_to_use;
957 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
958 desc_ret = desc[handle].retval;
959 if (desc_ret == CMD_EXEC_SUCCESS)
960 ret = 0;
961 else
962 ret = -EIO;
963 priv->cmq.last_status = desc_ret;
964 ntc++;
965 handle++;
966 if (ntc == csq->desc_num)
967 ntc = 0;
968 }
969 }
970
971 if (!complete)
972 ret = -EAGAIN;
973
974 /* clean the command send queue */
975 handle = hns_roce_cmq_csq_clean(hr_dev);
976 if (handle != num)
977 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
978 handle, num);
979
980 spin_unlock_bh(&csq->lock);
981
982 return ret;
983}
984
281d0ccf 985static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 986{
987 struct hns_roce_query_version *resp;
988 struct hns_roce_cmq_desc desc;
989 int ret;
990
991 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
992 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
993 if (ret)
994 return ret;
995
996 resp = (struct hns_roce_query_version *)desc.data;
997 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 998 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
999
1000 return 0;
1001}
1002
1003static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1004{
1005 struct hns_roce_query_fw_info *resp;
1006 struct hns_roce_cmq_desc desc;
1007 int ret;
1008
1009 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1010 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1011 if (ret)
1012 return ret;
1013
1014 resp = (struct hns_roce_query_fw_info *)desc.data;
1015 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1016
1017 return 0;
1018}
1019
1020static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1021{
1022 struct hns_roce_cfg_global_param *req;
1023 struct hns_roce_cmq_desc desc;
1024
1025 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1026 false);
1027
1028 req = (struct hns_roce_cfg_global_param *)desc.data;
1029 memset(req, 0, sizeof(*req));
1030 roce_set_field(req->time_cfg_udp_port,
1031 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1032 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1033 roce_set_field(req->time_cfg_udp_port,
1034 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1035 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1036
1037 return hns_roce_cmq_send(hr_dev, &desc, 1);
1038}
1039
1040static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1041{
1042 struct hns_roce_cmq_desc desc[2];
6b63597d 1043 struct hns_roce_pf_res_a *req_a;
1044 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1045 int ret;
1046 int i;
1047
1048 for (i = 0; i < 2; i++) {
1049 hns_roce_cmq_setup_basic_desc(&desc[i],
1050 HNS_ROCE_OPC_QUERY_PF_RES, true);
1051
1052 if (i == 0)
1053 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1054 else
1055 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1056 }
1057
1058 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1059 if (ret)
1060 return ret;
1061
6b63597d 1062 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1063 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1064
6b63597d 1065 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1066 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1067 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1068 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1069 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1070 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1071 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1072 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1073 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1074 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1075 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1076 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1077
6b63597d 1078 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1079 PF_RES_DATA_3_PF_SL_NUM_M,
1080 PF_RES_DATA_3_PF_SL_NUM_S);
1081
cfc85f3e
WHX		 1082 return 0;
1083}
1084
1085static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1086{
1087 struct hns_roce_cmq_desc desc[2];
1088 struct hns_roce_vf_res_a *req_a;
1089 struct hns_roce_vf_res_b *req_b;
1090 int i;
1091
1092 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1093 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1094 memset(req_a, 0, sizeof(*req_a));
1095 memset(req_b, 0, sizeof(*req_b));
1096 for (i = 0; i < 2; i++) {
1097 hns_roce_cmq_setup_basic_desc(&desc[i],
1098 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1099
1100 if (i == 0)
1101 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1102 else
1103 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1104
1105 if (i == 0) {
1106 roce_set_field(req_a->vf_qpc_bt_idx_num,
1107 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1108 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1109 roce_set_field(req_a->vf_qpc_bt_idx_num,
1110 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1111 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
1112 HNS_ROCE_VF_QPC_BT_NUM);
1113
1114 roce_set_field(req_a->vf_srqc_bt_idx_num,
1115 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1116 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1117 roce_set_field(req_a->vf_srqc_bt_idx_num,
1118 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1119 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1120 HNS_ROCE_VF_SRQC_BT_NUM);
1121
1122 roce_set_field(req_a->vf_cqc_bt_idx_num,
1123 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1124 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1125 roce_set_field(req_a->vf_cqc_bt_idx_num,
1126 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1127 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
1128 HNS_ROCE_VF_CQC_BT_NUM);
1129
1130 roce_set_field(req_a->vf_mpt_bt_idx_num,
1131 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1132 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1133 roce_set_field(req_a->vf_mpt_bt_idx_num,
1134 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1135 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
1136 HNS_ROCE_VF_MPT_BT_NUM);
1137
1138 roce_set_field(req_a->vf_eqc_bt_idx_num,
1139 VF_RES_A_DATA_5_VF_EQC_IDX_M,
1140 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1141 roce_set_field(req_a->vf_eqc_bt_idx_num,
1142 VF_RES_A_DATA_5_VF_EQC_NUM_M,
1143 VF_RES_A_DATA_5_VF_EQC_NUM_S,
1144 HNS_ROCE_VF_EQC_NUM);
1145 } else {
1146 roce_set_field(req_b->vf_smac_idx_num,
1147 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1148 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1149 roce_set_field(req_b->vf_smac_idx_num,
1150 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1151 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
1152 HNS_ROCE_VF_SMAC_NUM);
1153
1154 roce_set_field(req_b->vf_sgid_idx_num,
1155 VF_RES_B_DATA_2_VF_SGID_IDX_M,
1156 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1157 roce_set_field(req_b->vf_sgid_idx_num,
1158 VF_RES_B_DATA_2_VF_SGID_NUM_M,
1159 VF_RES_B_DATA_2_VF_SGID_NUM_S,
1160 HNS_ROCE_VF_SGID_NUM);
1161
1162 roce_set_field(req_b->vf_qid_idx_sl_num,
1163 VF_RES_B_DATA_3_VF_QID_IDX_M,
1164 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1165 roce_set_field(req_b->vf_qid_idx_sl_num,
1166 VF_RES_B_DATA_3_VF_SL_NUM_M,
1167 VF_RES_B_DATA_3_VF_SL_NUM_S,
1168 HNS_ROCE_VF_SL_NUM);
1169 }
1170 }
1171
1172 return hns_roce_cmq_send(hr_dev, desc, 2);
1173}
1174
a81fba28
WHX		 1175static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1176{
1177 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1178 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1179 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1180 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
1181 struct hns_roce_cfg_bt_attr *req;
1182 struct hns_roce_cmq_desc desc;
1183
1184 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1185 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1186 memset(req, 0, sizeof(*req));
1187
1188 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1189 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1190 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1191 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1192 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1193 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1194 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1195 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1196 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1197
1198 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1199 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1200 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1201 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1202 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1203 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1204 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1205 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1206 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1207
1208 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1209 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1210 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1211 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1212 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1213 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1214 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1215 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1216 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1217
1218 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1219 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1220 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1221 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1222 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1223 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1224 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1225 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1226 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1227
1228 return hns_roce_cmq_send(hr_dev, &desc, 1);
1229}
1230
cfc85f3e
WHX		 1231static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1232{
1233 struct hns_roce_caps *caps = &hr_dev->caps;
1234 int ret;
1235
1236 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 1237 if (ret) {
1238 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
1239 ret);
1240 return ret;
1241 }
1242
1243 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 1244 if (ret) {
1245 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1246 ret);
1247 return ret;
1248 }
1249
1250 ret = hns_roce_config_global_param(hr_dev);
1251 if (ret) {
1252 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1253 ret);
2349fdd4 1254 return ret;
cfc85f3e
WHX		 1255 }
1256
1257 /* Get pf resource owned by every pf */
1258 ret = hns_roce_query_pf_resource(hr_dev);
1259 if (ret) {
1260 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1261 ret);
1262 return ret;
1263 }
1264
1265 ret = hns_roce_alloc_vf_resource(hr_dev);
1266 if (ret) {
1267 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
1268 ret);
1269 return ret;
1270 }
1271
3a63c964
LO		 1272
1273 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
1274 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e
WHX		 1275
1276 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1277 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1278 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1279 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1280 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
05ad5482 1281 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
cfc85f3e
WHX		 1282 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1283 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1284 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1285 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
a5073d60
YL		 1286 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1287 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1288 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
cfc85f3e
WHX		 1289 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1290 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1291 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1292 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1293 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1294 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1295 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1296 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1297 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1298 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1299 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 1300 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e
WHX		 1301 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1302 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1303 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1304 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1305 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1306 caps->reserved_lkey = 0;
1307 caps->reserved_pds = 0;
1308 caps->reserved_mrws = 1;
1309 caps->reserved_uars = 0;
1310 caps->reserved_cqs = 0;
06ef0ee4 1311 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
cfc85f3e 1312
a25d13cb
SX		 1313 caps->qpc_ba_pg_sz = 0;
1314 caps->qpc_buf_pg_sz = 0;
1315 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1316 caps->srqc_ba_pg_sz = 0;
1317 caps->srqc_buf_pg_sz = 0;
1318 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
1319 caps->cqc_ba_pg_sz = 0;
1320 caps->cqc_buf_pg_sz = 0;
1321 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1322 caps->mpt_ba_pg_sz = 0;
1323 caps->mpt_buf_pg_sz = 0;
1324 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
ff795f71
WHX		 1325 caps->pbl_ba_pg_sz = 0;
1326 caps->pbl_buf_pg_sz = 0;
1327 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 1328 caps->mtt_ba_pg_sz = 0;
1329 caps->mtt_buf_pg_sz = 0;
1330 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1331 caps->cqe_ba_pg_sz = 0;
1332 caps->cqe_buf_pg_sz = 0;
1333 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
a5073d60
YL		 1334 caps->eqe_ba_pg_sz = 0;
1335 caps->eqe_buf_pg_sz = 0;
1336 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1337 caps->tsq_buf_pg_sz = 0;
29a1fe5d 1338 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 1339
023c1477 1340 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
0009c2db 1341 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
e088a685 1342 HNS_ROCE_CAP_FLAG_RQ_INLINE |
0425e3e6
YL		 1343 HNS_ROCE_CAP_FLAG_RECORD_DB |
1344 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
c7c28191
YL		 1345
1346 if (hr_dev->pci_dev->revision == 0x21)
68a997c5
YL		 1347 caps->flags |= HNS_ROCE_CAP_FLAG_MW |
1348 HNS_ROCE_CAP_FLAG_FRMR;
c7c28191 1349
cfc85f3e 1350 caps->pkey_table_len[0] = 1;
b5ff0f61 1351 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
a5073d60
YL		 1352 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1353 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
cfc85f3e
WHX		 1354 caps->local_ca_ack_delay = 0;
1355 caps->max_mtu = IB_MTU_4096;
1356
384f8818
LO		 1357 if (hr_dev->pci_dev->revision == 0x21)
1358 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC;
1359
a81fba28
WHX		 1360 ret = hns_roce_v2_set_bt(hr_dev);
1361 if (ret)
1362 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
1363 ret);
1364
1365 return ret;
cfc85f3e
WHX		 1366}
1367
6b63597d 1368static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
1369 enum hns_roce_link_table_type type)
1370{
1371 struct hns_roce_cmq_desc desc[2];
1372 struct hns_roce_cfg_llm_a *req_a =
1373 (struct hns_roce_cfg_llm_a *)desc[0].data;
1374 struct hns_roce_cfg_llm_b *req_b =
1375 (struct hns_roce_cfg_llm_b *)desc[1].data;
1376 struct hns_roce_v2_priv *priv = hr_dev->priv;
1377 struct hns_roce_link_table *link_tbl;
1378 struct hns_roce_link_table_entry *entry;
1379 enum hns_roce_opcode_type opcode;
1380 u32 page_num;
1381 int i;
1382
1383 switch (type) {
1384 case TSQ_LINK_TABLE:
1385 link_tbl = &priv->tsq;
1386 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
1387 break;
ded58ff9 1388 case TPQ_LINK_TABLE:
1389 link_tbl = &priv->tpq;
1390 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
1391 break;
6b63597d 1392 default:
1393 return -EINVAL;
1394 }
1395
1396 page_num = link_tbl->npages;
1397 entry = link_tbl->table.buf;
1398 memset(req_a, 0, sizeof(*req_a));
1399 memset(req_b, 0, sizeof(*req_b));
1400
1401 for (i = 0; i < 2; i++) {
1402 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
1403
1404 if (i == 0)
1405 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1406 else
1407 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1408
1409 if (i == 0) {
1410 req_a->base_addr_l = link_tbl->table.map & 0xffffffff;
1411 req_a->base_addr_h = (link_tbl->table.map >> 32) &
1412 0xffffffff;
1413 roce_set_field(req_a->depth_pgsz_init_en,
1414 CFG_LLM_QUE_DEPTH_M,
1415 CFG_LLM_QUE_DEPTH_S,
1416 link_tbl->npages);
1417 roce_set_field(req_a->depth_pgsz_init_en,
1418 CFG_LLM_QUE_PGSZ_M,
1419 CFG_LLM_QUE_PGSZ_S,
1420 link_tbl->pg_sz);
1421 req_a->head_ba_l = entry[0].blk_ba0;
1422 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr;
1423 roce_set_field(req_a->head_ptr,
1424 CFG_LLM_HEAD_PTR_M,
1425 CFG_LLM_HEAD_PTR_S, 0);
1426 } else {
1427 req_b->tail_ba_l = entry[page_num - 1].blk_ba0;
1428 roce_set_field(req_b->tail_ba_h,
1429 CFG_LLM_TAIL_BA_H_M,
1430 CFG_LLM_TAIL_BA_H_S,
1431 entry[page_num - 1].blk_ba1_nxt_ptr &
1432 HNS_ROCE_LINK_TABLE_BA1_M);
1433 roce_set_field(req_b->tail_ptr,
1434 CFG_LLM_TAIL_PTR_M,
1435 CFG_LLM_TAIL_PTR_S,
1436 (entry[page_num - 2].blk_ba1_nxt_ptr &
1437 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
1438 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
1439 }
1440 }
1441 roce_set_field(req_a->depth_pgsz_init_en,
1442 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1);
1443
1444 return hns_roce_cmq_send(hr_dev, desc, 2);
1445}
1446
1447static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
1448 enum hns_roce_link_table_type type)
1449{
1450 struct hns_roce_v2_priv *priv = hr_dev->priv;
1451 struct hns_roce_link_table *link_tbl;
1452 struct hns_roce_link_table_entry *entry;
1453 struct device *dev = hr_dev->dev;
1454 u32 buf_chk_sz;
1455 dma_addr_t t;
ded58ff9 1456 int func_num = 1;
6b63597d 1457 int pg_num_a;
1458 int pg_num_b;
1459 int pg_num;
1460 int size;
1461 int i;
1462
1463 switch (type) {
1464 case TSQ_LINK_TABLE:
1465 link_tbl = &priv->tsq;
1466 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
1467 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
1468 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
1469 break;
ded58ff9 1470 case TPQ_LINK_TABLE:
1471 link_tbl = &priv->tpq;
1472 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
1473 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
1474 pg_num_b = 2 * 4 * func_num + 2;
1475 break;
6b63597d 1476 default:
1477 return -EINVAL;
1478 }
1479
1480 pg_num = max(pg_num_a, pg_num_b);
1481 size = pg_num * sizeof(struct hns_roce_link_table_entry);
1482
1483 link_tbl->table.buf = dma_alloc_coherent(dev, size,
1484 &link_tbl->table.map,
1485 GFP_KERNEL);
1486 if (!link_tbl->table.buf)
1487 goto out;
1488
1489 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
1490 GFP_KERNEL);
1491 if (!link_tbl->pg_list)
1492 goto err_kcalloc_failed;
1493
1494 entry = link_tbl->table.buf;
1495 for (i = 0; i < pg_num; ++i) {
1496 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
1497 &t, GFP_KERNEL);
1498 if (!link_tbl->pg_list[i].buf)
1499 goto err_alloc_buf_failed;
1500
1501 link_tbl->pg_list[i].map = t;
1502 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz);
1503
1504 entry[i].blk_ba0 = (t >> 12) & 0xffffffff;
1505 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1506 HNS_ROCE_LINK_TABLE_BA1_M,
1507 HNS_ROCE_LINK_TABLE_BA1_S,
1508 t >> 44);
1509
1510 if (i < (pg_num - 1))
1511 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1512 HNS_ROCE_LINK_TABLE_NXT_PTR_M,
1513 HNS_ROCE_LINK_TABLE_NXT_PTR_S,
1514 i + 1);
1515 }
1516 link_tbl->npages = pg_num;
1517 link_tbl->pg_sz = buf_chk_sz;
1518
1519 return hns_roce_config_link_table(hr_dev, type);
1520
1521err_alloc_buf_failed:
1522 for (i -= 1; i >= 0; i--)
1523 dma_free_coherent(dev, buf_chk_sz,
1524 link_tbl->pg_list[i].buf,
1525 link_tbl->pg_list[i].map);
1526 kfree(link_tbl->pg_list);
1527
1528err_kcalloc_failed:
1529 dma_free_coherent(dev, size, link_tbl->table.buf,
1530 link_tbl->table.map);
1531
1532out:
1533 return -ENOMEM;
1534}
1535
1536static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
1537 struct hns_roce_link_table *link_tbl)
1538{
1539 struct device *dev = hr_dev->dev;
1540 int size;
1541 int i;
1542
1543 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
1544
1545 for (i = 0; i < link_tbl->npages; ++i)
1546 if (link_tbl->pg_list[i].buf)
1547 dma_free_coherent(dev, link_tbl->pg_sz,
1548 link_tbl->pg_list[i].buf,
1549 link_tbl->pg_list[i].map);
1550 kfree(link_tbl->pg_list);
1551
1552 dma_free_coherent(dev, size, link_tbl->table.buf,
1553 link_tbl->table.map);
1554}
1555
1556static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
1557{
ded58ff9 1558 struct hns_roce_v2_priv *priv = hr_dev->priv;
6b63597d 1559 int ret;
1560
1561 /* TSQ includes SQ doorbell and ack doorbell */
1562 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 1563 if (ret) {
6b63597d 1564 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 1565 return ret;
1566 }
1567
1568 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
1569 if (ret) {
1570 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
1571 goto err_tpq_init_failed;
1572 }
1573
1574 return 0;
1575
1576err_tpq_init_failed:
1577 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 1578
1579 return ret;
1580}
1581
1582static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
1583{
1584 struct hns_roce_v2_priv *priv = hr_dev->priv;
1585
ded58ff9 1586 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 1587 hns_roce_free_link_table(hr_dev, &priv->tsq);
1588}
1589
a680f2f3
WHX		 1590static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
1591{
1592 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1593
1594 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
1595}
1596
1597static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
1598{
1599 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1600
1601 return status & HNS_ROCE_HW_MB_STATUS_MASK;
1602}
1603
1604static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1605 u64 out_param, u32 in_modifier, u8 op_modifier,
1606 u16 op, u16 token, int event)
1607{
1608 struct device *dev = hr_dev->dev;
cc4ed08b
BVA		 1609 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base +
1610 ROCEE_VF_MB_CFG0_REG);
a680f2f3
WHX		 1611 unsigned long end;
1612 u32 val0 = 0;
1613 u32 val1 = 0;
1614
1615 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1616 while (hns_roce_v2_cmd_pending(hr_dev)) {
1617 if (time_after(jiffies, end)) {
1618 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1619 (int)end);
1620 return -EAGAIN;
1621 }
1622 cond_resched();
1623 }
1624
1625 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK,
1626 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier);
1627 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK,
1628 HNS_ROCE_VF_MB4_CMD_SHIFT, op);
1629 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK,
1630 HNS_ROCE_VF_MB5_EVENT_SHIFT, event);
1631 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK,
1632 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token);
1633
71591d12
AS		 1634 writeq(in_param, hcr + 0);
1635 writeq(out_param, hcr + 2);
a680f2f3
WHX		 1636
1637 /* Memory barrier */
1638 wmb();
1639
71591d12
AS		 1640 writel(val0, hcr + 4);
1641 writel(val1, hcr + 5);
a680f2f3
WHX		 1642
1643 mmiowb();
1644
1645 return 0;
1646}
1647
1648static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1649 unsigned long timeout)
1650{
1651 struct device *dev = hr_dev->dev;
1652 unsigned long end = 0;
1653 u32 status;
1654
1655 end = msecs_to_jiffies(timeout) + jiffies;
1656 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1657 cond_resched();
1658
1659 if (hns_roce_v2_cmd_pending(hr_dev)) {
1660 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1661 return -ETIMEDOUT;
1662 }
1663
1664 status = hns_roce_v2_cmd_complete(hr_dev);
1665 if (status != 0x1) {
1666 dev_err(dev, "mailbox status 0x%x!\n", status);
1667 return -EBUSY;
1668 }
1669
1670 return 0;
1671}
1672
4db134a3 1673static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
1674 int gid_index, const union ib_gid *gid,
1675 enum hns_roce_sgid_type sgid_type)
1676{
1677 struct hns_roce_cmq_desc desc;
1678 struct hns_roce_cfg_sgid_tb *sgid_tb =
1679 (struct hns_roce_cfg_sgid_tb *)desc.data;
1680 u32 *p;
1681
1682 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
1683
1684 roce_set_field(sgid_tb->table_idx_rsv,
1685 CFG_SGID_TB_TABLE_IDX_M,
1686 CFG_SGID_TB_TABLE_IDX_S, gid_index);
1687 roce_set_field(sgid_tb->vf_sgid_type_rsv,
1688 CFG_SGID_TB_VF_SGID_TYPE_M,
1689 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
1690
1691 p = (u32 *)&gid->raw[0];
1692 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
1693
1694 p = (u32 *)&gid->raw[4];
1695 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
1696
1697 p = (u32 *)&gid->raw[8];
1698 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
1699
1700 p = (u32 *)&gid->raw[0xc];
1701 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
1702
1703 return hns_roce_cmq_send(hr_dev, &desc, 1);
1704}
1705
b5ff0f61 1706static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 1707 int gid_index, const union ib_gid *gid,
b5ff0f61 1708 const struct ib_gid_attr *attr)
7afddafa 1709{
b5ff0f61 1710 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 1711 int ret;
7afddafa 1712
b5ff0f61
WHX		 1713 if (!gid || !attr)
1714 return -EINVAL;
1715
1716 if (attr->gid_type == IB_GID_TYPE_ROCE)
1717 sgid_type = GID_TYPE_FLAG_ROCE_V1;
1718
1719 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
1720 if (ipv6_addr_v4mapped((void *)gid))
1721 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
1722 else
1723 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
1724 }
1725
4db134a3 1726 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
1727 if (ret)
1728 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);
b5ff0f61 1729
4db134a3 1730 return ret;
7afddafa
WHX		 1731}
1732
a74dc41d
WHX		 1733static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1734 u8 *addr)
7afddafa 1735{
e8e8b652 1736 struct hns_roce_cmq_desc desc;
1737 struct hns_roce_cfg_smac_tb *smac_tb =
1738 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 1739 u16 reg_smac_h;
1740 u32 reg_smac_l;
e8e8b652 1741
1742 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 1743
1744 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 1745 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 1746
e8e8b652 1747 memset(smac_tb, 0, sizeof(*smac_tb));
1748 roce_set_field(smac_tb->tb_idx_rsv,
1749 CFG_SMAC_TB_IDX_M,
1750 CFG_SMAC_TB_IDX_S, phy_port);
1751 roce_set_field(smac_tb->vf_smac_h_rsv,
1752 CFG_SMAC_TB_VF_SMAC_H_M,
1753 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
1754 smac_tb->vf_smac_l = reg_smac_l;
a74dc41d 1755
e8e8b652 1756 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 1757}
1758
3958cc56
WHX		 1759static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1760 unsigned long mtpt_idx)
1761{
1762 struct hns_roce_v2_mpt_entry *mpt_entry;
1763 struct scatterlist *sg;
db270c41 1764 u64 page_addr;
3958cc56 1765 u64 *pages;
db270c41
WHX		 1766 int i, j;
1767 int len;
3958cc56 1768 int entry;
3958cc56
WHX		 1769
1770 mpt_entry = mb_buf;
1771 memset(mpt_entry, 0, sizeof(*mpt_entry));
1772
1773 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1774 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
1775 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1776 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
1777 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
1778 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1779 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 1780 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1781 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1782 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1783 V2_MPT_BYTE_4_PD_S, mr->pd);
1784 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
1785
1786 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
1787 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
e93df010 1788 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 1789 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
1790 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 1791 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
1792 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 1793 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1794 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1795 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1796 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1797 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1798 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1799 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
1800
1801 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
1802 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 1803 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
1804 1);
3958cc56
WHX		 1805 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
1806
1807 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
1808 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
1809 mpt_entry->lkey = cpu_to_le32(mr->key);
1810 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
1811 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
1812
1813 if (mr->type == MR_TYPE_DMA)
1814 return 0;
1815
1816 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1817
1818 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1819 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1820 V2_MPT_BYTE_48_PBL_BA_H_S,
1821 upper_32_bits(mr->pbl_ba >> 3));
1822 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
1823
1824 pages = (u64 *)__get_free_page(GFP_KERNEL);
1825 if (!pages)
1826 return -ENOMEM;
1827
1828 i = 0;
1829 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
db270c41
WHX		 1830 len = sg_dma_len(sg) >> PAGE_SHIFT;
1831 for (j = 0; j < len; ++j) {
1832 page_addr = sg_dma_address(sg) +
1833 (j << mr->umem->page_shift);
1834 pages[i] = page_addr >> 6;
1835
1836 /* Record the first 2 entry directly to MTPT table */
1837 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1838 goto found;
1839 i++;
1840 }
3958cc56
WHX		 1841 }
1842
db270c41 1843found:
3958cc56
WHX		 1844 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1845 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1846 V2_MPT_BYTE_56_PA0_H_S,
1847 upper_32_bits(pages[0]));
1848 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
1849
1850 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
1851 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
1852 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
1853
1854 free_page((unsigned long)pages);
1855
1856 roce_set_field(mpt_entry->byte_64_buf_pa1,
1857 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
5e6e78db
YL		 1858 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1859 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1860 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
1861
1862 return 0;
1863}
1864
a2c80b7b
WHX		 1865static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
1866 struct hns_roce_mr *mr, int flags,
1867 u32 pdn, int mr_access_flags, u64 iova,
1868 u64 size, void *mb_buf)
1869{
1870 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
1871
1872 if (flags & IB_MR_REREG_PD) {
1873 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1874 V2_MPT_BYTE_4_PD_S, pdn);
1875 mr->pd = pdn;
1876 }
1877
1878 if (flags & IB_MR_REREG_ACCESS) {
1879 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1880 V2_MPT_BYTE_8_BIND_EN_S,
1881 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
1882 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1883 V2_MPT_BYTE_8_ATOMIC_EN_S,
1884 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
1885 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1886 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
1887 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1888 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1889 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1890 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1891 }
1892
1893 if (flags & IB_MR_REREG_TRANS) {
1894 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
1895 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
1896 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
1897 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
1898
1899 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1900 mpt_entry->pbl_ba_l =
1901 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1902 roce_set_field(mpt_entry->byte_48_mode_ba,
1903 V2_MPT_BYTE_48_PBL_BA_H_M,
1904 V2_MPT_BYTE_48_PBL_BA_H_S,
1905 upper_32_bits(mr->pbl_ba >> 3));
1906 mpt_entry->byte_48_mode_ba =
1907 cpu_to_le32(mpt_entry->byte_48_mode_ba);
1908
1909 mr->iova = iova;
1910 mr->size = size;
1911 }
1912
1913 return 0;
1914}
1915
68a997c5
YL		 1916static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
1917{
1918 struct hns_roce_v2_mpt_entry *mpt_entry;
1919
1920 mpt_entry = mb_buf;
1921 memset(mpt_entry, 0, sizeof(*mpt_entry));
1922
1923 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1924 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
1925 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1926 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
1927 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1928 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1929 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1930 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
1931 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1932 V2_MPT_BYTE_4_PD_S, mr->pd);
1933
1934 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
1935 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1936 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
1937
1938 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
1939 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
1940 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
1941 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
1942
1943 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1944
1945 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1946 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1947 V2_MPT_BYTE_48_PBL_BA_H_S,
1948 upper_32_bits(mr->pbl_ba >> 3));
1949
1950 roce_set_field(mpt_entry->byte_64_buf_pa1,
1951 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
1952 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1953 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
1954
1955 return 0;
1956}
1957
c7c28191
YL		 1958static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
1959{
1960 struct hns_roce_v2_mpt_entry *mpt_entry;
1961
1962 mpt_entry = mb_buf;
1963 memset(mpt_entry, 0, sizeof(*mpt_entry));
1964
1965 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1966 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
1967 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1968 V2_MPT_BYTE_4_PD_S, mw->pdn);
1969 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1970 V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1971 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
1972 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ?
1973 0 : mw->pbl_hop_num);
1974 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1975 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1976 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1977 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
1978
1979 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1980 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
1981
1982 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
1983 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
1984 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
1985 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
1986 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
1987
1988 roce_set_field(mpt_entry->byte_64_buf_pa1,
1989 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
1990 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1991 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
1992
1993 mpt_entry->lkey = cpu_to_le32(mw->rkey);
1994
1995 return 0;
1996}
1997
93aa2187
WHX		 1998static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1999{
2000 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2001 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
2002}
2003
2004static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2005{
2006 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2007
2008 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2009 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
2010 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
2011}
2012
2013static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
2014{
2015 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
2016}
2017
2018static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2019{
86188a88 2020 *hr_cq->set_ci_db = cons_index & 0xffffff;
93aa2187
WHX		 2021}
2022
926a01dc
WHX		 2023static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2024 struct hns_roce_srq *srq)
2025{
2026 struct hns_roce_v2_cqe *cqe, *dest;
2027 u32 prod_index;
2028 int nfreed = 0;
2029 u8 owner_bit;
2030
2031 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2032 ++prod_index) {
2033 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2034 break;
2035 }
2036
2037 /*
2038 * Now backwards through the CQ, removing CQ entries
2039 * that match our QP by overwriting them with next entries.
2040 */
2041 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2042 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2043 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2044 V2_CQE_BYTE_16_LCL_QPN_S) &
2045 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
2046 /* In v1 engine, not support SRQ */
2047 ++nfreed;
2048 } else if (nfreed) {
2049 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2050 hr_cq->ib_cq.cqe);
2051 owner_bit = roce_get_bit(dest->byte_4,
2052 V2_CQE_BYTE_4_OWNER_S);
2053 memcpy(dest, cqe, sizeof(*cqe));
2054 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2055 owner_bit);
2056 }
2057 }
2058
2059 if (nfreed) {
2060 hr_cq->cons_index += nfreed;
2061 /*
2062 * Make sure update of buffer contents is done before
2063 * updating consumer index.
2064 */
2065 wmb();
2066 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2067 }
2068}
2069
2070static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2071 struct hns_roce_srq *srq)
2072{
2073 spin_lock_irq(&hr_cq->lock);
2074 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2075 spin_unlock_irq(&hr_cq->lock);
2076}
2077
93aa2187
WHX		 2078static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2079 struct hns_roce_cq *hr_cq, void *mb_buf,
2080 u64 *mtts, dma_addr_t dma_handle, int nent,
2081 u32 vector)
2082{
2083 struct hns_roce_v2_cq_context *cq_context;
2084
2085 cq_context = mb_buf;
2086 memset(cq_context, 0, sizeof(*cq_context));
2087
2088 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2089 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2090 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2091 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187
WHX		 2092 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
2093 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
2094 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
2095 V2_CQC_BYTE_4_CEQN_S, vector);
2096 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
2097
2098 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2099 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2100
2101 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2102 cq_context->cqe_cur_blk_addr =
2103 cpu_to_le32(cq_context->cqe_cur_blk_addr);
2104
2105 roce_set_field(cq_context->byte_16_hop_addr,
2106 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2107 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
2108 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
2109 roce_set_field(cq_context->byte_16_hop_addr,
2110 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2111 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2112 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2113
2114 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
2115 roce_set_field(cq_context->byte_24_pgsz_addr,
2116 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2117 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
2118 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
2119 roce_set_field(cq_context->byte_24_pgsz_addr,
2120 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2121 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 2122 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2123 roce_set_field(cq_context->byte_24_pgsz_addr,
2124 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2125 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 2126 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2127
2128 cq_context->cqe_ba = (u32)(dma_handle >> 3);
2129
2130 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2131 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2132
9b44703d
YL		 2133 if (hr_cq->db_en)
2134 roce_set_bit(cq_context->byte_44_db_record,
2135 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
2136
2137 roce_set_field(cq_context->byte_44_db_record,
2138 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2139 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2140 ((u32)hr_cq->db.dma) >> 1);
2141 cq_context->db_record_addr = hr_cq->db.dma >> 32;
2142
a5073d60
YL		 2143 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2144 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2145 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2146 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2147 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2148 V2_CQC_BYTE_56_CQ_PERIOD_M,
2149 V2_CQC_BYTE_56_CQ_PERIOD_S,
2150 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2151}
2152
2153static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2154 enum ib_cq_notify_flags flags)
2155{
2156 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2157 u32 notification_flag;
2158 u32 doorbell[2];
2159
2160 doorbell[0] = 0;
2161 doorbell[1] = 0;
2162
2163 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2164 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2165 /*
2166 * flags = 0; Notification Flag = 1, next
2167 * flags = 1; Notification Flag = 0, solocited
2168 */
2169 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2170 hr_cq->cqn);
2171 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2172 HNS_ROCE_V2_CQ_DB_NTR);
2173 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2174 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2175 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2176 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2177 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2178 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2179 notification_flag);
2180
2181 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2182
2183 return 0;
2184}
2185
0009c2db 2186static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2187 struct hns_roce_qp **cur_qp,
2188 struct ib_wc *wc)
2189{
2190 struct hns_roce_rinl_sge *sge_list;
2191 u32 wr_num, wr_cnt, sge_num;
2192 u32 sge_cnt, data_len, size;
2193 void *wqe_buf;
2194
2195 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2196 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2197 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2198
2199 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2200 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
2201 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt);
2202 data_len = wc->byte_len;
2203
2204 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2205 size = min(sge_list[sge_cnt].len, data_len);
2206 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2207
2208 data_len -= size;
2209 wqe_buf += size;
2210 }
2211
2212 if (data_len) {
2213 wc->status = IB_WC_LOC_LEN_ERR;
2214 return -EAGAIN;
2215 }
2216
2217 return 0;
2218}
2219
93aa2187
WHX		 2220static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2221 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2222{
2223 struct hns_roce_dev *hr_dev;
2224 struct hns_roce_v2_cqe *cqe;
2225 struct hns_roce_qp *hr_qp;
2226 struct hns_roce_wq *wq;
0425e3e6
YL		 2227 struct ib_qp_attr attr;
2228 int attr_mask;
93aa2187
WHX		 2229 int is_send;
2230 u16 wqe_ctr;
2231 u32 opcode;
2232 u32 status;
2233 int qpn;
0009c2db 2234 int ret;
93aa2187
WHX		 2235
2236 /* Find cqe according to consumer index */
2237 cqe = next_cqe_sw_v2(hr_cq);
2238 if (!cqe)
2239 return -EAGAIN;
2240
2241 ++hr_cq->cons_index;
2242 /* Memory barrier */
2243 rmb();
2244
2245 /* 0->SQ, 1->RQ */
2246 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2247
2248 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2249 V2_CQE_BYTE_16_LCL_QPN_S);
2250
2251 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2252 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2253 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2254 if (unlikely(!hr_qp)) {
2255 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
2256 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
2257 return -EINVAL;
2258 }
2259 *cur_qp = hr_qp;
2260 }
2261
2262 wc->qp = &(*cur_qp)->ibqp;
2263 wc->vendor_err = 0;
2264
2265 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
2266 V2_CQE_BYTE_4_STATUS_S);
2267 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
2268 case HNS_ROCE_CQE_V2_SUCCESS:
2269 wc->status = IB_WC_SUCCESS;
2270 break;
2271 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
2272 wc->status = IB_WC_LOC_LEN_ERR;
2273 break;
2274 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
2275 wc->status = IB_WC_LOC_QP_OP_ERR;
2276 break;
2277 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
2278 wc->status = IB_WC_LOC_PROT_ERR;
2279 break;
2280 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
2281 wc->status = IB_WC_WR_FLUSH_ERR;
2282 break;
2283 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
2284 wc->status = IB_WC_MW_BIND_ERR;
2285 break;
2286 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
2287 wc->status = IB_WC_BAD_RESP_ERR;
2288 break;
2289 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
2290 wc->status = IB_WC_LOC_ACCESS_ERR;
2291 break;
2292 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
2293 wc->status = IB_WC_REM_INV_REQ_ERR;
2294 break;
2295 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
2296 wc->status = IB_WC_REM_ACCESS_ERR;
2297 break;
2298 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
2299 wc->status = IB_WC_REM_OP_ERR;
2300 break;
2301 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
2302 wc->status = IB_WC_RETRY_EXC_ERR;
2303 break;
2304 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
2305 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2306 break;
2307 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
2308 wc->status = IB_WC_REM_ABORT_ERR;
2309 break;
2310 default:
2311 wc->status = IB_WC_GENERAL_ERR;
2312 break;
2313 }
2314
0425e3e6
YL		 2315 /* flush cqe if wc status is error, excluding flush error */
2316 if ((wc->status != IB_WC_SUCCESS) &&
2317 (wc->status != IB_WC_WR_FLUSH_ERR)) {
2318 attr_mask = IB_QP_STATE;
2319 attr.qp_state = IB_QPS_ERR;
2320 return hns_roce_v2_modify_qp(&(*cur_qp)->ibqp,
2321 &attr, attr_mask,
2322 (*cur_qp)->state, IB_QPS_ERR);
2323 }
2324
2325 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 2326 return 0;
2327
2328 if (is_send) {
2329 wc->wc_flags = 0;
2330 /* SQ corresponding to CQE */
2331 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2332 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
2333 case HNS_ROCE_SQ_OPCODE_SEND:
2334 wc->opcode = IB_WC_SEND;
2335 break;
2336 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
2337 wc->opcode = IB_WC_SEND;
2338 break;
2339 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
2340 wc->opcode = IB_WC_SEND;
2341 wc->wc_flags |= IB_WC_WITH_IMM;
2342 break;
2343 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
2344 wc->opcode = IB_WC_RDMA_READ;
2345 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2346 break;
2347 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
2348 wc->opcode = IB_WC_RDMA_WRITE;
2349 break;
2350 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
2351 wc->opcode = IB_WC_RDMA_WRITE;
2352 wc->wc_flags |= IB_WC_WITH_IMM;
2353 break;
2354 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
2355 wc->opcode = IB_WC_LOCAL_INV;
2356 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2357 break;
2358 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
2359 wc->opcode = IB_WC_COMP_SWAP;
2360 wc->byte_len = 8;
2361 break;
2362 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
2363 wc->opcode = IB_WC_FETCH_ADD;
2364 wc->byte_len = 8;
2365 break;
2366 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
2367 wc->opcode = IB_WC_MASKED_COMP_SWAP;
2368 wc->byte_len = 8;
2369 break;
2370 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
2371 wc->opcode = IB_WC_MASKED_FETCH_ADD;
2372 wc->byte_len = 8;
2373 break;
2374 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
2375 wc->opcode = IB_WC_REG_MR;
2376 break;
2377 case HNS_ROCE_SQ_OPCODE_BIND_MW:
2378 wc->opcode = IB_WC_REG_MR;
2379 break;
2380 default:
2381 wc->status = IB_WC_GENERAL_ERR;
2382 break;
2383 }
2384
2385 wq = &(*cur_qp)->sq;
2386 if ((*cur_qp)->sq_signal_bits) {
2387 /*
2388 * If sg_signal_bit is 1,
2389 * firstly tail pointer updated to wqe
2390 * which current cqe correspond to
2391 */
2392 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
2393 V2_CQE_BYTE_4_WQE_INDX_M,
2394 V2_CQE_BYTE_4_WQE_INDX_S);
2395 wq->tail += (wqe_ctr - (u16)wq->tail) &
2396 (wq->wqe_cnt - 1);
2397 }
2398
2399 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2400 ++wq->tail;
2401 } else {
2402 /* RQ correspond to CQE */
2403 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2404
2405 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2406 V2_CQE_BYTE_4_OPCODE_S);
2407 switch (opcode & 0x1f) {
2408 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
2409 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2410 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2411 wc->ex.imm_data =
2412 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2413 break;
2414 case HNS_ROCE_V2_OPCODE_SEND:
2415 wc->opcode = IB_WC_RECV;
2416 wc->wc_flags = 0;
2417 break;
2418 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
2419 wc->opcode = IB_WC_RECV;
2420 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2421 wc->ex.imm_data =
2422 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2423 break;
2424 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
2425 wc->opcode = IB_WC_RECV;
2426 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 2427 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 2428 break;
2429 default:
2430 wc->status = IB_WC_GENERAL_ERR;
2431 break;
2432 }
2433
0009c2db 2434 if ((wc->qp->qp_type == IB_QPT_RC ||
2435 wc->qp->qp_type == IB_QPT_UC) &&
2436 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
2437 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
2438 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
2439 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
2440 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
2441 if (ret)
2442 return -EAGAIN;
2443 }
2444
93aa2187
WHX		 2445 /* Update tail pointer, record wr_id */
2446 wq = &(*cur_qp)->rq;
2447 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2448 ++wq->tail;
2449
2450 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
2451 V2_CQE_BYTE_32_SL_S);
2452 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
2453 V2_CQE_BYTE_32_RMT_QPN_M,
2454 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 2455 wc->slid = 0;
93aa2187
WHX		 2456 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
2457 V2_CQE_BYTE_32_GRH_S) ?
2458 IB_WC_GRH : 0);
6c1f08b3 2459 wc->port_num = roce_get_field(cqe->byte_32,
2460 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
2461 wc->pkey_index = 0;
2eade675 2462 memcpy(wc->smac, cqe->smac, 4);
2463 wc->smac[4] = roce_get_field(cqe->byte_28,
2464 V2_CQE_BYTE_28_SMAC_4_M,
2465 V2_CQE_BYTE_28_SMAC_4_S);
2466 wc->smac[5] = roce_get_field(cqe->byte_28,
2467 V2_CQE_BYTE_28_SMAC_5_M,
2468 V2_CQE_BYTE_28_SMAC_5_S);
944e6409
LO		 2469 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
2470 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
2471 V2_CQE_BYTE_28_VID_M,
2472 V2_CQE_BYTE_28_VID_S);
2473 } else {
2474 wc->vlan_id = 0xffff;
2475 }
2476
2eade675 2477 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
2478 wc->network_hdr_type = roce_get_field(cqe->byte_28,
2479 V2_CQE_BYTE_28_PORT_TYPE_M,
2480 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 2481 }
2482
2483 return 0;
2484}
2485
2486static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
2487 struct ib_wc *wc)
2488{
2489 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2490 struct hns_roce_qp *cur_qp = NULL;
2491 unsigned long flags;
2492 int npolled;
2493
2494 spin_lock_irqsave(&hr_cq->lock, flags);
2495
2496 for (npolled = 0; npolled < num_entries; ++npolled) {
2497 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
2498 break;
2499 }
2500
2501 if (npolled) {
2502 /* Memory barrier */
2503 wmb();
2504 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2505 }
2506
2507 spin_unlock_irqrestore(&hr_cq->lock, flags);
2508
2509 return npolled;
2510}
2511
a81fba28
WHX		 2512static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
2513 struct hns_roce_hem_table *table, int obj,
2514 int step_idx)
2515{
2516 struct device *dev = hr_dev->dev;
2517 struct hns_roce_cmd_mailbox *mailbox;
2518 struct hns_roce_hem_iter iter;
2519 struct hns_roce_hem_mhop mhop;
2520 struct hns_roce_hem *hem;
2521 unsigned long mhop_obj = obj;
2522 int i, j, k;
2523 int ret = 0;
2524 u64 hem_idx = 0;
2525 u64 l1_idx = 0;
2526 u64 bt_ba = 0;
2527 u32 chunk_ba_num;
2528 u32 hop_num;
2529 u16 op = 0xff;
2530
2531 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2532 return 0;
2533
2534 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
2535 i = mhop.l0_idx;
2536 j = mhop.l1_idx;
2537 k = mhop.l2_idx;
2538 hop_num = mhop.hop_num;
2539 chunk_ba_num = mhop.bt_chunk_size / 8;
2540
2541 if (hop_num == 2) {
2542 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
2543 k;
2544 l1_idx = i * chunk_ba_num + j;
2545 } else if (hop_num == 1) {
2546 hem_idx = i * chunk_ba_num + j;
2547 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
2548 hem_idx = i;
2549 }
2550
2551 switch (table->type) {
2552 case HEM_TYPE_QPC:
2553 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
2554 break;
2555 case HEM_TYPE_MTPT:
2556 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
2557 break;
2558 case HEM_TYPE_CQC:
2559 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
2560 break;
2561 case HEM_TYPE_SRQC:
2562 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
2563 break;
2564 default:
2565 dev_warn(dev, "Table %d not to be written by mailbox!\n",
2566 table->type);
2567 return 0;
2568 }
2569 op += step_idx;
2570
2571 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2572 if (IS_ERR(mailbox))
2573 return PTR_ERR(mailbox);
2574
2575 if (check_whether_last_step(hop_num, step_idx)) {
2576 hem = table->hem[hem_idx];
2577 for (hns_roce_hem_first(hem, &iter);
2578 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
2579 bt_ba = hns_roce_hem_addr(&iter);
2580
2581 /* configure the ba, tag, and op */
2582 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
2583 obj, 0, op,
2584 HNS_ROCE_CMD_TIMEOUT_MSECS);
2585 }
2586 } else {
2587 if (step_idx == 0)
2588 bt_ba = table->bt_l0_dma_addr[i];
2589 else if (step_idx == 1 && hop_num == 2)
2590 bt_ba = table->bt_l1_dma_addr[l1_idx];
2591
2592 /* configure the ba, tag, and op */
2593 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
2594 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
2595 }
2596
2597 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2598 return ret;
2599}
2600
2601static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
2602 struct hns_roce_hem_table *table, int obj,
2603 int step_idx)
2604{
2605 struct device *dev = hr_dev->dev;
2606 struct hns_roce_cmd_mailbox *mailbox;
2607 int ret = 0;
2608 u16 op = 0xff;
2609
2610 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2611 return 0;
2612
2613 switch (table->type) {
2614 case HEM_TYPE_QPC:
2615 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
2616 break;
2617 case HEM_TYPE_MTPT:
2618 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
2619 break;
2620 case HEM_TYPE_CQC:
2621 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
2622 break;
2623 case HEM_TYPE_SRQC:
2624 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
2625 break;
2626 default:
2627 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
2628 table->type);
2629 return 0;
2630 }
2631 op += step_idx;
2632
2633 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2634 if (IS_ERR(mailbox))
2635 return PTR_ERR(mailbox);
2636
2637 /* configure the tag and op */
2638 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
2639 HNS_ROCE_CMD_TIMEOUT_MSECS);
2640
2641 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2642 return ret;
2643}
2644
926a01dc
WHX		 2645static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
2646 struct hns_roce_mtt *mtt,
2647 enum ib_qp_state cur_state,
2648 enum ib_qp_state new_state,
2649 struct hns_roce_v2_qp_context *context,
2650 struct hns_roce_qp *hr_qp)
2651{
2652 struct hns_roce_cmd_mailbox *mailbox;
2653 int ret;
2654
2655 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2656 if (IS_ERR(mailbox))
2657 return PTR_ERR(mailbox);
2658
2659 memcpy(mailbox->buf, context, sizeof(*context) * 2);
2660
2661 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2662 HNS_ROCE_CMD_MODIFY_QPC,
2663 HNS_ROCE_CMD_TIMEOUT_MSECS);
2664
2665 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2666
2667 return ret;
2668}
2669
ace1c541 2670static void set_access_flags(struct hns_roce_qp *hr_qp,
2671 struct hns_roce_v2_qp_context *context,
2672 struct hns_roce_v2_qp_context *qpc_mask,
2673 const struct ib_qp_attr *attr, int attr_mask)
2674{
2675 u8 dest_rd_atomic;
2676 u32 access_flags;
2677
c2799119 2678 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 2679 attr->max_dest_rd_atomic : hr_qp->resp_depth;
2680
c2799119 2681 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 2682 attr->qp_access_flags : hr_qp->atomic_rd_en;
2683
2684 if (!dest_rd_atomic)
2685 access_flags &= IB_ACCESS_REMOTE_WRITE;
2686
2687 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2688 !!(access_flags & IB_ACCESS_REMOTE_READ));
2689 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
2690
2691 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2692 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
2693 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
2694
2695 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2696 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
2697 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
2698}
2699
926a01dc
WHX		 2700static void modify_qp_reset_to_init(struct ib_qp *ibqp,
2701 const struct ib_qp_attr *attr,
0fa95a9a 2702 int attr_mask,
926a01dc
WHX		 2703 struct hns_roce_v2_qp_context *context,
2704 struct hns_roce_v2_qp_context *qpc_mask)
2705{
ecaaf1e2 2706 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 2707 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2708
2709 /*
2710 * In v2 engine, software pass context and context mask to hardware
2711 * when modifying qp. If software need modify some fields in context,
2712 * we should set all bits of the relevant fields in context mask to
2713 * 0 at the same time, else set them to 0x1.
2714 */
2715 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2716 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2717 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2718 V2_QPC_BYTE_4_TST_S, 0);
2719
0fa95a9a 2720 if (ibqp->qp_type == IB_QPT_GSI)
2721 roce_set_field(context->byte_4_sqpn_tst,
2722 V2_QPC_BYTE_4_SGE_SHIFT_M,
2723 V2_QPC_BYTE_4_SGE_SHIFT_S,
2724 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2725 else
2726 roce_set_field(context->byte_4_sqpn_tst,
2727 V2_QPC_BYTE_4_SGE_SHIFT_M,
2728 V2_QPC_BYTE_4_SGE_SHIFT_S,
2729 hr_qp->sq.max_gs > 2 ?
2730 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2731
926a01dc
WHX		 2732 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2733 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2734
2735 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2736 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2737 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2738 V2_QPC_BYTE_4_SQPN_S, 0);
2739
2740 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2741 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2742 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2743 V2_QPC_BYTE_16_PD_S, 0);
2744
2745 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2746 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
2747 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2748 V2_QPC_BYTE_20_RQWS_S, 0);
2749
2750 roce_set_field(context->byte_20_smac_sgid_idx,
2751 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2752 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2753 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2754 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2755
2756 roce_set_field(context->byte_20_smac_sgid_idx,
2757 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2758 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2759 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2760 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2761
2762 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 2763 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2764 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
2765 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2766 V2_QPC_BYTE_24_VLAN_ID_S, 0);
926a01dc
WHX		 2767
2768 /*
2769 * Set some fields in context to zero, Because the default values
2770 * of all fields in context are zero, we need not set them to 0 again.
2771 * but we should set the relevant fields of context mask to 0.
2772 */
2773 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
2774 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
2775 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
2776 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
2777
2362ccee
LO		 2778 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_TEMPID_M,
2779 V2_QPC_BYTE_60_TEMPID_S, 0);
2780
2781 roce_set_field(qpc_mask->byte_60_qpst_tempid,
2782 V2_QPC_BYTE_60_SCC_TOKEN_M, V2_QPC_BYTE_60_SCC_TOKEN_S,
2783 0);
2784 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2785 V2_QPC_BYTE_60_SQ_DB_DOING_S, 0);
2786 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2787 V2_QPC_BYTE_60_RQ_DB_DOING_S, 0);
926a01dc
WHX		 2788 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
2789 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
2790
0fa95a9a 2791 if (attr_mask & IB_QP_QKEY) {
2792 context->qkey_xrcd = attr->qkey;
2793 qpc_mask->qkey_xrcd = 0;
2794 hr_qp->qkey = attr->qkey;
2795 }
2796
e088a685
YL		 2797 if (hr_qp->rdb_en) {
2798 roce_set_bit(context->byte_68_rq_db,
2799 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
2800 roce_set_bit(qpc_mask->byte_68_rq_db,
2801 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0);
2802 }
2803
2804 roce_set_field(context->byte_68_rq_db,
2805 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2806 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
2807 ((u32)hr_qp->rdb.dma) >> 1);
2808 roce_set_field(qpc_mask->byte_68_rq_db,
2809 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2810 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0);
2811 context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
2812 qpc_mask->rq_db_record_addr = 0;
2813
ecaaf1e2 2814 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
2815 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 2816 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
2817
2818 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2819 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2820 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2821 V2_QPC_BYTE_80_RX_CQN_S, 0);
2822 if (ibqp->srq) {
2823 roce_set_field(context->byte_76_srqn_op_en,
2824 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2825 to_hr_srq(ibqp->srq)->srqn);
2826 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2827 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2828 roce_set_bit(context->byte_76_srqn_op_en,
2829 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2830 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2831 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2832 }
2833
2834 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2835 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2836 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
2837 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2838 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
2839 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
2840
2841 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
2842 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
2843
2844 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
2845 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
2846
2847 roce_set_field(qpc_mask->byte_104_rq_sge,
2848 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
2849 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
2850
2851 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2852 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
2853 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2854 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
2855 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
2856 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2857 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
2858
2859 qpc_mask->rq_rnr_timer = 0;
2860 qpc_mask->rx_msg_len = 0;
2861 qpc_mask->rx_rkey_pkt_info = 0;
2862 qpc_mask->rx_va = 0;
2863
2864 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2865 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2866 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2867 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2868
2362ccee
LO		 2869 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S,
2870 0);
926a01dc
WHX		 2871 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
2872 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
2873 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
2874 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
2875
2876 roce_set_field(qpc_mask->byte_144_raq,
2877 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
2878 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
926a01dc
WHX		 2879 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
2880 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
2881 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
2882
2883 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
2884 V2_QPC_BYTE_148_RQ_MSN_S, 0);
2885 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
2886 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
2887
2888 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2889 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2890 roce_set_field(qpc_mask->byte_152_raq,
2891 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
2892 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
2893
2894 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
2895 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
2896
2897 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2898 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
2899 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
2900 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2901 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
2902 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
2903
2362ccee
LO		 2904 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2905 V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S, 0);
2906 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2907 V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S, 0);
2908 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2909 V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S, 0);
926a01dc
WHX		 2910 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2911 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 2912 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2913 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 2914 roce_set_field(qpc_mask->byte_168_irrl_idx,
2915 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
2916 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
2917
2918 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2919 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
2920 roce_set_field(qpc_mask->byte_172_sq_psn,
2921 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2922 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
2923
2924 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
2925 0);
2926
68a997c5
YL		 2927 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
2928 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 0);
2929
926a01dc
WHX		 2930 roce_set_field(qpc_mask->byte_176_msg_pktn,
2931 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
2932 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
2933 roce_set_field(qpc_mask->byte_176_msg_pktn,
2934 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
2935 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
2936
2937 roce_set_field(qpc_mask->byte_184_irrl_idx,
2938 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
2939 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
2940
2941 qpc_mask->cur_sge_offset = 0;
2942
2943 roce_set_field(qpc_mask->byte_192_ext_sge,
2944 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
2945 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
2946 roce_set_field(qpc_mask->byte_192_ext_sge,
2947 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
2948 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
2949
2950 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2951 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2952
2953 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
2954 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
2955 roce_set_field(qpc_mask->byte_200_sq_max,
2956 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
2957 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
2958
2959 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
2960 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
2961
2962 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2963 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2964
2965 qpc_mask->sq_timer = 0;
2966
2967 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2968 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2969 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2970 roce_set_field(qpc_mask->byte_232_irrl_sge,
2971 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2972 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2973
2362ccee
LO		 2974 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_SO_LP_VLD_S,
2975 0);
2976 roce_set_bit(qpc_mask->byte_232_irrl_sge,
2977 V2_QPC_BYTE_232_FENCE_LP_VLD_S, 0);
2978 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_IRRL_LP_VLD_S,
2979 0);
2980
926a01dc
WHX		 2981 qpc_mask->irrl_cur_sge_offset = 0;
2982
2983 roce_set_field(qpc_mask->byte_240_irrl_tail,
2984 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2985 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2986 roce_set_field(qpc_mask->byte_240_irrl_tail,
2987 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
2988 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
2989 roce_set_field(qpc_mask->byte_240_irrl_tail,
2990 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2991 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2992
2993 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
2994 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2995 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
2996 0);
2997 roce_set_field(qpc_mask->byte_248_ack_psn,
2998 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2999 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3000 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
3001 0);
3002 roce_set_bit(qpc_mask->byte_248_ack_psn,
3003 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3004 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
3005 0);
3006
3007 hr_qp->access_flags = attr->qp_access_flags;
3008 hr_qp->pkey_index = attr->pkey_index;
3009 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3010 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
3011 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3012 V2_QPC_BYTE_252_TX_CQN_S, 0);
3013
3014 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
3015 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
3016
3017 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3018 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
3019 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
3020 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3021 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
3022 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
3023}
3024
3025static void modify_qp_init_to_init(struct ib_qp *ibqp,
3026 const struct ib_qp_attr *attr, int attr_mask,
3027 struct hns_roce_v2_qp_context *context,
3028 struct hns_roce_v2_qp_context *qpc_mask)
3029{
3030 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3031
3032 /*
3033 * In v2 engine, software pass context and context mask to hardware
3034 * when modifying qp. If software need modify some fields in context,
3035 * we should set all bits of the relevant fields in context mask to
3036 * 0 at the same time, else set them to 0x1.
3037 */
3038 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3039 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3040 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3041 V2_QPC_BYTE_4_TST_S, 0);
3042
0fa95a9a 3043 if (ibqp->qp_type == IB_QPT_GSI)
3044 roce_set_field(context->byte_4_sqpn_tst,
3045 V2_QPC_BYTE_4_SGE_SHIFT_M,
3046 V2_QPC_BYTE_4_SGE_SHIFT_S,
3047 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3048 else
3049 roce_set_field(context->byte_4_sqpn_tst,
3050 V2_QPC_BYTE_4_SGE_SHIFT_M,
3051 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
3052 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3053
926a01dc
WHX		 3054 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
3055 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
3056
3057 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3058 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3059 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3060 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3061 0);
3062
3063 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3064 !!(attr->qp_access_flags &
3065 IB_ACCESS_REMOTE_WRITE));
3066 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3067 0);
3068
3069 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3070 !!(attr->qp_access_flags &
3071 IB_ACCESS_REMOTE_ATOMIC));
3072 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3073 0);
3074 } else {
3075 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3076 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3077 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3078 0);
3079
3080 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3081 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3082 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3083 0);
3084
3085 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3086 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3087 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3088 0);
3089 }
3090
3091 roce_set_field(context->byte_20_smac_sgid_idx,
3092 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3093 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
3094 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3095 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
3096
3097 roce_set_field(context->byte_20_smac_sgid_idx,
3098 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
3099 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
3100 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3101 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
3102
3103 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3104 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3105 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3106 V2_QPC_BYTE_16_PD_S, 0);
3107
3108 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3109 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3110 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3111 V2_QPC_BYTE_80_RX_CQN_S, 0);
3112
3113 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3114 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3115 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3116 V2_QPC_BYTE_252_TX_CQN_S, 0);
3117
3118 if (ibqp->srq) {
3119 roce_set_bit(context->byte_76_srqn_op_en,
3120 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3121 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3122 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3123 roce_set_field(context->byte_76_srqn_op_en,
3124 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3125 to_hr_srq(ibqp->srq)->srqn);
3126 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3127 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3128 }
3129
0fa95a9a 3130 if (attr_mask & IB_QP_QKEY) {
3131 context->qkey_xrcd = attr->qkey;
3132 qpc_mask->qkey_xrcd = 0;
3133 }
926a01dc
WHX		 3134
3135 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3136 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3137 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3138 V2_QPC_BYTE_4_SQPN_S, 0);
3139
b6dd9b34 3140 if (attr_mask & IB_QP_DEST_QPN) {
3141 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3142 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3143 roce_set_field(qpc_mask->byte_56_dqpn_err,
3144 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3145 }
926a01dc
WHX		 3146}
3147
3148static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3149 const struct ib_qp_attr *attr, int attr_mask,
3150 struct hns_roce_v2_qp_context *context,
3151 struct hns_roce_v2_qp_context *qpc_mask)
3152{
3153 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3154 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3155 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3156 struct device *dev = hr_dev->dev;
e92f2c18 3157 dma_addr_t dma_handle_3;
926a01dc
WHX		 3158 dma_addr_t dma_handle_2;
3159 dma_addr_t dma_handle;
3160 u32 page_size;
3161 u8 port_num;
e92f2c18 3162 u64 *mtts_3;
926a01dc
WHX		 3163 u64 *mtts_2;
3164 u64 *mtts;
3165 u8 *dmac;
3166 u8 *smac;
3167 int port;
3168
3169 /* Search qp buf's mtts */
3170 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3171 hr_qp->mtt.first_seg, &dma_handle);
3172 if (!mtts) {
3173 dev_err(dev, "qp buf pa find failed\n");
3174 return -EINVAL;
3175 }
3176
3177 /* Search IRRL's mtts */
3178 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3179 hr_qp->qpn, &dma_handle_2);
3180 if (!mtts_2) {
3181 dev_err(dev, "qp irrl_table find failed\n");
3182 return -EINVAL;
3183 }
3184
e92f2c18 3185 /* Search TRRL's mtts */
3186 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3187 hr_qp->qpn, &dma_handle_3);
3188 if (!mtts_3) {
3189 dev_err(dev, "qp trrl_table find failed\n");
3190 return -EINVAL;
3191 }
3192
734f3863 3193 if (attr_mask & IB_QP_ALT_PATH) {
926a01dc
WHX		 3194 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
3195 return -EINVAL;
3196 }
3197
3198 dmac = (u8 *)attr->ah_attr.roce.dmac;
3199 context->wqe_sge_ba = (u32)(dma_handle >> 3);
3200 qpc_mask->wqe_sge_ba = 0;
3201
3202 /*
3203 * In v2 engine, software pass context and context mask to hardware
3204 * when modifying qp. If software need modify some fields in context,
3205 * we should set all bits of the relevant fields in context mask to
3206 * 0 at the same time, else set them to 0x1.
3207 */
3208 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3209 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
3210 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3211 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3212
3213 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3214 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
3215 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3216 0 : hr_dev->caps.mtt_hop_num);
3217 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3218 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3219
3220 roce_set_field(context->byte_20_smac_sgid_idx,
3221 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3222 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
0fa95a9a 3223 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
3224 hr_dev->caps.mtt_hop_num : 0);
926a01dc
WHX		 3225 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3226 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3227 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3228
3229 roce_set_field(context->byte_20_smac_sgid_idx,
3230 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3231 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
3232 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3233 0 : hr_dev->caps.mtt_hop_num);
3234 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3235 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3236 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3237
3238 roce_set_field(context->byte_16_buf_ba_pg_sz,
3239 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3240 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
5e6e78db 3241 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3242 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3243 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3244 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3245
3246 roce_set_field(context->byte_16_buf_ba_pg_sz,
3247 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3248 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
5e6e78db 3249 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3250 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3251 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3252 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3253
3254 roce_set_field(context->byte_80_rnr_rx_cqn,
3255 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3256 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
3257 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
3258 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3259 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
3260
3261 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
3262 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
3263 >> PAGE_ADDR_SHIFT);
3264 qpc_mask->rq_cur_blk_addr = 0;
3265
3266 roce_set_field(context->byte_92_srq_info,
3267 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3268 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
3269 mtts[hr_qp->rq.offset / page_size]
3270 >> (32 + PAGE_ADDR_SHIFT));
3271 roce_set_field(qpc_mask->byte_92_srq_info,
3272 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3273 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3274
3275 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
3276 >> PAGE_ADDR_SHIFT);
3277 qpc_mask->rq_nxt_blk_addr = 0;
3278
3279 roce_set_field(context->byte_104_rq_sge,
3280 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3281 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
3282 mtts[hr_qp->rq.offset / page_size + 1]
3283 >> (32 + PAGE_ADDR_SHIFT));
3284 roce_set_field(qpc_mask->byte_104_rq_sge,
3285 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3286 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3287
3288 roce_set_field(context->byte_108_rx_reqepsn,
3289 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3290 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
3291 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3292 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3293 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
3294
e92f2c18 3295 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3296 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3297 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3298 V2_QPC_BYTE_132_TRRL_BA_S, 0);
3299 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
3300 qpc_mask->trrl_ba = 0;
3301 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3302 V2_QPC_BYTE_140_TRRL_BA_S,
3303 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3304 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3305 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3306
d5514246 3307 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 3308 qpc_mask->irrl_ba = 0;
3309 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3310 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3311 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3312 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3313 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3314
3315 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3316 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3317
3318 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3319 hr_qp->sq_signal_bits);
3320 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3321 0);
3322
3323 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3324
3325 smac = (u8 *)hr_dev->dev_addr[port];
3326 /* when dmac equals smac or loop_idc is 1, it should loopback */
3327 if (ether_addr_equal_unaligned(dmac, smac) ||
3328 hr_dev->loop_idc == 0x1) {
3329 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3330 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3331 }
3332
4f3f7a70 3333 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
3334 attr->max_dest_rd_atomic) {
3335 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3336 V2_QPC_BYTE_140_RR_MAX_S,
3337 fls(attr->max_dest_rd_atomic - 1));
3338 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3339 V2_QPC_BYTE_140_RR_MAX_S, 0);
3340 }
926a01dc 3341
b6dd9b34 3342 if (attr_mask & IB_QP_DEST_QPN) {
3343 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3344 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3345 roce_set_field(qpc_mask->byte_56_dqpn_err,
3346 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3347 }
926a01dc
WHX		 3348
3349 /* Configure GID index */
3350 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3351 roce_set_field(context->byte_20_smac_sgid_idx,
3352 V2_QPC_BYTE_20_SGID_IDX_M,
3353 V2_QPC_BYTE_20_SGID_IDX_S,
3354 hns_get_gid_index(hr_dev, port_num - 1,
3355 grh->sgid_index));
3356 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3357 V2_QPC_BYTE_20_SGID_IDX_M,
3358 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3359 memcpy(&(context->dmac), dmac, 4);
3360 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3361 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3362 qpc_mask->dmac = 0;
3363 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3364 V2_QPC_BYTE_52_DMAC_S, 0);
3365
3366 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3367 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
3368 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3369 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3370
0fa95a9a 3371 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3372 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3373 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3374 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3375 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3376 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3377
926a01dc
WHX		 3378 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3379 V2_QPC_BYTE_24_MTU_S, 0);
3380
926a01dc
WHX		 3381 roce_set_field(context->byte_84_rq_ci_pi,
3382 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3383 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3384 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3385 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3386 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3387
3388 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3389 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3390 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3391 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3392 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3393 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3394 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3395 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3396 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3397 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3398
3399 context->rq_rnr_timer = 0;
3400 qpc_mask->rq_rnr_timer = 0;
3401
3402 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3403 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
3404 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3405 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3406
3407 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3408 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3409 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3410 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3411
3412 roce_set_field(context->byte_168_irrl_idx,
3413 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3414 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3415 roce_set_field(qpc_mask->byte_168_irrl_idx,
3416 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3417 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3418
926a01dc
WHX		 3419 return 0;
3420}
3421
3422static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3423 const struct ib_qp_attr *attr, int attr_mask,
3424 struct hns_roce_v2_qp_context *context,
3425 struct hns_roce_v2_qp_context *qpc_mask)
3426{
3427 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3428 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3429 struct device *dev = hr_dev->dev;
3430 dma_addr_t dma_handle;
befb63b4 3431 u32 page_size;
926a01dc
WHX		 3432 u64 *mtts;
3433
3434 /* Search qp buf's mtts */
3435 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3436 hr_qp->mtt.first_seg, &dma_handle);
3437 if (!mtts) {
3438 dev_err(dev, "qp buf pa find failed\n");
3439 return -EINVAL;
3440 }
3441
734f3863 3442 /* Not support alternate path and path migration */
3443 if ((attr_mask & IB_QP_ALT_PATH) ||
3444 (attr_mask & IB_QP_PATH_MIG_STATE)) {
926a01dc
WHX		 3445 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
3446 return -EINVAL;
3447 }
3448
3449 /*
3450 * In v2 engine, software pass context and context mask to hardware
3451 * when modifying qp. If software need modify some fields in context,
3452 * we should set all bits of the relevant fields in context mask to
3453 * 0 at the same time, else set them to 0x1.
3454 */
926a01dc
WHX		 3455 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3456 roce_set_field(context->byte_168_irrl_idx,
3457 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3458 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3459 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3460 qpc_mask->sq_cur_blk_addr = 0;
3461 roce_set_field(qpc_mask->byte_168_irrl_idx,
3462 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3463 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3464
befb63b4 3465 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
0fa95a9a 3466 context->sq_cur_sge_blk_addr =
3467 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3468 ((u32)(mtts[hr_qp->sge.offset / page_size]
3469 >> PAGE_ADDR_SHIFT)) : 0;
3470 roce_set_field(context->byte_184_irrl_idx,
3471 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3472 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
0fa95a9a 3473 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3474 (mtts[hr_qp->sge.offset / page_size] >>
3475 (32 + PAGE_ADDR_SHIFT)) : 0);
3476 qpc_mask->sq_cur_sge_blk_addr = 0;
3477 roce_set_field(qpc_mask->byte_184_irrl_idx,
3478 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3479 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3480
926a01dc
WHX		 3481 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3482 roce_set_field(context->byte_232_irrl_sge,
3483 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3484 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3485 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3486 qpc_mask->rx_sq_cur_blk_addr = 0;
3487 roce_set_field(qpc_mask->byte_232_irrl_sge,
3488 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3489 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3490
3491 /*
3492 * Set some fields in context to zero, Because the default values
3493 * of all fields in context are zero, we need not set them to 0 again.
3494 * but we should set the relevant fields of context mask to 0.
3495 */
3496 roce_set_field(qpc_mask->byte_232_irrl_sge,
3497 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3498 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3499
3500 roce_set_field(qpc_mask->byte_240_irrl_tail,
3501 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3502 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3503
3504 roce_set_field(context->byte_244_rnr_rxack,
3505 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3506 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
3507 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3508 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3509 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
3510
3511 roce_set_field(qpc_mask->byte_248_ack_psn,
3512 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3513 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3514 roce_set_bit(qpc_mask->byte_248_ack_psn,
3515 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
3516 roce_set_field(qpc_mask->byte_248_ack_psn,
3517 V2_QPC_BYTE_248_IRRL_PSN_M,
3518 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3519
3520 roce_set_field(qpc_mask->byte_240_irrl_tail,
3521 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3522 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3523
3524 roce_set_field(context->byte_220_retry_psn_msn,
3525 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3526 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
3527 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3528 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3529 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
3530
3531 roce_set_field(context->byte_224_retry_msg,
3532 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3533 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
3534 roce_set_field(qpc_mask->byte_224_retry_msg,
3535 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3536 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
3537
3538 roce_set_field(context->byte_224_retry_msg,
3539 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3540 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
3541 roce_set_field(qpc_mask->byte_224_retry_msg,
3542 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3543 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
3544
3545 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3546 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3547 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3548
3549 roce_set_bit(qpc_mask->byte_248_ack_psn,
3550 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3551
3552 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3553 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3554
3555 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3556 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
3557 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3558 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
3559
3560 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3561 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
3562 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3563 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
3564
3565 roce_set_field(context->byte_244_rnr_rxack,
3566 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3567 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
3568 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3569 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3570 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
3571
3572 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3573 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
3574 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3575 V2_QPC_BYTE_244_RNR_CNT_S, 0);
3576
3577 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3578 V2_QPC_BYTE_212_LSN_S, 0x100);
3579 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3580 V2_QPC_BYTE_212_LSN_S, 0);
3581
28726461 3582 if (attr_mask & IB_QP_TIMEOUT) {
926a01dc
WHX		 3583 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3584 V2_QPC_BYTE_28_AT_S, attr->timeout);
28726461 3585 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3586 V2_QPC_BYTE_28_AT_S, 0);
3587 }
926a01dc 3588
926a01dc
WHX		 3589 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3590 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
3591 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3592 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
3593
3594 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3595 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3596 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3597 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
3598 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3599 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
3600
4f3f7a70 3601 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
3602 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
3603 V2_QPC_BYTE_208_SR_MAX_S,
3604 fls(attr->max_rd_atomic - 1));
3605 roce_set_field(qpc_mask->byte_208_irrl,
3606 V2_QPC_BYTE_208_SR_MAX_M,
3607 V2_QPC_BYTE_208_SR_MAX_S, 0);
3608 }
926a01dc
WHX		 3609 return 0;
3610}
3611
3612static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
3613 const struct ib_qp_attr *attr,
3614 int attr_mask, enum ib_qp_state cur_state,
3615 enum ib_qp_state new_state)
3616{
3617 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3618 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3619 struct hns_roce_v2_qp_context *context;
3620 struct hns_roce_v2_qp_context *qpc_mask;
3621 struct device *dev = hr_dev->dev;
3622 int ret = -EINVAL;
3623
6396bb22 3624 context = kcalloc(2, sizeof(*context), GFP_KERNEL);
926a01dc
WHX		 3625 if (!context)
3626 return -ENOMEM;
3627
3628 qpc_mask = context + 1;
3629 /*
3630 * In v2 engine, software pass context and context mask to hardware
3631 * when modifying qp. If software need modify some fields in context,
3632 * we should set all bits of the relevant fields in context mask to
3633 * 0 at the same time, else set them to 0x1.
3634 */
3635 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
3636 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0fa95a9a 3637 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
3638 qpc_mask);
926a01dc
WHX		 3639 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3640 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
3641 qpc_mask);
3642 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3643 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
3644 qpc_mask);
3645 if (ret)
3646 goto out;
3647 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3648 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
3649 qpc_mask);
3650 if (ret)
3651 goto out;
3652 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) ||
3653 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) ||
3654 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) ||
3655 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) ||
3656 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) ||
3657 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3658 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3659 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3660 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3661 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3662 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3663 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3664 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) ||
6e1a7094 3665 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) ||
3666 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) {
926a01dc
WHX		 3667 /* Nothing */
3668 ;
3669 } else {
3670 dev_err(dev, "Illegal state for QP!\n");
ac7cbf96 3671 ret = -EINVAL;
926a01dc
WHX		 3672 goto out;
3673 }
3674
0425e3e6
YL		 3675 /* When QP state is err, SQ and RQ WQE should be flushed */
3676 if (new_state == IB_QPS_ERR) {
3677 roce_set_field(context->byte_160_sq_ci_pi,
3678 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3679 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
3680 hr_qp->sq.head);
3681 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3682 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3683 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
3684 roce_set_field(context->byte_84_rq_ci_pi,
3685 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3686 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
3687 hr_qp->rq.head);
3688 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3689 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3690 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3691 }
3692
610b8967
LO		 3693 if (attr_mask & IB_QP_AV) {
3694 const struct ib_global_route *grh =
3695 rdma_ah_read_grh(&attr->ah_attr);
3696 const struct ib_gid_attr *gid_attr = NULL;
3697 u8 src_mac[ETH_ALEN];
3698 int is_roce_protocol;
3699 u16 vlan = 0xffff;
3700 u8 ib_port;
3701 u8 hr_port;
3702
3703 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num :
3704 hr_qp->port + 1;
3705 hr_port = ib_port - 1;
3706 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
3707 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
3708
3709 if (is_roce_protocol) {
3710 gid_attr = attr->ah_attr.grh.sgid_attr;
3711 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
3712 memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN);
3713 }
3714
caf3e406
LO		 3715 if (is_vlan_dev(gid_attr->ndev)) {
3716 roce_set_bit(context->byte_76_srqn_op_en,
3717 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
3718 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3719 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
3720 roce_set_bit(context->byte_168_irrl_idx,
3721 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
3722 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3723 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
3724 }
3725
c8e46f8d
LO		 3726 roce_set_field(context->byte_24_mtu_tc,
3727 V2_QPC_BYTE_24_VLAN_ID_M,
3728 V2_QPC_BYTE_24_VLAN_ID_S, vlan);
3729 roce_set_field(qpc_mask->byte_24_mtu_tc,
3730 V2_QPC_BYTE_24_VLAN_ID_M,
3731 V2_QPC_BYTE_24_VLAN_ID_S, 0);
3732
610b8967
LO		 3733 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
3734 dev_err(hr_dev->dev,
3735 "sgid_index(%u) too large. max is %d\n",
3736 grh->sgid_index,
3737 hr_dev->caps.gid_table_len[hr_port]);
3738 ret = -EINVAL;
3739 goto out;
3740 }
3741
3742 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
3743 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n");
3744 ret = -EINVAL;
3745 goto out;
3746 }
3747
3748 roce_set_field(context->byte_52_udpspn_dmac,
3749 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S,
3750 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3751 0 : 0x12b7);
3752
3753 roce_set_field(qpc_mask->byte_52_udpspn_dmac,
3754 V2_QPC_BYTE_52_UDPSPN_M,
3755 V2_QPC_BYTE_52_UDPSPN_S, 0);
3756
3757 roce_set_field(context->byte_20_smac_sgid_idx,
3758 V2_QPC_BYTE_20_SGID_IDX_M,
3759 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index);
3760
3761 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3762 V2_QPC_BYTE_20_SGID_IDX_M,
3763 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3764
3765 roce_set_field(context->byte_24_mtu_tc,
3766 V2_QPC_BYTE_24_HOP_LIMIT_M,
3767 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
3768 roce_set_field(qpc_mask->byte_24_mtu_tc,
3769 V2_QPC_BYTE_24_HOP_LIMIT_M,
3770 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
3771
157b52a0
LO		 3772 if (hr_dev->pci_dev->revision == 0x21 &&
3773 gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3774 roce_set_field(context->byte_24_mtu_tc,
3775 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
3776 grh->traffic_class >> 2);
3777 else
3778 roce_set_field(context->byte_24_mtu_tc,
3779 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
3780 grh->traffic_class);
610b8967
LO		 3781 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
3782 V2_QPC_BYTE_24_TC_S, 0);
3783 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3784 V2_QPC_BYTE_28_FL_S, grh->flow_label);
3785 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3786 V2_QPC_BYTE_28_FL_S, 0);
3787 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
3788 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
3789 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3790 V2_QPC_BYTE_28_SL_S,
3791 rdma_ah_get_sl(&attr->ah_attr));
3792 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3793 V2_QPC_BYTE_28_SL_S, 0);
3794 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3795 }
3796
ace1c541 3797 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3798 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
3799
926a01dc 3800 /* Every status migrate must change state */
2362ccee 3801 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 3802 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 3803 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 3804 V2_QPC_BYTE_60_QP_ST_S, 0);
3805
3806 /* SW pass context to HW */
3807 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
3808 context, hr_qp);
3809 if (ret) {
3810 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
3811 goto out;
3812 }
3813
3814 hr_qp->state = new_state;
3815
ace1c541 3816 if (attr_mask & IB_QP_ACCESS_FLAGS)
3817 hr_qp->atomic_rd_en = attr->qp_access_flags;
3818
926a01dc
WHX		 3819 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3820 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3821 if (attr_mask & IB_QP_PORT) {
3822 hr_qp->port = attr->port_num - 1;
3823 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3824 }
3825
3826 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3827 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3828 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3829 if (ibqp->send_cq != ibqp->recv_cq)
3830 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
3831 hr_qp->qpn, NULL);
3832
3833 hr_qp->rq.head = 0;
3834 hr_qp->rq.tail = 0;
3835 hr_qp->sq.head = 0;
3836 hr_qp->sq.tail = 0;
3837 hr_qp->sq_next_wqe = 0;
3838 hr_qp->next_sge = 0;
e088a685
YL		 3839 if (hr_qp->rq.wqe_cnt)
3840 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 3841 }
3842
3843out:
3844 kfree(context);
3845 return ret;
3846}
3847
3848static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
3849{
3850 switch (state) {
3851 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
3852 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
3853 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
3854 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
3855 case HNS_ROCE_QP_ST_SQ_DRAINING:
3856 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
3857 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
3858 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
3859 default: return -1;
3860 }
3861}
3862
3863static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
3864 struct hns_roce_qp *hr_qp,
3865 struct hns_roce_v2_qp_context *hr_context)
3866{
3867 struct hns_roce_cmd_mailbox *mailbox;
3868 int ret;
3869
3870 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3871 if (IS_ERR(mailbox))
3872 return PTR_ERR(mailbox);
3873
3874 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3875 HNS_ROCE_CMD_QUERY_QPC,
3876 HNS_ROCE_CMD_TIMEOUT_MSECS);
3877 if (ret) {
3878 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
3879 goto out;
3880 }
3881
3882 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3883
3884out:
3885 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3886 return ret;
3887}
3888
3889static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3890 int qp_attr_mask,
3891 struct ib_qp_init_attr *qp_init_attr)
3892{
3893 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3894 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3895 struct hns_roce_v2_qp_context *context;
3896 struct device *dev = hr_dev->dev;
3897 int tmp_qp_state;
3898 int state;
3899 int ret;
3900
3901 context = kzalloc(sizeof(*context), GFP_KERNEL);
3902 if (!context)
3903 return -ENOMEM;
3904
3905 memset(qp_attr, 0, sizeof(*qp_attr));
3906 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3907
3908 mutex_lock(&hr_qp->mutex);
3909
3910 if (hr_qp->state == IB_QPS_RESET) {
3911 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 3912 ret = 0;
926a01dc
WHX		 3913 goto done;
3914 }
3915
3916 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
3917 if (ret) {
3918 dev_err(dev, "query qpc error\n");
3919 ret = -EINVAL;
3920 goto out;
3921 }
3922
2362ccee 3923 state = roce_get_field(context->byte_60_qpst_tempid,
926a01dc
WHX		 3924 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
3925 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
3926 if (tmp_qp_state == -1) {
3927 dev_err(dev, "Illegal ib_qp_state\n");
3928 ret = -EINVAL;
3929 goto out;
3930 }
3931 hr_qp->state = (u8)tmp_qp_state;
3932 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3933 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
3934 V2_QPC_BYTE_24_MTU_M,
3935 V2_QPC_BYTE_24_MTU_S);
3936 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 3937 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 3938 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3939 qp_attr->qkey = V2_QKEY_VAL;
3940
3941 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
3942 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3943 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
3944 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
3945 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3946 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
3947 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
3948 V2_QPC_BYTE_56_DQPN_M,
3949 V2_QPC_BYTE_56_DQPN_S);
3950 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
3951 V2_QPC_BYTE_76_RRE_S)) << 2) |
3952 ((roce_get_bit(context->byte_76_srqn_op_en,
3953 V2_QPC_BYTE_76_RWE_S)) << 1) |
3954 ((roce_get_bit(context->byte_76_srqn_op_en,
3955 V2_QPC_BYTE_76_ATE_S)) << 3);
3956 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3957 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3958 struct ib_global_route *grh =
3959 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3960
3961 rdma_ah_set_sl(&qp_attr->ah_attr,
3962 roce_get_field(context->byte_28_at_fl,
3963 V2_QPC_BYTE_28_SL_M,
3964 V2_QPC_BYTE_28_SL_S));
3965 grh->flow_label = roce_get_field(context->byte_28_at_fl,
3966 V2_QPC_BYTE_28_FL_M,
3967 V2_QPC_BYTE_28_FL_S);
3968 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
3969 V2_QPC_BYTE_20_SGID_IDX_M,
3970 V2_QPC_BYTE_20_SGID_IDX_S);
3971 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
3972 V2_QPC_BYTE_24_HOP_LIMIT_M,
3973 V2_QPC_BYTE_24_HOP_LIMIT_S);
3974 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
3975 V2_QPC_BYTE_24_TC_M,
3976 V2_QPC_BYTE_24_TC_S);
3977
3978 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
3979 }
3980
3981 qp_attr->port_num = hr_qp->port + 1;
3982 qp_attr->sq_draining = 0;
3983 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
3984 V2_QPC_BYTE_208_SR_MAX_M,
3985 V2_QPC_BYTE_208_SR_MAX_S);
3986 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
3987 V2_QPC_BYTE_140_RR_MAX_M,
3988 V2_QPC_BYTE_140_RR_MAX_S);
3989 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
3990 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3991 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
3992 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
3993 V2_QPC_BYTE_28_AT_M,
3994 V2_QPC_BYTE_28_AT_S);
3995 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
3996 V2_QPC_BYTE_212_RETRY_CNT_M,
3997 V2_QPC_BYTE_212_RETRY_CNT_S);
3998 qp_attr->rnr_retry = context->rq_rnr_timer;
3999
4000done:
4001 qp_attr->cur_qp_state = qp_attr->qp_state;
4002 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4003 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4004
4005 if (!ibqp->uobject) {
4006 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4007 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4008 } else {
4009 qp_attr->cap.max_send_wr = 0;
4010 qp_attr->cap.max_send_sge = 0;
4011 }
4012
4013 qp_init_attr->cap = qp_attr->cap;
4014
4015out:
4016 mutex_unlock(&hr_qp->mutex);
4017 kfree(context);
4018 return ret;
4019}
4020
4021static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4022 struct hns_roce_qp *hr_qp,
4023 int is_user)
4024{
4025 struct hns_roce_cq *send_cq, *recv_cq;
4026 struct device *dev = hr_dev->dev;
4027 int ret;
4028
4029 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4030 /* Modify qp to reset before destroying qp */
4031 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4032 hr_qp->state, IB_QPS_RESET);
4033 if (ret) {
4034 dev_err(dev, "modify QP %06lx to ERR failed.\n",
4035 hr_qp->qpn);
4036 return ret;
4037 }
4038 }
4039
4040 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
4041 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
4042
4043 hns_roce_lock_cqs(send_cq, recv_cq);
4044
4045 if (!is_user) {
4046 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
4047 to_hr_srq(hr_qp->ibqp.srq) : NULL);
4048 if (send_cq != recv_cq)
4049 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
4050 }
4051
4052 hns_roce_qp_remove(hr_dev, hr_qp);
4053
4054 hns_roce_unlock_cqs(send_cq, recv_cq);
4055
4056 hns_roce_qp_free(hr_dev, hr_qp);
4057
4058 /* Not special_QP, free their QPN */
4059 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
4060 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
4061 (hr_qp->ibqp.qp_type == IB_QPT_UD))
4062 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
4063
4064 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
4065
4066 if (is_user) {
0425e3e6
YL		 4067 if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1))
4068 hns_roce_db_unmap_user(
4069 to_hr_ucontext(hr_qp->ibqp.uobject->context),
4070 &hr_qp->sdb);
4071
e088a685
YL		 4072 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1))
4073 hns_roce_db_unmap_user(
4074 to_hr_ucontext(hr_qp->ibqp.uobject->context),
4075 &hr_qp->rdb);
926a01dc
WHX		 4076 ib_umem_release(hr_qp->umem);
4077 } else {
4078 kfree(hr_qp->sq.wrid);
4079 kfree(hr_qp->rq.wrid);
4080 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
472bc0fb
YL		 4081 if (hr_qp->rq.wqe_cnt)
4082 hns_roce_free_db(hr_dev, &hr_qp->rdb);
926a01dc
WHX		 4083 }
4084
0009c2db 4085 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
4086 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
4087 kfree(hr_qp->rq_inl_buf.wqe_list);
4088 }
4089
926a01dc
WHX		 4090 return 0;
4091}
4092
4093static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
4094{
4095 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4096 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4097 int ret;
4098
4099 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
4100 if (ret) {
4101 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
4102 return ret;
4103 }
4104
4105 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
4106 kfree(hr_to_hr_sqp(hr_qp));
4107 else
4108 kfree(hr_qp);
4109
4110 return 0;
4111}
4112
b156269d 4113static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
4114{
4115 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
4116 struct hns_roce_v2_cq_context *cq_context;
4117 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
4118 struct hns_roce_v2_cq_context *cqc_mask;
4119 struct hns_roce_cmd_mailbox *mailbox;
4120 int ret;
4121
4122 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4123 if (IS_ERR(mailbox))
4124 return PTR_ERR(mailbox);
4125
4126 cq_context = mailbox->buf;
4127 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
4128
4129 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
4130
4131 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4132 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4133 cq_count);
4134 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4135 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4136 0);
4137 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4138 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4139 cq_period);
4140 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4141 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4142 0);
4143
4144 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
4145 HNS_ROCE_CMD_MODIFY_CQC,
4146 HNS_ROCE_CMD_TIMEOUT_MSECS);
4147 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4148 if (ret)
4149 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
4150
4151 return ret;
4152}
4153
0425e3e6
YL		 4154static void hns_roce_set_qps_to_err(struct hns_roce_dev *hr_dev, u32 qpn)
4155{
4156 struct hns_roce_qp *hr_qp;
4157 struct ib_qp_attr attr;
4158 int attr_mask;
4159 int ret;
4160
4161 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
4162 if (!hr_qp) {
4163 dev_warn(hr_dev->dev, "no hr_qp can be found!\n");
4164 return;
4165 }
4166
4167 if (hr_qp->ibqp.uobject) {
4168 if (hr_qp->sdb_en == 1) {
4169 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
4170 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
4171 } else {
4172 dev_warn(hr_dev->dev, "flush cqe is unsupported in userspace!\n");
4173 return;
4174 }
4175 }
4176
4177 attr_mask = IB_QP_STATE;
4178 attr.qp_state = IB_QPS_ERR;
4179 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, attr_mask,
4180 hr_qp->state, IB_QPS_ERR);
4181 if (ret)
4182 dev_err(hr_dev->dev, "failed to modify qp %d to err state.\n",
4183 qpn);
4184}
4185
4186static void hns_roce_irq_work_handle(struct work_struct *work)
4187{
4188 struct hns_roce_work *irq_work =
4189 container_of(work, struct hns_roce_work, work);
b00a92c8 4190 struct device *dev = irq_work->hr_dev->dev;
0425e3e6 4191 u32 qpn = irq_work->qpn;
b00a92c8 4192 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4193
4194 switch (irq_work->event_type) {
b00a92c8 4195 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4196 dev_info(dev, "Path migrated succeeded.\n");
4197 break;
4198 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4199 dev_warn(dev, "Path migration failed.\n");
4200 break;
4201 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4202 dev_info(dev, "Communication established.\n");
4203 break;
4204 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4205 dev_warn(dev, "Send queue drained.\n");
4206 break;
0425e3e6 4207 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
b00a92c8 4208 dev_err(dev, "Local work queue catastrophic error.\n");
4209 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4210 switch (irq_work->sub_type) {
4211 case HNS_ROCE_LWQCE_QPC_ERROR:
4212 dev_err(dev, "QP %d, QPC error.\n", qpn);
4213 break;
4214 case HNS_ROCE_LWQCE_MTU_ERROR:
4215 dev_err(dev, "QP %d, MTU error.\n", qpn);
4216 break;
4217 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4218 dev_err(dev, "QP %d, WQE BA addr error.\n", qpn);
4219 break;
4220 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4221 dev_err(dev, "QP %d, WQE addr error.\n", qpn);
4222 break;
4223 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4224 dev_err(dev, "QP %d, WQE shift error.\n", qpn);
4225 break;
4226 default:
4227 dev_err(dev, "Unhandled sub_event type %d.\n",
4228 irq_work->sub_type);
4229 break;
4230 }
4231 break;
0425e3e6 4232 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
b00a92c8 4233 dev_err(dev, "Invalid request local work queue error.\n");
4234 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4235 break;
0425e3e6 4236 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4237 dev_err(dev, "Local access violation work queue error.\n");
0425e3e6 4238 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
b00a92c8 4239 switch (irq_work->sub_type) {
4240 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4241 dev_err(dev, "QP %d, R_key violation.\n", qpn);
4242 break;
4243 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4244 dev_err(dev, "QP %d, length error.\n", qpn);
4245 break;
4246 case HNS_ROCE_LAVWQE_VA_ERROR:
4247 dev_err(dev, "QP %d, VA error.\n", qpn);
4248 break;
4249 case HNS_ROCE_LAVWQE_PD_ERROR:
4250 dev_err(dev, "QP %d, PD error.\n", qpn);
4251 break;
4252 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4253 dev_err(dev, "QP %d, rw acc error.\n", qpn);
4254 break;
4255 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4256 dev_err(dev, "QP %d, key state error.\n", qpn);
4257 break;
4258 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4259 dev_err(dev, "QP %d, MR operation error.\n", qpn);
4260 break;
4261 default:
4262 dev_err(dev, "Unhandled sub_event type %d.\n",
4263 irq_work->sub_type);
4264 break;
4265 }
4266 break;
4267 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4268 dev_warn(dev, "SRQ limit reach.\n");
4269 break;
4270 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4271 dev_warn(dev, "SRQ last wqe reach.\n");
4272 break;
4273 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4274 dev_err(dev, "SRQ catas error.\n");
4275 break;
4276 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4277 dev_err(dev, "CQ 0x%x access err.\n", cqn);
4278 break;
4279 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4280 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4281 break;
4282 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4283 dev_warn(dev, "DB overflow.\n");
4284 break;
4285 case HNS_ROCE_EVENT_TYPE_FLR:
4286 dev_warn(dev, "Function level reset.\n");
0425e3e6
YL		 4287 break;
4288 default:
4289 break;
4290 }
4291
4292 kfree(irq_work);
4293}
4294
4295static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4296 struct hns_roce_eq *eq,
4297 u32 qpn, u32 cqn)
0425e3e6
YL		 4298{
4299 struct hns_roce_work *irq_work;
4300
4301 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4302 if (!irq_work)
4303 return;
4304
4305 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4306 irq_work->hr_dev = hr_dev;
4307 irq_work->qpn = qpn;
b00a92c8 4308 irq_work->cqn = cqn;
0425e3e6
YL		 4309 irq_work->event_type = eq->event_type;
4310 irq_work->sub_type = eq->sub_type;
4311 queue_work(hr_dev->irq_workq, &(irq_work->work));
4312}
4313
a5073d60
YL		 4314static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4315{
4316 u32 doorbell[2];
4317
4318 doorbell[0] = 0;
4319 doorbell[1] = 0;
4320
4321 if (eq->type_flag == HNS_ROCE_AEQ) {
4322 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4323 HNS_ROCE_V2_EQ_DB_CMD_S,
4324 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4325 HNS_ROCE_EQ_DB_CMD_AEQ :
4326 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4327 } else {
4328 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4329 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4330
4331 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4332 HNS_ROCE_V2_EQ_DB_CMD_S,
4333 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4334 HNS_ROCE_EQ_DB_CMD_CEQ :
4335 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4336 }
4337
4338 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4339 HNS_ROCE_V2_EQ_DB_PARA_S,
4340 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4341
4342 hns_roce_write64_k(doorbell, eq->doorbell);
a5073d60
YL		 4343}
4344
a5073d60
YL		 4345static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry)
4346{
4347 u32 buf_chk_sz;
4348 unsigned long off;
4349
4350 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4351 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4352
4353 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) +
4354 off % buf_chk_sz);
4355}
4356
4357static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry)
4358{
4359 u32 buf_chk_sz;
4360 unsigned long off;
4361
4362 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4363
4364 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4365
4366 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4367 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) +
4368 off % buf_chk_sz);
4369 else
4370 return (struct hns_roce_aeqe *)((u8 *)
4371 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz);
4372}
4373
4374static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4375{
4376 struct hns_roce_aeqe *aeqe;
4377
4378 if (!eq->hop_num)
4379 aeqe = get_aeqe_v2(eq, eq->cons_index);
4380 else
4381 aeqe = mhop_get_aeqe(eq, eq->cons_index);
4382
4383 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4384 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4385}
4386
4387static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4388 struct hns_roce_eq *eq)
4389{
4390 struct device *dev = hr_dev->dev;
4391 struct hns_roce_aeqe *aeqe;
4392 int aeqe_found = 0;
4393 int event_type;
0425e3e6
YL		 4394 int sub_type;
4395 u32 qpn;
4396 u32 cqn;
a5073d60
YL		 4397
4398 while ((aeqe = next_aeqe_sw_v2(eq))) {
4044a3f4
YL		 4399
4400 /* Make sure we read AEQ entry after we have checked the
4401 * ownership bit
4402 */
4403 dma_rmb();
a5073d60
YL		 4404
4405 event_type = roce_get_field(aeqe->asyn,
4406 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
4407 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 4408 sub_type = roce_get_field(aeqe->asyn,
4409 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
4410 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
4411 qpn = roce_get_field(aeqe->event.qp_event.qp,
4412 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4413 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4414 cqn = roce_get_field(aeqe->event.cq_event.cq,
4415 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4416 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 4417
4418 switch (event_type) {
4419 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 4420 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 4421 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4422 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4423 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4424 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4425 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4426 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 4427 break;
4428 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4429 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4430 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
a5073d60
YL		 4431 break;
4432 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4433 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 4434 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 4435 break;
4436 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 4437 break;
4438 case HNS_ROCE_EVENT_TYPE_MB:
4439 hns_roce_cmd_event(hr_dev,
4440 le16_to_cpu(aeqe->event.cmd.token),
4441 aeqe->event.cmd.status,
4442 le64_to_cpu(aeqe->event.cmd.out_param));
4443 break;
4444 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 4445 break;
4446 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 4447 break;
4448 default:
4449 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4450 event_type, eq->eqn, eq->cons_index);
4451 break;
4452 };
4453
0425e3e6
YL		 4454 eq->event_type = event_type;
4455 eq->sub_type = sub_type;
a5073d60
YL		 4456 ++eq->cons_index;
4457 aeqe_found = 1;
4458
4459 if (eq->cons_index > (2 * eq->entries - 1)) {
4460 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4461 eq->cons_index = 0;
4462 }
b00a92c8 4463 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
a5073d60
YL		 4464 }
4465
4466 set_eq_cons_index_v2(eq);
4467 return aeqe_found;
4468}
4469
4470static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry)
4471{
4472 u32 buf_chk_sz;
4473 unsigned long off;
4474
4475 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4476 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4477
4478 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) +
4479 off % buf_chk_sz);
4480}
4481
4482static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry)
4483{
4484 u32 buf_chk_sz;
4485 unsigned long off;
4486
4487 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4488
4489 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4490
4491 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4492 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) +
4493 off % buf_chk_sz);
4494 else
4495 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off /
4496 buf_chk_sz]) + off % buf_chk_sz);
4497}
4498
4499static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
4500{
4501 struct hns_roce_ceqe *ceqe;
4502
4503 if (!eq->hop_num)
4504 ceqe = get_ceqe_v2(eq, eq->cons_index);
4505 else
4506 ceqe = mhop_get_ceqe(eq, eq->cons_index);
4507
4508 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
4509 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4510}
4511
4512static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
4513 struct hns_roce_eq *eq)
4514{
4515 struct device *dev = hr_dev->dev;
4516 struct hns_roce_ceqe *ceqe;
4517 int ceqe_found = 0;
4518 u32 cqn;
4519
4520 while ((ceqe = next_ceqe_sw_v2(eq))) {
4521
4044a3f4
YL		 4522 /* Make sure we read CEQ entry after we have checked the
4523 * ownership bit
4524 */
4525 dma_rmb();
4526
a5073d60
YL		 4527 cqn = roce_get_field(ceqe->comp,
4528 HNS_ROCE_V2_CEQE_COMP_CQN_M,
4529 HNS_ROCE_V2_CEQE_COMP_CQN_S);
4530
4531 hns_roce_cq_completion(hr_dev, cqn);
4532
4533 ++eq->cons_index;
4534 ceqe_found = 1;
4535
4536 if (eq->cons_index > (2 * eq->entries - 1)) {
4537 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4538 eq->cons_index = 0;
4539 }
4540 }
4541
4542 set_eq_cons_index_v2(eq);
4543
4544 return ceqe_found;
4545}
4546
4547static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
4548{
4549 struct hns_roce_eq *eq = eq_ptr;
4550 struct hns_roce_dev *hr_dev = eq->hr_dev;
4551 int int_work = 0;
4552
4553 if (eq->type_flag == HNS_ROCE_CEQ)
4554 /* Completion event interrupt */
4555 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
4556 else
4557 /* Asychronous event interrupt */
4558 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
4559
4560 return IRQ_RETVAL(int_work);
4561}
4562
4563static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
4564{
4565 struct hns_roce_dev *hr_dev = dev_id;
4566 struct device *dev = hr_dev->dev;
4567 int int_work = 0;
4568 u32 int_st;
4569 u32 int_en;
4570
4571 /* Abnormal interrupt */
4572 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
4573 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
4574
4575 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
4576 dev_err(dev, "AEQ overflow!\n");
4577
4578 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
4579 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4580
a5073d60
YL		 4581 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4582 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4583
4584 int_work = 1;
4585 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
4586 dev_err(dev, "BUS ERR!\n");
4587
4588 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
4589 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4590
a5073d60
YL		 4591 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4592 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4593
4594 int_work = 1;
4595 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
4596 dev_err(dev, "OTHER ERR!\n");
4597
4598 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
4599 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4600
a5073d60
YL		 4601 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4602 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4603
4604 int_work = 1;
4605 } else
4606 dev_err(dev, "There is no abnormal irq found!\n");
4607
4608 return IRQ_RETVAL(int_work);
4609}
4610
4611static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
4612 int eq_num, int enable_flag)
4613{
4614 int i;
4615
4616 if (enable_flag == EQ_ENABLE) {
4617 for (i = 0; i < eq_num; i++)
4618 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4619 i * EQ_REG_OFFSET,
4620 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
4621
4622 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4623 HNS_ROCE_V2_VF_ABN_INT_EN_M);
4624 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4625 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
4626 } else {
4627 for (i = 0; i < eq_num; i++)
4628 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4629 i * EQ_REG_OFFSET,
4630 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
4631
4632 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4633 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
4634 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4635 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
4636 }
4637}
4638
4639static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
4640{
4641 struct device *dev = hr_dev->dev;
4642 int ret;
4643
4644 if (eqn < hr_dev->caps.num_comp_vectors)
4645 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4646 0, HNS_ROCE_CMD_DESTROY_CEQC,
4647 HNS_ROCE_CMD_TIMEOUT_MSECS);
4648 else
4649 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4650 0, HNS_ROCE_CMD_DESTROY_AEQC,
4651 HNS_ROCE_CMD_TIMEOUT_MSECS);
4652 if (ret)
4653 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
4654}
4655
4656static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev,
4657 struct hns_roce_eq *eq)
4658{
4659 struct device *dev = hr_dev->dev;
4660 u64 idx;
4661 u64 size;
4662 u32 buf_chk_sz;
4663 u32 bt_chk_sz;
4664 u32 mhop_num;
4665 int eqe_alloc;
a5073d60
YL		 4666 int i = 0;
4667 int j = 0;
4668
4669 mhop_num = hr_dev->caps.eqe_hop_num;
4670 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4671 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
a5073d60
YL		 4672
4673 /* hop_num = 0 */
4674 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4675 dma_free_coherent(dev, (unsigned int)(eq->entries *
4676 eq->eqe_size), eq->bt_l0, eq->l0_dma);
4677 return;
4678 }
4679
4680 /* hop_num = 1 or hop = 2 */
4681 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4682 if (mhop_num == 1) {
4683 for (i = 0; i < eq->l0_last_num; i++) {
4684 if (i == eq->l0_last_num - 1) {
4685 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4686 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4687 dma_free_coherent(dev, size, eq->buf[i],
4688 eq->buf_dma[i]);
4689 break;
4690 }
4691 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4692 eq->buf_dma[i]);
4693 }
4694 } else if (mhop_num == 2) {
4695 for (i = 0; i < eq->l0_last_num; i++) {
4696 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4697 eq->l1_dma[i]);
4698
4699 for (j = 0; j < bt_chk_sz / 8; j++) {
4700 idx = i * (bt_chk_sz / 8) + j;
4701 if ((i == eq->l0_last_num - 1)
4702 && j == eq->l1_last_num - 1) {
4703 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4704 * idx;
4705 size = (eq->entries - eqe_alloc)
4706 * eq->eqe_size;
4707 dma_free_coherent(dev, size,
4708 eq->buf[idx],
4709 eq->buf_dma[idx]);
4710 break;
4711 }
4712 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4713 eq->buf_dma[idx]);
4714 }
4715 }
4716 }
4717 kfree(eq->buf_dma);
4718 kfree(eq->buf);
4719 kfree(eq->l1_dma);
4720 kfree(eq->bt_l1);
4721 eq->buf_dma = NULL;
4722 eq->buf = NULL;
4723 eq->l1_dma = NULL;
4724 eq->bt_l1 = NULL;
4725}
4726
4727static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev,
4728 struct hns_roce_eq *eq)
4729{
4730 u32 buf_chk_sz;
4731
4732 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4733
4734 if (hr_dev->caps.eqe_hop_num) {
4735 hns_roce_mhop_free_eq(hr_dev, eq);
4736 return;
4737 }
4738
4739 if (eq->buf_list)
4740 dma_free_coherent(hr_dev->dev, buf_chk_sz,
4741 eq->buf_list->buf, eq->buf_list->map);
4742}
4743
4744static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
4745 struct hns_roce_eq *eq,
4746 void *mb_buf)
4747{
4748 struct hns_roce_eq_context *eqc;
4749
4750 eqc = mb_buf;
4751 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
4752
4753 /* init eqc */
4754 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
4755 eq->hop_num = hr_dev->caps.eqe_hop_num;
4756 eq->cons_index = 0;
4757 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
4758 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
4759 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
4760 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz;
4761 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz;
4762 eq->shift = ilog2((unsigned int)eq->entries);
4763
4764 if (!eq->hop_num)
4765 eq->eqe_ba = eq->buf_list->map;
4766 else
4767 eq->eqe_ba = eq->l0_dma;
4768
4769 /* set eqc state */
4770 roce_set_field(eqc->byte_4,
4771 HNS_ROCE_EQC_EQ_ST_M,
4772 HNS_ROCE_EQC_EQ_ST_S,
4773 HNS_ROCE_V2_EQ_STATE_VALID);
4774
4775 /* set eqe hop num */
4776 roce_set_field(eqc->byte_4,
4777 HNS_ROCE_EQC_HOP_NUM_M,
4778 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
4779
4780 /* set eqc over_ignore */
4781 roce_set_field(eqc->byte_4,
4782 HNS_ROCE_EQC_OVER_IGNORE_M,
4783 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
4784
4785 /* set eqc coalesce */
4786 roce_set_field(eqc->byte_4,
4787 HNS_ROCE_EQC_COALESCE_M,
4788 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
4789
4790 /* set eqc arm_state */
4791 roce_set_field(eqc->byte_4,
4792 HNS_ROCE_EQC_ARM_ST_M,
4793 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
4794
4795 /* set eqn */
4796 roce_set_field(eqc->byte_4,
4797 HNS_ROCE_EQC_EQN_M,
4798 HNS_ROCE_EQC_EQN_S, eq->eqn);
4799
4800 /* set eqe_cnt */
4801 roce_set_field(eqc->byte_4,
4802 HNS_ROCE_EQC_EQE_CNT_M,
4803 HNS_ROCE_EQC_EQE_CNT_S,
4804 HNS_ROCE_EQ_INIT_EQE_CNT);
4805
4806 /* set eqe_ba_pg_sz */
4807 roce_set_field(eqc->byte_8,
4808 HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db
YL		 4809 HNS_ROCE_EQC_BA_PG_SZ_S,
4810 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4811
4812 /* set eqe_buf_pg_sz */
4813 roce_set_field(eqc->byte_8,
4814 HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db
YL		 4815 HNS_ROCE_EQC_BUF_PG_SZ_S,
4816 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4817
4818 /* set eq_producer_idx */
4819 roce_set_field(eqc->byte_8,
4820 HNS_ROCE_EQC_PROD_INDX_M,
4821 HNS_ROCE_EQC_PROD_INDX_S,
4822 HNS_ROCE_EQ_INIT_PROD_IDX);
4823
4824 /* set eq_max_cnt */
4825 roce_set_field(eqc->byte_12,
4826 HNS_ROCE_EQC_MAX_CNT_M,
4827 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
4828
4829 /* set eq_period */
4830 roce_set_field(eqc->byte_12,
4831 HNS_ROCE_EQC_PERIOD_M,
4832 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
4833
4834 /* set eqe_report_timer */
4835 roce_set_field(eqc->eqe_report_timer,
4836 HNS_ROCE_EQC_REPORT_TIMER_M,
4837 HNS_ROCE_EQC_REPORT_TIMER_S,
4838 HNS_ROCE_EQ_INIT_REPORT_TIMER);
4839
4840 /* set eqe_ba [34:3] */
4841 roce_set_field(eqc->eqe_ba0,
4842 HNS_ROCE_EQC_EQE_BA_L_M,
4843 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3);
4844
4845 /* set eqe_ba [64:35] */
4846 roce_set_field(eqc->eqe_ba1,
4847 HNS_ROCE_EQC_EQE_BA_H_M,
4848 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35);
4849
4850 /* set eq shift */
4851 roce_set_field(eqc->byte_28,
4852 HNS_ROCE_EQC_SHIFT_M,
4853 HNS_ROCE_EQC_SHIFT_S, eq->shift);
4854
4855 /* set eq MSI_IDX */
4856 roce_set_field(eqc->byte_28,
4857 HNS_ROCE_EQC_MSI_INDX_M,
4858 HNS_ROCE_EQC_MSI_INDX_S,
4859 HNS_ROCE_EQ_INIT_MSI_IDX);
4860
4861 /* set cur_eqe_ba [27:12] */
4862 roce_set_field(eqc->byte_28,
4863 HNS_ROCE_EQC_CUR_EQE_BA_L_M,
4864 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12);
4865
4866 /* set cur_eqe_ba [59:28] */
4867 roce_set_field(eqc->byte_32,
4868 HNS_ROCE_EQC_CUR_EQE_BA_M_M,
4869 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28);
4870
4871 /* set cur_eqe_ba [63:60] */
4872 roce_set_field(eqc->byte_36,
4873 HNS_ROCE_EQC_CUR_EQE_BA_H_M,
4874 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60);
4875
4876 /* set eq consumer idx */
4877 roce_set_field(eqc->byte_36,
4878 HNS_ROCE_EQC_CONS_INDX_M,
4879 HNS_ROCE_EQC_CONS_INDX_S,
4880 HNS_ROCE_EQ_INIT_CONS_IDX);
4881
4882 /* set nex_eqe_ba[43:12] */
4883 roce_set_field(eqc->nxt_eqe_ba0,
4884 HNS_ROCE_EQC_NXT_EQE_BA_L_M,
4885 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12);
4886
4887 /* set nex_eqe_ba[63:44] */
4888 roce_set_field(eqc->nxt_eqe_ba1,
4889 HNS_ROCE_EQC_NXT_EQE_BA_H_M,
4890 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44);
4891}
4892
4893static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev,
4894 struct hns_roce_eq *eq)
4895{
4896 struct device *dev = hr_dev->dev;
4897 int eq_alloc_done = 0;
4898 int eq_buf_cnt = 0;
4899 int eqe_alloc;
4900 u32 buf_chk_sz;
4901 u32 bt_chk_sz;
4902 u32 mhop_num;
4903 u64 size;
4904 u64 idx;
4905 int ba_num;
4906 int bt_num;
4907 int record_i;
4908 int record_j;
4909 int i = 0;
4910 int j = 0;
4911
4912 mhop_num = hr_dev->caps.eqe_hop_num;
4913 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4914 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
4915
4916 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1)
4917 / buf_chk_sz;
4918 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8);
4919
4920 /* hop_num = 0 */
4921 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4922 if (eq->entries > buf_chk_sz / eq->eqe_size) {
4923 dev_err(dev, "eq entries %d is larger than buf_pg_sz!",
4924 eq->entries);
4925 return -EINVAL;
4926 }
4927 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size,
4928 &(eq->l0_dma), GFP_KERNEL);
4929 if (!eq->bt_l0)
4930 return -ENOMEM;
4931
4932 eq->cur_eqe_ba = eq->l0_dma;
4933 eq->nxt_eqe_ba = 0;
4934
4935 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size);
4936
4937 return 0;
4938 }
4939
4940 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL);
4941 if (!eq->buf_dma)
4942 return -ENOMEM;
4943 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL);
4944 if (!eq->buf)
4945 goto err_kcalloc_buf;
4946
4947 if (mhop_num == 2) {
4948 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL);
4949 if (!eq->l1_dma)
4950 goto err_kcalloc_l1_dma;
4951
4952 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL);
4953 if (!eq->bt_l1)
4954 goto err_kcalloc_bt_l1;
4955 }
4956
4957 /* alloc L0 BT */
4958 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL);
4959 if (!eq->bt_l0)
4960 goto err_dma_alloc_l0;
4961
4962 if (mhop_num == 1) {
4963 if (ba_num > (bt_chk_sz / 8))
4964 dev_err(dev, "ba_num %d is too large for 1 hop\n",
4965 ba_num);
4966
4967 /* alloc buf */
4968 for (i = 0; i < bt_chk_sz / 8; i++) {
4969 if (eq_buf_cnt + 1 < ba_num) {
4970 size = buf_chk_sz;
4971 } else {
4972 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4973 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4974 }
6d10550c 4975 eq->buf[i] = dma_zalloc_coherent(dev, size,
a5073d60
YL		 4976 &(eq->buf_dma[i]),
4977 GFP_KERNEL);
4978 if (!eq->buf[i])
4979 goto err_dma_alloc_buf;
4980
a5073d60
YL		 4981 *(eq->bt_l0 + i) = eq->buf_dma[i];
4982
4983 eq_buf_cnt++;
4984 if (eq_buf_cnt >= ba_num)
4985 break;
4986 }
4987 eq->cur_eqe_ba = eq->buf_dma[0];
4988 eq->nxt_eqe_ba = eq->buf_dma[1];
4989
4990 } else if (mhop_num == 2) {
4991 /* alloc L1 BT and buf */
4992 for (i = 0; i < bt_chk_sz / 8; i++) {
4993 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz,
4994 &(eq->l1_dma[i]),
4995 GFP_KERNEL);
4996 if (!eq->bt_l1[i])
4997 goto err_dma_alloc_l1;
4998 *(eq->bt_l0 + i) = eq->l1_dma[i];
4999
5000 for (j = 0; j < bt_chk_sz / 8; j++) {
5001 idx = i * bt_chk_sz / 8 + j;
5002 if (eq_buf_cnt + 1 < ba_num) {
5003 size = buf_chk_sz;
5004 } else {
5005 eqe_alloc = (buf_chk_sz / eq->eqe_size)
5006 * idx;
5007 size = (eq->entries - eqe_alloc)
5008 * eq->eqe_size;
5009 }
6d10550c 5010 eq->buf[idx] = dma_zalloc_coherent(dev, size,
a5073d60
YL		 5011 &(eq->buf_dma[idx]),
5012 GFP_KERNEL);
5013 if (!eq->buf[idx])
5014 goto err_dma_alloc_buf;
5015
a5073d60
YL		 5016 *(eq->bt_l1[i] + j) = eq->buf_dma[idx];
5017
5018 eq_buf_cnt++;
5019 if (eq_buf_cnt >= ba_num) {
5020 eq_alloc_done = 1;
5021 break;
5022 }
5023 }
5024
5025 if (eq_alloc_done)
5026 break;
5027 }
5028 eq->cur_eqe_ba = eq->buf_dma[0];
5029 eq->nxt_eqe_ba = eq->buf_dma[1];
5030 }
5031
5032 eq->l0_last_num = i + 1;
5033 if (mhop_num == 2)
5034 eq->l1_last_num = j + 1;
5035
5036 return 0;
5037
5038err_dma_alloc_l1:
5039 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5040 eq->bt_l0 = NULL;
5041 eq->l0_dma = 0;
5042 for (i -= 1; i >= 0; i--) {
5043 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5044 eq->l1_dma[i]);
5045
5046 for (j = 0; j < bt_chk_sz / 8; j++) {
5047 idx = i * bt_chk_sz / 8 + j;
5048 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
5049 eq->buf_dma[idx]);
5050 }
5051 }
5052 goto err_dma_alloc_l0;
5053
5054err_dma_alloc_buf:
5055 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5056 eq->bt_l0 = NULL;
5057 eq->l0_dma = 0;
5058
5059 if (mhop_num == 1)
38759d61 5060 for (i -= 1; i >= 0; i--)
a5073d60
YL		 5061 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
5062 eq->buf_dma[i]);
5063 else if (mhop_num == 2) {
5064 record_i = i;
5065 record_j = j;
5066 for (; i >= 0; i--) {
5067 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5068 eq->l1_dma[i]);
5069
5070 for (j = 0; j < bt_chk_sz / 8; j++) {
5071 if (i == record_i && j >= record_j)
5072 break;
5073
5074 idx = i * bt_chk_sz / 8 + j;
5075 dma_free_coherent(dev, buf_chk_sz,
5076 eq->buf[idx],
5077 eq->buf_dma[idx]);
5078 }
5079 }
5080 }
5081
5082err_dma_alloc_l0:
5083 kfree(eq->bt_l1);
5084 eq->bt_l1 = NULL;
5085
5086err_kcalloc_bt_l1:
5087 kfree(eq->l1_dma);
5088 eq->l1_dma = NULL;
5089
5090err_kcalloc_l1_dma:
5091 kfree(eq->buf);
5092 eq->buf = NULL;
5093
5094err_kcalloc_buf:
5095 kfree(eq->buf_dma);
5096 eq->buf_dma = NULL;
5097
5098 return -ENOMEM;
5099}
5100
5101static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5102 struct hns_roce_eq *eq,
5103 unsigned int eq_cmd)
5104{
5105 struct device *dev = hr_dev->dev;
5106 struct hns_roce_cmd_mailbox *mailbox;
5107 u32 buf_chk_sz = 0;
5108 int ret;
5109
5110 /* Allocate mailbox memory */
5111 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5112 if (IS_ERR(mailbox))
5113 return PTR_ERR(mailbox);
5114
5115 if (!hr_dev->caps.eqe_hop_num) {
5116 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5117
5118 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list),
5119 GFP_KERNEL);
5120 if (!eq->buf_list) {
5121 ret = -ENOMEM;
5122 goto free_cmd_mbox;
5123 }
5124
6d10550c 5125 eq->buf_list->buf = dma_zalloc_coherent(dev, buf_chk_sz,
a5073d60
YL		 5126 &(eq->buf_list->map),
5127 GFP_KERNEL);
5128 if (!eq->buf_list->buf) {
5129 ret = -ENOMEM;
5130 goto err_alloc_buf;
5131 }
5132
a5073d60
YL		 5133 } else {
5134 ret = hns_roce_mhop_alloc_eq(hr_dev, eq);
5135 if (ret) {
5136 ret = -ENOMEM;
5137 goto free_cmd_mbox;
5138 }
5139 }
5140
5141 hns_roce_config_eqc(hr_dev, eq, mailbox->buf);
5142
5143 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5144 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5145 if (ret) {
ab178849 5146 dev_err(dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5147 goto err_cmd_mbox;
5148 }
5149
5150 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5151
5152 return 0;
5153
5154err_cmd_mbox:
5155 if (!hr_dev->caps.eqe_hop_num)
5156 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf,
5157 eq->buf_list->map);
5158 else {
5159 hns_roce_mhop_free_eq(hr_dev, eq);
5160 goto free_cmd_mbox;
5161 }
5162
5163err_alloc_buf:
5164 kfree(eq->buf_list);
5165
5166free_cmd_mbox:
5167 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5168
5169 return ret;
5170}
5171
5172static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5173{
5174 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5175 struct device *dev = hr_dev->dev;
5176 struct hns_roce_eq *eq;
5177 unsigned int eq_cmd;
5178 int irq_num;
5179 int eq_num;
5180 int other_num;
5181 int comp_num;
5182 int aeq_num;
5183 int i, j, k;
5184 int ret;
5185
5186 other_num = hr_dev->caps.num_other_vectors;
5187 comp_num = hr_dev->caps.num_comp_vectors;
5188 aeq_num = hr_dev->caps.num_aeq_vectors;
5189
5190 eq_num = comp_num + aeq_num;
5191 irq_num = eq_num + other_num;
5192
5193 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5194 if (!eq_table->eq)
5195 return -ENOMEM;
5196
5197 for (i = 0; i < irq_num; i++) {
5198 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5199 GFP_KERNEL);
5200 if (!hr_dev->irq_names[i]) {
5201 ret = -ENOMEM;
5202 goto err_failed_kzalloc;
5203 }
5204 }
5205
5206 /* create eq */
5207 for (j = 0; j < eq_num; j++) {
5208 eq = &eq_table->eq[j];
5209 eq->hr_dev = hr_dev;
5210 eq->eqn = j;
5211 if (j < comp_num) {
5212 /* CEQ */
5213 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5214 eq->type_flag = HNS_ROCE_CEQ;
5215 eq->entries = hr_dev->caps.ceqe_depth;
5216 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
5217 eq->irq = hr_dev->irq[j + other_num + aeq_num];
5218 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5219 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5220 } else {
5221 /* AEQ */
5222 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5223 eq->type_flag = HNS_ROCE_AEQ;
5224 eq->entries = hr_dev->caps.aeqe_depth;
5225 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
5226 eq->irq = hr_dev->irq[j - comp_num + other_num];
5227 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5228 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5229 }
5230
5231 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5232 if (ret) {
5233 dev_err(dev, "eq create failed.\n");
5234 goto err_create_eq_fail;
5235 }
5236 }
5237
5238 /* enable irq */
5239 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5240
5241 /* irq contains: abnormal + AEQ + CEQ*/
5242 for (k = 0; k < irq_num; k++)
5243 if (k < other_num)
5244 snprintf((char *)hr_dev->irq_names[k],
5245 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k);
5246 else if (k < (other_num + aeq_num))
5247 snprintf((char *)hr_dev->irq_names[k],
5248 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d",
5249 k - other_num);
5250 else
5251 snprintf((char *)hr_dev->irq_names[k],
5252 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d",
5253 k - other_num - aeq_num);
5254
5255 for (k = 0; k < irq_num; k++) {
5256 if (k < other_num)
5257 ret = request_irq(hr_dev->irq[k],
5258 hns_roce_v2_msix_interrupt_abn,
5259 0, hr_dev->irq_names[k], hr_dev);
5260
5261 else if (k < (other_num + comp_num))
5262 ret = request_irq(eq_table->eq[k - other_num].irq,
5263 hns_roce_v2_msix_interrupt_eq,
5264 0, hr_dev->irq_names[k + aeq_num],
5265 &eq_table->eq[k - other_num]);
5266 else
5267 ret = request_irq(eq_table->eq[k - other_num].irq,
5268 hns_roce_v2_msix_interrupt_eq,
5269 0, hr_dev->irq_names[k - comp_num],
5270 &eq_table->eq[k - other_num]);
5271 if (ret) {
5272 dev_err(dev, "Request irq error!\n");
5273 goto err_request_irq_fail;
5274 }
5275 }
5276
0425e3e6
YL		 5277 hr_dev->irq_workq =
5278 create_singlethread_workqueue("hns_roce_irq_workqueue");
5279 if (!hr_dev->irq_workq) {
5280 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5281 ret = -ENOMEM;
0425e3e6
YL		 5282 goto err_request_irq_fail;
5283 }
5284
a5073d60
YL		 5285 return 0;
5286
5287err_request_irq_fail:
5288 for (k -= 1; k >= 0; k--)
5289 if (k < other_num)
5290 free_irq(hr_dev->irq[k], hr_dev);
5291 else
5292 free_irq(eq_table->eq[k - other_num].irq,
5293 &eq_table->eq[k - other_num]);
5294
5295err_create_eq_fail:
5296 for (j -= 1; j >= 0; j--)
5297 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]);
5298
5299err_failed_kzalloc:
5300 for (i -= 1; i >= 0; i--)
5301 kfree(hr_dev->irq_names[i]);
5302 kfree(eq_table->eq);
5303
5304 return ret;
5305}
5306
5307static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5308{
5309 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5310 int irq_num;
5311 int eq_num;
5312 int i;
5313
5314 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5315 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5316
5317 /* Disable irq */
5318 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5319
5320 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5321 free_irq(hr_dev->irq[i], hr_dev);
5322
5323 for (i = 0; i < eq_num; i++) {
5324 hns_roce_v2_destroy_eqc(hr_dev, i);
5325
5326 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]);
5327
5328 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]);
5329 }
5330
5331 for (i = 0; i < irq_num; i++)
5332 kfree(hr_dev->irq_names[i]);
5333
5334 kfree(eq_table->eq);
0425e3e6
YL		 5335
5336 flush_workqueue(hr_dev->irq_workq);
5337 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5338}
5339
a04ff739
WHX		 5340static const struct hns_roce_hw hns_roce_hw_v2 = {
5341 .cmq_init = hns_roce_v2_cmq_init,
5342 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5343 .hw_profile = hns_roce_v2_profile,
6b63597d 5344 .hw_init = hns_roce_v2_init,
5345 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5346 .post_mbox = hns_roce_v2_post_mbox,
5347 .chk_mbox = hns_roce_v2_chk_mbox,
7afddafa
WHX		 5348 .set_gid = hns_roce_v2_set_gid,
5349 .set_mac = hns_roce_v2_set_mac,
3958cc56 5350 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5351 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 5352 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 5353 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 5354 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5355 .set_hem = hns_roce_v2_set_hem,
5356 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5357 .modify_qp = hns_roce_v2_modify_qp,
5358 .query_qp = hns_roce_v2_query_qp,
5359 .destroy_qp = hns_roce_v2_destroy_qp,
b156269d 5360 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5361 .post_send = hns_roce_v2_post_send,
5362 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5363 .req_notify_cq = hns_roce_v2_req_notify_cq,
5364 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5365 .init_eq = hns_roce_v2_init_eq_table,
5366 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
a04ff739 5367};
dd74282d
WHX		 5368
5369static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5370 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5371 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 5372 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
5373 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 5374 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
5375 /* required last entry */
5376 {0, }
5377};
5378
f97a62c3 5379MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
5380
dd74282d
WHX		 5381static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
5382 struct hnae3_handle *handle)
5383{
5384 const struct pci_device_id *id;
a5073d60 5385 int i;
dd74282d
WHX		 5386
5387 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
5388 if (!id) {
5389 dev_err(hr_dev->dev, "device is not compatible!\n");
5390 return -ENXIO;
5391 }
5392
5393 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 5394 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
5395 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 5396
5397 /* Get info from NIC driver. */
5398 hr_dev->reg_base = handle->rinfo.roce_io_base;
5399 hr_dev->caps.num_ports = 1;
5400 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
5401 hr_dev->iboe.phy_port[0] = 0;
5402
d4994d2f 5403 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
5404 hr_dev->iboe.netdevs[0]->dev_addr);
5405
a5073d60
YL		 5406 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
5407 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
5408 i + handle->rinfo.base_vector);
5409
dd74282d 5410 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 5411 hr_dev->cmd_mod = 1;
dd74282d
WHX		 5412 hr_dev->loop_idc = 0;
5413
5414 return 0;
5415}
5416
5417static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
5418{
5419 struct hns_roce_dev *hr_dev;
5420 int ret;
5421
5422 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
5423 if (!hr_dev)
5424 return -ENOMEM;
5425
a04ff739
WHX		 5426 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
5427 if (!hr_dev->priv) {
5428 ret = -ENOMEM;
5429 goto error_failed_kzalloc;
5430 }
5431
dd74282d
WHX		 5432 hr_dev->pci_dev = handle->pdev;
5433 hr_dev->dev = &handle->pdev->dev;
5434 handle->priv = hr_dev;
5435
5436 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
5437 if (ret) {
5438 dev_err(hr_dev->dev, "Get Configuration failed!\n");
5439 goto error_failed_get_cfg;
5440 }
5441
5442 ret = hns_roce_init(hr_dev);
5443 if (ret) {
5444 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
5445 goto error_failed_get_cfg;
5446 }
5447
5448 return 0;
5449
5450error_failed_get_cfg:
a04ff739
WHX		 5451 kfree(hr_dev->priv);
5452
5453error_failed_kzalloc:
dd74282d
WHX		 5454 ib_dealloc_device(&hr_dev->ib_dev);
5455
5456 return ret;
5457}
5458
5459static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
5460 bool reset)
5461{
5462 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5463
cb7a94c9
WHX		 5464 if (!hr_dev)
5465 return;
5466
dd74282d 5467 hns_roce_exit(hr_dev);
a04ff739 5468 kfree(hr_dev->priv);
dd74282d
WHX		 5469 ib_dealloc_device(&hr_dev->ib_dev);
5470}
5471
cb7a94c9
WHX		 5472static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
5473{
5474 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5475 struct ib_event event;
5476
5477 if (!hr_dev) {
5478 dev_err(&handle->pdev->dev,
5479 "Input parameter handle->priv is NULL!\n");
5480 return -EINVAL;
5481 }
5482
5483 hr_dev->active = false;
5484 hr_dev->is_reset = true;
5485
5486 event.event = IB_EVENT_DEVICE_FATAL;
5487 event.device = &hr_dev->ib_dev;
5488 event.element.port_num = 1;
5489 ib_dispatch_event(&event);
5490
5491 return 0;
5492}
5493
5494static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
5495{
5496 int ret;
5497
5498 ret = hns_roce_hw_v2_init_instance(handle);
5499 if (ret) {
5500 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
5501 * callback function, RoCE Engine reinitialize. If RoCE reinit
5502 * failed, we should inform NIC driver.
5503 */
5504 handle->priv = NULL;
5505 dev_err(&handle->pdev->dev,
5506 "In reset process RoCE reinit failed %d.\n", ret);
5507 }
5508
5509 return ret;
5510}
5511
5512static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
5513{
5514 msleep(100);
5515 hns_roce_hw_v2_uninit_instance(handle, false);
5516 return 0;
5517}
5518
5519static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
5520 enum hnae3_reset_notify_type type)
5521{
5522 int ret = 0;
5523
5524 switch (type) {
5525 case HNAE3_DOWN_CLIENT:
5526 ret = hns_roce_hw_v2_reset_notify_down(handle);
5527 break;
5528 case HNAE3_INIT_CLIENT:
5529 ret = hns_roce_hw_v2_reset_notify_init(handle);
5530 break;
5531 case HNAE3_UNINIT_CLIENT:
5532 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
5533 break;
5534 default:
5535 break;
5536 }
5537
5538 return ret;
5539}
5540
dd74282d
WHX		 5541static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
5542 .init_instance = hns_roce_hw_v2_init_instance,
5543 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 5544 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 5545};
5546
5547static struct hnae3_client hns_roce_hw_v2_client = {
5548 .name = "hns_roce_hw_v2",
5549 .type = HNAE3_CLIENT_ROCE,
5550 .ops = &hns_roce_hw_v2_ops,
5551};
5552
5553static int __init hns_roce_hw_v2_init(void)
5554{
5555 return hnae3_register_client(&hns_roce_hw_v2_client);
5556}
5557
5558static void __exit hns_roce_hw_v2_exit(void)
5559{
5560 hnae3_unregister_client(&hns_roce_hw_v2_client);
5561}
5562
5563module_init(hns_roce_hw_v2_init);
5564module_exit(hns_roce_hw_v2_exit);
5565
5566MODULE_LICENSE("Dual BSD/GPL");
5567MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5568MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5569MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
5570MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)