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RDMA/hns: Simplify the qp state convert code
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
a70c0739 40#include <rdma/ib_cache.h>
dd74282d 41#include <rdma/ib_umem.h>
bdeacabd 42#include <rdma/uverbs_ioctl.h>
dd74282d
WHX		 43
44#include "hnae3.h"
45#include "hns_roce_common.h"
46#include "hns_roce_device.h"
47#include "hns_roce_cmd.h"
48#include "hns_roce_hem.h"
a04ff739 49#include "hns_roce_hw_v2.h"
dd74282d 50
2d407888
WHX		 51static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
52 struct ib_sge *sg)
53{
54 dseg->lkey = cpu_to_le32(sg->lkey);
55 dseg->addr = cpu_to_le64(sg->addr);
56 dseg->len = cpu_to_le32(sg->length);
57}
58
e363f7de
XW		 59/*
60 * mapped-value = 1 + real-value
61 * The hns wr opcode real value is start from 0, In order to distinguish between
62 * initialized and uninitialized map values, we plus 1 to the actual value when
63 * defining the mapping, so that the validity can be identified by checking the
64 * mapped value is greater than 0.
65 */
66#define HR_OPC_MAP(ib_key, hr_key) \
67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
68
69static const u32 hns_roce_op_code[] = {
70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
72 HR_OPC_MAP(SEND, SEND),
73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
74 HR_OPC_MAP(RDMA_READ, RDMA_READ),
75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV),
79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
81 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
82};
83
84static u32 to_hr_opcode(u32 ib_opcode)
85{
86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
87 return HNS_ROCE_V2_WQE_OP_MASK;
88
89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
90 HNS_ROCE_V2_WQE_OP_MASK;
91}
92
68a997c5 93static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
00a59d30 94 void *wqe, const struct ib_reg_wr *wr)
68a997c5
YL		 95{
96 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
00a59d30 97 struct hns_roce_wqe_frmr_seg *fseg = wqe;
68a997c5
YL		 98
99 /* use ib_access_flags */
60262b10 100 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
68a997c5 101 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
60262b10 102 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
68a997c5 103 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
60262b10 104 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S,
68a997c5 105 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
60262b10 106 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S,
68a997c5 107 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
60262b10 108 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S,
68a997c5
YL		 109 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
110
111 /* Data structure reuse may lead to confusion */
112 rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff);
113 rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32);
114
115 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
116 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
117 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
118 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
119
120 fseg->pbl_size = cpu_to_le32(mr->pbl_size);
121 roce_set_field(fseg->mode_buf_pg_sz,
122 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
123 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
124 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
125 roce_set_bit(fseg->mode_buf_pg_sz,
126 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
127}
128
00a59d30
XW		 129static void set_atomic_seg(const struct ib_send_wr *wr, void *wqe,
130 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
131 int valid_num_sge)
384f8818 132{
00a59d30
XW		 133 struct hns_roce_wqe_atomic_seg *aseg;
134
135 set_data_seg_v2(wqe, wr->sg_list);
136 aseg = wqe + sizeof(struct hns_roce_v2_wqe_data_seg);
137
138 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
139 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
140 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
384f8818 141 } else {
00a59d30
XW		 142 aseg->fetchadd_swap_data =
143 cpu_to_le64(atomic_wr(wr)->compare_add);
384f8818
LO		 144 aseg->cmp_data = 0;
145 }
00a59d30
XW		 146
147 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
148 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
384f8818
LO		 149}
150
f696bf6d 151static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
468d020e 152 unsigned int *sge_ind, int valid_num_sge)
0b25c9cc
WHX		 153{
154 struct hns_roce_v2_wqe_data_seg *dseg;
155 struct ib_sge *sg;
156 int num_in_wqe = 0;
157 int extend_sge_num;
158 int fi_sge_num;
159 int se_sge_num;
160 int shift;
161 int i;
162
163 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
164 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
468d020e 165 extend_sge_num = valid_num_sge - num_in_wqe;
0b25c9cc 166 sg = wr->sg_list + num_in_wqe;
d563099e 167 shift = qp->mtr.hem_cfg.buf_pg_shift;
0b25c9cc
WHX		 168
169 /*
170 * Check whether wr->num_sge sges are in the same page. If not, we
171 * should calculate how many sges in the first page and the second
172 * page.
173 */
6c6e3921 174 dseg = hns_roce_get_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
0b25c9cc
WHX		 175 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
176 (uintptr_t)dseg) /
177 sizeof(struct hns_roce_v2_wqe_data_seg);
178 if (extend_sge_num > fi_sge_num) {
179 se_sge_num = extend_sge_num - fi_sge_num;
180 for (i = 0; i < fi_sge_num; i++) {
181 set_data_seg_v2(dseg++, sg + i);
182 (*sge_ind)++;
183 }
6c6e3921 184 dseg = hns_roce_get_extend_sge(qp,
0b25c9cc
WHX		 185 (*sge_ind) & (qp->sge.sge_cnt - 1));
186 for (i = 0; i < se_sge_num; i++) {
187 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
188 (*sge_ind)++;
189 }
190 } else {
191 for (i = 0; i < extend_sge_num; i++) {
192 set_data_seg_v2(dseg++, sg + i);
193 (*sge_ind)++;
194 }
195 }
196}
197
f696bf6d 198static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 199 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
200 void *wqe, unsigned int *sge_ind,
00a59d30 201 int valid_num_sge)
7bdee415 202{
203 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
204 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
00a59d30 205 struct ib_device *ibdev = &hr_dev->ib_dev;
7bdee415 206 struct hns_roce_qp *qp = to_hr_qp(ibqp);
468d020e 207 int j = 0;
7bdee415 208 int i;
209
468d020e 210 if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) {
8b9b8d14 211 if (le32_to_cpu(rc_sq_wqe->msg_len) >
212 hr_dev->caps.max_sq_inline) {
00a59d30
XW		 213 ibdev_err(ibdev, "inline len(1-%d)=%d, illegal",
214 rc_sq_wqe->msg_len,
215 hr_dev->caps.max_sq_inline);
7bdee415 216 return -EINVAL;
217 }
218
328d405b 219 if (wr->opcode == IB_WR_RDMA_READ) {
00a59d30 220 ibdev_err(ibdev, "Not support inline data!\n");
328d405b 221 return -EINVAL;
222 }
223
7bdee415 224 for (i = 0; i < wr->num_sge; i++) {
225 memcpy(wqe, ((void *)wr->sg_list[i].addr),
226 wr->sg_list[i].length);
227 wqe += wr->sg_list[i].length;
228 }
229
230 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
231 1);
232 } else {
468d020e 233 if (valid_num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 234 for (i = 0; i < wr->num_sge; i++) {
235 if (likely(wr->sg_list[i].length)) {
236 set_data_seg_v2(dseg, wr->sg_list + i);
237 dseg++;
238 }
239 }
240 } else {
241 roce_set_field(rc_sq_wqe->byte_20,
242 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
243 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
244 (*sge_ind) & (qp->sge.sge_cnt - 1));
245
468d020e
LO		 246 for (i = 0; i < wr->num_sge &&
247 j < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 248 if (likely(wr->sg_list[i].length)) {
249 set_data_seg_v2(dseg, wr->sg_list + i);
250 dseg++;
468d020e 251 j++;
7bdee415 252 }
253 }
254
468d020e 255 set_extend_sge(qp, wr, sge_ind, valid_num_sge);
7bdee415 256 }
257
258 roce_set_field(rc_sq_wqe->byte_16,
259 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
468d020e 260 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
7bdee415 261 }
262
263 return 0;
264}
265
626903e9
XW		 266static int check_send_valid(struct hns_roce_dev *hr_dev,
267 struct hns_roce_qp *hr_qp)
268{
ae1c6148 269 struct ib_device *ibdev = &hr_dev->ib_dev;
626903e9 270 struct ib_qp *ibqp = &hr_qp->ibqp;
626903e9
XW		 271
272 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
273 ibqp->qp_type != IB_QPT_GSI &&
274 ibqp->qp_type != IB_QPT_UD)) {
ae1c6148
LO		 275 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n",
276 ibqp->qp_type);
626903e9
XW		 277 return -EOPNOTSUPP;
278 } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
279 hr_qp->state == IB_QPS_INIT ||
280 hr_qp->state == IB_QPS_RTR)) {
ae1c6148
LO		 281 ibdev_err(ibdev, "failed to post WQE, QP state %d!\n",
282 hr_qp->state);
626903e9
XW		 283 return -EINVAL;
284 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
ae1c6148
LO		 285 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
286 hr_dev->state);
626903e9
XW		 287 return -EIO;
288 }
289
290 return 0;
291}
292
d6a3627e
XW		 293static inline int calc_wr_sge_num(const struct ib_send_wr *wr, u32 *sge_len)
294{
295 int valid_num = 0;
296 u32 len = 0;
297 int i;
298
299 for (i = 0; i < wr->num_sge; i++) {
300 if (likely(wr->sg_list[i].length)) {
301 len += wr->sg_list[i].length;
302 valid_num++;
303 }
304 }
305
306 *sge_len = len;
307 return valid_num;
308}
309
310static inline int set_ud_wqe(struct hns_roce_qp *qp,
311 const struct ib_send_wr *wr,
312 void *wqe, unsigned int *sge_idx,
313 unsigned int owner_bit)
314{
315 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
316 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
317 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
318 unsigned int curr_idx = *sge_idx;
319 int valid_num_sge;
320 u32 msg_len = 0;
321 bool loopback;
322 u8 *smac;
323
324 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
325 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
326
327 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
328 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
329 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
330 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
331 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
332 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
333 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
334 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
335 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
336 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]);
337 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
338 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]);
339
340 /* MAC loopback */
341 smac = (u8 *)hr_dev->dev_addr[qp->port];
342 loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0;
343
344 roce_set_bit(ud_sq_wqe->byte_40,
345 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
346
347 roce_set_field(ud_sq_wqe->byte_4,
348 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
349 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
350 HNS_ROCE_V2_WQE_OP_SEND);
351
352 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
353
354 switch (wr->opcode) {
355 case IB_WR_SEND_WITH_IMM:
356 case IB_WR_RDMA_WRITE_WITH_IMM:
357 ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
358 break;
359 default:
360 ud_sq_wqe->immtdata = 0;
361 break;
362 }
363
364 /* Set sig attr */
365 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S,
366 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
367
368 /* Set se attr */
369 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S,
370 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
371
372 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S,
373 owner_bit);
374
375 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M,
376 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn);
377
378 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
379 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
380
381 roce_set_field(ud_sq_wqe->byte_20,
382 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
383 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
384 curr_idx & (qp->sge.sge_cnt - 1));
385
386 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
387 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
388 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
389 qp->qkey : ud_wr(wr)->remote_qkey);
390 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M,
391 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn);
392
393 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M,
394 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id);
395 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
396 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit);
397 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
398 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass);
399 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
400 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel);
401 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M,
402 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl);
403 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M,
404 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port);
405
406 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
407 ah->av.vlan_en ? 1 : 0);
408 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
409 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index);
410
411 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2);
412
413 set_extend_sge(qp, wr, &curr_idx, valid_num_sge);
414
415 *sge_idx = curr_idx;
416
417 return 0;
418}
419
420static inline int set_rc_wqe(struct hns_roce_qp *qp,
421 const struct ib_send_wr *wr,
422 void *wqe, unsigned int *sge_idx,
423 unsigned int owner_bit)
424{
425 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
426 unsigned int curr_idx = *sge_idx;
427 int valid_num_sge;
428 u32 msg_len = 0;
429 int ret = 0;
430
431 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
432 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
433
434 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
435
436 switch (wr->opcode) {
437 case IB_WR_SEND_WITH_IMM:
438 case IB_WR_RDMA_WRITE_WITH_IMM:
439 rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
440 break;
441 case IB_WR_SEND_WITH_INV:
442 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
443 break;
444 default:
445 rc_sq_wqe->immtdata = 0;
446 break;
447 }
448
449 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
450 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
451
452 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
453 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
454
455 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
456 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
457
458 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
459 owner_bit);
460
461 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
462 switch (wr->opcode) {
463 case IB_WR_RDMA_READ:
464 case IB_WR_RDMA_WRITE:
465 case IB_WR_RDMA_WRITE_WITH_IMM:
466 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
467 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
468 break;
469 case IB_WR_LOCAL_INV:
470 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
471 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
472 break;
473 case IB_WR_REG_MR:
474 set_frmr_seg(rc_sq_wqe, wqe, reg_wr(wr));
475 break;
476 case IB_WR_ATOMIC_CMP_AND_SWP:
477 case IB_WR_ATOMIC_FETCH_AND_ADD:
478 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
479 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
480 break;
481 default:
482 break;
483 }
484
485 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
486 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
487 to_hr_opcode(wr->opcode));
488
489 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
490 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
491 set_atomic_seg(wr, wqe, rc_sq_wqe, valid_num_sge);
492 else if (wr->opcode != IB_WR_REG_MR)
493 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
494 wqe, &curr_idx, valid_num_sge);
495
496 *sge_idx = curr_idx;
497
498 return ret;
499}
500
75c994e6
YL		 501static inline void update_sq_db(struct hns_roce_dev *hr_dev,
502 struct hns_roce_qp *qp)
503{
504 /*
505 * Hip08 hardware cannot flush the WQEs in SQ if the QP state
506 * gets into errored mode. Hence, as a workaround to this
507 * hardware limitation, driver needs to assist in flushing. But
508 * the flushing operation uses mailbox to convey the QP state to
509 * the hardware and which can sleep due to the mutex protection
510 * around the mailbox calls. Hence, use the deferred flush for
511 * now.
512 */
513 if (qp->state == IB_QPS_ERR) {
514 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
515 init_flush_work(hr_dev, qp);
516 } else {
517 struct hns_roce_v2_db sq_db = {};
518
519 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
520 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
521 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
522 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
523 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
524 V2_DB_PARAMETER_IDX_S,
525 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
526 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
527 V2_DB_PARAMETER_SL_S, qp->sl);
528
529 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l);
530 }
531}
532
d34ac5cd
BVA		 533static int hns_roce_v2_post_send(struct ib_qp *ibqp,
534 const struct ib_send_wr *wr,
535 const struct ib_send_wr **bad_wr)
2d407888
WHX		 536{
537 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
d6a3627e 538 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 539 struct hns_roce_qp *qp = to_hr_qp(ibqp);
d6a3627e 540 unsigned long flags = 0;
e8d18533 541 unsigned int owner_bit;
47688202
YL		 542 unsigned int sge_idx;
543 unsigned int wqe_idx;
2d407888 544 void *wqe = NULL;
2d407888 545 int nreq;
626903e9 546 int ret;
2d407888 547
626903e9 548 spin_lock_irqsave(&qp->sq.lock, flags);
2d407888 549
626903e9
XW		 550 ret = check_send_valid(hr_dev, qp);
551 if (ret) {
2d407888 552 *bad_wr = wr;
626903e9
XW		 553 nreq = 0;
554 goto out;
2d407888
WHX		 555 }
556
47688202 557 sge_idx = qp->next_sge;
2d407888
WHX		 558
559 for (nreq = 0; wr; ++nreq, wr = wr->next) {
560 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
561 ret = -ENOMEM;
562 *bad_wr = wr;
563 goto out;
564 }
565
47688202
YL		 566 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
567
2d407888 568 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
d6a3627e
XW		 569 ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n",
570 wr->num_sge, qp->sq.max_gs);
2d407888
WHX		 571 ret = -EINVAL;
572 *bad_wr = wr;
573 goto out;
574 }
575
6c6e3921 576 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
47688202 577 qp->sq.wrid[wqe_idx] = wr->wr_id;
634f6390 578 owner_bit =
579 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
468d020e 580
7bdee415 581 /* Corresponding to the QP type, wqe process separately */
d6a3627e
XW		 582 if (ibqp->qp_type == IB_QPT_GSI)
583 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
584 else if (ibqp->qp_type == IB_QPT_RC)
585 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
d6a3627e
XW		 586
587 if (ret) {
588 *bad_wr = wr;
589 goto out;
590 }
2d407888
WHX		 591 }
592
593out:
594 if (likely(nreq)) {
595 qp->sq.head += nreq;
75c994e6 596 qp->next_sge = sge_idx;
2d407888
WHX		 597 /* Memory barrier */
598 wmb();
75c994e6 599 update_sq_db(hr_dev, qp);
2d407888
WHX		 600 }
601
602 spin_unlock_irqrestore(&qp->sq.lock, flags);
603
604 return ret;
605}
606
626903e9
XW		 607static int check_recv_valid(struct hns_roce_dev *hr_dev,
608 struct hns_roce_qp *hr_qp)
609{
610 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
611 return -EIO;
612 else if (hr_qp->state == IB_QPS_RESET)
613 return -EINVAL;
614
615 return 0;
616}
617
d34ac5cd
BVA		 618static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
619 const struct ib_recv_wr *wr,
620 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 621{
622 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
623 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 624 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 625 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 626 struct hns_roce_rinl_sge *sge_list;
2d407888
WHX		 627 unsigned long flags;
628 void *wqe = NULL;
47688202 629 u32 wqe_idx;
2d407888 630 int nreq;
626903e9 631 int ret;
2d407888
WHX		 632 int i;
633
634 spin_lock_irqsave(&hr_qp->rq.lock, flags);
2d407888 635
626903e9
XW		 636 ret = check_recv_valid(hr_dev, hr_qp);
637 if (ret) {
2d407888 638 *bad_wr = wr;
626903e9
XW		 639 nreq = 0;
640 goto out;
2d407888
WHX		 641 }
642
643 for (nreq = 0; wr; ++nreq, wr = wr->next) {
644 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
645 hr_qp->ibqp.recv_cq)) {
646 ret = -ENOMEM;
647 *bad_wr = wr;
648 goto out;
649 }
650
47688202
YL		 651 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
652
2d407888 653 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
ae1c6148
LO		 654 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n",
655 wr->num_sge, hr_qp->rq.max_gs);
2d407888
WHX		 656 ret = -EINVAL;
657 *bad_wr = wr;
658 goto out;
659 }
660
6c6e3921 661 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
2d407888
WHX		 662 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
663 for (i = 0; i < wr->num_sge; i++) {
664 if (!wr->sg_list[i].length)
665 continue;
666 set_data_seg_v2(dseg, wr->sg_list + i);
667 dseg++;
668 }
669
670 if (i < hr_qp->rq.max_gs) {
778cc5a8 671 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
672 dseg->addr = 0;
2d407888
WHX		 673 }
674
0009c2db 675 /* rq support inline data */
ecaaf1e2 676 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
47688202
YL		 677 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
678 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt =
ecaaf1e2 679 (u32)wr->num_sge;
680 for (i = 0; i < wr->num_sge; i++) {
681 sge_list[i].addr =
682 (void *)(u64)wr->sg_list[i].addr;
683 sge_list[i].len = wr->sg_list[i].length;
684 }
0009c2db 685 }
686
47688202 687 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
2d407888
WHX		 688 }
689
690out:
691 if (likely(nreq)) {
692 hr_qp->rq.head += nreq;
693 /* Memory barrier */
694 wmb();
695
b5374286
YL		 696 /*
697 * Hip08 hardware cannot flush the WQEs in RQ if the QP state
698 * gets into errored mode. Hence, as a workaround to this
699 * hardware limitation, driver needs to assist in flushing. But
700 * the flushing operation uses mailbox to convey the QP state to
701 * the hardware and which can sleep due to the mutex protection
702 * around the mailbox calls. Hence, use the deferred flush for
703 * now.
704 */
75c994e6 705 if (hr_qp->state == IB_QPS_ERR) {
b5374286
YL		 706 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG,
707 &hr_qp->flush_flag))
708 init_flush_work(hr_dev, hr_qp);
75c994e6
YL		 709 } else {
710 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
711 }
2d407888
WHX		 712 }
713 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
714
715 return ret;
716}
717
6a04aed6
WHX		 718static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
719 unsigned long instance_stage,
720 unsigned long reset_stage)
721{
722 /* When hardware reset has been completed once or more, we should stop
d3743fa9 723 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
6a04aed6
WHX		 724 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
725 * stage of soft reset process, we should exit with error, and then
726 * HNAE3_INIT_CLIENT related process can rollback the operation like
727 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
728 * process will exit with error to notify NIC driver to reschedule soft
729 * reset process once again.
730 */
731 hr_dev->is_reset = true;
d3743fa9 732 hr_dev->dis_db = true;
6a04aed6
WHX		 733
734 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
735 instance_stage == HNS_ROCE_STATE_INIT)
736 return CMD_RST_PRC_EBUSY;
737
738 return CMD_RST_PRC_SUCCESS;
739}
740
741static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
742 unsigned long instance_stage,
743 unsigned long reset_stage)
744{
745 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
746 struct hnae3_handle *handle = priv->handle;
747 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
748
d3743fa9
WHX		 749 /* When hardware reset is detected, we should stop sending mailbox&cmq&
750 * doorbell to hardware. If now in .init_instance() function, we should
6a04aed6
WHX		 751 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
752 * process, we should exit with error, and then HNAE3_INIT_CLIENT
753 * related process can rollback the operation like notifing hardware to
754 * free resources, HNAE3_INIT_CLIENT related process will exit with
755 * error to notify NIC driver to reschedule soft reset process once
756 * again.
757 */
d3743fa9 758 hr_dev->dis_db = true;
6a04aed6
WHX		 759 if (!ops->get_hw_reset_stat(handle))
760 hr_dev->is_reset = true;
761
762 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
763 instance_stage == HNS_ROCE_STATE_INIT)
764 return CMD_RST_PRC_EBUSY;
765
766 return CMD_RST_PRC_SUCCESS;
767}
768
769static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
770{
771 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
772 struct hnae3_handle *handle = priv->handle;
773 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
774
775 /* When software reset is detected at .init_instance() function, we
d3743fa9
WHX		 776 * should stop sending mailbox&cmq&doorbell to hardware, and exit
777 * with error.
6a04aed6 778 */
d3743fa9 779 hr_dev->dis_db = true;
6a04aed6
WHX		 780 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
781 hr_dev->is_reset = true;
782
783 return CMD_RST_PRC_EBUSY;
784}
785
786static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
787{
788 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
789 struct hnae3_handle *handle = priv->handle;
790 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
791 unsigned long instance_stage; /* the current instance stage */
792 unsigned long reset_stage; /* the current reset stage */
793 unsigned long reset_cnt;
794 bool sw_resetting;
795 bool hw_resetting;
796
797 if (hr_dev->is_reset)
798 return CMD_RST_PRC_SUCCESS;
799
800 /* Get information about reset from NIC driver or RoCE driver itself,
801 * the meaning of the following variables from NIC driver are described
802 * as below:
803 * reset_cnt -- The count value of completed hardware reset.
804 * hw_resetting -- Whether hardware device is resetting now.
805 * sw_resetting -- Whether NIC's software reset process is running now.
806 */
807 instance_stage = handle->rinfo.instance_state;
808 reset_stage = handle->rinfo.reset_state;
809 reset_cnt = ops->ae_dev_reset_cnt(handle);
810 hw_resetting = ops->get_hw_reset_stat(handle);
811 sw_resetting = ops->ae_dev_resetting(handle);
812
813 if (reset_cnt != hr_dev->reset_cnt)
814 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
815 reset_stage);
816 else if (hw_resetting)
817 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
818 reset_stage);
819 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
820 return hns_roce_v2_cmd_sw_resetting(hr_dev);
821
822 return 0;
823}
824
a04ff739
WHX		 825static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
826{
827 int ntu = ring->next_to_use;
828 int ntc = ring->next_to_clean;
829 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
830
831 return ring->desc_num - used - 1;
832}
833
834static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
835 struct hns_roce_v2_cmq_ring *ring)
836{
837 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
838
839 ring->desc = kzalloc(size, GFP_KERNEL);
840 if (!ring->desc)
841 return -ENOMEM;
842
843 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
844 DMA_BIDIRECTIONAL);
845 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
846 ring->desc_dma_addr = 0;
847 kfree(ring->desc);
848 ring->desc = NULL;
849 return -ENOMEM;
850 }
851
852 return 0;
853}
854
855static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
856 struct hns_roce_v2_cmq_ring *ring)
857{
858 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
859 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
860 DMA_BIDIRECTIONAL);
90e7a4d5 861
862 ring->desc_dma_addr = 0;
a04ff739
WHX		 863 kfree(ring->desc);
864}
865
866static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
867{
868 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
869 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
870 &priv->cmq.csq : &priv->cmq.crq;
871
872 ring->flag = ring_type;
873 ring->next_to_clean = 0;
874 ring->next_to_use = 0;
875
876 return hns_roce_alloc_cmq_desc(hr_dev, ring);
877}
878
879static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
880{
881 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
882 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
883 &priv->cmq.csq : &priv->cmq.crq;
884 dma_addr_t dma = ring->desc_dma_addr;
885
886 if (ring_type == TYPE_CSQ) {
887 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
888 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
889 upper_32_bits(dma));
890 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
2288b3b3 891 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 892 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
893 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
894 } else {
895 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
896 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
897 upper_32_bits(dma));
898 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
2288b3b3 899 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 900 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
901 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
902 }
903}
904
905static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
906{
907 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
908 int ret;
909
910 /* Setup the queue entries for command queue */
426c4146
LO		 911 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
912 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 913
914 /* Setup the lock for command queue */
915 spin_lock_init(&priv->cmq.csq.lock);
916 spin_lock_init(&priv->cmq.crq.lock);
917
918 /* Setup Tx write back timeout */
919 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
920
921 /* Init CSQ */
922 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
923 if (ret) {
924 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
925 return ret;
926 }
927
928 /* Init CRQ */
929 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
930 if (ret) {
931 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
932 goto err_crq;
933 }
934
935 /* Init CSQ REG */
936 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
937
938 /* Init CRQ REG */
939 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
940
941 return 0;
942
943err_crq:
944 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
945
946 return ret;
947}
948
949static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
950{
951 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
952
953 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
954 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
955}
956
281d0ccf
CIK		 957static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
958 enum hns_roce_opcode_type opcode,
959 bool is_read)
a04ff739
WHX		 960{
961 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
962 desc->opcode = cpu_to_le16(opcode);
963 desc->flag =
964 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
965 if (is_read)
966 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
967 else
968 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
969}
970
971static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
972{
973 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
974 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
975
976 return head == priv->cmq.csq.next_to_use;
977}
978
979static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
980{
981 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
982 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
983 struct hns_roce_cmq_desc *desc;
984 u16 ntc = csq->next_to_clean;
985 u32 head;
986 int clean = 0;
987
988 desc = &csq->desc[ntc];
989 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
990 while (head != ntc) {
991 memset(desc, 0, sizeof(*desc));
992 ntc++;
993 if (ntc == csq->desc_num)
994 ntc = 0;
995 desc = &csq->desc[ntc];
996 clean++;
997 }
998 csq->next_to_clean = ntc;
999
1000 return clean;
1001}
1002
6a04aed6
WHX		 1003static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1004 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 1005{
1006 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1007 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1008 struct hns_roce_cmq_desc *desc_to_use;
1009 bool complete = false;
1010 u32 timeout = 0;
1011 int handle = 0;
1012 u16 desc_ret;
1013 int ret = 0;
1014 int ntc;
1015
1016 spin_lock_bh(&csq->lock);
1017
1018 if (num > hns_roce_cmq_space(csq)) {
1019 spin_unlock_bh(&csq->lock);
1020 return -EBUSY;
1021 }
1022
1023 /*
1024 * Record the location of desc in the cmq for this time
1025 * which will be use for hardware to write back
1026 */
1027 ntc = csq->next_to_use;
1028
1029 while (handle < num) {
1030 desc_to_use = &csq->desc[csq->next_to_use];
1031 *desc_to_use = desc[handle];
1032 dev_dbg(hr_dev->dev, "set cmq desc:\n");
1033 csq->next_to_use++;
1034 if (csq->next_to_use == csq->desc_num)
1035 csq->next_to_use = 0;
1036 handle++;
1037 }
1038
1039 /* Write to hardware */
1040 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
1041
1042 /*
1043 * If the command is sync, wait for the firmware to write back,
1044 * if multi descriptors to be sent, use the first one to check
1045 */
bfe86035 1046 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
a04ff739
WHX		 1047 do {
1048 if (hns_roce_cmq_csq_done(hr_dev))
1049 break;
988e175b 1050 udelay(1);
a04ff739
WHX		 1051 timeout++;
1052 } while (timeout < priv->cmq.tx_timeout);
1053 }
1054
1055 if (hns_roce_cmq_csq_done(hr_dev)) {
1056 complete = true;
1057 handle = 0;
1058 while (handle < num) {
1059 /* get the result of hardware write back */
1060 desc_to_use = &csq->desc[ntc];
1061 desc[handle] = *desc_to_use;
1062 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
bfe86035 1063 desc_ret = le16_to_cpu(desc[handle].retval);
a04ff739
WHX		 1064 if (desc_ret == CMD_EXEC_SUCCESS)
1065 ret = 0;
1066 else
1067 ret = -EIO;
1068 priv->cmq.last_status = desc_ret;
1069 ntc++;
1070 handle++;
1071 if (ntc == csq->desc_num)
1072 ntc = 0;
1073 }
1074 }
1075
1076 if (!complete)
1077 ret = -EAGAIN;
1078
1079 /* clean the command send queue */
1080 handle = hns_roce_cmq_csq_clean(hr_dev);
1081 if (handle != num)
1082 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
1083 handle, num);
1084
1085 spin_unlock_bh(&csq->lock);
1086
1087 return ret;
1088}
1089
e95e52a1 1090static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
6a04aed6
WHX		 1091 struct hns_roce_cmq_desc *desc, int num)
1092{
1093 int retval;
1094 int ret;
1095
1096 ret = hns_roce_v2_rst_process_cmd(hr_dev);
1097 if (ret == CMD_RST_PRC_SUCCESS)
1098 return 0;
1099 if (ret == CMD_RST_PRC_EBUSY)
b417c087 1100 return -EBUSY;
6a04aed6
WHX		 1101
1102 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1103 if (ret) {
1104 retval = hns_roce_v2_rst_process_cmd(hr_dev);
1105 if (retval == CMD_RST_PRC_SUCCESS)
1106 return 0;
1107 else if (retval == CMD_RST_PRC_EBUSY)
b417c087 1108 return -EBUSY;
6a04aed6
WHX		 1109 }
1110
1111 return ret;
1112}
1113
281d0ccf 1114static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 1115{
1116 struct hns_roce_query_version *resp;
1117 struct hns_roce_cmq_desc desc;
1118 int ret;
1119
1120 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1121 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1122 if (ret)
1123 return ret;
1124
1125 resp = (struct hns_roce_query_version *)desc.data;
bfe86035 1126 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 1127 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1128
1129 return 0;
1130}
1131
e075da5e
LC		 1132static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev)
1133{
1134 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1135 struct hnae3_handle *handle = priv->handle;
1136 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1137 unsigned long reset_cnt;
1138 bool sw_resetting;
1139 bool hw_resetting;
1140
1141 reset_cnt = ops->ae_dev_reset_cnt(handle);
1142 hw_resetting = ops->get_hw_reset_stat(handle);
1143 sw_resetting = ops->ae_dev_resetting(handle);
1144
1145 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting)
1146 return true;
1147
1148 return false;
1149}
1150
1151static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval,
1152 int flag)
1153{
1154 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1155 struct hnae3_handle *handle = priv->handle;
1156 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1157 unsigned long instance_stage;
1158 unsigned long reset_cnt;
1159 unsigned long end;
1160 bool sw_resetting;
1161 bool hw_resetting;
1162
1163 instance_stage = handle->rinfo.instance_state;
1164 reset_cnt = ops->ae_dev_reset_cnt(handle);
1165 hw_resetting = ops->get_hw_reset_stat(handle);
1166 sw_resetting = ops->ae_dev_resetting(handle);
1167
1168 if (reset_cnt != hr_dev->reset_cnt) {
1169 hr_dev->dis_db = true;
1170 hr_dev->is_reset = true;
1171 dev_info(hr_dev->dev, "Func clear success after reset.\n");
1172 } else if (hw_resetting) {
1173 hr_dev->dis_db = true;
1174
1175 dev_warn(hr_dev->dev,
1176 "Func clear is pending, device in resetting state.\n");
1177 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1178 while (end) {
1179 if (!ops->get_hw_reset_stat(handle)) {
1180 hr_dev->is_reset = true;
1181 dev_info(hr_dev->dev,
1182 "Func clear success after reset.\n");
1183 return;
1184 }
1185 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1186 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1187 }
1188
1189 dev_warn(hr_dev->dev, "Func clear failed.\n");
1190 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) {
1191 hr_dev->dis_db = true;
1192
1193 dev_warn(hr_dev->dev,
1194 "Func clear is pending, device in resetting state.\n");
1195 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1196 while (end) {
1197 if (ops->ae_dev_reset_cnt(handle) !=
1198 hr_dev->reset_cnt) {
1199 hr_dev->is_reset = true;
1200 dev_info(hr_dev->dev,
1201 "Func clear success after sw reset\n");
1202 return;
1203 }
1204 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1205 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1206 }
1207
1208 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
1209 } else {
1210 if (retval && !flag)
1211 dev_warn(hr_dev->dev,
1212 "Func clear read failed, ret = %d.\n", retval);
1213
1214 dev_warn(hr_dev->dev, "Func clear failed.\n");
1215 }
1216}
89a6da3c
LC		 1217static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1218{
e075da5e 1219 bool fclr_write_fail_flag = false;
89a6da3c
LC		 1220 struct hns_roce_func_clear *resp;
1221 struct hns_roce_cmq_desc desc;
1222 unsigned long end;
e075da5e
LC		 1223 int ret = 0;
1224
1225 if (hns_roce_func_clr_chk_rst(hr_dev))
1226 goto out;
89a6da3c
LC		 1227
1228 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1229 resp = (struct hns_roce_func_clear *)desc.data;
1230
1231 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1232 if (ret) {
e075da5e 1233 fclr_write_fail_flag = true;
89a6da3c
LC		 1234 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n",
1235 ret);
e075da5e 1236 goto out;
89a6da3c
LC		 1237 }
1238
1239 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1240 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1241 while (end) {
e075da5e
LC		 1242 if (hns_roce_func_clr_chk_rst(hr_dev))
1243 goto out;
89a6da3c
LC		 1244 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1245 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1246
1247 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1248 true);
1249
1250 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1251 if (ret)
1252 continue;
1253
1254 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) {
1255 hr_dev->is_reset = true;
1256 return;
1257 }
1258 }
1259
e075da5e 1260out:
e075da5e 1261 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag);
89a6da3c
LC		 1262}
1263
3a63c964
LO		 1264static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1265{
1266 struct hns_roce_query_fw_info *resp;
1267 struct hns_roce_cmq_desc desc;
1268 int ret;
1269
1270 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1271 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1272 if (ret)
1273 return ret;
1274
1275 resp = (struct hns_roce_query_fw_info *)desc.data;
1276 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1277
1278 return 0;
1279}
1280
1281static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1282{
1283 struct hns_roce_cfg_global_param *req;
1284 struct hns_roce_cmq_desc desc;
1285
1286 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1287 false);
1288
1289 req = (struct hns_roce_cfg_global_param *)desc.data;
1290 memset(req, 0, sizeof(*req));
1291 roce_set_field(req->time_cfg_udp_port,
1292 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1293 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1294 roce_set_field(req->time_cfg_udp_port,
1295 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1296 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1297
1298 return hns_roce_cmq_send(hr_dev, &desc, 1);
1299}
1300
1301static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1302{
1303 struct hns_roce_cmq_desc desc[2];
6b63597d 1304 struct hns_roce_pf_res_a *req_a;
1305 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1306 int ret;
1307 int i;
1308
1309 for (i = 0; i < 2; i++) {
1310 hns_roce_cmq_setup_basic_desc(&desc[i],
1311 HNS_ROCE_OPC_QUERY_PF_RES, true);
1312
1313 if (i == 0)
1314 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1315 else
1316 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1317 }
1318
1319 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1320 if (ret)
1321 return ret;
1322
6b63597d 1323 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1324 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1325
6b63597d 1326 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1327 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1328 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1329 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1330 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1331 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1332 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1333 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1334 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1335 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1336 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1337 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1338
6b63597d 1339 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1340 PF_RES_DATA_3_PF_SL_NUM_M,
1341 PF_RES_DATA_3_PF_SL_NUM_S);
6a157f7d
YL		 1342 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,
1343 PF_RES_DATA_4_PF_SCCC_BT_NUM_M,
1344 PF_RES_DATA_4_PF_SCCC_BT_NUM_S);
6b63597d 1345
cfc85f3e
WHX		 1346 return 0;
1347}
1348
0e40dc2f
YL		 1349static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
1350{
1351 struct hns_roce_pf_timer_res_a *req_a;
1352 struct hns_roce_cmq_desc desc[2];
1353 int ret, i;
1354
1355 for (i = 0; i < 2; i++) {
1356 hns_roce_cmq_setup_basic_desc(&desc[i],
1357 HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1358 true);
1359
1360 if (i == 0)
1361 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1362 else
1363 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1364 }
1365
1366 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1367 if (ret)
1368 return ret;
1369
1370 req_a = (struct hns_roce_pf_timer_res_a *)desc[0].data;
1371
1372 hr_dev->caps.qpc_timer_bt_num =
1373 roce_get_field(req_a->qpc_timer_bt_idx_num,
1374 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
1375 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
1376 hr_dev->caps.cqc_timer_bt_num =
1377 roce_get_field(req_a->cqc_timer_bt_idx_num,
1378 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
1379 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
1380
1381 return 0;
1382}
1383
60262b10 1384static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id)
0c1c3880
LO		 1385{
1386 struct hns_roce_cmq_desc desc;
1387 struct hns_roce_vf_switch *swt;
1388 int ret;
1389
1390 swt = (struct hns_roce_vf_switch *)desc.data;
1391 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
bfe86035 1392 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
60262b10
LO		 1393 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1394 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id);
0c1c3880
LO		 1395 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1396 if (ret)
1397 return ret;
60262b10 1398
0c1c3880
LO		 1399 desc.flag =
1400 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1401 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1402 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
d967e262 1403 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0);
0c1c3880
LO		 1404 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1405
1406 return hns_roce_cmq_send(hr_dev, &desc, 1);
1407}
1408
cfc85f3e
WHX		 1409static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1410{
1411 struct hns_roce_cmq_desc desc[2];
1412 struct hns_roce_vf_res_a *req_a;
1413 struct hns_roce_vf_res_b *req_b;
1414 int i;
1415
1416 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1417 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1418 memset(req_a, 0, sizeof(*req_a));
1419 memset(req_b, 0, sizeof(*req_b));
1420 for (i = 0; i < 2; i++) {
1421 hns_roce_cmq_setup_basic_desc(&desc[i],
1422 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1423
1424 if (i == 0)
1425 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1426 else
1427 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
cfc85f3e
WHX		 1428 }
1429
99e713f8
LO		 1430 roce_set_field(req_a->vf_qpc_bt_idx_num,
1431 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1432 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1433 roce_set_field(req_a->vf_qpc_bt_idx_num,
1434 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1435 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM);
1436
1437 roce_set_field(req_a->vf_srqc_bt_idx_num,
1438 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1439 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1440 roce_set_field(req_a->vf_srqc_bt_idx_num,
1441 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1442 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1443 HNS_ROCE_VF_SRQC_BT_NUM);
1444
1445 roce_set_field(req_a->vf_cqc_bt_idx_num,
1446 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1447 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1448 roce_set_field(req_a->vf_cqc_bt_idx_num,
1449 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1450 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM);
1451
1452 roce_set_field(req_a->vf_mpt_bt_idx_num,
1453 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1454 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1455 roce_set_field(req_a->vf_mpt_bt_idx_num,
1456 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1457 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM);
1458
1459 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M,
1460 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1461 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M,
1462 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM);
1463
1464 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1465 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1466 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1467 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM);
1468
1469 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M,
1470 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1471 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M,
1472 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM);
1473
1474 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M,
1475 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1476 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M,
1477 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM);
1478
1479 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,
1480 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);
1481 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,
1482 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,
1483 HNS_ROCE_VF_SCCC_BT_NUM);
1484
cfc85f3e
WHX		 1485 return hns_roce_cmq_send(hr_dev, desc, 2);
1486}
1487
a81fba28
WHX		 1488static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1489{
1490 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1491 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1492 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1493 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
6a157f7d 1494 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;
a81fba28
WHX		 1495 struct hns_roce_cfg_bt_attr *req;
1496 struct hns_roce_cmq_desc desc;
1497
1498 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1499 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1500 memset(req, 0, sizeof(*req));
1501
1502 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1503 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1504 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1505 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1506 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1507 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1508 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1509 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1510 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1511
1512 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1513 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1514 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1515 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1516 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1517 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1518 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1519 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1520 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1521
1522 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1523 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1524 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1525 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1526 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1527 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1528 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1529 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1530 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1531
1532 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1533 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1534 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1535 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1536 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1537 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1538 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1539 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1540 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1541
6a157f7d
YL		 1542 roce_set_field(req->vf_sccc_cfg,
1543 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,
1544 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,
1545 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1546 roce_set_field(req->vf_sccc_cfg,
1547 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,
1548 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,
1549 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1550 roce_set_field(req->vf_sccc_cfg,
1551 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,
1552 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,
1553 sccc_hop_num ==
1554 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);
1555
a81fba28
WHX		 1556 return hns_roce_cmq_send(hr_dev, &desc, 1);
1557}
1558
ba6bb7e9
LO		 1559static void set_default_caps(struct hns_roce_dev *hr_dev)
1560{
1561 struct hns_roce_caps *caps = &hr_dev->caps;
1562
1563 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1564 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1565 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1566 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
1567 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1568 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1569 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1570 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
1571 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1572 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1573 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1574 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
1575 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1576 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1577 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1578 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1579 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1580 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1581 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1582 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1583 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1584 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1585 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1586 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1587 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1588 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1589 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1590 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
7db82697 1591 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
ba6bb7e9
LO		 1592 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1593 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1594 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1595 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1596 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ;
1597 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1598 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1599 caps->reserved_lkey = 0;
1600 caps->reserved_pds = 0;
1601 caps->reserved_mrws = 1;
1602 caps->reserved_uars = 0;
1603 caps->reserved_cqs = 0;
1604 caps->reserved_srqs = 0;
1605 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
1606
1607 caps->qpc_ba_pg_sz = 0;
1608 caps->qpc_buf_pg_sz = 0;
1609 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1610 caps->srqc_ba_pg_sz = 0;
1611 caps->srqc_buf_pg_sz = 0;
1612 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1613 caps->cqc_ba_pg_sz = 0;
1614 caps->cqc_buf_pg_sz = 0;
1615 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1616 caps->mpt_ba_pg_sz = 0;
1617 caps->mpt_buf_pg_sz = 0;
1618 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1619 caps->mtt_ba_pg_sz = 0;
1620 caps->mtt_buf_pg_sz = 0;
1621 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1622 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM;
1623 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM;
1624 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM;
1625 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
1626 caps->cqe_buf_pg_sz = 0;
1627 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
1628 caps->srqwqe_ba_pg_sz = 0;
1629 caps->srqwqe_buf_pg_sz = 0;
1630 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
1631 caps->idx_ba_pg_sz = 0;
1632 caps->idx_buf_pg_sz = 0;
1633 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
1634 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
1635
1636 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
1637 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
1638 HNS_ROCE_CAP_FLAG_RQ_INLINE |
1639 HNS_ROCE_CAP_FLAG_RECORD_DB |
1640 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
1641
1642 caps->pkey_table_len[0] = 1;
1643 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
1644 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1645 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
1646 caps->local_ca_ack_delay = 0;
1647 caps->max_mtu = IB_MTU_4096;
1648
1649 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1650 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1651
dfaf2854 1652 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
ba6bb7e9
LO		 1653 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
1654 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
1655 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
1656
1657 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1658 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1659 caps->qpc_timer_ba_pg_sz = 0;
1660 caps->qpc_timer_buf_pg_sz = 0;
1661 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1662 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1663 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1664 caps->cqc_timer_ba_pg_sz = 0;
1665 caps->cqc_timer_buf_pg_sz = 0;
1666 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1667
1668 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
1669 caps->sccc_ba_pg_sz = 0;
1670 caps->sccc_buf_pg_sz = 0;
1671 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
1672 }
1673}
1674
1675static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
1676 int *buf_page_size, int *bt_page_size, u32 hem_type)
1677{
1678 u64 obj_per_chunk;
1679 int bt_chunk_size = 1 << PAGE_SHIFT;
1680 int buf_chunk_size = 1 << PAGE_SHIFT;
1681 int obj_per_chunk_default = buf_chunk_size / obj_size;
1682
1683 *buf_page_size = 0;
1684 *bt_page_size = 0;
1685
1686 switch (hop_num) {
1687 case 3:
1688 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1689 (bt_chunk_size / BA_BYTE_LEN) *
1690 (bt_chunk_size / BA_BYTE_LEN) *
1691 obj_per_chunk_default;
1692 break;
1693 case 2:
1694 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1695 (bt_chunk_size / BA_BYTE_LEN) *
1696 obj_per_chunk_default;
1697 break;
1698 case 1:
1699 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1700 obj_per_chunk_default;
1701 break;
1702 case HNS_ROCE_HOP_NUM_0:
1703 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1704 break;
1705 default:
1706 pr_err("Table %d not support hop_num = %d!\n", hem_type,
1707 hop_num);
1708 return;
1709 }
1710
1711 if (hem_type >= HEM_TYPE_MTT)
1712 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1713 else
1714 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1715}
1716
1717static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
1718{
1719 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
1720 struct hns_roce_caps *caps = &hr_dev->caps;
1721 struct hns_roce_query_pf_caps_a *resp_a;
1722 struct hns_roce_query_pf_caps_b *resp_b;
1723 struct hns_roce_query_pf_caps_c *resp_c;
1724 struct hns_roce_query_pf_caps_d *resp_d;
1725 struct hns_roce_query_pf_caps_e *resp_e;
1726 int ctx_hop_num;
1727 int pbl_hop_num;
1728 int ret;
1729 int i;
1730
1731 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
1732 hns_roce_cmq_setup_basic_desc(&desc[i],
1733 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
1734 true);
1735 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
1736 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1737 else
1738 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1739 }
1740
1741 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
1742 if (ret)
1743 return ret;
1744
1745 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
1746 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
1747 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
1748 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
1749 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
1750
1751 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
1752 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
1753 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
1754 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
1755 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg);
1756 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer);
1757 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer);
1758 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
1759 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
1760 caps->num_other_vectors = resp_a->num_other_vectors;
1761 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
1762 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
1763 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz;
1764 caps->cq_entry_sz = resp_a->cq_entry_sz;
1765
1766 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
1767 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
1768 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
1769 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
1770 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
1771 caps->idx_entry_sz = resp_b->idx_entry_sz;
1772 caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz;
1773 caps->max_mtu = resp_b->max_mtu;
1774 caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz);
1775 caps->min_cqes = resp_b->min_cqes;
1776 caps->min_wqes = resp_b->min_wqes;
1777 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
1778 caps->pkey_table_len[0] = resp_b->pkey_table_len;
1779 caps->phy_num_uars = resp_b->phy_num_uars;
1780 ctx_hop_num = resp_b->ctx_hop_num;
1781 pbl_hop_num = resp_b->pbl_hop_num;
1782
1783 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds,
1784 V2_QUERY_PF_CAPS_C_NUM_PDS_M,
1785 V2_QUERY_PF_CAPS_C_NUM_PDS_S);
1786 caps->flags = roce_get_field(resp_c->cap_flags_num_pds,
1787 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M,
1788 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S);
1789 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs,
1790 V2_QUERY_PF_CAPS_C_NUM_CQS_M,
1791 V2_QUERY_PF_CAPS_C_NUM_CQS_S);
1792 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs,
1793 V2_QUERY_PF_CAPS_C_MAX_GID_M,
1794 V2_QUERY_PF_CAPS_C_MAX_GID_S);
1795 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth,
1796 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M,
1797 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S);
1798 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws,
1799 V2_QUERY_PF_CAPS_C_NUM_MRWS_M,
1800 V2_QUERY_PF_CAPS_C_NUM_MRWS_S);
1801 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps,
1802 V2_QUERY_PF_CAPS_C_NUM_QPS_M,
1803 V2_QUERY_PF_CAPS_C_NUM_QPS_S);
1804 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps,
1805 V2_QUERY_PF_CAPS_C_MAX_ORD_M,
1806 V2_QUERY_PF_CAPS_C_MAX_ORD_S);
1807 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
1808 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
1809 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs,
1810 V2_QUERY_PF_CAPS_D_NUM_SRQS_M,
1811 V2_QUERY_PF_CAPS_D_NUM_SRQS_S);
1812 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
1813 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth,
1814 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M,
1815 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S);
1816 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth,
1817 V2_QUERY_PF_CAPS_D_NUM_CEQS_M,
1818 V2_QUERY_PF_CAPS_D_NUM_CEQS_S);
1819 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth,
1820 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M,
1821 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S);
1822 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1823 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M,
1824 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S);
1825 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1826 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M,
1827 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S);
1828 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds,
1829 V2_QUERY_PF_CAPS_D_RSV_PDS_M,
1830 V2_QUERY_PF_CAPS_D_RSV_PDS_S);
1831 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds,
1832 V2_QUERY_PF_CAPS_D_NUM_UARS_M,
1833 V2_QUERY_PF_CAPS_D_NUM_UARS_S);
1834 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps,
1835 V2_QUERY_PF_CAPS_D_RSV_QPS_M,
1836 V2_QUERY_PF_CAPS_D_RSV_QPS_S);
1837 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps,
1838 V2_QUERY_PF_CAPS_D_RSV_UARS_M,
1839 V2_QUERY_PF_CAPS_D_RSV_UARS_S);
1840 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1841 V2_QUERY_PF_CAPS_E_RSV_MRWS_M,
1842 V2_QUERY_PF_CAPS_E_RSV_MRWS_S);
1843 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1844 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M,
1845 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S);
1846 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs,
1847 V2_QUERY_PF_CAPS_E_RSV_CQS_M,
1848 V2_QUERY_PF_CAPS_E_RSV_CQS_S);
1849 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs,
1850 V2_QUERY_PF_CAPS_E_RSV_SRQS_M,
1851 V2_QUERY_PF_CAPS_E_RSV_SRQS_S);
1852 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey,
1853 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M,
1854 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S);
1855 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
1856 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
1857 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
1858 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
1859
1860 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1861 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1862 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1863 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1864 caps->mtt_ba_pg_sz = 0;
1865 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1866 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1867 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1868
1869 caps->qpc_hop_num = ctx_hop_num;
1870 caps->srqc_hop_num = ctx_hop_num;
1871 caps->cqc_hop_num = ctx_hop_num;
1872 caps->mpt_hop_num = ctx_hop_num;
1873 caps->mtt_hop_num = pbl_hop_num;
1874 caps->cqe_hop_num = pbl_hop_num;
1875 caps->srqwqe_hop_num = pbl_hop_num;
1876 caps->idx_hop_num = pbl_hop_num;
1877 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1878 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M,
1879 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S);
1880 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1881 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M,
1882 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S);
1883 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1884 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
1885 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
1886
1887 calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
1888 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
1889 HEM_TYPE_QPC);
1890 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
1891 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
1892 HEM_TYPE_MTPT);
1893 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
1894 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
1895 HEM_TYPE_CQC);
1896 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num,
1897 caps->srqc_bt_num, &caps->srqc_buf_pg_sz,
1898 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC);
1899
dfaf2854 1900 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
ba6bb7e9
LO		 1901 caps->sccc_hop_num = ctx_hop_num;
1902 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1903 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1904
1905 calc_pg_sz(caps->num_qps, caps->sccc_entry_sz,
1906 caps->sccc_hop_num, caps->sccc_bt_num,
1907 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,
1908 HEM_TYPE_SCCC);
1909 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
1910 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
1911 &caps->cqc_timer_buf_pg_sz,
1912 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
1913 }
1914
1915 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num,
1916 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
1917 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
1918 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
1919 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
1920 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num,
1921 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
1922
1923 return 0;
1924}
1925
cfc85f3e
WHX		 1926static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1927{
1928 struct hns_roce_caps *caps = &hr_dev->caps;
1929 int ret;
1930
1931 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 1932 if (ret) {
1933 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
1934 ret);
1935 return ret;
1936 }
1937
1938 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 1939 if (ret) {
1940 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1941 ret);
1942 return ret;
1943 }
1944
1945 ret = hns_roce_config_global_param(hr_dev);
1946 if (ret) {
1947 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1948 ret);
2349fdd4 1949 return ret;
cfc85f3e
WHX		 1950 }
1951
1952 /* Get pf resource owned by every pf */
1953 ret = hns_roce_query_pf_resource(hr_dev);
1954 if (ret) {
1955 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1956 ret);
1957 return ret;
1958 }
1959
dfaf2854 1960 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
0e40dc2f
YL		 1961 ret = hns_roce_query_pf_timer_resource(hr_dev);
1962 if (ret) {
1963 dev_err(hr_dev->dev,
1964 "Query pf timer resource fail, ret = %d.\n",
1965 ret);
1966 return ret;
1967 }
cfc85f3e 1968
0c1c3880
LO		 1969 ret = hns_roce_set_vf_switch_param(hr_dev, 0);
1970 if (ret) {
1971 dev_err(hr_dev->dev,
1972 "Set function switch param fail, ret = %d.\n",
1973 ret);
1974 return ret;
1975 }
1976 }
3a63c964
LO		 1977
1978 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
1979 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e 1980
cfc85f3e
WHX		 1981 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1982 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
5c1f167a
LO		 1983 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1984 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
cfc85f3e 1985
80a78570 1986 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
ff795f71
WHX		 1987 caps->pbl_buf_pg_sz = 0;
1988 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
a5073d60
YL		 1989 caps->eqe_ba_pg_sz = 0;
1990 caps->eqe_buf_pg_sz = 0;
1991 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1992 caps->tsq_buf_pg_sz = 0;
aa84fa18 1993
80a78570
LO		 1994 ret = hns_roce_query_pf_caps(hr_dev);
1995 if (ret)
1996 set_default_caps(hr_dev);
384f8818 1997
99e713f8
LO		 1998 ret = hns_roce_alloc_vf_resource(hr_dev);
1999 if (ret) {
2000 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
2001 ret);
2002 return ret;
2003 }
2004
a81fba28
WHX		 2005 ret = hns_roce_v2_set_bt(hr_dev);
2006 if (ret)
2007 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
2008 ret);
2009
2010 return ret;
cfc85f3e
WHX		 2011}
2012
6b63597d 2013static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
2014 enum hns_roce_link_table_type type)
2015{
2016 struct hns_roce_cmq_desc desc[2];
2017 struct hns_roce_cfg_llm_a *req_a =
2018 (struct hns_roce_cfg_llm_a *)desc[0].data;
2019 struct hns_roce_cfg_llm_b *req_b =
2020 (struct hns_roce_cfg_llm_b *)desc[1].data;
2021 struct hns_roce_v2_priv *priv = hr_dev->priv;
2022 struct hns_roce_link_table *link_tbl;
2023 struct hns_roce_link_table_entry *entry;
2024 enum hns_roce_opcode_type opcode;
2025 u32 page_num;
2026 int i;
2027
2028 switch (type) {
2029 case TSQ_LINK_TABLE:
2030 link_tbl = &priv->tsq;
2031 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2032 break;
ded58ff9 2033 case TPQ_LINK_TABLE:
2034 link_tbl = &priv->tpq;
2035 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
2036 break;
6b63597d 2037 default:
2038 return -EINVAL;
2039 }
2040
2041 page_num = link_tbl->npages;
2042 entry = link_tbl->table.buf;
6b63597d 2043
2044 for (i = 0; i < 2; i++) {
2045 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
2046
2047 if (i == 0)
2048 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2049 else
2050 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
6b63597d 2051 }
9976ea27
LO		 2052
2053 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff);
2054 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32);
2055 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M,
2056 CFG_LLM_QUE_DEPTH_S, link_tbl->npages);
2057 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M,
2058 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz);
60262b10
LO		 2059 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M,
2060 CFG_LLM_INIT_EN_S, 1);
9976ea27
LO		 2061 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0);
2062 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr);
2063 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S,
2064 0);
2065
2066 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0);
2067 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M,
2068 CFG_LLM_TAIL_BA_H_S,
2069 entry[page_num - 1].blk_ba1_nxt_ptr &
2070 HNS_ROCE_LINK_TABLE_BA1_M);
2071 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S,
2072 (entry[page_num - 2].blk_ba1_nxt_ptr &
2073 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
2074 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
6b63597d 2075
2076 return hns_roce_cmq_send(hr_dev, desc, 2);
2077}
2078
2079static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
2080 enum hns_roce_link_table_type type)
2081{
2082 struct hns_roce_v2_priv *priv = hr_dev->priv;
2083 struct hns_roce_link_table *link_tbl;
2084 struct hns_roce_link_table_entry *entry;
2085 struct device *dev = hr_dev->dev;
2086 u32 buf_chk_sz;
2087 dma_addr_t t;
ded58ff9 2088 int func_num = 1;
6b63597d 2089 int pg_num_a;
2090 int pg_num_b;
2091 int pg_num;
2092 int size;
2093 int i;
2094
2095 switch (type) {
2096 case TSQ_LINK_TABLE:
2097 link_tbl = &priv->tsq;
2098 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
2099 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
2100 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
2101 break;
ded58ff9 2102 case TPQ_LINK_TABLE:
2103 link_tbl = &priv->tpq;
2104 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
2105 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
2106 pg_num_b = 2 * 4 * func_num + 2;
2107 break;
6b63597d 2108 default:
2109 return -EINVAL;
2110 }
2111
2112 pg_num = max(pg_num_a, pg_num_b);
2113 size = pg_num * sizeof(struct hns_roce_link_table_entry);
2114
2115 link_tbl->table.buf = dma_alloc_coherent(dev, size,
2116 &link_tbl->table.map,
2117 GFP_KERNEL);
2118 if (!link_tbl->table.buf)
2119 goto out;
2120
2121 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
2122 GFP_KERNEL);
2123 if (!link_tbl->pg_list)
2124 goto err_kcalloc_failed;
2125
2126 entry = link_tbl->table.buf;
2127 for (i = 0; i < pg_num; ++i) {
2128 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
2129 &t, GFP_KERNEL);
2130 if (!link_tbl->pg_list[i].buf)
2131 goto err_alloc_buf_failed;
2132
2133 link_tbl->pg_list[i].map = t;
6b63597d 2134
bfe86035
LC		 2135 entry[i].blk_ba0 = (u32)(t >> 12);
2136 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44);
6b63597d 2137
2138 if (i < (pg_num - 1))
bfe86035
LC		 2139 entry[i].blk_ba1_nxt_ptr |=
2140 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S;
2141
6b63597d 2142 }
2143 link_tbl->npages = pg_num;
2144 link_tbl->pg_sz = buf_chk_sz;
2145
2146 return hns_roce_config_link_table(hr_dev, type);
2147
2148err_alloc_buf_failed:
2149 for (i -= 1; i >= 0; i--)
2150 dma_free_coherent(dev, buf_chk_sz,
2151 link_tbl->pg_list[i].buf,
2152 link_tbl->pg_list[i].map);
2153 kfree(link_tbl->pg_list);
2154
2155err_kcalloc_failed:
2156 dma_free_coherent(dev, size, link_tbl->table.buf,
2157 link_tbl->table.map);
2158
2159out:
2160 return -ENOMEM;
2161}
2162
2163static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
2164 struct hns_roce_link_table *link_tbl)
2165{
2166 struct device *dev = hr_dev->dev;
2167 int size;
2168 int i;
2169
2170 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
2171
2172 for (i = 0; i < link_tbl->npages; ++i)
2173 if (link_tbl->pg_list[i].buf)
2174 dma_free_coherent(dev, link_tbl->pg_sz,
2175 link_tbl->pg_list[i].buf,
2176 link_tbl->pg_list[i].map);
2177 kfree(link_tbl->pg_list);
2178
2179 dma_free_coherent(dev, size, link_tbl->table.buf,
2180 link_tbl->table.map);
2181}
2182
2183static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2184{
ded58ff9 2185 struct hns_roce_v2_priv *priv = hr_dev->priv;
0e40dc2f
YL		 2186 int qpc_count, cqc_count;
2187 int ret, i;
6b63597d 2188
2189 /* TSQ includes SQ doorbell and ack doorbell */
2190 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 2191 if (ret) {
6b63597d 2192 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 2193 return ret;
2194 }
2195
2196 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
2197 if (ret) {
2198 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
2199 goto err_tpq_init_failed;
2200 }
2201
6def7de6 2202 /* Alloc memory for QPC Timer buffer space chunk */
0e40dc2f
YL		 2203 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2204 qpc_count++) {
2205 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2206 qpc_count);
2207 if (ret) {
2208 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2209 goto err_qpc_timer_failed;
2210 }
2211 }
2212
6def7de6 2213 /* Alloc memory for CQC Timer buffer space chunk */
0e40dc2f
YL		 2214 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2215 cqc_count++) {
2216 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2217 cqc_count);
2218 if (ret) {
2219 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2220 goto err_cqc_timer_failed;
2221 }
2222 }
2223
ded58ff9 2224 return 0;
2225
0e40dc2f
YL		 2226err_cqc_timer_failed:
2227 for (i = 0; i < cqc_count; i++)
2228 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2229
2230err_qpc_timer_failed:
2231 for (i = 0; i < qpc_count; i++)
2232 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2233
2234 hns_roce_free_link_table(hr_dev, &priv->tpq);
2235
ded58ff9 2236err_tpq_init_failed:
2237 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 2238
2239 return ret;
2240}
2241
2242static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2243{
2244 struct hns_roce_v2_priv *priv = hr_dev->priv;
2245
dfaf2854 2246 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B)
89a6da3c
LC		 2247 hns_roce_function_clear(hr_dev);
2248
ded58ff9 2249 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 2250 hns_roce_free_link_table(hr_dev, &priv->tsq);
2251}
2252
f747b689
LO		 2253static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
2254{
2255 struct hns_roce_cmq_desc desc;
2256 struct hns_roce_mbox_status *mb_st =
2257 (struct hns_roce_mbox_status *)desc.data;
2258 enum hns_roce_cmd_return_status status;
2259
2260 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
2261
2262 status = hns_roce_cmq_send(hr_dev, &desc, 1);
2263 if (status)
2264 return status;
2265
bfe86035 2266 return le32_to_cpu(mb_st->mb_status_hw_run);
f747b689
LO		 2267}
2268
a680f2f3
WHX		 2269static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
2270{
f747b689 2271 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2272
2273 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
2274}
2275
2276static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
2277{
f747b689 2278 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2279
2280 return status & HNS_ROCE_HW_MB_STATUS_MASK;
2281}
2282
f747b689
LO		 2283static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
2284 u64 out_param, u32 in_modifier, u8 op_modifier,
2285 u16 op, u16 token, int event)
2286{
2287 struct hns_roce_cmq_desc desc;
2288 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2289
2290 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2291
bfe86035
LC		 2292 mb->in_param_l = cpu_to_le32(in_param);
2293 mb->in_param_h = cpu_to_le32(in_param >> 32);
2294 mb->out_param_l = cpu_to_le32(out_param);
2295 mb->out_param_h = cpu_to_le32(out_param >> 32);
f747b689
LO		 2296 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
2297 mb->token_event_en = cpu_to_le32(event << 16 | token);
2298
2299 return hns_roce_cmq_send(hr_dev, &desc, 1);
2300}
2301
a680f2f3
WHX		 2302static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
2303 u64 out_param, u32 in_modifier, u8 op_modifier,
2304 u16 op, u16 token, int event)
2305{
2306 struct device *dev = hr_dev->dev;
a680f2f3 2307 unsigned long end;
f747b689 2308 int ret;
a680f2f3
WHX		 2309
2310 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
2311 while (hns_roce_v2_cmd_pending(hr_dev)) {
2312 if (time_after(jiffies, end)) {
2313 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
2314 (int)end);
2315 return -EAGAIN;
2316 }
2317 cond_resched();
2318 }
2319
f747b689
LO		 2320 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
2321 op_modifier, op, token, event);
2322 if (ret)
2323 dev_err(dev, "Post mailbox fail(%d)\n", ret);
a680f2f3 2324
f747b689 2325 return ret;
a680f2f3
WHX		 2326}
2327
2328static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
2329 unsigned long timeout)
2330{
2331 struct device *dev = hr_dev->dev;
617cf24f 2332 unsigned long end;
a680f2f3
WHX		 2333 u32 status;
2334
2335 end = msecs_to_jiffies(timeout) + jiffies;
2336 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
2337 cond_resched();
2338
2339 if (hns_roce_v2_cmd_pending(hr_dev)) {
2340 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
2341 return -ETIMEDOUT;
2342 }
2343
2344 status = hns_roce_v2_cmd_complete(hr_dev);
2345 if (status != 0x1) {
6a04aed6
WHX		 2346 if (status == CMD_RST_PRC_EBUSY)
2347 return status;
2348
a680f2f3
WHX		 2349 dev_err(dev, "mailbox status 0x%x!\n", status);
2350 return -EBUSY;
2351 }
2352
2353 return 0;
2354}
2355
4db134a3 2356static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
2357 int gid_index, const union ib_gid *gid,
2358 enum hns_roce_sgid_type sgid_type)
2359{
2360 struct hns_roce_cmq_desc desc;
2361 struct hns_roce_cfg_sgid_tb *sgid_tb =
2362 (struct hns_roce_cfg_sgid_tb *)desc.data;
2363 u32 *p;
2364
2365 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2366
60262b10 2367 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M,
4db134a3 2368 CFG_SGID_TB_TABLE_IDX_S, gid_index);
60262b10 2369 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M,
4db134a3 2370 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2371
2372 p = (u32 *)&gid->raw[0];
2373 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
2374
2375 p = (u32 *)&gid->raw[4];
2376 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
2377
2378 p = (u32 *)&gid->raw[8];
2379 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
2380
2381 p = (u32 *)&gid->raw[0xc];
2382 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
2383
2384 return hns_roce_cmq_send(hr_dev, &desc, 1);
2385}
2386
b5ff0f61 2387static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 2388 int gid_index, const union ib_gid *gid,
b5ff0f61 2389 const struct ib_gid_attr *attr)
7afddafa 2390{
b5ff0f61 2391 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 2392 int ret;
7afddafa 2393
b5ff0f61
WHX		 2394 if (!gid || !attr)
2395 return -EINVAL;
2396
2397 if (attr->gid_type == IB_GID_TYPE_ROCE)
2398 sgid_type = GID_TYPE_FLAG_ROCE_V1;
2399
2400 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2401 if (ipv6_addr_v4mapped((void *)gid))
2402 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
2403 else
2404 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
2405 }
2406
4db134a3 2407 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
2408 if (ret)
ae1c6148
LO		 2409 ibdev_err(&hr_dev->ib_dev,
2410 "failed to configure sgid table, ret = %d!\n",
2411 ret);
b5ff0f61 2412
4db134a3 2413 return ret;
7afddafa
WHX		 2414}
2415
a74dc41d
WHX		 2416static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
2417 u8 *addr)
7afddafa 2418{
e8e8b652 2419 struct hns_roce_cmq_desc desc;
2420 struct hns_roce_cfg_smac_tb *smac_tb =
2421 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 2422 u16 reg_smac_h;
2423 u32 reg_smac_l;
e8e8b652 2424
2425 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 2426
2427 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 2428 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 2429
375898e8 2430 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M,
e8e8b652 2431 CFG_SMAC_TB_IDX_S, phy_port);
375898e8 2432 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M,
e8e8b652 2433 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
bfe86035 2434 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
a74dc41d 2435
e8e8b652 2436 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 2437}
2438
ca088320
YL		 2439static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry,
2440 struct hns_roce_mr *mr)
3958cc56 2441{
3856ec55 2442 struct sg_dma_page_iter sg_iter;
db270c41 2443 u64 page_addr;
3958cc56 2444 u64 *pages;
3856ec55 2445 int i;
3958cc56 2446
ca088320
YL		 2447 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2448 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2449 roce_set_field(mpt_entry->byte_48_mode_ba,
2450 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
2451 upper_32_bits(mr->pbl_ba >> 3));
2452
2453 pages = (u64 *)__get_free_page(GFP_KERNEL);
2454 if (!pages)
2455 return -ENOMEM;
2456
2457 i = 0;
3856ec55
SS		 2458 for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
2459 page_addr = sg_page_iter_dma_address(&sg_iter);
2460 pages[i] = page_addr >> 6;
2461
2462 /* Record the first 2 entry directly to MTPT table */
2463 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
2464 goto found;
2465 i++;
ca088320
YL		 2466 }
2467found:
2468 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
2469 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
2470 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
2471
2472 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
2473 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
2474 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
2475 roce_set_field(mpt_entry->byte_64_buf_pa1,
2476 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2477 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2478 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2479
2480 free_page((unsigned long)pages);
2481
2482 return 0;
2483}
2484
2485static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
2486 unsigned long mtpt_idx)
2487{
2488 struct hns_roce_v2_mpt_entry *mpt_entry;
2489 int ret;
2490
3958cc56
WHX		 2491 mpt_entry = mb_buf;
2492 memset(mpt_entry, 0, sizeof(*mpt_entry));
2493
2494 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2495 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2496 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2497 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
2498 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
2499 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2500 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 2501 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2502 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 2503 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2504 V2_MPT_BYTE_4_PD_S, mr->pd);
3958cc56
WHX		 2505
2506 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
82342e49 2507 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0);
e93df010 2508 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 2509 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
2510 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 2511 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
2512 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 2513 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2514 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
2515 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2516 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
2517 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2518 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
3958cc56
WHX		 2519
2520 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
2521 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 2522 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
2523 1);
3958cc56
WHX		 2524
2525 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
2526 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
2527 mpt_entry->lkey = cpu_to_le32(mr->key);
2528 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
2529 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
2530
2531 if (mr->type == MR_TYPE_DMA)
2532 return 0;
2533
ca088320 2534 ret = set_mtpt_pbl(mpt_entry, mr);
3958cc56 2535
ca088320 2536 return ret;
3958cc56
WHX		 2537}
2538
a2c80b7b
WHX		 2539static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
2540 struct hns_roce_mr *mr, int flags,
2541 u32 pdn, int mr_access_flags, u64 iova,
2542 u64 size, void *mb_buf)
2543{
2544 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
ca088320 2545 int ret = 0;
a2c80b7b 2546
ab22bf05
YL		 2547 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2548 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2549
a2c80b7b
WHX		 2550 if (flags & IB_MR_REREG_PD) {
2551 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2552 V2_MPT_BYTE_4_PD_S, pdn);
2553 mr->pd = pdn;
2554 }
2555
2556 if (flags & IB_MR_REREG_ACCESS) {
2557 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2558 V2_MPT_BYTE_8_BIND_EN_S,
2559 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
2560 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
ca088320
YL		 2561 V2_MPT_BYTE_8_ATOMIC_EN_S,
2562 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
a2c80b7b 2563 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
ca088320 2564 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
a2c80b7b 2565 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
ca088320 2566 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
a2c80b7b 2567 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
ca088320 2568 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
a2c80b7b
WHX		 2569 }
2570
2571 if (flags & IB_MR_REREG_TRANS) {
2572 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
2573 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
2574 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
2575 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
2576
a2c80b7b
WHX		 2577 mr->iova = iova;
2578 mr->size = size;
ca088320
YL		 2579
2580 ret = set_mtpt_pbl(mpt_entry, mr);
a2c80b7b
WHX		 2581 }
2582
ca088320 2583 return ret;
a2c80b7b
WHX		 2584}
2585
68a997c5
YL		 2586static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
2587{
2588 struct hns_roce_v2_mpt_entry *mpt_entry;
2589
2590 mpt_entry = mb_buf;
2591 memset(mpt_entry, 0, sizeof(*mpt_entry));
2592
2593 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2594 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2595 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2596 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
2597 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2598 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2599 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2600 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2601 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2602 V2_MPT_BYTE_4_PD_S, mr->pd);
2603
2604 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
2605 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2606 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2607
2608 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
2609 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2610 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
2611 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2612
2613 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2614
2615 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2616 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
2617 V2_MPT_BYTE_48_PBL_BA_H_S,
2618 upper_32_bits(mr->pbl_ba >> 3));
2619
2620 roce_set_field(mpt_entry->byte_64_buf_pa1,
2621 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2622 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2623 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2624
2625 return 0;
2626}
2627
c7c28191
YL		 2628static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
2629{
2630 struct hns_roce_v2_mpt_entry *mpt_entry;
2631
2632 mpt_entry = mb_buf;
2633 memset(mpt_entry, 0, sizeof(*mpt_entry));
2634
2635 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2636 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2637 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2638 V2_MPT_BYTE_4_PD_S, mw->pdn);
60262b10 2639 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
c7c28191 2640 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
60262b10
LO		 2641 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
2642 mw->pbl_hop_num);
c7c28191
YL		 2643 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2644 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2645 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2646 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2647
2648 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2649 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2650
2651 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2652 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
2653 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2654 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
2655 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2656
2657 roce_set_field(mpt_entry->byte_64_buf_pa1,
2658 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2659 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2660 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2661
2662 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2663
2664 return 0;
2665}
2666
93aa2187
WHX		 2667static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2668{
744b7bdf
XW		 2669 return hns_roce_buf_offset(hr_cq->mtr.kmem,
2670 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
93aa2187
WHX		 2671}
2672
2673static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2674{
2675 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2676
2677 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2678 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
e2b2744a 2679 !!(n & hr_cq->cq_depth)) ? cqe : NULL;
93aa2187
WHX		 2680}
2681
2682static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
2683{
2684 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
2685}
2686
c7bcb134
LO		 2687static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
2688{
6fd610c5 2689 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
c7bcb134
LO		 2690}
2691
2692static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index)
2693{
c7bcb134
LO		 2694 /* always called with interrupts disabled. */
2695 spin_lock(&srq->lock);
2696
97545b10 2697 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
c7bcb134
LO		 2698 srq->tail++;
2699
2700 spin_unlock(&srq->lock);
2701}
2702
93aa2187
WHX		 2703static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2704{
b14c95be 2705 *hr_cq->set_ci_db = cons_index & V2_CQ_DB_PARAMETER_CONS_IDX_M;
93aa2187
WHX		 2706}
2707
926a01dc
WHX		 2708static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2709 struct hns_roce_srq *srq)
2710{
2711 struct hns_roce_v2_cqe *cqe, *dest;
2712 u32 prod_index;
2713 int nfreed = 0;
c7bcb134 2714 int wqe_index;
926a01dc
WHX		 2715 u8 owner_bit;
2716
2717 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2718 ++prod_index) {
d7e5ca88 2719 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
926a01dc
WHX		 2720 break;
2721 }
2722
2723 /*
2724 * Now backwards through the CQ, removing CQ entries
2725 * that match our QP by overwriting them with next entries.
2726 */
2727 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2728 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2729 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2730 V2_CQE_BYTE_16_LCL_QPN_S) &
2731 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
c7bcb134
LO		 2732 if (srq &&
2733 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) {
2734 wqe_index = roce_get_field(cqe->byte_4,
2735 V2_CQE_BYTE_4_WQE_INDX_M,
2736 V2_CQE_BYTE_4_WQE_INDX_S);
2737 hns_roce_free_srq_wqe(srq, wqe_index);
2738 }
926a01dc
WHX		 2739 ++nfreed;
2740 } else if (nfreed) {
2741 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2742 hr_cq->ib_cq.cqe);
2743 owner_bit = roce_get_bit(dest->byte_4,
2744 V2_CQE_BYTE_4_OWNER_S);
2745 memcpy(dest, cqe, sizeof(*cqe));
2746 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2747 owner_bit);
2748 }
2749 }
2750
2751 if (nfreed) {
2752 hr_cq->cons_index += nfreed;
2753 /*
2754 * Make sure update of buffer contents is done before
2755 * updating consumer index.
2756 */
2757 wmb();
2758 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2759 }
2760}
2761
2762static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2763 struct hns_roce_srq *srq)
2764{
2765 spin_lock_irq(&hr_cq->lock);
2766 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2767 spin_unlock_irq(&hr_cq->lock);
2768}
2769
93aa2187
WHX		 2770static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2771 struct hns_roce_cq *hr_cq, void *mb_buf,
e2b2744a 2772 u64 *mtts, dma_addr_t dma_handle)
93aa2187
WHX		 2773{
2774 struct hns_roce_v2_cq_context *cq_context;
2775
2776 cq_context = mb_buf;
2777 memset(cq_context, 0, sizeof(*cq_context));
2778
2779 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2780 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2781 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2782 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187 2783 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
60262b10 2784 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth));
93aa2187 2785 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
e2b2744a 2786 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector);
93aa2187
WHX		 2787
2788 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2789 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2790
744b7bdf 2791 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
93aa2187
WHX		 2792
2793 roce_set_field(cq_context->byte_16_hop_addr,
2794 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2795 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
744b7bdf 2796 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
93aa2187
WHX		 2797 roce_set_field(cq_context->byte_16_hop_addr,
2798 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2799 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2800 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2801
744b7bdf 2802 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
93aa2187
WHX		 2803 roce_set_field(cq_context->byte_24_pgsz_addr,
2804 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2805 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
744b7bdf 2806 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
93aa2187
WHX		 2807 roce_set_field(cq_context->byte_24_pgsz_addr,
2808 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2809 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
744b7bdf 2810 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
93aa2187
WHX		 2811 roce_set_field(cq_context->byte_24_pgsz_addr,
2812 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2813 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
744b7bdf 2814 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
93aa2187 2815
bfe86035 2816 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3);
93aa2187
WHX		 2817
2818 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2819 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2820
9b44703d
YL		 2821 if (hr_cq->db_en)
2822 roce_set_bit(cq_context->byte_44_db_record,
2823 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
2824
2825 roce_set_field(cq_context->byte_44_db_record,
2826 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2827 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2828 ((u32)hr_cq->db.dma) >> 1);
bfe86035 2829 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32);
9b44703d 2830
a5073d60
YL		 2831 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2832 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2833 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2834 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2835 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2836 V2_CQC_BYTE_56_CQ_PERIOD_M,
2837 V2_CQC_BYTE_56_CQ_PERIOD_S,
2838 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2839}
2840
2841static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2842 enum ib_cq_notify_flags flags)
2843{
d3743fa9 2844 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 2845 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2846 u32 notification_flag;
bfe86035 2847 __le32 doorbell[2];
93aa2187
WHX		 2848
2849 doorbell[0] = 0;
2850 doorbell[1] = 0;
2851
2852 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2853 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2854 /*
2855 * flags = 0; Notification Flag = 1, next
2856 * flags = 1; Notification Flag = 0, solocited
2857 */
2858 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2859 hr_cq->cqn);
2860 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2861 HNS_ROCE_V2_CQ_DB_NTR);
2862 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2863 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2864 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2865 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2866 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2867 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2868 notification_flag);
2869
d3743fa9 2870 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l);
93aa2187
WHX		 2871
2872 return 0;
2873}
2874
0009c2db 2875static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2876 struct hns_roce_qp **cur_qp,
2877 struct ib_wc *wc)
2878{
2879 struct hns_roce_rinl_sge *sge_list;
2880 u32 wr_num, wr_cnt, sge_num;
2881 u32 sge_cnt, data_len, size;
2882 void *wqe_buf;
2883
2884 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2885 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2886 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2887
2888 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2889 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
6c6e3921 2890 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt);
0009c2db 2891 data_len = wc->byte_len;
2892
2893 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2894 size = min(sge_list[sge_cnt].len, data_len);
2895 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2896
2897 data_len -= size;
2898 wqe_buf += size;
2899 }
2900
2901 if (data_len) {
2902 wc->status = IB_WC_LOC_LEN_ERR;
2903 return -EAGAIN;
2904 }
2905
2906 return 0;
2907}
2908
626903e9
XW		 2909static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
2910 int num_entries, struct ib_wc *wc)
2911{
2912 unsigned int left;
2913 int npolled = 0;
2914
2915 left = wq->head - wq->tail;
2916 if (left == 0)
2917 return 0;
2918
2919 left = min_t(unsigned int, (unsigned int)num_entries, left);
2920 while (npolled < left) {
2921 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2922 wc->status = IB_WC_WR_FLUSH_ERR;
2923 wc->vendor_err = 0;
2924 wc->qp = &hr_qp->ibqp;
2925
2926 wq->tail++;
2927 wc++;
2928 npolled++;
2929 }
2930
2931 return npolled;
2932}
2933
2934static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
2935 struct ib_wc *wc)
2936{
2937 struct hns_roce_qp *hr_qp;
2938 int npolled = 0;
2939
2940 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
2941 npolled += sw_comp(hr_qp, &hr_qp->sq,
2942 num_entries - npolled, wc + npolled);
2943 if (npolled >= num_entries)
2944 goto out;
2945 }
2946
2947 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
2948 npolled += sw_comp(hr_qp, &hr_qp->rq,
2949 num_entries - npolled, wc + npolled);
2950 if (npolled >= num_entries)
2951 goto out;
2952 }
2953
2954out:
2955 return npolled;
2956}
2957
93aa2187
WHX		 2958static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2959 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2960{
b5374286 2961 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
c7bcb134 2962 struct hns_roce_srq *srq = NULL;
93aa2187
WHX		 2963 struct hns_roce_v2_cqe *cqe;
2964 struct hns_roce_qp *hr_qp;
2965 struct hns_roce_wq *wq;
2966 int is_send;
2967 u16 wqe_ctr;
2968 u32 opcode;
2969 u32 status;
2970 int qpn;
0009c2db 2971 int ret;
93aa2187
WHX		 2972
2973 /* Find cqe according to consumer index */
2974 cqe = next_cqe_sw_v2(hr_cq);
2975 if (!cqe)
2976 return -EAGAIN;
2977
2978 ++hr_cq->cons_index;
2979 /* Memory barrier */
2980 rmb();
2981
2982 /* 0->SQ, 1->RQ */
2983 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2984
2985 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2986 V2_CQE_BYTE_16_LCL_QPN_S);
2987
2988 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
93aa2187
WHX		 2989 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2990 if (unlikely(!hr_qp)) {
ae1c6148
LO		 2991 ibdev_err(&hr_dev->ib_dev,
2992 "CQ %06lx with entry for unknown QPN %06x\n",
2993 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK);
93aa2187
WHX		 2994 return -EINVAL;
2995 }
2996 *cur_qp = hr_qp;
2997 }
2998
b5374286 2999 hr_qp = *cur_qp;
93aa2187
WHX		 3000 wc->qp = &(*cur_qp)->ibqp;
3001 wc->vendor_err = 0;
3002
c7bcb134
LO		 3003 if (is_send) {
3004 wq = &(*cur_qp)->sq;
3005 if ((*cur_qp)->sq_signal_bits) {
3006 /*
3007 * If sg_signal_bit is 1,
3008 * firstly tail pointer updated to wqe
3009 * which current cqe correspond to
3010 */
3011 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3012 V2_CQE_BYTE_4_WQE_INDX_M,
3013 V2_CQE_BYTE_4_WQE_INDX_S);
3014 wq->tail += (wqe_ctr - (u16)wq->tail) &
3015 (wq->wqe_cnt - 1);
3016 }
3017
3018 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3019 ++wq->tail;
3020 } else if ((*cur_qp)->ibqp.srq) {
3021 srq = to_hr_srq((*cur_qp)->ibqp.srq);
bfe86035
LC		 3022 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3023 V2_CQE_BYTE_4_WQE_INDX_M,
3024 V2_CQE_BYTE_4_WQE_INDX_S);
c7bcb134
LO		 3025 wc->wr_id = srq->wrid[wqe_ctr];
3026 hns_roce_free_srq_wqe(srq, wqe_ctr);
3027 } else {
3028 /* Update tail pointer, record wr_id */
3029 wq = &(*cur_qp)->rq;
3030 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3031 ++wq->tail;
3032 }
3033
93aa2187
WHX		 3034 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
3035 V2_CQE_BYTE_4_STATUS_S);
3036 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
3037 case HNS_ROCE_CQE_V2_SUCCESS:
3038 wc->status = IB_WC_SUCCESS;
3039 break;
3040 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
3041 wc->status = IB_WC_LOC_LEN_ERR;
3042 break;
3043 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
3044 wc->status = IB_WC_LOC_QP_OP_ERR;
3045 break;
3046 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
3047 wc->status = IB_WC_LOC_PROT_ERR;
3048 break;
3049 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
3050 wc->status = IB_WC_WR_FLUSH_ERR;
3051 break;
3052 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
3053 wc->status = IB_WC_MW_BIND_ERR;
3054 break;
3055 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
3056 wc->status = IB_WC_BAD_RESP_ERR;
3057 break;
3058 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
3059 wc->status = IB_WC_LOC_ACCESS_ERR;
3060 break;
3061 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
3062 wc->status = IB_WC_REM_INV_REQ_ERR;
3063 break;
3064 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
3065 wc->status = IB_WC_REM_ACCESS_ERR;
3066 break;
3067 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
3068 wc->status = IB_WC_REM_OP_ERR;
3069 break;
3070 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
3071 wc->status = IB_WC_RETRY_EXC_ERR;
3072 break;
3073 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
3074 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
3075 break;
3076 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
3077 wc->status = IB_WC_REM_ABORT_ERR;
3078 break;
3079 default:
3080 wc->status = IB_WC_GENERAL_ERR;
3081 break;
3082 }
3083
b5374286
YL		 3084 /*
3085 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets
3086 * into errored mode. Hence, as a workaround to this hardware
3087 * limitation, driver needs to assist in flushing. But the flushing
3088 * operation uses mailbox to convey the QP state to the hardware and
3089 * which can sleep due to the mutex protection around the mailbox calls.
3090 * Hence, use the deferred flush for now. Once wc error detected, the
3091 * flushing operation is needed.
3092 */
3093 if (wc->status != IB_WC_SUCCESS &&
3094 wc->status != IB_WC_WR_FLUSH_ERR) {
ae1c6148
LO		 3095 ibdev_err(&hr_dev->ib_dev, "error cqe status is: 0x%x\n",
3096 status & HNS_ROCE_V2_CQE_STATUS_MASK);
b5374286
YL		 3097
3098 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag))
3099 init_flush_work(hr_dev, hr_qp);
3100
3101 return 0;
0425e3e6
YL		 3102 }
3103
3104 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 3105 return 0;
3106
3107 if (is_send) {
3108 wc->wc_flags = 0;
3109 /* SQ corresponding to CQE */
3110 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3111 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
3112 case HNS_ROCE_SQ_OPCODE_SEND:
3113 wc->opcode = IB_WC_SEND;
3114 break;
3115 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
3116 wc->opcode = IB_WC_SEND;
3117 break;
3118 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
3119 wc->opcode = IB_WC_SEND;
3120 wc->wc_flags |= IB_WC_WITH_IMM;
3121 break;
3122 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
3123 wc->opcode = IB_WC_RDMA_READ;
3124 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3125 break;
3126 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
3127 wc->opcode = IB_WC_RDMA_WRITE;
3128 break;
3129 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
3130 wc->opcode = IB_WC_RDMA_WRITE;
3131 wc->wc_flags |= IB_WC_WITH_IMM;
3132 break;
3133 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
3134 wc->opcode = IB_WC_LOCAL_INV;
3135 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3136 break;
3137 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
3138 wc->opcode = IB_WC_COMP_SWAP;
3139 wc->byte_len = 8;
3140 break;
3141 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
3142 wc->opcode = IB_WC_FETCH_ADD;
3143 wc->byte_len = 8;
3144 break;
3145 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
3146 wc->opcode = IB_WC_MASKED_COMP_SWAP;
3147 wc->byte_len = 8;
3148 break;
3149 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
3150 wc->opcode = IB_WC_MASKED_FETCH_ADD;
3151 wc->byte_len = 8;
3152 break;
3153 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
3154 wc->opcode = IB_WC_REG_MR;
3155 break;
3156 case HNS_ROCE_SQ_OPCODE_BIND_MW:
3157 wc->opcode = IB_WC_REG_MR;
3158 break;
3159 default:
3160 wc->status = IB_WC_GENERAL_ERR;
3161 break;
3162 }
93aa2187
WHX		 3163 } else {
3164 /* RQ correspond to CQE */
3165 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3166
3167 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3168 V2_CQE_BYTE_4_OPCODE_S);
3169 switch (opcode & 0x1f) {
3170 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3171 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3172 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3173 wc->ex.imm_data =
3174 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3175 break;
3176 case HNS_ROCE_V2_OPCODE_SEND:
3177 wc->opcode = IB_WC_RECV;
3178 wc->wc_flags = 0;
3179 break;
3180 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3181 wc->opcode = IB_WC_RECV;
3182 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3183 wc->ex.imm_data =
3184 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3185 break;
3186 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3187 wc->opcode = IB_WC_RECV;
3188 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 3189 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 3190 break;
3191 default:
3192 wc->status = IB_WC_GENERAL_ERR;
3193 break;
3194 }
3195
0009c2db 3196 if ((wc->qp->qp_type == IB_QPT_RC ||
3197 wc->qp->qp_type == IB_QPT_UC) &&
3198 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
3199 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3200 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3201 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
3202 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
3203 if (ret)
3204 return -EAGAIN;
3205 }
3206
93aa2187
WHX		 3207 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
3208 V2_CQE_BYTE_32_SL_S);
3209 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
3210 V2_CQE_BYTE_32_RMT_QPN_M,
3211 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 3212 wc->slid = 0;
93aa2187
WHX		 3213 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
3214 V2_CQE_BYTE_32_GRH_S) ?
3215 IB_WC_GRH : 0);
6c1f08b3 3216 wc->port_num = roce_get_field(cqe->byte_32,
3217 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
3218 wc->pkey_index = 0;
cd4a70bb 3219
944e6409
LO		 3220 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
3221 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
3222 V2_CQE_BYTE_28_VID_M,
3223 V2_CQE_BYTE_28_VID_S);
0e1aa6f0 3224 wc->wc_flags |= IB_WC_WITH_VLAN;
944e6409
LO		 3225 } else {
3226 wc->vlan_id = 0xffff;
3227 }
3228
2eade675 3229 wc->network_hdr_type = roce_get_field(cqe->byte_28,
3230 V2_CQE_BYTE_28_PORT_TYPE_M,
3231 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 3232 }
3233
3234 return 0;
3235}
3236
3237static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3238 struct ib_wc *wc)
3239{
626903e9 3240 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 3241 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3242 struct hns_roce_qp *cur_qp = NULL;
3243 unsigned long flags;
3244 int npolled;
3245
3246 spin_lock_irqsave(&hr_cq->lock, flags);
3247
626903e9
XW		 3248 /*
3249 * When the device starts to reset, the state is RST_DOWN. At this time,
3250 * there may still be some valid CQEs in the hardware that are not
3251 * polled. Therefore, it is not allowed to switch to the software mode
3252 * immediately. When the state changes to UNINIT, CQE no longer exists
3253 * in the hardware, and then switch to software mode.
3254 */
3255 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3256 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3257 goto out;
3258 }
3259
93aa2187
WHX		 3260 for (npolled = 0; npolled < num_entries; ++npolled) {
3261 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3262 break;
3263 }
3264
3265 if (npolled) {
3266 /* Memory barrier */
3267 wmb();
3268 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
3269 }
3270
626903e9 3271out:
93aa2187
WHX		 3272 spin_unlock_irqrestore(&hr_cq->lock, flags);
3273
3274 return npolled;
3275}
3276
260c3b34
YL		 3277static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3278 int step_idx)
3279{
3280 int op;
3281
3282 if (type == HEM_TYPE_SCCC && step_idx)
3283 return -EINVAL;
3284
3285 switch (type) {
3286 case HEM_TYPE_QPC:
3287 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
3288 break;
3289 case HEM_TYPE_MTPT:
3290 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
3291 break;
3292 case HEM_TYPE_CQC:
3293 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
3294 break;
3295 case HEM_TYPE_SRQC:
3296 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3297 break;
3298 case HEM_TYPE_SCCC:
3299 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3300 break;
3301 case HEM_TYPE_QPC_TIMER:
3302 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3303 break;
3304 case HEM_TYPE_CQC_TIMER:
3305 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3306 break;
3307 default:
3308 dev_warn(hr_dev->dev,
3309 "Table %d not to be written by mailbox!\n", type);
3310 return -EINVAL;
3311 }
3312
3313 return op + step_idx;
3314}
3315
a81fba28
WHX		 3316static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
3317 struct hns_roce_hem_table *table, int obj,
3318 int step_idx)
3319{
a81fba28
WHX		 3320 struct hns_roce_cmd_mailbox *mailbox;
3321 struct hns_roce_hem_iter iter;
3322 struct hns_roce_hem_mhop mhop;
3323 struct hns_roce_hem *hem;
3324 unsigned long mhop_obj = obj;
3325 int i, j, k;
3326 int ret = 0;
3327 u64 hem_idx = 0;
3328 u64 l1_idx = 0;
3329 u64 bt_ba = 0;
3330 u32 chunk_ba_num;
3331 u32 hop_num;
260c3b34 3332 int op;
a81fba28
WHX		 3333
3334 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3335 return 0;
3336
3337 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
3338 i = mhop.l0_idx;
3339 j = mhop.l1_idx;
3340 k = mhop.l2_idx;
3341 hop_num = mhop.hop_num;
3342 chunk_ba_num = mhop.bt_chunk_size / 8;
3343
3344 if (hop_num == 2) {
3345 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
3346 k;
3347 l1_idx = i * chunk_ba_num + j;
3348 } else if (hop_num == 1) {
3349 hem_idx = i * chunk_ba_num + j;
3350 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
3351 hem_idx = i;
3352 }
3353
260c3b34
YL		 3354 op = get_op_for_set_hem(hr_dev, table->type, step_idx);
3355 if (op == -EINVAL)
a81fba28 3356 return 0;
a81fba28
WHX		 3357
3358 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3359 if (IS_ERR(mailbox))
3360 return PTR_ERR(mailbox);
3361
6ac16e40
YL		 3362 if (table->type == HEM_TYPE_SCCC)
3363 obj = mhop.l0_idx;
3364
a81fba28
WHX		 3365 if (check_whether_last_step(hop_num, step_idx)) {
3366 hem = table->hem[hem_idx];
3367 for (hns_roce_hem_first(hem, &iter);
3368 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
3369 bt_ba = hns_roce_hem_addr(&iter);
3370
3371 /* configure the ba, tag, and op */
3372 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
3373 obj, 0, op,
3374 HNS_ROCE_CMD_TIMEOUT_MSECS);
3375 }
3376 } else {
3377 if (step_idx == 0)
3378 bt_ba = table->bt_l0_dma_addr[i];
3379 else if (step_idx == 1 && hop_num == 2)
3380 bt_ba = table->bt_l1_dma_addr[l1_idx];
3381
3382 /* configure the ba, tag, and op */
3383 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
3384 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
3385 }
3386
3387 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3388 return ret;
3389}
3390
3391static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
3392 struct hns_roce_hem_table *table, int obj,
3393 int step_idx)
3394{
3395 struct device *dev = hr_dev->dev;
3396 struct hns_roce_cmd_mailbox *mailbox;
617cf24f 3397 int ret;
a81fba28
WHX		 3398 u16 op = 0xff;
3399
3400 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3401 return 0;
3402
3403 switch (table->type) {
3404 case HEM_TYPE_QPC:
3405 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
3406 break;
3407 case HEM_TYPE_MTPT:
3408 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
3409 break;
3410 case HEM_TYPE_CQC:
3411 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
3412 break;
6a157f7d 3413 case HEM_TYPE_SCCC:
0e40dc2f
YL		 3414 case HEM_TYPE_QPC_TIMER:
3415 case HEM_TYPE_CQC_TIMER:
6a157f7d 3416 break;
a81fba28
WHX		 3417 case HEM_TYPE_SRQC:
3418 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
3419 break;
3420 default:
3421 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
3422 table->type);
3423 return 0;
3424 }
6a157f7d 3425
0e40dc2f
YL		 3426 if (table->type == HEM_TYPE_SCCC ||
3427 table->type == HEM_TYPE_QPC_TIMER ||
3428 table->type == HEM_TYPE_CQC_TIMER)
6a157f7d
YL		 3429 return 0;
3430
a81fba28
WHX		 3431 op += step_idx;
3432
3433 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3434 if (IS_ERR(mailbox))
3435 return PTR_ERR(mailbox);
3436
3437 /* configure the tag and op */
3438 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3439 HNS_ROCE_CMD_TIMEOUT_MSECS);
3440
3441 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3442 return ret;
3443}
3444
926a01dc 3445static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
926a01dc
WHX		 3446 struct hns_roce_v2_qp_context *context,
3447 struct hns_roce_qp *hr_qp)
3448{
3449 struct hns_roce_cmd_mailbox *mailbox;
3450 int ret;
3451
3452 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3453 if (IS_ERR(mailbox))
3454 return PTR_ERR(mailbox);
3455
3456 memcpy(mailbox->buf, context, sizeof(*context) * 2);
3457
3458 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
3459 HNS_ROCE_CMD_MODIFY_QPC,
3460 HNS_ROCE_CMD_TIMEOUT_MSECS);
3461
3462 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3463
3464 return ret;
3465}
3466
ace1c541 3467static void set_access_flags(struct hns_roce_qp *hr_qp,
3468 struct hns_roce_v2_qp_context *context,
3469 struct hns_roce_v2_qp_context *qpc_mask,
3470 const struct ib_qp_attr *attr, int attr_mask)
3471{
3472 u8 dest_rd_atomic;
3473 u32 access_flags;
3474
c2799119 3475 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 3476 attr->max_dest_rd_atomic : hr_qp->resp_depth;
3477
c2799119 3478 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 3479 attr->qp_access_flags : hr_qp->atomic_rd_en;
3480
3481 if (!dest_rd_atomic)
3482 access_flags &= IB_ACCESS_REMOTE_WRITE;
3483
3484 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3485 !!(access_flags & IB_ACCESS_REMOTE_READ));
3486 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
3487
3488 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3489 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3490 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
3491
3492 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3493 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3494 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
7db82697
JZ		 3495 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S,
3496 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3497 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0);
ace1c541 3498}
3499
99441ab5
XW		 3500static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
3501 struct hns_roce_v2_qp_context *context,
3502 struct hns_roce_v2_qp_context *qpc_mask)
3503{
3504 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
3505 roce_set_field(context->byte_4_sqpn_tst,
3506 V2_QPC_BYTE_4_SGE_SHIFT_M,
3507 V2_QPC_BYTE_4_SGE_SHIFT_S,
3508 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3509 else
3510 roce_set_field(context->byte_4_sqpn_tst,
3511 V2_QPC_BYTE_4_SGE_SHIFT_M,
3512 V2_QPC_BYTE_4_SGE_SHIFT_S,
3513 hr_qp->sq.max_gs >
3514 HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE ?
3515 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3516
99441ab5
XW		 3517 roce_set_field(context->byte_20_smac_sgid_idx,
3518 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3519 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
99441ab5
XW		 3520
3521 roce_set_field(context->byte_20_smac_sgid_idx,
3522 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
3523 (hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3524 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT ||
3525 hr_qp->ibqp.srq) ? 0 :
3526 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
99441ab5
XW		 3527}
3528
926a01dc
WHX		 3529static void modify_qp_reset_to_init(struct ib_qp *ibqp,
3530 const struct ib_qp_attr *attr,
0fa95a9a 3531 int attr_mask,
926a01dc
WHX		 3532 struct hns_roce_v2_qp_context *context,
3533 struct hns_roce_v2_qp_context *qpc_mask)
3534{
ecaaf1e2 3535 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 3536 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3537
3538 /*
3539 * In v2 engine, software pass context and context mask to hardware
3540 * when modifying qp. If software need modify some fields in context,
3541 * we should set all bits of the relevant fields in context mask to
3542 * 0 at the same time, else set them to 0x1.
3543 */
3544 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3545 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
926a01dc 3546
926a01dc
WHX		 3547 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3548 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
926a01dc
WHX		 3549
3550 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3551 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
926a01dc
WHX		 3552
3553 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3554 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
926a01dc 3555
99441ab5 3556 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
926a01dc
WHX		 3557
3558 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 3559 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3560 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
926a01dc 3561
f4c5d869 3562 if (hr_qp->rdb_en)
e088a685
YL		 3563 roce_set_bit(context->byte_68_rq_db,
3564 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
e088a685
YL		 3565
3566 roce_set_field(context->byte_68_rq_db,
3567 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3568 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
3569 ((u32)hr_qp->rdb.dma) >> 1);
bfe86035 3570 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32);
e088a685 3571
ecaaf1e2 3572 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
3573 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 3574
3575 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3576 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
926a01dc
WHX		 3577 if (ibqp->srq) {
3578 roce_set_field(context->byte_76_srqn_op_en,
3579 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3580 to_hr_srq(ibqp->srq)->srqn);
926a01dc
WHX		 3581 roce_set_bit(context->byte_76_srqn_op_en,
3582 V2_QPC_BYTE_76_SRQ_EN_S, 1);
f4c5d869 3583 }
926a01dc
WHX		 3584
3585 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3586 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
926a01dc 3587
68a997c5 3588 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
926a01dc
WHX		 3589
3590 hr_qp->access_flags = attr->qp_access_flags;
926a01dc
WHX		 3591 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3592 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3593}
3594
3595static void modify_qp_init_to_init(struct ib_qp *ibqp,
3596 const struct ib_qp_attr *attr, int attr_mask,
3597 struct hns_roce_v2_qp_context *context,
3598 struct hns_roce_v2_qp_context *qpc_mask)
3599{
3600 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3601
3602 /*
3603 * In v2 engine, software pass context and context mask to hardware
3604 * when modifying qp. If software need modify some fields in context,
3605 * we should set all bits of the relevant fields in context mask to
3606 * 0 at the same time, else set them to 0x1.
3607 */
3608 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3609 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3610 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3611 V2_QPC_BYTE_4_TST_S, 0);
3612
926a01dc
WHX		 3613 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3614 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3615 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3616 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3617 0);
3618
3619 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3620 !!(attr->qp_access_flags &
3621 IB_ACCESS_REMOTE_WRITE));
3622 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3623 0);
3624
3625 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3626 !!(attr->qp_access_flags &
3627 IB_ACCESS_REMOTE_ATOMIC));
3628 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3629 0);
7db82697
JZ		 3630 roce_set_bit(context->byte_76_srqn_op_en,
3631 V2_QPC_BYTE_76_EXT_ATE_S,
3632 !!(attr->qp_access_flags &
3633 IB_ACCESS_REMOTE_ATOMIC));
3634 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3635 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3636 } else {
3637 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3638 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3639 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3640 0);
3641
3642 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3643 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3644 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3645 0);
3646
3647 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3648 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3649 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3650 0);
7db82697
JZ		 3651 roce_set_bit(context->byte_76_srqn_op_en,
3652 V2_QPC_BYTE_76_EXT_ATE_S,
3653 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3654 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3655 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3656 }
3657
926a01dc
WHX		 3658 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3659 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3660 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3661 V2_QPC_BYTE_16_PD_S, 0);
3662
3663 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3664 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3665 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3666 V2_QPC_BYTE_80_RX_CQN_S, 0);
3667
3668 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3669 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3670 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3671 V2_QPC_BYTE_252_TX_CQN_S, 0);
3672
3673 if (ibqp->srq) {
3674 roce_set_bit(context->byte_76_srqn_op_en,
3675 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3676 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3677 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3678 roce_set_field(context->byte_76_srqn_op_en,
3679 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3680 to_hr_srq(ibqp->srq)->srqn);
3681 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3682 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3683 }
3684
926a01dc
WHX		 3685 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3686 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3687 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3688 V2_QPC_BYTE_4_SQPN_S, 0);
3689
b6dd9b34 3690 if (attr_mask & IB_QP_DEST_QPN) {
3691 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3692 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3693 roce_set_field(qpc_mask->byte_56_dqpn_err,
3694 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3695 }
926a01dc
WHX		 3696}
3697
8d18ad83
LO		 3698static bool check_wqe_rq_mtt_count(struct hns_roce_dev *hr_dev,
3699 struct hns_roce_qp *hr_qp, int mtt_cnt,
3700 u32 page_size)
3701{
ae1c6148 3702 struct ib_device *ibdev = &hr_dev->ib_dev;
8d18ad83
LO		 3703
3704 if (hr_qp->rq.wqe_cnt < 1)
3705 return true;
3706
3707 if (mtt_cnt < 1) {
ae1c6148
LO		 3708 ibdev_err(ibdev, "failed to find RQWQE buf ba of QP(0x%lx)\n",
3709 hr_qp->qpn);
8d18ad83
LO		 3710 return false;
3711 }
3712
3713 if (mtt_cnt < MTT_MIN_COUNT &&
3714 (hr_qp->rq.offset + page_size) < hr_qp->buff_size) {
ae1c6148
LO		 3715 ibdev_err(ibdev,
3716 "failed to find next RQWQE buf ba of QP(0x%lx)\n",
3717 hr_qp->qpn);
8d18ad83
LO		 3718 return false;
3719 }
3720
3721 return true;
3722}
3723
926a01dc
WHX		 3724static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3725 const struct ib_qp_attr *attr, int attr_mask,
3726 struct hns_roce_v2_qp_context *context,
3727 struct hns_roce_v2_qp_context *qpc_mask)
3728{
3729 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3730 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3731 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 3732 struct ib_device *ibdev = &hr_dev->ib_dev;
8d18ad83 3733 u64 mtts[MTT_MIN_COUNT] = { 0 };
e92f2c18 3734 dma_addr_t dma_handle_3;
926a01dc 3735 dma_addr_t dma_handle_2;
8d18ad83 3736 u64 wqe_sge_ba;
926a01dc
WHX		 3737 u32 page_size;
3738 u8 port_num;
e92f2c18 3739 u64 *mtts_3;
926a01dc 3740 u64 *mtts_2;
8d18ad83 3741 int count;
926a01dc
WHX		 3742 u8 *dmac;
3743 u8 *smac;
3744 int port;
3745
3746 /* Search qp buf's mtts */
d563099e 3747 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift;
8d18ad83
LO		 3748 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
3749 hr_qp->rq.offset / page_size, mtts,
3750 MTT_MIN_COUNT, &wqe_sge_ba);
3751 if (!ibqp->srq)
3752 if (!check_wqe_rq_mtt_count(hr_dev, hr_qp, count, page_size))
3753 return -EINVAL;
926a01dc
WHX		 3754
3755 /* Search IRRL's mtts */
3756 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3757 hr_qp->qpn, &dma_handle_2);
3758 if (!mtts_2) {
ae1c6148 3759 ibdev_err(ibdev, "failed to find QP irrl_table\n");
926a01dc
WHX		 3760 return -EINVAL;
3761 }
3762
e92f2c18 3763 /* Search TRRL's mtts */
3764 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3765 hr_qp->qpn, &dma_handle_3);
3766 if (!mtts_3) {
ae1c6148 3767 ibdev_err(ibdev, "failed to find QP trrl_table\n");
e92f2c18 3768 return -EINVAL;
3769 }
3770
734f3863 3771 if (attr_mask & IB_QP_ALT_PATH) {
ae1c6148
LO		 3772 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error\n",
3773 attr_mask);
926a01dc
WHX		 3774 return -EINVAL;
3775 }
3776
3777 dmac = (u8 *)attr->ah_attr.roce.dmac;
bfe86035 3778 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
926a01dc
WHX		 3779 qpc_mask->wqe_sge_ba = 0;
3780
3781 /*
3782 * In v2 engine, software pass context and context mask to hardware
3783 * when modifying qp. If software need modify some fields in context,
3784 * we should set all bits of the relevant fields in context mask to
3785 * 0 at the same time, else set them to 0x1.
3786 */
3787 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
8d18ad83 3788 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3));
926a01dc
WHX		 3789 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3790 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3791
3792 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3793 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
8d18ad83
LO		 3794 hr_dev->caps.wqe_sq_hop_num == HNS_ROCE_HOP_NUM_0 ?
3795 0 : hr_dev->caps.wqe_sq_hop_num);
926a01dc
WHX		 3796 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3797 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3798
3799 roce_set_field(context->byte_20_smac_sgid_idx,
3800 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3801 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
8d18ad83
LO		 3802 ((ibqp->qp_type == IB_QPT_GSI) ||
3803 hr_qp->sq.max_gs > HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ?
3804 hr_dev->caps.wqe_sge_hop_num : 0);
926a01dc
WHX		 3805 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3806 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3807 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3808
3809 roce_set_field(context->byte_20_smac_sgid_idx,
3810 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3811 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
8d18ad83
LO		 3812 hr_dev->caps.wqe_rq_hop_num == HNS_ROCE_HOP_NUM_0 ?
3813 0 : hr_dev->caps.wqe_rq_hop_num);
926a01dc
WHX		 3814 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3815 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3816 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3817
3818 roce_set_field(context->byte_16_buf_ba_pg_sz,
3819 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3820 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
d563099e 3821 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
926a01dc
WHX		 3822 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3823 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3824 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3825
3826 roce_set_field(context->byte_16_buf_ba_pg_sz,
3827 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3828 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
d563099e 3829 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
926a01dc
WHX		 3830 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3831 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3832 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3833
d563099e 3834 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
926a01dc
WHX		 3835 qpc_mask->rq_cur_blk_addr = 0;
3836
3837 roce_set_field(context->byte_92_srq_info,
3838 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3839 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
d563099e 3840 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
926a01dc
WHX		 3841 roce_set_field(qpc_mask->byte_92_srq_info,
3842 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3843 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3844
d563099e 3845 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
926a01dc
WHX		 3846 qpc_mask->rq_nxt_blk_addr = 0;
3847
3848 roce_set_field(context->byte_104_rq_sge,
3849 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3850 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
d563099e 3851 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
926a01dc
WHX		 3852 roce_set_field(qpc_mask->byte_104_rq_sge,
3853 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3854 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3855
e92f2c18 3856 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3857 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3858 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3859 V2_QPC_BYTE_132_TRRL_BA_S, 0);
bfe86035 3860 context->trrl_ba = cpu_to_le32(dma_handle_3 >> (16 + 4));
e92f2c18 3861 qpc_mask->trrl_ba = 0;
3862 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3863 V2_QPC_BYTE_140_TRRL_BA_S,
3864 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3865 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3866 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3867
bfe86035 3868 context->irrl_ba = cpu_to_le32(dma_handle_2 >> 6);
926a01dc
WHX		 3869 qpc_mask->irrl_ba = 0;
3870 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3871 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3872 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3873 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3874 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3875
3876 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3877 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3878
3879 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3880 hr_qp->sq_signal_bits);
3881 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3882 0);
3883
3884 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3885
3886 smac = (u8 *)hr_dev->dev_addr[port];
3887 /* when dmac equals smac or loop_idc is 1, it should loopback */
3888 if (ether_addr_equal_unaligned(dmac, smac) ||
3889 hr_dev->loop_idc == 0x1) {
3890 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3891 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3892 }
3893
b6dd9b34 3894 if (attr_mask & IB_QP_DEST_QPN) {
3895 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3896 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3897 roce_set_field(qpc_mask->byte_56_dqpn_err,
3898 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3899 }
926a01dc
WHX		 3900
3901 /* Configure GID index */
3902 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3903 roce_set_field(context->byte_20_smac_sgid_idx,
60262b10 3904 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
926a01dc
WHX		 3905 hns_get_gid_index(hr_dev, port_num - 1,
3906 grh->sgid_index));
3907 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
60262b10 3908 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
2a3d923f 3909 memcpy(&(context->dmac), dmac, sizeof(u32));
926a01dc
WHX		 3910 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3911 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3912 qpc_mask->dmac = 0;
3913 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3914 V2_QPC_BYTE_52_DMAC_S, 0);
3915
2a3d923f 3916 /* mtu*(2^LP_PKTN_INI) should not bigger than 1 message length 64kb */
926a01dc 3917 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
9d04d56c 3918 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
926a01dc
WHX		 3919 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3920 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3921
0fa95a9a 3922 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3923 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3924 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3925 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3926 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3927 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3928
926a01dc
WHX		 3929 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3930 V2_QPC_BYTE_24_MTU_S, 0);
3931
926a01dc
WHX		 3932 roce_set_field(context->byte_84_rq_ci_pi,
3933 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3934 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3935 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3936 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3937 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3938
3939 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3940 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3941 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3942 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3943 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3944 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3945 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3946 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3947 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3948 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3949
3950 context->rq_rnr_timer = 0;
3951 qpc_mask->rq_rnr_timer = 0;
3952
926a01dc
WHX		 3953 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3954 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3955 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3956 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3957
2a3d923f 3958 /* rocee send 2^lp_sgen_ini segs every time */
926a01dc
WHX		 3959 roce_set_field(context->byte_168_irrl_idx,
3960 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3961 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3962 roce_set_field(qpc_mask->byte_168_irrl_idx,
3963 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3964 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3965
926a01dc
WHX		 3966 return 0;
3967}
3968
3969static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3970 const struct ib_qp_attr *attr, int attr_mask,
3971 struct hns_roce_v2_qp_context *context,
3972 struct hns_roce_v2_qp_context *qpc_mask)
3973{
3974 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3975 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 3976 struct ib_device *ibdev = &hr_dev->ib_dev;
8d18ad83
LO		 3977 u64 sge_cur_blk = 0;
3978 u64 sq_cur_blk = 0;
befb63b4 3979 u32 page_size;
8d18ad83 3980 int count;
926a01dc
WHX		 3981
3982 /* Search qp buf's mtts */
8d18ad83
LO		 3983 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
3984 if (count < 1) {
d563099e 3985 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf\n",
ae1c6148 3986 hr_qp->qpn);
926a01dc
WHX		 3987 return -EINVAL;
3988 }
3989
8d18ad83 3990 if (hr_qp->sge.offset) {
d563099e 3991 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift;
8d18ad83
LO		 3992 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
3993 hr_qp->sge.offset / page_size,
3994 &sge_cur_blk, 1, NULL);
3995 if (count < 1) {
d563099e 3996 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf\n",
ae1c6148 3997 hr_qp->qpn);
8d18ad83
LO		 3998 return -EINVAL;
3999 }
4000 }
4001
734f3863 4002 /* Not support alternate path and path migration */
d398d4ca 4003 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
ae1c6148 4004 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
926a01dc
WHX		 4005 return -EINVAL;
4006 }
4007
4008 /*
4009 * In v2 engine, software pass context and context mask to hardware
4010 * when modifying qp. If software need modify some fields in context,
4011 * we should set all bits of the relevant fields in context mask to
4012 * 0 at the same time, else set them to 0x1.
4013 */
d563099e 4014 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
926a01dc
WHX		 4015 roce_set_field(context->byte_168_irrl_idx,
4016 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
4017 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
d563099e 4018 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
926a01dc
WHX		 4019 qpc_mask->sq_cur_blk_addr = 0;
4020 roce_set_field(qpc_mask->byte_168_irrl_idx,
4021 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
4022 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
4023
2a3d923f
LO		 4024 context->sq_cur_sge_blk_addr = ((ibqp->qp_type == IB_QPT_GSI) ||
4025 hr_qp->sq.max_gs > HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ?
d563099e 4026 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk)) : 0;
befb63b4 4027 roce_set_field(context->byte_184_irrl_idx,
4028 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
4029 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
2a3d923f
LO		 4030 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs >
4031 HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ?
d563099e 4032 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)) : 0);
befb63b4 4033 qpc_mask->sq_cur_sge_blk_addr = 0;
4034 roce_set_field(qpc_mask->byte_184_irrl_idx,
4035 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
4036 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
4037
bfe86035 4038 context->rx_sq_cur_blk_addr =
d563099e 4039 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
926a01dc
WHX		 4040 roce_set_field(context->byte_232_irrl_sge,
4041 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
4042 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
d563099e 4043 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
926a01dc
WHX		 4044 qpc_mask->rx_sq_cur_blk_addr = 0;
4045 roce_set_field(qpc_mask->byte_232_irrl_sge,
4046 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
4047 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
4048
4049 /*
4050 * Set some fields in context to zero, Because the default values
4051 * of all fields in context are zero, we need not set them to 0 again.
4052 * but we should set the relevant fields of context mask to 0.
4053 */
4054 roce_set_field(qpc_mask->byte_232_irrl_sge,
4055 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
4056 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
4057
4058 roce_set_field(qpc_mask->byte_240_irrl_tail,
4059 V2_QPC_BYTE_240_RX_ACK_MSN_M,
4060 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
4061
926a01dc
WHX		 4062 roce_set_field(qpc_mask->byte_248_ack_psn,
4063 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
4064 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
4065 roce_set_bit(qpc_mask->byte_248_ack_psn,
4066 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
4067 roce_set_field(qpc_mask->byte_248_ack_psn,
4068 V2_QPC_BYTE_248_IRRL_PSN_M,
4069 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
4070
4071 roce_set_field(qpc_mask->byte_240_irrl_tail,
4072 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
4073 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
4074
926a01dc
WHX		 4075 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4076 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
4077 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
4078
4079 roce_set_bit(qpc_mask->byte_248_ack_psn,
4080 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
4081
4082 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
4083 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
4084
926a01dc
WHX		 4085 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4086 V2_QPC_BYTE_212_LSN_S, 0x100);
4087 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4088 V2_QPC_BYTE_212_LSN_S, 0);
4089
926a01dc
WHX		 4090 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
4091 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
926a01dc
WHX		 4092
4093 return 0;
4094}
4095
233673e4
LO		 4096static inline bool hns_roce_v2_check_qp_stat(enum ib_qp_state cur_state,
4097 enum ib_qp_state new_state)
4098{
4099
4100 if ((cur_state != IB_QPS_RESET &&
4101 (new_state == IB_QPS_ERR || new_state == IB_QPS_RESET)) ||
4102 ((cur_state == IB_QPS_RTS || cur_state == IB_QPS_SQD) &&
4103 (new_state == IB_QPS_RTS || new_state == IB_QPS_SQD)) ||
4104 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS))
4105 return true;
4106
4107 return false;
4108
4109}
4110
606bf89e
LO		 4111static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4112 const struct ib_qp_attr *attr,
4113 int attr_mask,
4114 struct hns_roce_v2_qp_context *context,
4115 struct hns_roce_v2_qp_context *qpc_mask)
926a01dc 4116{
606bf89e 4117 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
926a01dc
WHX		 4118 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4119 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 4120 struct ib_device *ibdev = &hr_dev->ib_dev;
606bf89e
LO		 4121 const struct ib_gid_attr *gid_attr = NULL;
4122 int is_roce_protocol;
32883228 4123 u16 vlan_id = 0xffff;
606bf89e 4124 bool is_udp = false;
606bf89e
LO		 4125 u8 ib_port;
4126 u8 hr_port;
4127 int ret;
926a01dc 4128
606bf89e
LO		 4129 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4130 hr_port = ib_port - 1;
4131 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4132 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4133
4134 if (is_roce_protocol) {
4135 gid_attr = attr->ah_attr.grh.sgid_attr;
32883228 4136 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
606bf89e
LO		 4137 if (ret)
4138 return ret;
4139
4140 if (gid_attr)
4141 is_udp = (gid_attr->gid_type ==
4142 IB_GID_TYPE_ROCE_UDP_ENCAP);
4143 }
4144
32883228 4145 if (vlan_id < VLAN_N_VID) {
606bf89e
LO		 4146 roce_set_bit(context->byte_76_srqn_op_en,
4147 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
4148 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
4149 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
4150 roce_set_bit(context->byte_168_irrl_idx,
4151 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
4152 roce_set_bit(qpc_mask->byte_168_irrl_idx,
4153 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
4154 }
4155
4156 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
32883228 4157 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id);
606bf89e
LO		 4158 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
4159 V2_QPC_BYTE_24_VLAN_ID_S, 0);
4160
4161 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
ae1c6148
LO		 4162 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4163 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
606bf89e
LO		 4164 return -EINVAL;
4165 }
4166
4167 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
ae1c6148 4168 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
606bf89e
LO		 4169 return -EINVAL;
4170 }
4171
4172 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4173 V2_QPC_BYTE_52_UDPSPN_S,
4174 is_udp ? 0x12b7 : 0);
4175
4176 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4177 V2_QPC_BYTE_52_UDPSPN_S, 0);
4178
4179 roce_set_field(context->byte_20_smac_sgid_idx,
4180 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
4181 grh->sgid_index);
4182
4183 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4184 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
4185
4186 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4187 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
4188 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4189 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
4190
dfaf2854 4191 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B && is_udp)
606bf89e
LO		 4192 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4193 V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2);
4194 else
4195 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4196 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
4197 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4198 V2_QPC_BYTE_24_TC_S, 0);
4199 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4200 V2_QPC_BYTE_28_FL_S, grh->flow_label);
4201 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4202 V2_QPC_BYTE_28_FL_S, 0);
4203 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4204 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4205 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4206 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr));
4207 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4208 V2_QPC_BYTE_28_SL_S, 0);
4209 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4210
4211 return 0;
4212}
4213
4214static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4215 const struct ib_qp_attr *attr,
4216 int attr_mask,
4217 enum ib_qp_state cur_state,
4218 enum ib_qp_state new_state,
4219 struct hns_roce_v2_qp_context *context,
4220 struct hns_roce_v2_qp_context *qpc_mask)
4221{
4222 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4223 int ret = 0;
926a01dc 4224
926a01dc 4225 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
9f507101 4226 memset(qpc_mask, 0, sizeof(*qpc_mask));
0fa95a9a 4227 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
4228 qpc_mask);
926a01dc
WHX		 4229 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4230 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
4231 qpc_mask);
4232 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4233 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4234 qpc_mask);
4235 if (ret)
4236 goto out;
4237 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4238 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
4239 qpc_mask);
4240 if (ret)
4241 goto out;
233673e4 4242 } else if (hns_roce_v2_check_qp_stat(cur_state, new_state)) {
926a01dc
WHX		 4243 /* Nothing */
4244 ;
4245 } else {
ae1c6148 4246 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
ac7cbf96 4247 ret = -EINVAL;
926a01dc
WHX		 4248 goto out;
4249 }
4250
606bf89e
LO		 4251out:
4252 return ret;
4253}
9c6ccc03 4254
606bf89e
LO		 4255static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
4256 const struct ib_qp_attr *attr,
4257 int attr_mask,
4258 struct hns_roce_v2_qp_context *context,
4259 struct hns_roce_v2_qp_context *qpc_mask)
4260{
4261 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4262 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4263 int ret = 0;
0425e3e6 4264
610b8967 4265 if (attr_mask & IB_QP_AV) {
606bf89e
LO		 4266 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
4267 qpc_mask);
4268 if (ret)
4269 return ret;
610b8967
LO		 4270 }
4271
5b01b243
LO		 4272 if (attr_mask & IB_QP_TIMEOUT) {
4273 if (attr->timeout < 31) {
4274 roce_set_field(context->byte_28_at_fl,
4275 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4276 attr->timeout);
4277 roce_set_field(qpc_mask->byte_28_at_fl,
4278 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4279 0);
4280 } else {
ae1c6148
LO		 4281 ibdev_warn(&hr_dev->ib_dev,
4282 "Local ACK timeout shall be 0 to 30.\n");
5b01b243
LO		 4283 }
4284 }
4285
4286 if (attr_mask & IB_QP_RETRY_CNT) {
4287 roce_set_field(context->byte_212_lsn,
4288 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4289 V2_QPC_BYTE_212_RETRY_NUM_INIT_S,
4290 attr->retry_cnt);
4291 roce_set_field(qpc_mask->byte_212_lsn,
4292 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4293 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
4294
4295 roce_set_field(context->byte_212_lsn,
4296 V2_QPC_BYTE_212_RETRY_CNT_M,
60262b10 4297 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
5b01b243
LO		 4298 roce_set_field(qpc_mask->byte_212_lsn,
4299 V2_QPC_BYTE_212_RETRY_CNT_M,
4300 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
4301 }
4302
4303 if (attr_mask & IB_QP_RNR_RETRY) {
4304 roce_set_field(context->byte_244_rnr_rxack,
4305 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4306 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
4307 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4308 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4309 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
4310
4311 roce_set_field(context->byte_244_rnr_rxack,
4312 V2_QPC_BYTE_244_RNR_CNT_M,
4313 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
4314 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4315 V2_QPC_BYTE_244_RNR_CNT_M,
4316 V2_QPC_BYTE_244_RNR_CNT_S, 0);
4317 }
4318
606bf89e 4319 /* RC&UC&UD required attr */
f04cc178
LO		 4320 if (attr_mask & IB_QP_SQ_PSN) {
4321 roce_set_field(context->byte_172_sq_psn,
4322 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4323 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
4324 roce_set_field(qpc_mask->byte_172_sq_psn,
4325 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4326 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
4327
4328 roce_set_field(context->byte_196_sq_psn,
4329 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4330 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
4331 roce_set_field(qpc_mask->byte_196_sq_psn,
4332 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4333 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
4334
4335 roce_set_field(context->byte_220_retry_psn_msn,
4336 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4337 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
4338 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4339 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4340 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
4341
4342 roce_set_field(context->byte_224_retry_msg,
4343 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4344 V2_QPC_BYTE_224_RETRY_MSG_PSN_S,
2a3d923f 4345 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S);
f04cc178
LO		 4346 roce_set_field(qpc_mask->byte_224_retry_msg,
4347 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4348 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
4349
4350 roce_set_field(context->byte_224_retry_msg,
4351 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4352 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S,
4353 attr->sq_psn);
4354 roce_set_field(qpc_mask->byte_224_retry_msg,
4355 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4356 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
4357
4358 roce_set_field(context->byte_244_rnr_rxack,
4359 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4360 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
4361 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4362 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4363 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
4364 }
4365
5b01b243
LO		 4366 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
4367 attr->max_dest_rd_atomic) {
4368 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4369 V2_QPC_BYTE_140_RR_MAX_S,
4370 fls(attr->max_dest_rd_atomic - 1));
4371 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4372 V2_QPC_BYTE_140_RR_MAX_S, 0);
4373 }
4374
4375 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
4376 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
4377 V2_QPC_BYTE_208_SR_MAX_S,
4378 fls(attr->max_rd_atomic - 1));
4379 roce_set_field(qpc_mask->byte_208_irrl,
4380 V2_QPC_BYTE_208_SR_MAX_M,
4381 V2_QPC_BYTE_208_SR_MAX_S, 0);
4382 }
4383
ace1c541 4384 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4385 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4386
5b01b243
LO		 4387 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
4388 roce_set_field(context->byte_80_rnr_rx_cqn,
4389 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4390 V2_QPC_BYTE_80_MIN_RNR_TIME_S,
4391 attr->min_rnr_timer);
4392 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
4393 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4394 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
4395 }
4396
601f3e6d
LO		 4397 /* RC&UC required attr */
4398 if (attr_mask & IB_QP_RQ_PSN) {
4399 roce_set_field(context->byte_108_rx_reqepsn,
4400 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4401 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
4402 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4403 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4404 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
4405
4406 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
4407 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
4408 roce_set_field(qpc_mask->byte_152_raq,
4409 V2_QPC_BYTE_152_RAQ_PSN_M,
4410 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
4411 }
4412
5b01b243 4413 if (attr_mask & IB_QP_QKEY) {
bfe86035 4414 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5b01b243
LO		 4415 qpc_mask->qkey_xrcd = 0;
4416 hr_qp->qkey = attr->qkey;
4417 }
4418
606bf89e
LO		 4419 return ret;
4420}
4421
4422static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
4423 const struct ib_qp_attr *attr,
4424 int attr_mask)
4425{
4426 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4427 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4428
4429 if (attr_mask & IB_QP_ACCESS_FLAGS)
4430 hr_qp->atomic_rd_en = attr->qp_access_flags;
4431
4432 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4433 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4434 if (attr_mask & IB_QP_PORT) {
4435 hr_qp->port = attr->port_num - 1;
4436 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4437 }
4438}
4439
4440static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
4441 const struct ib_qp_attr *attr,
4442 int attr_mask, enum ib_qp_state cur_state,
4443 enum ib_qp_state new_state)
4444{
4445 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4446 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d
LC		 4447 struct hns_roce_v2_qp_context ctx[2];
4448 struct hns_roce_v2_qp_context *context = ctx;
4449 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
ae1c6148 4450 struct ib_device *ibdev = &hr_dev->ib_dev;
b5374286
YL		 4451 unsigned long sq_flag = 0;
4452 unsigned long rq_flag = 0;
b5c229dc 4453 int ret;
606bf89e 4454
606bf89e
LO		 4455 /*
4456 * In v2 engine, software pass context and context mask to hardware
4457 * when modifying qp. If software need modify some fields in context,
4458 * we should set all bits of the relevant fields in context mask to
4459 * 0 at the same time, else set them to 0x1.
4460 */
4b42d05d 4461 memset(context, 0, sizeof(*context));
606bf89e
LO		 4462 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
4463 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
4464 new_state, context, qpc_mask);
4465 if (ret)
4466 goto out;
4467
4468 /* When QP state is err, SQ and RQ WQE should be flushed */
4469 if (new_state == IB_QPS_ERR) {
b5374286 4470 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
b5374286 4471 hr_qp->state = IB_QPS_ERR;
606bf89e
LO		 4472 roce_set_field(context->byte_160_sq_ci_pi,
4473 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4474 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
4475 hr_qp->sq.head);
4476 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
4477 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4478 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
75c994e6 4479 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
606bf89e
LO		 4480
4481 if (!ibqp->srq) {
75c994e6 4482 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4483 roce_set_field(context->byte_84_rq_ci_pi,
4484 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4485 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
4486 hr_qp->rq.head);
4487 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
4488 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4489 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
75c994e6 4490 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4491 }
4492 }
4493
4494 /* Configure the optional fields */
4495 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
4496 qpc_mask);
4497 if (ret)
4498 goto out;
4499
c7bcb134
LO		 4500 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S,
4501 ibqp->srq ? 1 : 0);
4502 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4503 V2_QPC_BYTE_108_INV_CREDIT_S, 0);
4504
926a01dc 4505 /* Every status migrate must change state */
2362ccee 4506 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 4507 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 4508 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 4509 V2_QPC_BYTE_60_QP_ST_S, 0);
4510
4511 /* SW pass context to HW */
032b0574 4512 ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp);
926a01dc 4513 if (ret) {
ae1c6148 4514 ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret);
926a01dc
WHX		 4515 goto out;
4516 }
4517
4518 hr_qp->state = new_state;
4519
606bf89e 4520 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
926a01dc
WHX		 4521
4522 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
4523 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
4524 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
4525 if (ibqp->send_cq != ibqp->recv_cq)
4526 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4527 hr_qp->qpn, NULL);
4528
4529 hr_qp->rq.head = 0;
4530 hr_qp->rq.tail = 0;
4531 hr_qp->sq.head = 0;
4532 hr_qp->sq.tail = 0;
926a01dc 4533 hr_qp->next_sge = 0;
e088a685
YL		 4534 if (hr_qp->rq.wqe_cnt)
4535 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 4536 }
4537
4538out:
926a01dc
WHX		 4539 return ret;
4540}
4541
a3de9e83 4542static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
926a01dc 4543{
a3de9e83
LC		 4544 static const enum ib_qp_state map[] = {
4545 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
4546 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
4547 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
4548 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
4549 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
4550 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
4551 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
4552 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
4553 };
4554
4555 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
926a01dc
WHX		 4556}
4557
4558static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
4559 struct hns_roce_qp *hr_qp,
4560 struct hns_roce_v2_qp_context *hr_context)
4561{
4562 struct hns_roce_cmd_mailbox *mailbox;
4563 int ret;
4564
4565 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4566 if (IS_ERR(mailbox))
4567 return PTR_ERR(mailbox);
4568
4569 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
4570 HNS_ROCE_CMD_QUERY_QPC,
4571 HNS_ROCE_CMD_TIMEOUT_MSECS);
ae1c6148 4572 if (ret)
926a01dc 4573 goto out;
926a01dc
WHX		 4574
4575 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
4576
4577out:
4578 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4579 return ret;
4580}
4581
4582static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4583 int qp_attr_mask,
4584 struct ib_qp_init_attr *qp_init_attr)
4585{
4586 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4587 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d 4588 struct hns_roce_v2_qp_context context = {};
ae1c6148 4589 struct ib_device *ibdev = &hr_dev->ib_dev;
926a01dc
WHX		 4590 int tmp_qp_state;
4591 int state;
4592 int ret;
4593
926a01dc
WHX		 4594 memset(qp_attr, 0, sizeof(*qp_attr));
4595 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4596
4597 mutex_lock(&hr_qp->mutex);
4598
4599 if (hr_qp->state == IB_QPS_RESET) {
4600 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 4601 ret = 0;
926a01dc
WHX		 4602 goto done;
4603 }
4604
4b42d05d 4605 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context);
926a01dc 4606 if (ret) {
ae1c6148 4607 ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret);
926a01dc
WHX		 4608 ret = -EINVAL;
4609 goto out;
4610 }
4611
4b42d05d 4612 state = roce_get_field(context.byte_60_qpst_tempid,
926a01dc
WHX		 4613 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
4614 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
4615 if (tmp_qp_state == -1) {
ae1c6148 4616 ibdev_err(ibdev, "Illegal ib_qp_state\n");
926a01dc
WHX		 4617 ret = -EINVAL;
4618 goto out;
4619 }
4620 hr_qp->state = (u8)tmp_qp_state;
4621 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
4b42d05d 4622 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4623 V2_QPC_BYTE_24_MTU_M,
4624 V2_QPC_BYTE_24_MTU_S);
4625 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 4626 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 4627 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
4628 qp_attr->qkey = V2_QKEY_VAL;
4629
4b42d05d 4630 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn,
926a01dc
WHX		 4631 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4632 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
4b42d05d 4633 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn,
926a01dc
WHX		 4634 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4635 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
4b42d05d 4636 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err,
926a01dc
WHX		 4637 V2_QPC_BYTE_56_DQPN_M,
4638 V2_QPC_BYTE_56_DQPN_S);
4b42d05d 4639 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4640 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) |
4b42d05d 4641 ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4642 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) |
4b42d05d 4643 ((roce_get_bit(context.byte_76_srqn_op_en,
2a3d923f
LO		 4644 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S);
4645
926a01dc
WHX		 4646 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
4647 hr_qp->ibqp.qp_type == IB_QPT_UC) {
4648 struct ib_global_route *grh =
4649 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
4650
4651 rdma_ah_set_sl(&qp_attr->ah_attr,
4b42d05d 4652 roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4653 V2_QPC_BYTE_28_SL_M,
4654 V2_QPC_BYTE_28_SL_S));
4b42d05d 4655 grh->flow_label = roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4656 V2_QPC_BYTE_28_FL_M,
4657 V2_QPC_BYTE_28_FL_S);
4b42d05d 4658 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx,
926a01dc
WHX		 4659 V2_QPC_BYTE_20_SGID_IDX_M,
4660 V2_QPC_BYTE_20_SGID_IDX_S);
4b42d05d 4661 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4662 V2_QPC_BYTE_24_HOP_LIMIT_M,
4663 V2_QPC_BYTE_24_HOP_LIMIT_S);
4b42d05d 4664 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4665 V2_QPC_BYTE_24_TC_M,
4666 V2_QPC_BYTE_24_TC_S);
4667
4b42d05d 4668 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
926a01dc
WHX		 4669 }
4670
4671 qp_attr->port_num = hr_qp->port + 1;
4672 qp_attr->sq_draining = 0;
4b42d05d 4673 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl,
926a01dc
WHX		 4674 V2_QPC_BYTE_208_SR_MAX_M,
4675 V2_QPC_BYTE_208_SR_MAX_S);
4b42d05d 4676 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq,
926a01dc
WHX		 4677 V2_QPC_BYTE_140_RR_MAX_M,
4678 V2_QPC_BYTE_140_RR_MAX_S);
4b42d05d 4679 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn,
926a01dc
WHX		 4680 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4681 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4b42d05d 4682 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4683 V2_QPC_BYTE_28_AT_M,
4684 V2_QPC_BYTE_28_AT_S);
4b42d05d 4685 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn,
926a01dc
WHX		 4686 V2_QPC_BYTE_212_RETRY_CNT_M,
4687 V2_QPC_BYTE_212_RETRY_CNT_S);
bfe86035 4688 qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer);
926a01dc
WHX		 4689
4690done:
4691 qp_attr->cur_qp_state = qp_attr->qp_state;
4692 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4693 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4694
4695 if (!ibqp->uobject) {
4696 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4697 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4698 } else {
4699 qp_attr->cap.max_send_wr = 0;
4700 qp_attr->cap.max_send_sge = 0;
4701 }
4702
4703 qp_init_attr->cap = qp_attr->cap;
4704
4705out:
4706 mutex_unlock(&hr_qp->mutex);
926a01dc
WHX		 4707 return ret;
4708}
4709
4710static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4711 struct hns_roce_qp *hr_qp,
bdeacabd 4712 struct ib_udata *udata)
926a01dc 4713{
db50077b 4714 struct ib_device *ibdev = &hr_dev->ib_dev;
ae1c6148 4715 struct hns_roce_cq *send_cq, *recv_cq;
626903e9 4716 unsigned long flags;
d302c6e3 4717 int ret = 0;
926a01dc
WHX		 4718
4719 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4720 /* Modify qp to reset before destroying qp */
4721 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4722 hr_qp->state, IB_QPS_RESET);
d302c6e3 4723 if (ret)
ae1c6148
LO		 4724 ibdev_err(ibdev,
4725 "failed to modify QP to RST, ret = %d\n",
4726 ret);
926a01dc
WHX		 4727 }
4728
626903e9
XW		 4729 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
4730 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
926a01dc 4731
626903e9 4732 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
926a01dc
WHX		 4733 hns_roce_lock_cqs(send_cq, recv_cq);
4734
bdeacabd 4735 if (!udata) {
626903e9
XW		 4736 if (recv_cq)
4737 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
4738 (hr_qp->ibqp.srq ?
4739 to_hr_srq(hr_qp->ibqp.srq) :
4740 NULL));
4741
4742 if (send_cq && send_cq != recv_cq)
926a01dc 4743 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
626903e9 4744
926a01dc
WHX		 4745 }
4746
4747 hns_roce_qp_remove(hr_dev, hr_qp);
4748
4749 hns_roce_unlock_cqs(send_cq, recv_cq);
626903e9 4750 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
926a01dc 4751
d302c6e3 4752 return ret;
926a01dc
WHX		 4753}
4754
c4367a26 4755static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
926a01dc
WHX		 4756{
4757 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4758 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4759 int ret;
4760
bdeacabd 4761 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
d302c6e3 4762 if (ret)
ae1c6148
LO		 4763 ibdev_err(&hr_dev->ib_dev,
4764 "failed to destroy QP 0x%06lx, ret = %d\n",
db50077b 4765 hr_qp->qpn, ret);
926a01dc 4766
e365b26c 4767 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
926a01dc
WHX		 4768
4769 return 0;
4770}
4771
aa84fa18 4772static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
ae1c6148 4773 struct hns_roce_qp *hr_qp)
aa84fa18 4774{
ae1c6148 4775 struct ib_device *ibdev = &hr_dev->ib_dev;
da91ddfd 4776 struct hns_roce_sccc_clr_done *resp;
aa84fa18
YL		 4777 struct hns_roce_sccc_clr *clr;
4778 struct hns_roce_cmq_desc desc;
4779 int ret, i;
4780
4781 mutex_lock(&hr_dev->qp_table.scc_mutex);
4782
4783 /* set scc ctx clear done flag */
4784 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
aa84fa18
YL		 4785 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4786 if (ret) {
ae1c6148 4787 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4788 goto out;
4789 }
4790
4791 /* clear scc context */
4792 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
4793 clr = (struct hns_roce_sccc_clr *)desc.data;
4794 clr->qpn = cpu_to_le32(hr_qp->qpn);
4795 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4796 if (ret) {
ae1c6148 4797 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4798 goto out;
4799 }
4800
4801 /* query scc context clear is done or not */
4802 resp = (struct hns_roce_sccc_clr_done *)desc.data;
4803 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
4804 hns_roce_cmq_setup_basic_desc(&desc,
4805 HNS_ROCE_OPC_QUERY_SCCC, true);
4806 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4807 if (ret) {
ae1c6148
LO		 4808 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
4809 ret);
aa84fa18
YL		 4810 goto out;
4811 }
4812
4813 if (resp->clr_done)
4814 goto out;
4815
4816 msleep(20);
4817 }
4818
ae1c6148 4819 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n");
aa84fa18
YL		 4820 ret = -ETIMEDOUT;
4821
4822out:
4823 mutex_unlock(&hr_dev->qp_table.scc_mutex);
4824 return ret;
4825}
4826
b156269d 4827static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
4828{
4829 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
4830 struct hns_roce_v2_cq_context *cq_context;
4831 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
4832 struct hns_roce_v2_cq_context *cqc_mask;
4833 struct hns_roce_cmd_mailbox *mailbox;
4834 int ret;
4835
4836 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4837 if (IS_ERR(mailbox))
4838 return PTR_ERR(mailbox);
4839
4840 cq_context = mailbox->buf;
4841 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
4842
4843 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
4844
4845 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4846 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4847 cq_count);
4848 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4849 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4850 0);
4851 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4852 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4853 cq_period);
4854 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4855 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4856 0);
4857
4858 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
4859 HNS_ROCE_CMD_MODIFY_CQC,
4860 HNS_ROCE_CMD_TIMEOUT_MSECS);
4861 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4862 if (ret)
ae1c6148
LO		 4863 ibdev_err(&hr_dev->ib_dev,
4864 "failed to process cmd when modifying CQ, ret = %d\n",
4865 ret);
b156269d 4866
4867 return ret;
4868}
4869
0425e3e6
YL		 4870static void hns_roce_irq_work_handle(struct work_struct *work)
4871{
4872 struct hns_roce_work *irq_work =
4873 container_of(work, struct hns_roce_work, work);
ae1c6148 4874 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
0425e3e6 4875 u32 qpn = irq_work->qpn;
b00a92c8 4876 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4877
4878 switch (irq_work->event_type) {
b00a92c8 4879 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
ae1c6148 4880 ibdev_info(ibdev, "Path migrated succeeded.\n");
b00a92c8 4881 break;
4882 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
ae1c6148 4883 ibdev_warn(ibdev, "Path migration failed.\n");
b00a92c8 4884 break;
4885 case HNS_ROCE_EVENT_TYPE_COMM_EST:
b00a92c8 4886 break;
4887 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
ae1c6148 4888 ibdev_warn(ibdev, "Send queue drained.\n");
b00a92c8 4889 break;
0425e3e6 4890 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
ae1c6148
LO		 4891 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n",
4892 qpn, irq_work->sub_type);
b00a92c8 4893 break;
0425e3e6 4894 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
ae1c6148
LO		 4895 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n",
4896 qpn);
b00a92c8 4897 break;
0425e3e6 4898 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
ae1c6148
LO		 4899 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n",
4900 qpn, irq_work->sub_type);
b00a92c8 4901 break;
4902 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
ae1c6148 4903 ibdev_warn(ibdev, "SRQ limit reach.\n");
b00a92c8 4904 break;
4905 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
ae1c6148 4906 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
b00a92c8 4907 break;
4908 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
ae1c6148 4909 ibdev_err(ibdev, "SRQ catas error.\n");
b00a92c8 4910 break;
4911 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
ae1c6148 4912 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn);
b00a92c8 4913 break;
4914 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
ae1c6148 4915 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn);
b00a92c8 4916 break;
4917 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
ae1c6148 4918 ibdev_warn(ibdev, "DB overflow.\n");
b00a92c8 4919 break;
4920 case HNS_ROCE_EVENT_TYPE_FLR:
ae1c6148 4921 ibdev_warn(ibdev, "Function level reset.\n");
0425e3e6
YL		 4922 break;
4923 default:
4924 break;
4925 }
4926
4927 kfree(irq_work);
4928}
4929
4930static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4931 struct hns_roce_eq *eq,
4932 u32 qpn, u32 cqn)
0425e3e6
YL		 4933{
4934 struct hns_roce_work *irq_work;
4935
4936 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4937 if (!irq_work)
4938 return;
4939
4940 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4941 irq_work->hr_dev = hr_dev;
4942 irq_work->qpn = qpn;
b00a92c8 4943 irq_work->cqn = cqn;
0425e3e6
YL		 4944 irq_work->event_type = eq->event_type;
4945 irq_work->sub_type = eq->sub_type;
4946 queue_work(hr_dev->irq_workq, &(irq_work->work));
4947}
4948
a5073d60
YL		 4949static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4950{
d3743fa9 4951 struct hns_roce_dev *hr_dev = eq->hr_dev;
880f133c 4952 __le32 doorbell[2] = {};
a5073d60
YL		 4953
4954 if (eq->type_flag == HNS_ROCE_AEQ) {
4955 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4956 HNS_ROCE_V2_EQ_DB_CMD_S,
4957 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4958 HNS_ROCE_EQ_DB_CMD_AEQ :
4959 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4960 } else {
4961 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4962 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4963
4964 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4965 HNS_ROCE_V2_EQ_DB_CMD_S,
4966 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4967 HNS_ROCE_EQ_DB_CMD_CEQ :
4968 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4969 }
4970
4971 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4972 HNS_ROCE_V2_EQ_DB_PARA_S,
4973 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4974
d3743fa9 4975 hns_roce_write64(hr_dev, doorbell, eq->doorbell);
a5073d60
YL		 4976}
4977
a5073d60
YL		 4978static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4979{
4980 struct hns_roce_aeqe *aeqe;
4981
477a0a38 4982 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a
XW		 4983 (eq->cons_index & (eq->entries - 1)) *
4984 HNS_ROCE_AEQ_ENTRY_SIZE);
4985
a5073d60
YL		 4986 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4987 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4988}
4989
4990static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4991 struct hns_roce_eq *eq)
4992{
4993 struct device *dev = hr_dev->dev;
e7f40440 4994 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 4995 int aeqe_found = 0;
4996 int event_type;
0425e3e6 4997 int sub_type;
81fce629 4998 u32 srqn;
0425e3e6
YL		 4999 u32 qpn;
5000 u32 cqn;
a5073d60 5001
e7f40440 5002 while (aeqe) {
4044a3f4
YL		 5003 /* Make sure we read AEQ entry after we have checked the
5004 * ownership bit
5005 */
5006 dma_rmb();
a5073d60
YL		 5007
5008 event_type = roce_get_field(aeqe->asyn,
5009 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
5010 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 5011 sub_type = roce_get_field(aeqe->asyn,
5012 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
5013 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
5014 qpn = roce_get_field(aeqe->event.qp_event.qp,
5015 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5016 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5017 cqn = roce_get_field(aeqe->event.cq_event.cq,
5018 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5019 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
81fce629
LO		 5020 srqn = roce_get_field(aeqe->event.srq_event.srq,
5021 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5022 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 5023
5024 switch (event_type) {
5025 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 5026 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 5027 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5028 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5029 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
81fce629 5030 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
a5073d60
YL		 5031 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5032 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 5033 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 5034 break;
5035 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
a5073d60 5036 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
81fce629 5037 hns_roce_srq_event(hr_dev, srqn, event_type);
a5073d60
YL		 5038 break;
5039 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5040 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 5041 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 5042 break;
5043 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 5044 break;
5045 case HNS_ROCE_EVENT_TYPE_MB:
5046 hns_roce_cmd_event(hr_dev,
5047 le16_to_cpu(aeqe->event.cmd.token),
5048 aeqe->event.cmd.status,
5049 le64_to_cpu(aeqe->event.cmd.out_param));
5050 break;
5051 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 5052 break;
5053 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 5054 break;
5055 default:
5056 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
5057 event_type, eq->eqn, eq->cons_index);
5058 break;
790b57f6 5059 }
a5073d60 5060
0425e3e6
YL		 5061 eq->event_type = event_type;
5062 eq->sub_type = sub_type;
a5073d60
YL		 5063 ++eq->cons_index;
5064 aeqe_found = 1;
5065
249f2f92 5066 if (eq->cons_index > (2 * eq->entries - 1))
a5073d60 5067 eq->cons_index = 0;
249f2f92 5068
b00a92c8 5069 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
e7f40440
LC		 5070
5071 aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 5072 }
5073
5074 set_eq_cons_index_v2(eq);
5075 return aeqe_found;
5076}
5077
a5073d60
YL		 5078static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
5079{
5080 struct hns_roce_ceqe *ceqe;
5081
477a0a38 5082 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a
XW		 5083 (eq->cons_index & (eq->entries - 1)) *
5084 HNS_ROCE_CEQ_ENTRY_SIZE);
a5073d60
YL		 5085 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
5086 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
5087}
5088
5089static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
5090 struct hns_roce_eq *eq)
5091{
e7f40440 5092 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5093 int ceqe_found = 0;
5094 u32 cqn;
5095
e7f40440 5096 while (ceqe) {
4044a3f4
YL		 5097 /* Make sure we read CEQ entry after we have checked the
5098 * ownership bit
5099 */
5100 dma_rmb();
5101
60262b10 5102 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M,
a5073d60
YL		 5103 HNS_ROCE_V2_CEQE_COMP_CQN_S);
5104
5105 hns_roce_cq_completion(hr_dev, cqn);
5106
5107 ++eq->cons_index;
5108 ceqe_found = 1;
5109
bceda6e6 5110 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1))
a5073d60 5111 eq->cons_index = 0;
e7f40440
LC		 5112
5113 ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5114 }
5115
5116 set_eq_cons_index_v2(eq);
5117
5118 return ceqe_found;
5119}
5120
5121static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
5122{
5123 struct hns_roce_eq *eq = eq_ptr;
5124 struct hns_roce_dev *hr_dev = eq->hr_dev;
5125 int int_work = 0;
5126
5127 if (eq->type_flag == HNS_ROCE_CEQ)
5128 /* Completion event interrupt */
5129 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
5130 else
5131 /* Asychronous event interrupt */
5132 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5133
5134 return IRQ_RETVAL(int_work);
5135}
5136
5137static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5138{
5139 struct hns_roce_dev *hr_dev = dev_id;
5140 struct device *dev = hr_dev->dev;
5141 int int_work = 0;
5142 u32 int_st;
5143 u32 int_en;
5144
5145 /* Abnormal interrupt */
5146 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5147 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5148
bfe86035 5149 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
2b9acb9a
XT		 5150 struct pci_dev *pdev = hr_dev->pci_dev;
5151 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5152 const struct hnae3_ae_ops *ops = ae_dev->ops;
5153
a5073d60
YL		 5154 dev_err(dev, "AEQ overflow!\n");
5155
bfe86035 5156 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S;
a5073d60
YL		 5157 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5158
2b9acb9a
XT		 5159 /* Set reset level for reset_event() */
5160 if (ops->set_default_reset_request)
5161 ops->set_default_reset_request(ae_dev,
5162 HNAE3_FUNC_RESET);
5163 if (ops->reset_event)
5164 ops->reset_event(pdev, NULL);
5165
bfe86035 5166 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5167 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5168
5169 int_work = 1;
bfe86035 5170 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
a5073d60
YL		 5171 dev_err(dev, "BUS ERR!\n");
5172
bfe86035 5173 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S;
a5073d60
YL		 5174 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5175
bfe86035 5176 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5177 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5178
5179 int_work = 1;
bfe86035 5180 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
a5073d60
YL		 5181 dev_err(dev, "OTHER ERR!\n");
5182
bfe86035 5183 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S;
a5073d60
YL		 5184 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5185
bfe86035 5186 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5187 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5188
5189 int_work = 1;
5190 } else
5191 dev_err(dev, "There is no abnormal irq found!\n");
5192
5193 return IRQ_RETVAL(int_work);
5194}
5195
5196static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5197 int eq_num, int enable_flag)
5198{
5199 int i;
5200
5201 if (enable_flag == EQ_ENABLE) {
5202 for (i = 0; i < eq_num; i++)
5203 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5204 i * EQ_REG_OFFSET,
5205 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
5206
5207 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5208 HNS_ROCE_V2_VF_ABN_INT_EN_M);
5209 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5210 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
5211 } else {
5212 for (i = 0; i < eq_num; i++)
5213 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5214 i * EQ_REG_OFFSET,
5215 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
5216
5217 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5218 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
5219 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5220 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
5221 }
5222}
5223
5224static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5225{
5226 struct device *dev = hr_dev->dev;
5227 int ret;
5228
5229 if (eqn < hr_dev->caps.num_comp_vectors)
5230 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5231 0, HNS_ROCE_CMD_DESTROY_CEQC,
5232 HNS_ROCE_CMD_TIMEOUT_MSECS);
5233 else
5234 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5235 0, HNS_ROCE_CMD_DESTROY_AEQC,
5236 HNS_ROCE_CMD_TIMEOUT_MSECS);
5237 if (ret)
5238 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5239}
5240
d7e2d343 5241static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
a5073d60 5242{
477a0a38 5243 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
a5073d60
YL		 5244}
5245
477a0a38
XW		 5246static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
5247 void *mb_buf)
a5073d60 5248{
477a0a38 5249 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
a5073d60 5250 struct hns_roce_eq_context *eqc;
477a0a38 5251 u64 bt_ba = 0;
d7e2d343 5252 int count;
a5073d60
YL		 5253
5254 eqc = mb_buf;
5255 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5256
5257 /* init eqc */
5258 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
a5073d60
YL		 5259 eq->cons_index = 0;
5260 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5261 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5262 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
a5073d60
YL		 5263 eq->shift = ilog2((unsigned int)eq->entries);
5264
cc23267a 5265 /* if not multi-hop, eqe buffer only use one trunk */
477a0a38
XW		 5266 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
5267 &bt_ba);
5268 if (count < 1) {
5269 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
5270 return -ENOBUFS;
d7e2d343 5271 }
a5073d60
YL		 5272
5273 /* set eqc state */
60262b10 5274 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S,
a5073d60
YL		 5275 HNS_ROCE_V2_EQ_STATE_VALID);
5276
5277 /* set eqe hop num */
60262b10 5278 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M,
a5073d60
YL		 5279 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
5280
5281 /* set eqc over_ignore */
60262b10 5282 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M,
a5073d60
YL		 5283 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
5284
5285 /* set eqc coalesce */
60262b10 5286 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M,
a5073d60
YL		 5287 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
5288
5289 /* set eqc arm_state */
60262b10 5290 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M,
a5073d60
YL		 5291 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
5292
5293 /* set eqn */
60262b10
LO		 5294 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S,
5295 eq->eqn);
a5073d60
YL		 5296
5297 /* set eqe_cnt */
60262b10
LO		 5298 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M,
5299 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT);
a5073d60
YL		 5300
5301 /* set eqe_ba_pg_sz */
60262b10 5302 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db 5303 HNS_ROCE_EQC_BA_PG_SZ_S,
477a0a38 5304 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
a5073d60
YL		 5305
5306 /* set eqe_buf_pg_sz */
60262b10 5307 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db 5308 HNS_ROCE_EQC_BUF_PG_SZ_S,
477a0a38 5309 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
a5073d60
YL		 5310
5311 /* set eq_producer_idx */
60262b10
LO		 5312 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M,
5313 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX);
a5073d60
YL		 5314
5315 /* set eq_max_cnt */
60262b10 5316 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M,
a5073d60
YL		 5317 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
5318
5319 /* set eq_period */
60262b10 5320 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M,
a5073d60
YL		 5321 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
5322
5323 /* set eqe_report_timer */
60262b10 5324 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M,
a5073d60
YL		 5325 HNS_ROCE_EQC_REPORT_TIMER_S,
5326 HNS_ROCE_EQ_INIT_REPORT_TIMER);
5327
477a0a38 5328 /* set bt_ba [34:3] */
60262b10 5329 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M,
477a0a38 5330 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3);
a5073d60 5331
477a0a38 5332 /* set bt_ba [64:35] */
60262b10 5333 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M,
477a0a38 5334 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35);
a5073d60
YL		 5335
5336 /* set eq shift */
60262b10
LO		 5337 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S,
5338 eq->shift);
a5073d60
YL		 5339
5340 /* set eq MSI_IDX */
60262b10
LO		 5341 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M,
5342 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX);
a5073d60
YL		 5343
5344 /* set cur_eqe_ba [27:12] */
60262b10 5345 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M,
477a0a38 5346 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12);
a5073d60
YL		 5347
5348 /* set cur_eqe_ba [59:28] */
60262b10 5349 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M,
477a0a38 5350 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28);
a5073d60
YL		 5351
5352 /* set cur_eqe_ba [63:60] */
60262b10 5353 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M,
477a0a38 5354 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60);
a5073d60
YL		 5355
5356 /* set eq consumer idx */
60262b10
LO		 5357 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
5358 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
a5073d60
YL		 5359
5360 /* set nex_eqe_ba[43:12] */
60262b10 5361 roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
477a0a38 5362 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
a5073d60
YL		 5363
5364 /* set nex_eqe_ba[63:44] */
60262b10 5365 roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
477a0a38 5366 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
a5073d60 5367
477a0a38 5368 return 0;
d7e2d343 5369}
a5073d60 5370
d7e2d343
XW		 5371static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5372{
477a0a38
XW		 5373 struct hns_roce_buf_attr buf_attr = {};
5374 int err;
a5073d60 5375
477a0a38
XW		 5376 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
5377 eq->hop_num = 0;
5378 else
5379 eq->hop_num = hr_dev->caps.eqe_hop_num;
a5073d60 5380
477a0a38
XW		 5381 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_ADDR_SHIFT;
5382 buf_attr.region[0].size = eq->entries * eq->eqe_size;
5383 buf_attr.region[0].hopnum = eq->hop_num;
5384 buf_attr.region_count = 1;
5385 buf_attr.fixed_page = true;
d7e2d343 5386
477a0a38
XW		 5387 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
5388 hr_dev->caps.srqwqe_ba_pg_sz +
5389 PAGE_ADDR_SHIFT, NULL, 0);
5390 if (err)
5391 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err);
a5073d60 5392
477a0a38 5393 return err;
a5073d60
YL		 5394}
5395
5396static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5397 struct hns_roce_eq *eq,
5398 unsigned int eq_cmd)
5399{
a5073d60 5400 struct hns_roce_cmd_mailbox *mailbox;
a5073d60
YL		 5401 int ret;
5402
5403 /* Allocate mailbox memory */
5404 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
477a0a38
XW		 5405 if (IS_ERR_OR_NULL(mailbox))
5406 return -ENOMEM;
a5073d60 5407
d7e2d343 5408 ret = alloc_eq_buf(hr_dev, eq);
477a0a38 5409 if (ret)
d7e2d343 5410 goto free_cmd_mbox;
477a0a38
XW		 5411
5412 ret = config_eqc(hr_dev, eq, mailbox->buf);
5413 if (ret)
5414 goto err_cmd_mbox;
a5073d60
YL		 5415
5416 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5417 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5418 if (ret) {
d7e2d343 5419 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5420 goto err_cmd_mbox;
5421 }
5422
5423 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5424
5425 return 0;
5426
5427err_cmd_mbox:
d7e2d343 5428 free_eq_buf(hr_dev, eq);
a5073d60
YL		 5429
5430free_cmd_mbox:
5431 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5432
5433 return ret;
5434}
5435
33db6f94
YL		 5436static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
5437 int comp_num, int aeq_num, int other_num)
5438{
5439 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5440 int i, j;
5441 int ret;
5442
5443 for (i = 0; i < irq_num; i++) {
5444 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5445 GFP_KERNEL);
5446 if (!hr_dev->irq_names[i]) {
5447 ret = -ENOMEM;
5448 goto err_kzalloc_failed;
5449 }
5450 }
5451
6def7de6 5452 /* irq contains: abnormal + AEQ + CEQ */
bebdb83f 5453 for (j = 0; j < other_num; j++)
60262b10
LO		 5454 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5455 "hns-abn-%d", j);
bebdb83f
LC		 5456
5457 for (j = other_num; j < (other_num + aeq_num); j++)
60262b10
LO		 5458 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5459 "hns-aeq-%d", j - other_num);
bebdb83f
LC		 5460
5461 for (j = (other_num + aeq_num); j < irq_num; j++)
60262b10
LO		 5462 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5463 "hns-ceq-%d", j - other_num - aeq_num);
33db6f94
YL		 5464
5465 for (j = 0; j < irq_num; j++) {
5466 if (j < other_num)
5467 ret = request_irq(hr_dev->irq[j],
5468 hns_roce_v2_msix_interrupt_abn,
5469 0, hr_dev->irq_names[j], hr_dev);
5470
5471 else if (j < (other_num + comp_num))
5472 ret = request_irq(eq_table->eq[j - other_num].irq,
5473 hns_roce_v2_msix_interrupt_eq,
5474 0, hr_dev->irq_names[j + aeq_num],
5475 &eq_table->eq[j - other_num]);
5476 else
5477 ret = request_irq(eq_table->eq[j - other_num].irq,
5478 hns_roce_v2_msix_interrupt_eq,
5479 0, hr_dev->irq_names[j - comp_num],
5480 &eq_table->eq[j - other_num]);
5481 if (ret) {
5482 dev_err(hr_dev->dev, "Request irq error!\n");
5483 goto err_request_failed;
5484 }
5485 }
5486
5487 return 0;
5488
5489err_request_failed:
5490 for (j -= 1; j >= 0; j--)
5491 if (j < other_num)
5492 free_irq(hr_dev->irq[j], hr_dev);
5493 else
5494 free_irq(eq_table->eq[j - other_num].irq,
5495 &eq_table->eq[j - other_num]);
5496
5497err_kzalloc_failed:
5498 for (i -= 1; i >= 0; i--)
5499 kfree(hr_dev->irq_names[i]);
5500
5501 return ret;
5502}
5503
5504static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
5505{
5506 int irq_num;
5507 int eq_num;
5508 int i;
5509
5510 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5511 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5512
5513 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5514 free_irq(hr_dev->irq[i], hr_dev);
5515
5516 for (i = 0; i < eq_num; i++)
5517 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
5518
5519 for (i = 0; i < irq_num; i++)
5520 kfree(hr_dev->irq_names[i]);
5521}
5522
a5073d60
YL		 5523static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5524{
5525 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5526 struct device *dev = hr_dev->dev;
5527 struct hns_roce_eq *eq;
5528 unsigned int eq_cmd;
5529 int irq_num;
5530 int eq_num;
5531 int other_num;
5532 int comp_num;
5533 int aeq_num;
33db6f94 5534 int i;
a5073d60
YL		 5535 int ret;
5536
5537 other_num = hr_dev->caps.num_other_vectors;
5538 comp_num = hr_dev->caps.num_comp_vectors;
5539 aeq_num = hr_dev->caps.num_aeq_vectors;
5540
5541 eq_num = comp_num + aeq_num;
5542 irq_num = eq_num + other_num;
5543
5544 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5545 if (!eq_table->eq)
5546 return -ENOMEM;
5547
a5073d60 5548 /* create eq */
33db6f94
YL		 5549 for (i = 0; i < eq_num; i++) {
5550 eq = &eq_table->eq[i];
a5073d60 5551 eq->hr_dev = hr_dev;
33db6f94
YL		 5552 eq->eqn = i;
5553 if (i < comp_num) {
a5073d60
YL		 5554 /* CEQ */
5555 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5556 eq->type_flag = HNS_ROCE_CEQ;
5557 eq->entries = hr_dev->caps.ceqe_depth;
5558 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
33db6f94 5559 eq->irq = hr_dev->irq[i + other_num + aeq_num];
a5073d60
YL		 5560 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5561 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5562 } else {
5563 /* AEQ */
5564 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5565 eq->type_flag = HNS_ROCE_AEQ;
5566 eq->entries = hr_dev->caps.aeqe_depth;
5567 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
33db6f94 5568 eq->irq = hr_dev->irq[i - comp_num + other_num];
a5073d60
YL		 5569 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5570 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5571 }
5572
5573 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5574 if (ret) {
5575 dev_err(dev, "eq create failed.\n");
5576 goto err_create_eq_fail;
5577 }
5578 }
5579
5580 /* enable irq */
5581 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5582
33db6f94
YL		 5583 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num,
5584 aeq_num, other_num);
5585 if (ret) {
5586 dev_err(dev, "Request irq failed.\n");
5587 goto err_request_irq_fail;
a5073d60
YL		 5588 }
5589
ffd541d4 5590 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
0425e3e6
YL		 5591 if (!hr_dev->irq_workq) {
5592 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5593 ret = -ENOMEM;
33db6f94 5594 goto err_create_wq_fail;
0425e3e6
YL		 5595 }
5596
a5073d60
YL		 5597 return 0;
5598
33db6f94
YL		 5599err_create_wq_fail:
5600 __hns_roce_free_irq(hr_dev);
5601
a5073d60 5602err_request_irq_fail:
33db6f94 5603 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
a5073d60
YL		 5604
5605err_create_eq_fail:
a5073d60 5606 for (i -= 1; i >= 0; i--)
d7e2d343 5607 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5608 kfree(eq_table->eq);
5609
5610 return ret;
5611}
5612
5613static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5614{
5615 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
a5073d60
YL		 5616 int eq_num;
5617 int i;
5618
5619 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
a5073d60
YL		 5620
5621 /* Disable irq */
5622 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5623
33db6f94 5624 __hns_roce_free_irq(hr_dev);
a5073d60
YL		 5625
5626 for (i = 0; i < eq_num; i++) {
5627 hns_roce_v2_destroy_eqc(hr_dev, i);
5628
d7e2d343 5629 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5630 }
5631
a5073d60 5632 kfree(eq_table->eq);
0425e3e6
YL		 5633
5634 flush_workqueue(hr_dev->irq_workq);
5635 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5636}
5637
c7bcb134
LO		 5638static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
5639 struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
5640 u32 cqn, void *mb_buf, u64 *mtts_wqe,
5641 u64 *mtts_idx, dma_addr_t dma_handle_wqe,
5642 dma_addr_t dma_handle_idx)
5643{
5644 struct hns_roce_srq_context *srq_context;
5645
5646 srq_context = mb_buf;
5647 memset(srq_context, 0, sizeof(*srq_context));
5648
5649 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M,
5650 SRQC_BYTE_4_SRQ_ST_S, 1);
5651
5652 roce_set_field(srq_context->byte_4_srqn_srqst,
5653 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M,
5654 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S,
5655 (hr_dev->caps.srqwqe_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5656 hr_dev->caps.srqwqe_hop_num));
5657 roce_set_field(srq_context->byte_4_srqn_srqst,
5658 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S,
d938d785 5659 ilog2(srq->wqe_cnt));
c7bcb134
LO		 5660
5661 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M,
5662 SRQC_BYTE_4_SRQN_S, srq->srqn);
5663
5664 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5665 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5666
5667 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
5668 SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
5669
5670 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));
5671
5672 roce_set_field(srq_context->byte_24_wqe_bt_ba,
5673 SRQC_BYTE_24_SRQ_WQE_BT_BA_M,
5674 SRQC_BYTE_24_SRQ_WQE_BT_BA_S,
bfe86035 5675 dma_handle_wqe >> 35);
c7bcb134
LO		 5676
5677 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
5678 SRQC_BYTE_28_PD_S, pdn);
5679 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
5680 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
5681 fls(srq->max_gs - 1));
5682
bfe86035 5683 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3);
c7bcb134
LO		 5684 roce_set_field(srq_context->rsv_idx_bt_ba,
5685 SRQC_BYTE_36_SRQ_IDX_BT_BA_M,
5686 SRQC_BYTE_36_SRQ_IDX_BT_BA_S,
bfe86035 5687 dma_handle_idx >> 35);
c7bcb134 5688
c7bcb134 5689 srq_context->idx_cur_blk_addr =
6fd610c5 5690 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0]));
c7bcb134
LO		 5691 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5692 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M,
5693 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S,
6fd610c5 5694 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
c7bcb134
LO		 5695 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5696 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M,
5697 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S,
5698 hr_dev->caps.idx_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5699 hr_dev->caps.idx_hop_num);
5700
6fd610c5
XW		 5701 roce_set_field(
5702 srq_context->byte_44_idxbufpgsz_addr,
5703 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
5704 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
5705 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift));
5706 roce_set_field(
5707 srq_context->byte_44_idxbufpgsz_addr,
5708 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
5709 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
5710 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift));
c7bcb134 5711
c7bcb134 5712 srq_context->idx_nxt_blk_addr =
6fd610c5 5713 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1]));
c7bcb134
LO		 5714 roce_set_field(srq_context->rsv_idxnxtblkaddr,
5715 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M,
5716 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S,
6fd610c5 5717 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
c7bcb134
LO		 5718 roce_set_field(srq_context->byte_56_xrc_cqn,
5719 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
5720 cqn);
5721 roce_set_field(srq_context->byte_56_xrc_cqn,
5722 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
5723 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
6fd610c5 5724 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
c7bcb134
LO		 5725 roce_set_field(srq_context->byte_56_xrc_cqn,
5726 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M,
5727 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S,
6fd610c5 5728 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
c7bcb134
LO		 5729
5730 roce_set_bit(srq_context->db_record_addr_record_en,
5731 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0);
5732}
5733
5734static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5735 struct ib_srq_attr *srq_attr,
5736 enum ib_srq_attr_mask srq_attr_mask,
5737 struct ib_udata *udata)
5738{
5739 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5740 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5741 struct hns_roce_srq_context *srq_context;
5742 struct hns_roce_srq_context *srqc_mask;
5743 struct hns_roce_cmd_mailbox *mailbox;
5744 int ret;
5745
5746 if (srq_attr_mask & IB_SRQ_LIMIT) {
d938d785 5747 if (srq_attr->srq_limit >= srq->wqe_cnt)
c7bcb134
LO		 5748 return -EINVAL;
5749
5750 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5751 if (IS_ERR(mailbox))
5752 return PTR_ERR(mailbox);
5753
5754 srq_context = mailbox->buf;
5755 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5756
5757 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5758
5759 roce_set_field(srq_context->byte_8_limit_wl,
5760 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5761 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit);
5762 roce_set_field(srqc_mask->byte_8_limit_wl,
5763 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5764 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5765
5766 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5767 HNS_ROCE_CMD_MODIFY_SRQC,
5768 HNS_ROCE_CMD_TIMEOUT_MSECS);
5769 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5770 if (ret) {
ae1c6148
LO		 5771 ibdev_err(&hr_dev->ib_dev,
5772 "failed to process cmd when modifying SRQ, ret = %d\n",
5773 ret);
c7bcb134
LO		 5774 return ret;
5775 }
5776 }
5777
5778 return 0;
5779}
5780
c3c668e7 5781static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
c7bcb134
LO		 5782{
5783 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5784 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5785 struct hns_roce_srq_context *srq_context;
5786 struct hns_roce_cmd_mailbox *mailbox;
5787 int limit_wl;
5788 int ret;
5789
5790 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5791 if (IS_ERR(mailbox))
5792 return PTR_ERR(mailbox);
5793
5794 srq_context = mailbox->buf;
5795 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5796 HNS_ROCE_CMD_QUERY_SRQC,
5797 HNS_ROCE_CMD_TIMEOUT_MSECS);
5798 if (ret) {
ae1c6148
LO		 5799 ibdev_err(&hr_dev->ib_dev,
5800 "failed to process cmd when querying SRQ, ret = %d\n",
5801 ret);
c7bcb134
LO		 5802 goto out;
5803 }
5804
5805 limit_wl = roce_get_field(srq_context->byte_8_limit_wl,
5806 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5807 SRQC_BYTE_8_SRQ_LIMIT_WL_S);
5808
5809 attr->srq_limit = limit_wl;
d938d785 5810 attr->max_wr = srq->wqe_cnt - 1;
c7bcb134
LO		 5811 attr->max_sge = srq->max_gs;
5812
5813 memcpy(srq_context, mailbox->buf, sizeof(*srq_context));
5814
5815out:
5816 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5817 return ret;
5818}
5819
97545b10
LO		 5820static int find_empty_entry(struct hns_roce_idx_que *idx_que,
5821 unsigned long size)
c7bcb134 5822{
97545b10 5823 int wqe_idx;
c7bcb134 5824
97545b10
LO		 5825 if (unlikely(bitmap_full(idx_que->bitmap, size)))
5826 return -ENOSPC;
5827
5828 wqe_idx = find_first_zero_bit(idx_que->bitmap, size);
5829
5830 bitmap_set(idx_que->bitmap, wqe_idx, 1);
c7bcb134 5831
97545b10 5832 return wqe_idx;
c7bcb134
LO		 5833}
5834
5835static void fill_idx_queue(struct hns_roce_idx_que *idx_que,
5836 int cur_idx, int wqe_idx)
5837{
5838 unsigned int *addr;
5839
6fd610c5 5840 addr = (unsigned int *)hns_roce_buf_offset(idx_que->mtr.kmem,
c7bcb134
LO		 5841 cur_idx * idx_que->entry_sz);
5842 *addr = wqe_idx;
5843}
5844
5845static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
5846 const struct ib_recv_wr *wr,
5847 const struct ib_recv_wr **bad_wr)
5848{
d3743fa9 5849 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
c7bcb134
LO		 5850 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5851 struct hns_roce_v2_wqe_data_seg *dseg;
5852 struct hns_roce_v2_db srq_db;
5853 unsigned long flags;
5854 int ret = 0;
5855 int wqe_idx;
5856 void *wqe;
5857 int nreq;
5858 int ind;
5859 int i;
5860
5861 spin_lock_irqsave(&srq->lock, flags);
5862
d938d785 5863 ind = srq->head & (srq->wqe_cnt - 1);
c7bcb134
LO		 5864
5865 for (nreq = 0; wr; ++nreq, wr = wr->next) {
5866 if (unlikely(wr->num_sge > srq->max_gs)) {
5867 ret = -EINVAL;
5868 *bad_wr = wr;
5869 break;
5870 }
5871
5872 if (unlikely(srq->head == srq->tail)) {
5873 ret = -ENOMEM;
5874 *bad_wr = wr;
5875 break;
5876 }
5877
d938d785 5878 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt);
97545b10
LO		 5879 if (wqe_idx < 0) {
5880 ret = -ENOMEM;
5881 *bad_wr = wr;
5882 break;
5883 }
5884
c7bcb134
LO		 5885 fill_idx_queue(&srq->idx_que, ind, wqe_idx);
5886 wqe = get_srq_wqe(srq, wqe_idx);
5887 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
5888
5889 for (i = 0; i < wr->num_sge; ++i) {
5890 dseg[i].len = cpu_to_le32(wr->sg_list[i].length);
5891 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey);
5892 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr);
5893 }
5894
5895 if (i < srq->max_gs) {
4f18904c
LO		 5896 dseg[i].len = 0;
5897 dseg[i].lkey = cpu_to_le32(0x100);
5898 dseg[i].addr = 0;
c7bcb134
LO		 5899 }
5900
5901 srq->wrid[wqe_idx] = wr->wr_id;
d938d785 5902 ind = (ind + 1) & (srq->wqe_cnt - 1);
c7bcb134
LO		 5903 }
5904
5905 if (likely(nreq)) {
5906 srq->head += nreq;
5907
5908 /*
5909 * Make sure that descriptors are written before
5910 * doorbell record.
5911 */
5912 wmb();
5913
bfe86035
LC		 5914 srq_db.byte_4 =
5915 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S |
5916 (srq->srqn & V2_DB_BYTE_4_TAG_M));
5917 srq_db.parameter = cpu_to_le32(srq->head);
c7bcb134 5918
d3743fa9 5919 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l);
c7bcb134
LO		 5920
5921 }
5922
5923 spin_unlock_irqrestore(&srq->lock, flags);
5924
5925 return ret;
5926}
5927
e1c9a0dc
LO		 5928static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = {
5929 .query_cqc_info = hns_roce_v2_query_cqc_info,
5930};
5931
7f645a58
KH		 5932static const struct ib_device_ops hns_roce_v2_dev_ops = {
5933 .destroy_qp = hns_roce_v2_destroy_qp,
5934 .modify_cq = hns_roce_v2_modify_cq,
5935 .poll_cq = hns_roce_v2_poll_cq,
5936 .post_recv = hns_roce_v2_post_recv,
5937 .post_send = hns_roce_v2_post_send,
5938 .query_qp = hns_roce_v2_query_qp,
5939 .req_notify_cq = hns_roce_v2_req_notify_cq,
5940};
5941
5942static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
5943 .modify_srq = hns_roce_v2_modify_srq,
5944 .post_srq_recv = hns_roce_v2_post_srq_recv,
5945 .query_srq = hns_roce_v2_query_srq,
5946};
5947
a04ff739
WHX		 5948static const struct hns_roce_hw hns_roce_hw_v2 = {
5949 .cmq_init = hns_roce_v2_cmq_init,
5950 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5951 .hw_profile = hns_roce_v2_profile,
6b63597d 5952 .hw_init = hns_roce_v2_init,
5953 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5954 .post_mbox = hns_roce_v2_post_mbox,
5955 .chk_mbox = hns_roce_v2_chk_mbox,
6a04aed6 5956 .rst_prc_mbox = hns_roce_v2_rst_process_cmd,
7afddafa
WHX		 5957 .set_gid = hns_roce_v2_set_gid,
5958 .set_mac = hns_roce_v2_set_mac,
3958cc56 5959 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5960 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 5961 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 5962 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 5963 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5964 .set_hem = hns_roce_v2_set_hem,
5965 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5966 .modify_qp = hns_roce_v2_modify_qp,
5967 .query_qp = hns_roce_v2_query_qp,
5968 .destroy_qp = hns_roce_v2_destroy_qp,
aa84fa18 5969 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
b156269d 5970 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5971 .post_send = hns_roce_v2_post_send,
5972 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5973 .req_notify_cq = hns_roce_v2_req_notify_cq,
5974 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5975 .init_eq = hns_roce_v2_init_eq_table,
5976 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
c7bcb134
LO		 5977 .write_srqc = hns_roce_v2_write_srqc,
5978 .modify_srq = hns_roce_v2_modify_srq,
5979 .query_srq = hns_roce_v2_query_srq,
5980 .post_srq_recv = hns_roce_v2_post_srq_recv,
7f645a58
KH		 5981 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
5982 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
a04ff739 5983};
dd74282d
WHX		 5984
5985static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5986 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5987 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 5988 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
5989 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 5990 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
5991 /* required last entry */
5992 {0, }
5993};
5994
f97a62c3 5995MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
5996
301cc7eb 5997static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
dd74282d
WHX		 5998 struct hnae3_handle *handle)
5999{
d061effc 6000 struct hns_roce_v2_priv *priv = hr_dev->priv;
a5073d60 6001 int i;
dd74282d 6002
301cc7eb
LC		 6003 hr_dev->pci_dev = handle->pdev;
6004 hr_dev->dev = &handle->pdev->dev;
dd74282d 6005 hr_dev->hw = &hns_roce_hw_v2;
e1c9a0dc 6006 hr_dev->dfx = &hns_roce_dfx_hw_v2;
2d407888
WHX		 6007 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6008 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 6009
6010 /* Get info from NIC driver. */
6011 hr_dev->reg_base = handle->rinfo.roce_io_base;
6012 hr_dev->caps.num_ports = 1;
6013 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6014 hr_dev->iboe.phy_port[0] = 0;
6015
d4994d2f 6016 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6017 hr_dev->iboe.netdevs[0]->dev_addr);
6018
a5073d60
YL		 6019 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
6020 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6021 i + handle->rinfo.base_vector);
6022
dd74282d 6023 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 6024 hr_dev->cmd_mod = 1;
dd74282d
WHX		 6025 hr_dev->loop_idc = 0;
6026
d061effc
WHX		 6027 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6028 priv->handle = handle;
dd74282d
WHX		 6029}
6030
d061effc 6031static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
dd74282d
WHX		 6032{
6033 struct hns_roce_dev *hr_dev;
6034 int ret;
6035
459cc69f 6036 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
dd74282d
WHX		 6037 if (!hr_dev)
6038 return -ENOMEM;
6039
a04ff739
WHX		 6040 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6041 if (!hr_dev->priv) {
6042 ret = -ENOMEM;
6043 goto error_failed_kzalloc;
6044 }
6045
301cc7eb 6046 hns_roce_hw_v2_get_cfg(hr_dev, handle);
dd74282d
WHX		 6047
6048 ret = hns_roce_init(hr_dev);
6049 if (ret) {
6050 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6051 goto error_failed_get_cfg;
6052 }
6053
d061effc
WHX		 6054 handle->priv = hr_dev;
6055
dd74282d
WHX		 6056 return 0;
6057
6058error_failed_get_cfg:
a04ff739
WHX		 6059 kfree(hr_dev->priv);
6060
6061error_failed_kzalloc:
dd74282d
WHX		 6062 ib_dealloc_device(&hr_dev->ib_dev);
6063
6064 return ret;
6065}
6066
d061effc 6067static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
dd74282d
WHX		 6068 bool reset)
6069{
6070 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
6071
cb7a94c9
WHX		 6072 if (!hr_dev)
6073 return;
6074
d061effc 6075 handle->priv = NULL;
626903e9
XW		 6076
6077 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6078 hns_roce_handle_device_err(hr_dev);
6079
dd74282d 6080 hns_roce_exit(hr_dev);
a04ff739 6081 kfree(hr_dev->priv);
dd74282d
WHX		 6082 ib_dealloc_device(&hr_dev->ib_dev);
6083}
6084
d061effc
WHX		 6085static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6086{
6087 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
07c2339a 6088 const struct pci_device_id *id;
d061effc
WHX		 6089 struct device *dev = &handle->pdev->dev;
6090 int ret;
6091
6092 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6093
6094 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6095 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6096 goto reset_chk_err;
6097 }
6098
07c2339a
LO		 6099 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6100 if (!id)
6101 return 0;
6102
d061effc
WHX		 6103 ret = __hns_roce_hw_v2_init_instance(handle);
6104 if (ret) {
6105 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6106 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6107 if (ops->ae_dev_resetting(handle) ||
6108 ops->get_hw_reset_stat(handle))
6109 goto reset_chk_err;
6110 else
6111 return ret;
6112 }
6113
6114 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6115
6116
6117 return 0;
6118
6119reset_chk_err:
6120 dev_err(dev, "Device is busy in resetting state.\n"
6121 "please retry later.\n");
6122
6123 return -EBUSY;
6124}
6125
6126static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6127 bool reset)
6128{
6129 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6130 return;
6131
6132 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6133
6134 __hns_roce_hw_v2_uninit_instance(handle, reset);
6135
6136 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6137}
cb7a94c9
WHX		 6138static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6139{
d061effc 6140 struct hns_roce_dev *hr_dev;
cb7a94c9 6141
d061effc
WHX		 6142 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6143 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6144 return 0;
cb7a94c9
WHX		 6145 }
6146
d061effc
WHX		 6147 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6148 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6149
6150 hr_dev = (struct hns_roce_dev *)handle->priv;
6151 if (!hr_dev)
6152 return 0;
6153
726be12f 6154 hr_dev->is_reset = true;
cb7a94c9 6155 hr_dev->active = false;
d3743fa9 6156 hr_dev->dis_db = true;
cb7a94c9 6157
626903e9 6158 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
cb7a94c9
WHX		 6159
6160 return 0;
6161}
6162
6163static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6164{
d061effc 6165 struct device *dev = &handle->pdev->dev;
cb7a94c9
WHX		 6166 int ret;
6167
d061effc
WHX		 6168 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6169 &handle->rinfo.state)) {
6170 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6171 return 0;
6172 }
6173
6174 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6175
6176 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6177 ret = __hns_roce_hw_v2_init_instance(handle);
cb7a94c9
WHX		 6178 if (ret) {
6179 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6180 * callback function, RoCE Engine reinitialize. If RoCE reinit
6181 * failed, we should inform NIC driver.
6182 */
6183 handle->priv = NULL;
d061effc
WHX		 6184 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6185 } else {
6186 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6187 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
cb7a94c9
WHX		 6188 }
6189
6190 return ret;
6191}
6192
6193static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6194{
d061effc
WHX		 6195 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6196 return 0;
6197
6198 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6199 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
90c559b1 6200 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
d061effc
WHX		 6201 __hns_roce_hw_v2_uninit_instance(handle, false);
6202
cb7a94c9
WHX		 6203 return 0;
6204}
6205
6206static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6207 enum hnae3_reset_notify_type type)
6208{
6209 int ret = 0;
6210
6211 switch (type) {
6212 case HNAE3_DOWN_CLIENT:
6213 ret = hns_roce_hw_v2_reset_notify_down(handle);
6214 break;
6215 case HNAE3_INIT_CLIENT:
6216 ret = hns_roce_hw_v2_reset_notify_init(handle);
6217 break;
6218 case HNAE3_UNINIT_CLIENT:
6219 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6220 break;
6221 default:
6222 break;
6223 }
6224
6225 return ret;
6226}
6227
dd74282d
WHX		 6228static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6229 .init_instance = hns_roce_hw_v2_init_instance,
6230 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 6231 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 6232};
6233
6234static struct hnae3_client hns_roce_hw_v2_client = {
6235 .name = "hns_roce_hw_v2",
6236 .type = HNAE3_CLIENT_ROCE,
6237 .ops = &hns_roce_hw_v2_ops,
6238};
6239
6240static int __init hns_roce_hw_v2_init(void)
6241{
6242 return hnae3_register_client(&hns_roce_hw_v2_client);
6243}
6244
6245static void __exit hns_roce_hw_v2_exit(void)
6246{
6247 hnae3_unregister_client(&hns_roce_hw_v2_client);
6248}
6249
6250module_init(hns_roce_hw_v2_init);
6251module_exit(hns_roce_hw_v2_exit);
6252
6253MODULE_LICENSE("Dual BSD/GPL");
6254MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6255MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6256MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6257MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)