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RDMA/hns: Add support for QPC in size of 512 Bytes
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
a70c0739 40#include <rdma/ib_cache.h>
dd74282d 41#include <rdma/ib_umem.h>
bdeacabd 42#include <rdma/uverbs_ioctl.h>
dd74282d
WHX		 43
44#include "hnae3.h"
45#include "hns_roce_common.h"
46#include "hns_roce_device.h"
47#include "hns_roce_cmd.h"
48#include "hns_roce_hem.h"
a04ff739 49#include "hns_roce_hw_v2.h"
dd74282d 50
2d407888
WHX		 51static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
52 struct ib_sge *sg)
53{
54 dseg->lkey = cpu_to_le32(sg->lkey);
55 dseg->addr = cpu_to_le64(sg->addr);
56 dseg->len = cpu_to_le32(sg->length);
57}
58
e363f7de
XW		 59/*
60 * mapped-value = 1 + real-value
61 * The hns wr opcode real value is start from 0, In order to distinguish between
62 * initialized and uninitialized map values, we plus 1 to the actual value when
63 * defining the mapping, so that the validity can be identified by checking the
64 * mapped value is greater than 0.
65 */
66#define HR_OPC_MAP(ib_key, hr_key) \
67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
68
69static const u32 hns_roce_op_code[] = {
70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
72 HR_OPC_MAP(SEND, SEND),
73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
74 HR_OPC_MAP(RDMA_READ, RDMA_READ),
75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV),
79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
81 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
82};
83
84static u32 to_hr_opcode(u32 ib_opcode)
85{
86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
87 return HNS_ROCE_V2_WQE_OP_MASK;
88
89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
90 HNS_ROCE_V2_WQE_OP_MASK;
91}
92
68a997c5 93static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
eaaa98de 94 const struct ib_reg_wr *wr)
68a997c5 95{
eaaa98de
WL		 96 struct hns_roce_wqe_frmr_seg *fseg =
97 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
68a997c5 98 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
9b2cf76c 99 u64 pbl_ba;
68a997c5
YL		 100
101 /* use ib_access_flags */
60262b10 102 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
68a997c5 103 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
60262b10 104 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
68a997c5 105 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
60262b10 106 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S,
68a997c5 107 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
60262b10 108 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S,
68a997c5 109 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
60262b10 110 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S,
68a997c5
YL		 111 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
112
113 /* Data structure reuse may lead to confusion */
9b2cf76c
XW		 114 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
115 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
116 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
68a997c5
YL		 117
118 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
119 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
120 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
121 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
122
9b2cf76c 123 fseg->pbl_size = cpu_to_le32(mr->npages);
68a997c5
YL		 124 roce_set_field(fseg->mode_buf_pg_sz,
125 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
126 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
9b2cf76c 127 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
68a997c5
YL		 128 roce_set_bit(fseg->mode_buf_pg_sz,
129 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
130}
131
eaaa98de 132static void set_atomic_seg(const struct ib_send_wr *wr,
00a59d30 133 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
13aa13dd 134 unsigned int valid_num_sge)
384f8818 135{
eaaa98de
WL		 136 struct hns_roce_v2_wqe_data_seg *dseg =
137 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
138 struct hns_roce_wqe_atomic_seg *aseg =
139 (void *)dseg + sizeof(struct hns_roce_v2_wqe_data_seg);
00a59d30 140
eaaa98de 141 set_data_seg_v2(dseg, wr->sg_list);
00a59d30
XW		 142
143 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
144 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
145 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
384f8818 146 } else {
00a59d30
XW		 147 aseg->fetchadd_swap_data =
148 cpu_to_le64(atomic_wr(wr)->compare_add);
eaaa98de 149 aseg->cmp_data = 0;
384f8818 150 }
00a59d30
XW		 151
152 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
153 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
384f8818
LO		 154}
155
f696bf6d 156static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
13aa13dd 157 unsigned int *sge_ind, unsigned int valid_num_sge)
0b25c9cc
WHX		 158{
159 struct hns_roce_v2_wqe_data_seg *dseg;
13aa13dd 160 unsigned int cnt = valid_num_sge;
54d66387
XW		 161 struct ib_sge *sge = wr->sg_list;
162 unsigned int idx = *sge_ind;
0b25c9cc 163
54d66387
XW		 164 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
165 cnt -= HNS_ROCE_SGE_IN_WQE;
166 sge += HNS_ROCE_SGE_IN_WQE;
167 }
0b25c9cc 168
54d66387
XW		 169 while (cnt > 0) {
170 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
171 set_data_seg_v2(dseg, sge);
172 idx++;
173 sge++;
174 cnt--;
0b25c9cc 175 }
54d66387
XW		 176
177 *sge_ind = idx;
0b25c9cc
WHX		 178}
179
f696bf6d 180static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 181 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
eaaa98de 182 unsigned int *sge_ind,
13aa13dd 183 unsigned int valid_num_sge)
7bdee415 184{
185 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
eaaa98de
WL		 186 struct hns_roce_v2_wqe_data_seg *dseg =
187 (void *)rc_sq_wqe + sizeof(struct hns_roce_v2_rc_send_wqe);
00a59d30 188 struct ib_device *ibdev = &hr_dev->ib_dev;
7bdee415 189 struct hns_roce_qp *qp = to_hr_qp(ibqp);
eaaa98de 190 void *wqe = dseg;
468d020e 191 int j = 0;
7bdee415 192 int i;
193
468d020e 194 if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) {
0db65709
LC		 195 if (unlikely(le32_to_cpu(rc_sq_wqe->msg_len) >
196 hr_dev->caps.max_sq_inline)) {
00a59d30
XW		 197 ibdev_err(ibdev, "inline len(1-%d)=%d, illegal",
198 rc_sq_wqe->msg_len,
199 hr_dev->caps.max_sq_inline);
7bdee415 200 return -EINVAL;
201 }
202
0db65709 203 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
00a59d30 204 ibdev_err(ibdev, "Not support inline data!\n");
328d405b 205 return -EINVAL;
206 }
207
7bdee415 208 for (i = 0; i < wr->num_sge; i++) {
209 memcpy(wqe, ((void *)wr->sg_list[i].addr),
210 wr->sg_list[i].length);
211 wqe += wr->sg_list[i].length;
212 }
213
214 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
215 1);
216 } else {
54d66387 217 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
7bdee415 218 for (i = 0; i < wr->num_sge; i++) {
219 if (likely(wr->sg_list[i].length)) {
220 set_data_seg_v2(dseg, wr->sg_list + i);
221 dseg++;
222 }
223 }
224 } else {
225 roce_set_field(rc_sq_wqe->byte_20,
226 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
227 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
228 (*sge_ind) & (qp->sge.sge_cnt - 1));
229
54d66387
XW		 230 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE;
231 i++) {
7bdee415 232 if (likely(wr->sg_list[i].length)) {
233 set_data_seg_v2(dseg, wr->sg_list + i);
234 dseg++;
468d020e 235 j++;
7bdee415 236 }
237 }
238
468d020e 239 set_extend_sge(qp, wr, sge_ind, valid_num_sge);
7bdee415 240 }
241
242 roce_set_field(rc_sq_wqe->byte_16,
243 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
468d020e 244 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
7bdee415 245 }
246
247 return 0;
248}
249
626903e9
XW		 250static int check_send_valid(struct hns_roce_dev *hr_dev,
251 struct hns_roce_qp *hr_qp)
252{
ae1c6148 253 struct ib_device *ibdev = &hr_dev->ib_dev;
626903e9 254 struct ib_qp *ibqp = &hr_qp->ibqp;
626903e9
XW		 255
256 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
257 ibqp->qp_type != IB_QPT_GSI &&
258 ibqp->qp_type != IB_QPT_UD)) {
ae1c6148
LO		 259 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n",
260 ibqp->qp_type);
626903e9
XW		 261 return -EOPNOTSUPP;
262 } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
263 hr_qp->state == IB_QPS_INIT ||
264 hr_qp->state == IB_QPS_RTR)) {
ae1c6148
LO		 265 ibdev_err(ibdev, "failed to post WQE, QP state %d!\n",
266 hr_qp->state);
626903e9
XW		 267 return -EINVAL;
268 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
ae1c6148
LO		 269 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
270 hr_dev->state);
626903e9
XW		 271 return -EIO;
272 }
273
274 return 0;
275}
276
13aa13dd
WL		 277static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
278 unsigned int *sge_len)
d6a3627e 279{
13aa13dd
WL		 280 unsigned int valid_num = 0;
281 unsigned int len = 0;
d6a3627e
XW		 282 int i;
283
284 for (i = 0; i < wr->num_sge; i++) {
285 if (likely(wr->sg_list[i].length)) {
286 len += wr->sg_list[i].length;
287 valid_num++;
288 }
289 }
290
291 *sge_len = len;
292 return valid_num;
293}
294
295static inline int set_ud_wqe(struct hns_roce_qp *qp,
296 const struct ib_send_wr *wr,
297 void *wqe, unsigned int *sge_idx,
298 unsigned int owner_bit)
299{
300 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
301 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
302 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
303 unsigned int curr_idx = *sge_idx;
304 int valid_num_sge;
305 u32 msg_len = 0;
306 bool loopback;
307 u8 *smac;
308
309 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
310 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
311
312 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
313 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
314 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
315 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
316 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
317 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
318 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
319 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
320 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
321 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]);
322 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
323 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]);
324
325 /* MAC loopback */
326 smac = (u8 *)hr_dev->dev_addr[qp->port];
327 loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0;
328
329 roce_set_bit(ud_sq_wqe->byte_40,
330 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
331
332 roce_set_field(ud_sq_wqe->byte_4,
333 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
334 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
335 HNS_ROCE_V2_WQE_OP_SEND);
336
337 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
338
339 switch (wr->opcode) {
340 case IB_WR_SEND_WITH_IMM:
341 case IB_WR_RDMA_WRITE_WITH_IMM:
342 ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
343 break;
344 default:
345 ud_sq_wqe->immtdata = 0;
346 break;
347 }
348
349 /* Set sig attr */
350 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S,
351 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
352
353 /* Set se attr */
354 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S,
355 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
356
357 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S,
358 owner_bit);
359
360 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M,
361 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn);
362
363 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
364 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
365
366 roce_set_field(ud_sq_wqe->byte_20,
367 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
368 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
369 curr_idx & (qp->sge.sge_cnt - 1));
370
371 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
074bf2c2 372 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, ah->av.udp_sport);
d6a3627e
XW		 373 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
374 qp->qkey : ud_wr(wr)->remote_qkey);
375 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M,
376 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn);
377
378 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M,
379 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id);
380 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
381 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit);
382 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
383 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass);
384 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
385 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel);
386 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M,
387 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl);
388 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M,
389 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port);
390
391 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
392 ah->av.vlan_en ? 1 : 0);
393 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
394 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index);
395
396 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2);
397
398 set_extend_sge(qp, wr, &curr_idx, valid_num_sge);
399
400 *sge_idx = curr_idx;
401
402 return 0;
403}
404
405static inline int set_rc_wqe(struct hns_roce_qp *qp,
406 const struct ib_send_wr *wr,
407 void *wqe, unsigned int *sge_idx,
408 unsigned int owner_bit)
409{
410 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
411 unsigned int curr_idx = *sge_idx;
13aa13dd 412 unsigned int valid_num_sge;
d6a3627e
XW		 413 u32 msg_len = 0;
414 int ret = 0;
415
416 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
417 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
418
419 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
420
421 switch (wr->opcode) {
422 case IB_WR_SEND_WITH_IMM:
423 case IB_WR_RDMA_WRITE_WITH_IMM:
424 rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
425 break;
426 case IB_WR_SEND_WITH_INV:
427 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
428 break;
429 default:
430 rc_sq_wqe->immtdata = 0;
431 break;
432 }
433
434 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
435 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
436
437 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
438 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
439
440 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
441 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
442
443 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
444 owner_bit);
445
d6a3627e
XW		 446 switch (wr->opcode) {
447 case IB_WR_RDMA_READ:
448 case IB_WR_RDMA_WRITE:
449 case IB_WR_RDMA_WRITE_WITH_IMM:
450 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
451 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
452 break;
453 case IB_WR_LOCAL_INV:
454 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
455 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
456 break;
457 case IB_WR_REG_MR:
eaaa98de 458 set_frmr_seg(rc_sq_wqe, reg_wr(wr));
d6a3627e
XW		 459 break;
460 case IB_WR_ATOMIC_CMP_AND_SWP:
461 case IB_WR_ATOMIC_FETCH_AND_ADD:
462 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
463 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
464 break;
465 default:
466 break;
467 }
468
469 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
470 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
471 to_hr_opcode(wr->opcode));
472
473 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
474 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
eaaa98de 475 set_atomic_seg(wr, rc_sq_wqe, valid_num_sge);
d6a3627e
XW		 476 else if (wr->opcode != IB_WR_REG_MR)
477 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
eaaa98de 478 &curr_idx, valid_num_sge);
d6a3627e
XW		 479
480 *sge_idx = curr_idx;
481
482 return ret;
483}
484
75c994e6
YL		 485static inline void update_sq_db(struct hns_roce_dev *hr_dev,
486 struct hns_roce_qp *qp)
487{
488 /*
489 * Hip08 hardware cannot flush the WQEs in SQ if the QP state
490 * gets into errored mode. Hence, as a workaround to this
491 * hardware limitation, driver needs to assist in flushing. But
492 * the flushing operation uses mailbox to convey the QP state to
493 * the hardware and which can sleep due to the mutex protection
494 * around the mailbox calls. Hence, use the deferred flush for
495 * now.
496 */
497 if (qp->state == IB_QPS_ERR) {
498 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
499 init_flush_work(hr_dev, qp);
500 } else {
501 struct hns_roce_v2_db sq_db = {};
502
503 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
504 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
505 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
506 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
507 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
25966e89 508 V2_DB_PARAMETER_IDX_S, qp->sq.head);
75c994e6
YL		 509 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
510 V2_DB_PARAMETER_SL_S, qp->sl);
511
512 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l);
513 }
514}
515
d34ac5cd
BVA		 516static int hns_roce_v2_post_send(struct ib_qp *ibqp,
517 const struct ib_send_wr *wr,
518 const struct ib_send_wr **bad_wr)
2d407888
WHX		 519{
520 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
d6a3627e 521 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 522 struct hns_roce_qp *qp = to_hr_qp(ibqp);
d6a3627e 523 unsigned long flags = 0;
e8d18533 524 unsigned int owner_bit;
47688202
YL		 525 unsigned int sge_idx;
526 unsigned int wqe_idx;
2d407888 527 void *wqe = NULL;
2d407888 528 int nreq;
626903e9 529 int ret;
2d407888 530
626903e9 531 spin_lock_irqsave(&qp->sq.lock, flags);
2d407888 532
626903e9 533 ret = check_send_valid(hr_dev, qp);
0db65709 534 if (unlikely(ret)) {
2d407888 535 *bad_wr = wr;
626903e9
XW		 536 nreq = 0;
537 goto out;
2d407888
WHX		 538 }
539
47688202 540 sge_idx = qp->next_sge;
2d407888
WHX		 541
542 for (nreq = 0; wr; ++nreq, wr = wr->next) {
543 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
544 ret = -ENOMEM;
545 *bad_wr = wr;
546 goto out;
547 }
548
47688202
YL		 549 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
550
2d407888 551 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
d6a3627e
XW		 552 ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n",
553 wr->num_sge, qp->sq.max_gs);
2d407888
WHX		 554 ret = -EINVAL;
555 *bad_wr = wr;
556 goto out;
557 }
558
6c6e3921 559 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
47688202 560 qp->sq.wrid[wqe_idx] = wr->wr_id;
634f6390 561 owner_bit =
562 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
468d020e 563
7bdee415 564 /* Corresponding to the QP type, wqe process separately */
d6a3627e
XW		 565 if (ibqp->qp_type == IB_QPT_GSI)
566 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
567 else if (ibqp->qp_type == IB_QPT_RC)
568 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
d6a3627e 569
0db65709 570 if (unlikely(ret)) {
d6a3627e
XW		 571 *bad_wr = wr;
572 goto out;
573 }
2d407888
WHX		 574 }
575
576out:
577 if (likely(nreq)) {
578 qp->sq.head += nreq;
75c994e6 579 qp->next_sge = sge_idx;
2d407888
WHX		 580 /* Memory barrier */
581 wmb();
75c994e6 582 update_sq_db(hr_dev, qp);
2d407888
WHX		 583 }
584
585 spin_unlock_irqrestore(&qp->sq.lock, flags);
586
587 return ret;
588}
589
626903e9
XW		 590static int check_recv_valid(struct hns_roce_dev *hr_dev,
591 struct hns_roce_qp *hr_qp)
592{
593 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
594 return -EIO;
595 else if (hr_qp->state == IB_QPS_RESET)
596 return -EINVAL;
597
598 return 0;
599}
600
d34ac5cd
BVA		 601static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
602 const struct ib_recv_wr *wr,
603 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 604{
605 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
606 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 607 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 608 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 609 struct hns_roce_rinl_sge *sge_list;
2d407888
WHX		 610 unsigned long flags;
611 void *wqe = NULL;
47688202 612 u32 wqe_idx;
2d407888 613 int nreq;
626903e9 614 int ret;
2d407888
WHX		 615 int i;
616
617 spin_lock_irqsave(&hr_qp->rq.lock, flags);
2d407888 618
626903e9 619 ret = check_recv_valid(hr_dev, hr_qp);
0db65709 620 if (unlikely(ret)) {
2d407888 621 *bad_wr = wr;
626903e9
XW		 622 nreq = 0;
623 goto out;
2d407888
WHX		 624 }
625
626 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0db65709
LC		 627 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
628 hr_qp->ibqp.recv_cq))) {
2d407888
WHX		 629 ret = -ENOMEM;
630 *bad_wr = wr;
631 goto out;
632 }
633
47688202
YL		 634 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
635
6da06c62 636 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
ae1c6148
LO		 637 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n",
638 wr->num_sge, hr_qp->rq.max_gs);
2d407888
WHX		 639 ret = -EINVAL;
640 *bad_wr = wr;
641 goto out;
642 }
643
6c6e3921 644 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
2d407888
WHX		 645 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
646 for (i = 0; i < wr->num_sge; i++) {
647 if (!wr->sg_list[i].length)
648 continue;
649 set_data_seg_v2(dseg, wr->sg_list + i);
650 dseg++;
651 }
652
e1b43f07 653 if (wr->num_sge < hr_qp->rq.max_gs) {
778cc5a8 654 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
655 dseg->addr = 0;
2d407888
WHX		 656 }
657
0009c2db 658 /* rq support inline data */
54d66387 659 if (hr_qp->rq_inl_buf.wqe_cnt) {
47688202
YL		 660 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
661 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt =
ecaaf1e2 662 (u32)wr->num_sge;
663 for (i = 0; i < wr->num_sge; i++) {
664 sge_list[i].addr =
665 (void *)(u64)wr->sg_list[i].addr;
666 sge_list[i].len = wr->sg_list[i].length;
667 }
0009c2db 668 }
669
47688202 670 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
2d407888
WHX		 671 }
672
673out:
674 if (likely(nreq)) {
675 hr_qp->rq.head += nreq;
676 /* Memory barrier */
677 wmb();
678
b5374286
YL		 679 /*
680 * Hip08 hardware cannot flush the WQEs in RQ if the QP state
681 * gets into errored mode. Hence, as a workaround to this
682 * hardware limitation, driver needs to assist in flushing. But
683 * the flushing operation uses mailbox to convey the QP state to
684 * the hardware and which can sleep due to the mutex protection
685 * around the mailbox calls. Hence, use the deferred flush for
686 * now.
687 */
75c994e6 688 if (hr_qp->state == IB_QPS_ERR) {
b5374286
YL		 689 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG,
690 &hr_qp->flush_flag))
691 init_flush_work(hr_dev, hr_qp);
75c994e6
YL		 692 } else {
693 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
694 }
2d407888
WHX		 695 }
696 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
697
698 return ret;
699}
700
ffb1308b
YL		 701static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
702{
703 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
704}
705
67954a6e
XW		 706static void *get_idx_buf(struct hns_roce_idx_que *idx_que, int n)
707{
708 return hns_roce_buf_offset(idx_que->mtr.kmem,
709 n << idx_que->entry_shift);
710}
711
ffb1308b
YL		 712static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index)
713{
714 /* always called with interrupts disabled. */
715 spin_lock(&srq->lock);
716
717 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
718 srq->tail++;
719
720 spin_unlock(&srq->lock);
721}
722
723static int find_empty_entry(struct hns_roce_idx_que *idx_que,
724 unsigned long size)
725{
726 int wqe_idx;
727
728 if (unlikely(bitmap_full(idx_que->bitmap, size)))
729 return -ENOSPC;
730
731 wqe_idx = find_first_zero_bit(idx_que->bitmap, size);
732
733 bitmap_set(idx_que->bitmap, wqe_idx, 1);
734
735 return wqe_idx;
736}
737
ffb1308b
YL		 738static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
739 const struct ib_recv_wr *wr,
740 const struct ib_recv_wr **bad_wr)
741{
742 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
743 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
744 struct hns_roce_v2_wqe_data_seg *dseg;
745 struct hns_roce_v2_db srq_db;
746 unsigned long flags;
67954a6e 747 __le32 *srq_idx;
ffb1308b
YL		 748 int ret = 0;
749 int wqe_idx;
750 void *wqe;
751 int nreq;
752 int ind;
753 int i;
754
755 spin_lock_irqsave(&srq->lock, flags);
756
757 ind = srq->head & (srq->wqe_cnt - 1);
758
759 for (nreq = 0; wr; ++nreq, wr = wr->next) {
760 if (unlikely(wr->num_sge >= srq->max_gs)) {
761 ret = -EINVAL;
762 *bad_wr = wr;
763 break;
764 }
765
766 if (unlikely(srq->head == srq->tail)) {
767 ret = -ENOMEM;
768 *bad_wr = wr;
769 break;
770 }
771
772 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt);
0db65709 773 if (unlikely(wqe_idx < 0)) {
ffb1308b
YL		 774 ret = -ENOMEM;
775 *bad_wr = wr;
776 break;
777 }
778
ffb1308b
YL		 779 wqe = get_srq_wqe(srq, wqe_idx);
780 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
781
782 for (i = 0; i < wr->num_sge; ++i) {
783 dseg[i].len = cpu_to_le32(wr->sg_list[i].length);
784 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey);
785 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr);
786 }
787
e1b43f07 788 if (wr->num_sge < srq->max_gs) {
6da06c62
WL		 789 dseg[i].len = 0;
790 dseg[i].lkey = cpu_to_le32(0x100);
ffb1308b
YL		 791 dseg[i].addr = 0;
792 }
793
67954a6e
XW		 794 srq_idx = get_idx_buf(&srq->idx_que, ind);
795 *srq_idx = cpu_to_le32(wqe_idx);
796
ffb1308b
YL		 797 srq->wrid[wqe_idx] = wr->wr_id;
798 ind = (ind + 1) & (srq->wqe_cnt - 1);
799 }
800
801 if (likely(nreq)) {
802 srq->head += nreq;
803
804 /*
805 * Make sure that descriptors are written before
806 * doorbell record.
807 */
808 wmb();
809
810 srq_db.byte_4 =
811 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S |
812 (srq->srqn & V2_DB_BYTE_4_TAG_M));
25966e89
LC		 813 srq_db.parameter =
814 cpu_to_le32(srq->head & V2_DB_PARAMETER_IDX_M);
ffb1308b
YL		 815
816 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l);
817 }
818
819 spin_unlock_irqrestore(&srq->lock, flags);
820
821 return ret;
822}
823
6a04aed6
WHX		 824static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
825 unsigned long instance_stage,
826 unsigned long reset_stage)
827{
828 /* When hardware reset has been completed once or more, we should stop
d3743fa9 829 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
6a04aed6
WHX		 830 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
831 * stage of soft reset process, we should exit with error, and then
832 * HNAE3_INIT_CLIENT related process can rollback the operation like
833 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
834 * process will exit with error to notify NIC driver to reschedule soft
835 * reset process once again.
836 */
837 hr_dev->is_reset = true;
d3743fa9 838 hr_dev->dis_db = true;
6a04aed6
WHX		 839
840 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
841 instance_stage == HNS_ROCE_STATE_INIT)
842 return CMD_RST_PRC_EBUSY;
843
844 return CMD_RST_PRC_SUCCESS;
845}
846
847static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
848 unsigned long instance_stage,
849 unsigned long reset_stage)
850{
14ba8730 851 struct hns_roce_v2_priv *priv = hr_dev->priv;
6a04aed6
WHX		 852 struct hnae3_handle *handle = priv->handle;
853 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
854
d3743fa9
WHX		 855 /* When hardware reset is detected, we should stop sending mailbox&cmq&
856 * doorbell to hardware. If now in .init_instance() function, we should
6a04aed6
WHX		 857 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
858 * process, we should exit with error, and then HNAE3_INIT_CLIENT
859 * related process can rollback the operation like notifing hardware to
860 * free resources, HNAE3_INIT_CLIENT related process will exit with
861 * error to notify NIC driver to reschedule soft reset process once
862 * again.
863 */
d3743fa9 864 hr_dev->dis_db = true;
6a04aed6
WHX		 865 if (!ops->get_hw_reset_stat(handle))
866 hr_dev->is_reset = true;
867
868 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
869 instance_stage == HNS_ROCE_STATE_INIT)
870 return CMD_RST_PRC_EBUSY;
871
872 return CMD_RST_PRC_SUCCESS;
873}
874
875static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
876{
14ba8730 877 struct hns_roce_v2_priv *priv = hr_dev->priv;
6a04aed6
WHX		 878 struct hnae3_handle *handle = priv->handle;
879 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
880
881 /* When software reset is detected at .init_instance() function, we
d3743fa9
WHX		 882 * should stop sending mailbox&cmq&doorbell to hardware, and exit
883 * with error.
6a04aed6 884 */
d3743fa9 885 hr_dev->dis_db = true;
6a04aed6
WHX		 886 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
887 hr_dev->is_reset = true;
888
889 return CMD_RST_PRC_EBUSY;
890}
891
892static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
893{
14ba8730 894 struct hns_roce_v2_priv *priv = hr_dev->priv;
6a04aed6
WHX		 895 struct hnae3_handle *handle = priv->handle;
896 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
897 unsigned long instance_stage; /* the current instance stage */
898 unsigned long reset_stage; /* the current reset stage */
899 unsigned long reset_cnt;
900 bool sw_resetting;
901 bool hw_resetting;
902
903 if (hr_dev->is_reset)
904 return CMD_RST_PRC_SUCCESS;
905
906 /* Get information about reset from NIC driver or RoCE driver itself,
907 * the meaning of the following variables from NIC driver are described
908 * as below:
909 * reset_cnt -- The count value of completed hardware reset.
910 * hw_resetting -- Whether hardware device is resetting now.
911 * sw_resetting -- Whether NIC's software reset process is running now.
912 */
913 instance_stage = handle->rinfo.instance_state;
914 reset_stage = handle->rinfo.reset_state;
915 reset_cnt = ops->ae_dev_reset_cnt(handle);
3ec5f54f 916 hw_resetting = ops->get_cmdq_stat(handle);
6a04aed6
WHX		 917 sw_resetting = ops->ae_dev_resetting(handle);
918
919 if (reset_cnt != hr_dev->reset_cnt)
920 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
921 reset_stage);
922 else if (hw_resetting)
923 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
924 reset_stage);
925 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
926 return hns_roce_v2_cmd_sw_resetting(hr_dev);
927
928 return 0;
929}
930
a04ff739
WHX		 931static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
932{
933 int ntu = ring->next_to_use;
934 int ntc = ring->next_to_clean;
935 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
936
937 return ring->desc_num - used - 1;
938}
939
940static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
941 struct hns_roce_v2_cmq_ring *ring)
942{
943 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
944
945 ring->desc = kzalloc(size, GFP_KERNEL);
946 if (!ring->desc)
947 return -ENOMEM;
948
949 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
950 DMA_BIDIRECTIONAL);
951 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
952 ring->desc_dma_addr = 0;
953 kfree(ring->desc);
954 ring->desc = NULL;
955 return -ENOMEM;
956 }
957
958 return 0;
959}
960
961static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
962 struct hns_roce_v2_cmq_ring *ring)
963{
964 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
965 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
966 DMA_BIDIRECTIONAL);
90e7a4d5 967
968 ring->desc_dma_addr = 0;
a04ff739
WHX		 969 kfree(ring->desc);
970}
971
972static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
973{
14ba8730 974 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 975 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
976 &priv->cmq.csq : &priv->cmq.crq;
977
978 ring->flag = ring_type;
979 ring->next_to_clean = 0;
980 ring->next_to_use = 0;
981
982 return hns_roce_alloc_cmq_desc(hr_dev, ring);
983}
984
985static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
986{
14ba8730 987 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 988 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
989 &priv->cmq.csq : &priv->cmq.crq;
990 dma_addr_t dma = ring->desc_dma_addr;
991
992 if (ring_type == TYPE_CSQ) {
993 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
994 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
995 upper_32_bits(dma));
996 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
2288b3b3 997 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 998 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
999 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
1000 } else {
1001 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
1002 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
1003 upper_32_bits(dma));
1004 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
2288b3b3 1005 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 1006 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
1007 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
1008 }
1009}
1010
1011static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1012{
14ba8730 1013 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1014 int ret;
1015
1016 /* Setup the queue entries for command queue */
426c4146
LO		 1017 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
1018 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 1019
1020 /* Setup the lock for command queue */
1021 spin_lock_init(&priv->cmq.csq.lock);
1022 spin_lock_init(&priv->cmq.crq.lock);
1023
1024 /* Setup Tx write back timeout */
1025 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1026
1027 /* Init CSQ */
1028 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
1029 if (ret) {
1030 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
1031 return ret;
1032 }
1033
1034 /* Init CRQ */
1035 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
1036 if (ret) {
1037 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
1038 goto err_crq;
1039 }
1040
1041 /* Init CSQ REG */
1042 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
1043
1044 /* Init CRQ REG */
1045 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
1046
1047 return 0;
1048
1049err_crq:
1050 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1051
1052 return ret;
1053}
1054
1055static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1056{
14ba8730 1057 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1058
1059 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1060 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
1061}
1062
281d0ccf
CIK		 1063static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1064 enum hns_roce_opcode_type opcode,
1065 bool is_read)
a04ff739
WHX		 1066{
1067 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1068 desc->opcode = cpu_to_le16(opcode);
1069 desc->flag =
1070 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1071 if (is_read)
1072 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1073 else
1074 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1075}
1076
1077static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1078{
a04ff739 1079 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
14ba8730 1080 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1081
1082 return head == priv->cmq.csq.next_to_use;
1083}
1084
1085static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
1086{
14ba8730 1087 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1088 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1089 struct hns_roce_cmq_desc *desc;
1090 u16 ntc = csq->next_to_clean;
1091 u32 head;
1092 int clean = 0;
1093
1094 desc = &csq->desc[ntc];
1095 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
1096 while (head != ntc) {
1097 memset(desc, 0, sizeof(*desc));
1098 ntc++;
1099 if (ntc == csq->desc_num)
1100 ntc = 0;
1101 desc = &csq->desc[ntc];
1102 clean++;
1103 }
1104 csq->next_to_clean = ntc;
1105
1106 return clean;
1107}
1108
6a04aed6
WHX		 1109static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1110 struct hns_roce_cmq_desc *desc, int num)
a04ff739 1111{
14ba8730 1112 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1113 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1114 struct hns_roce_cmq_desc *desc_to_use;
1115 bool complete = false;
1116 u32 timeout = 0;
1117 int handle = 0;
1118 u16 desc_ret;
1119 int ret = 0;
1120 int ntc;
1121
1122 spin_lock_bh(&csq->lock);
1123
1124 if (num > hns_roce_cmq_space(csq)) {
1125 spin_unlock_bh(&csq->lock);
1126 return -EBUSY;
1127 }
1128
1129 /*
1130 * Record the location of desc in the cmq for this time
1131 * which will be use for hardware to write back
1132 */
1133 ntc = csq->next_to_use;
1134
1135 while (handle < num) {
1136 desc_to_use = &csq->desc[csq->next_to_use];
1137 *desc_to_use = desc[handle];
1138 dev_dbg(hr_dev->dev, "set cmq desc:\n");
1139 csq->next_to_use++;
1140 if (csq->next_to_use == csq->desc_num)
1141 csq->next_to_use = 0;
1142 handle++;
1143 }
1144
1145 /* Write to hardware */
1146 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
1147
1148 /*
1149 * If the command is sync, wait for the firmware to write back,
1150 * if multi descriptors to be sent, use the first one to check
1151 */
bfe86035 1152 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
a04ff739
WHX		 1153 do {
1154 if (hns_roce_cmq_csq_done(hr_dev))
1155 break;
988e175b 1156 udelay(1);
a04ff739
WHX		 1157 timeout++;
1158 } while (timeout < priv->cmq.tx_timeout);
1159 }
1160
1161 if (hns_roce_cmq_csq_done(hr_dev)) {
1162 complete = true;
1163 handle = 0;
1164 while (handle < num) {
1165 /* get the result of hardware write back */
1166 desc_to_use = &csq->desc[ntc];
1167 desc[handle] = *desc_to_use;
1168 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
bfe86035 1169 desc_ret = le16_to_cpu(desc[handle].retval);
a04ff739
WHX		 1170 if (desc_ret == CMD_EXEC_SUCCESS)
1171 ret = 0;
1172 else
1173 ret = -EIO;
1174 priv->cmq.last_status = desc_ret;
1175 ntc++;
1176 handle++;
1177 if (ntc == csq->desc_num)
1178 ntc = 0;
1179 }
1180 }
1181
1182 if (!complete)
1183 ret = -EAGAIN;
1184
1185 /* clean the command send queue */
1186 handle = hns_roce_cmq_csq_clean(hr_dev);
1187 if (handle != num)
1188 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
1189 handle, num);
1190
1191 spin_unlock_bh(&csq->lock);
1192
1193 return ret;
1194}
1195
e95e52a1 1196static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
6a04aed6
WHX		 1197 struct hns_roce_cmq_desc *desc, int num)
1198{
1199 int retval;
1200 int ret;
1201
1202 ret = hns_roce_v2_rst_process_cmd(hr_dev);
1203 if (ret == CMD_RST_PRC_SUCCESS)
1204 return 0;
1205 if (ret == CMD_RST_PRC_EBUSY)
b417c087 1206 return -EBUSY;
6a04aed6
WHX		 1207
1208 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1209 if (ret) {
1210 retval = hns_roce_v2_rst_process_cmd(hr_dev);
1211 if (retval == CMD_RST_PRC_SUCCESS)
1212 return 0;
1213 else if (retval == CMD_RST_PRC_EBUSY)
b417c087 1214 return -EBUSY;
6a04aed6
WHX		 1215 }
1216
1217 return ret;
1218}
1219
281d0ccf 1220static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 1221{
1222 struct hns_roce_query_version *resp;
1223 struct hns_roce_cmq_desc desc;
1224 int ret;
1225
1226 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1227 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1228 if (ret)
1229 return ret;
1230
1231 resp = (struct hns_roce_query_version *)desc.data;
bfe86035 1232 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 1233 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1234
1235 return 0;
1236}
1237
e075da5e
LC		 1238static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev)
1239{
14ba8730 1240 struct hns_roce_v2_priv *priv = hr_dev->priv;
e075da5e
LC		 1241 struct hnae3_handle *handle = priv->handle;
1242 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1243 unsigned long reset_cnt;
1244 bool sw_resetting;
1245 bool hw_resetting;
1246
1247 reset_cnt = ops->ae_dev_reset_cnt(handle);
1248 hw_resetting = ops->get_hw_reset_stat(handle);
1249 sw_resetting = ops->ae_dev_resetting(handle);
1250
1251 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting)
1252 return true;
1253
1254 return false;
1255}
1256
1257static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval,
1258 int flag)
1259{
14ba8730 1260 struct hns_roce_v2_priv *priv = hr_dev->priv;
e075da5e
LC		 1261 struct hnae3_handle *handle = priv->handle;
1262 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1263 unsigned long instance_stage;
1264 unsigned long reset_cnt;
1265 unsigned long end;
1266 bool sw_resetting;
1267 bool hw_resetting;
1268
1269 instance_stage = handle->rinfo.instance_state;
1270 reset_cnt = ops->ae_dev_reset_cnt(handle);
1271 hw_resetting = ops->get_hw_reset_stat(handle);
1272 sw_resetting = ops->ae_dev_resetting(handle);
1273
1274 if (reset_cnt != hr_dev->reset_cnt) {
1275 hr_dev->dis_db = true;
1276 hr_dev->is_reset = true;
1277 dev_info(hr_dev->dev, "Func clear success after reset.\n");
1278 } else if (hw_resetting) {
1279 hr_dev->dis_db = true;
1280
1281 dev_warn(hr_dev->dev,
1282 "Func clear is pending, device in resetting state.\n");
1283 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1284 while (end) {
1285 if (!ops->get_hw_reset_stat(handle)) {
1286 hr_dev->is_reset = true;
1287 dev_info(hr_dev->dev,
1288 "Func clear success after reset.\n");
1289 return;
1290 }
1291 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1292 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1293 }
1294
1295 dev_warn(hr_dev->dev, "Func clear failed.\n");
1296 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) {
1297 hr_dev->dis_db = true;
1298
1299 dev_warn(hr_dev->dev,
1300 "Func clear is pending, device in resetting state.\n");
1301 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1302 while (end) {
1303 if (ops->ae_dev_reset_cnt(handle) !=
1304 hr_dev->reset_cnt) {
1305 hr_dev->is_reset = true;
1306 dev_info(hr_dev->dev,
1307 "Func clear success after sw reset\n");
1308 return;
1309 }
1310 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1311 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1312 }
1313
1314 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
1315 } else {
1316 if (retval && !flag)
1317 dev_warn(hr_dev->dev,
1318 "Func clear read failed, ret = %d.\n", retval);
1319
1320 dev_warn(hr_dev->dev, "Func clear failed.\n");
1321 }
1322}
89a6da3c
LC		 1323static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1324{
e075da5e 1325 bool fclr_write_fail_flag = false;
89a6da3c
LC		 1326 struct hns_roce_func_clear *resp;
1327 struct hns_roce_cmq_desc desc;
1328 unsigned long end;
e075da5e
LC		 1329 int ret = 0;
1330
1331 if (hns_roce_func_clr_chk_rst(hr_dev))
1332 goto out;
89a6da3c
LC		 1333
1334 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1335 resp = (struct hns_roce_func_clear *)desc.data;
1336
1337 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1338 if (ret) {
e075da5e 1339 fclr_write_fail_flag = true;
89a6da3c
LC		 1340 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n",
1341 ret);
e075da5e 1342 goto out;
89a6da3c
LC		 1343 }
1344
1345 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1346 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1347 while (end) {
e075da5e
LC		 1348 if (hns_roce_func_clr_chk_rst(hr_dev))
1349 goto out;
89a6da3c
LC		 1350 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1351 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1352
1353 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1354 true);
1355
1356 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1357 if (ret)
1358 continue;
1359
1360 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) {
1361 hr_dev->is_reset = true;
1362 return;
1363 }
1364 }
1365
e075da5e 1366out:
e075da5e 1367 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag);
89a6da3c
LC		 1368}
1369
3a63c964
LO		 1370static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1371{
1372 struct hns_roce_query_fw_info *resp;
1373 struct hns_roce_cmq_desc desc;
1374 int ret;
1375
1376 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1377 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1378 if (ret)
1379 return ret;
1380
1381 resp = (struct hns_roce_query_fw_info *)desc.data;
1382 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1383
1384 return 0;
1385}
1386
1387static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1388{
1389 struct hns_roce_cfg_global_param *req;
1390 struct hns_roce_cmq_desc desc;
1391
1392 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1393 false);
1394
1395 req = (struct hns_roce_cfg_global_param *)desc.data;
1396 memset(req, 0, sizeof(*req));
1397 roce_set_field(req->time_cfg_udp_port,
1398 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1399 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1400 roce_set_field(req->time_cfg_udp_port,
1401 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1402 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1403
1404 return hns_roce_cmq_send(hr_dev, &desc, 1);
1405}
1406
1407static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1408{
1409 struct hns_roce_cmq_desc desc[2];
6b63597d 1410 struct hns_roce_pf_res_a *req_a;
1411 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1412 int ret;
1413 int i;
1414
1415 for (i = 0; i < 2; i++) {
1416 hns_roce_cmq_setup_basic_desc(&desc[i],
1417 HNS_ROCE_OPC_QUERY_PF_RES, true);
1418
1419 if (i == 0)
1420 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1421 else
1422 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1423 }
1424
1425 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1426 if (ret)
1427 return ret;
1428
6b63597d 1429 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1430 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1431
6b63597d 1432 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1433 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1434 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1435 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1436 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1437 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1438 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1439 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1440 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1441 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1442 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1443 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1444
6b63597d 1445 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1446 PF_RES_DATA_3_PF_SL_NUM_M,
1447 PF_RES_DATA_3_PF_SL_NUM_S);
6a157f7d
YL		 1448 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,
1449 PF_RES_DATA_4_PF_SCCC_BT_NUM_M,
1450 PF_RES_DATA_4_PF_SCCC_BT_NUM_S);
6b63597d 1451
cfc85f3e
WHX		 1452 return 0;
1453}
1454
0e40dc2f
YL		 1455static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
1456{
1457 struct hns_roce_pf_timer_res_a *req_a;
441c88d5
LC		 1458 struct hns_roce_cmq_desc desc;
1459 int ret;
0e40dc2f 1460
441c88d5
LC		 1461 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1462 true);
0e40dc2f 1463
441c88d5 1464 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
0e40dc2f
YL		 1465 if (ret)
1466 return ret;
1467
441c88d5 1468 req_a = (struct hns_roce_pf_timer_res_a *)desc.data;
0e40dc2f
YL		 1469
1470 hr_dev->caps.qpc_timer_bt_num =
441c88d5
LC		 1471 roce_get_field(req_a->qpc_timer_bt_idx_num,
1472 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
1473 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
0e40dc2f 1474 hr_dev->caps.cqc_timer_bt_num =
441c88d5
LC		 1475 roce_get_field(req_a->cqc_timer_bt_idx_num,
1476 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
1477 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
0e40dc2f
YL		 1478
1479 return 0;
1480}
1481
60262b10 1482static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id)
0c1c3880
LO		 1483{
1484 struct hns_roce_cmq_desc desc;
1485 struct hns_roce_vf_switch *swt;
1486 int ret;
1487
1488 swt = (struct hns_roce_vf_switch *)desc.data;
1489 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
bfe86035 1490 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
60262b10
LO		 1491 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1492 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id);
0c1c3880
LO		 1493 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1494 if (ret)
1495 return ret;
60262b10 1496
0c1c3880
LO		 1497 desc.flag =
1498 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1499 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1500 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
d967e262 1501 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0);
0c1c3880
LO		 1502 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1503
1504 return hns_roce_cmq_send(hr_dev, &desc, 1);
1505}
1506
cfc85f3e
WHX		 1507static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1508{
1509 struct hns_roce_cmq_desc desc[2];
1510 struct hns_roce_vf_res_a *req_a;
1511 struct hns_roce_vf_res_b *req_b;
1512 int i;
1513
1514 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1515 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
cfc85f3e
WHX		 1516 for (i = 0; i < 2; i++) {
1517 hns_roce_cmq_setup_basic_desc(&desc[i],
1518 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1519
1520 if (i == 0)
1521 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1522 else
1523 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
cfc85f3e
WHX		 1524 }
1525
99e713f8
LO		 1526 roce_set_field(req_a->vf_qpc_bt_idx_num,
1527 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1528 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1529 roce_set_field(req_a->vf_qpc_bt_idx_num,
1530 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1531 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM);
1532
1533 roce_set_field(req_a->vf_srqc_bt_idx_num,
1534 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1535 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1536 roce_set_field(req_a->vf_srqc_bt_idx_num,
1537 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1538 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1539 HNS_ROCE_VF_SRQC_BT_NUM);
1540
1541 roce_set_field(req_a->vf_cqc_bt_idx_num,
1542 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1543 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1544 roce_set_field(req_a->vf_cqc_bt_idx_num,
1545 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1546 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM);
1547
1548 roce_set_field(req_a->vf_mpt_bt_idx_num,
1549 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1550 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1551 roce_set_field(req_a->vf_mpt_bt_idx_num,
1552 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1553 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM);
1554
1555 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M,
1556 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1557 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M,
1558 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM);
1559
1560 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1561 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1562 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1563 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM);
1564
1565 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M,
1566 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1567 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M,
1568 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM);
1569
1570 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M,
1571 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1572 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M,
1573 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM);
1574
1575 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,
1576 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);
1577 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,
1578 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,
1579 HNS_ROCE_VF_SCCC_BT_NUM);
1580
cfc85f3e
WHX		 1581 return hns_roce_cmq_send(hr_dev, desc, 2);
1582}
1583
a81fba28
WHX		 1584static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1585{
1586 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1587 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1588 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1589 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
6a157f7d 1590 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;
a81fba28
WHX		 1591 struct hns_roce_cfg_bt_attr *req;
1592 struct hns_roce_cmq_desc desc;
1593
1594 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1595 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1596 memset(req, 0, sizeof(*req));
1597
1598 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1599 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1600 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1601 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1602 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1603 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1604 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1605 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1606 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1607
1608 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1609 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1610 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1611 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1612 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1613 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1614 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1615 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1616 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1617
1618 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1619 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1620 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1621 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1622 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1623 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1624 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1625 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1626 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1627
1628 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1629 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1630 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1631 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1632 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1633 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1634 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1635 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1636 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1637
6a157f7d
YL		 1638 roce_set_field(req->vf_sccc_cfg,
1639 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,
1640 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,
1641 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1642 roce_set_field(req->vf_sccc_cfg,
1643 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,
1644 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,
1645 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1646 roce_set_field(req->vf_sccc_cfg,
1647 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,
1648 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,
1649 sccc_hop_num ==
1650 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);
1651
a81fba28
WHX		 1652 return hns_roce_cmq_send(hr_dev, &desc, 1);
1653}
1654
ba6bb7e9
LO		 1655static void set_default_caps(struct hns_roce_dev *hr_dev)
1656{
1657 struct hns_roce_caps *caps = &hr_dev->caps;
1658
1659 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1660 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1661 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1662 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
1663 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1664 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1665 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1666 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
1667 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1668 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1669 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1670 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
1671 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1672 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1673 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1674 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1675 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1676 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1677 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1678 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1679 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1680 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1681 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1682 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1683 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1684 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
98912ee8 1685 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
ba6bb7e9 1686 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
7db82697 1687 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
ba6bb7e9
LO		 1688 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1689 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1690 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1691 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1692 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ;
09a5f210 1693 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
ba6bb7e9
LO		 1694 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1695 caps->reserved_lkey = 0;
1696 caps->reserved_pds = 0;
1697 caps->reserved_mrws = 1;
1698 caps->reserved_uars = 0;
1699 caps->reserved_cqs = 0;
1700 caps->reserved_srqs = 0;
1701 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
1702
1703 caps->qpc_ba_pg_sz = 0;
1704 caps->qpc_buf_pg_sz = 0;
1705 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1706 caps->srqc_ba_pg_sz = 0;
1707 caps->srqc_buf_pg_sz = 0;
1708 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1709 caps->cqc_ba_pg_sz = 0;
1710 caps->cqc_buf_pg_sz = 0;
1711 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1712 caps->mpt_ba_pg_sz = 0;
1713 caps->mpt_buf_pg_sz = 0;
1714 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1715 caps->mtt_ba_pg_sz = 0;
1716 caps->mtt_buf_pg_sz = 0;
1717 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1718 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM;
1719 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM;
1720 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM;
1721 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
1722 caps->cqe_buf_pg_sz = 0;
1723 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
1724 caps->srqwqe_ba_pg_sz = 0;
1725 caps->srqwqe_buf_pg_sz = 0;
1726 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
1727 caps->idx_ba_pg_sz = 0;
1728 caps->idx_buf_pg_sz = 0;
1729 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
1730 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
1731
1732 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
1733 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
1734 HNS_ROCE_CAP_FLAG_RQ_INLINE |
1735 HNS_ROCE_CAP_FLAG_RECORD_DB |
1736 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
1737
1738 caps->pkey_table_len[0] = 1;
1739 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
1740 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1741 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
247fc16d
WL		 1742 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
1743 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
ba6bb7e9
LO		 1744 caps->local_ca_ack_delay = 0;
1745 caps->max_mtu = IB_MTU_4096;
1746
1747 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1748 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1749
a247fd28
LC		 1750 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
1751 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
1752 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
1753
1754 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1755 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1756 caps->qpc_timer_ba_pg_sz = 0;
1757 caps->qpc_timer_buf_pg_sz = 0;
1758 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1759 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1760 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1761 caps->cqc_timer_ba_pg_sz = 0;
1762 caps->cqc_timer_buf_pg_sz = 0;
1763 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1764
1765 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
1766 caps->sccc_ba_pg_sz = 0;
1767 caps->sccc_buf_pg_sz = 0;
1768 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
247fc16d
WL		 1769
1770 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1771 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
1772 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
09a5f210 1773 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
98912ee8 1774 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
247fc16d 1775 }
ba6bb7e9
LO		 1776}
1777
1778static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
1779 int *buf_page_size, int *bt_page_size, u32 hem_type)
1780{
1781 u64 obj_per_chunk;
1782 int bt_chunk_size = 1 << PAGE_SHIFT;
1783 int buf_chunk_size = 1 << PAGE_SHIFT;
1784 int obj_per_chunk_default = buf_chunk_size / obj_size;
1785
1786 *buf_page_size = 0;
1787 *bt_page_size = 0;
1788
1789 switch (hop_num) {
1790 case 3:
1791 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1792 (bt_chunk_size / BA_BYTE_LEN) *
1793 (bt_chunk_size / BA_BYTE_LEN) *
1794 obj_per_chunk_default;
1795 break;
1796 case 2:
1797 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1798 (bt_chunk_size / BA_BYTE_LEN) *
1799 obj_per_chunk_default;
1800 break;
1801 case 1:
1802 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1803 obj_per_chunk_default;
1804 break;
1805 case HNS_ROCE_HOP_NUM_0:
1806 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1807 break;
1808 default:
1809 pr_err("Table %d not support hop_num = %d!\n", hem_type,
1810 hop_num);
1811 return;
1812 }
1813
1814 if (hem_type >= HEM_TYPE_MTT)
1815 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1816 else
1817 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1818}
1819
1820static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
1821{
1822 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
1823 struct hns_roce_caps *caps = &hr_dev->caps;
1824 struct hns_roce_query_pf_caps_a *resp_a;
1825 struct hns_roce_query_pf_caps_b *resp_b;
1826 struct hns_roce_query_pf_caps_c *resp_c;
1827 struct hns_roce_query_pf_caps_d *resp_d;
1828 struct hns_roce_query_pf_caps_e *resp_e;
1829 int ctx_hop_num;
1830 int pbl_hop_num;
1831 int ret;
1832 int i;
1833
1834 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
1835 hns_roce_cmq_setup_basic_desc(&desc[i],
1836 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
1837 true);
1838 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
1839 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1840 else
1841 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1842 }
1843
1844 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
1845 if (ret)
1846 return ret;
1847
1848 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
1849 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
1850 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
1851 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
1852 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
1853
1854 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
1855 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
1856 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
1857 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
1858 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg);
1859 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer);
1860 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer);
1861 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
1862 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
1863 caps->num_other_vectors = resp_a->num_other_vectors;
1864 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
1865 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
1866 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz;
09a5f210 1867 caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;
ba6bb7e9
LO		 1868
1869 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
1870 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
1871 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
1872 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
1873 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
1874 caps->idx_entry_sz = resp_b->idx_entry_sz;
1875 caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz;
1876 caps->max_mtu = resp_b->max_mtu;
98912ee8 1877 caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;
ba6bb7e9
LO		 1878 caps->min_cqes = resp_b->min_cqes;
1879 caps->min_wqes = resp_b->min_wqes;
1880 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
1881 caps->pkey_table_len[0] = resp_b->pkey_table_len;
1882 caps->phy_num_uars = resp_b->phy_num_uars;
1883 ctx_hop_num = resp_b->ctx_hop_num;
1884 pbl_hop_num = resp_b->pbl_hop_num;
1885
1886 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds,
1887 V2_QUERY_PF_CAPS_C_NUM_PDS_M,
1888 V2_QUERY_PF_CAPS_C_NUM_PDS_S);
1889 caps->flags = roce_get_field(resp_c->cap_flags_num_pds,
1890 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M,
1891 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S);
30661322
WL		 1892 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
1893 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
1894
ba6bb7e9
LO		 1895 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs,
1896 V2_QUERY_PF_CAPS_C_NUM_CQS_M,
1897 V2_QUERY_PF_CAPS_C_NUM_CQS_S);
1898 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs,
1899 V2_QUERY_PF_CAPS_C_MAX_GID_M,
1900 V2_QUERY_PF_CAPS_C_MAX_GID_S);
1901 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth,
1902 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M,
1903 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S);
1904 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws,
1905 V2_QUERY_PF_CAPS_C_NUM_MRWS_M,
1906 V2_QUERY_PF_CAPS_C_NUM_MRWS_S);
1907 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps,
1908 V2_QUERY_PF_CAPS_C_NUM_QPS_M,
1909 V2_QUERY_PF_CAPS_C_NUM_QPS_S);
1910 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps,
1911 V2_QUERY_PF_CAPS_C_MAX_ORD_M,
1912 V2_QUERY_PF_CAPS_C_MAX_ORD_S);
1913 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
1914 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
1915 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs,
1916 V2_QUERY_PF_CAPS_D_NUM_SRQS_M,
1917 V2_QUERY_PF_CAPS_D_NUM_SRQS_S);
1918 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
1919 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth,
1920 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M,
1921 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S);
1922 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth,
1923 V2_QUERY_PF_CAPS_D_NUM_CEQS_M,
1924 V2_QUERY_PF_CAPS_D_NUM_CEQS_S);
1925 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth,
1926 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M,
1927 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S);
1928 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1929 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M,
1930 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S);
1931 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1932 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M,
1933 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S);
1934 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds,
1935 V2_QUERY_PF_CAPS_D_RSV_PDS_M,
1936 V2_QUERY_PF_CAPS_D_RSV_PDS_S);
1937 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds,
1938 V2_QUERY_PF_CAPS_D_NUM_UARS_M,
1939 V2_QUERY_PF_CAPS_D_NUM_UARS_S);
1940 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps,
1941 V2_QUERY_PF_CAPS_D_RSV_QPS_M,
1942 V2_QUERY_PF_CAPS_D_RSV_QPS_S);
1943 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps,
1944 V2_QUERY_PF_CAPS_D_RSV_UARS_M,
1945 V2_QUERY_PF_CAPS_D_RSV_UARS_S);
1946 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1947 V2_QUERY_PF_CAPS_E_RSV_MRWS_M,
1948 V2_QUERY_PF_CAPS_E_RSV_MRWS_S);
1949 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1950 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M,
1951 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S);
1952 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs,
1953 V2_QUERY_PF_CAPS_E_RSV_CQS_M,
1954 V2_QUERY_PF_CAPS_E_RSV_CQS_S);
1955 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs,
1956 V2_QUERY_PF_CAPS_E_RSV_SRQS_M,
1957 V2_QUERY_PF_CAPS_E_RSV_SRQS_S);
1958 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey,
1959 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M,
1960 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S);
1961 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
1962 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
1963 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
1964 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
1965
1966 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1967 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1968 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1969 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
247fc16d
WL		 1970 caps->ceqe_size = HNS_ROCE_CEQE_SIZE;
1971 caps->aeqe_size = HNS_ROCE_AEQE_SIZE;
ba6bb7e9
LO		 1972 caps->mtt_ba_pg_sz = 0;
1973 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1974 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1975 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1976
1977 caps->qpc_hop_num = ctx_hop_num;
1978 caps->srqc_hop_num = ctx_hop_num;
1979 caps->cqc_hop_num = ctx_hop_num;
1980 caps->mpt_hop_num = ctx_hop_num;
1981 caps->mtt_hop_num = pbl_hop_num;
1982 caps->cqe_hop_num = pbl_hop_num;
1983 caps->srqwqe_hop_num = pbl_hop_num;
1984 caps->idx_hop_num = pbl_hop_num;
1985 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1986 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M,
1987 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S);
1988 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1989 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M,
1990 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S);
1991 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1992 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
1993 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
1994
247fc16d
WL		 1995 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
1996 caps->ceqe_size = HNS_ROCE_V3_EQE_SIZE;
1997 caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;
09a5f210 1998 caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;
98912ee8 1999 caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;
247fc16d
WL		 2000 }
2001
98912ee8 2002 calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
ba6bb7e9
LO		 2003 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
2004 HEM_TYPE_QPC);
2005 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
2006 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
2007 HEM_TYPE_MTPT);
2008 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
2009 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
2010 HEM_TYPE_CQC);
2011 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num,
2012 caps->srqc_bt_num, &caps->srqc_buf_pg_sz,
2013 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC);
2014
a247fd28
LC		 2015 caps->sccc_hop_num = ctx_hop_num;
2016 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2017 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2018
2019 calc_pg_sz(caps->num_qps, caps->sccc_entry_sz,
2020 caps->sccc_hop_num, caps->sccc_bt_num,
2021 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,
2022 HEM_TYPE_SCCC);
2023 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
2024 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
2025 &caps->cqc_timer_buf_pg_sz,
2026 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
ba6bb7e9
LO		 2027
2028 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num,
2029 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2030 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2031 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2032 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2033 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num,
2034 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2035
2036 return 0;
2037}
2038
98912ee8
WL		 2039static int hns_roce_config_qpc_size(struct hns_roce_dev *hr_dev)
2040{
2041 struct hns_roce_cmq_desc desc;
2042 struct hns_roce_cfg_entry_size *cfg_size =
2043 (struct hns_roce_cfg_entry_size *)desc.data;
2044
2045 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,
2046 false);
2047
2048 cfg_size->type = cpu_to_le32(HNS_ROCE_CFG_QPC_SIZE);
2049 cfg_size->size = cpu_to_le32(hr_dev->caps.qpc_sz);
2050
2051 return hns_roce_cmq_send(hr_dev, &desc, 1);
2052}
2053
2054static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)
2055{
2056 int ret;
2057
2058 if (hr_dev->pci_dev->revision < PCI_REVISION_ID_HIP09)
2059 return 0;
2060
2061 ret = hns_roce_config_qpc_size(hr_dev);
2062 if (ret)
2063 dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);
2064
2065 return ret;
2066}
2067
cfc85f3e
WHX		 2068static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2069{
2070 struct hns_roce_caps *caps = &hr_dev->caps;
2071 int ret;
2072
2073 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 2074 if (ret) {
2075 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
2076 ret);
2077 return ret;
2078 }
2079
2080 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 2081 if (ret) {
2082 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
2083 ret);
2084 return ret;
2085 }
2086
2087 ret = hns_roce_config_global_param(hr_dev);
2088 if (ret) {
2089 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
2090 ret);
2349fdd4 2091 return ret;
cfc85f3e
WHX		 2092 }
2093
2094 /* Get pf resource owned by every pf */
2095 ret = hns_roce_query_pf_resource(hr_dev);
2096 if (ret) {
2097 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
2098 ret);
2099 return ret;
2100 }
2101
a247fd28
LC		 2102 ret = hns_roce_query_pf_timer_resource(hr_dev);
2103 if (ret) {
2104 dev_err(hr_dev->dev,
2105 "failed to query pf timer resource, ret = %d.\n", ret);
2106 return ret;
2107 }
cfc85f3e 2108
a247fd28
LC		 2109 ret = hns_roce_set_vf_switch_param(hr_dev, 0);
2110 if (ret) {
2111 dev_err(hr_dev->dev,
2112 "failed to set function switch param, ret = %d.\n",
2113 ret);
2114 return ret;
0c1c3880 2115 }
3a63c964
LO		 2116
2117 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2118 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e 2119
80a78570 2120 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
ff795f71
WHX		 2121 caps->pbl_buf_pg_sz = 0;
2122 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
a5073d60
YL		 2123 caps->eqe_ba_pg_sz = 0;
2124 caps->eqe_buf_pg_sz = 0;
2125 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 2126 caps->tsq_buf_pg_sz = 0;
aa84fa18 2127
80a78570
LO		 2128 ret = hns_roce_query_pf_caps(hr_dev);
2129 if (ret)
2130 set_default_caps(hr_dev);
384f8818 2131
99e713f8
LO		 2132 ret = hns_roce_alloc_vf_resource(hr_dev);
2133 if (ret) {
2134 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
2135 ret);
2136 return ret;
2137 }
2138
a81fba28 2139 ret = hns_roce_v2_set_bt(hr_dev);
98912ee8
WL		 2140 if (ret) {
2141 dev_err(hr_dev->dev,
2142 "Configure bt attribute fail, ret = %d.\n", ret);
2143 return ret;
2144 }
2145
2146 /* Configure the size of QPC, SCCC, etc. */
2147 ret = hns_roce_config_entry_size(hr_dev);
a81fba28
WHX		 2148
2149 return ret;
cfc85f3e
WHX		 2150}
2151
6b63597d 2152static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
2153 enum hns_roce_link_table_type type)
2154{
2155 struct hns_roce_cmq_desc desc[2];
2156 struct hns_roce_cfg_llm_a *req_a =
2157 (struct hns_roce_cfg_llm_a *)desc[0].data;
2158 struct hns_roce_cfg_llm_b *req_b =
2159 (struct hns_roce_cfg_llm_b *)desc[1].data;
2160 struct hns_roce_v2_priv *priv = hr_dev->priv;
2161 struct hns_roce_link_table *link_tbl;
2162 struct hns_roce_link_table_entry *entry;
2163 enum hns_roce_opcode_type opcode;
2164 u32 page_num;
2165 int i;
2166
2167 switch (type) {
2168 case TSQ_LINK_TABLE:
2169 link_tbl = &priv->tsq;
2170 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2171 break;
ded58ff9 2172 case TPQ_LINK_TABLE:
2173 link_tbl = &priv->tpq;
2174 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
2175 break;
6b63597d 2176 default:
2177 return -EINVAL;
2178 }
2179
2180 page_num = link_tbl->npages;
2181 entry = link_tbl->table.buf;
6b63597d 2182
2183 for (i = 0; i < 2; i++) {
2184 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
2185
2186 if (i == 0)
2187 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2188 else
2189 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
6b63597d 2190 }
9976ea27
LO		 2191
2192 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff);
2193 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32);
2194 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M,
2195 CFG_LLM_QUE_DEPTH_S, link_tbl->npages);
2196 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M,
2197 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz);
60262b10
LO		 2198 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M,
2199 CFG_LLM_INIT_EN_S, 1);
9976ea27
LO		 2200 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0);
2201 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr);
2202 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S,
2203 0);
2204
2205 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0);
2206 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M,
2207 CFG_LLM_TAIL_BA_H_S,
2208 entry[page_num - 1].blk_ba1_nxt_ptr &
2209 HNS_ROCE_LINK_TABLE_BA1_M);
2210 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S,
2211 (entry[page_num - 2].blk_ba1_nxt_ptr &
2212 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
2213 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
6b63597d 2214
2215 return hns_roce_cmq_send(hr_dev, desc, 2);
2216}
2217
2218static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
2219 enum hns_roce_link_table_type type)
2220{
2221 struct hns_roce_v2_priv *priv = hr_dev->priv;
2222 struct hns_roce_link_table *link_tbl;
2223 struct hns_roce_link_table_entry *entry;
2224 struct device *dev = hr_dev->dev;
2225 u32 buf_chk_sz;
2226 dma_addr_t t;
ded58ff9 2227 int func_num = 1;
6b63597d 2228 int pg_num_a;
2229 int pg_num_b;
2230 int pg_num;
2231 int size;
2232 int i;
2233
2234 switch (type) {
2235 case TSQ_LINK_TABLE:
2236 link_tbl = &priv->tsq;
2237 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
2238 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
2239 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
2240 break;
ded58ff9 2241 case TPQ_LINK_TABLE:
2242 link_tbl = &priv->tpq;
2243 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
2244 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
2245 pg_num_b = 2 * 4 * func_num + 2;
2246 break;
6b63597d 2247 default:
2248 return -EINVAL;
2249 }
2250
2251 pg_num = max(pg_num_a, pg_num_b);
2252 size = pg_num * sizeof(struct hns_roce_link_table_entry);
2253
2254 link_tbl->table.buf = dma_alloc_coherent(dev, size,
2255 &link_tbl->table.map,
2256 GFP_KERNEL);
2257 if (!link_tbl->table.buf)
2258 goto out;
2259
2260 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
2261 GFP_KERNEL);
2262 if (!link_tbl->pg_list)
2263 goto err_kcalloc_failed;
2264
2265 entry = link_tbl->table.buf;
2266 for (i = 0; i < pg_num; ++i) {
2267 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
2268 &t, GFP_KERNEL);
2269 if (!link_tbl->pg_list[i].buf)
2270 goto err_alloc_buf_failed;
2271
2272 link_tbl->pg_list[i].map = t;
6b63597d 2273
bfe86035
LC		 2274 entry[i].blk_ba0 = (u32)(t >> 12);
2275 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44);
6b63597d 2276
2277 if (i < (pg_num - 1))
bfe86035
LC		 2278 entry[i].blk_ba1_nxt_ptr |=
2279 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S;
2280
6b63597d 2281 }
2282 link_tbl->npages = pg_num;
2283 link_tbl->pg_sz = buf_chk_sz;
2284
2285 return hns_roce_config_link_table(hr_dev, type);
2286
2287err_alloc_buf_failed:
2288 for (i -= 1; i >= 0; i--)
2289 dma_free_coherent(dev, buf_chk_sz,
2290 link_tbl->pg_list[i].buf,
2291 link_tbl->pg_list[i].map);
2292 kfree(link_tbl->pg_list);
2293
2294err_kcalloc_failed:
2295 dma_free_coherent(dev, size, link_tbl->table.buf,
2296 link_tbl->table.map);
2297
2298out:
2299 return -ENOMEM;
2300}
2301
2302static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
2303 struct hns_roce_link_table *link_tbl)
2304{
2305 struct device *dev = hr_dev->dev;
2306 int size;
2307 int i;
2308
2309 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
2310
2311 for (i = 0; i < link_tbl->npages; ++i)
2312 if (link_tbl->pg_list[i].buf)
2313 dma_free_coherent(dev, link_tbl->pg_sz,
2314 link_tbl->pg_list[i].buf,
2315 link_tbl->pg_list[i].map);
2316 kfree(link_tbl->pg_list);
2317
2318 dma_free_coherent(dev, size, link_tbl->table.buf,
2319 link_tbl->table.map);
2320}
2321
2322static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2323{
ded58ff9 2324 struct hns_roce_v2_priv *priv = hr_dev->priv;
0e40dc2f
YL		 2325 int qpc_count, cqc_count;
2326 int ret, i;
6b63597d 2327
2328 /* TSQ includes SQ doorbell and ack doorbell */
2329 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 2330 if (ret) {
6b63597d 2331 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 2332 return ret;
2333 }
2334
2335 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
2336 if (ret) {
2337 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
2338 goto err_tpq_init_failed;
2339 }
2340
6def7de6 2341 /* Alloc memory for QPC Timer buffer space chunk */
0e40dc2f
YL		 2342 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2343 qpc_count++) {
2344 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2345 qpc_count);
2346 if (ret) {
2347 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2348 goto err_qpc_timer_failed;
2349 }
2350 }
2351
6def7de6 2352 /* Alloc memory for CQC Timer buffer space chunk */
0e40dc2f
YL		 2353 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2354 cqc_count++) {
2355 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2356 cqc_count);
2357 if (ret) {
2358 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2359 goto err_cqc_timer_failed;
2360 }
2361 }
2362
ded58ff9 2363 return 0;
2364
0e40dc2f
YL		 2365err_cqc_timer_failed:
2366 for (i = 0; i < cqc_count; i++)
2367 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2368
2369err_qpc_timer_failed:
2370 for (i = 0; i < qpc_count; i++)
2371 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2372
2373 hns_roce_free_link_table(hr_dev, &priv->tpq);
2374
ded58ff9 2375err_tpq_init_failed:
2376 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 2377
2378 return ret;
2379}
2380
2381static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2382{
2383 struct hns_roce_v2_priv *priv = hr_dev->priv;
2384
a247fd28 2385 hns_roce_function_clear(hr_dev);
89a6da3c 2386
ded58ff9 2387 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 2388 hns_roce_free_link_table(hr_dev, &priv->tsq);
2389}
2390
f747b689
LO		 2391static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
2392{
2393 struct hns_roce_cmq_desc desc;
2394 struct hns_roce_mbox_status *mb_st =
2395 (struct hns_roce_mbox_status *)desc.data;
2396 enum hns_roce_cmd_return_status status;
2397
2398 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
2399
2400 status = hns_roce_cmq_send(hr_dev, &desc, 1);
2401 if (status)
2402 return status;
2403
bfe86035 2404 return le32_to_cpu(mb_st->mb_status_hw_run);
f747b689
LO		 2405}
2406
a680f2f3
WHX		 2407static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
2408{
f747b689 2409 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2410
2411 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
2412}
2413
2414static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
2415{
f747b689 2416 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2417
2418 return status & HNS_ROCE_HW_MB_STATUS_MASK;
2419}
2420
f747b689
LO		 2421static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
2422 u64 out_param, u32 in_modifier, u8 op_modifier,
2423 u16 op, u16 token, int event)
2424{
2425 struct hns_roce_cmq_desc desc;
2426 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2427
2428 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2429
bfe86035
LC		 2430 mb->in_param_l = cpu_to_le32(in_param);
2431 mb->in_param_h = cpu_to_le32(in_param >> 32);
2432 mb->out_param_l = cpu_to_le32(out_param);
2433 mb->out_param_h = cpu_to_le32(out_param >> 32);
f747b689
LO		 2434 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
2435 mb->token_event_en = cpu_to_le32(event << 16 | token);
2436
2437 return hns_roce_cmq_send(hr_dev, &desc, 1);
2438}
2439
a680f2f3
WHX		 2440static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
2441 u64 out_param, u32 in_modifier, u8 op_modifier,
2442 u16 op, u16 token, int event)
2443{
2444 struct device *dev = hr_dev->dev;
a680f2f3 2445 unsigned long end;
f747b689 2446 int ret;
a680f2f3
WHX		 2447
2448 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
2449 while (hns_roce_v2_cmd_pending(hr_dev)) {
2450 if (time_after(jiffies, end)) {
2451 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
2452 (int)end);
2453 return -EAGAIN;
2454 }
2455 cond_resched();
2456 }
2457
f747b689
LO		 2458 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
2459 op_modifier, op, token, event);
2460 if (ret)
2461 dev_err(dev, "Post mailbox fail(%d)\n", ret);
a680f2f3 2462
f747b689 2463 return ret;
a680f2f3
WHX		 2464}
2465
2466static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
2467 unsigned long timeout)
2468{
2469 struct device *dev = hr_dev->dev;
617cf24f 2470 unsigned long end;
a680f2f3
WHX		 2471 u32 status;
2472
2473 end = msecs_to_jiffies(timeout) + jiffies;
2474 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
2475 cond_resched();
2476
2477 if (hns_roce_v2_cmd_pending(hr_dev)) {
2478 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
2479 return -ETIMEDOUT;
2480 }
2481
2482 status = hns_roce_v2_cmd_complete(hr_dev);
2483 if (status != 0x1) {
6a04aed6
WHX		 2484 if (status == CMD_RST_PRC_EBUSY)
2485 return status;
2486
a680f2f3
WHX		 2487 dev_err(dev, "mailbox status 0x%x!\n", status);
2488 return -EBUSY;
2489 }
2490
2491 return 0;
2492}
2493
4db134a3 2494static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
2495 int gid_index, const union ib_gid *gid,
2496 enum hns_roce_sgid_type sgid_type)
2497{
2498 struct hns_roce_cmq_desc desc;
2499 struct hns_roce_cfg_sgid_tb *sgid_tb =
2500 (struct hns_roce_cfg_sgid_tb *)desc.data;
2501 u32 *p;
2502
2503 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2504
60262b10 2505 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M,
4db134a3 2506 CFG_SGID_TB_TABLE_IDX_S, gid_index);
60262b10 2507 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M,
4db134a3 2508 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2509
2510 p = (u32 *)&gid->raw[0];
2511 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
2512
2513 p = (u32 *)&gid->raw[4];
2514 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
2515
2516 p = (u32 *)&gid->raw[8];
2517 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
2518
2519 p = (u32 *)&gid->raw[0xc];
2520 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
2521
2522 return hns_roce_cmq_send(hr_dev, &desc, 1);
2523}
2524
b5ff0f61 2525static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 2526 int gid_index, const union ib_gid *gid,
b5ff0f61 2527 const struct ib_gid_attr *attr)
7afddafa 2528{
b5ff0f61 2529 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 2530 int ret;
7afddafa 2531
b5ff0f61
WHX		 2532 if (!gid || !attr)
2533 return -EINVAL;
2534
2535 if (attr->gid_type == IB_GID_TYPE_ROCE)
2536 sgid_type = GID_TYPE_FLAG_ROCE_V1;
2537
2538 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2539 if (ipv6_addr_v4mapped((void *)gid))
2540 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
2541 else
2542 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
2543 }
2544
4db134a3 2545 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
2546 if (ret)
ae1c6148
LO		 2547 ibdev_err(&hr_dev->ib_dev,
2548 "failed to configure sgid table, ret = %d!\n",
2549 ret);
b5ff0f61 2550
4db134a3 2551 return ret;
7afddafa
WHX		 2552}
2553
a74dc41d
WHX		 2554static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
2555 u8 *addr)
7afddafa 2556{
e8e8b652 2557 struct hns_roce_cmq_desc desc;
2558 struct hns_roce_cfg_smac_tb *smac_tb =
2559 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 2560 u16 reg_smac_h;
2561 u32 reg_smac_l;
e8e8b652 2562
2563 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 2564
2565 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 2566 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 2567
375898e8 2568 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M,
e8e8b652 2569 CFG_SMAC_TB_IDX_S, phy_port);
375898e8 2570 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M,
e8e8b652 2571 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
bfe86035 2572 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
a74dc41d 2573
e8e8b652 2574 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 2575}
2576
98a61519
YL		 2577static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
2578 struct hns_roce_v2_mpt_entry *mpt_entry,
ca088320 2579 struct hns_roce_mr *mr)
3958cc56 2580{
9b2cf76c
XW		 2581 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
2582 struct ib_device *ibdev = &hr_dev->ib_dev;
2583 dma_addr_t pbl_ba;
2584 int i, count;
2585
2586 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
2587 ARRAY_SIZE(pages), &pbl_ba);
2588 if (count < 1) {
2589 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
2590 count);
2591 return -ENOBUFS;
2592 }
3958cc56 2593
9b2cf76c
XW		 2594 /* Aligned to the hardware address access unit */
2595 for (i = 0; i < count; i++)
2596 pages[i] >>= 6;
2597
2598 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
2599 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
ca088320
YL		 2600 roce_set_field(mpt_entry->byte_48_mode_ba,
2601 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
9b2cf76c 2602 upper_32_bits(pbl_ba >> 3));
ca088320 2603
ca088320
YL		 2604 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
2605 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
2606 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
2607
2608 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
2609 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
2610 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
2611 roce_set_field(mpt_entry->byte_64_buf_pa1,
2612 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2613 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
9b2cf76c 2614 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
ca088320
YL		 2615
2616 return 0;
2617}
2618
98a61519
YL		 2619static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
2620 void *mb_buf, struct hns_roce_mr *mr,
ca088320
YL		 2621 unsigned long mtpt_idx)
2622{
2623 struct hns_roce_v2_mpt_entry *mpt_entry;
2624 int ret;
2625
3958cc56
WHX		 2626 mpt_entry = mb_buf;
2627 memset(mpt_entry, 0, sizeof(*mpt_entry));
2628
2629 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2630 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2631 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2632 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
2633 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
2634 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2635 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db 2636 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
9b2cf76c 2637 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3958cc56
WHX		 2638 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2639 V2_MPT_BYTE_4_PD_S, mr->pd);
3958cc56
WHX		 2640
2641 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
82342e49 2642 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0);
e93df010 2643 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 2644 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
2645 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 2646 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
2647 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 2648 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2649 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
2650 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2651 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
2652 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2653 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
3958cc56
WHX		 2654
2655 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
2656 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 2657 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
2658 1);
3958cc56
WHX		 2659
2660 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
2661 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
2662 mpt_entry->lkey = cpu_to_le32(mr->key);
2663 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
2664 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
2665
2666 if (mr->type == MR_TYPE_DMA)
2667 return 0;
2668
98a61519 2669 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3958cc56 2670
ca088320 2671 return ret;
3958cc56
WHX		 2672}
2673
a2c80b7b
WHX		 2674static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
2675 struct hns_roce_mr *mr, int flags,
2676 u32 pdn, int mr_access_flags, u64 iova,
2677 u64 size, void *mb_buf)
2678{
2679 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
ca088320 2680 int ret = 0;
a2c80b7b 2681
ab22bf05
YL		 2682 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2683 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2684
a2c80b7b
WHX		 2685 if (flags & IB_MR_REREG_PD) {
2686 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2687 V2_MPT_BYTE_4_PD_S, pdn);
2688 mr->pd = pdn;
2689 }
2690
2691 if (flags & IB_MR_REREG_ACCESS) {
2692 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2693 V2_MPT_BYTE_8_BIND_EN_S,
2694 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
2695 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
ca088320
YL		 2696 V2_MPT_BYTE_8_ATOMIC_EN_S,
2697 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
a2c80b7b 2698 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
ca088320 2699 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
a2c80b7b 2700 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
ca088320 2701 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
a2c80b7b 2702 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
ca088320 2703 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
a2c80b7b
WHX		 2704 }
2705
2706 if (flags & IB_MR_REREG_TRANS) {
2707 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
2708 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
2709 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
2710 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
2711
a2c80b7b
WHX		 2712 mr->iova = iova;
2713 mr->size = size;
ca088320 2714
98a61519 2715 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
a2c80b7b
WHX		 2716 }
2717
ca088320 2718 return ret;
a2c80b7b
WHX		 2719}
2720
98a61519
YL		 2721static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
2722 void *mb_buf, struct hns_roce_mr *mr)
68a997c5 2723{
9b2cf76c 2724 struct ib_device *ibdev = &hr_dev->ib_dev;
68a997c5 2725 struct hns_roce_v2_mpt_entry *mpt_entry;
9b2cf76c 2726 dma_addr_t pbl_ba = 0;
68a997c5
YL		 2727
2728 mpt_entry = mb_buf;
2729 memset(mpt_entry, 0, sizeof(*mpt_entry));
2730
9b2cf76c
XW		 2731 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
2732 ibdev_err(ibdev, "failed to find frmr mtr.\n");
2733 return -ENOBUFS;
2734 }
2735
68a997c5
YL		 2736 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2737 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2738 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2739 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
2740 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2741 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2742 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
9b2cf76c 2743 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
68a997c5
YL		 2744 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2745 V2_MPT_BYTE_4_PD_S, mr->pd);
2746
2747 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
2748 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2749 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2750
2751 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
2752 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2753 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
2754 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2755
9b2cf76c 2756 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
68a997c5 2757
9b2cf76c 2758 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
68a997c5
YL		 2759 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
2760 V2_MPT_BYTE_48_PBL_BA_H_S,
9b2cf76c 2761 upper_32_bits(pbl_ba >> 3));
68a997c5
YL		 2762
2763 roce_set_field(mpt_entry->byte_64_buf_pa1,
2764 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2765 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
9b2cf76c 2766 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
68a997c5
YL		 2767
2768 return 0;
2769}
2770
c7c28191
YL		 2771static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
2772{
2773 struct hns_roce_v2_mpt_entry *mpt_entry;
2774
2775 mpt_entry = mb_buf;
2776 memset(mpt_entry, 0, sizeof(*mpt_entry));
2777
2778 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2779 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2780 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2781 V2_MPT_BYTE_4_PD_S, mw->pdn);
60262b10 2782 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
c7c28191 2783 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
60262b10
LO		 2784 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
2785 mw->pbl_hop_num);
c7c28191
YL		 2786 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2787 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2788 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2789 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2790
2791 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2792 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2793
2794 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2795 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
2796 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2797 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
2798 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2799
2800 roce_set_field(mpt_entry->byte_64_buf_pa1,
2801 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2802 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2803 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2804
2805 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2806
2807 return 0;
2808}
2809
93aa2187
WHX		 2810static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2811{
09a5f210 2812 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * hr_cq->cqe_size);
93aa2187
WHX		 2813}
2814
2815static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2816{
2817 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2818
2819 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2820 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
e2b2744a 2821 !!(n & hr_cq->cq_depth)) ? cqe : NULL;
93aa2187
WHX		 2822}
2823
e4aaf4ba 2824static inline void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 ci)
93aa2187 2825{
e4aaf4ba 2826 *hr_cq->set_ci_db = ci & V2_CQ_DB_PARAMETER_CONS_IDX_M;
93aa2187
WHX		 2827}
2828
926a01dc
WHX		 2829static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2830 struct hns_roce_srq *srq)
2831{
2832 struct hns_roce_v2_cqe *cqe, *dest;
2833 u32 prod_index;
2834 int nfreed = 0;
c7bcb134 2835 int wqe_index;
926a01dc
WHX		 2836 u8 owner_bit;
2837
2838 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2839 ++prod_index) {
d7e5ca88 2840 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
926a01dc
WHX		 2841 break;
2842 }
2843
2844 /*
2845 * Now backwards through the CQ, removing CQ entries
2846 * that match our QP by overwriting them with next entries.
2847 */
2848 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2849 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2850 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2851 V2_CQE_BYTE_16_LCL_QPN_S) &
2852 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
c7bcb134
LO		 2853 if (srq &&
2854 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) {
2855 wqe_index = roce_get_field(cqe->byte_4,
2856 V2_CQE_BYTE_4_WQE_INDX_M,
2857 V2_CQE_BYTE_4_WQE_INDX_S);
2858 hns_roce_free_srq_wqe(srq, wqe_index);
2859 }
926a01dc
WHX		 2860 ++nfreed;
2861 } else if (nfreed) {
2862 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2863 hr_cq->ib_cq.cqe);
2864 owner_bit = roce_get_bit(dest->byte_4,
2865 V2_CQE_BYTE_4_OWNER_S);
2866 memcpy(dest, cqe, sizeof(*cqe));
2867 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2868 owner_bit);
2869 }
2870 }
2871
2872 if (nfreed) {
2873 hr_cq->cons_index += nfreed;
2874 /*
2875 * Make sure update of buffer contents is done before
2876 * updating consumer index.
2877 */
2878 wmb();
2879 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2880 }
2881}
2882
2883static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2884 struct hns_roce_srq *srq)
2885{
2886 spin_lock_irq(&hr_cq->lock);
2887 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2888 spin_unlock_irq(&hr_cq->lock);
2889}
2890
93aa2187
WHX		 2891static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2892 struct hns_roce_cq *hr_cq, void *mb_buf,
e2b2744a 2893 u64 *mtts, dma_addr_t dma_handle)
93aa2187
WHX		 2894{
2895 struct hns_roce_v2_cq_context *cq_context;
2896
2897 cq_context = mb_buf;
2898 memset(cq_context, 0, sizeof(*cq_context));
2899
2900 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2901 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2902 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2903 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187 2904 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
60262b10 2905 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth));
93aa2187 2906 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
e2b2744a 2907 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector);
93aa2187
WHX		 2908
2909 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2910 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2911
09a5f210
WL		 2912 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQE_SIZE_M,
2913 V2_CQC_BYTE_8_CQE_SIZE_S, hr_cq->cqe_size ==
2914 HNS_ROCE_V3_CQE_SIZE ? 1 : 0);
2915
744b7bdf 2916 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
93aa2187
WHX		 2917
2918 roce_set_field(cq_context->byte_16_hop_addr,
2919 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2920 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
744b7bdf 2921 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
93aa2187
WHX		 2922 roce_set_field(cq_context->byte_16_hop_addr,
2923 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2924 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2925 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2926
744b7bdf 2927 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
93aa2187
WHX		 2928 roce_set_field(cq_context->byte_24_pgsz_addr,
2929 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2930 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
744b7bdf 2931 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
93aa2187
WHX		 2932 roce_set_field(cq_context->byte_24_pgsz_addr,
2933 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2934 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
744b7bdf 2935 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
93aa2187
WHX		 2936 roce_set_field(cq_context->byte_24_pgsz_addr,
2937 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2938 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
744b7bdf 2939 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
93aa2187 2940
bfe86035 2941 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3);
93aa2187
WHX		 2942
2943 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2944 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2945
05e6a5a6
LC		 2946 roce_set_bit(cq_context->byte_44_db_record,
2947 V2_CQC_BYTE_44_DB_RECORD_EN_S,
2948 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0);
9b44703d
YL		 2949
2950 roce_set_field(cq_context->byte_44_db_record,
2951 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2952 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2953 ((u32)hr_cq->db.dma) >> 1);
bfe86035 2954 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32);
9b44703d 2955
a5073d60
YL		 2956 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2957 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2958 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2959 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2960 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2961 V2_CQC_BYTE_56_CQ_PERIOD_M,
2962 V2_CQC_BYTE_56_CQ_PERIOD_S,
2963 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2964}
2965
2966static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2967 enum ib_cq_notify_flags flags)
2968{
d3743fa9 2969 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 2970 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2971 u32 notification_flag;
bfe86035 2972 __le32 doorbell[2];
93aa2187
WHX		 2973
2974 doorbell[0] = 0;
2975 doorbell[1] = 0;
2976
2977 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2978 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2979 /*
2980 * flags = 0; Notification Flag = 1, next
2981 * flags = 1; Notification Flag = 0, solocited
2982 */
2983 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2984 hr_cq->cqn);
2985 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2986 HNS_ROCE_V2_CQ_DB_NTR);
2987 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
25966e89 2988 V2_CQ_DB_PARAMETER_CONS_IDX_S, hr_cq->cons_index);
93aa2187 2989 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2990 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2991 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2992 notification_flag);
2993
d3743fa9 2994 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l);
93aa2187
WHX		 2995
2996 return 0;
2997}
2998
0009c2db 2999static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
3000 struct hns_roce_qp **cur_qp,
3001 struct ib_wc *wc)
3002{
3003 struct hns_roce_rinl_sge *sge_list;
3004 u32 wr_num, wr_cnt, sge_num;
3005 u32 sge_cnt, data_len, size;
3006 void *wqe_buf;
3007
3008 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
3009 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
3010 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
3011
3012 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
3013 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
6c6e3921 3014 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt);
0009c2db 3015 data_len = wc->byte_len;
3016
3017 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
3018 size = min(sge_list[sge_cnt].len, data_len);
3019 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
3020
3021 data_len -= size;
3022 wqe_buf += size;
3023 }
3024
0db65709 3025 if (unlikely(data_len)) {
0009c2db 3026 wc->status = IB_WC_LOC_LEN_ERR;
3027 return -EAGAIN;
3028 }
3029
3030 return 0;
3031}
3032
626903e9
XW		 3033static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
3034 int num_entries, struct ib_wc *wc)
3035{
3036 unsigned int left;
3037 int npolled = 0;
3038
3039 left = wq->head - wq->tail;
3040 if (left == 0)
3041 return 0;
3042
3043 left = min_t(unsigned int, (unsigned int)num_entries, left);
3044 while (npolled < left) {
3045 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3046 wc->status = IB_WC_WR_FLUSH_ERR;
3047 wc->vendor_err = 0;
3048 wc->qp = &hr_qp->ibqp;
3049
3050 wq->tail++;
3051 wc++;
3052 npolled++;
3053 }
3054
3055 return npolled;
3056}
3057
3058static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3059 struct ib_wc *wc)
3060{
3061 struct hns_roce_qp *hr_qp;
3062 int npolled = 0;
3063
3064 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3065 npolled += sw_comp(hr_qp, &hr_qp->sq,
3066 num_entries - npolled, wc + npolled);
3067 if (npolled >= num_entries)
3068 goto out;
3069 }
3070
3071 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3072 npolled += sw_comp(hr_qp, &hr_qp->rq,
3073 num_entries - npolled, wc + npolled);
3074 if (npolled >= num_entries)
3075 goto out;
3076 }
3077
3078out:
3079 return npolled;
3080}
3081
7c044adc 3082static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
09a5f210
WL		 3083 struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe,
3084 struct ib_wc *wc)
7c044adc
LC		 3085{
3086 static const struct {
3087 u32 cqe_status;
3088 enum ib_wc_status wc_status;
3089 } map[] = {
3090 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3091 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3092 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3093 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3094 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3095 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3096 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3097 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3098 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3099 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3100 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3101 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3102 IB_WC_RETRY_EXC_ERR },
3103 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3104 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
395f2e8f 3105 { HNS_ROCE_CQE_V2_GENERAL_ERR, IB_WC_GENERAL_ERR}
7c044adc
LC		 3106 };
3107
3108 u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
3109 V2_CQE_BYTE_4_STATUS_S);
3110 int i;
3111
3112 wc->status = IB_WC_GENERAL_ERR;
3113 for (i = 0; i < ARRAY_SIZE(map); i++)
3114 if (cqe_status == map[i].cqe_status) {
3115 wc->status = map[i].wc_status;
3116 break;
3117 }
3118
0db65709
LC		 3119 if (likely(wc->status == IB_WC_SUCCESS ||
3120 wc->status == IB_WC_WR_FLUSH_ERR))
7c044adc
LC		 3121 return;
3122
3123 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3124 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
09a5f210 3125 cq->cqe_size, false);
7c044adc 3126
395f2e8f
XW		 3127 /*
3128 * For hns ROCEE, GENERAL_ERR is an error type that is not defined in
3129 * the standard protocol, the driver must ignore it and needn't to set
3130 * the QP to an error state.
3131 */
3132 if (cqe_status == HNS_ROCE_CQE_V2_GENERAL_ERR)
3133 return;
3134
7c044adc
LC		 3135 /*
3136 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets
3137 * into errored mode. Hence, as a workaround to this hardware
3138 * limitation, driver needs to assist in flushing. But the flushing
3139 * operation uses mailbox to convey the QP state to the hardware and
3140 * which can sleep due to the mutex protection around the mailbox calls.
3141 * Hence, use the deferred flush for now. Once wc error detected, the
3142 * flushing operation is needed.
3143 */
3144 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
3145 init_flush_work(hr_dev, qp);
3146}
3147
93aa2187
WHX		 3148static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3149 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3150{
b5374286 3151 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
c7bcb134 3152 struct hns_roce_srq *srq = NULL;
93aa2187
WHX		 3153 struct hns_roce_v2_cqe *cqe;
3154 struct hns_roce_qp *hr_qp;
3155 struct hns_roce_wq *wq;
3156 int is_send;
3157 u16 wqe_ctr;
3158 u32 opcode;
93aa2187 3159 int qpn;
0009c2db 3160 int ret;
93aa2187
WHX		 3161
3162 /* Find cqe according to consumer index */
e4aaf4ba 3163 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
93aa2187
WHX		 3164 if (!cqe)
3165 return -EAGAIN;
3166
3167 ++hr_cq->cons_index;
3168 /* Memory barrier */
3169 rmb();
3170
3171 /* 0->SQ, 1->RQ */
3172 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
3173
3174 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
3175 V2_CQE_BYTE_16_LCL_QPN_S);
3176
3177 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
93aa2187
WHX		 3178 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3179 if (unlikely(!hr_qp)) {
ae1c6148
LO		 3180 ibdev_err(&hr_dev->ib_dev,
3181 "CQ %06lx with entry for unknown QPN %06x\n",
3182 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK);
93aa2187
WHX		 3183 return -EINVAL;
3184 }
3185 *cur_qp = hr_qp;
3186 }
3187
3188 wc->qp = &(*cur_qp)->ibqp;
3189 wc->vendor_err = 0;
3190
c7bcb134
LO		 3191 if (is_send) {
3192 wq = &(*cur_qp)->sq;
3193 if ((*cur_qp)->sq_signal_bits) {
3194 /*
3195 * If sg_signal_bit is 1,
3196 * firstly tail pointer updated to wqe
3197 * which current cqe correspond to
3198 */
3199 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3200 V2_CQE_BYTE_4_WQE_INDX_M,
3201 V2_CQE_BYTE_4_WQE_INDX_S);
3202 wq->tail += (wqe_ctr - (u16)wq->tail) &
3203 (wq->wqe_cnt - 1);
3204 }
3205
3206 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3207 ++wq->tail;
3208 } else if ((*cur_qp)->ibqp.srq) {
3209 srq = to_hr_srq((*cur_qp)->ibqp.srq);
bfe86035
LC		 3210 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3211 V2_CQE_BYTE_4_WQE_INDX_M,
3212 V2_CQE_BYTE_4_WQE_INDX_S);
c7bcb134
LO		 3213 wc->wr_id = srq->wrid[wqe_ctr];
3214 hns_roce_free_srq_wqe(srq, wqe_ctr);
3215 } else {
3216 /* Update tail pointer, record wr_id */
3217 wq = &(*cur_qp)->rq;
3218 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3219 ++wq->tail;
3220 }
3221
09a5f210 3222 get_cqe_status(hr_dev, *cur_qp, hr_cq, cqe, wc);
0db65709 3223 if (unlikely(wc->status != IB_WC_SUCCESS))
93aa2187
WHX		 3224 return 0;
3225
3226 if (is_send) {
3227 wc->wc_flags = 0;
3228 /* SQ corresponding to CQE */
3229 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3230 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
57005c96 3231 case HNS_ROCE_V2_WQE_OP_SEND:
93aa2187
WHX		 3232 wc->opcode = IB_WC_SEND;
3233 break;
57005c96 3234 case HNS_ROCE_V2_WQE_OP_SEND_WITH_INV:
93aa2187
WHX		 3235 wc->opcode = IB_WC_SEND;
3236 break;
57005c96 3237 case HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM:
93aa2187
WHX		 3238 wc->opcode = IB_WC_SEND;
3239 wc->wc_flags |= IB_WC_WITH_IMM;
3240 break;
57005c96 3241 case HNS_ROCE_V2_WQE_OP_RDMA_READ:
93aa2187
WHX		 3242 wc->opcode = IB_WC_RDMA_READ;
3243 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3244 break;
57005c96 3245 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE:
93aa2187
WHX		 3246 wc->opcode = IB_WC_RDMA_WRITE;
3247 break;
57005c96 3248 case HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM:
93aa2187
WHX		 3249 wc->opcode = IB_WC_RDMA_WRITE;
3250 wc->wc_flags |= IB_WC_WITH_IMM;
3251 break;
57005c96 3252 case HNS_ROCE_V2_WQE_OP_LOCAL_INV:
93aa2187
WHX		 3253 wc->opcode = IB_WC_LOCAL_INV;
3254 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3255 break;
57005c96 3256 case HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP:
93aa2187
WHX		 3257 wc->opcode = IB_WC_COMP_SWAP;
3258 wc->byte_len = 8;
3259 break;
57005c96 3260 case HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD:
93aa2187
WHX		 3261 wc->opcode = IB_WC_FETCH_ADD;
3262 wc->byte_len = 8;
3263 break;
57005c96 3264 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP:
93aa2187
WHX		 3265 wc->opcode = IB_WC_MASKED_COMP_SWAP;
3266 wc->byte_len = 8;
3267 break;
57005c96 3268 case HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD:
93aa2187
WHX		 3269 wc->opcode = IB_WC_MASKED_FETCH_ADD;
3270 wc->byte_len = 8;
3271 break;
57005c96 3272 case HNS_ROCE_V2_WQE_OP_FAST_REG_PMR:
93aa2187
WHX		 3273 wc->opcode = IB_WC_REG_MR;
3274 break;
57005c96 3275 case HNS_ROCE_V2_WQE_OP_BIND_MW:
93aa2187
WHX		 3276 wc->opcode = IB_WC_REG_MR;
3277 break;
3278 default:
3279 wc->status = IB_WC_GENERAL_ERR;
3280 break;
3281 }
93aa2187
WHX		 3282 } else {
3283 /* RQ correspond to CQE */
3284 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3285
3286 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3287 V2_CQE_BYTE_4_OPCODE_S);
3288 switch (opcode & 0x1f) {
3289 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3290 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3291 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3292 wc->ex.imm_data =
3293 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3294 break;
3295 case HNS_ROCE_V2_OPCODE_SEND:
3296 wc->opcode = IB_WC_RECV;
3297 wc->wc_flags = 0;
3298 break;
3299 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3300 wc->opcode = IB_WC_RECV;
3301 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3302 wc->ex.imm_data =
3303 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3304 break;
3305 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3306 wc->opcode = IB_WC_RECV;
3307 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 3308 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 3309 break;
3310 default:
3311 wc->status = IB_WC_GENERAL_ERR;
3312 break;
3313 }
3314
0009c2db 3315 if ((wc->qp->qp_type == IB_QPT_RC ||
3316 wc->qp->qp_type == IB_QPT_UC) &&
3317 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
3318 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3319 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3320 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
3321 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
0db65709 3322 if (unlikely(ret))
0009c2db 3323 return -EAGAIN;
3324 }
3325
93aa2187
WHX		 3326 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
3327 V2_CQE_BYTE_32_SL_S);
3328 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
3329 V2_CQE_BYTE_32_RMT_QPN_M,
3330 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 3331 wc->slid = 0;
93aa2187
WHX		 3332 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
3333 V2_CQE_BYTE_32_GRH_S) ?
3334 IB_WC_GRH : 0);
6c1f08b3 3335 wc->port_num = roce_get_field(cqe->byte_32,
3336 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
3337 wc->pkey_index = 0;
cd4a70bb 3338
944e6409
LO		 3339 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
3340 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
3341 V2_CQE_BYTE_28_VID_M,
3342 V2_CQE_BYTE_28_VID_S);
0e1aa6f0 3343 wc->wc_flags |= IB_WC_WITH_VLAN;
944e6409
LO		 3344 } else {
3345 wc->vlan_id = 0xffff;
3346 }
3347
2eade675 3348 wc->network_hdr_type = roce_get_field(cqe->byte_28,
3349 V2_CQE_BYTE_28_PORT_TYPE_M,
3350 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 3351 }
3352
3353 return 0;
3354}
3355
3356static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3357 struct ib_wc *wc)
3358{
626903e9 3359 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 3360 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3361 struct hns_roce_qp *cur_qp = NULL;
3362 unsigned long flags;
3363 int npolled;
3364
3365 spin_lock_irqsave(&hr_cq->lock, flags);
3366
626903e9
XW		 3367 /*
3368 * When the device starts to reset, the state is RST_DOWN. At this time,
3369 * there may still be some valid CQEs in the hardware that are not
3370 * polled. Therefore, it is not allowed to switch to the software mode
3371 * immediately. When the state changes to UNINIT, CQE no longer exists
3372 * in the hardware, and then switch to software mode.
3373 */
3374 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3375 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3376 goto out;
3377 }
3378
93aa2187
WHX		 3379 for (npolled = 0; npolled < num_entries; ++npolled) {
3380 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3381 break;
3382 }
3383
3384 if (npolled) {
3385 /* Memory barrier */
3386 wmb();
3387 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
3388 }
3389
626903e9 3390out:
93aa2187
WHX		 3391 spin_unlock_irqrestore(&hr_cq->lock, flags);
3392
3393 return npolled;
3394}
3395
260c3b34
YL		 3396static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3397 int step_idx)
3398{
3399 int op;
3400
3401 if (type == HEM_TYPE_SCCC && step_idx)
3402 return -EINVAL;
3403
3404 switch (type) {
3405 case HEM_TYPE_QPC:
3406 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
3407 break;
3408 case HEM_TYPE_MTPT:
3409 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
3410 break;
3411 case HEM_TYPE_CQC:
3412 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
3413 break;
3414 case HEM_TYPE_SRQC:
3415 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3416 break;
3417 case HEM_TYPE_SCCC:
3418 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3419 break;
3420 case HEM_TYPE_QPC_TIMER:
3421 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3422 break;
3423 case HEM_TYPE_CQC_TIMER:
3424 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3425 break;
3426 default:
3427 dev_warn(hr_dev->dev,
3428 "Table %d not to be written by mailbox!\n", type);
3429 return -EINVAL;
3430 }
3431
3432 return op + step_idx;
3433}
3434
cdc1f3e9
WL		 3435static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, u64 bt_ba,
3436 u32 hem_type, int step_idx)
3437{
3438 struct hns_roce_cmd_mailbox *mailbox;
3439 int ret;
3440 int op;
3441
3442 op = get_op_for_set_hem(hr_dev, hem_type, step_idx);
3443 if (op < 0)
3444 return 0;
3445
3446 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3447 if (IS_ERR(mailbox))
3448 return PTR_ERR(mailbox);
3449
3450 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
3451 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
3452
3453 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3454
3455 return ret;
3456}
3457
a81fba28
WHX		 3458static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
3459 struct hns_roce_hem_table *table, int obj,
3460 int step_idx)
3461{
a81fba28
WHX		 3462 struct hns_roce_hem_iter iter;
3463 struct hns_roce_hem_mhop mhop;
3464 struct hns_roce_hem *hem;
3465 unsigned long mhop_obj = obj;
3466 int i, j, k;
3467 int ret = 0;
3468 u64 hem_idx = 0;
3469 u64 l1_idx = 0;
3470 u64 bt_ba = 0;
3471 u32 chunk_ba_num;
3472 u32 hop_num;
a81fba28
WHX		 3473
3474 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3475 return 0;
3476
3477 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
3478 i = mhop.l0_idx;
3479 j = mhop.l1_idx;
3480 k = mhop.l2_idx;
3481 hop_num = mhop.hop_num;
3482 chunk_ba_num = mhop.bt_chunk_size / 8;
3483
3484 if (hop_num == 2) {
3485 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
3486 k;
3487 l1_idx = i * chunk_ba_num + j;
3488 } else if (hop_num == 1) {
3489 hem_idx = i * chunk_ba_num + j;
3490 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
3491 hem_idx = i;
3492 }
3493
6ac16e40
YL		 3494 if (table->type == HEM_TYPE_SCCC)
3495 obj = mhop.l0_idx;
3496
a81fba28
WHX		 3497 if (check_whether_last_step(hop_num, step_idx)) {
3498 hem = table->hem[hem_idx];
3499 for (hns_roce_hem_first(hem, &iter);
3500 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
3501 bt_ba = hns_roce_hem_addr(&iter);
cdc1f3e9
WL		 3502 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type,
3503 step_idx);
a81fba28
WHX		 3504 }
3505 } else {
3506 if (step_idx == 0)
3507 bt_ba = table->bt_l0_dma_addr[i];
3508 else if (step_idx == 1 && hop_num == 2)
3509 bt_ba = table->bt_l1_dma_addr[l1_idx];
3510
cdc1f3e9 3511 ret = set_hem_to_hw(hr_dev, obj, bt_ba, table->type, step_idx);
a81fba28
WHX		 3512 }
3513
a81fba28
WHX		 3514 return ret;
3515}
3516
3517static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
3518 struct hns_roce_hem_table *table, int obj,
3519 int step_idx)
3520{
3521 struct device *dev = hr_dev->dev;
3522 struct hns_roce_cmd_mailbox *mailbox;
617cf24f 3523 int ret;
a81fba28
WHX		 3524 u16 op = 0xff;
3525
3526 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3527 return 0;
3528
3529 switch (table->type) {
3530 case HEM_TYPE_QPC:
3531 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
3532 break;
3533 case HEM_TYPE_MTPT:
3534 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
3535 break;
3536 case HEM_TYPE_CQC:
3537 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
3538 break;
6a157f7d 3539 case HEM_TYPE_SCCC:
0e40dc2f
YL		 3540 case HEM_TYPE_QPC_TIMER:
3541 case HEM_TYPE_CQC_TIMER:
6a157f7d 3542 break;
a81fba28
WHX		 3543 case HEM_TYPE_SRQC:
3544 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
3545 break;
3546 default:
3547 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
3548 table->type);
3549 return 0;
3550 }
6a157f7d 3551
0e40dc2f
YL		 3552 if (table->type == HEM_TYPE_SCCC ||
3553 table->type == HEM_TYPE_QPC_TIMER ||
3554 table->type == HEM_TYPE_CQC_TIMER)
6a157f7d
YL		 3555 return 0;
3556
a81fba28
WHX		 3557 op += step_idx;
3558
3559 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3560 if (IS_ERR(mailbox))
3561 return PTR_ERR(mailbox);
3562
3563 /* configure the tag and op */
3564 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3565 HNS_ROCE_CMD_TIMEOUT_MSECS);
3566
3567 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3568 return ret;
3569}
3570
926a01dc 3571static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
926a01dc 3572 struct hns_roce_v2_qp_context *context,
98912ee8 3573 struct hns_roce_v2_qp_context *qpc_mask,
926a01dc
WHX		 3574 struct hns_roce_qp *hr_qp)
3575{
3576 struct hns_roce_cmd_mailbox *mailbox;
98912ee8 3577 int qpc_size;
926a01dc
WHX		 3578 int ret;
3579
3580 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3581 if (IS_ERR(mailbox))
3582 return PTR_ERR(mailbox);
3583
98912ee8
WL		 3584 /* The qpc size of HIP08 is only 256B, which is half of HIP09 */
3585 qpc_size = hr_dev->caps.qpc_sz;
3586 memcpy(mailbox->buf, context, qpc_size);
3587 memcpy(mailbox->buf + qpc_size, qpc_mask, qpc_size);
926a01dc
WHX		 3588
3589 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
3590 HNS_ROCE_CMD_MODIFY_QPC,
3591 HNS_ROCE_CMD_TIMEOUT_MSECS);
3592
3593 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3594
3595 return ret;
3596}
3597
ace1c541 3598static void set_access_flags(struct hns_roce_qp *hr_qp,
3599 struct hns_roce_v2_qp_context *context,
3600 struct hns_roce_v2_qp_context *qpc_mask,
3601 const struct ib_qp_attr *attr, int attr_mask)
3602{
3603 u8 dest_rd_atomic;
3604 u32 access_flags;
3605
c2799119 3606 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 3607 attr->max_dest_rd_atomic : hr_qp->resp_depth;
3608
c2799119 3609 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 3610 attr->qp_access_flags : hr_qp->atomic_rd_en;
3611
3612 if (!dest_rd_atomic)
3613 access_flags &= IB_ACCESS_REMOTE_WRITE;
3614
3615 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3616 !!(access_flags & IB_ACCESS_REMOTE_READ));
3617 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
3618
3619 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3620 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3621 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
3622
3623 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3624 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3625 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
7db82697
JZ		 3626 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S,
3627 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3628 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0);
ace1c541 3629}
3630
99441ab5
XW		 3631static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
3632 struct hns_roce_v2_qp_context *context,
3633 struct hns_roce_v2_qp_context *qpc_mask)
3634{
54d66387
XW		 3635 roce_set_field(context->byte_4_sqpn_tst,
3636 V2_QPC_BYTE_4_SGE_SHIFT_M, V2_QPC_BYTE_4_SGE_SHIFT_S,
3637 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
3638 hr_qp->sge.sge_shift));
99441ab5 3639
99441ab5
XW		 3640 roce_set_field(context->byte_20_smac_sgid_idx,
3641 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
54d66387 3642 ilog2(hr_qp->sq.wqe_cnt));
99441ab5
XW		 3643
3644 roce_set_field(context->byte_20_smac_sgid_idx,
3645 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
54d66387 3646 ilog2(hr_qp->rq.wqe_cnt));
99441ab5
XW		 3647}
3648
926a01dc
WHX		 3649static void modify_qp_reset_to_init(struct ib_qp *ibqp,
3650 const struct ib_qp_attr *attr,
0fa95a9a 3651 int attr_mask,
926a01dc
WHX		 3652 struct hns_roce_v2_qp_context *context,
3653 struct hns_roce_v2_qp_context *qpc_mask)
3654{
ecaaf1e2 3655 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 3656 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3657
3658 /*
3659 * In v2 engine, software pass context and context mask to hardware
3660 * when modifying qp. If software need modify some fields in context,
3661 * we should set all bits of the relevant fields in context mask to
3662 * 0 at the same time, else set them to 0x1.
3663 */
3664 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3665 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
926a01dc 3666
926a01dc
WHX		 3667 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3668 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
926a01dc
WHX		 3669
3670 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3671 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
926a01dc
WHX		 3672
3673 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3674 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
926a01dc 3675
99441ab5 3676 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
926a01dc
WHX		 3677
3678 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 3679 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3680 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
926a01dc 3681
90ae0b57 3682 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
e088a685
YL		 3683 roce_set_bit(context->byte_68_rq_db,
3684 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
e088a685
YL		 3685
3686 roce_set_field(context->byte_68_rq_db,
3687 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3688 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
3689 ((u32)hr_qp->rdb.dma) >> 1);
bfe86035 3690 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32);
e088a685 3691
ecaaf1e2 3692 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
3693 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 3694
3695 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3696 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
926a01dc
WHX		 3697 if (ibqp->srq) {
3698 roce_set_field(context->byte_76_srqn_op_en,
3699 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3700 to_hr_srq(ibqp->srq)->srqn);
926a01dc
WHX		 3701 roce_set_bit(context->byte_76_srqn_op_en,
3702 V2_QPC_BYTE_76_SRQ_EN_S, 1);
f4c5d869 3703 }
926a01dc
WHX		 3704
3705 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3706 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
926a01dc 3707
68a997c5 3708 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
926a01dc
WHX		 3709
3710 hr_qp->access_flags = attr->qp_access_flags;
926a01dc
WHX		 3711 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3712 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3713}
3714
3715static void modify_qp_init_to_init(struct ib_qp *ibqp,
3716 const struct ib_qp_attr *attr, int attr_mask,
3717 struct hns_roce_v2_qp_context *context,
3718 struct hns_roce_v2_qp_context *qpc_mask)
3719{
3720 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3721
3722 /*
3723 * In v2 engine, software pass context and context mask to hardware
3724 * when modifying qp. If software need modify some fields in context,
3725 * we should set all bits of the relevant fields in context mask to
3726 * 0 at the same time, else set them to 0x1.
3727 */
3728 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3729 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3730 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3731 V2_QPC_BYTE_4_TST_S, 0);
3732
926a01dc
WHX		 3733 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3734 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3735 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3736 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3737 0);
3738
3739 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3740 !!(attr->qp_access_flags &
3741 IB_ACCESS_REMOTE_WRITE));
3742 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3743 0);
3744
3745 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3746 !!(attr->qp_access_flags &
3747 IB_ACCESS_REMOTE_ATOMIC));
3748 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3749 0);
7db82697
JZ		 3750 roce_set_bit(context->byte_76_srqn_op_en,
3751 V2_QPC_BYTE_76_EXT_ATE_S,
3752 !!(attr->qp_access_flags &
3753 IB_ACCESS_REMOTE_ATOMIC));
3754 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3755 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3756 } else {
3757 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3758 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3759 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3760 0);
3761
3762 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3763 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3764 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3765 0);
3766
3767 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3768 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3769 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3770 0);
7db82697
JZ		 3771 roce_set_bit(context->byte_76_srqn_op_en,
3772 V2_QPC_BYTE_76_EXT_ATE_S,
3773 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3774 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3775 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3776 }
3777
926a01dc
WHX		 3778 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3779 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3780 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3781 V2_QPC_BYTE_16_PD_S, 0);
3782
3783 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3784 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3785 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3786 V2_QPC_BYTE_80_RX_CQN_S, 0);
3787
3788 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3789 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3790 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3791 V2_QPC_BYTE_252_TX_CQN_S, 0);
3792
3793 if (ibqp->srq) {
3794 roce_set_bit(context->byte_76_srqn_op_en,
3795 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3796 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3797 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3798 roce_set_field(context->byte_76_srqn_op_en,
3799 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3800 to_hr_srq(ibqp->srq)->srqn);
3801 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3802 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3803 }
3804
926a01dc
WHX		 3805 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3806 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3807 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3808 V2_QPC_BYTE_4_SQPN_S, 0);
3809
b6dd9b34 3810 if (attr_mask & IB_QP_DEST_QPN) {
3811 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3812 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3813 roce_set_field(qpc_mask->byte_56_dqpn_err,
3814 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3815 }
926a01dc
WHX		 3816}
3817
494c3b31
XW		 3818static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
3819 struct hns_roce_qp *hr_qp,
3820 struct hns_roce_v2_qp_context *context,
3821 struct hns_roce_v2_qp_context *qpc_mask)
926a01dc 3822{
8d18ad83 3823 u64 mtts[MTT_MIN_COUNT] = { 0 };
8d18ad83 3824 u64 wqe_sge_ba;
8d18ad83 3825 int count;
926a01dc
WHX		 3826
3827 /* Search qp buf's mtts */
cc33b23e 3828 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, mtts,
8d18ad83 3829 MTT_MIN_COUNT, &wqe_sge_ba);
cc33b23e
XW		 3830 if (hr_qp->rq.wqe_cnt && count < 1) {
3831 ibdev_err(&hr_dev->ib_dev,
3832 "failed to find RQ WQE, QPN = 0x%lx.\n", hr_qp->qpn);
3833 return -EINVAL;
3834 }
926a01dc 3835
bfe86035 3836 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
926a01dc
WHX		 3837 qpc_mask->wqe_sge_ba = 0;
3838
3839 /*
3840 * In v2 engine, software pass context and context mask to hardware
3841 * when modifying qp. If software need modify some fields in context,
3842 * we should set all bits of the relevant fields in context mask to
3843 * 0 at the same time, else set them to 0x1.
3844 */
3845 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
8d18ad83 3846 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3));
926a01dc
WHX		 3847 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3848 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3849
3850 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3851 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
54d66387
XW		 3852 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
3853 hr_qp->sq.wqe_cnt));
926a01dc
WHX		 3854 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3855 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3856
3857 roce_set_field(context->byte_20_smac_sgid_idx,
3858 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3859 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
54d66387
XW		 3860 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
3861 hr_qp->sge.sge_cnt));
926a01dc
WHX		 3862 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3863 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3864 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3865
3866 roce_set_field(context->byte_20_smac_sgid_idx,
3867 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3868 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
54d66387
XW		 3869 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
3870 hr_qp->rq.wqe_cnt));
3871
926a01dc
WHX		 3872 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3873 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3874 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3875
3876 roce_set_field(context->byte_16_buf_ba_pg_sz,
3877 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3878 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
d563099e 3879 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
926a01dc
WHX		 3880 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3881 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3882 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3883
3884 roce_set_field(context->byte_16_buf_ba_pg_sz,
3885 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3886 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
d563099e 3887 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
926a01dc
WHX		 3888 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3889 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3890 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3891
d563099e 3892 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
926a01dc
WHX		 3893 qpc_mask->rq_cur_blk_addr = 0;
3894
3895 roce_set_field(context->byte_92_srq_info,
3896 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3897 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
d563099e 3898 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
926a01dc
WHX		 3899 roce_set_field(qpc_mask->byte_92_srq_info,
3900 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3901 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3902
d563099e 3903 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
926a01dc
WHX		 3904 qpc_mask->rq_nxt_blk_addr = 0;
3905
3906 roce_set_field(context->byte_104_rq_sge,
3907 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3908 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
d563099e 3909 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
926a01dc
WHX		 3910 roce_set_field(qpc_mask->byte_104_rq_sge,
3911 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3912 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3913
494c3b31
XW		 3914 roce_set_field(context->byte_84_rq_ci_pi,
3915 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3916 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3917 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3918 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3919 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3920
3921 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3922 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3923 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3924
3925 return 0;
3926}
3927
3928static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
3929 struct hns_roce_qp *hr_qp,
3930 struct hns_roce_v2_qp_context *context,
3931 struct hns_roce_v2_qp_context *qpc_mask)
3932{
3933 struct ib_device *ibdev = &hr_dev->ib_dev;
3934 u64 sge_cur_blk = 0;
3935 u64 sq_cur_blk = 0;
494c3b31
XW		 3936 int count;
3937
3938 /* search qp buf's mtts */
3939 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
3940 if (count < 1) {
3941 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
3942 hr_qp->qpn);
3943 return -EINVAL;
3944 }
3945 if (hr_qp->sge.sge_cnt > 0) {
494c3b31 3946 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
cc33b23e 3947 hr_qp->sge.offset,
494c3b31
XW		 3948 &sge_cur_blk, 1, NULL);
3949 if (count < 1) {
3950 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
3951 hr_qp->qpn);
3952 return -EINVAL;
3953 }
3954 }
3955
3956 /*
3957 * In v2 engine, software pass context and context mask to hardware
3958 * when modifying qp. If software need modify some fields in context,
3959 * we should set all bits of the relevant fields in context mask to
3960 * 0 at the same time, else set them to 0x1.
3961 */
3962 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
3963 roce_set_field(context->byte_168_irrl_idx,
3964 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3965 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3966 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
3967 qpc_mask->sq_cur_blk_addr = 0;
3968 roce_set_field(qpc_mask->byte_168_irrl_idx,
3969 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3970 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3971
3972 context->sq_cur_sge_blk_addr =
3973 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk));
3974 roce_set_field(context->byte_184_irrl_idx,
3975 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3976 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
3977 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
3978 qpc_mask->sq_cur_sge_blk_addr = 0;
3979 roce_set_field(qpc_mask->byte_184_irrl_idx,
3980 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3981 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3982
3983 context->rx_sq_cur_blk_addr =
3984 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
3985 roce_set_field(context->byte_232_irrl_sge,
3986 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3987 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3988 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
3989 qpc_mask->rx_sq_cur_blk_addr = 0;
3990 roce_set_field(qpc_mask->byte_232_irrl_sge,
3991 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3992 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3993
3994 return 0;
3995}
3996
7b9bd73e
WL		 3997static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
3998 const struct ib_qp_attr *attr)
3999{
4000 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
4001 return IB_MTU_4096;
4002
4003 return attr->path_mtu;
4004}
4005
494c3b31
XW		 4006static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
4007 const struct ib_qp_attr *attr, int attr_mask,
4008 struct hns_roce_v2_qp_context *context,
4009 struct hns_roce_v2_qp_context *qpc_mask)
4010{
4011 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
4012 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4013 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4014 struct ib_device *ibdev = &hr_dev->ib_dev;
4015 dma_addr_t trrl_ba;
4016 dma_addr_t irrl_ba;
7b9bd73e 4017 enum ib_mtu mtu;
494c3b31
XW		 4018 u8 port_num;
4019 u64 *mtts;
4020 u8 *dmac;
4021 u8 *smac;
4022 int port;
4023 int ret;
4024
4025 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
4026 if (ret) {
4027 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
4028 return ret;
4029 }
4030
4031 /* Search IRRL's mtts */
4032 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
4033 hr_qp->qpn, &irrl_ba);
4034 if (!mtts) {
4035 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
4036 return -EINVAL;
4037 }
4038
4039 /* Search TRRL's mtts */
4040 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4041 hr_qp->qpn, &trrl_ba);
4042 if (!mtts) {
4043 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4044 return -EINVAL;
4045 }
4046
4047 if (attr_mask & IB_QP_ALT_PATH) {
4048 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4049 attr_mask);
4050 return -EINVAL;
4051 }
4052
e92f2c18 4053 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
494c3b31 4054 V2_QPC_BYTE_132_TRRL_BA_S, trrl_ba >> 4);
e92f2c18 4055 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
4056 V2_QPC_BYTE_132_TRRL_BA_S, 0);
494c3b31 4057 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
e92f2c18 4058 qpc_mask->trrl_ba = 0;
4059 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
4060 V2_QPC_BYTE_140_TRRL_BA_S,
494c3b31 4061 (u32)(trrl_ba >> (32 + 16 + 4)));
e92f2c18 4062 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
4063 V2_QPC_BYTE_140_TRRL_BA_S, 0);
4064
494c3b31 4065 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
926a01dc
WHX		 4066 qpc_mask->irrl_ba = 0;
4067 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
4068 V2_QPC_BYTE_208_IRRL_BA_S,
494c3b31 4069 irrl_ba >> (32 + 6));
926a01dc
WHX		 4070 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
4071 V2_QPC_BYTE_208_IRRL_BA_S, 0);
4072
4073 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
4074 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
4075
4076 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
4077 hr_qp->sq_signal_bits);
4078 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
4079 0);
4080
4081 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4082
4083 smac = (u8 *)hr_dev->dev_addr[port];
87d9e568 4084 dmac = (u8 *)attr->ah_attr.roce.dmac;
926a01dc
WHX		 4085 /* when dmac equals smac or loop_idc is 1, it should loopback */
4086 if (ether_addr_equal_unaligned(dmac, smac) ||
4087 hr_dev->loop_idc == 0x1) {
4088 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
4089 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
4090 }
4091
b6dd9b34 4092 if (attr_mask & IB_QP_DEST_QPN) {
4093 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
4094 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
4095 roce_set_field(qpc_mask->byte_56_dqpn_err,
4096 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
4097 }
926a01dc
WHX		 4098
4099 /* Configure GID index */
4100 port_num = rdma_ah_get_port_num(&attr->ah_attr);
4101 roce_set_field(context->byte_20_smac_sgid_idx,
60262b10 4102 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
926a01dc
WHX		 4103 hns_get_gid_index(hr_dev, port_num - 1,
4104 grh->sgid_index));
4105 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
60262b10 4106 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
494c3b31 4107
2a3d923f 4108 memcpy(&(context->dmac), dmac, sizeof(u32));
926a01dc
WHX		 4109 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
4110 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
4111 qpc_mask->dmac = 0;
4112 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
4113 V2_QPC_BYTE_52_DMAC_S, 0);
4114
7b9bd73e
WL		 4115 mtu = get_mtu(ibqp, attr);
4116
4117 if (attr_mask & IB_QP_PATH_MTU) {
4118 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
4119 V2_QPC_BYTE_24_MTU_S, mtu);
4120 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
4121 V2_QPC_BYTE_24_MTU_S, 0);
4122 }
4123
4124#define MAX_LP_MSG_LEN 65536
4125 /* MTU*(2^LP_PKTN_INI) shouldn't be bigger than 64kb */
926a01dc 4126 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
b713128d 4127 V2_QPC_BYTE_56_LP_PKTN_INI_S,
7b9bd73e 4128 ilog2(MAX_LP_MSG_LEN / ib_mtu_enum_to_int(mtu)));
926a01dc
WHX		 4129 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
4130 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
4131
926a01dc
WHX		 4132 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4133 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
4134 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
4135 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
4136 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4137 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
4138 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
4139
4140 context->rq_rnr_timer = 0;
4141 qpc_mask->rq_rnr_timer = 0;
4142
926a01dc
WHX		 4143 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
4144 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
4145 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
4146 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
4147
2a3d923f 4148 /* rocee send 2^lp_sgen_ini segs every time */
926a01dc
WHX		 4149 roce_set_field(context->byte_168_irrl_idx,
4150 V2_QPC_BYTE_168_LP_SGEN_INI_M,
4151 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
4152 roce_set_field(qpc_mask->byte_168_irrl_idx,
4153 V2_QPC_BYTE_168_LP_SGEN_INI_M,
4154 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
4155
926a01dc
WHX		 4156 return 0;
4157}
4158
4159static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4160 const struct ib_qp_attr *attr, int attr_mask,
4161 struct hns_roce_v2_qp_context *context,
4162 struct hns_roce_v2_qp_context *qpc_mask)
4163{
4164 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4165 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 4166 struct ib_device *ibdev = &hr_dev->ib_dev;
494c3b31 4167 int ret;
8d18ad83 4168
734f3863 4169 /* Not support alternate path and path migration */
d398d4ca 4170 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
ae1c6148 4171 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
926a01dc
WHX		 4172 return -EINVAL;
4173 }
4174
494c3b31
XW		 4175 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4176 if (ret) {
4177 ibdev_err(ibdev, "failed to config sq buf, ret %d\n", ret);
4178 return ret;
4179 }
926a01dc
WHX		 4180
4181 /*
4182 * Set some fields in context to zero, Because the default values
4183 * of all fields in context are zero, we need not set them to 0 again.
4184 * but we should set the relevant fields of context mask to 0.
4185 */
4186 roce_set_field(qpc_mask->byte_232_irrl_sge,
4187 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
4188 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
4189
4190 roce_set_field(qpc_mask->byte_240_irrl_tail,
4191 V2_QPC_BYTE_240_RX_ACK_MSN_M,
4192 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
4193
926a01dc
WHX		 4194 roce_set_field(qpc_mask->byte_248_ack_psn,
4195 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
4196 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
4197 roce_set_bit(qpc_mask->byte_248_ack_psn,
4198 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
4199 roce_set_field(qpc_mask->byte_248_ack_psn,
4200 V2_QPC_BYTE_248_IRRL_PSN_M,
4201 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
4202
4203 roce_set_field(qpc_mask->byte_240_irrl_tail,
4204 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
4205 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
4206
926a01dc
WHX		 4207 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4208 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
4209 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
4210
4211 roce_set_bit(qpc_mask->byte_248_ack_psn,
4212 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
4213
4214 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
4215 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
4216
926a01dc
WHX		 4217 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4218 V2_QPC_BYTE_212_LSN_S, 0x100);
4219 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4220 V2_QPC_BYTE_212_LSN_S, 0);
4221
926a01dc
WHX		 4222 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
4223 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
926a01dc
WHX		 4224
4225 return 0;
4226}
4227
074bf2c2
WL		 4228static inline u16 get_udp_sport(u32 fl, u32 lqpn, u32 rqpn)
4229{
4230 if (!fl)
4231 fl = rdma_calc_flow_label(lqpn, rqpn);
4232
4233 return rdma_flow_label_to_udp_sport(fl);
4234}
4235
606bf89e
LO		 4236static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4237 const struct ib_qp_attr *attr,
4238 int attr_mask,
4239 struct hns_roce_v2_qp_context *context,
4240 struct hns_roce_v2_qp_context *qpc_mask)
926a01dc 4241{
606bf89e 4242 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
926a01dc
WHX		 4243 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4244 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 4245 struct ib_device *ibdev = &hr_dev->ib_dev;
606bf89e
LO		 4246 const struct ib_gid_attr *gid_attr = NULL;
4247 int is_roce_protocol;
32883228 4248 u16 vlan_id = 0xffff;
606bf89e 4249 bool is_udp = false;
606bf89e
LO		 4250 u8 ib_port;
4251 u8 hr_port;
4252 int ret;
926a01dc 4253
606bf89e
LO		 4254 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4255 hr_port = ib_port - 1;
4256 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4257 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4258
4259 if (is_roce_protocol) {
4260 gid_attr = attr->ah_attr.grh.sgid_attr;
32883228 4261 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
606bf89e
LO		 4262 if (ret)
4263 return ret;
4264
4265 if (gid_attr)
4266 is_udp = (gid_attr->gid_type ==
4267 IB_GID_TYPE_ROCE_UDP_ENCAP);
4268 }
4269
32883228 4270 if (vlan_id < VLAN_N_VID) {
606bf89e
LO		 4271 roce_set_bit(context->byte_76_srqn_op_en,
4272 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
4273 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
4274 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
4275 roce_set_bit(context->byte_168_irrl_idx,
4276 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
4277 roce_set_bit(qpc_mask->byte_168_irrl_idx,
4278 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
4279 }
4280
4281 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
32883228 4282 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id);
606bf89e
LO		 4283 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
4284 V2_QPC_BYTE_24_VLAN_ID_S, 0);
4285
4286 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
ae1c6148
LO		 4287 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4288 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
606bf89e
LO		 4289 return -EINVAL;
4290 }
4291
4292 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
ae1c6148 4293 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
606bf89e
LO		 4294 return -EINVAL;
4295 }
4296
4297 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4298 V2_QPC_BYTE_52_UDPSPN_S,
074bf2c2
WL		 4299 is_udp ? get_udp_sport(grh->flow_label, ibqp->qp_num,
4300 attr->dest_qp_num) : 0);
606bf89e
LO		 4301
4302 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4303 V2_QPC_BYTE_52_UDPSPN_S, 0);
4304
4305 roce_set_field(context->byte_20_smac_sgid_idx,
4306 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
4307 grh->sgid_index);
4308
4309 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4310 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
4311
4312 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4313 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
4314 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4315 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
4316
a247fd28 4317 if (is_udp)
606bf89e
LO		 4318 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4319 V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2);
4320 else
4321 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4322 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
a247fd28 4323
606bf89e
LO		 4324 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4325 V2_QPC_BYTE_24_TC_S, 0);
4326 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4327 V2_QPC_BYTE_28_FL_S, grh->flow_label);
4328 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4329 V2_QPC_BYTE_28_FL_S, 0);
4330 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4331 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4332 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4333 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr));
4334 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4335 V2_QPC_BYTE_28_SL_S, 0);
4336 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4337
4338 return 0;
4339}
4340
357f3429
LC		 4341static bool check_qp_state(enum ib_qp_state cur_state,
4342 enum ib_qp_state new_state)
4343{
4344 static const bool sm[][IB_QPS_ERR + 1] = {
4345 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4346 [IB_QPS_INIT] = true },
4347 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4348 [IB_QPS_INIT] = true,
4349 [IB_QPS_RTR] = true,
4350 [IB_QPS_ERR] = true },
4351 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4352 [IB_QPS_RTS] = true,
4353 [IB_QPS_ERR] = true },
4327bd2c
LC		 4354 [IB_QPS_RTS] = { [IB_QPS_RESET] = true,
4355 [IB_QPS_RTS] = true,
4356 [IB_QPS_ERR] = true },
357f3429
LC		 4357 [IB_QPS_SQD] = {},
4358 [IB_QPS_SQE] = {},
4359 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
4360 };
4361
4362 return sm[cur_state][new_state];
4363}
4364
606bf89e
LO		 4365static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4366 const struct ib_qp_attr *attr,
4367 int attr_mask,
4368 enum ib_qp_state cur_state,
4369 enum ib_qp_state new_state,
4370 struct hns_roce_v2_qp_context *context,
4371 struct hns_roce_v2_qp_context *qpc_mask)
4372{
4373 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4374 int ret = 0;
926a01dc 4375
357f3429
LC		 4376 if (!check_qp_state(cur_state, new_state)) {
4377 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
4378 return -EINVAL;
4379 }
4380
926a01dc 4381 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
98912ee8 4382 memset(qpc_mask, 0, hr_dev->caps.qpc_sz);
0fa95a9a 4383 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
4384 qpc_mask);
926a01dc
WHX		 4385 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4386 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
4387 qpc_mask);
4388 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4389 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4390 qpc_mask);
926a01dc
WHX		 4391 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4392 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
4393 qpc_mask);
926a01dc
WHX		 4394 }
4395
606bf89e
LO		 4396 return ret;
4397}
9c6ccc03 4398
606bf89e
LO		 4399static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
4400 const struct ib_qp_attr *attr,
4401 int attr_mask,
4402 struct hns_roce_v2_qp_context *context,
4403 struct hns_roce_v2_qp_context *qpc_mask)
4404{
4405 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4406 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4407 int ret = 0;
0425e3e6 4408
610b8967 4409 if (attr_mask & IB_QP_AV) {
606bf89e
LO		 4410 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
4411 qpc_mask);
4412 if (ret)
4413 return ret;
610b8967
LO		 4414 }
4415
5b01b243
LO		 4416 if (attr_mask & IB_QP_TIMEOUT) {
4417 if (attr->timeout < 31) {
4418 roce_set_field(context->byte_28_at_fl,
4419 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4420 attr->timeout);
4421 roce_set_field(qpc_mask->byte_28_at_fl,
4422 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4423 0);
4424 } else {
ae1c6148
LO		 4425 ibdev_warn(&hr_dev->ib_dev,
4426 "Local ACK timeout shall be 0 to 30.\n");
5b01b243
LO		 4427 }
4428 }
4429
4430 if (attr_mask & IB_QP_RETRY_CNT) {
4431 roce_set_field(context->byte_212_lsn,
4432 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4433 V2_QPC_BYTE_212_RETRY_NUM_INIT_S,
4434 attr->retry_cnt);
4435 roce_set_field(qpc_mask->byte_212_lsn,
4436 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4437 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
4438
4439 roce_set_field(context->byte_212_lsn,
4440 V2_QPC_BYTE_212_RETRY_CNT_M,
60262b10 4441 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
5b01b243
LO		 4442 roce_set_field(qpc_mask->byte_212_lsn,
4443 V2_QPC_BYTE_212_RETRY_CNT_M,
4444 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
4445 }
4446
4447 if (attr_mask & IB_QP_RNR_RETRY) {
4448 roce_set_field(context->byte_244_rnr_rxack,
4449 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4450 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
4451 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4452 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4453 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
4454
4455 roce_set_field(context->byte_244_rnr_rxack,
4456 V2_QPC_BYTE_244_RNR_CNT_M,
4457 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
4458 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4459 V2_QPC_BYTE_244_RNR_CNT_M,
4460 V2_QPC_BYTE_244_RNR_CNT_S, 0);
4461 }
4462
606bf89e 4463 /* RC&UC&UD required attr */
f04cc178
LO		 4464 if (attr_mask & IB_QP_SQ_PSN) {
4465 roce_set_field(context->byte_172_sq_psn,
4466 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4467 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
4468 roce_set_field(qpc_mask->byte_172_sq_psn,
4469 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4470 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
4471
4472 roce_set_field(context->byte_196_sq_psn,
4473 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4474 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
4475 roce_set_field(qpc_mask->byte_196_sq_psn,
4476 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4477 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
4478
4479 roce_set_field(context->byte_220_retry_psn_msn,
4480 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4481 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
4482 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4483 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4484 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
4485
4486 roce_set_field(context->byte_224_retry_msg,
4487 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4488 V2_QPC_BYTE_224_RETRY_MSG_PSN_S,
2a3d923f 4489 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S);
f04cc178
LO		 4490 roce_set_field(qpc_mask->byte_224_retry_msg,
4491 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4492 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
4493
4494 roce_set_field(context->byte_224_retry_msg,
4495 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4496 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S,
4497 attr->sq_psn);
4498 roce_set_field(qpc_mask->byte_224_retry_msg,
4499 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4500 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
4501
4502 roce_set_field(context->byte_244_rnr_rxack,
4503 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4504 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
4505 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4506 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4507 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
4508 }
4509
5b01b243
LO		 4510 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
4511 attr->max_dest_rd_atomic) {
4512 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4513 V2_QPC_BYTE_140_RR_MAX_S,
4514 fls(attr->max_dest_rd_atomic - 1));
4515 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4516 V2_QPC_BYTE_140_RR_MAX_S, 0);
4517 }
4518
4519 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
4520 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
4521 V2_QPC_BYTE_208_SR_MAX_S,
4522 fls(attr->max_rd_atomic - 1));
4523 roce_set_field(qpc_mask->byte_208_irrl,
4524 V2_QPC_BYTE_208_SR_MAX_M,
4525 V2_QPC_BYTE_208_SR_MAX_S, 0);
4526 }
4527
ace1c541 4528 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4529 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4530
5b01b243
LO		 4531 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
4532 roce_set_field(context->byte_80_rnr_rx_cqn,
4533 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4534 V2_QPC_BYTE_80_MIN_RNR_TIME_S,
4535 attr->min_rnr_timer);
4536 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
4537 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4538 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
4539 }
4540
601f3e6d
LO		 4541 /* RC&UC required attr */
4542 if (attr_mask & IB_QP_RQ_PSN) {
4543 roce_set_field(context->byte_108_rx_reqepsn,
4544 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4545 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
4546 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4547 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4548 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
4549
4550 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
4551 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
4552 roce_set_field(qpc_mask->byte_152_raq,
4553 V2_QPC_BYTE_152_RAQ_PSN_M,
4554 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
4555 }
4556
5b01b243 4557 if (attr_mask & IB_QP_QKEY) {
bfe86035 4558 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5b01b243
LO		 4559 qpc_mask->qkey_xrcd = 0;
4560 hr_qp->qkey = attr->qkey;
4561 }
4562
606bf89e
LO		 4563 return ret;
4564}
4565
4566static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
4567 const struct ib_qp_attr *attr,
4568 int attr_mask)
4569{
4570 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4571 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4572
4573 if (attr_mask & IB_QP_ACCESS_FLAGS)
4574 hr_qp->atomic_rd_en = attr->qp_access_flags;
4575
4576 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4577 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4578 if (attr_mask & IB_QP_PORT) {
4579 hr_qp->port = attr->port_num - 1;
4580 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4581 }
4582}
4583
4584static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
4585 const struct ib_qp_attr *attr,
4586 int attr_mask, enum ib_qp_state cur_state,
4587 enum ib_qp_state new_state)
4588{
4589 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4590 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d
LC		 4591 struct hns_roce_v2_qp_context ctx[2];
4592 struct hns_roce_v2_qp_context *context = ctx;
4593 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
ae1c6148 4594 struct ib_device *ibdev = &hr_dev->ib_dev;
b5374286
YL		 4595 unsigned long sq_flag = 0;
4596 unsigned long rq_flag = 0;
b5c229dc 4597 int ret;
606bf89e 4598
606bf89e
LO		 4599 /*
4600 * In v2 engine, software pass context and context mask to hardware
4601 * when modifying qp. If software need modify some fields in context,
4602 * we should set all bits of the relevant fields in context mask to
4603 * 0 at the same time, else set them to 0x1.
4604 */
98912ee8
WL		 4605 memset(context, 0, hr_dev->caps.qpc_sz);
4606 memset(qpc_mask, 0xff, hr_dev->caps.qpc_sz);
4607
606bf89e
LO		 4608 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
4609 new_state, context, qpc_mask);
4610 if (ret)
4611 goto out;
4612
4613 /* When QP state is err, SQ and RQ WQE should be flushed */
4614 if (new_state == IB_QPS_ERR) {
b5374286 4615 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
b5374286 4616 hr_qp->state = IB_QPS_ERR;
606bf89e
LO		 4617 roce_set_field(context->byte_160_sq_ci_pi,
4618 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4619 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
4620 hr_qp->sq.head);
4621 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
4622 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4623 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
75c994e6 4624 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
606bf89e
LO		 4625
4626 if (!ibqp->srq) {
75c994e6 4627 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4628 roce_set_field(context->byte_84_rq_ci_pi,
4629 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4630 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
4631 hr_qp->rq.head);
4632 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
4633 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4634 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
75c994e6 4635 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4636 }
4637 }
4638
4639 /* Configure the optional fields */
4640 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
4641 qpc_mask);
4642 if (ret)
4643 goto out;
4644
c7bcb134
LO		 4645 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S,
4646 ibqp->srq ? 1 : 0);
4647 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4648 V2_QPC_BYTE_108_INV_CREDIT_S, 0);
4649
926a01dc 4650 /* Every status migrate must change state */
2362ccee 4651 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 4652 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 4653 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 4654 V2_QPC_BYTE_60_QP_ST_S, 0);
4655
4656 /* SW pass context to HW */
98912ee8 4657 ret = hns_roce_v2_qp_modify(hr_dev, context, qpc_mask, hr_qp);
926a01dc 4658 if (ret) {
ae1c6148 4659 ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret);
926a01dc
WHX		 4660 goto out;
4661 }
4662
4663 hr_qp->state = new_state;
4664
606bf89e 4665 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
926a01dc
WHX		 4666
4667 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
4668 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
4669 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
4670 if (ibqp->send_cq != ibqp->recv_cq)
4671 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4672 hr_qp->qpn, NULL);
4673
4674 hr_qp->rq.head = 0;
4675 hr_qp->rq.tail = 0;
4676 hr_qp->sq.head = 0;
4677 hr_qp->sq.tail = 0;
926a01dc 4678 hr_qp->next_sge = 0;
e088a685
YL		 4679 if (hr_qp->rq.wqe_cnt)
4680 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 4681 }
4682
4683out:
926a01dc
WHX		 4684 return ret;
4685}
4686
a3de9e83 4687static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
926a01dc 4688{
a3de9e83
LC		 4689 static const enum ib_qp_state map[] = {
4690 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
4691 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
4692 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
4693 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
4694 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
4695 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
4696 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
4697 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
4698 };
4699
4700 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
926a01dc
WHX		 4701}
4702
4703static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
4704 struct hns_roce_qp *hr_qp,
4705 struct hns_roce_v2_qp_context *hr_context)
4706{
4707 struct hns_roce_cmd_mailbox *mailbox;
4708 int ret;
4709
4710 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4711 if (IS_ERR(mailbox))
4712 return PTR_ERR(mailbox);
4713
4714 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
4715 HNS_ROCE_CMD_QUERY_QPC,
4716 HNS_ROCE_CMD_TIMEOUT_MSECS);
ae1c6148 4717 if (ret)
926a01dc 4718 goto out;
926a01dc 4719
98912ee8 4720 memcpy(hr_context, mailbox->buf, hr_dev->caps.qpc_sz);
926a01dc
WHX		 4721
4722out:
4723 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4724 return ret;
4725}
4726
4727static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4728 int qp_attr_mask,
4729 struct ib_qp_init_attr *qp_init_attr)
4730{
4731 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4732 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d 4733 struct hns_roce_v2_qp_context context = {};
ae1c6148 4734 struct ib_device *ibdev = &hr_dev->ib_dev;
926a01dc
WHX		 4735 int tmp_qp_state;
4736 int state;
4737 int ret;
4738
926a01dc
WHX		 4739 memset(qp_attr, 0, sizeof(*qp_attr));
4740 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4741
4742 mutex_lock(&hr_qp->mutex);
4743
4744 if (hr_qp->state == IB_QPS_RESET) {
4745 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 4746 ret = 0;
926a01dc
WHX		 4747 goto done;
4748 }
4749
4b42d05d 4750 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context);
926a01dc 4751 if (ret) {
ae1c6148 4752 ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret);
926a01dc
WHX		 4753 ret = -EINVAL;
4754 goto out;
4755 }
4756
4b42d05d 4757 state = roce_get_field(context.byte_60_qpst_tempid,
926a01dc
WHX		 4758 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
4759 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
4760 if (tmp_qp_state == -1) {
ae1c6148 4761 ibdev_err(ibdev, "Illegal ib_qp_state\n");
926a01dc
WHX		 4762 ret = -EINVAL;
4763 goto out;
4764 }
4765 hr_qp->state = (u8)tmp_qp_state;
4766 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
4b42d05d 4767 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4768 V2_QPC_BYTE_24_MTU_M,
4769 V2_QPC_BYTE_24_MTU_S);
4770 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 4771 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc 4772 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
349be276 4773 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
926a01dc 4774
4b42d05d 4775 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn,
926a01dc
WHX		 4776 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4777 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
4b42d05d 4778 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn,
926a01dc
WHX		 4779 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4780 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
4b42d05d 4781 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err,
926a01dc
WHX		 4782 V2_QPC_BYTE_56_DQPN_M,
4783 V2_QPC_BYTE_56_DQPN_S);
4b42d05d 4784 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4785 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) |
4b42d05d 4786 ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4787 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) |
4b42d05d 4788 ((roce_get_bit(context.byte_76_srqn_op_en,
2a3d923f
LO		 4789 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S);
4790
926a01dc
WHX		 4791 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
4792 hr_qp->ibqp.qp_type == IB_QPT_UC) {
4793 struct ib_global_route *grh =
4794 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
4795
4796 rdma_ah_set_sl(&qp_attr->ah_attr,
4b42d05d 4797 roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4798 V2_QPC_BYTE_28_SL_M,
4799 V2_QPC_BYTE_28_SL_S));
4b42d05d 4800 grh->flow_label = roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4801 V2_QPC_BYTE_28_FL_M,
4802 V2_QPC_BYTE_28_FL_S);
4b42d05d 4803 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx,
926a01dc
WHX		 4804 V2_QPC_BYTE_20_SGID_IDX_M,
4805 V2_QPC_BYTE_20_SGID_IDX_S);
4b42d05d 4806 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4807 V2_QPC_BYTE_24_HOP_LIMIT_M,
4808 V2_QPC_BYTE_24_HOP_LIMIT_S);
4b42d05d 4809 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4810 V2_QPC_BYTE_24_TC_M,
4811 V2_QPC_BYTE_24_TC_S);
4812
4b42d05d 4813 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
926a01dc
WHX		 4814 }
4815
4816 qp_attr->port_num = hr_qp->port + 1;
4817 qp_attr->sq_draining = 0;
4b42d05d 4818 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl,
926a01dc
WHX		 4819 V2_QPC_BYTE_208_SR_MAX_M,
4820 V2_QPC_BYTE_208_SR_MAX_S);
4b42d05d 4821 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq,
926a01dc
WHX		 4822 V2_QPC_BYTE_140_RR_MAX_M,
4823 V2_QPC_BYTE_140_RR_MAX_S);
4b42d05d 4824 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn,
926a01dc
WHX		 4825 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4826 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4b42d05d 4827 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4828 V2_QPC_BYTE_28_AT_M,
4829 V2_QPC_BYTE_28_AT_S);
4b42d05d 4830 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn,
926a01dc
WHX		 4831 V2_QPC_BYTE_212_RETRY_CNT_M,
4832 V2_QPC_BYTE_212_RETRY_CNT_S);
bfe86035 4833 qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer);
926a01dc
WHX		 4834
4835done:
4836 qp_attr->cur_qp_state = qp_attr->qp_state;
4837 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4838 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4839
4840 if (!ibqp->uobject) {
4841 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4842 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4843 } else {
4844 qp_attr->cap.max_send_wr = 0;
4845 qp_attr->cap.max_send_sge = 0;
4846 }
4847
4848 qp_init_attr->cap = qp_attr->cap;
4849
4850out:
4851 mutex_unlock(&hr_qp->mutex);
926a01dc
WHX		 4852 return ret;
4853}
4854
4855static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4856 struct hns_roce_qp *hr_qp,
bdeacabd 4857 struct ib_udata *udata)
926a01dc 4858{
db50077b 4859 struct ib_device *ibdev = &hr_dev->ib_dev;
ae1c6148 4860 struct hns_roce_cq *send_cq, *recv_cq;
626903e9 4861 unsigned long flags;
d302c6e3 4862 int ret = 0;
926a01dc
WHX		 4863
4864 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4865 /* Modify qp to reset before destroying qp */
4866 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4867 hr_qp->state, IB_QPS_RESET);
d302c6e3 4868 if (ret)
ae1c6148
LO		 4869 ibdev_err(ibdev,
4870 "failed to modify QP to RST, ret = %d\n",
4871 ret);
926a01dc
WHX		 4872 }
4873
626903e9
XW		 4874 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
4875 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
926a01dc 4876
626903e9 4877 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
926a01dc
WHX		 4878 hns_roce_lock_cqs(send_cq, recv_cq);
4879
bdeacabd 4880 if (!udata) {
626903e9
XW		 4881 if (recv_cq)
4882 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
4883 (hr_qp->ibqp.srq ?
4884 to_hr_srq(hr_qp->ibqp.srq) :
4885 NULL));
4886
4887 if (send_cq && send_cq != recv_cq)
926a01dc 4888 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
626903e9 4889
926a01dc
WHX		 4890 }
4891
4892 hns_roce_qp_remove(hr_dev, hr_qp);
4893
4894 hns_roce_unlock_cqs(send_cq, recv_cq);
626903e9 4895 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
926a01dc 4896
d302c6e3 4897 return ret;
926a01dc
WHX		 4898}
4899
c4367a26 4900static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
926a01dc
WHX		 4901{
4902 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4903 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4904 int ret;
4905
bdeacabd 4906 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
d302c6e3 4907 if (ret)
ae1c6148
LO		 4908 ibdev_err(&hr_dev->ib_dev,
4909 "failed to destroy QP 0x%06lx, ret = %d\n",
db50077b 4910 hr_qp->qpn, ret);
926a01dc 4911
e365b26c 4912 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
926a01dc
WHX		 4913
4914 return 0;
4915}
4916
aa84fa18 4917static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
ae1c6148 4918 struct hns_roce_qp *hr_qp)
aa84fa18 4919{
ae1c6148 4920 struct ib_device *ibdev = &hr_dev->ib_dev;
da91ddfd 4921 struct hns_roce_sccc_clr_done *resp;
aa84fa18
YL		 4922 struct hns_roce_sccc_clr *clr;
4923 struct hns_roce_cmq_desc desc;
4924 int ret, i;
4925
4926 mutex_lock(&hr_dev->qp_table.scc_mutex);
4927
4928 /* set scc ctx clear done flag */
4929 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
aa84fa18
YL		 4930 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4931 if (ret) {
ae1c6148 4932 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4933 goto out;
4934 }
4935
4936 /* clear scc context */
4937 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
4938 clr = (struct hns_roce_sccc_clr *)desc.data;
4939 clr->qpn = cpu_to_le32(hr_qp->qpn);
4940 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4941 if (ret) {
ae1c6148 4942 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4943 goto out;
4944 }
4945
4946 /* query scc context clear is done or not */
4947 resp = (struct hns_roce_sccc_clr_done *)desc.data;
4948 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
4949 hns_roce_cmq_setup_basic_desc(&desc,
4950 HNS_ROCE_OPC_QUERY_SCCC, true);
4951 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4952 if (ret) {
ae1c6148
LO		 4953 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
4954 ret);
aa84fa18
YL		 4955 goto out;
4956 }
4957
4958 if (resp->clr_done)
4959 goto out;
4960
4961 msleep(20);
4962 }
4963
ae1c6148 4964 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n");
aa84fa18
YL		 4965 ret = -ETIMEDOUT;
4966
4967out:
4968 mutex_unlock(&hr_dev->qp_table.scc_mutex);
4969 return ret;
4970}
4971
ffb1308b
YL		 4972static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
4973 struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
4974 u32 cqn, void *mb_buf, u64 *mtts_wqe,
4975 u64 *mtts_idx, dma_addr_t dma_handle_wqe,
4976 dma_addr_t dma_handle_idx)
b156269d 4977{
ffb1308b 4978 struct hns_roce_srq_context *srq_context;
b156269d 4979
ffb1308b
YL		 4980 srq_context = mb_buf;
4981 memset(srq_context, 0, sizeof(*srq_context));
b156269d 4982
ffb1308b
YL		 4983 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M,
4984 SRQC_BYTE_4_SRQ_ST_S, 1);
b156269d 4985
ffb1308b
YL		 4986 roce_set_field(srq_context->byte_4_srqn_srqst,
4987 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M,
4988 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S,
67954a6e
XW		 4989 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
4990 srq->wqe_cnt));
ffb1308b
YL		 4991 roce_set_field(srq_context->byte_4_srqn_srqst,
4992 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S,
4993 ilog2(srq->wqe_cnt));
b156269d 4994
ffb1308b
YL		 4995 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M,
4996 SRQC_BYTE_4_SRQN_S, srq->srqn);
b156269d 4997
ffb1308b
YL		 4998 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M,
4999 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
b156269d 5000
ffb1308b
YL		 5001 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
5002 SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
0425e3e6 5003
ffb1308b 5004 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));
0425e3e6 5005
ffb1308b
YL		 5006 roce_set_field(srq_context->byte_24_wqe_bt_ba,
5007 SRQC_BYTE_24_SRQ_WQE_BT_BA_M,
5008 SRQC_BYTE_24_SRQ_WQE_BT_BA_S,
5009 dma_handle_wqe >> 35);
5010
5011 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
5012 SRQC_BYTE_28_PD_S, pdn);
5013 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
5014 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
5015 fls(srq->max_gs - 1));
5016
5017 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3);
5018 roce_set_field(srq_context->rsv_idx_bt_ba,
5019 SRQC_BYTE_36_SRQ_IDX_BT_BA_M,
5020 SRQC_BYTE_36_SRQ_IDX_BT_BA_S,
5021 dma_handle_idx >> 35);
5022
5023 srq_context->idx_cur_blk_addr =
5024 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0]));
5025 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5026 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M,
5027 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S,
5028 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
5029 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5030 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M,
5031 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S,
67954a6e
XW		 5032 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num,
5033 srq->wqe_cnt));
ffb1308b
YL		 5034
5035 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5036 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
5037 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
5038 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift));
5039 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5040 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
5041 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
5042 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift));
5043
5044 srq_context->idx_nxt_blk_addr =
5045 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1]));
5046 roce_set_field(srq_context->rsv_idxnxtblkaddr,
5047 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M,
5048 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S,
5049 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
5050 roce_set_field(srq_context->byte_56_xrc_cqn,
5051 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
5052 cqn);
5053 roce_set_field(srq_context->byte_56_xrc_cqn,
5054 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
5055 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
5056 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5057 roce_set_field(srq_context->byte_56_xrc_cqn,
5058 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M,
5059 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S,
5060 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5061
5062 roce_set_bit(srq_context->db_record_addr_record_en,
5063 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0);
5064}
5065
5066static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5067 struct ib_srq_attr *srq_attr,
5068 enum ib_srq_attr_mask srq_attr_mask,
5069 struct ib_udata *udata)
5070{
5071 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5072 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5073 struct hns_roce_srq_context *srq_context;
5074 struct hns_roce_srq_context *srqc_mask;
5075 struct hns_roce_cmd_mailbox *mailbox;
5076 int ret;
5077
5078 if (srq_attr_mask & IB_SRQ_LIMIT) {
5079 if (srq_attr->srq_limit >= srq->wqe_cnt)
5080 return -EINVAL;
5081
5082 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5083 if (IS_ERR(mailbox))
5084 return PTR_ERR(mailbox);
5085
5086 srq_context = mailbox->buf;
5087 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5088
5089 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5090
5091 roce_set_field(srq_context->byte_8_limit_wl,
5092 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5093 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit);
5094 roce_set_field(srqc_mask->byte_8_limit_wl,
5095 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5096 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5097
5098 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5099 HNS_ROCE_CMD_MODIFY_SRQC,
5100 HNS_ROCE_CMD_TIMEOUT_MSECS);
5101 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5102 if (ret) {
5103 ibdev_err(&hr_dev->ib_dev,
5104 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5105 ret);
5106 return ret;
5107 }
5108 }
5109
5110 return 0;
5111}
5112
5113static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5114{
5115 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5116 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5117 struct hns_roce_srq_context *srq_context;
5118 struct hns_roce_cmd_mailbox *mailbox;
5119 int limit_wl;
5120 int ret;
5121
5122 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5123 if (IS_ERR(mailbox))
5124 return PTR_ERR(mailbox);
5125
5126 srq_context = mailbox->buf;
5127 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5128 HNS_ROCE_CMD_QUERY_SRQC,
5129 HNS_ROCE_CMD_TIMEOUT_MSECS);
5130 if (ret) {
5131 ibdev_err(&hr_dev->ib_dev,
5132 "failed to process cmd of querying SRQ, ret = %d.\n",
5133 ret);
5134 goto out;
5135 }
5136
5137 limit_wl = roce_get_field(srq_context->byte_8_limit_wl,
5138 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5139 SRQC_BYTE_8_SRQ_LIMIT_WL_S);
5140
5141 attr->srq_limit = limit_wl;
6968aeb5 5142 attr->max_wr = srq->wqe_cnt - 1;
6da06c62 5143 attr->max_sge = srq->max_gs;
ffb1308b 5144
ffb1308b
YL		 5145out:
5146 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5147 return ret;
5148}
5149
5150static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5151{
5152 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5153 struct hns_roce_v2_cq_context *cq_context;
5154 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5155 struct hns_roce_v2_cq_context *cqc_mask;
5156 struct hns_roce_cmd_mailbox *mailbox;
5157 int ret;
5158
5159 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5160 if (IS_ERR(mailbox))
5161 return PTR_ERR(mailbox);
5162
5163 cq_context = mailbox->buf;
5164 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5165
5166 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5167
5168 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
5169 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
5170 cq_count);
5171 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
5172 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
5173 0);
5174 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
5175 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
5176 cq_period);
5177 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
5178 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
5179 0);
5180
5181 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
5182 HNS_ROCE_CMD_MODIFY_CQC,
5183 HNS_ROCE_CMD_TIMEOUT_MSECS);
5184 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5185 if (ret)
5186 ibdev_err(&hr_dev->ib_dev,
5187 "failed to process cmd when modifying CQ, ret = %d\n",
5188 ret);
5189
5190 return ret;
5191}
5192
5193static void hns_roce_irq_work_handle(struct work_struct *work)
5194{
5195 struct hns_roce_work *irq_work =
5196 container_of(work, struct hns_roce_work, work);
5197 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5198 u32 qpn = irq_work->qpn;
5199 u32 cqn = irq_work->cqn;
5200
5201 switch (irq_work->event_type) {
5202 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5203 ibdev_info(ibdev, "Path migrated succeeded.\n");
5204 break;
5205 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5206 ibdev_warn(ibdev, "Path migration failed.\n");
5207 break;
5208 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5209 break;
5210 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5211 ibdev_warn(ibdev, "Send queue drained.\n");
5212 break;
5213 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5214 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n",
5215 qpn, irq_work->sub_type);
5216 break;
5217 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5218 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n",
5219 qpn);
5220 break;
5221 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5222 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n",
5223 qpn, irq_work->sub_type);
5224 break;
5225 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5226 ibdev_warn(ibdev, "SRQ limit reach.\n");
5227 break;
5228 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5229 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
5230 break;
5231 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5232 ibdev_err(ibdev, "SRQ catas error.\n");
5233 break;
5234 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5235 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn);
5236 break;
5237 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5238 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn);
5239 break;
5240 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5241 ibdev_warn(ibdev, "DB overflow.\n");
5242 break;
5243 case HNS_ROCE_EVENT_TYPE_FLR:
5244 ibdev_warn(ibdev, "Function level reset.\n");
5245 break;
5246 default:
5247 break;
5248 }
5249
5250 kfree(irq_work);
5251}
0425e3e6
YL		 5252
5253static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 5254 struct hns_roce_eq *eq,
5255 u32 qpn, u32 cqn)
0425e3e6
YL		 5256{
5257 struct hns_roce_work *irq_work;
5258
5259 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5260 if (!irq_work)
5261 return;
5262
5263 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
5264 irq_work->hr_dev = hr_dev;
5265 irq_work->qpn = qpn;
b00a92c8 5266 irq_work->cqn = cqn;
0425e3e6
YL		 5267 irq_work->event_type = eq->event_type;
5268 irq_work->sub_type = eq->sub_type;
5269 queue_work(hr_dev->irq_workq, &(irq_work->work));
5270}
5271
a5073d60
YL		 5272static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
5273{
d3743fa9 5274 struct hns_roce_dev *hr_dev = eq->hr_dev;
880f133c 5275 __le32 doorbell[2] = {};
a5073d60
YL		 5276
5277 if (eq->type_flag == HNS_ROCE_AEQ) {
5278 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
5279 HNS_ROCE_V2_EQ_DB_CMD_S,
5280 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5281 HNS_ROCE_EQ_DB_CMD_AEQ :
5282 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5283 } else {
5284 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
5285 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
5286
5287 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
5288 HNS_ROCE_V2_EQ_DB_CMD_S,
5289 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5290 HNS_ROCE_EQ_DB_CMD_CEQ :
5291 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5292 }
5293
5294 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
5295 HNS_ROCE_V2_EQ_DB_PARA_S,
5296 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
5297
d3743fa9 5298 hns_roce_write64(hr_dev, doorbell, eq->doorbell);
a5073d60
YL		 5299}
5300
a5073d60
YL		 5301static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5302{
5303 struct hns_roce_aeqe *aeqe;
5304
477a0a38 5305 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a 5306 (eq->cons_index & (eq->entries - 1)) *
247fc16d 5307 eq->eqe_size);
cc23267a 5308
a5073d60
YL		 5309 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
5310 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5311}
5312
5313static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5314 struct hns_roce_eq *eq)
5315{
5316 struct device *dev = hr_dev->dev;
e7f40440 5317 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 5318 int aeqe_found = 0;
5319 int event_type;
0425e3e6 5320 int sub_type;
81fce629 5321 u32 srqn;
0425e3e6
YL		 5322 u32 qpn;
5323 u32 cqn;
a5073d60 5324
e7f40440 5325 while (aeqe) {
4044a3f4
YL		 5326 /* Make sure we read AEQ entry after we have checked the
5327 * ownership bit
5328 */
5329 dma_rmb();
a5073d60
YL		 5330
5331 event_type = roce_get_field(aeqe->asyn,
5332 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
5333 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 5334 sub_type = roce_get_field(aeqe->asyn,
5335 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
5336 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
5337 qpn = roce_get_field(aeqe->event.qp_event.qp,
5338 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5339 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5340 cqn = roce_get_field(aeqe->event.cq_event.cq,
5341 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5342 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
81fce629
LO		 5343 srqn = roce_get_field(aeqe->event.srq_event.srq,
5344 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5345 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 5346
5347 switch (event_type) {
5348 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 5349 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 5350 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5351 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5352 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
81fce629 5353 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
a5073d60
YL		 5354 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5355 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 5356 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 5357 break;
5358 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
a5073d60 5359 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
81fce629 5360 hns_roce_srq_event(hr_dev, srqn, event_type);
a5073d60
YL		 5361 break;
5362 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5363 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 5364 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 5365 break;
5366 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 5367 break;
5368 case HNS_ROCE_EVENT_TYPE_MB:
5369 hns_roce_cmd_event(hr_dev,
5370 le16_to_cpu(aeqe->event.cmd.token),
5371 aeqe->event.cmd.status,
5372 le64_to_cpu(aeqe->event.cmd.out_param));
5373 break;
5374 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 5375 break;
5376 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 5377 break;
5378 default:
5379 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
5380 event_type, eq->eqn, eq->cons_index);
5381 break;
790b57f6 5382 }
a5073d60 5383
0425e3e6
YL		 5384 eq->event_type = event_type;
5385 eq->sub_type = sub_type;
a5073d60
YL		 5386 ++eq->cons_index;
5387 aeqe_found = 1;
5388
249f2f92 5389 if (eq->cons_index > (2 * eq->entries - 1))
a5073d60 5390 eq->cons_index = 0;
249f2f92 5391
b00a92c8 5392 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
e7f40440
LC		 5393
5394 aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 5395 }
5396
5397 set_eq_cons_index_v2(eq);
5398 return aeqe_found;
5399}
5400
a5073d60
YL		 5401static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
5402{
5403 struct hns_roce_ceqe *ceqe;
5404
477a0a38 5405 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a 5406 (eq->cons_index & (eq->entries - 1)) *
247fc16d
WL		 5407 eq->eqe_size);
5408
a5073d60
YL		 5409 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
5410 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
5411}
5412
5413static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
5414 struct hns_roce_eq *eq)
5415{
e7f40440 5416 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5417 int ceqe_found = 0;
5418 u32 cqn;
5419
e7f40440 5420 while (ceqe) {
4044a3f4
YL		 5421 /* Make sure we read CEQ entry after we have checked the
5422 * ownership bit
5423 */
5424 dma_rmb();
5425
60262b10 5426 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M,
a5073d60
YL		 5427 HNS_ROCE_V2_CEQE_COMP_CQN_S);
5428
5429 hns_roce_cq_completion(hr_dev, cqn);
5430
5431 ++eq->cons_index;
5432 ceqe_found = 1;
5433
bceda6e6 5434 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1))
a5073d60 5435 eq->cons_index = 0;
e7f40440
LC		 5436
5437 ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5438 }
5439
5440 set_eq_cons_index_v2(eq);
5441
5442 return ceqe_found;
5443}
5444
5445static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
5446{
5447 struct hns_roce_eq *eq = eq_ptr;
5448 struct hns_roce_dev *hr_dev = eq->hr_dev;
a2f3d447 5449 int int_work;
a5073d60
YL		 5450
5451 if (eq->type_flag == HNS_ROCE_CEQ)
5452 /* Completion event interrupt */
5453 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
5454 else
5455 /* Asychronous event interrupt */
5456 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5457
5458 return IRQ_RETVAL(int_work);
5459}
5460
5461static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5462{
5463 struct hns_roce_dev *hr_dev = dev_id;
5464 struct device *dev = hr_dev->dev;
5465 int int_work = 0;
5466 u32 int_st;
5467 u32 int_en;
5468
5469 /* Abnormal interrupt */
5470 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5471 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5472
bfe86035 5473 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
2b9acb9a
XT		 5474 struct pci_dev *pdev = hr_dev->pci_dev;
5475 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5476 const struct hnae3_ae_ops *ops = ae_dev->ops;
5477
a5073d60
YL		 5478 dev_err(dev, "AEQ overflow!\n");
5479
bfe86035 5480 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S;
a5073d60
YL		 5481 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5482
2b9acb9a
XT		 5483 /* Set reset level for reset_event() */
5484 if (ops->set_default_reset_request)
5485 ops->set_default_reset_request(ae_dev,
5486 HNAE3_FUNC_RESET);
5487 if (ops->reset_event)
5488 ops->reset_event(pdev, NULL);
5489
bfe86035 5490 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5491 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5492
5493 int_work = 1;
bfe86035 5494 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
a5073d60
YL		 5495 dev_err(dev, "BUS ERR!\n");
5496
bfe86035 5497 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S;
a5073d60
YL		 5498 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5499
bfe86035 5500 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5501 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5502
5503 int_work = 1;
bfe86035 5504 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
a5073d60
YL		 5505 dev_err(dev, "OTHER ERR!\n");
5506
bfe86035 5507 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S;
a5073d60
YL		 5508 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5509
bfe86035 5510 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5511 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5512
5513 int_work = 1;
5514 } else
5515 dev_err(dev, "There is no abnormal irq found!\n");
5516
5517 return IRQ_RETVAL(int_work);
5518}
5519
5520static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5521 int eq_num, int enable_flag)
5522{
5523 int i;
5524
5525 if (enable_flag == EQ_ENABLE) {
5526 for (i = 0; i < eq_num; i++)
5527 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5528 i * EQ_REG_OFFSET,
5529 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
5530
5531 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5532 HNS_ROCE_V2_VF_ABN_INT_EN_M);
5533 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5534 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
5535 } else {
5536 for (i = 0; i < eq_num; i++)
5537 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5538 i * EQ_REG_OFFSET,
5539 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
5540
5541 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5542 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
5543 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5544 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
5545 }
5546}
5547
5548static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5549{
5550 struct device *dev = hr_dev->dev;
5551 int ret;
5552
5553 if (eqn < hr_dev->caps.num_comp_vectors)
5554 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5555 0, HNS_ROCE_CMD_DESTROY_CEQC,
5556 HNS_ROCE_CMD_TIMEOUT_MSECS);
5557 else
5558 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5559 0, HNS_ROCE_CMD_DESTROY_AEQC,
5560 HNS_ROCE_CMD_TIMEOUT_MSECS);
5561 if (ret)
5562 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5563}
5564
d7e2d343 5565static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
a5073d60 5566{
477a0a38 5567 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
a5073d60
YL		 5568}
5569
477a0a38
XW		 5570static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
5571 void *mb_buf)
a5073d60 5572{
477a0a38 5573 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
a5073d60 5574 struct hns_roce_eq_context *eqc;
477a0a38 5575 u64 bt_ba = 0;
d7e2d343 5576 int count;
a5073d60
YL		 5577
5578 eqc = mb_buf;
5579 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5580
5581 /* init eqc */
5582 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
a5073d60
YL		 5583 eq->cons_index = 0;
5584 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5585 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5586 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
a5073d60
YL		 5587 eq->shift = ilog2((unsigned int)eq->entries);
5588
cc23267a 5589 /* if not multi-hop, eqe buffer only use one trunk */
477a0a38
XW		 5590 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
5591 &bt_ba);
5592 if (count < 1) {
5593 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
5594 return -ENOBUFS;
d7e2d343 5595 }
a5073d60
YL		 5596
5597 /* set eqc state */
60262b10 5598 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S,
a5073d60
YL		 5599 HNS_ROCE_V2_EQ_STATE_VALID);
5600
5601 /* set eqe hop num */
60262b10 5602 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M,
a5073d60
YL		 5603 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
5604
5605 /* set eqc over_ignore */
60262b10 5606 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M,
a5073d60
YL		 5607 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
5608
5609 /* set eqc coalesce */
60262b10 5610 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M,
a5073d60
YL		 5611 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
5612
5613 /* set eqc arm_state */
60262b10 5614 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M,
a5073d60
YL		 5615 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
5616
5617 /* set eqn */
60262b10
LO		 5618 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S,
5619 eq->eqn);
a5073d60
YL		 5620
5621 /* set eqe_cnt */
60262b10
LO		 5622 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M,
5623 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT);
a5073d60
YL		 5624
5625 /* set eqe_ba_pg_sz */
60262b10 5626 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db 5627 HNS_ROCE_EQC_BA_PG_SZ_S,
477a0a38 5628 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
a5073d60
YL		 5629
5630 /* set eqe_buf_pg_sz */
60262b10 5631 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db 5632 HNS_ROCE_EQC_BUF_PG_SZ_S,
477a0a38 5633 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
a5073d60
YL		 5634
5635 /* set eq_producer_idx */
60262b10
LO		 5636 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M,
5637 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX);
a5073d60
YL		 5638
5639 /* set eq_max_cnt */
60262b10 5640 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M,
a5073d60
YL		 5641 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
5642
5643 /* set eq_period */
60262b10 5644 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M,
a5073d60
YL		 5645 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
5646
5647 /* set eqe_report_timer */
60262b10 5648 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M,
a5073d60
YL		 5649 HNS_ROCE_EQC_REPORT_TIMER_S,
5650 HNS_ROCE_EQ_INIT_REPORT_TIMER);
5651
477a0a38 5652 /* set bt_ba [34:3] */
60262b10 5653 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M,
477a0a38 5654 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3);
a5073d60 5655
477a0a38 5656 /* set bt_ba [64:35] */
60262b10 5657 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M,
477a0a38 5658 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35);
a5073d60
YL		 5659
5660 /* set eq shift */
60262b10
LO		 5661 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S,
5662 eq->shift);
a5073d60
YL		 5663
5664 /* set eq MSI_IDX */
60262b10
LO		 5665 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M,
5666 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX);
a5073d60
YL		 5667
5668 /* set cur_eqe_ba [27:12] */
60262b10 5669 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M,
477a0a38 5670 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12);
a5073d60
YL		 5671
5672 /* set cur_eqe_ba [59:28] */
60262b10 5673 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M,
477a0a38 5674 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28);
a5073d60
YL		 5675
5676 /* set cur_eqe_ba [63:60] */
60262b10 5677 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M,
477a0a38 5678 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60);
a5073d60
YL		 5679
5680 /* set eq consumer idx */
60262b10
LO		 5681 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
5682 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
a5073d60 5683
247fc16d 5684 roce_set_field(eqc->byte_40, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
477a0a38 5685 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
a5073d60 5686
247fc16d 5687 roce_set_field(eqc->byte_44, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
477a0a38 5688 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
a5073d60 5689
247fc16d
WL		 5690 roce_set_field(eqc->byte_44, HNS_ROCE_EQC_EQE_SIZE_M,
5691 HNS_ROCE_EQC_EQE_SIZE_S,
5692 eq->eqe_size == HNS_ROCE_V3_EQE_SIZE ? 1 : 0);
5693
477a0a38 5694 return 0;
d7e2d343 5695}
a5073d60 5696
d7e2d343
XW		 5697static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5698{
477a0a38
XW		 5699 struct hns_roce_buf_attr buf_attr = {};
5700 int err;
a5073d60 5701
477a0a38
XW		 5702 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
5703 eq->hop_num = 0;
5704 else
5705 eq->hop_num = hr_dev->caps.eqe_hop_num;
a5073d60 5706
9581a356 5707 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + HNS_HW_PAGE_SHIFT;
477a0a38
XW		 5708 buf_attr.region[0].size = eq->entries * eq->eqe_size;
5709 buf_attr.region[0].hopnum = eq->hop_num;
5710 buf_attr.region_count = 1;
5711 buf_attr.fixed_page = true;
d7e2d343 5712
477a0a38 5713 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
053c0acf 5714 hr_dev->caps.eqe_ba_pg_sz +
9581a356 5715 HNS_HW_PAGE_SHIFT, NULL, 0);
477a0a38
XW		 5716 if (err)
5717 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err);
a5073d60 5718
477a0a38 5719 return err;
a5073d60
YL		 5720}
5721
5722static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5723 struct hns_roce_eq *eq,
5724 unsigned int eq_cmd)
5725{
a5073d60 5726 struct hns_roce_cmd_mailbox *mailbox;
a5073d60
YL		 5727 int ret;
5728
5729 /* Allocate mailbox memory */
5730 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
477a0a38
XW		 5731 if (IS_ERR_OR_NULL(mailbox))
5732 return -ENOMEM;
a5073d60 5733
d7e2d343 5734 ret = alloc_eq_buf(hr_dev, eq);
477a0a38 5735 if (ret)
d7e2d343 5736 goto free_cmd_mbox;
477a0a38
XW		 5737
5738 ret = config_eqc(hr_dev, eq, mailbox->buf);
5739 if (ret)
5740 goto err_cmd_mbox;
a5073d60
YL		 5741
5742 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5743 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5744 if (ret) {
d7e2d343 5745 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5746 goto err_cmd_mbox;
5747 }
5748
5749 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5750
5751 return 0;
5752
5753err_cmd_mbox:
d7e2d343 5754 free_eq_buf(hr_dev, eq);
a5073d60
YL		 5755
5756free_cmd_mbox:
5757 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5758
5759 return ret;
5760}
5761
33db6f94
YL		 5762static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
5763 int comp_num, int aeq_num, int other_num)
5764{
5765 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5766 int i, j;
5767 int ret;
5768
5769 for (i = 0; i < irq_num; i++) {
5770 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5771 GFP_KERNEL);
5772 if (!hr_dev->irq_names[i]) {
5773 ret = -ENOMEM;
5774 goto err_kzalloc_failed;
5775 }
5776 }
5777
6def7de6 5778 /* irq contains: abnormal + AEQ + CEQ */
bebdb83f 5779 for (j = 0; j < other_num; j++)
60262b10
LO		 5780 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5781 "hns-abn-%d", j);
bebdb83f
LC		 5782
5783 for (j = other_num; j < (other_num + aeq_num); j++)
60262b10
LO		 5784 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5785 "hns-aeq-%d", j - other_num);
bebdb83f
LC		 5786
5787 for (j = (other_num + aeq_num); j < irq_num; j++)
60262b10
LO		 5788 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5789 "hns-ceq-%d", j - other_num - aeq_num);
33db6f94
YL		 5790
5791 for (j = 0; j < irq_num; j++) {
5792 if (j < other_num)
5793 ret = request_irq(hr_dev->irq[j],
5794 hns_roce_v2_msix_interrupt_abn,
5795 0, hr_dev->irq_names[j], hr_dev);
5796
5797 else if (j < (other_num + comp_num))
5798 ret = request_irq(eq_table->eq[j - other_num].irq,
5799 hns_roce_v2_msix_interrupt_eq,
5800 0, hr_dev->irq_names[j + aeq_num],
5801 &eq_table->eq[j - other_num]);
5802 else
5803 ret = request_irq(eq_table->eq[j - other_num].irq,
5804 hns_roce_v2_msix_interrupt_eq,
5805 0, hr_dev->irq_names[j - comp_num],
5806 &eq_table->eq[j - other_num]);
5807 if (ret) {
5808 dev_err(hr_dev->dev, "Request irq error!\n");
5809 goto err_request_failed;
5810 }
5811 }
5812
5813 return 0;
5814
5815err_request_failed:
5816 for (j -= 1; j >= 0; j--)
5817 if (j < other_num)
5818 free_irq(hr_dev->irq[j], hr_dev);
5819 else
5820 free_irq(eq_table->eq[j - other_num].irq,
5821 &eq_table->eq[j - other_num]);
5822
5823err_kzalloc_failed:
5824 for (i -= 1; i >= 0; i--)
5825 kfree(hr_dev->irq_names[i]);
5826
5827 return ret;
5828}
5829
5830static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
5831{
5832 int irq_num;
5833 int eq_num;
5834 int i;
5835
5836 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5837 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5838
5839 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5840 free_irq(hr_dev->irq[i], hr_dev);
5841
5842 for (i = 0; i < eq_num; i++)
5843 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
5844
5845 for (i = 0; i < irq_num; i++)
5846 kfree(hr_dev->irq_names[i]);
5847}
5848
a5073d60
YL		 5849static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5850{
5851 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5852 struct device *dev = hr_dev->dev;
5853 struct hns_roce_eq *eq;
5854 unsigned int eq_cmd;
5855 int irq_num;
5856 int eq_num;
5857 int other_num;
5858 int comp_num;
5859 int aeq_num;
33db6f94 5860 int i;
a5073d60
YL		 5861 int ret;
5862
5863 other_num = hr_dev->caps.num_other_vectors;
5864 comp_num = hr_dev->caps.num_comp_vectors;
5865 aeq_num = hr_dev->caps.num_aeq_vectors;
5866
5867 eq_num = comp_num + aeq_num;
5868 irq_num = eq_num + other_num;
5869
5870 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5871 if (!eq_table->eq)
5872 return -ENOMEM;
5873
a5073d60 5874 /* create eq */
33db6f94
YL		 5875 for (i = 0; i < eq_num; i++) {
5876 eq = &eq_table->eq[i];
a5073d60 5877 eq->hr_dev = hr_dev;
33db6f94
YL		 5878 eq->eqn = i;
5879 if (i < comp_num) {
a5073d60
YL		 5880 /* CEQ */
5881 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5882 eq->type_flag = HNS_ROCE_CEQ;
5883 eq->entries = hr_dev->caps.ceqe_depth;
247fc16d 5884 eq->eqe_size = hr_dev->caps.ceqe_size;
33db6f94 5885 eq->irq = hr_dev->irq[i + other_num + aeq_num];
a5073d60
YL		 5886 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5887 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5888 } else {
5889 /* AEQ */
5890 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5891 eq->type_flag = HNS_ROCE_AEQ;
5892 eq->entries = hr_dev->caps.aeqe_depth;
247fc16d 5893 eq->eqe_size = hr_dev->caps.aeqe_size;
33db6f94 5894 eq->irq = hr_dev->irq[i - comp_num + other_num];
a5073d60
YL		 5895 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5896 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5897 }
5898
5899 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5900 if (ret) {
5901 dev_err(dev, "eq create failed.\n");
5902 goto err_create_eq_fail;
5903 }
5904 }
5905
5906 /* enable irq */
5907 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5908
33db6f94
YL		 5909 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num,
5910 aeq_num, other_num);
5911 if (ret) {
5912 dev_err(dev, "Request irq failed.\n");
5913 goto err_request_irq_fail;
a5073d60
YL		 5914 }
5915
ffd541d4 5916 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
0425e3e6
YL		 5917 if (!hr_dev->irq_workq) {
5918 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5919 ret = -ENOMEM;
33db6f94 5920 goto err_create_wq_fail;
0425e3e6
YL		 5921 }
5922
a5073d60
YL		 5923 return 0;
5924
33db6f94
YL		 5925err_create_wq_fail:
5926 __hns_roce_free_irq(hr_dev);
5927
a5073d60 5928err_request_irq_fail:
33db6f94 5929 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
a5073d60
YL		 5930
5931err_create_eq_fail:
a5073d60 5932 for (i -= 1; i >= 0; i--)
d7e2d343 5933 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5934 kfree(eq_table->eq);
5935
5936 return ret;
5937}
5938
5939static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5940{
5941 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
a5073d60
YL		 5942 int eq_num;
5943 int i;
5944
5945 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
a5073d60
YL		 5946
5947 /* Disable irq */
5948 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5949
33db6f94 5950 __hns_roce_free_irq(hr_dev);
a5073d60
YL		 5951
5952 for (i = 0; i < eq_num; i++) {
5953 hns_roce_v2_destroy_eqc(hr_dev, i);
5954
d7e2d343 5955 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5956 }
5957
a5073d60 5958 kfree(eq_table->eq);
0425e3e6
YL		 5959
5960 flush_workqueue(hr_dev->irq_workq);
5961 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5962}
5963
e1c9a0dc
LO		 5964static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = {
5965 .query_cqc_info = hns_roce_v2_query_cqc_info,
5966};
5967
7f645a58
KH		 5968static const struct ib_device_ops hns_roce_v2_dev_ops = {
5969 .destroy_qp = hns_roce_v2_destroy_qp,
5970 .modify_cq = hns_roce_v2_modify_cq,
5971 .poll_cq = hns_roce_v2_poll_cq,
5972 .post_recv = hns_roce_v2_post_recv,
5973 .post_send = hns_roce_v2_post_send,
5974 .query_qp = hns_roce_v2_query_qp,
5975 .req_notify_cq = hns_roce_v2_req_notify_cq,
5976};
5977
5978static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
5979 .modify_srq = hns_roce_v2_modify_srq,
5980 .post_srq_recv = hns_roce_v2_post_srq_recv,
5981 .query_srq = hns_roce_v2_query_srq,
5982};
5983
a04ff739
WHX		 5984static const struct hns_roce_hw hns_roce_hw_v2 = {
5985 .cmq_init = hns_roce_v2_cmq_init,
5986 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5987 .hw_profile = hns_roce_v2_profile,
6b63597d 5988 .hw_init = hns_roce_v2_init,
5989 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5990 .post_mbox = hns_roce_v2_post_mbox,
5991 .chk_mbox = hns_roce_v2_chk_mbox,
6a04aed6 5992 .rst_prc_mbox = hns_roce_v2_rst_process_cmd,
7afddafa
WHX		 5993 .set_gid = hns_roce_v2_set_gid,
5994 .set_mac = hns_roce_v2_set_mac,
3958cc56 5995 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5996 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 5997 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 5998 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 5999 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 6000 .set_hem = hns_roce_v2_set_hem,
6001 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 6002 .modify_qp = hns_roce_v2_modify_qp,
6003 .query_qp = hns_roce_v2_query_qp,
6004 .destroy_qp = hns_roce_v2_destroy_qp,
aa84fa18 6005 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
b156269d 6006 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 6007 .post_send = hns_roce_v2_post_send,
6008 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 6009 .req_notify_cq = hns_roce_v2_req_notify_cq,
6010 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 6011 .init_eq = hns_roce_v2_init_eq_table,
6012 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
c7bcb134
LO		 6013 .write_srqc = hns_roce_v2_write_srqc,
6014 .modify_srq = hns_roce_v2_modify_srq,
6015 .query_srq = hns_roce_v2_query_srq,
6016 .post_srq_recv = hns_roce_v2_post_srq_recv,
7f645a58
KH		 6017 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6018 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
a04ff739 6019};
dd74282d
WHX		 6020
6021static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6022 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6023 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 6024 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6025 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 6026 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6027 /* required last entry */
6028 {0, }
6029};
6030
f97a62c3 6031MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6032
301cc7eb 6033static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
dd74282d
WHX		 6034 struct hnae3_handle *handle)
6035{
d061effc 6036 struct hns_roce_v2_priv *priv = hr_dev->priv;
a5073d60 6037 int i;
dd74282d 6038
301cc7eb
LC		 6039 hr_dev->pci_dev = handle->pdev;
6040 hr_dev->dev = &handle->pdev->dev;
dd74282d 6041 hr_dev->hw = &hns_roce_hw_v2;
e1c9a0dc 6042 hr_dev->dfx = &hns_roce_dfx_hw_v2;
2d407888
WHX		 6043 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6044 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 6045
6046 /* Get info from NIC driver. */
6047 hr_dev->reg_base = handle->rinfo.roce_io_base;
6048 hr_dev->caps.num_ports = 1;
6049 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6050 hr_dev->iboe.phy_port[0] = 0;
6051
d4994d2f 6052 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6053 hr_dev->iboe.netdevs[0]->dev_addr);
6054
a5073d60
YL		 6055 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
6056 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6057 i + handle->rinfo.base_vector);
6058
dd74282d 6059 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 6060 hr_dev->cmd_mod = 1;
dd74282d
WHX		 6061 hr_dev->loop_idc = 0;
6062
d061effc
WHX		 6063 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6064 priv->handle = handle;
dd74282d
WHX		 6065}
6066
d061effc 6067static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
dd74282d
WHX		 6068{
6069 struct hns_roce_dev *hr_dev;
6070 int ret;
6071
459cc69f 6072 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
dd74282d
WHX		 6073 if (!hr_dev)
6074 return -ENOMEM;
6075
a04ff739
WHX		 6076 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6077 if (!hr_dev->priv) {
6078 ret = -ENOMEM;
6079 goto error_failed_kzalloc;
6080 }
6081
301cc7eb 6082 hns_roce_hw_v2_get_cfg(hr_dev, handle);
dd74282d
WHX		 6083
6084 ret = hns_roce_init(hr_dev);
6085 if (ret) {
6086 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6087 goto error_failed_get_cfg;
6088 }
6089
d061effc
WHX		 6090 handle->priv = hr_dev;
6091
dd74282d
WHX		 6092 return 0;
6093
6094error_failed_get_cfg:
a04ff739
WHX		 6095 kfree(hr_dev->priv);
6096
6097error_failed_kzalloc:
dd74282d
WHX		 6098 ib_dealloc_device(&hr_dev->ib_dev);
6099
6100 return ret;
6101}
6102
d061effc 6103static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
dd74282d
WHX		 6104 bool reset)
6105{
14ba8730 6106 struct hns_roce_dev *hr_dev = handle->priv;
dd74282d 6107
cb7a94c9
WHX		 6108 if (!hr_dev)
6109 return;
6110
d061effc 6111 handle->priv = NULL;
626903e9
XW		 6112
6113 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6114 hns_roce_handle_device_err(hr_dev);
6115
dd74282d 6116 hns_roce_exit(hr_dev);
a04ff739 6117 kfree(hr_dev->priv);
dd74282d
WHX		 6118 ib_dealloc_device(&hr_dev->ib_dev);
6119}
6120
d061effc
WHX		 6121static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6122{
6123 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
07c2339a 6124 const struct pci_device_id *id;
d061effc
WHX		 6125 struct device *dev = &handle->pdev->dev;
6126 int ret;
6127
6128 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6129
6130 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6131 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6132 goto reset_chk_err;
6133 }
6134
07c2339a
LO		 6135 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6136 if (!id)
6137 return 0;
6138
d061effc
WHX		 6139 ret = __hns_roce_hw_v2_init_instance(handle);
6140 if (ret) {
6141 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6142 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6143 if (ops->ae_dev_resetting(handle) ||
6144 ops->get_hw_reset_stat(handle))
6145 goto reset_chk_err;
6146 else
6147 return ret;
6148 }
6149
6150 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6151
6152
6153 return 0;
6154
6155reset_chk_err:
6156 dev_err(dev, "Device is busy in resetting state.\n"
6157 "please retry later.\n");
6158
6159 return -EBUSY;
6160}
6161
6162static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6163 bool reset)
6164{
6165 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6166 return;
6167
6168 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6169
6170 __hns_roce_hw_v2_uninit_instance(handle, reset);
6171
6172 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6173}
cb7a94c9
WHX		 6174static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6175{
d061effc 6176 struct hns_roce_dev *hr_dev;
cb7a94c9 6177
d061effc
WHX		 6178 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6179 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6180 return 0;
cb7a94c9
WHX		 6181 }
6182
d061effc
WHX		 6183 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6184 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6185
14ba8730 6186 hr_dev = handle->priv;
d061effc
WHX		 6187 if (!hr_dev)
6188 return 0;
6189
726be12f 6190 hr_dev->is_reset = true;
cb7a94c9 6191 hr_dev->active = false;
d3743fa9 6192 hr_dev->dis_db = true;
cb7a94c9 6193
626903e9 6194 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
cb7a94c9
WHX		 6195
6196 return 0;
6197}
6198
6199static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6200{
d061effc 6201 struct device *dev = &handle->pdev->dev;
cb7a94c9
WHX		 6202 int ret;
6203
d061effc
WHX		 6204 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6205 &handle->rinfo.state)) {
6206 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6207 return 0;
6208 }
6209
6210 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6211
6212 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6213 ret = __hns_roce_hw_v2_init_instance(handle);
cb7a94c9
WHX		 6214 if (ret) {
6215 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6216 * callback function, RoCE Engine reinitialize. If RoCE reinit
6217 * failed, we should inform NIC driver.
6218 */
6219 handle->priv = NULL;
d061effc
WHX		 6220 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6221 } else {
6222 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6223 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
cb7a94c9
WHX		 6224 }
6225
6226 return ret;
6227}
6228
6229static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6230{
d061effc
WHX		 6231 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6232 return 0;
6233
6234 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6235 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
90c559b1 6236 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
d061effc
WHX		 6237 __hns_roce_hw_v2_uninit_instance(handle, false);
6238
cb7a94c9
WHX		 6239 return 0;
6240}
6241
6242static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6243 enum hnae3_reset_notify_type type)
6244{
6245 int ret = 0;
6246
6247 switch (type) {
6248 case HNAE3_DOWN_CLIENT:
6249 ret = hns_roce_hw_v2_reset_notify_down(handle);
6250 break;
6251 case HNAE3_INIT_CLIENT:
6252 ret = hns_roce_hw_v2_reset_notify_init(handle);
6253 break;
6254 case HNAE3_UNINIT_CLIENT:
6255 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6256 break;
6257 default:
6258 break;
6259 }
6260
6261 return ret;
6262}
6263
dd74282d
WHX		 6264static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6265 .init_instance = hns_roce_hw_v2_init_instance,
6266 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 6267 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 6268};
6269
6270static struct hnae3_client hns_roce_hw_v2_client = {
6271 .name = "hns_roce_hw_v2",
6272 .type = HNAE3_CLIENT_ROCE,
6273 .ops = &hns_roce_hw_v2_ops,
6274};
6275
6276static int __init hns_roce_hw_v2_init(void)
6277{
6278 return hnae3_register_client(&hns_roce_hw_v2_client);
6279}
6280
6281static void __exit hns_roce_hw_v2_exit(void)
6282{
6283 hnae3_unregister_client(&hns_roce_hw_v2_client);
6284}
6285
6286module_init(hns_roce_hw_v2_init);
6287module_exit(hns_roce_hw_v2_exit);
6288
6289MODULE_LICENSE("Dual BSD/GPL");
6290MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6291MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6292MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6293MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)