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RDMA/hns: Add enable judgement for UD vlan
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
dd74282d
WHX		 40#include <rdma/ib_umem.h>
41
42#include "hnae3.h"
43#include "hns_roce_common.h"
44#include "hns_roce_device.h"
45#include "hns_roce_cmd.h"
46#include "hns_roce_hem.h"
a04ff739 47#include "hns_roce_hw_v2.h"
dd74282d 48
2d407888
WHX		 49static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
50 struct ib_sge *sg)
51{
52 dseg->lkey = cpu_to_le32(sg->lkey);
53 dseg->addr = cpu_to_le64(sg->addr);
54 dseg->len = cpu_to_le32(sg->length);
55}
56
384f8818
LO		 57static void set_atomic_seg(struct hns_roce_wqe_atomic_seg *aseg,
58 const struct ib_atomic_wr *wr)
59{
60 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
61 aseg->fetchadd_swap_data = cpu_to_le64(wr->swap);
62 aseg->cmp_data = cpu_to_le64(wr->compare_add);
63 } else {
64 aseg->fetchadd_swap_data = cpu_to_le64(wr->compare_add);
65 aseg->cmp_data = 0;
66 }
67}
68
f696bf6d 69static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
0b25c9cc
WHX		 70 unsigned int *sge_ind)
71{
72 struct hns_roce_v2_wqe_data_seg *dseg;
73 struct ib_sge *sg;
74 int num_in_wqe = 0;
75 int extend_sge_num;
76 int fi_sge_num;
77 int se_sge_num;
78 int shift;
79 int i;
80
81 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
82 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
83 extend_sge_num = wr->num_sge - num_in_wqe;
84 sg = wr->sg_list + num_in_wqe;
85 shift = qp->hr_buf.page_shift;
86
87 /*
88 * Check whether wr->num_sge sges are in the same page. If not, we
89 * should calculate how many sges in the first page and the second
90 * page.
91 */
92 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
93 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
94 (uintptr_t)dseg) /
95 sizeof(struct hns_roce_v2_wqe_data_seg);
96 if (extend_sge_num > fi_sge_num) {
97 se_sge_num = extend_sge_num - fi_sge_num;
98 for (i = 0; i < fi_sge_num; i++) {
99 set_data_seg_v2(dseg++, sg + i);
100 (*sge_ind)++;
101 }
102 dseg = get_send_extend_sge(qp,
103 (*sge_ind) & (qp->sge.sge_cnt - 1));
104 for (i = 0; i < se_sge_num; i++) {
105 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
106 (*sge_ind)++;
107 }
108 } else {
109 for (i = 0; i < extend_sge_num; i++) {
110 set_data_seg_v2(dseg++, sg + i);
111 (*sge_ind)++;
112 }
113 }
114}
115
f696bf6d 116static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 117 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
118 void *wqe, unsigned int *sge_ind,
d34ac5cd 119 const struct ib_send_wr **bad_wr)
7bdee415 120{
121 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
122 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
123 struct hns_roce_qp *qp = to_hr_qp(ibqp);
124 int i;
125
126 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 127 if (le32_to_cpu(rc_sq_wqe->msg_len) >
128 hr_dev->caps.max_sq_inline) {
7bdee415 129 *bad_wr = wr;
130 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
131 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
132 return -EINVAL;
133 }
134
328d405b 135 if (wr->opcode == IB_WR_RDMA_READ) {
136 dev_err(hr_dev->dev, "Not support inline data!\n");
137 return -EINVAL;
138 }
139
7bdee415 140 for (i = 0; i < wr->num_sge; i++) {
141 memcpy(wqe, ((void *)wr->sg_list[i].addr),
142 wr->sg_list[i].length);
143 wqe += wr->sg_list[i].length;
144 }
145
146 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
147 1);
148 } else {
0b25c9cc 149 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 150 for (i = 0; i < wr->num_sge; i++) {
151 if (likely(wr->sg_list[i].length)) {
152 set_data_seg_v2(dseg, wr->sg_list + i);
153 dseg++;
154 }
155 }
156 } else {
157 roce_set_field(rc_sq_wqe->byte_20,
158 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
159 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
160 (*sge_ind) & (qp->sge.sge_cnt - 1));
161
0b25c9cc 162 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 163 if (likely(wr->sg_list[i].length)) {
164 set_data_seg_v2(dseg, wr->sg_list + i);
165 dseg++;
166 }
167 }
168
0b25c9cc 169 set_extend_sge(qp, wr, sge_ind);
7bdee415 170 }
171
172 roce_set_field(rc_sq_wqe->byte_16,
173 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
174 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
175 }
176
177 return 0;
178}
179
0425e3e6
YL		 180static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
181 const struct ib_qp_attr *attr,
182 int attr_mask, enum ib_qp_state cur_state,
183 enum ib_qp_state new_state);
184
d34ac5cd
BVA		 185static int hns_roce_v2_post_send(struct ib_qp *ibqp,
186 const struct ib_send_wr *wr,
187 const struct ib_send_wr **bad_wr)
2d407888
WHX		 188{
189 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
7bdee415 190 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
191 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
2d407888
WHX		 192 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
193 struct hns_roce_qp *qp = to_hr_qp(ibqp);
384f8818 194 struct hns_roce_v2_wqe_data_seg *dseg;
2d407888
WHX		 195 struct device *dev = hr_dev->dev;
196 struct hns_roce_v2_db sq_db;
0425e3e6 197 struct ib_qp_attr attr;
2d407888 198 unsigned int sge_ind = 0;
e8d18533 199 unsigned int owner_bit;
2d407888
WHX		 200 unsigned long flags;
201 unsigned int ind;
202 void *wqe = NULL;
7bdee415 203 bool loopback;
0425e3e6 204 int attr_mask;
55ba49cb 205 u32 tmp_len;
2d407888 206 int ret = 0;
b9c1ea40 207 u32 hr_op;
7bdee415 208 u8 *smac;
2d407888
WHX		 209 int nreq;
210 int i;
211
7bdee415 212 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
213 ibqp->qp_type != IB_QPT_GSI &&
214 ibqp->qp_type != IB_QPT_UD)) {
2d407888 215 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
137ae320 216 *bad_wr = wr;
2d407888
WHX		 217 return -EOPNOTSUPP;
218 }
219
10bd2ade
YL		 220 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT ||
221 qp->state == IB_QPS_RTR)) {
2d407888
WHX		 222 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
223 *bad_wr = wr;
224 return -EINVAL;
225 }
226
227 spin_lock_irqsave(&qp->sq.lock, flags);
228 ind = qp->sq_next_wqe;
229 sge_ind = qp->next_sge;
230
231 for (nreq = 0; wr; ++nreq, wr = wr->next) {
232 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
233 ret = -ENOMEM;
234 *bad_wr = wr;
235 goto out;
236 }
237
238 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
239 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
240 wr->num_sge, qp->sq.max_gs);
241 ret = -EINVAL;
242 *bad_wr = wr;
243 goto out;
244 }
245
246 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
247 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
248 wr->wr_id;
249
634f6390 250 owner_bit =
251 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
55ba49cb 252 tmp_len = 0;
2d407888 253
7bdee415 254 /* Corresponding to the QP type, wqe process separately */
255 if (ibqp->qp_type == IB_QPT_GSI) {
256 ud_sq_wqe = wqe;
257 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
258
259 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
260 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
261 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
262 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
263 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
264 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
265 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
266 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
267 roce_set_field(ud_sq_wqe->byte_48,
268 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
269 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
270 ah->av.mac[4]);
271 roce_set_field(ud_sq_wqe->byte_48,
272 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
273 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
274 ah->av.mac[5]);
275
276 /* MAC loopback */
277 smac = (u8 *)hr_dev->dev_addr[qp->port];
278 loopback = ether_addr_equal_unaligned(ah->av.mac,
279 smac) ? 1 : 0;
280
281 roce_set_bit(ud_sq_wqe->byte_40,
282 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
283
284 roce_set_field(ud_sq_wqe->byte_4,
285 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
286 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
287 HNS_ROCE_V2_WQE_OP_SEND);
2d407888 288
7bdee415 289 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 290 tmp_len += wr->sg_list[i].length;
492b2bd0 291
8b9b8d14 292 ud_sq_wqe->msg_len =
293 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len);
294
295 switch (wr->opcode) {
296 case IB_WR_SEND_WITH_IMM:
297 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 298 ud_sq_wqe->immtdata =
299 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 300 break;
301 default:
302 ud_sq_wqe->immtdata = 0;
303 break;
304 }
651487c2 305
7bdee415 306 /* Set sig attr */
307 roce_set_bit(ud_sq_wqe->byte_4,
308 V2_UD_SEND_WQE_BYTE_4_CQE_S,
309 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
a49d761f 310
7bdee415 311 /* Set se attr */
312 roce_set_bit(ud_sq_wqe->byte_4,
313 V2_UD_SEND_WQE_BYTE_4_SE_S,
314 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
e8d18533 315
7bdee415 316 roce_set_bit(ud_sq_wqe->byte_4,
317 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
318
319 roce_set_field(ud_sq_wqe->byte_16,
320 V2_UD_SEND_WQE_BYTE_16_PD_M,
321 V2_UD_SEND_WQE_BYTE_16_PD_S,
322 to_hr_pd(ibqp->pd)->pdn);
323
324 roce_set_field(ud_sq_wqe->byte_16,
325 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
326 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
327 wr->num_sge);
328
329 roce_set_field(ud_sq_wqe->byte_20,
330 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
331 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
332 sge_ind & (qp->sge.sge_cnt - 1));
333
334 roce_set_field(ud_sq_wqe->byte_24,
335 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
336 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
337 ud_sq_wqe->qkey =
8b9b8d14 338 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
339 qp->qkey : ud_wr(wr)->remote_qkey);
7bdee415 340 roce_set_field(ud_sq_wqe->byte_32,
341 V2_UD_SEND_WQE_BYTE_32_DQPN_M,
342 V2_UD_SEND_WQE_BYTE_32_DQPN_S,
343 ud_wr(wr)->remote_qpn);
344
345 roce_set_field(ud_sq_wqe->byte_36,
346 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
347 V2_UD_SEND_WQE_BYTE_36_VLAN_S,
8b9b8d14 348 le16_to_cpu(ah->av.vlan));
7bdee415 349 roce_set_field(ud_sq_wqe->byte_36,
350 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
351 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
352 ah->av.hop_limit);
353 roce_set_field(ud_sq_wqe->byte_36,
354 V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
355 V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
cdfa4ad5
LO		 356 ah->av.sl_tclass_flowlabel >>
357 HNS_ROCE_TCLASS_SHIFT);
7bdee415 358 roce_set_field(ud_sq_wqe->byte_40,
359 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
cdfa4ad5
LO		 360 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
361 ah->av.sl_tclass_flowlabel &
362 HNS_ROCE_FLOW_LABEL_MASK);
7bdee415 363 roce_set_field(ud_sq_wqe->byte_40,
364 V2_UD_SEND_WQE_BYTE_40_SL_M,
365 V2_UD_SEND_WQE_BYTE_40_SL_S,
8b9b8d14 366 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
367 HNS_ROCE_SL_SHIFT);
7bdee415 368 roce_set_field(ud_sq_wqe->byte_40,
369 V2_UD_SEND_WQE_BYTE_40_PORTN_M,
370 V2_UD_SEND_WQE_BYTE_40_PORTN_S,
371 qp->port);
372
8320deb8
LO		 373 roce_set_bit(ud_sq_wqe->byte_40,
374 V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
375 ah->av.vlan_en ? 1 : 0);
7bdee415 376 roce_set_field(ud_sq_wqe->byte_48,
377 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
378 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
379 hns_get_gid_index(hr_dev, qp->phy_port,
380 ah->av.gid_index));
381
382 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
383 GID_LEN_V2);
384
0b25c9cc 385 set_extend_sge(qp, wr, &sge_ind);
7bdee415 386 ind++;
387 } else if (ibqp->qp_type == IB_QPT_RC) {
388 rc_sq_wqe = wqe;
389 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
390 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 391 tmp_len += wr->sg_list[i].length;
392
393 rc_sq_wqe->msg_len =
394 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len);
7bdee415 395
8b9b8d14 396 switch (wr->opcode) {
397 case IB_WR_SEND_WITH_IMM:
398 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 399 rc_sq_wqe->immtdata =
400 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 401 break;
402 case IB_WR_SEND_WITH_INV:
403 rc_sq_wqe->inv_key =
404 cpu_to_le32(wr->ex.invalidate_rkey);
405 break;
406 default:
407 rc_sq_wqe->immtdata = 0;
408 break;
409 }
7bdee415 410
411 roce_set_bit(rc_sq_wqe->byte_4,
412 V2_RC_SEND_WQE_BYTE_4_FENCE_S,
413 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
414
415 roce_set_bit(rc_sq_wqe->byte_4,
416 V2_RC_SEND_WQE_BYTE_4_SE_S,
417 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
418
419 roce_set_bit(rc_sq_wqe->byte_4,
420 V2_RC_SEND_WQE_BYTE_4_CQE_S,
421 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
422
423 roce_set_bit(rc_sq_wqe->byte_4,
424 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
425
384f8818 426 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
7bdee415 427 switch (wr->opcode) {
428 case IB_WR_RDMA_READ:
b9c1ea40 429 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
7bdee415 430 rc_sq_wqe->rkey =
431 cpu_to_le32(rdma_wr(wr)->rkey);
432 rc_sq_wqe->va =
433 cpu_to_le64(rdma_wr(wr)->remote_addr);
434 break;
435 case IB_WR_RDMA_WRITE:
b9c1ea40 436 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
7bdee415 437 rc_sq_wqe->rkey =
438 cpu_to_le32(rdma_wr(wr)->rkey);
439 rc_sq_wqe->va =
440 cpu_to_le64(rdma_wr(wr)->remote_addr);
441 break;
442 case IB_WR_RDMA_WRITE_WITH_IMM:
b9c1ea40 443 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
7bdee415 444 rc_sq_wqe->rkey =
445 cpu_to_le32(rdma_wr(wr)->rkey);
446 rc_sq_wqe->va =
447 cpu_to_le64(rdma_wr(wr)->remote_addr);
448 break;
449 case IB_WR_SEND:
b9c1ea40 450 hr_op = HNS_ROCE_V2_WQE_OP_SEND;
7bdee415 451 break;
452 case IB_WR_SEND_WITH_INV:
b9c1ea40 453 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
7bdee415 454 break;
455 case IB_WR_SEND_WITH_IMM:
b9c1ea40 456 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
7bdee415 457 break;
458 case IB_WR_LOCAL_INV:
b9c1ea40 459 hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
7bdee415 460 break;
461 case IB_WR_ATOMIC_CMP_AND_SWP:
b9c1ea40 462 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
384f8818
LO		 463 rc_sq_wqe->rkey =
464 cpu_to_le32(atomic_wr(wr)->rkey);
465 rc_sq_wqe->va =
466 cpu_to_le32(atomic_wr(wr)->remote_addr);
467 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
468 set_atomic_seg(wqe, atomic_wr(wr));
7bdee415 469 break;
470 case IB_WR_ATOMIC_FETCH_AND_ADD:
b9c1ea40 471 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
384f8818
LO		 472 rc_sq_wqe->rkey =
473 cpu_to_le32(atomic_wr(wr)->rkey);
474 rc_sq_wqe->va =
475 cpu_to_le32(atomic_wr(wr)->remote_addr);
476 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
477 set_atomic_seg(wqe, atomic_wr(wr));
7bdee415 478 break;
479 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
b9c1ea40
LO		 480 hr_op =
481 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
7bdee415 482 break;
483 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
b9c1ea40
LO		 484 hr_op =
485 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
7bdee415 486 break;
487 default:
b9c1ea40 488 hr_op = HNS_ROCE_V2_WQE_OP_MASK;
7bdee415 489 break;
2d407888
WHX		 490 }
491
b9c1ea40
LO		 492 roce_set_field(rc_sq_wqe->byte_4,
493 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
494 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
384f8818
LO		 495 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
496 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
497 dseg =
498 wqe - sizeof(struct hns_roce_v2_wqe_data_seg);
499 else
500 dseg = wqe;
2d407888 501
7bdee415 502 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe,
503 &sge_ind, bad_wr);
504 if (ret)
505 goto out;
506 ind++;
2d407888 507 } else {
7bdee415 508 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
509 spin_unlock_irqrestore(&qp->sq.lock, flags);
137ae320 510 *bad_wr = wr;
7bdee415 511 return -EOPNOTSUPP;
2d407888 512 }
2d407888
WHX		 513 }
514
515out:
516 if (likely(nreq)) {
517 qp->sq.head += nreq;
518 /* Memory barrier */
519 wmb();
520
521 sq_db.byte_4 = 0;
522 sq_db.parameter = 0;
523
524 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
525 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
526 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
527 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
cc3391cb 528 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
529 V2_DB_PARAMETER_IDX_S,
2d407888
WHX		 530 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
531 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
532 V2_DB_PARAMETER_SL_S, qp->sl);
533
8b9b8d14 534 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l);
2d407888
WHX		 535
536 qp->sq_next_wqe = ind;
537 qp->next_sge = sge_ind;
0425e3e6
YL		 538
539 if (qp->state == IB_QPS_ERR) {
540 attr_mask = IB_QP_STATE;
541 attr.qp_state = IB_QPS_ERR;
542
543 ret = hns_roce_v2_modify_qp(&qp->ibqp, &attr, attr_mask,
544 qp->state, IB_QPS_ERR);
545 if (ret) {
546 spin_unlock_irqrestore(&qp->sq.lock, flags);
547 *bad_wr = wr;
548 return ret;
549 }
550 }
2d407888
WHX		 551 }
552
553 spin_unlock_irqrestore(&qp->sq.lock, flags);
554
555 return ret;
556}
557
d34ac5cd
BVA		 558static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
559 const struct ib_recv_wr *wr,
560 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 561{
562 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
563 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
564 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 565 struct hns_roce_rinl_sge *sge_list;
2d407888 566 struct device *dev = hr_dev->dev;
0425e3e6 567 struct ib_qp_attr attr;
2d407888
WHX		 568 unsigned long flags;
569 void *wqe = NULL;
0425e3e6 570 int attr_mask;
2d407888
WHX		 571 int ret = 0;
572 int nreq;
573 int ind;
574 int i;
575
576 spin_lock_irqsave(&hr_qp->rq.lock, flags);
577 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
578
ced07769 579 if (hr_qp->state == IB_QPS_RESET) {
2d407888
WHX		 580 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
581 *bad_wr = wr;
582 return -EINVAL;
583 }
584
585 for (nreq = 0; wr; ++nreq, wr = wr->next) {
586 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
587 hr_qp->ibqp.recv_cq)) {
588 ret = -ENOMEM;
589 *bad_wr = wr;
590 goto out;
591 }
592
593 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
594 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
595 wr->num_sge, hr_qp->rq.max_gs);
596 ret = -EINVAL;
597 *bad_wr = wr;
598 goto out;
599 }
600
601 wqe = get_recv_wqe(hr_qp, ind);
602 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
603 for (i = 0; i < wr->num_sge; i++) {
604 if (!wr->sg_list[i].length)
605 continue;
606 set_data_seg_v2(dseg, wr->sg_list + i);
607 dseg++;
608 }
609
610 if (i < hr_qp->rq.max_gs) {
778cc5a8 611 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
612 dseg->addr = 0;
2d407888
WHX		 613 }
614
0009c2db 615 /* rq support inline data */
ecaaf1e2 616 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
617 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
618 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
619 (u32)wr->num_sge;
620 for (i = 0; i < wr->num_sge; i++) {
621 sge_list[i].addr =
622 (void *)(u64)wr->sg_list[i].addr;
623 sge_list[i].len = wr->sg_list[i].length;
624 }
0009c2db 625 }
626
2d407888
WHX		 627 hr_qp->rq.wrid[ind] = wr->wr_id;
628
629 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
630 }
631
632out:
633 if (likely(nreq)) {
634 hr_qp->rq.head += nreq;
635 /* Memory barrier */
636 wmb();
637
472bc0fb 638 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
0425e3e6
YL		 639
640 if (hr_qp->state == IB_QPS_ERR) {
641 attr_mask = IB_QP_STATE;
642 attr.qp_state = IB_QPS_ERR;
643
644 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr,
645 attr_mask, hr_qp->state,
646 IB_QPS_ERR);
647 if (ret) {
648 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
649 *bad_wr = wr;
650 return ret;
651 }
652 }
2d407888
WHX		 653 }
654 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
655
656 return ret;
657}
658
a04ff739
WHX		 659static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
660{
661 int ntu = ring->next_to_use;
662 int ntc = ring->next_to_clean;
663 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
664
665 return ring->desc_num - used - 1;
666}
667
668static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
669 struct hns_roce_v2_cmq_ring *ring)
670{
671 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
672
673 ring->desc = kzalloc(size, GFP_KERNEL);
674 if (!ring->desc)
675 return -ENOMEM;
676
677 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
678 DMA_BIDIRECTIONAL);
679 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
680 ring->desc_dma_addr = 0;
681 kfree(ring->desc);
682 ring->desc = NULL;
683 return -ENOMEM;
684 }
685
686 return 0;
687}
688
689static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
690 struct hns_roce_v2_cmq_ring *ring)
691{
692 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
693 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
694 DMA_BIDIRECTIONAL);
90e7a4d5 695
696 ring->desc_dma_addr = 0;
a04ff739
WHX		 697 kfree(ring->desc);
698}
699
700static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
701{
702 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
703 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
704 &priv->cmq.csq : &priv->cmq.crq;
705
706 ring->flag = ring_type;
707 ring->next_to_clean = 0;
708 ring->next_to_use = 0;
709
710 return hns_roce_alloc_cmq_desc(hr_dev, ring);
711}
712
713static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
714{
715 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
716 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
717 &priv->cmq.csq : &priv->cmq.crq;
718 dma_addr_t dma = ring->desc_dma_addr;
719
720 if (ring_type == TYPE_CSQ) {
721 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
722 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
723 upper_32_bits(dma));
724 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
725 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
726 HNS_ROCE_CMQ_ENABLE);
727 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
728 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
729 } else {
730 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
731 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
732 upper_32_bits(dma));
733 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
734 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
735 HNS_ROCE_CMQ_ENABLE);
736 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
737 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
738 }
739}
740
741static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
742{
743 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
744 int ret;
745
746 /* Setup the queue entries for command queue */
426c4146
LO		 747 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
748 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 749
750 /* Setup the lock for command queue */
751 spin_lock_init(&priv->cmq.csq.lock);
752 spin_lock_init(&priv->cmq.crq.lock);
753
754 /* Setup Tx write back timeout */
755 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
756
757 /* Init CSQ */
758 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
759 if (ret) {
760 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
761 return ret;
762 }
763
764 /* Init CRQ */
765 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
766 if (ret) {
767 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
768 goto err_crq;
769 }
770
771 /* Init CSQ REG */
772 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
773
774 /* Init CRQ REG */
775 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
776
777 return 0;
778
779err_crq:
780 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
781
782 return ret;
783}
784
785static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
786{
787 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
788
789 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
790 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
791}
792
281d0ccf
CIK		 793static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
794 enum hns_roce_opcode_type opcode,
795 bool is_read)
a04ff739
WHX		 796{
797 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
798 desc->opcode = cpu_to_le16(opcode);
799 desc->flag =
800 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
801 if (is_read)
802 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
803 else
804 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
805}
806
807static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
808{
809 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
810 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
811
812 return head == priv->cmq.csq.next_to_use;
813}
814
815static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
816{
817 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
818 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
819 struct hns_roce_cmq_desc *desc;
820 u16 ntc = csq->next_to_clean;
821 u32 head;
822 int clean = 0;
823
824 desc = &csq->desc[ntc];
825 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
826 while (head != ntc) {
827 memset(desc, 0, sizeof(*desc));
828 ntc++;
829 if (ntc == csq->desc_num)
830 ntc = 0;
831 desc = &csq->desc[ntc];
832 clean++;
833 }
834 csq->next_to_clean = ntc;
835
836 return clean;
837}
838
281d0ccf
CIK		 839static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
840 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 841{
842 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
843 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
844 struct hns_roce_cmq_desc *desc_to_use;
845 bool complete = false;
846 u32 timeout = 0;
847 int handle = 0;
848 u16 desc_ret;
849 int ret = 0;
850 int ntc;
851
cb7a94c9
WHX		 852 if (hr_dev->is_reset)
853 return 0;
854
a04ff739
WHX		 855 spin_lock_bh(&csq->lock);
856
857 if (num > hns_roce_cmq_space(csq)) {
858 spin_unlock_bh(&csq->lock);
859 return -EBUSY;
860 }
861
862 /*
863 * Record the location of desc in the cmq for this time
864 * which will be use for hardware to write back
865 */
866 ntc = csq->next_to_use;
867
868 while (handle < num) {
869 desc_to_use = &csq->desc[csq->next_to_use];
870 *desc_to_use = desc[handle];
871 dev_dbg(hr_dev->dev, "set cmq desc:\n");
872 csq->next_to_use++;
873 if (csq->next_to_use == csq->desc_num)
874 csq->next_to_use = 0;
875 handle++;
876 }
877
878 /* Write to hardware */
879 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
880
881 /*
882 * If the command is sync, wait for the firmware to write back,
883 * if multi descriptors to be sent, use the first one to check
884 */
885 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
886 do {
887 if (hns_roce_cmq_csq_done(hr_dev))
888 break;
988e175b 889 udelay(1);
a04ff739
WHX		 890 timeout++;
891 } while (timeout < priv->cmq.tx_timeout);
892 }
893
894 if (hns_roce_cmq_csq_done(hr_dev)) {
895 complete = true;
896 handle = 0;
897 while (handle < num) {
898 /* get the result of hardware write back */
899 desc_to_use = &csq->desc[ntc];
900 desc[handle] = *desc_to_use;
901 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
902 desc_ret = desc[handle].retval;
903 if (desc_ret == CMD_EXEC_SUCCESS)
904 ret = 0;
905 else
906 ret = -EIO;
907 priv->cmq.last_status = desc_ret;
908 ntc++;
909 handle++;
910 if (ntc == csq->desc_num)
911 ntc = 0;
912 }
913 }
914
915 if (!complete)
916 ret = -EAGAIN;
917
918 /* clean the command send queue */
919 handle = hns_roce_cmq_csq_clean(hr_dev);
920 if (handle != num)
921 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
922 handle, num);
923
924 spin_unlock_bh(&csq->lock);
925
926 return ret;
927}
928
281d0ccf 929static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 930{
931 struct hns_roce_query_version *resp;
932 struct hns_roce_cmq_desc desc;
933 int ret;
934
935 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
936 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
937 if (ret)
938 return ret;
939
940 resp = (struct hns_roce_query_version *)desc.data;
941 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
942 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id);
943
944 return 0;
945}
946
947static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
948{
949 struct hns_roce_cfg_global_param *req;
950 struct hns_roce_cmq_desc desc;
951
952 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
953 false);
954
955 req = (struct hns_roce_cfg_global_param *)desc.data;
956 memset(req, 0, sizeof(*req));
957 roce_set_field(req->time_cfg_udp_port,
958 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
959 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
960 roce_set_field(req->time_cfg_udp_port,
961 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
962 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
963
964 return hns_roce_cmq_send(hr_dev, &desc, 1);
965}
966
967static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
968{
969 struct hns_roce_cmq_desc desc[2];
6b63597d 970 struct hns_roce_pf_res_a *req_a;
971 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 972 int ret;
973 int i;
974
975 for (i = 0; i < 2; i++) {
976 hns_roce_cmq_setup_basic_desc(&desc[i],
977 HNS_ROCE_OPC_QUERY_PF_RES, true);
978
979 if (i == 0)
980 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
981 else
982 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
983 }
984
985 ret = hns_roce_cmq_send(hr_dev, desc, 2);
986 if (ret)
987 return ret;
988
6b63597d 989 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
990 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 991
6b63597d 992 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 993 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
994 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 995 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 996 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
997 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 998 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 999 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1000 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1001 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1002 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1003 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1004
6b63597d 1005 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1006 PF_RES_DATA_3_PF_SL_NUM_M,
1007 PF_RES_DATA_3_PF_SL_NUM_S);
1008
cfc85f3e
WHX		 1009 return 0;
1010}
1011
1012static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1013{
1014 struct hns_roce_cmq_desc desc[2];
1015 struct hns_roce_vf_res_a *req_a;
1016 struct hns_roce_vf_res_b *req_b;
1017 int i;
1018
1019 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1020 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1021 memset(req_a, 0, sizeof(*req_a));
1022 memset(req_b, 0, sizeof(*req_b));
1023 for (i = 0; i < 2; i++) {
1024 hns_roce_cmq_setup_basic_desc(&desc[i],
1025 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1026
1027 if (i == 0)
1028 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1029 else
1030 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1031
1032 if (i == 0) {
1033 roce_set_field(req_a->vf_qpc_bt_idx_num,
1034 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1035 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1036 roce_set_field(req_a->vf_qpc_bt_idx_num,
1037 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1038 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
1039 HNS_ROCE_VF_QPC_BT_NUM);
1040
1041 roce_set_field(req_a->vf_srqc_bt_idx_num,
1042 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1043 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1044 roce_set_field(req_a->vf_srqc_bt_idx_num,
1045 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1046 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1047 HNS_ROCE_VF_SRQC_BT_NUM);
1048
1049 roce_set_field(req_a->vf_cqc_bt_idx_num,
1050 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1051 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1052 roce_set_field(req_a->vf_cqc_bt_idx_num,
1053 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1054 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
1055 HNS_ROCE_VF_CQC_BT_NUM);
1056
1057 roce_set_field(req_a->vf_mpt_bt_idx_num,
1058 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1059 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1060 roce_set_field(req_a->vf_mpt_bt_idx_num,
1061 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1062 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
1063 HNS_ROCE_VF_MPT_BT_NUM);
1064
1065 roce_set_field(req_a->vf_eqc_bt_idx_num,
1066 VF_RES_A_DATA_5_VF_EQC_IDX_M,
1067 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1068 roce_set_field(req_a->vf_eqc_bt_idx_num,
1069 VF_RES_A_DATA_5_VF_EQC_NUM_M,
1070 VF_RES_A_DATA_5_VF_EQC_NUM_S,
1071 HNS_ROCE_VF_EQC_NUM);
1072 } else {
1073 roce_set_field(req_b->vf_smac_idx_num,
1074 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1075 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1076 roce_set_field(req_b->vf_smac_idx_num,
1077 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1078 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
1079 HNS_ROCE_VF_SMAC_NUM);
1080
1081 roce_set_field(req_b->vf_sgid_idx_num,
1082 VF_RES_B_DATA_2_VF_SGID_IDX_M,
1083 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1084 roce_set_field(req_b->vf_sgid_idx_num,
1085 VF_RES_B_DATA_2_VF_SGID_NUM_M,
1086 VF_RES_B_DATA_2_VF_SGID_NUM_S,
1087 HNS_ROCE_VF_SGID_NUM);
1088
1089 roce_set_field(req_b->vf_qid_idx_sl_num,
1090 VF_RES_B_DATA_3_VF_QID_IDX_M,
1091 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1092 roce_set_field(req_b->vf_qid_idx_sl_num,
1093 VF_RES_B_DATA_3_VF_SL_NUM_M,
1094 VF_RES_B_DATA_3_VF_SL_NUM_S,
1095 HNS_ROCE_VF_SL_NUM);
1096 }
1097 }
1098
1099 return hns_roce_cmq_send(hr_dev, desc, 2);
1100}
1101
a81fba28
WHX		 1102static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1103{
1104 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1105 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1106 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1107 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
1108 struct hns_roce_cfg_bt_attr *req;
1109 struct hns_roce_cmq_desc desc;
1110
1111 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1112 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1113 memset(req, 0, sizeof(*req));
1114
1115 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1116 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1117 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1118 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1119 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1120 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1121 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1122 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1123 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1124
1125 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1126 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1127 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1128 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1129 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1130 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1131 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1132 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1133 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1134
1135 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1136 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1137 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1138 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1139 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1140 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1141 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1142 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1143 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1144
1145 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1146 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1147 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1148 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1149 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1150 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1151 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1152 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1153 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1154
1155 return hns_roce_cmq_send(hr_dev, &desc, 1);
1156}
1157
cfc85f3e
WHX		 1158static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1159{
1160 struct hns_roce_caps *caps = &hr_dev->caps;
1161 int ret;
1162
1163 ret = hns_roce_cmq_query_hw_info(hr_dev);
1164 if (ret) {
1165 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1166 ret);
1167 return ret;
1168 }
1169
1170 ret = hns_roce_config_global_param(hr_dev);
1171 if (ret) {
1172 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1173 ret);
2349fdd4 1174 return ret;
cfc85f3e
WHX		 1175 }
1176
1177 /* Get pf resource owned by every pf */
1178 ret = hns_roce_query_pf_resource(hr_dev);
1179 if (ret) {
1180 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1181 ret);
1182 return ret;
1183 }
1184
1185 ret = hns_roce_alloc_vf_resource(hr_dev);
1186 if (ret) {
1187 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
1188 ret);
1189 return ret;
1190 }
1191
1192 hr_dev->vendor_part_id = 0;
1193 hr_dev->sys_image_guid = 0;
1194
1195 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1196 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1197 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1198 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1199 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1200 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1201 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1202 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1203 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
a5073d60
YL		 1204 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1205 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1206 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
cfc85f3e
WHX		 1207 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1208 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1209 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1210 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1211 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1212 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1213 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1214 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1215 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1216 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1217 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 1218 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e
WHX		 1219 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1220 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1221 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1222 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1223 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1224 caps->reserved_lkey = 0;
1225 caps->reserved_pds = 0;
1226 caps->reserved_mrws = 1;
1227 caps->reserved_uars = 0;
1228 caps->reserved_cqs = 0;
1229
a25d13cb
SX		 1230 caps->qpc_ba_pg_sz = 0;
1231 caps->qpc_buf_pg_sz = 0;
1232 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1233 caps->srqc_ba_pg_sz = 0;
1234 caps->srqc_buf_pg_sz = 0;
1235 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
1236 caps->cqc_ba_pg_sz = 0;
1237 caps->cqc_buf_pg_sz = 0;
1238 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1239 caps->mpt_ba_pg_sz = 0;
1240 caps->mpt_buf_pg_sz = 0;
1241 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
ff795f71
WHX		 1242 caps->pbl_ba_pg_sz = 0;
1243 caps->pbl_buf_pg_sz = 0;
1244 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 1245 caps->mtt_ba_pg_sz = 0;
1246 caps->mtt_buf_pg_sz = 0;
1247 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1248 caps->cqe_ba_pg_sz = 0;
1249 caps->cqe_buf_pg_sz = 0;
1250 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
a5073d60
YL		 1251 caps->eqe_ba_pg_sz = 0;
1252 caps->eqe_buf_pg_sz = 0;
1253 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1254 caps->tsq_buf_pg_sz = 0;
29a1fe5d 1255 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 1256
023c1477 1257 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
0009c2db 1258 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
e088a685 1259 HNS_ROCE_CAP_FLAG_RQ_INLINE |
0425e3e6
YL		 1260 HNS_ROCE_CAP_FLAG_RECORD_DB |
1261 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
cfc85f3e 1262 caps->pkey_table_len[0] = 1;
b5ff0f61 1263 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
a5073d60
YL		 1264 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1265 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
cfc85f3e
WHX		 1266 caps->local_ca_ack_delay = 0;
1267 caps->max_mtu = IB_MTU_4096;
1268
384f8818
LO		 1269 if (hr_dev->pci_dev->revision == 0x21)
1270 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC;
1271
a81fba28
WHX		 1272 ret = hns_roce_v2_set_bt(hr_dev);
1273 if (ret)
1274 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
1275 ret);
1276
1277 return ret;
cfc85f3e
WHX		 1278}
1279
6b63597d 1280static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
1281 enum hns_roce_link_table_type type)
1282{
1283 struct hns_roce_cmq_desc desc[2];
1284 struct hns_roce_cfg_llm_a *req_a =
1285 (struct hns_roce_cfg_llm_a *)desc[0].data;
1286 struct hns_roce_cfg_llm_b *req_b =
1287 (struct hns_roce_cfg_llm_b *)desc[1].data;
1288 struct hns_roce_v2_priv *priv = hr_dev->priv;
1289 struct hns_roce_link_table *link_tbl;
1290 struct hns_roce_link_table_entry *entry;
1291 enum hns_roce_opcode_type opcode;
1292 u32 page_num;
1293 int i;
1294
1295 switch (type) {
1296 case TSQ_LINK_TABLE:
1297 link_tbl = &priv->tsq;
1298 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
1299 break;
ded58ff9 1300 case TPQ_LINK_TABLE:
1301 link_tbl = &priv->tpq;
1302 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
1303 break;
6b63597d 1304 default:
1305 return -EINVAL;
1306 }
1307
1308 page_num = link_tbl->npages;
1309 entry = link_tbl->table.buf;
1310 memset(req_a, 0, sizeof(*req_a));
1311 memset(req_b, 0, sizeof(*req_b));
1312
1313 for (i = 0; i < 2; i++) {
1314 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
1315
1316 if (i == 0)
1317 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1318 else
1319 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1320
1321 if (i == 0) {
1322 req_a->base_addr_l = link_tbl->table.map & 0xffffffff;
1323 req_a->base_addr_h = (link_tbl->table.map >> 32) &
1324 0xffffffff;
1325 roce_set_field(req_a->depth_pgsz_init_en,
1326 CFG_LLM_QUE_DEPTH_M,
1327 CFG_LLM_QUE_DEPTH_S,
1328 link_tbl->npages);
1329 roce_set_field(req_a->depth_pgsz_init_en,
1330 CFG_LLM_QUE_PGSZ_M,
1331 CFG_LLM_QUE_PGSZ_S,
1332 link_tbl->pg_sz);
1333 req_a->head_ba_l = entry[0].blk_ba0;
1334 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr;
1335 roce_set_field(req_a->head_ptr,
1336 CFG_LLM_HEAD_PTR_M,
1337 CFG_LLM_HEAD_PTR_S, 0);
1338 } else {
1339 req_b->tail_ba_l = entry[page_num - 1].blk_ba0;
1340 roce_set_field(req_b->tail_ba_h,
1341 CFG_LLM_TAIL_BA_H_M,
1342 CFG_LLM_TAIL_BA_H_S,
1343 entry[page_num - 1].blk_ba1_nxt_ptr &
1344 HNS_ROCE_LINK_TABLE_BA1_M);
1345 roce_set_field(req_b->tail_ptr,
1346 CFG_LLM_TAIL_PTR_M,
1347 CFG_LLM_TAIL_PTR_S,
1348 (entry[page_num - 2].blk_ba1_nxt_ptr &
1349 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
1350 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
1351 }
1352 }
1353 roce_set_field(req_a->depth_pgsz_init_en,
1354 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1);
1355
1356 return hns_roce_cmq_send(hr_dev, desc, 2);
1357}
1358
1359static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
1360 enum hns_roce_link_table_type type)
1361{
1362 struct hns_roce_v2_priv *priv = hr_dev->priv;
1363 struct hns_roce_link_table *link_tbl;
1364 struct hns_roce_link_table_entry *entry;
1365 struct device *dev = hr_dev->dev;
1366 u32 buf_chk_sz;
1367 dma_addr_t t;
ded58ff9 1368 int func_num = 1;
6b63597d 1369 int pg_num_a;
1370 int pg_num_b;
1371 int pg_num;
1372 int size;
1373 int i;
1374
1375 switch (type) {
1376 case TSQ_LINK_TABLE:
1377 link_tbl = &priv->tsq;
1378 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
1379 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
1380 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
1381 break;
ded58ff9 1382 case TPQ_LINK_TABLE:
1383 link_tbl = &priv->tpq;
1384 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
1385 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
1386 pg_num_b = 2 * 4 * func_num + 2;
1387 break;
6b63597d 1388 default:
1389 return -EINVAL;
1390 }
1391
1392 pg_num = max(pg_num_a, pg_num_b);
1393 size = pg_num * sizeof(struct hns_roce_link_table_entry);
1394
1395 link_tbl->table.buf = dma_alloc_coherent(dev, size,
1396 &link_tbl->table.map,
1397 GFP_KERNEL);
1398 if (!link_tbl->table.buf)
1399 goto out;
1400
1401 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
1402 GFP_KERNEL);
1403 if (!link_tbl->pg_list)
1404 goto err_kcalloc_failed;
1405
1406 entry = link_tbl->table.buf;
1407 for (i = 0; i < pg_num; ++i) {
1408 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
1409 &t, GFP_KERNEL);
1410 if (!link_tbl->pg_list[i].buf)
1411 goto err_alloc_buf_failed;
1412
1413 link_tbl->pg_list[i].map = t;
1414 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz);
1415
1416 entry[i].blk_ba0 = (t >> 12) & 0xffffffff;
1417 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1418 HNS_ROCE_LINK_TABLE_BA1_M,
1419 HNS_ROCE_LINK_TABLE_BA1_S,
1420 t >> 44);
1421
1422 if (i < (pg_num - 1))
1423 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1424 HNS_ROCE_LINK_TABLE_NXT_PTR_M,
1425 HNS_ROCE_LINK_TABLE_NXT_PTR_S,
1426 i + 1);
1427 }
1428 link_tbl->npages = pg_num;
1429 link_tbl->pg_sz = buf_chk_sz;
1430
1431 return hns_roce_config_link_table(hr_dev, type);
1432
1433err_alloc_buf_failed:
1434 for (i -= 1; i >= 0; i--)
1435 dma_free_coherent(dev, buf_chk_sz,
1436 link_tbl->pg_list[i].buf,
1437 link_tbl->pg_list[i].map);
1438 kfree(link_tbl->pg_list);
1439
1440err_kcalloc_failed:
1441 dma_free_coherent(dev, size, link_tbl->table.buf,
1442 link_tbl->table.map);
1443
1444out:
1445 return -ENOMEM;
1446}
1447
1448static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
1449 struct hns_roce_link_table *link_tbl)
1450{
1451 struct device *dev = hr_dev->dev;
1452 int size;
1453 int i;
1454
1455 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
1456
1457 for (i = 0; i < link_tbl->npages; ++i)
1458 if (link_tbl->pg_list[i].buf)
1459 dma_free_coherent(dev, link_tbl->pg_sz,
1460 link_tbl->pg_list[i].buf,
1461 link_tbl->pg_list[i].map);
1462 kfree(link_tbl->pg_list);
1463
1464 dma_free_coherent(dev, size, link_tbl->table.buf,
1465 link_tbl->table.map);
1466}
1467
1468static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
1469{
ded58ff9 1470 struct hns_roce_v2_priv *priv = hr_dev->priv;
6b63597d 1471 int ret;
1472
1473 /* TSQ includes SQ doorbell and ack doorbell */
1474 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 1475 if (ret) {
6b63597d 1476 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 1477 return ret;
1478 }
1479
1480 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
1481 if (ret) {
1482 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
1483 goto err_tpq_init_failed;
1484 }
1485
1486 return 0;
1487
1488err_tpq_init_failed:
1489 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 1490
1491 return ret;
1492}
1493
1494static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
1495{
1496 struct hns_roce_v2_priv *priv = hr_dev->priv;
1497
ded58ff9 1498 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 1499 hns_roce_free_link_table(hr_dev, &priv->tsq);
1500}
1501
a680f2f3
WHX		 1502static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
1503{
1504 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1505
1506 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
1507}
1508
1509static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
1510{
1511 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1512
1513 return status & HNS_ROCE_HW_MB_STATUS_MASK;
1514}
1515
1516static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1517 u64 out_param, u32 in_modifier, u8 op_modifier,
1518 u16 op, u16 token, int event)
1519{
1520 struct device *dev = hr_dev->dev;
cc4ed08b
BVA		 1521 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base +
1522 ROCEE_VF_MB_CFG0_REG);
a680f2f3
WHX		 1523 unsigned long end;
1524 u32 val0 = 0;
1525 u32 val1 = 0;
1526
1527 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1528 while (hns_roce_v2_cmd_pending(hr_dev)) {
1529 if (time_after(jiffies, end)) {
1530 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1531 (int)end);
1532 return -EAGAIN;
1533 }
1534 cond_resched();
1535 }
1536
1537 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK,
1538 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier);
1539 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK,
1540 HNS_ROCE_VF_MB4_CMD_SHIFT, op);
1541 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK,
1542 HNS_ROCE_VF_MB5_EVENT_SHIFT, event);
1543 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK,
1544 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token);
1545
71591d12
AS		 1546 writeq(in_param, hcr + 0);
1547 writeq(out_param, hcr + 2);
a680f2f3
WHX		 1548
1549 /* Memory barrier */
1550 wmb();
1551
71591d12
AS		 1552 writel(val0, hcr + 4);
1553 writel(val1, hcr + 5);
a680f2f3
WHX		 1554
1555 mmiowb();
1556
1557 return 0;
1558}
1559
1560static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1561 unsigned long timeout)
1562{
1563 struct device *dev = hr_dev->dev;
1564 unsigned long end = 0;
1565 u32 status;
1566
1567 end = msecs_to_jiffies(timeout) + jiffies;
1568 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1569 cond_resched();
1570
1571 if (hns_roce_v2_cmd_pending(hr_dev)) {
1572 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1573 return -ETIMEDOUT;
1574 }
1575
1576 status = hns_roce_v2_cmd_complete(hr_dev);
1577 if (status != 0x1) {
1578 dev_err(dev, "mailbox status 0x%x!\n", status);
1579 return -EBUSY;
1580 }
1581
1582 return 0;
1583}
1584
4db134a3 1585static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
1586 int gid_index, const union ib_gid *gid,
1587 enum hns_roce_sgid_type sgid_type)
1588{
1589 struct hns_roce_cmq_desc desc;
1590 struct hns_roce_cfg_sgid_tb *sgid_tb =
1591 (struct hns_roce_cfg_sgid_tb *)desc.data;
1592 u32 *p;
1593
1594 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
1595
1596 roce_set_field(sgid_tb->table_idx_rsv,
1597 CFG_SGID_TB_TABLE_IDX_M,
1598 CFG_SGID_TB_TABLE_IDX_S, gid_index);
1599 roce_set_field(sgid_tb->vf_sgid_type_rsv,
1600 CFG_SGID_TB_VF_SGID_TYPE_M,
1601 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
1602
1603 p = (u32 *)&gid->raw[0];
1604 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
1605
1606 p = (u32 *)&gid->raw[4];
1607 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
1608
1609 p = (u32 *)&gid->raw[8];
1610 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
1611
1612 p = (u32 *)&gid->raw[0xc];
1613 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
1614
1615 return hns_roce_cmq_send(hr_dev, &desc, 1);
1616}
1617
b5ff0f61 1618static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 1619 int gid_index, const union ib_gid *gid,
b5ff0f61 1620 const struct ib_gid_attr *attr)
7afddafa 1621{
b5ff0f61 1622 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 1623 int ret;
7afddafa 1624
b5ff0f61
WHX		 1625 if (!gid || !attr)
1626 return -EINVAL;
1627
1628 if (attr->gid_type == IB_GID_TYPE_ROCE)
1629 sgid_type = GID_TYPE_FLAG_ROCE_V1;
1630
1631 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
1632 if (ipv6_addr_v4mapped((void *)gid))
1633 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
1634 else
1635 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
1636 }
1637
4db134a3 1638 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
1639 if (ret)
1640 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);
b5ff0f61 1641
4db134a3 1642 return ret;
7afddafa
WHX		 1643}
1644
a74dc41d
WHX		 1645static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1646 u8 *addr)
7afddafa 1647{
e8e8b652 1648 struct hns_roce_cmq_desc desc;
1649 struct hns_roce_cfg_smac_tb *smac_tb =
1650 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 1651 u16 reg_smac_h;
1652 u32 reg_smac_l;
e8e8b652 1653
1654 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 1655
1656 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 1657 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 1658
e8e8b652 1659 memset(smac_tb, 0, sizeof(*smac_tb));
1660 roce_set_field(smac_tb->tb_idx_rsv,
1661 CFG_SMAC_TB_IDX_M,
1662 CFG_SMAC_TB_IDX_S, phy_port);
1663 roce_set_field(smac_tb->vf_smac_h_rsv,
1664 CFG_SMAC_TB_VF_SMAC_H_M,
1665 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
1666 smac_tb->vf_smac_l = reg_smac_l;
a74dc41d 1667
e8e8b652 1668 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 1669}
1670
3958cc56
WHX		 1671static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1672 unsigned long mtpt_idx)
1673{
1674 struct hns_roce_v2_mpt_entry *mpt_entry;
1675 struct scatterlist *sg;
db270c41 1676 u64 page_addr;
3958cc56 1677 u64 *pages;
db270c41
WHX		 1678 int i, j;
1679 int len;
3958cc56 1680 int entry;
3958cc56
WHX		 1681
1682 mpt_entry = mb_buf;
1683 memset(mpt_entry, 0, sizeof(*mpt_entry));
1684
1685 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1686 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
1687 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1688 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
1689 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
1690 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1691 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 1692 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1693 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1694 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1695 V2_MPT_BYTE_4_PD_S, mr->pd);
1696 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
1697
1698 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
1699 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1700 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0);
1701 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
1702 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 1703 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
1704 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 1705 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1706 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1707 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1708 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1709 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1710 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1711 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
1712
1713 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
1714 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 1715 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
1716 1);
3958cc56
WHX		 1717 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
1718
1719 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
1720 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
1721 mpt_entry->lkey = cpu_to_le32(mr->key);
1722 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
1723 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
1724
1725 if (mr->type == MR_TYPE_DMA)
1726 return 0;
1727
1728 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1729
1730 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1731 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1732 V2_MPT_BYTE_48_PBL_BA_H_S,
1733 upper_32_bits(mr->pbl_ba >> 3));
1734 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
1735
1736 pages = (u64 *)__get_free_page(GFP_KERNEL);
1737 if (!pages)
1738 return -ENOMEM;
1739
1740 i = 0;
1741 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
db270c41
WHX		 1742 len = sg_dma_len(sg) >> PAGE_SHIFT;
1743 for (j = 0; j < len; ++j) {
1744 page_addr = sg_dma_address(sg) +
1745 (j << mr->umem->page_shift);
1746 pages[i] = page_addr >> 6;
1747
1748 /* Record the first 2 entry directly to MTPT table */
1749 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1750 goto found;
1751 i++;
1752 }
3958cc56
WHX		 1753 }
1754
db270c41 1755found:
3958cc56
WHX		 1756 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1757 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1758 V2_MPT_BYTE_56_PA0_H_S,
1759 upper_32_bits(pages[0]));
1760 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
1761
1762 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
1763 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
1764 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
1765
1766 free_page((unsigned long)pages);
1767
1768 roce_set_field(mpt_entry->byte_64_buf_pa1,
1769 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
5e6e78db
YL		 1770 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1771 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1772 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
1773
1774 return 0;
1775}
1776
a2c80b7b
WHX		 1777static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
1778 struct hns_roce_mr *mr, int flags,
1779 u32 pdn, int mr_access_flags, u64 iova,
1780 u64 size, void *mb_buf)
1781{
1782 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
1783
1784 if (flags & IB_MR_REREG_PD) {
1785 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1786 V2_MPT_BYTE_4_PD_S, pdn);
1787 mr->pd = pdn;
1788 }
1789
1790 if (flags & IB_MR_REREG_ACCESS) {
1791 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1792 V2_MPT_BYTE_8_BIND_EN_S,
1793 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
1794 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1795 V2_MPT_BYTE_8_ATOMIC_EN_S,
1796 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
1797 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1798 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
1799 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1800 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1801 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1802 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1803 }
1804
1805 if (flags & IB_MR_REREG_TRANS) {
1806 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
1807 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
1808 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
1809 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
1810
1811 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1812 mpt_entry->pbl_ba_l =
1813 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1814 roce_set_field(mpt_entry->byte_48_mode_ba,
1815 V2_MPT_BYTE_48_PBL_BA_H_M,
1816 V2_MPT_BYTE_48_PBL_BA_H_S,
1817 upper_32_bits(mr->pbl_ba >> 3));
1818 mpt_entry->byte_48_mode_ba =
1819 cpu_to_le32(mpt_entry->byte_48_mode_ba);
1820
1821 mr->iova = iova;
1822 mr->size = size;
1823 }
1824
1825 return 0;
1826}
1827
93aa2187
WHX		 1828static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1829{
1830 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1831 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
1832}
1833
1834static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1835{
1836 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
1837
1838 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1839 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
1840 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
1841}
1842
1843static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
1844{
1845 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
1846}
1847
1848static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1849{
86188a88 1850 *hr_cq->set_ci_db = cons_index & 0xffffff;
93aa2187
WHX		 1851}
1852
926a01dc
WHX		 1853static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1854 struct hns_roce_srq *srq)
1855{
1856 struct hns_roce_v2_cqe *cqe, *dest;
1857 u32 prod_index;
1858 int nfreed = 0;
1859 u8 owner_bit;
1860
1861 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
1862 ++prod_index) {
1863 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1864 break;
1865 }
1866
1867 /*
1868 * Now backwards through the CQ, removing CQ entries
1869 * that match our QP by overwriting them with next entries.
1870 */
1871 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1872 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1873 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
1874 V2_CQE_BYTE_16_LCL_QPN_S) &
1875 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
1876 /* In v1 engine, not support SRQ */
1877 ++nfreed;
1878 } else if (nfreed) {
1879 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
1880 hr_cq->ib_cq.cqe);
1881 owner_bit = roce_get_bit(dest->byte_4,
1882 V2_CQE_BYTE_4_OWNER_S);
1883 memcpy(dest, cqe, sizeof(*cqe));
1884 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
1885 owner_bit);
1886 }
1887 }
1888
1889 if (nfreed) {
1890 hr_cq->cons_index += nfreed;
1891 /*
1892 * Make sure update of buffer contents is done before
1893 * updating consumer index.
1894 */
1895 wmb();
1896 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
1897 }
1898}
1899
1900static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1901 struct hns_roce_srq *srq)
1902{
1903 spin_lock_irq(&hr_cq->lock);
1904 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
1905 spin_unlock_irq(&hr_cq->lock);
1906}
1907
93aa2187
WHX		 1908static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
1909 struct hns_roce_cq *hr_cq, void *mb_buf,
1910 u64 *mtts, dma_addr_t dma_handle, int nent,
1911 u32 vector)
1912{
1913 struct hns_roce_v2_cq_context *cq_context;
1914
1915 cq_context = mb_buf;
1916 memset(cq_context, 0, sizeof(*cq_context));
1917
1918 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
1919 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 1920 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
1921 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187
WHX		 1922 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
1923 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
1924 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
1925 V2_CQC_BYTE_4_CEQN_S, vector);
1926 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
1927
1928 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
1929 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
1930
1931 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
1932 cq_context->cqe_cur_blk_addr =
1933 cpu_to_le32(cq_context->cqe_cur_blk_addr);
1934
1935 roce_set_field(cq_context->byte_16_hop_addr,
1936 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
1937 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
1938 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
1939 roce_set_field(cq_context->byte_16_hop_addr,
1940 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
1941 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
1942 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
1943
1944 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
1945 roce_set_field(cq_context->byte_24_pgsz_addr,
1946 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
1947 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
1948 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
1949 roce_set_field(cq_context->byte_24_pgsz_addr,
1950 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
1951 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 1952 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 1953 roce_set_field(cq_context->byte_24_pgsz_addr,
1954 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
1955 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 1956 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 1957
1958 cq_context->cqe_ba = (u32)(dma_handle >> 3);
1959
1960 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
1961 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 1962
9b44703d
YL		 1963 if (hr_cq->db_en)
1964 roce_set_bit(cq_context->byte_44_db_record,
1965 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
1966
1967 roce_set_field(cq_context->byte_44_db_record,
1968 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
1969 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
1970 ((u32)hr_cq->db.dma) >> 1);
1971 cq_context->db_record_addr = hr_cq->db.dma >> 32;
1972
a5073d60
YL		 1973 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
1974 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
1975 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
1976 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
1977 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
1978 V2_CQC_BYTE_56_CQ_PERIOD_M,
1979 V2_CQC_BYTE_56_CQ_PERIOD_S,
1980 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 1981}
1982
1983static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
1984 enum ib_cq_notify_flags flags)
1985{
1986 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1987 u32 notification_flag;
1988 u32 doorbell[2];
1989
1990 doorbell[0] = 0;
1991 doorbell[1] = 0;
1992
1993 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
1994 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
1995 /*
1996 * flags = 0; Notification Flag = 1, next
1997 * flags = 1; Notification Flag = 0, solocited
1998 */
1999 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2000 hr_cq->cqn);
2001 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2002 HNS_ROCE_V2_CQ_DB_NTR);
2003 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2004 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2005 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2006 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2007 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2008 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2009 notification_flag);
2010
2011 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2012
2013 return 0;
2014}
2015
0009c2db 2016static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2017 struct hns_roce_qp **cur_qp,
2018 struct ib_wc *wc)
2019{
2020 struct hns_roce_rinl_sge *sge_list;
2021 u32 wr_num, wr_cnt, sge_num;
2022 u32 sge_cnt, data_len, size;
2023 void *wqe_buf;
2024
2025 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2026 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2027 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2028
2029 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2030 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
2031 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt);
2032 data_len = wc->byte_len;
2033
2034 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2035 size = min(sge_list[sge_cnt].len, data_len);
2036 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2037
2038 data_len -= size;
2039 wqe_buf += size;
2040 }
2041
2042 if (data_len) {
2043 wc->status = IB_WC_LOC_LEN_ERR;
2044 return -EAGAIN;
2045 }
2046
2047 return 0;
2048}
2049
93aa2187
WHX		 2050static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2051 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2052{
2053 struct hns_roce_dev *hr_dev;
2054 struct hns_roce_v2_cqe *cqe;
2055 struct hns_roce_qp *hr_qp;
2056 struct hns_roce_wq *wq;
0425e3e6
YL		 2057 struct ib_qp_attr attr;
2058 int attr_mask;
93aa2187
WHX		 2059 int is_send;
2060 u16 wqe_ctr;
2061 u32 opcode;
2062 u32 status;
2063 int qpn;
0009c2db 2064 int ret;
93aa2187
WHX		 2065
2066 /* Find cqe according to consumer index */
2067 cqe = next_cqe_sw_v2(hr_cq);
2068 if (!cqe)
2069 return -EAGAIN;
2070
2071 ++hr_cq->cons_index;
2072 /* Memory barrier */
2073 rmb();
2074
2075 /* 0->SQ, 1->RQ */
2076 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2077
2078 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2079 V2_CQE_BYTE_16_LCL_QPN_S);
2080
2081 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2082 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2083 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2084 if (unlikely(!hr_qp)) {
2085 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
2086 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
2087 return -EINVAL;
2088 }
2089 *cur_qp = hr_qp;
2090 }
2091
2092 wc->qp = &(*cur_qp)->ibqp;
2093 wc->vendor_err = 0;
2094
2095 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
2096 V2_CQE_BYTE_4_STATUS_S);
2097 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
2098 case HNS_ROCE_CQE_V2_SUCCESS:
2099 wc->status = IB_WC_SUCCESS;
2100 break;
2101 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
2102 wc->status = IB_WC_LOC_LEN_ERR;
2103 break;
2104 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
2105 wc->status = IB_WC_LOC_QP_OP_ERR;
2106 break;
2107 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
2108 wc->status = IB_WC_LOC_PROT_ERR;
2109 break;
2110 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
2111 wc->status = IB_WC_WR_FLUSH_ERR;
2112 break;
2113 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
2114 wc->status = IB_WC_MW_BIND_ERR;
2115 break;
2116 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
2117 wc->status = IB_WC_BAD_RESP_ERR;
2118 break;
2119 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
2120 wc->status = IB_WC_LOC_ACCESS_ERR;
2121 break;
2122 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
2123 wc->status = IB_WC_REM_INV_REQ_ERR;
2124 break;
2125 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
2126 wc->status = IB_WC_REM_ACCESS_ERR;
2127 break;
2128 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
2129 wc->status = IB_WC_REM_OP_ERR;
2130 break;
2131 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
2132 wc->status = IB_WC_RETRY_EXC_ERR;
2133 break;
2134 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
2135 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2136 break;
2137 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
2138 wc->status = IB_WC_REM_ABORT_ERR;
2139 break;
2140 default:
2141 wc->status = IB_WC_GENERAL_ERR;
2142 break;
2143 }
2144
0425e3e6
YL		 2145 /* flush cqe if wc status is error, excluding flush error */
2146 if ((wc->status != IB_WC_SUCCESS) &&
2147 (wc->status != IB_WC_WR_FLUSH_ERR)) {
2148 attr_mask = IB_QP_STATE;
2149 attr.qp_state = IB_QPS_ERR;
2150 return hns_roce_v2_modify_qp(&(*cur_qp)->ibqp,
2151 &attr, attr_mask,
2152 (*cur_qp)->state, IB_QPS_ERR);
2153 }
2154
2155 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 2156 return 0;
2157
2158 if (is_send) {
2159 wc->wc_flags = 0;
2160 /* SQ corresponding to CQE */
2161 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2162 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
2163 case HNS_ROCE_SQ_OPCODE_SEND:
2164 wc->opcode = IB_WC_SEND;
2165 break;
2166 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
2167 wc->opcode = IB_WC_SEND;
2168 break;
2169 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
2170 wc->opcode = IB_WC_SEND;
2171 wc->wc_flags |= IB_WC_WITH_IMM;
2172 break;
2173 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
2174 wc->opcode = IB_WC_RDMA_READ;
2175 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2176 break;
2177 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
2178 wc->opcode = IB_WC_RDMA_WRITE;
2179 break;
2180 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
2181 wc->opcode = IB_WC_RDMA_WRITE;
2182 wc->wc_flags |= IB_WC_WITH_IMM;
2183 break;
2184 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
2185 wc->opcode = IB_WC_LOCAL_INV;
2186 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2187 break;
2188 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
2189 wc->opcode = IB_WC_COMP_SWAP;
2190 wc->byte_len = 8;
2191 break;
2192 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
2193 wc->opcode = IB_WC_FETCH_ADD;
2194 wc->byte_len = 8;
2195 break;
2196 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
2197 wc->opcode = IB_WC_MASKED_COMP_SWAP;
2198 wc->byte_len = 8;
2199 break;
2200 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
2201 wc->opcode = IB_WC_MASKED_FETCH_ADD;
2202 wc->byte_len = 8;
2203 break;
2204 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
2205 wc->opcode = IB_WC_REG_MR;
2206 break;
2207 case HNS_ROCE_SQ_OPCODE_BIND_MW:
2208 wc->opcode = IB_WC_REG_MR;
2209 break;
2210 default:
2211 wc->status = IB_WC_GENERAL_ERR;
2212 break;
2213 }
2214
2215 wq = &(*cur_qp)->sq;
2216 if ((*cur_qp)->sq_signal_bits) {
2217 /*
2218 * If sg_signal_bit is 1,
2219 * firstly tail pointer updated to wqe
2220 * which current cqe correspond to
2221 */
2222 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
2223 V2_CQE_BYTE_4_WQE_INDX_M,
2224 V2_CQE_BYTE_4_WQE_INDX_S);
2225 wq->tail += (wqe_ctr - (u16)wq->tail) &
2226 (wq->wqe_cnt - 1);
2227 }
2228
2229 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2230 ++wq->tail;
2231 } else {
2232 /* RQ correspond to CQE */
2233 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2234
2235 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2236 V2_CQE_BYTE_4_OPCODE_S);
2237 switch (opcode & 0x1f) {
2238 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
2239 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2240 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2241 wc->ex.imm_data =
2242 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2243 break;
2244 case HNS_ROCE_V2_OPCODE_SEND:
2245 wc->opcode = IB_WC_RECV;
2246 wc->wc_flags = 0;
2247 break;
2248 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
2249 wc->opcode = IB_WC_RECV;
2250 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2251 wc->ex.imm_data =
2252 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2253 break;
2254 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
2255 wc->opcode = IB_WC_RECV;
2256 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 2257 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 2258 break;
2259 default:
2260 wc->status = IB_WC_GENERAL_ERR;
2261 break;
2262 }
2263
0009c2db 2264 if ((wc->qp->qp_type == IB_QPT_RC ||
2265 wc->qp->qp_type == IB_QPT_UC) &&
2266 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
2267 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
2268 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
2269 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
2270 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
2271 if (ret)
2272 return -EAGAIN;
2273 }
2274
93aa2187
WHX		 2275 /* Update tail pointer, record wr_id */
2276 wq = &(*cur_qp)->rq;
2277 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2278 ++wq->tail;
2279
2280 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
2281 V2_CQE_BYTE_32_SL_S);
2282 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
2283 V2_CQE_BYTE_32_RMT_QPN_M,
2284 V2_CQE_BYTE_32_RMT_QPN_S);
2285 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
2286 V2_CQE_BYTE_32_GRH_S) ?
2287 IB_WC_GRH : 0);
6c1f08b3 2288 wc->port_num = roce_get_field(cqe->byte_32,
2289 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
2290 wc->pkey_index = 0;
2eade675 2291 memcpy(wc->smac, cqe->smac, 4);
2292 wc->smac[4] = roce_get_field(cqe->byte_28,
2293 V2_CQE_BYTE_28_SMAC_4_M,
2294 V2_CQE_BYTE_28_SMAC_4_S);
2295 wc->smac[5] = roce_get_field(cqe->byte_28,
2296 V2_CQE_BYTE_28_SMAC_5_M,
2297 V2_CQE_BYTE_28_SMAC_5_S);
944e6409
LO		 2298 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
2299 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
2300 V2_CQE_BYTE_28_VID_M,
2301 V2_CQE_BYTE_28_VID_S);
2302 } else {
2303 wc->vlan_id = 0xffff;
2304 }
2305
2eade675 2306 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
2307 wc->network_hdr_type = roce_get_field(cqe->byte_28,
2308 V2_CQE_BYTE_28_PORT_TYPE_M,
2309 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 2310 }
2311
2312 return 0;
2313}
2314
2315static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
2316 struct ib_wc *wc)
2317{
2318 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2319 struct hns_roce_qp *cur_qp = NULL;
2320 unsigned long flags;
2321 int npolled;
2322
2323 spin_lock_irqsave(&hr_cq->lock, flags);
2324
2325 for (npolled = 0; npolled < num_entries; ++npolled) {
2326 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
2327 break;
2328 }
2329
2330 if (npolled) {
2331 /* Memory barrier */
2332 wmb();
2333 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2334 }
2335
2336 spin_unlock_irqrestore(&hr_cq->lock, flags);
2337
2338 return npolled;
2339}
2340
a81fba28
WHX		 2341static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
2342 struct hns_roce_hem_table *table, int obj,
2343 int step_idx)
2344{
2345 struct device *dev = hr_dev->dev;
2346 struct hns_roce_cmd_mailbox *mailbox;
2347 struct hns_roce_hem_iter iter;
2348 struct hns_roce_hem_mhop mhop;
2349 struct hns_roce_hem *hem;
2350 unsigned long mhop_obj = obj;
2351 int i, j, k;
2352 int ret = 0;
2353 u64 hem_idx = 0;
2354 u64 l1_idx = 0;
2355 u64 bt_ba = 0;
2356 u32 chunk_ba_num;
2357 u32 hop_num;
2358 u16 op = 0xff;
2359
2360 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2361 return 0;
2362
2363 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
2364 i = mhop.l0_idx;
2365 j = mhop.l1_idx;
2366 k = mhop.l2_idx;
2367 hop_num = mhop.hop_num;
2368 chunk_ba_num = mhop.bt_chunk_size / 8;
2369
2370 if (hop_num == 2) {
2371 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
2372 k;
2373 l1_idx = i * chunk_ba_num + j;
2374 } else if (hop_num == 1) {
2375 hem_idx = i * chunk_ba_num + j;
2376 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
2377 hem_idx = i;
2378 }
2379
2380 switch (table->type) {
2381 case HEM_TYPE_QPC:
2382 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
2383 break;
2384 case HEM_TYPE_MTPT:
2385 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
2386 break;
2387 case HEM_TYPE_CQC:
2388 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
2389 break;
2390 case HEM_TYPE_SRQC:
2391 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
2392 break;
2393 default:
2394 dev_warn(dev, "Table %d not to be written by mailbox!\n",
2395 table->type);
2396 return 0;
2397 }
2398 op += step_idx;
2399
2400 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2401 if (IS_ERR(mailbox))
2402 return PTR_ERR(mailbox);
2403
2404 if (check_whether_last_step(hop_num, step_idx)) {
2405 hem = table->hem[hem_idx];
2406 for (hns_roce_hem_first(hem, &iter);
2407 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
2408 bt_ba = hns_roce_hem_addr(&iter);
2409
2410 /* configure the ba, tag, and op */
2411 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
2412 obj, 0, op,
2413 HNS_ROCE_CMD_TIMEOUT_MSECS);
2414 }
2415 } else {
2416 if (step_idx == 0)
2417 bt_ba = table->bt_l0_dma_addr[i];
2418 else if (step_idx == 1 && hop_num == 2)
2419 bt_ba = table->bt_l1_dma_addr[l1_idx];
2420
2421 /* configure the ba, tag, and op */
2422 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
2423 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
2424 }
2425
2426 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2427 return ret;
2428}
2429
2430static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
2431 struct hns_roce_hem_table *table, int obj,
2432 int step_idx)
2433{
2434 struct device *dev = hr_dev->dev;
2435 struct hns_roce_cmd_mailbox *mailbox;
2436 int ret = 0;
2437 u16 op = 0xff;
2438
2439 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2440 return 0;
2441
2442 switch (table->type) {
2443 case HEM_TYPE_QPC:
2444 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
2445 break;
2446 case HEM_TYPE_MTPT:
2447 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
2448 break;
2449 case HEM_TYPE_CQC:
2450 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
2451 break;
2452 case HEM_TYPE_SRQC:
2453 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
2454 break;
2455 default:
2456 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
2457 table->type);
2458 return 0;
2459 }
2460 op += step_idx;
2461
2462 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2463 if (IS_ERR(mailbox))
2464 return PTR_ERR(mailbox);
2465
2466 /* configure the tag and op */
2467 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
2468 HNS_ROCE_CMD_TIMEOUT_MSECS);
2469
2470 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2471 return ret;
2472}
2473
926a01dc
WHX		 2474static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
2475 struct hns_roce_mtt *mtt,
2476 enum ib_qp_state cur_state,
2477 enum ib_qp_state new_state,
2478 struct hns_roce_v2_qp_context *context,
2479 struct hns_roce_qp *hr_qp)
2480{
2481 struct hns_roce_cmd_mailbox *mailbox;
2482 int ret;
2483
2484 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2485 if (IS_ERR(mailbox))
2486 return PTR_ERR(mailbox);
2487
2488 memcpy(mailbox->buf, context, sizeof(*context) * 2);
2489
2490 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2491 HNS_ROCE_CMD_MODIFY_QPC,
2492 HNS_ROCE_CMD_TIMEOUT_MSECS);
2493
2494 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2495
2496 return ret;
2497}
2498
ace1c541 2499static void set_access_flags(struct hns_roce_qp *hr_qp,
2500 struct hns_roce_v2_qp_context *context,
2501 struct hns_roce_v2_qp_context *qpc_mask,
2502 const struct ib_qp_attr *attr, int attr_mask)
2503{
2504 u8 dest_rd_atomic;
2505 u32 access_flags;
2506
c2799119 2507 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 2508 attr->max_dest_rd_atomic : hr_qp->resp_depth;
2509
c2799119 2510 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 2511 attr->qp_access_flags : hr_qp->atomic_rd_en;
2512
2513 if (!dest_rd_atomic)
2514 access_flags &= IB_ACCESS_REMOTE_WRITE;
2515
2516 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2517 !!(access_flags & IB_ACCESS_REMOTE_READ));
2518 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
2519
2520 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2521 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
2522 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
2523
2524 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2525 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
2526 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
2527}
2528
926a01dc
WHX		 2529static void modify_qp_reset_to_init(struct ib_qp *ibqp,
2530 const struct ib_qp_attr *attr,
0fa95a9a 2531 int attr_mask,
926a01dc
WHX		 2532 struct hns_roce_v2_qp_context *context,
2533 struct hns_roce_v2_qp_context *qpc_mask)
2534{
ecaaf1e2 2535 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 2536 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2537
2538 /*
2539 * In v2 engine, software pass context and context mask to hardware
2540 * when modifying qp. If software need modify some fields in context,
2541 * we should set all bits of the relevant fields in context mask to
2542 * 0 at the same time, else set them to 0x1.
2543 */
2544 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2545 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2546 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2547 V2_QPC_BYTE_4_TST_S, 0);
2548
0fa95a9a 2549 if (ibqp->qp_type == IB_QPT_GSI)
2550 roce_set_field(context->byte_4_sqpn_tst,
2551 V2_QPC_BYTE_4_SGE_SHIFT_M,
2552 V2_QPC_BYTE_4_SGE_SHIFT_S,
2553 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2554 else
2555 roce_set_field(context->byte_4_sqpn_tst,
2556 V2_QPC_BYTE_4_SGE_SHIFT_M,
2557 V2_QPC_BYTE_4_SGE_SHIFT_S,
2558 hr_qp->sq.max_gs > 2 ?
2559 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2560
926a01dc
WHX		 2561 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2562 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2563
2564 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2565 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2566 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2567 V2_QPC_BYTE_4_SQPN_S, 0);
2568
2569 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2570 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2571 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2572 V2_QPC_BYTE_16_PD_S, 0);
2573
2574 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2575 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
2576 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2577 V2_QPC_BYTE_20_RQWS_S, 0);
2578
2579 roce_set_field(context->byte_20_smac_sgid_idx,
2580 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2581 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2582 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2583 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2584
2585 roce_set_field(context->byte_20_smac_sgid_idx,
2586 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2587 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2588 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2589 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2590
2591 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 2592 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2593 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
2594 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2595 V2_QPC_BYTE_24_VLAN_ID_S, 0);
926a01dc
WHX		 2596
2597 /*
2598 * Set some fields in context to zero, Because the default values
2599 * of all fields in context are zero, we need not set them to 0 again.
2600 * but we should set the relevant fields of context mask to 0.
2601 */
2602 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
2603 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
2604 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
2605 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
2606
2607 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M,
2608 V2_QPC_BYTE_60_MAPID_S, 0);
2609
2610 roce_set_bit(qpc_mask->byte_60_qpst_mapid,
2611 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0);
2612 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S,
2613 0);
2614 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S,
2615 0);
2616 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S,
2617 0);
2618 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S,
2619 0);
2620 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S,
2621 0);
2622 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
2623 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
2624
0fa95a9a 2625 if (attr_mask & IB_QP_QKEY) {
2626 context->qkey_xrcd = attr->qkey;
2627 qpc_mask->qkey_xrcd = 0;
2628 hr_qp->qkey = attr->qkey;
2629 }
2630
e088a685
YL		 2631 if (hr_qp->rdb_en) {
2632 roce_set_bit(context->byte_68_rq_db,
2633 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
2634 roce_set_bit(qpc_mask->byte_68_rq_db,
2635 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0);
2636 }
2637
2638 roce_set_field(context->byte_68_rq_db,
2639 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2640 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
2641 ((u32)hr_qp->rdb.dma) >> 1);
2642 roce_set_field(qpc_mask->byte_68_rq_db,
2643 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2644 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0);
2645 context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
2646 qpc_mask->rq_db_record_addr = 0;
2647
ecaaf1e2 2648 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
2649 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 2650 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
2651
2652 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2653 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2654 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2655 V2_QPC_BYTE_80_RX_CQN_S, 0);
2656 if (ibqp->srq) {
2657 roce_set_field(context->byte_76_srqn_op_en,
2658 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2659 to_hr_srq(ibqp->srq)->srqn);
2660 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2661 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2662 roce_set_bit(context->byte_76_srqn_op_en,
2663 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2664 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2665 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2666 }
2667
2668 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2669 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2670 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
2671 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2672 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
2673 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
2674
2675 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
2676 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
2677
2678 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
2679 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
2680
2681 roce_set_field(qpc_mask->byte_104_rq_sge,
2682 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
2683 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
2684
2685 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2686 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
2687 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2688 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
2689 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
2690 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2691 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
2692
2693 qpc_mask->rq_rnr_timer = 0;
2694 qpc_mask->rx_msg_len = 0;
2695 qpc_mask->rx_rkey_pkt_info = 0;
2696 qpc_mask->rx_va = 0;
2697
2698 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2699 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2700 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2701 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2702
2703 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0);
2704 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
2705 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
2706 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
2707 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
2708
2709 roce_set_field(qpc_mask->byte_144_raq,
2710 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
2711 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
2712 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S,
2713 0);
2714 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
2715 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
2716 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
2717
2718 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
2719 V2_QPC_BYTE_148_RQ_MSN_S, 0);
2720 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
2721 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
2722
2723 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2724 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2725 roce_set_field(qpc_mask->byte_152_raq,
2726 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
2727 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
2728
2729 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
2730 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
2731
2732 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2733 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
2734 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
2735 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2736 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
2737 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
2738
2739 roce_set_field(context->byte_168_irrl_idx,
2740 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2741 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2742 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2743 roce_set_field(qpc_mask->byte_168_irrl_idx,
2744 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2745 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2746
2747 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2748 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 2749 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2750 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 2751 roce_set_field(qpc_mask->byte_168_irrl_idx,
2752 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
2753 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
2754
2755 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2756 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
2757 roce_set_field(qpc_mask->byte_172_sq_psn,
2758 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2759 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
2760
2761 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
2762 0);
2763
2764 roce_set_field(qpc_mask->byte_176_msg_pktn,
2765 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
2766 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
2767 roce_set_field(qpc_mask->byte_176_msg_pktn,
2768 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
2769 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
2770
2771 roce_set_field(qpc_mask->byte_184_irrl_idx,
2772 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
2773 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
2774
2775 qpc_mask->cur_sge_offset = 0;
2776
2777 roce_set_field(qpc_mask->byte_192_ext_sge,
2778 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
2779 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
2780 roce_set_field(qpc_mask->byte_192_ext_sge,
2781 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
2782 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
2783
2784 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2785 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2786
2787 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
2788 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
2789 roce_set_field(qpc_mask->byte_200_sq_max,
2790 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
2791 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
2792
2793 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
2794 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
2795
2796 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2797 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2798
2799 qpc_mask->sq_timer = 0;
2800
2801 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2802 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2803 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2804 roce_set_field(qpc_mask->byte_232_irrl_sge,
2805 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2806 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2807
2808 qpc_mask->irrl_cur_sge_offset = 0;
2809
2810 roce_set_field(qpc_mask->byte_240_irrl_tail,
2811 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2812 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2813 roce_set_field(qpc_mask->byte_240_irrl_tail,
2814 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
2815 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
2816 roce_set_field(qpc_mask->byte_240_irrl_tail,
2817 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2818 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2819
2820 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
2821 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2822 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
2823 0);
2824 roce_set_field(qpc_mask->byte_248_ack_psn,
2825 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2826 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
2827 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
2828 0);
2829 roce_set_bit(qpc_mask->byte_248_ack_psn,
2830 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
2831 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
2832 0);
2833
2834 hr_qp->access_flags = attr->qp_access_flags;
2835 hr_qp->pkey_index = attr->pkey_index;
2836 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2837 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
2838 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2839 V2_QPC_BYTE_252_TX_CQN_S, 0);
2840
2841 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
2842 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
2843
2844 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2845 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
2846 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
2847 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2848 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
2849 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
2850}
2851
2852static void modify_qp_init_to_init(struct ib_qp *ibqp,
2853 const struct ib_qp_attr *attr, int attr_mask,
2854 struct hns_roce_v2_qp_context *context,
2855 struct hns_roce_v2_qp_context *qpc_mask)
2856{
2857 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2858
2859 /*
2860 * In v2 engine, software pass context and context mask to hardware
2861 * when modifying qp. If software need modify some fields in context,
2862 * we should set all bits of the relevant fields in context mask to
2863 * 0 at the same time, else set them to 0x1.
2864 */
2865 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2866 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2867 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2868 V2_QPC_BYTE_4_TST_S, 0);
2869
0fa95a9a 2870 if (ibqp->qp_type == IB_QPT_GSI)
2871 roce_set_field(context->byte_4_sqpn_tst,
2872 V2_QPC_BYTE_4_SGE_SHIFT_M,
2873 V2_QPC_BYTE_4_SGE_SHIFT_S,
2874 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2875 else
2876 roce_set_field(context->byte_4_sqpn_tst,
2877 V2_QPC_BYTE_4_SGE_SHIFT_M,
2878 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
2879 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2880
926a01dc
WHX		 2881 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2882 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2883
2884 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2885 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2886 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2887 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2888 0);
2889
2890 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2891 !!(attr->qp_access_flags &
2892 IB_ACCESS_REMOTE_WRITE));
2893 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2894 0);
2895
2896 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2897 !!(attr->qp_access_flags &
2898 IB_ACCESS_REMOTE_ATOMIC));
2899 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2900 0);
2901 } else {
2902 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2903 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
2904 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2905 0);
2906
2907 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2908 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
2909 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2910 0);
2911
2912 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2913 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
2914 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2915 0);
2916 }
2917
2918 roce_set_field(context->byte_20_smac_sgid_idx,
2919 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2920 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2921 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2922 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2923
2924 roce_set_field(context->byte_20_smac_sgid_idx,
2925 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2926 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2927 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2928 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2929
2930 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2931 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2932 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2933 V2_QPC_BYTE_16_PD_S, 0);
2934
2935 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2936 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2937 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2938 V2_QPC_BYTE_80_RX_CQN_S, 0);
2939
2940 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 2941 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 2942 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2943 V2_QPC_BYTE_252_TX_CQN_S, 0);
2944
2945 if (ibqp->srq) {
2946 roce_set_bit(context->byte_76_srqn_op_en,
2947 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2948 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2949 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2950 roce_set_field(context->byte_76_srqn_op_en,
2951 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2952 to_hr_srq(ibqp->srq)->srqn);
2953 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2954 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2955 }
2956
0fa95a9a 2957 if (attr_mask & IB_QP_QKEY) {
2958 context->qkey_xrcd = attr->qkey;
2959 qpc_mask->qkey_xrcd = 0;
2960 }
926a01dc
WHX		 2961
2962 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2963 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2964 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2965 V2_QPC_BYTE_4_SQPN_S, 0);
2966
b6dd9b34 2967 if (attr_mask & IB_QP_DEST_QPN) {
2968 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2969 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
2970 roce_set_field(qpc_mask->byte_56_dqpn_err,
2971 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
2972 }
926a01dc
WHX		 2973 roce_set_field(context->byte_168_irrl_idx,
2974 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2975 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2976 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2977 roce_set_field(qpc_mask->byte_168_irrl_idx,
2978 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2979 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2980}
2981
2982static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
2983 const struct ib_qp_attr *attr, int attr_mask,
2984 struct hns_roce_v2_qp_context *context,
2985 struct hns_roce_v2_qp_context *qpc_mask)
2986{
2987 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2988 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2989 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2990 struct device *dev = hr_dev->dev;
e92f2c18 2991 dma_addr_t dma_handle_3;
926a01dc
WHX		 2992 dma_addr_t dma_handle_2;
2993 dma_addr_t dma_handle;
2994 u32 page_size;
2995 u8 port_num;
e92f2c18 2996 u64 *mtts_3;
926a01dc
WHX		 2997 u64 *mtts_2;
2998 u64 *mtts;
2999 u8 *dmac;
3000 u8 *smac;
3001 int port;
3002
3003 /* Search qp buf's mtts */
3004 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3005 hr_qp->mtt.first_seg, &dma_handle);
3006 if (!mtts) {
3007 dev_err(dev, "qp buf pa find failed\n");
3008 return -EINVAL;
3009 }
3010
3011 /* Search IRRL's mtts */
3012 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3013 hr_qp->qpn, &dma_handle_2);
3014 if (!mtts_2) {
3015 dev_err(dev, "qp irrl_table find failed\n");
3016 return -EINVAL;
3017 }
3018
e92f2c18 3019 /* Search TRRL's mtts */
3020 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3021 hr_qp->qpn, &dma_handle_3);
3022 if (!mtts_3) {
3023 dev_err(dev, "qp trrl_table find failed\n");
3024 return -EINVAL;
3025 }
3026
734f3863 3027 if (attr_mask & IB_QP_ALT_PATH) {
926a01dc
WHX		 3028 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
3029 return -EINVAL;
3030 }
3031
3032 dmac = (u8 *)attr->ah_attr.roce.dmac;
3033 context->wqe_sge_ba = (u32)(dma_handle >> 3);
3034 qpc_mask->wqe_sge_ba = 0;
3035
3036 /*
3037 * In v2 engine, software pass context and context mask to hardware
3038 * when modifying qp. If software need modify some fields in context,
3039 * we should set all bits of the relevant fields in context mask to
3040 * 0 at the same time, else set them to 0x1.
3041 */
3042 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3043 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
3044 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3045 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3046
3047 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3048 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
3049 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3050 0 : hr_dev->caps.mtt_hop_num);
3051 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3052 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3053
3054 roce_set_field(context->byte_20_smac_sgid_idx,
3055 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3056 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
0fa95a9a 3057 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
3058 hr_dev->caps.mtt_hop_num : 0);
926a01dc
WHX		 3059 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3060 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3061 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3062
3063 roce_set_field(context->byte_20_smac_sgid_idx,
3064 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3065 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
3066 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3067 0 : hr_dev->caps.mtt_hop_num);
3068 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3069 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3070 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3071
3072 roce_set_field(context->byte_16_buf_ba_pg_sz,
3073 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3074 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
5e6e78db 3075 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3076 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3077 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3078 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3079
3080 roce_set_field(context->byte_16_buf_ba_pg_sz,
3081 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3082 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
5e6e78db 3083 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3084 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3085 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3086 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3087
3088 roce_set_field(context->byte_80_rnr_rx_cqn,
3089 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3090 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
3091 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
3092 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3093 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
3094
3095 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
3096 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
3097 >> PAGE_ADDR_SHIFT);
3098 qpc_mask->rq_cur_blk_addr = 0;
3099
3100 roce_set_field(context->byte_92_srq_info,
3101 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3102 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
3103 mtts[hr_qp->rq.offset / page_size]
3104 >> (32 + PAGE_ADDR_SHIFT));
3105 roce_set_field(qpc_mask->byte_92_srq_info,
3106 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3107 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3108
3109 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
3110 >> PAGE_ADDR_SHIFT);
3111 qpc_mask->rq_nxt_blk_addr = 0;
3112
3113 roce_set_field(context->byte_104_rq_sge,
3114 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3115 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
3116 mtts[hr_qp->rq.offset / page_size + 1]
3117 >> (32 + PAGE_ADDR_SHIFT));
3118 roce_set_field(qpc_mask->byte_104_rq_sge,
3119 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3120 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3121
3122 roce_set_field(context->byte_108_rx_reqepsn,
3123 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3124 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
3125 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3126 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3127 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
3128
e92f2c18 3129 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3130 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3131 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3132 V2_QPC_BYTE_132_TRRL_BA_S, 0);
3133 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
3134 qpc_mask->trrl_ba = 0;
3135 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3136 V2_QPC_BYTE_140_TRRL_BA_S,
3137 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3138 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3139 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3140
d5514246 3141 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 3142 qpc_mask->irrl_ba = 0;
3143 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3144 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3145 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3146 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3147 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3148
3149 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3150 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3151
3152 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3153 hr_qp->sq_signal_bits);
3154 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3155 0);
3156
3157 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3158
3159 smac = (u8 *)hr_dev->dev_addr[port];
3160 /* when dmac equals smac or loop_idc is 1, it should loopback */
3161 if (ether_addr_equal_unaligned(dmac, smac) ||
3162 hr_dev->loop_idc == 0x1) {
3163 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3164 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3165 }
3166
4f3f7a70 3167 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
3168 attr->max_dest_rd_atomic) {
3169 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3170 V2_QPC_BYTE_140_RR_MAX_S,
3171 fls(attr->max_dest_rd_atomic - 1));
3172 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3173 V2_QPC_BYTE_140_RR_MAX_S, 0);
3174 }
926a01dc 3175
b6dd9b34 3176 if (attr_mask & IB_QP_DEST_QPN) {
3177 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3178 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3179 roce_set_field(qpc_mask->byte_56_dqpn_err,
3180 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3181 }
926a01dc
WHX		 3182
3183 /* Configure GID index */
3184 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3185 roce_set_field(context->byte_20_smac_sgid_idx,
3186 V2_QPC_BYTE_20_SGID_IDX_M,
3187 V2_QPC_BYTE_20_SGID_IDX_S,
3188 hns_get_gid_index(hr_dev, port_num - 1,
3189 grh->sgid_index));
3190 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3191 V2_QPC_BYTE_20_SGID_IDX_M,
3192 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3193 memcpy(&(context->dmac), dmac, 4);
3194 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3195 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3196 qpc_mask->dmac = 0;
3197 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3198 V2_QPC_BYTE_52_DMAC_S, 0);
3199
3200 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3201 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
3202 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3203 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3204
0fa95a9a 3205 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3206 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3207 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3208 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3209 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3210 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3211
926a01dc
WHX		 3212 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3213 V2_QPC_BYTE_24_MTU_S, 0);
3214
926a01dc
WHX		 3215 roce_set_field(context->byte_84_rq_ci_pi,
3216 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3217 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3218 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3219 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3220 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3221
3222 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3223 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3224 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3225 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3226 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3227 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3228 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3229 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3230 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3231 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3232
3233 context->rq_rnr_timer = 0;
3234 qpc_mask->rq_rnr_timer = 0;
3235
3236 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3237 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
3238 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3239 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3240
3241 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3242 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3243 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3244 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3245
3246 roce_set_field(context->byte_168_irrl_idx,
3247 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3248 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3249 roce_set_field(qpc_mask->byte_168_irrl_idx,
3250 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3251 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3252
926a01dc
WHX		 3253 return 0;
3254}
3255
3256static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3257 const struct ib_qp_attr *attr, int attr_mask,
3258 struct hns_roce_v2_qp_context *context,
3259 struct hns_roce_v2_qp_context *qpc_mask)
3260{
3261 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3262 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3263 struct device *dev = hr_dev->dev;
3264 dma_addr_t dma_handle;
befb63b4 3265 u32 page_size;
926a01dc
WHX		 3266 u64 *mtts;
3267
3268 /* Search qp buf's mtts */
3269 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3270 hr_qp->mtt.first_seg, &dma_handle);
3271 if (!mtts) {
3272 dev_err(dev, "qp buf pa find failed\n");
3273 return -EINVAL;
3274 }
3275
734f3863 3276 /* Not support alternate path and path migration */
3277 if ((attr_mask & IB_QP_ALT_PATH) ||
3278 (attr_mask & IB_QP_PATH_MIG_STATE)) {
926a01dc
WHX		 3279 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
3280 return -EINVAL;
3281 }
3282
3283 /*
3284 * In v2 engine, software pass context and context mask to hardware
3285 * when modifying qp. If software need modify some fields in context,
3286 * we should set all bits of the relevant fields in context mask to
3287 * 0 at the same time, else set them to 0x1.
3288 */
3289 roce_set_field(context->byte_60_qpst_mapid,
3290 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
3291 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt);
3292 roce_set_field(qpc_mask->byte_60_qpst_mapid,
3293 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
3294 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0);
3295
3296 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3297 roce_set_field(context->byte_168_irrl_idx,
3298 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3299 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3300 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3301 qpc_mask->sq_cur_blk_addr = 0;
3302 roce_set_field(qpc_mask->byte_168_irrl_idx,
3303 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3304 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3305
befb63b4 3306 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
0fa95a9a 3307 context->sq_cur_sge_blk_addr =
3308 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3309 ((u32)(mtts[hr_qp->sge.offset / page_size]
3310 >> PAGE_ADDR_SHIFT)) : 0;
3311 roce_set_field(context->byte_184_irrl_idx,
3312 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3313 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
0fa95a9a 3314 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3315 (mtts[hr_qp->sge.offset / page_size] >>
3316 (32 + PAGE_ADDR_SHIFT)) : 0);
3317 qpc_mask->sq_cur_sge_blk_addr = 0;
3318 roce_set_field(qpc_mask->byte_184_irrl_idx,
3319 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3320 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3321
926a01dc
WHX		 3322 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3323 roce_set_field(context->byte_232_irrl_sge,
3324 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3325 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3326 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3327 qpc_mask->rx_sq_cur_blk_addr = 0;
3328 roce_set_field(qpc_mask->byte_232_irrl_sge,
3329 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3330 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3331
3332 /*
3333 * Set some fields in context to zero, Because the default values
3334 * of all fields in context are zero, we need not set them to 0 again.
3335 * but we should set the relevant fields of context mask to 0.
3336 */
3337 roce_set_field(qpc_mask->byte_232_irrl_sge,
3338 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3339 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3340
3341 roce_set_field(qpc_mask->byte_240_irrl_tail,
3342 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3343 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3344
3345 roce_set_field(context->byte_244_rnr_rxack,
3346 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3347 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
3348 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3349 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3350 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
3351
3352 roce_set_field(qpc_mask->byte_248_ack_psn,
3353 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3354 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3355 roce_set_bit(qpc_mask->byte_248_ack_psn,
3356 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
3357 roce_set_field(qpc_mask->byte_248_ack_psn,
3358 V2_QPC_BYTE_248_IRRL_PSN_M,
3359 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3360
3361 roce_set_field(qpc_mask->byte_240_irrl_tail,
3362 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3363 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3364
3365 roce_set_field(context->byte_220_retry_psn_msn,
3366 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3367 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
3368 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3369 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3370 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
3371
3372 roce_set_field(context->byte_224_retry_msg,
3373 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3374 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
3375 roce_set_field(qpc_mask->byte_224_retry_msg,
3376 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3377 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
3378
3379 roce_set_field(context->byte_224_retry_msg,
3380 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3381 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
3382 roce_set_field(qpc_mask->byte_224_retry_msg,
3383 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3384 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
3385
3386 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3387 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3388 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3389
3390 roce_set_bit(qpc_mask->byte_248_ack_psn,
3391 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3392
3393 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3394 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3395
3396 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3397 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
3398 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3399 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
3400
3401 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3402 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
3403 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3404 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
3405
3406 roce_set_field(context->byte_244_rnr_rxack,
3407 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3408 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
3409 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3410 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3411 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
3412
3413 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3414 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
3415 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3416 V2_QPC_BYTE_244_RNR_CNT_S, 0);
3417
3418 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3419 V2_QPC_BYTE_212_LSN_S, 0x100);
3420 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3421 V2_QPC_BYTE_212_LSN_S, 0);
3422
28726461 3423 if (attr_mask & IB_QP_TIMEOUT) {
926a01dc
WHX		 3424 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3425 V2_QPC_BYTE_28_AT_S, attr->timeout);
28726461 3426 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3427 V2_QPC_BYTE_28_AT_S, 0);
3428 }
926a01dc 3429
926a01dc
WHX		 3430 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3431 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
3432 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3433 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
3434
3435 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3436 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3437 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3438 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
3439 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3440 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
3441
4f3f7a70 3442 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
3443 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
3444 V2_QPC_BYTE_208_SR_MAX_S,
3445 fls(attr->max_rd_atomic - 1));
3446 roce_set_field(qpc_mask->byte_208_irrl,
3447 V2_QPC_BYTE_208_SR_MAX_M,
3448 V2_QPC_BYTE_208_SR_MAX_S, 0);
3449 }
926a01dc
WHX		 3450 return 0;
3451}
3452
3453static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
3454 const struct ib_qp_attr *attr,
3455 int attr_mask, enum ib_qp_state cur_state,
3456 enum ib_qp_state new_state)
3457{
3458 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3459 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3460 struct hns_roce_v2_qp_context *context;
3461 struct hns_roce_v2_qp_context *qpc_mask;
3462 struct device *dev = hr_dev->dev;
3463 int ret = -EINVAL;
3464
6396bb22 3465 context = kcalloc(2, sizeof(*context), GFP_KERNEL);
926a01dc
WHX		 3466 if (!context)
3467 return -ENOMEM;
3468
3469 qpc_mask = context + 1;
3470 /*
3471 * In v2 engine, software pass context and context mask to hardware
3472 * when modifying qp. If software need modify some fields in context,
3473 * we should set all bits of the relevant fields in context mask to
3474 * 0 at the same time, else set them to 0x1.
3475 */
3476 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
3477 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0fa95a9a 3478 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
3479 qpc_mask);
926a01dc
WHX		 3480 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3481 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
3482 qpc_mask);
3483 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3484 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
3485 qpc_mask);
3486 if (ret)
3487 goto out;
3488 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3489 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
3490 qpc_mask);
3491 if (ret)
3492 goto out;
3493 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) ||
3494 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) ||
3495 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) ||
3496 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) ||
3497 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) ||
3498 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3499 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3500 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3501 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3502 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3503 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3504 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3505 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) ||
6e1a7094 3506 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) ||
3507 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) {
926a01dc
WHX		 3508 /* Nothing */
3509 ;
3510 } else {
3511 dev_err(dev, "Illegal state for QP!\n");
ac7cbf96 3512 ret = -EINVAL;
926a01dc
WHX		 3513 goto out;
3514 }
3515
0425e3e6
YL		 3516 /* When QP state is err, SQ and RQ WQE should be flushed */
3517 if (new_state == IB_QPS_ERR) {
3518 roce_set_field(context->byte_160_sq_ci_pi,
3519 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3520 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
3521 hr_qp->sq.head);
3522 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3523 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3524 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
3525 roce_set_field(context->byte_84_rq_ci_pi,
3526 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3527 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
3528 hr_qp->rq.head);
3529 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3530 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3531 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3532 }
3533
610b8967
LO		 3534 if (attr_mask & IB_QP_AV) {
3535 const struct ib_global_route *grh =
3536 rdma_ah_read_grh(&attr->ah_attr);
3537 const struct ib_gid_attr *gid_attr = NULL;
3538 u8 src_mac[ETH_ALEN];
3539 int is_roce_protocol;
3540 u16 vlan = 0xffff;
3541 u8 ib_port;
3542 u8 hr_port;
3543
3544 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num :
3545 hr_qp->port + 1;
3546 hr_port = ib_port - 1;
3547 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
3548 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
3549
3550 if (is_roce_protocol) {
3551 gid_attr = attr->ah_attr.grh.sgid_attr;
3552 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
3553 memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN);
3554 }
3555
c8e46f8d
LO		 3556 roce_set_field(context->byte_24_mtu_tc,
3557 V2_QPC_BYTE_24_VLAN_ID_M,
3558 V2_QPC_BYTE_24_VLAN_ID_S, vlan);
3559 roce_set_field(qpc_mask->byte_24_mtu_tc,
3560 V2_QPC_BYTE_24_VLAN_ID_M,
3561 V2_QPC_BYTE_24_VLAN_ID_S, 0);
3562
610b8967
LO		 3563 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
3564 dev_err(hr_dev->dev,
3565 "sgid_index(%u) too large. max is %d\n",
3566 grh->sgid_index,
3567 hr_dev->caps.gid_table_len[hr_port]);
3568 ret = -EINVAL;
3569 goto out;
3570 }
3571
3572 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
3573 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n");
3574 ret = -EINVAL;
3575 goto out;
3576 }
3577
3578 roce_set_field(context->byte_52_udpspn_dmac,
3579 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S,
3580 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3581 0 : 0x12b7);
3582
3583 roce_set_field(qpc_mask->byte_52_udpspn_dmac,
3584 V2_QPC_BYTE_52_UDPSPN_M,
3585 V2_QPC_BYTE_52_UDPSPN_S, 0);
3586
3587 roce_set_field(context->byte_20_smac_sgid_idx,
3588 V2_QPC_BYTE_20_SGID_IDX_M,
3589 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index);
3590
3591 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3592 V2_QPC_BYTE_20_SGID_IDX_M,
3593 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3594
3595 roce_set_field(context->byte_24_mtu_tc,
3596 V2_QPC_BYTE_24_HOP_LIMIT_M,
3597 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
3598 roce_set_field(qpc_mask->byte_24_mtu_tc,
3599 V2_QPC_BYTE_24_HOP_LIMIT_M,
3600 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
3601
3602 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
3603 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
3604 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
3605 V2_QPC_BYTE_24_TC_S, 0);
3606 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3607 V2_QPC_BYTE_28_FL_S, grh->flow_label);
3608 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3609 V2_QPC_BYTE_28_FL_S, 0);
3610 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
3611 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
3612 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3613 V2_QPC_BYTE_28_SL_S,
3614 rdma_ah_get_sl(&attr->ah_attr));
3615 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3616 V2_QPC_BYTE_28_SL_S, 0);
3617 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3618 }
3619
ace1c541 3620 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3621 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
3622
926a01dc
WHX		 3623 /* Every status migrate must change state */
3624 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
3625 V2_QPC_BYTE_60_QP_ST_S, new_state);
3626 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
3627 V2_QPC_BYTE_60_QP_ST_S, 0);
3628
3629 /* SW pass context to HW */
3630 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
3631 context, hr_qp);
3632 if (ret) {
3633 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
3634 goto out;
3635 }
3636
3637 hr_qp->state = new_state;
3638
ace1c541 3639 if (attr_mask & IB_QP_ACCESS_FLAGS)
3640 hr_qp->atomic_rd_en = attr->qp_access_flags;
3641
926a01dc
WHX		 3642 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3643 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3644 if (attr_mask & IB_QP_PORT) {
3645 hr_qp->port = attr->port_num - 1;
3646 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3647 }
3648
3649 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3650 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3651 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3652 if (ibqp->send_cq != ibqp->recv_cq)
3653 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
3654 hr_qp->qpn, NULL);
3655
3656 hr_qp->rq.head = 0;
3657 hr_qp->rq.tail = 0;
3658 hr_qp->sq.head = 0;
3659 hr_qp->sq.tail = 0;
3660 hr_qp->sq_next_wqe = 0;
3661 hr_qp->next_sge = 0;
e088a685
YL		 3662 if (hr_qp->rq.wqe_cnt)
3663 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 3664 }
3665
3666out:
3667 kfree(context);
3668 return ret;
3669}
3670
3671static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
3672{
3673 switch (state) {
3674 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
3675 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
3676 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
3677 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
3678 case HNS_ROCE_QP_ST_SQ_DRAINING:
3679 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
3680 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
3681 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
3682 default: return -1;
3683 }
3684}
3685
3686static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
3687 struct hns_roce_qp *hr_qp,
3688 struct hns_roce_v2_qp_context *hr_context)
3689{
3690 struct hns_roce_cmd_mailbox *mailbox;
3691 int ret;
3692
3693 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3694 if (IS_ERR(mailbox))
3695 return PTR_ERR(mailbox);
3696
3697 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3698 HNS_ROCE_CMD_QUERY_QPC,
3699 HNS_ROCE_CMD_TIMEOUT_MSECS);
3700 if (ret) {
3701 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
3702 goto out;
3703 }
3704
3705 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3706
3707out:
3708 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3709 return ret;
3710}
3711
3712static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3713 int qp_attr_mask,
3714 struct ib_qp_init_attr *qp_init_attr)
3715{
3716 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3717 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3718 struct hns_roce_v2_qp_context *context;
3719 struct device *dev = hr_dev->dev;
3720 int tmp_qp_state;
3721 int state;
3722 int ret;
3723
3724 context = kzalloc(sizeof(*context), GFP_KERNEL);
3725 if (!context)
3726 return -ENOMEM;
3727
3728 memset(qp_attr, 0, sizeof(*qp_attr));
3729 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3730
3731 mutex_lock(&hr_qp->mutex);
3732
3733 if (hr_qp->state == IB_QPS_RESET) {
3734 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 3735 ret = 0;
926a01dc
WHX		 3736 goto done;
3737 }
3738
3739 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
3740 if (ret) {
3741 dev_err(dev, "query qpc error\n");
3742 ret = -EINVAL;
3743 goto out;
3744 }
3745
3746 state = roce_get_field(context->byte_60_qpst_mapid,
3747 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
3748 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
3749 if (tmp_qp_state == -1) {
3750 dev_err(dev, "Illegal ib_qp_state\n");
3751 ret = -EINVAL;
3752 goto out;
3753 }
3754 hr_qp->state = (u8)tmp_qp_state;
3755 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3756 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
3757 V2_QPC_BYTE_24_MTU_M,
3758 V2_QPC_BYTE_24_MTU_S);
3759 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 3760 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 3761 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3762 qp_attr->qkey = V2_QKEY_VAL;
3763
3764 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
3765 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3766 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
3767 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
3768 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3769 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
3770 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
3771 V2_QPC_BYTE_56_DQPN_M,
3772 V2_QPC_BYTE_56_DQPN_S);
3773 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
3774 V2_QPC_BYTE_76_RRE_S)) << 2) |
3775 ((roce_get_bit(context->byte_76_srqn_op_en,
3776 V2_QPC_BYTE_76_RWE_S)) << 1) |
3777 ((roce_get_bit(context->byte_76_srqn_op_en,
3778 V2_QPC_BYTE_76_ATE_S)) << 3);
3779 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3780 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3781 struct ib_global_route *grh =
3782 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3783
3784 rdma_ah_set_sl(&qp_attr->ah_attr,
3785 roce_get_field(context->byte_28_at_fl,
3786 V2_QPC_BYTE_28_SL_M,
3787 V2_QPC_BYTE_28_SL_S));
3788 grh->flow_label = roce_get_field(context->byte_28_at_fl,
3789 V2_QPC_BYTE_28_FL_M,
3790 V2_QPC_BYTE_28_FL_S);
3791 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
3792 V2_QPC_BYTE_20_SGID_IDX_M,
3793 V2_QPC_BYTE_20_SGID_IDX_S);
3794 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
3795 V2_QPC_BYTE_24_HOP_LIMIT_M,
3796 V2_QPC_BYTE_24_HOP_LIMIT_S);
3797 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
3798 V2_QPC_BYTE_24_TC_M,
3799 V2_QPC_BYTE_24_TC_S);
3800
3801 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
3802 }
3803
3804 qp_attr->port_num = hr_qp->port + 1;
3805 qp_attr->sq_draining = 0;
3806 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
3807 V2_QPC_BYTE_208_SR_MAX_M,
3808 V2_QPC_BYTE_208_SR_MAX_S);
3809 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
3810 V2_QPC_BYTE_140_RR_MAX_M,
3811 V2_QPC_BYTE_140_RR_MAX_S);
3812 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
3813 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3814 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
3815 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
3816 V2_QPC_BYTE_28_AT_M,
3817 V2_QPC_BYTE_28_AT_S);
3818 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
3819 V2_QPC_BYTE_212_RETRY_CNT_M,
3820 V2_QPC_BYTE_212_RETRY_CNT_S);
3821 qp_attr->rnr_retry = context->rq_rnr_timer;
3822
3823done:
3824 qp_attr->cur_qp_state = qp_attr->qp_state;
3825 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3826 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3827
3828 if (!ibqp->uobject) {
3829 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3830 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3831 } else {
3832 qp_attr->cap.max_send_wr = 0;
3833 qp_attr->cap.max_send_sge = 0;
3834 }
3835
3836 qp_init_attr->cap = qp_attr->cap;
3837
3838out:
3839 mutex_unlock(&hr_qp->mutex);
3840 kfree(context);
3841 return ret;
3842}
3843
3844static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
3845 struct hns_roce_qp *hr_qp,
3846 int is_user)
3847{
3848 struct hns_roce_cq *send_cq, *recv_cq;
3849 struct device *dev = hr_dev->dev;
3850 int ret;
3851
3852 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
3853 /* Modify qp to reset before destroying qp */
3854 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
3855 hr_qp->state, IB_QPS_RESET);
3856 if (ret) {
3857 dev_err(dev, "modify QP %06lx to ERR failed.\n",
3858 hr_qp->qpn);
3859 return ret;
3860 }
3861 }
3862
3863 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3864 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3865
3866 hns_roce_lock_cqs(send_cq, recv_cq);
3867
3868 if (!is_user) {
3869 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3870 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3871 if (send_cq != recv_cq)
3872 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
3873 }
3874
3875 hns_roce_qp_remove(hr_dev, hr_qp);
3876
3877 hns_roce_unlock_cqs(send_cq, recv_cq);
3878
3879 hns_roce_qp_free(hr_dev, hr_qp);
3880
3881 /* Not special_QP, free their QPN */
3882 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
3883 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
3884 (hr_qp->ibqp.qp_type == IB_QPT_UD))
3885 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3886
3887 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3888
3889 if (is_user) {
0425e3e6
YL		 3890 if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1))
3891 hns_roce_db_unmap_user(
3892 to_hr_ucontext(hr_qp->ibqp.uobject->context),
3893 &hr_qp->sdb);
3894
e088a685
YL		 3895 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1))
3896 hns_roce_db_unmap_user(
3897 to_hr_ucontext(hr_qp->ibqp.uobject->context),
3898 &hr_qp->rdb);
926a01dc
WHX		 3899 ib_umem_release(hr_qp->umem);
3900 } else {
3901 kfree(hr_qp->sq.wrid);
3902 kfree(hr_qp->rq.wrid);
3903 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
472bc0fb
YL		 3904 if (hr_qp->rq.wqe_cnt)
3905 hns_roce_free_db(hr_dev, &hr_qp->rdb);
926a01dc
WHX		 3906 }
3907
0009c2db 3908 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
3909 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
3910 kfree(hr_qp->rq_inl_buf.wqe_list);
3911 }
3912
926a01dc
WHX		 3913 return 0;
3914}
3915
3916static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
3917{
3918 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3919 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3920 int ret;
3921
3922 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
3923 if (ret) {
3924 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
3925 return ret;
3926 }
3927
3928 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
3929 kfree(hr_to_hr_sqp(hr_qp));
3930 else
3931 kfree(hr_qp);
3932
3933 return 0;
3934}
3935
b156269d 3936static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
3937{
3938 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
3939 struct hns_roce_v2_cq_context *cq_context;
3940 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
3941 struct hns_roce_v2_cq_context *cqc_mask;
3942 struct hns_roce_cmd_mailbox *mailbox;
3943 int ret;
3944
3945 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3946 if (IS_ERR(mailbox))
3947 return PTR_ERR(mailbox);
3948
3949 cq_context = mailbox->buf;
3950 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
3951
3952 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
3953
3954 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3955 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3956 cq_count);
3957 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3958 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3959 0);
3960 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3961 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3962 cq_period);
3963 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3964 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3965 0);
3966
3967 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
3968 HNS_ROCE_CMD_MODIFY_CQC,
3969 HNS_ROCE_CMD_TIMEOUT_MSECS);
3970 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3971 if (ret)
3972 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
3973
3974 return ret;
3975}
3976
0425e3e6
YL		 3977static void hns_roce_set_qps_to_err(struct hns_roce_dev *hr_dev, u32 qpn)
3978{
3979 struct hns_roce_qp *hr_qp;
3980 struct ib_qp_attr attr;
3981 int attr_mask;
3982 int ret;
3983
3984 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3985 if (!hr_qp) {
3986 dev_warn(hr_dev->dev, "no hr_qp can be found!\n");
3987 return;
3988 }
3989
3990 if (hr_qp->ibqp.uobject) {
3991 if (hr_qp->sdb_en == 1) {
3992 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
3993 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
3994 } else {
3995 dev_warn(hr_dev->dev, "flush cqe is unsupported in userspace!\n");
3996 return;
3997 }
3998 }
3999
4000 attr_mask = IB_QP_STATE;
4001 attr.qp_state = IB_QPS_ERR;
4002 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, attr_mask,
4003 hr_qp->state, IB_QPS_ERR);
4004 if (ret)
4005 dev_err(hr_dev->dev, "failed to modify qp %d to err state.\n",
4006 qpn);
4007}
4008
4009static void hns_roce_irq_work_handle(struct work_struct *work)
4010{
4011 struct hns_roce_work *irq_work =
4012 container_of(work, struct hns_roce_work, work);
b00a92c8 4013 struct device *dev = irq_work->hr_dev->dev;
0425e3e6 4014 u32 qpn = irq_work->qpn;
b00a92c8 4015 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4016
4017 switch (irq_work->event_type) {
b00a92c8 4018 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4019 dev_info(dev, "Path migrated succeeded.\n");
4020 break;
4021 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4022 dev_warn(dev, "Path migration failed.\n");
4023 break;
4024 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4025 dev_info(dev, "Communication established.\n");
4026 break;
4027 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4028 dev_warn(dev, "Send queue drained.\n");
4029 break;
0425e3e6 4030 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
b00a92c8 4031 dev_err(dev, "Local work queue catastrophic error.\n");
4032 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4033 switch (irq_work->sub_type) {
4034 case HNS_ROCE_LWQCE_QPC_ERROR:
4035 dev_err(dev, "QP %d, QPC error.\n", qpn);
4036 break;
4037 case HNS_ROCE_LWQCE_MTU_ERROR:
4038 dev_err(dev, "QP %d, MTU error.\n", qpn);
4039 break;
4040 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4041 dev_err(dev, "QP %d, WQE BA addr error.\n", qpn);
4042 break;
4043 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4044 dev_err(dev, "QP %d, WQE addr error.\n", qpn);
4045 break;
4046 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4047 dev_err(dev, "QP %d, WQE shift error.\n", qpn);
4048 break;
4049 default:
4050 dev_err(dev, "Unhandled sub_event type %d.\n",
4051 irq_work->sub_type);
4052 break;
4053 }
4054 break;
0425e3e6 4055 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
b00a92c8 4056 dev_err(dev, "Invalid request local work queue error.\n");
4057 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4058 break;
0425e3e6 4059 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4060 dev_err(dev, "Local access violation work queue error.\n");
0425e3e6 4061 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
b00a92c8 4062 switch (irq_work->sub_type) {
4063 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4064 dev_err(dev, "QP %d, R_key violation.\n", qpn);
4065 break;
4066 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4067 dev_err(dev, "QP %d, length error.\n", qpn);
4068 break;
4069 case HNS_ROCE_LAVWQE_VA_ERROR:
4070 dev_err(dev, "QP %d, VA error.\n", qpn);
4071 break;
4072 case HNS_ROCE_LAVWQE_PD_ERROR:
4073 dev_err(dev, "QP %d, PD error.\n", qpn);
4074 break;
4075 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4076 dev_err(dev, "QP %d, rw acc error.\n", qpn);
4077 break;
4078 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4079 dev_err(dev, "QP %d, key state error.\n", qpn);
4080 break;
4081 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4082 dev_err(dev, "QP %d, MR operation error.\n", qpn);
4083 break;
4084 default:
4085 dev_err(dev, "Unhandled sub_event type %d.\n",
4086 irq_work->sub_type);
4087 break;
4088 }
4089 break;
4090 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4091 dev_warn(dev, "SRQ limit reach.\n");
4092 break;
4093 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4094 dev_warn(dev, "SRQ last wqe reach.\n");
4095 break;
4096 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4097 dev_err(dev, "SRQ catas error.\n");
4098 break;
4099 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4100 dev_err(dev, "CQ 0x%x access err.\n", cqn);
4101 break;
4102 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4103 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4104 break;
4105 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4106 dev_warn(dev, "DB overflow.\n");
4107 break;
4108 case HNS_ROCE_EVENT_TYPE_FLR:
4109 dev_warn(dev, "Function level reset.\n");
0425e3e6
YL		 4110 break;
4111 default:
4112 break;
4113 }
4114
4115 kfree(irq_work);
4116}
4117
4118static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4119 struct hns_roce_eq *eq,
4120 u32 qpn, u32 cqn)
0425e3e6
YL		 4121{
4122 struct hns_roce_work *irq_work;
4123
4124 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4125 if (!irq_work)
4126 return;
4127
4128 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4129 irq_work->hr_dev = hr_dev;
4130 irq_work->qpn = qpn;
b00a92c8 4131 irq_work->cqn = cqn;
0425e3e6
YL		 4132 irq_work->event_type = eq->event_type;
4133 irq_work->sub_type = eq->sub_type;
4134 queue_work(hr_dev->irq_workq, &(irq_work->work));
4135}
4136
a5073d60
YL		 4137static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4138{
4139 u32 doorbell[2];
4140
4141 doorbell[0] = 0;
4142 doorbell[1] = 0;
4143
4144 if (eq->type_flag == HNS_ROCE_AEQ) {
4145 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4146 HNS_ROCE_V2_EQ_DB_CMD_S,
4147 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4148 HNS_ROCE_EQ_DB_CMD_AEQ :
4149 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4150 } else {
4151 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4152 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4153
4154 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4155 HNS_ROCE_V2_EQ_DB_CMD_S,
4156 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4157 HNS_ROCE_EQ_DB_CMD_CEQ :
4158 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4159 }
4160
4161 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4162 HNS_ROCE_V2_EQ_DB_PARA_S,
4163 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4164
4165 hns_roce_write64_k(doorbell, eq->doorbell);
a5073d60
YL		 4166}
4167
a5073d60
YL		 4168static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry)
4169{
4170 u32 buf_chk_sz;
4171 unsigned long off;
4172
4173 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4174 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4175
4176 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) +
4177 off % buf_chk_sz);
4178}
4179
4180static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry)
4181{
4182 u32 buf_chk_sz;
4183 unsigned long off;
4184
4185 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4186
4187 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4188
4189 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4190 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) +
4191 off % buf_chk_sz);
4192 else
4193 return (struct hns_roce_aeqe *)((u8 *)
4194 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz);
4195}
4196
4197static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4198{
4199 struct hns_roce_aeqe *aeqe;
4200
4201 if (!eq->hop_num)
4202 aeqe = get_aeqe_v2(eq, eq->cons_index);
4203 else
4204 aeqe = mhop_get_aeqe(eq, eq->cons_index);
4205
4206 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4207 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4208}
4209
4210static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4211 struct hns_roce_eq *eq)
4212{
4213 struct device *dev = hr_dev->dev;
4214 struct hns_roce_aeqe *aeqe;
4215 int aeqe_found = 0;
4216 int event_type;
0425e3e6
YL		 4217 int sub_type;
4218 u32 qpn;
4219 u32 cqn;
a5073d60
YL		 4220
4221 while ((aeqe = next_aeqe_sw_v2(eq))) {
4044a3f4
YL		 4222
4223 /* Make sure we read AEQ entry after we have checked the
4224 * ownership bit
4225 */
4226 dma_rmb();
a5073d60
YL		 4227
4228 event_type = roce_get_field(aeqe->asyn,
4229 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
4230 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 4231 sub_type = roce_get_field(aeqe->asyn,
4232 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
4233 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
4234 qpn = roce_get_field(aeqe->event.qp_event.qp,
4235 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4236 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4237 cqn = roce_get_field(aeqe->event.cq_event.cq,
4238 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4239 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 4240
4241 switch (event_type) {
4242 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 4243 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 4244 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4245 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4246 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4247 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4248 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4249 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 4250 break;
4251 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4252 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4253 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
a5073d60
YL		 4254 break;
4255 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4256 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 4257 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 4258 break;
4259 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 4260 break;
4261 case HNS_ROCE_EVENT_TYPE_MB:
4262 hns_roce_cmd_event(hr_dev,
4263 le16_to_cpu(aeqe->event.cmd.token),
4264 aeqe->event.cmd.status,
4265 le64_to_cpu(aeqe->event.cmd.out_param));
4266 break;
4267 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 4268 break;
4269 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 4270 break;
4271 default:
4272 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4273 event_type, eq->eqn, eq->cons_index);
4274 break;
4275 };
4276
0425e3e6
YL		 4277 eq->event_type = event_type;
4278 eq->sub_type = sub_type;
a5073d60
YL		 4279 ++eq->cons_index;
4280 aeqe_found = 1;
4281
4282 if (eq->cons_index > (2 * eq->entries - 1)) {
4283 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4284 eq->cons_index = 0;
4285 }
b00a92c8 4286 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
a5073d60
YL		 4287 }
4288
4289 set_eq_cons_index_v2(eq);
4290 return aeqe_found;
4291}
4292
4293static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry)
4294{
4295 u32 buf_chk_sz;
4296 unsigned long off;
4297
4298 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4299 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4300
4301 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) +
4302 off % buf_chk_sz);
4303}
4304
4305static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry)
4306{
4307 u32 buf_chk_sz;
4308 unsigned long off;
4309
4310 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4311
4312 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4313
4314 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4315 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) +
4316 off % buf_chk_sz);
4317 else
4318 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off /
4319 buf_chk_sz]) + off % buf_chk_sz);
4320}
4321
4322static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
4323{
4324 struct hns_roce_ceqe *ceqe;
4325
4326 if (!eq->hop_num)
4327 ceqe = get_ceqe_v2(eq, eq->cons_index);
4328 else
4329 ceqe = mhop_get_ceqe(eq, eq->cons_index);
4330
4331 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
4332 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4333}
4334
4335static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
4336 struct hns_roce_eq *eq)
4337{
4338 struct device *dev = hr_dev->dev;
4339 struct hns_roce_ceqe *ceqe;
4340 int ceqe_found = 0;
4341 u32 cqn;
4342
4343 while ((ceqe = next_ceqe_sw_v2(eq))) {
4344
4044a3f4
YL		 4345 /* Make sure we read CEQ entry after we have checked the
4346 * ownership bit
4347 */
4348 dma_rmb();
4349
a5073d60
YL		 4350 cqn = roce_get_field(ceqe->comp,
4351 HNS_ROCE_V2_CEQE_COMP_CQN_M,
4352 HNS_ROCE_V2_CEQE_COMP_CQN_S);
4353
4354 hns_roce_cq_completion(hr_dev, cqn);
4355
4356 ++eq->cons_index;
4357 ceqe_found = 1;
4358
4359 if (eq->cons_index > (2 * eq->entries - 1)) {
4360 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4361 eq->cons_index = 0;
4362 }
4363 }
4364
4365 set_eq_cons_index_v2(eq);
4366
4367 return ceqe_found;
4368}
4369
4370static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
4371{
4372 struct hns_roce_eq *eq = eq_ptr;
4373 struct hns_roce_dev *hr_dev = eq->hr_dev;
4374 int int_work = 0;
4375
4376 if (eq->type_flag == HNS_ROCE_CEQ)
4377 /* Completion event interrupt */
4378 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
4379 else
4380 /* Asychronous event interrupt */
4381 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
4382
4383 return IRQ_RETVAL(int_work);
4384}
4385
4386static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
4387{
4388 struct hns_roce_dev *hr_dev = dev_id;
4389 struct device *dev = hr_dev->dev;
4390 int int_work = 0;
4391 u32 int_st;
4392 u32 int_en;
4393
4394 /* Abnormal interrupt */
4395 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
4396 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
4397
4398 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
4399 dev_err(dev, "AEQ overflow!\n");
4400
4401 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
4402 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4403
a5073d60
YL		 4404 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4405 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4406
4407 int_work = 1;
4408 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
4409 dev_err(dev, "BUS ERR!\n");
4410
4411 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
4412 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4413
a5073d60
YL		 4414 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4415 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4416
4417 int_work = 1;
4418 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
4419 dev_err(dev, "OTHER ERR!\n");
4420
4421 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
4422 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4423
a5073d60
YL		 4424 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4425 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4426
4427 int_work = 1;
4428 } else
4429 dev_err(dev, "There is no abnormal irq found!\n");
4430
4431 return IRQ_RETVAL(int_work);
4432}
4433
4434static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
4435 int eq_num, int enable_flag)
4436{
4437 int i;
4438
4439 if (enable_flag == EQ_ENABLE) {
4440 for (i = 0; i < eq_num; i++)
4441 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4442 i * EQ_REG_OFFSET,
4443 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
4444
4445 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4446 HNS_ROCE_V2_VF_ABN_INT_EN_M);
4447 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4448 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
4449 } else {
4450 for (i = 0; i < eq_num; i++)
4451 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4452 i * EQ_REG_OFFSET,
4453 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
4454
4455 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4456 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
4457 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4458 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
4459 }
4460}
4461
4462static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
4463{
4464 struct device *dev = hr_dev->dev;
4465 int ret;
4466
4467 if (eqn < hr_dev->caps.num_comp_vectors)
4468 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4469 0, HNS_ROCE_CMD_DESTROY_CEQC,
4470 HNS_ROCE_CMD_TIMEOUT_MSECS);
4471 else
4472 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4473 0, HNS_ROCE_CMD_DESTROY_AEQC,
4474 HNS_ROCE_CMD_TIMEOUT_MSECS);
4475 if (ret)
4476 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
4477}
4478
4479static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev,
4480 struct hns_roce_eq *eq)
4481{
4482 struct device *dev = hr_dev->dev;
4483 u64 idx;
4484 u64 size;
4485 u32 buf_chk_sz;
4486 u32 bt_chk_sz;
4487 u32 mhop_num;
4488 int eqe_alloc;
a5073d60
YL		 4489 int i = 0;
4490 int j = 0;
4491
4492 mhop_num = hr_dev->caps.eqe_hop_num;
4493 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4494 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
a5073d60
YL		 4495
4496 /* hop_num = 0 */
4497 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4498 dma_free_coherent(dev, (unsigned int)(eq->entries *
4499 eq->eqe_size), eq->bt_l0, eq->l0_dma);
4500 return;
4501 }
4502
4503 /* hop_num = 1 or hop = 2 */
4504 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4505 if (mhop_num == 1) {
4506 for (i = 0; i < eq->l0_last_num; i++) {
4507 if (i == eq->l0_last_num - 1) {
4508 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4509 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4510 dma_free_coherent(dev, size, eq->buf[i],
4511 eq->buf_dma[i]);
4512 break;
4513 }
4514 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4515 eq->buf_dma[i]);
4516 }
4517 } else if (mhop_num == 2) {
4518 for (i = 0; i < eq->l0_last_num; i++) {
4519 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4520 eq->l1_dma[i]);
4521
4522 for (j = 0; j < bt_chk_sz / 8; j++) {
4523 idx = i * (bt_chk_sz / 8) + j;
4524 if ((i == eq->l0_last_num - 1)
4525 && j == eq->l1_last_num - 1) {
4526 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4527 * idx;
4528 size = (eq->entries - eqe_alloc)
4529 * eq->eqe_size;
4530 dma_free_coherent(dev, size,
4531 eq->buf[idx],
4532 eq->buf_dma[idx]);
4533 break;
4534 }
4535 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4536 eq->buf_dma[idx]);
4537 }
4538 }
4539 }
4540 kfree(eq->buf_dma);
4541 kfree(eq->buf);
4542 kfree(eq->l1_dma);
4543 kfree(eq->bt_l1);
4544 eq->buf_dma = NULL;
4545 eq->buf = NULL;
4546 eq->l1_dma = NULL;
4547 eq->bt_l1 = NULL;
4548}
4549
4550static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev,
4551 struct hns_roce_eq *eq)
4552{
4553 u32 buf_chk_sz;
4554
4555 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4556
4557 if (hr_dev->caps.eqe_hop_num) {
4558 hns_roce_mhop_free_eq(hr_dev, eq);
4559 return;
4560 }
4561
4562 if (eq->buf_list)
4563 dma_free_coherent(hr_dev->dev, buf_chk_sz,
4564 eq->buf_list->buf, eq->buf_list->map);
4565}
4566
4567static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
4568 struct hns_roce_eq *eq,
4569 void *mb_buf)
4570{
4571 struct hns_roce_eq_context *eqc;
4572
4573 eqc = mb_buf;
4574 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
4575
4576 /* init eqc */
4577 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
4578 eq->hop_num = hr_dev->caps.eqe_hop_num;
4579 eq->cons_index = 0;
4580 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
4581 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
4582 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
4583 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz;
4584 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz;
4585 eq->shift = ilog2((unsigned int)eq->entries);
4586
4587 if (!eq->hop_num)
4588 eq->eqe_ba = eq->buf_list->map;
4589 else
4590 eq->eqe_ba = eq->l0_dma;
4591
4592 /* set eqc state */
4593 roce_set_field(eqc->byte_4,
4594 HNS_ROCE_EQC_EQ_ST_M,
4595 HNS_ROCE_EQC_EQ_ST_S,
4596 HNS_ROCE_V2_EQ_STATE_VALID);
4597
4598 /* set eqe hop num */
4599 roce_set_field(eqc->byte_4,
4600 HNS_ROCE_EQC_HOP_NUM_M,
4601 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
4602
4603 /* set eqc over_ignore */
4604 roce_set_field(eqc->byte_4,
4605 HNS_ROCE_EQC_OVER_IGNORE_M,
4606 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
4607
4608 /* set eqc coalesce */
4609 roce_set_field(eqc->byte_4,
4610 HNS_ROCE_EQC_COALESCE_M,
4611 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
4612
4613 /* set eqc arm_state */
4614 roce_set_field(eqc->byte_4,
4615 HNS_ROCE_EQC_ARM_ST_M,
4616 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
4617
4618 /* set eqn */
4619 roce_set_field(eqc->byte_4,
4620 HNS_ROCE_EQC_EQN_M,
4621 HNS_ROCE_EQC_EQN_S, eq->eqn);
4622
4623 /* set eqe_cnt */
4624 roce_set_field(eqc->byte_4,
4625 HNS_ROCE_EQC_EQE_CNT_M,
4626 HNS_ROCE_EQC_EQE_CNT_S,
4627 HNS_ROCE_EQ_INIT_EQE_CNT);
4628
4629 /* set eqe_ba_pg_sz */
4630 roce_set_field(eqc->byte_8,
4631 HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db
YL		 4632 HNS_ROCE_EQC_BA_PG_SZ_S,
4633 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4634
4635 /* set eqe_buf_pg_sz */
4636 roce_set_field(eqc->byte_8,
4637 HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db
YL		 4638 HNS_ROCE_EQC_BUF_PG_SZ_S,
4639 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4640
4641 /* set eq_producer_idx */
4642 roce_set_field(eqc->byte_8,
4643 HNS_ROCE_EQC_PROD_INDX_M,
4644 HNS_ROCE_EQC_PROD_INDX_S,
4645 HNS_ROCE_EQ_INIT_PROD_IDX);
4646
4647 /* set eq_max_cnt */
4648 roce_set_field(eqc->byte_12,
4649 HNS_ROCE_EQC_MAX_CNT_M,
4650 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
4651
4652 /* set eq_period */
4653 roce_set_field(eqc->byte_12,
4654 HNS_ROCE_EQC_PERIOD_M,
4655 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
4656
4657 /* set eqe_report_timer */
4658 roce_set_field(eqc->eqe_report_timer,
4659 HNS_ROCE_EQC_REPORT_TIMER_M,
4660 HNS_ROCE_EQC_REPORT_TIMER_S,
4661 HNS_ROCE_EQ_INIT_REPORT_TIMER);
4662
4663 /* set eqe_ba [34:3] */
4664 roce_set_field(eqc->eqe_ba0,
4665 HNS_ROCE_EQC_EQE_BA_L_M,
4666 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3);
4667
4668 /* set eqe_ba [64:35] */
4669 roce_set_field(eqc->eqe_ba1,
4670 HNS_ROCE_EQC_EQE_BA_H_M,
4671 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35);
4672
4673 /* set eq shift */
4674 roce_set_field(eqc->byte_28,
4675 HNS_ROCE_EQC_SHIFT_M,
4676 HNS_ROCE_EQC_SHIFT_S, eq->shift);
4677
4678 /* set eq MSI_IDX */
4679 roce_set_field(eqc->byte_28,
4680 HNS_ROCE_EQC_MSI_INDX_M,
4681 HNS_ROCE_EQC_MSI_INDX_S,
4682 HNS_ROCE_EQ_INIT_MSI_IDX);
4683
4684 /* set cur_eqe_ba [27:12] */
4685 roce_set_field(eqc->byte_28,
4686 HNS_ROCE_EQC_CUR_EQE_BA_L_M,
4687 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12);
4688
4689 /* set cur_eqe_ba [59:28] */
4690 roce_set_field(eqc->byte_32,
4691 HNS_ROCE_EQC_CUR_EQE_BA_M_M,
4692 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28);
4693
4694 /* set cur_eqe_ba [63:60] */
4695 roce_set_field(eqc->byte_36,
4696 HNS_ROCE_EQC_CUR_EQE_BA_H_M,
4697 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60);
4698
4699 /* set eq consumer idx */
4700 roce_set_field(eqc->byte_36,
4701 HNS_ROCE_EQC_CONS_INDX_M,
4702 HNS_ROCE_EQC_CONS_INDX_S,
4703 HNS_ROCE_EQ_INIT_CONS_IDX);
4704
4705 /* set nex_eqe_ba[43:12] */
4706 roce_set_field(eqc->nxt_eqe_ba0,
4707 HNS_ROCE_EQC_NXT_EQE_BA_L_M,
4708 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12);
4709
4710 /* set nex_eqe_ba[63:44] */
4711 roce_set_field(eqc->nxt_eqe_ba1,
4712 HNS_ROCE_EQC_NXT_EQE_BA_H_M,
4713 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44);
4714}
4715
4716static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev,
4717 struct hns_roce_eq *eq)
4718{
4719 struct device *dev = hr_dev->dev;
4720 int eq_alloc_done = 0;
4721 int eq_buf_cnt = 0;
4722 int eqe_alloc;
4723 u32 buf_chk_sz;
4724 u32 bt_chk_sz;
4725 u32 mhop_num;
4726 u64 size;
4727 u64 idx;
4728 int ba_num;
4729 int bt_num;
4730 int record_i;
4731 int record_j;
4732 int i = 0;
4733 int j = 0;
4734
4735 mhop_num = hr_dev->caps.eqe_hop_num;
4736 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4737 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
4738
4739 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1)
4740 / buf_chk_sz;
4741 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8);
4742
4743 /* hop_num = 0 */
4744 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4745 if (eq->entries > buf_chk_sz / eq->eqe_size) {
4746 dev_err(dev, "eq entries %d is larger than buf_pg_sz!",
4747 eq->entries);
4748 return -EINVAL;
4749 }
4750 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size,
4751 &(eq->l0_dma), GFP_KERNEL);
4752 if (!eq->bt_l0)
4753 return -ENOMEM;
4754
4755 eq->cur_eqe_ba = eq->l0_dma;
4756 eq->nxt_eqe_ba = 0;
4757
4758 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size);
4759
4760 return 0;
4761 }
4762
4763 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL);
4764 if (!eq->buf_dma)
4765 return -ENOMEM;
4766 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL);
4767 if (!eq->buf)
4768 goto err_kcalloc_buf;
4769
4770 if (mhop_num == 2) {
4771 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL);
4772 if (!eq->l1_dma)
4773 goto err_kcalloc_l1_dma;
4774
4775 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL);
4776 if (!eq->bt_l1)
4777 goto err_kcalloc_bt_l1;
4778 }
4779
4780 /* alloc L0 BT */
4781 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL);
4782 if (!eq->bt_l0)
4783 goto err_dma_alloc_l0;
4784
4785 if (mhop_num == 1) {
4786 if (ba_num > (bt_chk_sz / 8))
4787 dev_err(dev, "ba_num %d is too large for 1 hop\n",
4788 ba_num);
4789
4790 /* alloc buf */
4791 for (i = 0; i < bt_chk_sz / 8; i++) {
4792 if (eq_buf_cnt + 1 < ba_num) {
4793 size = buf_chk_sz;
4794 } else {
4795 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4796 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4797 }
4798 eq->buf[i] = dma_alloc_coherent(dev, size,
4799 &(eq->buf_dma[i]),
4800 GFP_KERNEL);
4801 if (!eq->buf[i])
4802 goto err_dma_alloc_buf;
4803
4804 memset(eq->buf[i], 0, size);
4805 *(eq->bt_l0 + i) = eq->buf_dma[i];
4806
4807 eq_buf_cnt++;
4808 if (eq_buf_cnt >= ba_num)
4809 break;
4810 }
4811 eq->cur_eqe_ba = eq->buf_dma[0];
4812 eq->nxt_eqe_ba = eq->buf_dma[1];
4813
4814 } else if (mhop_num == 2) {
4815 /* alloc L1 BT and buf */
4816 for (i = 0; i < bt_chk_sz / 8; i++) {
4817 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz,
4818 &(eq->l1_dma[i]),
4819 GFP_KERNEL);
4820 if (!eq->bt_l1[i])
4821 goto err_dma_alloc_l1;
4822 *(eq->bt_l0 + i) = eq->l1_dma[i];
4823
4824 for (j = 0; j < bt_chk_sz / 8; j++) {
4825 idx = i * bt_chk_sz / 8 + j;
4826 if (eq_buf_cnt + 1 < ba_num) {
4827 size = buf_chk_sz;
4828 } else {
4829 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4830 * idx;
4831 size = (eq->entries - eqe_alloc)
4832 * eq->eqe_size;
4833 }
4834 eq->buf[idx] = dma_alloc_coherent(dev, size,
4835 &(eq->buf_dma[idx]),
4836 GFP_KERNEL);
4837 if (!eq->buf[idx])
4838 goto err_dma_alloc_buf;
4839
4840 memset(eq->buf[idx], 0, size);
4841 *(eq->bt_l1[i] + j) = eq->buf_dma[idx];
4842
4843 eq_buf_cnt++;
4844 if (eq_buf_cnt >= ba_num) {
4845 eq_alloc_done = 1;
4846 break;
4847 }
4848 }
4849
4850 if (eq_alloc_done)
4851 break;
4852 }
4853 eq->cur_eqe_ba = eq->buf_dma[0];
4854 eq->nxt_eqe_ba = eq->buf_dma[1];
4855 }
4856
4857 eq->l0_last_num = i + 1;
4858 if (mhop_num == 2)
4859 eq->l1_last_num = j + 1;
4860
4861 return 0;
4862
4863err_dma_alloc_l1:
4864 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4865 eq->bt_l0 = NULL;
4866 eq->l0_dma = 0;
4867 for (i -= 1; i >= 0; i--) {
4868 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4869 eq->l1_dma[i]);
4870
4871 for (j = 0; j < bt_chk_sz / 8; j++) {
4872 idx = i * bt_chk_sz / 8 + j;
4873 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4874 eq->buf_dma[idx]);
4875 }
4876 }
4877 goto err_dma_alloc_l0;
4878
4879err_dma_alloc_buf:
4880 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4881 eq->bt_l0 = NULL;
4882 eq->l0_dma = 0;
4883
4884 if (mhop_num == 1)
38759d61 4885 for (i -= 1; i >= 0; i--)
a5073d60
YL		 4886 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4887 eq->buf_dma[i]);
4888 else if (mhop_num == 2) {
4889 record_i = i;
4890 record_j = j;
4891 for (; i >= 0; i--) {
4892 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4893 eq->l1_dma[i]);
4894
4895 for (j = 0; j < bt_chk_sz / 8; j++) {
4896 if (i == record_i && j >= record_j)
4897 break;
4898
4899 idx = i * bt_chk_sz / 8 + j;
4900 dma_free_coherent(dev, buf_chk_sz,
4901 eq->buf[idx],
4902 eq->buf_dma[idx]);
4903 }
4904 }
4905 }
4906
4907err_dma_alloc_l0:
4908 kfree(eq->bt_l1);
4909 eq->bt_l1 = NULL;
4910
4911err_kcalloc_bt_l1:
4912 kfree(eq->l1_dma);
4913 eq->l1_dma = NULL;
4914
4915err_kcalloc_l1_dma:
4916 kfree(eq->buf);
4917 eq->buf = NULL;
4918
4919err_kcalloc_buf:
4920 kfree(eq->buf_dma);
4921 eq->buf_dma = NULL;
4922
4923 return -ENOMEM;
4924}
4925
4926static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
4927 struct hns_roce_eq *eq,
4928 unsigned int eq_cmd)
4929{
4930 struct device *dev = hr_dev->dev;
4931 struct hns_roce_cmd_mailbox *mailbox;
4932 u32 buf_chk_sz = 0;
4933 int ret;
4934
4935 /* Allocate mailbox memory */
4936 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4937 if (IS_ERR(mailbox))
4938 return PTR_ERR(mailbox);
4939
4940 if (!hr_dev->caps.eqe_hop_num) {
4941 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4942
4943 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list),
4944 GFP_KERNEL);
4945 if (!eq->buf_list) {
4946 ret = -ENOMEM;
4947 goto free_cmd_mbox;
4948 }
4949
4950 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz,
4951 &(eq->buf_list->map),
4952 GFP_KERNEL);
4953 if (!eq->buf_list->buf) {
4954 ret = -ENOMEM;
4955 goto err_alloc_buf;
4956 }
4957
4958 memset(eq->buf_list->buf, 0, buf_chk_sz);
4959 } else {
4960 ret = hns_roce_mhop_alloc_eq(hr_dev, eq);
4961 if (ret) {
4962 ret = -ENOMEM;
4963 goto free_cmd_mbox;
4964 }
4965 }
4966
4967 hns_roce_config_eqc(hr_dev, eq, mailbox->buf);
4968
4969 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
4970 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
4971 if (ret) {
ab178849 4972 dev_err(dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 4973 goto err_cmd_mbox;
4974 }
4975
4976 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4977
4978 return 0;
4979
4980err_cmd_mbox:
4981 if (!hr_dev->caps.eqe_hop_num)
4982 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf,
4983 eq->buf_list->map);
4984 else {
4985 hns_roce_mhop_free_eq(hr_dev, eq);
4986 goto free_cmd_mbox;
4987 }
4988
4989err_alloc_buf:
4990 kfree(eq->buf_list);
4991
4992free_cmd_mbox:
4993 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4994
4995 return ret;
4996}
4997
4998static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
4999{
5000 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5001 struct device *dev = hr_dev->dev;
5002 struct hns_roce_eq *eq;
5003 unsigned int eq_cmd;
5004 int irq_num;
5005 int eq_num;
5006 int other_num;
5007 int comp_num;
5008 int aeq_num;
5009 int i, j, k;
5010 int ret;
5011
5012 other_num = hr_dev->caps.num_other_vectors;
5013 comp_num = hr_dev->caps.num_comp_vectors;
5014 aeq_num = hr_dev->caps.num_aeq_vectors;
5015
5016 eq_num = comp_num + aeq_num;
5017 irq_num = eq_num + other_num;
5018
5019 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5020 if (!eq_table->eq)
5021 return -ENOMEM;
5022
5023 for (i = 0; i < irq_num; i++) {
5024 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5025 GFP_KERNEL);
5026 if (!hr_dev->irq_names[i]) {
5027 ret = -ENOMEM;
5028 goto err_failed_kzalloc;
5029 }
5030 }
5031
5032 /* create eq */
5033 for (j = 0; j < eq_num; j++) {
5034 eq = &eq_table->eq[j];
5035 eq->hr_dev = hr_dev;
5036 eq->eqn = j;
5037 if (j < comp_num) {
5038 /* CEQ */
5039 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5040 eq->type_flag = HNS_ROCE_CEQ;
5041 eq->entries = hr_dev->caps.ceqe_depth;
5042 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
5043 eq->irq = hr_dev->irq[j + other_num + aeq_num];
5044 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5045 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5046 } else {
5047 /* AEQ */
5048 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5049 eq->type_flag = HNS_ROCE_AEQ;
5050 eq->entries = hr_dev->caps.aeqe_depth;
5051 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
5052 eq->irq = hr_dev->irq[j - comp_num + other_num];
5053 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5054 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5055 }
5056
5057 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5058 if (ret) {
5059 dev_err(dev, "eq create failed.\n");
5060 goto err_create_eq_fail;
5061 }
5062 }
5063
5064 /* enable irq */
5065 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5066
5067 /* irq contains: abnormal + AEQ + CEQ*/
5068 for (k = 0; k < irq_num; k++)
5069 if (k < other_num)
5070 snprintf((char *)hr_dev->irq_names[k],
5071 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k);
5072 else if (k < (other_num + aeq_num))
5073 snprintf((char *)hr_dev->irq_names[k],
5074 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d",
5075 k - other_num);
5076 else
5077 snprintf((char *)hr_dev->irq_names[k],
5078 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d",
5079 k - other_num - aeq_num);
5080
5081 for (k = 0; k < irq_num; k++) {
5082 if (k < other_num)
5083 ret = request_irq(hr_dev->irq[k],
5084 hns_roce_v2_msix_interrupt_abn,
5085 0, hr_dev->irq_names[k], hr_dev);
5086
5087 else if (k < (other_num + comp_num))
5088 ret = request_irq(eq_table->eq[k - other_num].irq,
5089 hns_roce_v2_msix_interrupt_eq,
5090 0, hr_dev->irq_names[k + aeq_num],
5091 &eq_table->eq[k - other_num]);
5092 else
5093 ret = request_irq(eq_table->eq[k - other_num].irq,
5094 hns_roce_v2_msix_interrupt_eq,
5095 0, hr_dev->irq_names[k - comp_num],
5096 &eq_table->eq[k - other_num]);
5097 if (ret) {
5098 dev_err(dev, "Request irq error!\n");
5099 goto err_request_irq_fail;
5100 }
5101 }
5102
0425e3e6
YL		 5103 hr_dev->irq_workq =
5104 create_singlethread_workqueue("hns_roce_irq_workqueue");
5105 if (!hr_dev->irq_workq) {
5106 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5107 ret = -ENOMEM;
0425e3e6
YL		 5108 goto err_request_irq_fail;
5109 }
5110
a5073d60
YL		 5111 return 0;
5112
5113err_request_irq_fail:
5114 for (k -= 1; k >= 0; k--)
5115 if (k < other_num)
5116 free_irq(hr_dev->irq[k], hr_dev);
5117 else
5118 free_irq(eq_table->eq[k - other_num].irq,
5119 &eq_table->eq[k - other_num]);
5120
5121err_create_eq_fail:
5122 for (j -= 1; j >= 0; j--)
5123 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]);
5124
5125err_failed_kzalloc:
5126 for (i -= 1; i >= 0; i--)
5127 kfree(hr_dev->irq_names[i]);
5128 kfree(eq_table->eq);
5129
5130 return ret;
5131}
5132
5133static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5134{
5135 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5136 int irq_num;
5137 int eq_num;
5138 int i;
5139
5140 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5141 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5142
5143 /* Disable irq */
5144 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5145
5146 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5147 free_irq(hr_dev->irq[i], hr_dev);
5148
5149 for (i = 0; i < eq_num; i++) {
5150 hns_roce_v2_destroy_eqc(hr_dev, i);
5151
5152 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]);
5153
5154 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]);
5155 }
5156
5157 for (i = 0; i < irq_num; i++)
5158 kfree(hr_dev->irq_names[i]);
5159
5160 kfree(eq_table->eq);
0425e3e6
YL		 5161
5162 flush_workqueue(hr_dev->irq_workq);
5163 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5164}
5165
a04ff739
WHX		 5166static const struct hns_roce_hw hns_roce_hw_v2 = {
5167 .cmq_init = hns_roce_v2_cmq_init,
5168 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5169 .hw_profile = hns_roce_v2_profile,
6b63597d 5170 .hw_init = hns_roce_v2_init,
5171 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5172 .post_mbox = hns_roce_v2_post_mbox,
5173 .chk_mbox = hns_roce_v2_chk_mbox,
7afddafa
WHX		 5174 .set_gid = hns_roce_v2_set_gid,
5175 .set_mac = hns_roce_v2_set_mac,
3958cc56 5176 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5177 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
93aa2187 5178 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5179 .set_hem = hns_roce_v2_set_hem,
5180 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5181 .modify_qp = hns_roce_v2_modify_qp,
5182 .query_qp = hns_roce_v2_query_qp,
5183 .destroy_qp = hns_roce_v2_destroy_qp,
b156269d 5184 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5185 .post_send = hns_roce_v2_post_send,
5186 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5187 .req_notify_cq = hns_roce_v2_req_notify_cq,
5188 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5189 .init_eq = hns_roce_v2_init_eq_table,
5190 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
a04ff739 5191};
dd74282d
WHX		 5192
5193static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5194 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5195 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 5196 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
5197 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 5198 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
5199 /* required last entry */
5200 {0, }
5201};
5202
f97a62c3 5203MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
5204
dd74282d
WHX		 5205static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
5206 struct hnae3_handle *handle)
5207{
5208 const struct pci_device_id *id;
a5073d60 5209 int i;
dd74282d
WHX		 5210
5211 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
5212 if (!id) {
5213 dev_err(hr_dev->dev, "device is not compatible!\n");
5214 return -ENXIO;
5215 }
5216
5217 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 5218 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
5219 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 5220
5221 /* Get info from NIC driver. */
5222 hr_dev->reg_base = handle->rinfo.roce_io_base;
5223 hr_dev->caps.num_ports = 1;
5224 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
5225 hr_dev->iboe.phy_port[0] = 0;
5226
d4994d2f 5227 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
5228 hr_dev->iboe.netdevs[0]->dev_addr);
5229
a5073d60
YL		 5230 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
5231 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
5232 i + handle->rinfo.base_vector);
5233
dd74282d 5234 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 5235 hr_dev->cmd_mod = 1;
dd74282d
WHX		 5236 hr_dev->loop_idc = 0;
5237
5238 return 0;
5239}
5240
5241static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
5242{
5243 struct hns_roce_dev *hr_dev;
5244 int ret;
5245
5246 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
5247 if (!hr_dev)
5248 return -ENOMEM;
5249
a04ff739
WHX		 5250 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
5251 if (!hr_dev->priv) {
5252 ret = -ENOMEM;
5253 goto error_failed_kzalloc;
5254 }
5255
dd74282d
WHX		 5256 hr_dev->pci_dev = handle->pdev;
5257 hr_dev->dev = &handle->pdev->dev;
5258 handle->priv = hr_dev;
5259
5260 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
5261 if (ret) {
5262 dev_err(hr_dev->dev, "Get Configuration failed!\n");
5263 goto error_failed_get_cfg;
5264 }
5265
5266 ret = hns_roce_init(hr_dev);
5267 if (ret) {
5268 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
5269 goto error_failed_get_cfg;
5270 }
5271
5272 return 0;
5273
5274error_failed_get_cfg:
a04ff739
WHX		 5275 kfree(hr_dev->priv);
5276
5277error_failed_kzalloc:
dd74282d
WHX		 5278 ib_dealloc_device(&hr_dev->ib_dev);
5279
5280 return ret;
5281}
5282
5283static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
5284 bool reset)
5285{
5286 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5287
cb7a94c9
WHX		 5288 if (!hr_dev)
5289 return;
5290
dd74282d 5291 hns_roce_exit(hr_dev);
a04ff739 5292 kfree(hr_dev->priv);
dd74282d
WHX		 5293 ib_dealloc_device(&hr_dev->ib_dev);
5294}
5295
cb7a94c9
WHX		 5296static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
5297{
5298 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5299 struct ib_event event;
5300
5301 if (!hr_dev) {
5302 dev_err(&handle->pdev->dev,
5303 "Input parameter handle->priv is NULL!\n");
5304 return -EINVAL;
5305 }
5306
5307 hr_dev->active = false;
5308 hr_dev->is_reset = true;
5309
5310 event.event = IB_EVENT_DEVICE_FATAL;
5311 event.device = &hr_dev->ib_dev;
5312 event.element.port_num = 1;
5313 ib_dispatch_event(&event);
5314
5315 return 0;
5316}
5317
5318static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
5319{
5320 int ret;
5321
5322 ret = hns_roce_hw_v2_init_instance(handle);
5323 if (ret) {
5324 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
5325 * callback function, RoCE Engine reinitialize. If RoCE reinit
5326 * failed, we should inform NIC driver.
5327 */
5328 handle->priv = NULL;
5329 dev_err(&handle->pdev->dev,
5330 "In reset process RoCE reinit failed %d.\n", ret);
5331 }
5332
5333 return ret;
5334}
5335
5336static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
5337{
5338 msleep(100);
5339 hns_roce_hw_v2_uninit_instance(handle, false);
5340 return 0;
5341}
5342
5343static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
5344 enum hnae3_reset_notify_type type)
5345{
5346 int ret = 0;
5347
5348 switch (type) {
5349 case HNAE3_DOWN_CLIENT:
5350 ret = hns_roce_hw_v2_reset_notify_down(handle);
5351 break;
5352 case HNAE3_INIT_CLIENT:
5353 ret = hns_roce_hw_v2_reset_notify_init(handle);
5354 break;
5355 case HNAE3_UNINIT_CLIENT:
5356 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
5357 break;
5358 default:
5359 break;
5360 }
5361
5362 return ret;
5363}
5364
dd74282d
WHX		 5365static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
5366 .init_instance = hns_roce_hw_v2_init_instance,
5367 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 5368 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 5369};
5370
5371static struct hnae3_client hns_roce_hw_v2_client = {
5372 .name = "hns_roce_hw_v2",
5373 .type = HNAE3_CLIENT_ROCE,
5374 .ops = &hns_roce_hw_v2_ops,
5375};
5376
5377static int __init hns_roce_hw_v2_init(void)
5378{
5379 return hnae3_register_client(&hns_roce_hw_v2_client);
5380}
5381
5382static void __exit hns_roce_hw_v2_exit(void)
5383{
5384 hnae3_unregister_client(&hns_roce_hw_v2_client);
5385}
5386
5387module_init(hns_roce_hw_v2_init);
5388module_exit(hns_roce_hw_v2_exit);
5389
5390MODULE_LICENSE("Dual BSD/GPL");
5391MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5392MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5393MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
5394MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)