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RDMA/hns: Support 0 hop addressing for SRQ buffer
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
a70c0739 40#include <rdma/ib_cache.h>
dd74282d 41#include <rdma/ib_umem.h>
bdeacabd 42#include <rdma/uverbs_ioctl.h>
dd74282d
WHX		 43
44#include "hnae3.h"
45#include "hns_roce_common.h"
46#include "hns_roce_device.h"
47#include "hns_roce_cmd.h"
48#include "hns_roce_hem.h"
a04ff739 49#include "hns_roce_hw_v2.h"
dd74282d 50
2d407888
WHX		 51static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
52 struct ib_sge *sg)
53{
54 dseg->lkey = cpu_to_le32(sg->lkey);
55 dseg->addr = cpu_to_le64(sg->addr);
56 dseg->len = cpu_to_le32(sg->length);
57}
58
e363f7de
XW		 59/*
60 * mapped-value = 1 + real-value
61 * The hns wr opcode real value is start from 0, In order to distinguish between
62 * initialized and uninitialized map values, we plus 1 to the actual value when
63 * defining the mapping, so that the validity can be identified by checking the
64 * mapped value is greater than 0.
65 */
66#define HR_OPC_MAP(ib_key, hr_key) \
67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
68
69static const u32 hns_roce_op_code[] = {
70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
72 HR_OPC_MAP(SEND, SEND),
73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
74 HR_OPC_MAP(RDMA_READ, RDMA_READ),
75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV),
79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
81 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
82};
83
84static u32 to_hr_opcode(u32 ib_opcode)
85{
86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
87 return HNS_ROCE_V2_WQE_OP_MASK;
88
89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
90 HNS_ROCE_V2_WQE_OP_MASK;
91}
92
68a997c5 93static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
00a59d30 94 void *wqe, const struct ib_reg_wr *wr)
68a997c5
YL		 95{
96 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
00a59d30 97 struct hns_roce_wqe_frmr_seg *fseg = wqe;
68a997c5
YL		 98
99 /* use ib_access_flags */
60262b10 100 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
68a997c5 101 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
60262b10 102 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
68a997c5 103 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
60262b10 104 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S,
68a997c5 105 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
60262b10 106 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S,
68a997c5 107 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
60262b10 108 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S,
68a997c5
YL		 109 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
110
111 /* Data structure reuse may lead to confusion */
112 rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff);
113 rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32);
114
115 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
116 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
117 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
118 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
119
120 fseg->pbl_size = cpu_to_le32(mr->pbl_size);
121 roce_set_field(fseg->mode_buf_pg_sz,
122 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
123 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
124 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
125 roce_set_bit(fseg->mode_buf_pg_sz,
126 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
127}
128
00a59d30
XW		 129static void set_atomic_seg(const struct ib_send_wr *wr, void *wqe,
130 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
131 int valid_num_sge)
384f8818 132{
00a59d30
XW		 133 struct hns_roce_wqe_atomic_seg *aseg;
134
135 set_data_seg_v2(wqe, wr->sg_list);
136 aseg = wqe + sizeof(struct hns_roce_v2_wqe_data_seg);
137
138 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
139 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
140 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
384f8818 141 } else {
00a59d30
XW		 142 aseg->fetchadd_swap_data =
143 cpu_to_le64(atomic_wr(wr)->compare_add);
384f8818
LO		 144 aseg->cmp_data = 0;
145 }
00a59d30
XW		 146
147 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
148 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
384f8818
LO		 149}
150
f696bf6d 151static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
468d020e 152 unsigned int *sge_ind, int valid_num_sge)
0b25c9cc
WHX		 153{
154 struct hns_roce_v2_wqe_data_seg *dseg;
155 struct ib_sge *sg;
156 int num_in_wqe = 0;
157 int extend_sge_num;
158 int fi_sge_num;
159 int se_sge_num;
160 int shift;
161 int i;
162
163 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
164 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
468d020e 165 extend_sge_num = valid_num_sge - num_in_wqe;
0b25c9cc 166 sg = wr->sg_list + num_in_wqe;
d563099e 167 shift = qp->mtr.hem_cfg.buf_pg_shift;
0b25c9cc
WHX		 168
169 /*
170 * Check whether wr->num_sge sges are in the same page. If not, we
171 * should calculate how many sges in the first page and the second
172 * page.
173 */
6c6e3921 174 dseg = hns_roce_get_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
0b25c9cc
WHX		 175 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
176 (uintptr_t)dseg) /
177 sizeof(struct hns_roce_v2_wqe_data_seg);
178 if (extend_sge_num > fi_sge_num) {
179 se_sge_num = extend_sge_num - fi_sge_num;
180 for (i = 0; i < fi_sge_num; i++) {
181 set_data_seg_v2(dseg++, sg + i);
182 (*sge_ind)++;
183 }
6c6e3921 184 dseg = hns_roce_get_extend_sge(qp,
0b25c9cc
WHX		 185 (*sge_ind) & (qp->sge.sge_cnt - 1));
186 for (i = 0; i < se_sge_num; i++) {
187 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
188 (*sge_ind)++;
189 }
190 } else {
191 for (i = 0; i < extend_sge_num; i++) {
192 set_data_seg_v2(dseg++, sg + i);
193 (*sge_ind)++;
194 }
195 }
196}
197
f696bf6d 198static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 199 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
200 void *wqe, unsigned int *sge_ind,
00a59d30 201 int valid_num_sge)
7bdee415 202{
203 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
204 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
00a59d30 205 struct ib_device *ibdev = &hr_dev->ib_dev;
7bdee415 206 struct hns_roce_qp *qp = to_hr_qp(ibqp);
468d020e 207 int j = 0;
7bdee415 208 int i;
209
468d020e 210 if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) {
8b9b8d14 211 if (le32_to_cpu(rc_sq_wqe->msg_len) >
212 hr_dev->caps.max_sq_inline) {
00a59d30
XW		 213 ibdev_err(ibdev, "inline len(1-%d)=%d, illegal",
214 rc_sq_wqe->msg_len,
215 hr_dev->caps.max_sq_inline);
7bdee415 216 return -EINVAL;
217 }
218
328d405b 219 if (wr->opcode == IB_WR_RDMA_READ) {
00a59d30 220 ibdev_err(ibdev, "Not support inline data!\n");
328d405b 221 return -EINVAL;
222 }
223
7bdee415 224 for (i = 0; i < wr->num_sge; i++) {
225 memcpy(wqe, ((void *)wr->sg_list[i].addr),
226 wr->sg_list[i].length);
227 wqe += wr->sg_list[i].length;
228 }
229
230 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
231 1);
232 } else {
468d020e 233 if (valid_num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 234 for (i = 0; i < wr->num_sge; i++) {
235 if (likely(wr->sg_list[i].length)) {
236 set_data_seg_v2(dseg, wr->sg_list + i);
237 dseg++;
238 }
239 }
240 } else {
241 roce_set_field(rc_sq_wqe->byte_20,
242 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
243 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
244 (*sge_ind) & (qp->sge.sge_cnt - 1));
245
468d020e
LO		 246 for (i = 0; i < wr->num_sge &&
247 j < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 248 if (likely(wr->sg_list[i].length)) {
249 set_data_seg_v2(dseg, wr->sg_list + i);
250 dseg++;
468d020e 251 j++;
7bdee415 252 }
253 }
254
468d020e 255 set_extend_sge(qp, wr, sge_ind, valid_num_sge);
7bdee415 256 }
257
258 roce_set_field(rc_sq_wqe->byte_16,
259 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
468d020e 260 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
7bdee415 261 }
262
263 return 0;
264}
265
626903e9
XW		 266static int check_send_valid(struct hns_roce_dev *hr_dev,
267 struct hns_roce_qp *hr_qp)
268{
ae1c6148 269 struct ib_device *ibdev = &hr_dev->ib_dev;
626903e9 270 struct ib_qp *ibqp = &hr_qp->ibqp;
626903e9
XW		 271
272 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
273 ibqp->qp_type != IB_QPT_GSI &&
274 ibqp->qp_type != IB_QPT_UD)) {
ae1c6148
LO		 275 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n",
276 ibqp->qp_type);
626903e9
XW		 277 return -EOPNOTSUPP;
278 } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
279 hr_qp->state == IB_QPS_INIT ||
280 hr_qp->state == IB_QPS_RTR)) {
ae1c6148
LO		 281 ibdev_err(ibdev, "failed to post WQE, QP state %d!\n",
282 hr_qp->state);
626903e9
XW		 283 return -EINVAL;
284 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
ae1c6148
LO		 285 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
286 hr_dev->state);
626903e9
XW		 287 return -EIO;
288 }
289
290 return 0;
291}
292
d6a3627e
XW		 293static inline int calc_wr_sge_num(const struct ib_send_wr *wr, u32 *sge_len)
294{
295 int valid_num = 0;
296 u32 len = 0;
297 int i;
298
299 for (i = 0; i < wr->num_sge; i++) {
300 if (likely(wr->sg_list[i].length)) {
301 len += wr->sg_list[i].length;
302 valid_num++;
303 }
304 }
305
306 *sge_len = len;
307 return valid_num;
308}
309
310static inline int set_ud_wqe(struct hns_roce_qp *qp,
311 const struct ib_send_wr *wr,
312 void *wqe, unsigned int *sge_idx,
313 unsigned int owner_bit)
314{
315 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
316 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
317 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
318 unsigned int curr_idx = *sge_idx;
319 int valid_num_sge;
320 u32 msg_len = 0;
321 bool loopback;
322 u8 *smac;
323
324 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
325 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
326
327 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
328 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
329 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
330 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
331 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
332 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
333 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
334 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
335 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
336 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]);
337 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
338 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]);
339
340 /* MAC loopback */
341 smac = (u8 *)hr_dev->dev_addr[qp->port];
342 loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0;
343
344 roce_set_bit(ud_sq_wqe->byte_40,
345 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
346
347 roce_set_field(ud_sq_wqe->byte_4,
348 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
349 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
350 HNS_ROCE_V2_WQE_OP_SEND);
351
352 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
353
354 switch (wr->opcode) {
355 case IB_WR_SEND_WITH_IMM:
356 case IB_WR_RDMA_WRITE_WITH_IMM:
357 ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
358 break;
359 default:
360 ud_sq_wqe->immtdata = 0;
361 break;
362 }
363
364 /* Set sig attr */
365 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S,
366 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
367
368 /* Set se attr */
369 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S,
370 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
371
372 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S,
373 owner_bit);
374
375 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M,
376 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn);
377
378 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
379 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
380
381 roce_set_field(ud_sq_wqe->byte_20,
382 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
383 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
384 curr_idx & (qp->sge.sge_cnt - 1));
385
386 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
387 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
388 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
389 qp->qkey : ud_wr(wr)->remote_qkey);
390 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M,
391 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn);
392
393 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M,
394 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id);
395 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
396 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit);
397 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
398 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass);
399 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
400 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel);
401 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M,
402 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl);
403 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M,
404 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port);
405
406 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
407 ah->av.vlan_en ? 1 : 0);
408 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
409 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index);
410
411 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2);
412
413 set_extend_sge(qp, wr, &curr_idx, valid_num_sge);
414
415 *sge_idx = curr_idx;
416
417 return 0;
418}
419
420static inline int set_rc_wqe(struct hns_roce_qp *qp,
421 const struct ib_send_wr *wr,
422 void *wqe, unsigned int *sge_idx,
423 unsigned int owner_bit)
424{
425 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
426 unsigned int curr_idx = *sge_idx;
427 int valid_num_sge;
428 u32 msg_len = 0;
429 int ret = 0;
430
431 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
432 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
433
434 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
435
436 switch (wr->opcode) {
437 case IB_WR_SEND_WITH_IMM:
438 case IB_WR_RDMA_WRITE_WITH_IMM:
439 rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
440 break;
441 case IB_WR_SEND_WITH_INV:
442 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
443 break;
444 default:
445 rc_sq_wqe->immtdata = 0;
446 break;
447 }
448
449 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
450 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
451
452 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
453 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
454
455 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
456 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
457
458 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
459 owner_bit);
460
461 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
462 switch (wr->opcode) {
463 case IB_WR_RDMA_READ:
464 case IB_WR_RDMA_WRITE:
465 case IB_WR_RDMA_WRITE_WITH_IMM:
466 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
467 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
468 break;
469 case IB_WR_LOCAL_INV:
470 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
471 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
472 break;
473 case IB_WR_REG_MR:
474 set_frmr_seg(rc_sq_wqe, wqe, reg_wr(wr));
475 break;
476 case IB_WR_ATOMIC_CMP_AND_SWP:
477 case IB_WR_ATOMIC_FETCH_AND_ADD:
478 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
479 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
480 break;
481 default:
482 break;
483 }
484
485 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
486 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
487 to_hr_opcode(wr->opcode));
488
489 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
490 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
491 set_atomic_seg(wr, wqe, rc_sq_wqe, valid_num_sge);
492 else if (wr->opcode != IB_WR_REG_MR)
493 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
494 wqe, &curr_idx, valid_num_sge);
495
496 *sge_idx = curr_idx;
497
498 return ret;
499}
500
75c994e6
YL		 501static inline void update_sq_db(struct hns_roce_dev *hr_dev,
502 struct hns_roce_qp *qp)
503{
504 /*
505 * Hip08 hardware cannot flush the WQEs in SQ if the QP state
506 * gets into errored mode. Hence, as a workaround to this
507 * hardware limitation, driver needs to assist in flushing. But
508 * the flushing operation uses mailbox to convey the QP state to
509 * the hardware and which can sleep due to the mutex protection
510 * around the mailbox calls. Hence, use the deferred flush for
511 * now.
512 */
513 if (qp->state == IB_QPS_ERR) {
514 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
515 init_flush_work(hr_dev, qp);
516 } else {
517 struct hns_roce_v2_db sq_db = {};
518
519 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
520 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
521 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
522 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
523 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
524 V2_DB_PARAMETER_IDX_S,
525 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
526 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
527 V2_DB_PARAMETER_SL_S, qp->sl);
528
529 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l);
530 }
531}
532
d34ac5cd
BVA		 533static int hns_roce_v2_post_send(struct ib_qp *ibqp,
534 const struct ib_send_wr *wr,
535 const struct ib_send_wr **bad_wr)
2d407888
WHX		 536{
537 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
d6a3627e 538 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 539 struct hns_roce_qp *qp = to_hr_qp(ibqp);
d6a3627e 540 unsigned long flags = 0;
e8d18533 541 unsigned int owner_bit;
47688202
YL		 542 unsigned int sge_idx;
543 unsigned int wqe_idx;
2d407888 544 void *wqe = NULL;
2d407888 545 int nreq;
626903e9 546 int ret;
2d407888 547
626903e9 548 spin_lock_irqsave(&qp->sq.lock, flags);
2d407888 549
626903e9
XW		 550 ret = check_send_valid(hr_dev, qp);
551 if (ret) {
2d407888 552 *bad_wr = wr;
626903e9
XW		 553 nreq = 0;
554 goto out;
2d407888
WHX		 555 }
556
47688202 557 sge_idx = qp->next_sge;
2d407888
WHX		 558
559 for (nreq = 0; wr; ++nreq, wr = wr->next) {
560 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
561 ret = -ENOMEM;
562 *bad_wr = wr;
563 goto out;
564 }
565
47688202
YL		 566 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
567
2d407888 568 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
d6a3627e
XW		 569 ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n",
570 wr->num_sge, qp->sq.max_gs);
2d407888
WHX		 571 ret = -EINVAL;
572 *bad_wr = wr;
573 goto out;
574 }
575
6c6e3921 576 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
47688202 577 qp->sq.wrid[wqe_idx] = wr->wr_id;
634f6390 578 owner_bit =
579 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
468d020e 580
7bdee415 581 /* Corresponding to the QP type, wqe process separately */
d6a3627e
XW		 582 if (ibqp->qp_type == IB_QPT_GSI)
583 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
584 else if (ibqp->qp_type == IB_QPT_RC)
585 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
d6a3627e
XW		 586
587 if (ret) {
588 *bad_wr = wr;
589 goto out;
590 }
2d407888
WHX		 591 }
592
593out:
594 if (likely(nreq)) {
595 qp->sq.head += nreq;
75c994e6 596 qp->next_sge = sge_idx;
2d407888
WHX		 597 /* Memory barrier */
598 wmb();
75c994e6 599 update_sq_db(hr_dev, qp);
2d407888
WHX		 600 }
601
602 spin_unlock_irqrestore(&qp->sq.lock, flags);
603
604 return ret;
605}
606
626903e9
XW		 607static int check_recv_valid(struct hns_roce_dev *hr_dev,
608 struct hns_roce_qp *hr_qp)
609{
610 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
611 return -EIO;
612 else if (hr_qp->state == IB_QPS_RESET)
613 return -EINVAL;
614
615 return 0;
616}
617
d34ac5cd
BVA		 618static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
619 const struct ib_recv_wr *wr,
620 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 621{
622 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
623 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 624 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 625 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 626 struct hns_roce_rinl_sge *sge_list;
2d407888
WHX		 627 unsigned long flags;
628 void *wqe = NULL;
47688202 629 u32 wqe_idx;
2d407888 630 int nreq;
626903e9 631 int ret;
2d407888
WHX		 632 int i;
633
634 spin_lock_irqsave(&hr_qp->rq.lock, flags);
2d407888 635
626903e9
XW		 636 ret = check_recv_valid(hr_dev, hr_qp);
637 if (ret) {
2d407888 638 *bad_wr = wr;
626903e9
XW		 639 nreq = 0;
640 goto out;
2d407888
WHX		 641 }
642
643 for (nreq = 0; wr; ++nreq, wr = wr->next) {
644 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
645 hr_qp->ibqp.recv_cq)) {
646 ret = -ENOMEM;
647 *bad_wr = wr;
648 goto out;
649 }
650
47688202
YL		 651 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
652
2d407888 653 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
ae1c6148
LO		 654 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n",
655 wr->num_sge, hr_qp->rq.max_gs);
2d407888
WHX		 656 ret = -EINVAL;
657 *bad_wr = wr;
658 goto out;
659 }
660
6c6e3921 661 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
2d407888
WHX		 662 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
663 for (i = 0; i < wr->num_sge; i++) {
664 if (!wr->sg_list[i].length)
665 continue;
666 set_data_seg_v2(dseg, wr->sg_list + i);
667 dseg++;
668 }
669
670 if (i < hr_qp->rq.max_gs) {
778cc5a8 671 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
672 dseg->addr = 0;
2d407888
WHX		 673 }
674
0009c2db 675 /* rq support inline data */
ecaaf1e2 676 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
47688202
YL		 677 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
678 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt =
ecaaf1e2 679 (u32)wr->num_sge;
680 for (i = 0; i < wr->num_sge; i++) {
681 sge_list[i].addr =
682 (void *)(u64)wr->sg_list[i].addr;
683 sge_list[i].len = wr->sg_list[i].length;
684 }
0009c2db 685 }
686
47688202 687 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
2d407888
WHX		 688 }
689
690out:
691 if (likely(nreq)) {
692 hr_qp->rq.head += nreq;
693 /* Memory barrier */
694 wmb();
695
b5374286
YL		 696 /*
697 * Hip08 hardware cannot flush the WQEs in RQ if the QP state
698 * gets into errored mode. Hence, as a workaround to this
699 * hardware limitation, driver needs to assist in flushing. But
700 * the flushing operation uses mailbox to convey the QP state to
701 * the hardware and which can sleep due to the mutex protection
702 * around the mailbox calls. Hence, use the deferred flush for
703 * now.
704 */
75c994e6 705 if (hr_qp->state == IB_QPS_ERR) {
b5374286
YL		 706 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG,
707 &hr_qp->flush_flag))
708 init_flush_work(hr_dev, hr_qp);
75c994e6
YL		 709 } else {
710 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
711 }
2d407888
WHX		 712 }
713 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
714
715 return ret;
716}
717
6a04aed6
WHX		 718static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
719 unsigned long instance_stage,
720 unsigned long reset_stage)
721{
722 /* When hardware reset has been completed once or more, we should stop
d3743fa9 723 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
6a04aed6
WHX		 724 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
725 * stage of soft reset process, we should exit with error, and then
726 * HNAE3_INIT_CLIENT related process can rollback the operation like
727 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
728 * process will exit with error to notify NIC driver to reschedule soft
729 * reset process once again.
730 */
731 hr_dev->is_reset = true;
d3743fa9 732 hr_dev->dis_db = true;
6a04aed6
WHX		 733
734 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
735 instance_stage == HNS_ROCE_STATE_INIT)
736 return CMD_RST_PRC_EBUSY;
737
738 return CMD_RST_PRC_SUCCESS;
739}
740
741static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
742 unsigned long instance_stage,
743 unsigned long reset_stage)
744{
745 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
746 struct hnae3_handle *handle = priv->handle;
747 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
748
d3743fa9
WHX		 749 /* When hardware reset is detected, we should stop sending mailbox&cmq&
750 * doorbell to hardware. If now in .init_instance() function, we should
6a04aed6
WHX		 751 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
752 * process, we should exit with error, and then HNAE3_INIT_CLIENT
753 * related process can rollback the operation like notifing hardware to
754 * free resources, HNAE3_INIT_CLIENT related process will exit with
755 * error to notify NIC driver to reschedule soft reset process once
756 * again.
757 */
d3743fa9 758 hr_dev->dis_db = true;
6a04aed6
WHX		 759 if (!ops->get_hw_reset_stat(handle))
760 hr_dev->is_reset = true;
761
762 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
763 instance_stage == HNS_ROCE_STATE_INIT)
764 return CMD_RST_PRC_EBUSY;
765
766 return CMD_RST_PRC_SUCCESS;
767}
768
769static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
770{
771 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
772 struct hnae3_handle *handle = priv->handle;
773 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
774
775 /* When software reset is detected at .init_instance() function, we
d3743fa9
WHX		 776 * should stop sending mailbox&cmq&doorbell to hardware, and exit
777 * with error.
6a04aed6 778 */
d3743fa9 779 hr_dev->dis_db = true;
6a04aed6
WHX		 780 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
781 hr_dev->is_reset = true;
782
783 return CMD_RST_PRC_EBUSY;
784}
785
786static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
787{
788 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
789 struct hnae3_handle *handle = priv->handle;
790 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
791 unsigned long instance_stage; /* the current instance stage */
792 unsigned long reset_stage; /* the current reset stage */
793 unsigned long reset_cnt;
794 bool sw_resetting;
795 bool hw_resetting;
796
797 if (hr_dev->is_reset)
798 return CMD_RST_PRC_SUCCESS;
799
800 /* Get information about reset from NIC driver or RoCE driver itself,
801 * the meaning of the following variables from NIC driver are described
802 * as below:
803 * reset_cnt -- The count value of completed hardware reset.
804 * hw_resetting -- Whether hardware device is resetting now.
805 * sw_resetting -- Whether NIC's software reset process is running now.
806 */
807 instance_stage = handle->rinfo.instance_state;
808 reset_stage = handle->rinfo.reset_state;
809 reset_cnt = ops->ae_dev_reset_cnt(handle);
810 hw_resetting = ops->get_hw_reset_stat(handle);
811 sw_resetting = ops->ae_dev_resetting(handle);
812
813 if (reset_cnt != hr_dev->reset_cnt)
814 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
815 reset_stage);
816 else if (hw_resetting)
817 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
818 reset_stage);
819 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
820 return hns_roce_v2_cmd_sw_resetting(hr_dev);
821
822 return 0;
823}
824
a04ff739
WHX		 825static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
826{
827 int ntu = ring->next_to_use;
828 int ntc = ring->next_to_clean;
829 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
830
831 return ring->desc_num - used - 1;
832}
833
834static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
835 struct hns_roce_v2_cmq_ring *ring)
836{
837 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
838
839 ring->desc = kzalloc(size, GFP_KERNEL);
840 if (!ring->desc)
841 return -ENOMEM;
842
843 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
844 DMA_BIDIRECTIONAL);
845 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
846 ring->desc_dma_addr = 0;
847 kfree(ring->desc);
848 ring->desc = NULL;
849 return -ENOMEM;
850 }
851
852 return 0;
853}
854
855static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
856 struct hns_roce_v2_cmq_ring *ring)
857{
858 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
859 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
860 DMA_BIDIRECTIONAL);
90e7a4d5 861
862 ring->desc_dma_addr = 0;
a04ff739
WHX		 863 kfree(ring->desc);
864}
865
866static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
867{
868 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
869 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
870 &priv->cmq.csq : &priv->cmq.crq;
871
872 ring->flag = ring_type;
873 ring->next_to_clean = 0;
874 ring->next_to_use = 0;
875
876 return hns_roce_alloc_cmq_desc(hr_dev, ring);
877}
878
879static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
880{
881 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
882 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
883 &priv->cmq.csq : &priv->cmq.crq;
884 dma_addr_t dma = ring->desc_dma_addr;
885
886 if (ring_type == TYPE_CSQ) {
887 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
888 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
889 upper_32_bits(dma));
890 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
2288b3b3 891 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 892 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
893 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
894 } else {
895 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
896 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
897 upper_32_bits(dma));
898 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
2288b3b3 899 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 900 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
901 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
902 }
903}
904
905static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
906{
907 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
908 int ret;
909
910 /* Setup the queue entries for command queue */
426c4146
LO		 911 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
912 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 913
914 /* Setup the lock for command queue */
915 spin_lock_init(&priv->cmq.csq.lock);
916 spin_lock_init(&priv->cmq.crq.lock);
917
918 /* Setup Tx write back timeout */
919 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
920
921 /* Init CSQ */
922 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
923 if (ret) {
924 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
925 return ret;
926 }
927
928 /* Init CRQ */
929 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
930 if (ret) {
931 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
932 goto err_crq;
933 }
934
935 /* Init CSQ REG */
936 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
937
938 /* Init CRQ REG */
939 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
940
941 return 0;
942
943err_crq:
944 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
945
946 return ret;
947}
948
949static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
950{
951 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
952
953 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
954 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
955}
956
281d0ccf
CIK		 957static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
958 enum hns_roce_opcode_type opcode,
959 bool is_read)
a04ff739
WHX		 960{
961 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
962 desc->opcode = cpu_to_le16(opcode);
963 desc->flag =
964 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
965 if (is_read)
966 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
967 else
968 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
969}
970
971static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
972{
973 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
974 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
975
976 return head == priv->cmq.csq.next_to_use;
977}
978
979static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
980{
981 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
982 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
983 struct hns_roce_cmq_desc *desc;
984 u16 ntc = csq->next_to_clean;
985 u32 head;
986 int clean = 0;
987
988 desc = &csq->desc[ntc];
989 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
990 while (head != ntc) {
991 memset(desc, 0, sizeof(*desc));
992 ntc++;
993 if (ntc == csq->desc_num)
994 ntc = 0;
995 desc = &csq->desc[ntc];
996 clean++;
997 }
998 csq->next_to_clean = ntc;
999
1000 return clean;
1001}
1002
6a04aed6
WHX		 1003static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1004 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 1005{
1006 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1007 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1008 struct hns_roce_cmq_desc *desc_to_use;
1009 bool complete = false;
1010 u32 timeout = 0;
1011 int handle = 0;
1012 u16 desc_ret;
1013 int ret = 0;
1014 int ntc;
1015
1016 spin_lock_bh(&csq->lock);
1017
1018 if (num > hns_roce_cmq_space(csq)) {
1019 spin_unlock_bh(&csq->lock);
1020 return -EBUSY;
1021 }
1022
1023 /*
1024 * Record the location of desc in the cmq for this time
1025 * which will be use for hardware to write back
1026 */
1027 ntc = csq->next_to_use;
1028
1029 while (handle < num) {
1030 desc_to_use = &csq->desc[csq->next_to_use];
1031 *desc_to_use = desc[handle];
1032 dev_dbg(hr_dev->dev, "set cmq desc:\n");
1033 csq->next_to_use++;
1034 if (csq->next_to_use == csq->desc_num)
1035 csq->next_to_use = 0;
1036 handle++;
1037 }
1038
1039 /* Write to hardware */
1040 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
1041
1042 /*
1043 * If the command is sync, wait for the firmware to write back,
1044 * if multi descriptors to be sent, use the first one to check
1045 */
bfe86035 1046 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
a04ff739
WHX		 1047 do {
1048 if (hns_roce_cmq_csq_done(hr_dev))
1049 break;
988e175b 1050 udelay(1);
a04ff739
WHX		 1051 timeout++;
1052 } while (timeout < priv->cmq.tx_timeout);
1053 }
1054
1055 if (hns_roce_cmq_csq_done(hr_dev)) {
1056 complete = true;
1057 handle = 0;
1058 while (handle < num) {
1059 /* get the result of hardware write back */
1060 desc_to_use = &csq->desc[ntc];
1061 desc[handle] = *desc_to_use;
1062 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
bfe86035 1063 desc_ret = le16_to_cpu(desc[handle].retval);
a04ff739
WHX		 1064 if (desc_ret == CMD_EXEC_SUCCESS)
1065 ret = 0;
1066 else
1067 ret = -EIO;
1068 priv->cmq.last_status = desc_ret;
1069 ntc++;
1070 handle++;
1071 if (ntc == csq->desc_num)
1072 ntc = 0;
1073 }
1074 }
1075
1076 if (!complete)
1077 ret = -EAGAIN;
1078
1079 /* clean the command send queue */
1080 handle = hns_roce_cmq_csq_clean(hr_dev);
1081 if (handle != num)
1082 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
1083 handle, num);
1084
1085 spin_unlock_bh(&csq->lock);
1086
1087 return ret;
1088}
1089
e95e52a1 1090static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
6a04aed6
WHX		 1091 struct hns_roce_cmq_desc *desc, int num)
1092{
1093 int retval;
1094 int ret;
1095
1096 ret = hns_roce_v2_rst_process_cmd(hr_dev);
1097 if (ret == CMD_RST_PRC_SUCCESS)
1098 return 0;
1099 if (ret == CMD_RST_PRC_EBUSY)
b417c087 1100 return -EBUSY;
6a04aed6
WHX		 1101
1102 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1103 if (ret) {
1104 retval = hns_roce_v2_rst_process_cmd(hr_dev);
1105 if (retval == CMD_RST_PRC_SUCCESS)
1106 return 0;
1107 else if (retval == CMD_RST_PRC_EBUSY)
b417c087 1108 return -EBUSY;
6a04aed6
WHX		 1109 }
1110
1111 return ret;
1112}
1113
281d0ccf 1114static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 1115{
1116 struct hns_roce_query_version *resp;
1117 struct hns_roce_cmq_desc desc;
1118 int ret;
1119
1120 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1121 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1122 if (ret)
1123 return ret;
1124
1125 resp = (struct hns_roce_query_version *)desc.data;
bfe86035 1126 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 1127 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1128
1129 return 0;
1130}
1131
e075da5e
LC		 1132static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev)
1133{
1134 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1135 struct hnae3_handle *handle = priv->handle;
1136 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1137 unsigned long reset_cnt;
1138 bool sw_resetting;
1139 bool hw_resetting;
1140
1141 reset_cnt = ops->ae_dev_reset_cnt(handle);
1142 hw_resetting = ops->get_hw_reset_stat(handle);
1143 sw_resetting = ops->ae_dev_resetting(handle);
1144
1145 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting)
1146 return true;
1147
1148 return false;
1149}
1150
1151static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval,
1152 int flag)
1153{
1154 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1155 struct hnae3_handle *handle = priv->handle;
1156 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1157 unsigned long instance_stage;
1158 unsigned long reset_cnt;
1159 unsigned long end;
1160 bool sw_resetting;
1161 bool hw_resetting;
1162
1163 instance_stage = handle->rinfo.instance_state;
1164 reset_cnt = ops->ae_dev_reset_cnt(handle);
1165 hw_resetting = ops->get_hw_reset_stat(handle);
1166 sw_resetting = ops->ae_dev_resetting(handle);
1167
1168 if (reset_cnt != hr_dev->reset_cnt) {
1169 hr_dev->dis_db = true;
1170 hr_dev->is_reset = true;
1171 dev_info(hr_dev->dev, "Func clear success after reset.\n");
1172 } else if (hw_resetting) {
1173 hr_dev->dis_db = true;
1174
1175 dev_warn(hr_dev->dev,
1176 "Func clear is pending, device in resetting state.\n");
1177 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1178 while (end) {
1179 if (!ops->get_hw_reset_stat(handle)) {
1180 hr_dev->is_reset = true;
1181 dev_info(hr_dev->dev,
1182 "Func clear success after reset.\n");
1183 return;
1184 }
1185 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1186 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1187 }
1188
1189 dev_warn(hr_dev->dev, "Func clear failed.\n");
1190 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) {
1191 hr_dev->dis_db = true;
1192
1193 dev_warn(hr_dev->dev,
1194 "Func clear is pending, device in resetting state.\n");
1195 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1196 while (end) {
1197 if (ops->ae_dev_reset_cnt(handle) !=
1198 hr_dev->reset_cnt) {
1199 hr_dev->is_reset = true;
1200 dev_info(hr_dev->dev,
1201 "Func clear success after sw reset\n");
1202 return;
1203 }
1204 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1205 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1206 }
1207
1208 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
1209 } else {
1210 if (retval && !flag)
1211 dev_warn(hr_dev->dev,
1212 "Func clear read failed, ret = %d.\n", retval);
1213
1214 dev_warn(hr_dev->dev, "Func clear failed.\n");
1215 }
1216}
89a6da3c
LC		 1217static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1218{
e075da5e 1219 bool fclr_write_fail_flag = false;
89a6da3c
LC		 1220 struct hns_roce_func_clear *resp;
1221 struct hns_roce_cmq_desc desc;
1222 unsigned long end;
e075da5e
LC		 1223 int ret = 0;
1224
1225 if (hns_roce_func_clr_chk_rst(hr_dev))
1226 goto out;
89a6da3c
LC		 1227
1228 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1229 resp = (struct hns_roce_func_clear *)desc.data;
1230
1231 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1232 if (ret) {
e075da5e 1233 fclr_write_fail_flag = true;
89a6da3c
LC		 1234 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n",
1235 ret);
e075da5e 1236 goto out;
89a6da3c
LC		 1237 }
1238
1239 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1240 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1241 while (end) {
e075da5e
LC		 1242 if (hns_roce_func_clr_chk_rst(hr_dev))
1243 goto out;
89a6da3c
LC		 1244 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1245 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1246
1247 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1248 true);
1249
1250 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1251 if (ret)
1252 continue;
1253
1254 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) {
1255 hr_dev->is_reset = true;
1256 return;
1257 }
1258 }
1259
e075da5e 1260out:
e075da5e 1261 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag);
89a6da3c
LC		 1262}
1263
3a63c964
LO		 1264static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1265{
1266 struct hns_roce_query_fw_info *resp;
1267 struct hns_roce_cmq_desc desc;
1268 int ret;
1269
1270 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1271 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1272 if (ret)
1273 return ret;
1274
1275 resp = (struct hns_roce_query_fw_info *)desc.data;
1276 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1277
1278 return 0;
1279}
1280
1281static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1282{
1283 struct hns_roce_cfg_global_param *req;
1284 struct hns_roce_cmq_desc desc;
1285
1286 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1287 false);
1288
1289 req = (struct hns_roce_cfg_global_param *)desc.data;
1290 memset(req, 0, sizeof(*req));
1291 roce_set_field(req->time_cfg_udp_port,
1292 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1293 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1294 roce_set_field(req->time_cfg_udp_port,
1295 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1296 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1297
1298 return hns_roce_cmq_send(hr_dev, &desc, 1);
1299}
1300
1301static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1302{
1303 struct hns_roce_cmq_desc desc[2];
6b63597d 1304 struct hns_roce_pf_res_a *req_a;
1305 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1306 int ret;
1307 int i;
1308
1309 for (i = 0; i < 2; i++) {
1310 hns_roce_cmq_setup_basic_desc(&desc[i],
1311 HNS_ROCE_OPC_QUERY_PF_RES, true);
1312
1313 if (i == 0)
1314 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1315 else
1316 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1317 }
1318
1319 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1320 if (ret)
1321 return ret;
1322
6b63597d 1323 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1324 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1325
6b63597d 1326 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1327 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1328 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1329 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1330 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1331 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1332 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1333 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1334 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1335 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1336 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1337 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1338
6b63597d 1339 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1340 PF_RES_DATA_3_PF_SL_NUM_M,
1341 PF_RES_DATA_3_PF_SL_NUM_S);
6a157f7d
YL		 1342 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,
1343 PF_RES_DATA_4_PF_SCCC_BT_NUM_M,
1344 PF_RES_DATA_4_PF_SCCC_BT_NUM_S);
6b63597d 1345
cfc85f3e
WHX		 1346 return 0;
1347}
1348
0e40dc2f
YL		 1349static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
1350{
1351 struct hns_roce_pf_timer_res_a *req_a;
1352 struct hns_roce_cmq_desc desc[2];
1353 int ret, i;
1354
1355 for (i = 0; i < 2; i++) {
1356 hns_roce_cmq_setup_basic_desc(&desc[i],
1357 HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1358 true);
1359
1360 if (i == 0)
1361 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1362 else
1363 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1364 }
1365
1366 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1367 if (ret)
1368 return ret;
1369
1370 req_a = (struct hns_roce_pf_timer_res_a *)desc[0].data;
1371
1372 hr_dev->caps.qpc_timer_bt_num =
1373 roce_get_field(req_a->qpc_timer_bt_idx_num,
1374 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
1375 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
1376 hr_dev->caps.cqc_timer_bt_num =
1377 roce_get_field(req_a->cqc_timer_bt_idx_num,
1378 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
1379 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
1380
1381 return 0;
1382}
1383
60262b10 1384static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id)
0c1c3880
LO		 1385{
1386 struct hns_roce_cmq_desc desc;
1387 struct hns_roce_vf_switch *swt;
1388 int ret;
1389
1390 swt = (struct hns_roce_vf_switch *)desc.data;
1391 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
bfe86035 1392 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
60262b10
LO		 1393 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1394 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id);
0c1c3880
LO		 1395 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1396 if (ret)
1397 return ret;
60262b10 1398
0c1c3880
LO		 1399 desc.flag =
1400 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1401 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1402 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
d967e262 1403 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0);
0c1c3880
LO		 1404 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1405
1406 return hns_roce_cmq_send(hr_dev, &desc, 1);
1407}
1408
cfc85f3e
WHX		 1409static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1410{
1411 struct hns_roce_cmq_desc desc[2];
1412 struct hns_roce_vf_res_a *req_a;
1413 struct hns_roce_vf_res_b *req_b;
1414 int i;
1415
1416 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1417 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1418 memset(req_a, 0, sizeof(*req_a));
1419 memset(req_b, 0, sizeof(*req_b));
1420 for (i = 0; i < 2; i++) {
1421 hns_roce_cmq_setup_basic_desc(&desc[i],
1422 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1423
1424 if (i == 0)
1425 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1426 else
1427 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
cfc85f3e
WHX		 1428 }
1429
99e713f8
LO		 1430 roce_set_field(req_a->vf_qpc_bt_idx_num,
1431 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1432 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1433 roce_set_field(req_a->vf_qpc_bt_idx_num,
1434 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1435 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM);
1436
1437 roce_set_field(req_a->vf_srqc_bt_idx_num,
1438 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1439 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1440 roce_set_field(req_a->vf_srqc_bt_idx_num,
1441 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1442 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1443 HNS_ROCE_VF_SRQC_BT_NUM);
1444
1445 roce_set_field(req_a->vf_cqc_bt_idx_num,
1446 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1447 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1448 roce_set_field(req_a->vf_cqc_bt_idx_num,
1449 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1450 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM);
1451
1452 roce_set_field(req_a->vf_mpt_bt_idx_num,
1453 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1454 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1455 roce_set_field(req_a->vf_mpt_bt_idx_num,
1456 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1457 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM);
1458
1459 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M,
1460 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1461 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M,
1462 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM);
1463
1464 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1465 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1466 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1467 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM);
1468
1469 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M,
1470 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1471 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M,
1472 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM);
1473
1474 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M,
1475 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1476 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M,
1477 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM);
1478
1479 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,
1480 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);
1481 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,
1482 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,
1483 HNS_ROCE_VF_SCCC_BT_NUM);
1484
cfc85f3e
WHX		 1485 return hns_roce_cmq_send(hr_dev, desc, 2);
1486}
1487
a81fba28
WHX		 1488static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1489{
1490 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1491 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1492 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1493 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
6a157f7d 1494 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;
a81fba28
WHX		 1495 struct hns_roce_cfg_bt_attr *req;
1496 struct hns_roce_cmq_desc desc;
1497
1498 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1499 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1500 memset(req, 0, sizeof(*req));
1501
1502 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1503 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1504 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1505 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1506 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1507 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1508 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1509 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1510 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1511
1512 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1513 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1514 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1515 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1516 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1517 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1518 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1519 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1520 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1521
1522 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1523 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1524 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1525 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1526 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1527 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1528 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1529 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1530 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1531
1532 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1533 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1534 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1535 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1536 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1537 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1538 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1539 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1540 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1541
6a157f7d
YL		 1542 roce_set_field(req->vf_sccc_cfg,
1543 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,
1544 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,
1545 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1546 roce_set_field(req->vf_sccc_cfg,
1547 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,
1548 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,
1549 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1550 roce_set_field(req->vf_sccc_cfg,
1551 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,
1552 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,
1553 sccc_hop_num ==
1554 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);
1555
a81fba28
WHX		 1556 return hns_roce_cmq_send(hr_dev, &desc, 1);
1557}
1558
ba6bb7e9
LO		 1559static void set_default_caps(struct hns_roce_dev *hr_dev)
1560{
1561 struct hns_roce_caps *caps = &hr_dev->caps;
1562
1563 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1564 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1565 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1566 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
1567 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1568 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1569 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1570 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
1571 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1572 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1573 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1574 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
1575 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1576 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1577 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1578 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1579 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1580 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1581 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1582 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1583 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1584 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1585 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1586 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1587 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1588 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1589 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1590 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
7db82697 1591 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
ba6bb7e9
LO		 1592 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1593 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1594 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1595 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1596 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ;
1597 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1598 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1599 caps->reserved_lkey = 0;
1600 caps->reserved_pds = 0;
1601 caps->reserved_mrws = 1;
1602 caps->reserved_uars = 0;
1603 caps->reserved_cqs = 0;
1604 caps->reserved_srqs = 0;
1605 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
1606
1607 caps->qpc_ba_pg_sz = 0;
1608 caps->qpc_buf_pg_sz = 0;
1609 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1610 caps->srqc_ba_pg_sz = 0;
1611 caps->srqc_buf_pg_sz = 0;
1612 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1613 caps->cqc_ba_pg_sz = 0;
1614 caps->cqc_buf_pg_sz = 0;
1615 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1616 caps->mpt_ba_pg_sz = 0;
1617 caps->mpt_buf_pg_sz = 0;
1618 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1619 caps->mtt_ba_pg_sz = 0;
1620 caps->mtt_buf_pg_sz = 0;
1621 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1622 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM;
1623 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM;
1624 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM;
1625 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
1626 caps->cqe_buf_pg_sz = 0;
1627 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
1628 caps->srqwqe_ba_pg_sz = 0;
1629 caps->srqwqe_buf_pg_sz = 0;
1630 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
1631 caps->idx_ba_pg_sz = 0;
1632 caps->idx_buf_pg_sz = 0;
1633 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
1634 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
1635
1636 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
1637 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
1638 HNS_ROCE_CAP_FLAG_RQ_INLINE |
1639 HNS_ROCE_CAP_FLAG_RECORD_DB |
1640 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
1641
1642 caps->pkey_table_len[0] = 1;
1643 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
1644 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1645 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
1646 caps->local_ca_ack_delay = 0;
1647 caps->max_mtu = IB_MTU_4096;
1648
1649 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1650 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1651
dfaf2854 1652 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
ba6bb7e9
LO		 1653 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
1654 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
1655 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
1656
1657 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1658 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1659 caps->qpc_timer_ba_pg_sz = 0;
1660 caps->qpc_timer_buf_pg_sz = 0;
1661 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1662 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1663 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1664 caps->cqc_timer_ba_pg_sz = 0;
1665 caps->cqc_timer_buf_pg_sz = 0;
1666 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1667
1668 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
1669 caps->sccc_ba_pg_sz = 0;
1670 caps->sccc_buf_pg_sz = 0;
1671 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
1672 }
1673}
1674
1675static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
1676 int *buf_page_size, int *bt_page_size, u32 hem_type)
1677{
1678 u64 obj_per_chunk;
1679 int bt_chunk_size = 1 << PAGE_SHIFT;
1680 int buf_chunk_size = 1 << PAGE_SHIFT;
1681 int obj_per_chunk_default = buf_chunk_size / obj_size;
1682
1683 *buf_page_size = 0;
1684 *bt_page_size = 0;
1685
1686 switch (hop_num) {
1687 case 3:
1688 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1689 (bt_chunk_size / BA_BYTE_LEN) *
1690 (bt_chunk_size / BA_BYTE_LEN) *
1691 obj_per_chunk_default;
1692 break;
1693 case 2:
1694 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1695 (bt_chunk_size / BA_BYTE_LEN) *
1696 obj_per_chunk_default;
1697 break;
1698 case 1:
1699 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1700 obj_per_chunk_default;
1701 break;
1702 case HNS_ROCE_HOP_NUM_0:
1703 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1704 break;
1705 default:
1706 pr_err("Table %d not support hop_num = %d!\n", hem_type,
1707 hop_num);
1708 return;
1709 }
1710
1711 if (hem_type >= HEM_TYPE_MTT)
1712 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1713 else
1714 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1715}
1716
1717static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
1718{
1719 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
1720 struct hns_roce_caps *caps = &hr_dev->caps;
1721 struct hns_roce_query_pf_caps_a *resp_a;
1722 struct hns_roce_query_pf_caps_b *resp_b;
1723 struct hns_roce_query_pf_caps_c *resp_c;
1724 struct hns_roce_query_pf_caps_d *resp_d;
1725 struct hns_roce_query_pf_caps_e *resp_e;
1726 int ctx_hop_num;
1727 int pbl_hop_num;
1728 int ret;
1729 int i;
1730
1731 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
1732 hns_roce_cmq_setup_basic_desc(&desc[i],
1733 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
1734 true);
1735 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
1736 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1737 else
1738 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1739 }
1740
1741 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
1742 if (ret)
1743 return ret;
1744
1745 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
1746 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
1747 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
1748 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
1749 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
1750
1751 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
1752 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
1753 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
1754 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
1755 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg);
1756 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer);
1757 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer);
1758 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
1759 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
1760 caps->num_other_vectors = resp_a->num_other_vectors;
1761 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
1762 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
1763 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz;
1764 caps->cq_entry_sz = resp_a->cq_entry_sz;
1765
1766 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
1767 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
1768 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
1769 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
1770 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
1771 caps->idx_entry_sz = resp_b->idx_entry_sz;
1772 caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz;
1773 caps->max_mtu = resp_b->max_mtu;
1774 caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz);
1775 caps->min_cqes = resp_b->min_cqes;
1776 caps->min_wqes = resp_b->min_wqes;
1777 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
1778 caps->pkey_table_len[0] = resp_b->pkey_table_len;
1779 caps->phy_num_uars = resp_b->phy_num_uars;
1780 ctx_hop_num = resp_b->ctx_hop_num;
1781 pbl_hop_num = resp_b->pbl_hop_num;
1782
1783 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds,
1784 V2_QUERY_PF_CAPS_C_NUM_PDS_M,
1785 V2_QUERY_PF_CAPS_C_NUM_PDS_S);
1786 caps->flags = roce_get_field(resp_c->cap_flags_num_pds,
1787 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M,
1788 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S);
1789 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs,
1790 V2_QUERY_PF_CAPS_C_NUM_CQS_M,
1791 V2_QUERY_PF_CAPS_C_NUM_CQS_S);
1792 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs,
1793 V2_QUERY_PF_CAPS_C_MAX_GID_M,
1794 V2_QUERY_PF_CAPS_C_MAX_GID_S);
1795 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth,
1796 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M,
1797 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S);
1798 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws,
1799 V2_QUERY_PF_CAPS_C_NUM_MRWS_M,
1800 V2_QUERY_PF_CAPS_C_NUM_MRWS_S);
1801 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps,
1802 V2_QUERY_PF_CAPS_C_NUM_QPS_M,
1803 V2_QUERY_PF_CAPS_C_NUM_QPS_S);
1804 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps,
1805 V2_QUERY_PF_CAPS_C_MAX_ORD_M,
1806 V2_QUERY_PF_CAPS_C_MAX_ORD_S);
1807 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
1808 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
1809 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs,
1810 V2_QUERY_PF_CAPS_D_NUM_SRQS_M,
1811 V2_QUERY_PF_CAPS_D_NUM_SRQS_S);
1812 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
1813 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth,
1814 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M,
1815 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S);
1816 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth,
1817 V2_QUERY_PF_CAPS_D_NUM_CEQS_M,
1818 V2_QUERY_PF_CAPS_D_NUM_CEQS_S);
1819 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth,
1820 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M,
1821 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S);
1822 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1823 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M,
1824 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S);
1825 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1826 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M,
1827 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S);
1828 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds,
1829 V2_QUERY_PF_CAPS_D_RSV_PDS_M,
1830 V2_QUERY_PF_CAPS_D_RSV_PDS_S);
1831 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds,
1832 V2_QUERY_PF_CAPS_D_NUM_UARS_M,
1833 V2_QUERY_PF_CAPS_D_NUM_UARS_S);
1834 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps,
1835 V2_QUERY_PF_CAPS_D_RSV_QPS_M,
1836 V2_QUERY_PF_CAPS_D_RSV_QPS_S);
1837 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps,
1838 V2_QUERY_PF_CAPS_D_RSV_UARS_M,
1839 V2_QUERY_PF_CAPS_D_RSV_UARS_S);
1840 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1841 V2_QUERY_PF_CAPS_E_RSV_MRWS_M,
1842 V2_QUERY_PF_CAPS_E_RSV_MRWS_S);
1843 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1844 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M,
1845 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S);
1846 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs,
1847 V2_QUERY_PF_CAPS_E_RSV_CQS_M,
1848 V2_QUERY_PF_CAPS_E_RSV_CQS_S);
1849 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs,
1850 V2_QUERY_PF_CAPS_E_RSV_SRQS_M,
1851 V2_QUERY_PF_CAPS_E_RSV_SRQS_S);
1852 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey,
1853 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M,
1854 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S);
1855 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
1856 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
1857 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
1858 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
1859
1860 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1861 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1862 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1863 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1864 caps->mtt_ba_pg_sz = 0;
1865 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1866 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1867 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1868
1869 caps->qpc_hop_num = ctx_hop_num;
1870 caps->srqc_hop_num = ctx_hop_num;
1871 caps->cqc_hop_num = ctx_hop_num;
1872 caps->mpt_hop_num = ctx_hop_num;
1873 caps->mtt_hop_num = pbl_hop_num;
1874 caps->cqe_hop_num = pbl_hop_num;
1875 caps->srqwqe_hop_num = pbl_hop_num;
1876 caps->idx_hop_num = pbl_hop_num;
1877 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1878 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M,
1879 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S);
1880 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1881 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M,
1882 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S);
1883 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1884 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
1885 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
1886
1887 calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
1888 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
1889 HEM_TYPE_QPC);
1890 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
1891 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
1892 HEM_TYPE_MTPT);
1893 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
1894 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
1895 HEM_TYPE_CQC);
1896 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num,
1897 caps->srqc_bt_num, &caps->srqc_buf_pg_sz,
1898 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC);
1899
dfaf2854 1900 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
ba6bb7e9
LO		 1901 caps->sccc_hop_num = ctx_hop_num;
1902 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1903 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1904
1905 calc_pg_sz(caps->num_qps, caps->sccc_entry_sz,
1906 caps->sccc_hop_num, caps->sccc_bt_num,
1907 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,
1908 HEM_TYPE_SCCC);
1909 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
1910 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
1911 &caps->cqc_timer_buf_pg_sz,
1912 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
1913 }
1914
1915 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num,
1916 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
1917 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
1918 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
1919 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
1920 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num,
1921 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
1922
1923 return 0;
1924}
1925
cfc85f3e
WHX		 1926static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1927{
1928 struct hns_roce_caps *caps = &hr_dev->caps;
1929 int ret;
1930
1931 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 1932 if (ret) {
1933 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
1934 ret);
1935 return ret;
1936 }
1937
1938 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 1939 if (ret) {
1940 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1941 ret);
1942 return ret;
1943 }
1944
1945 ret = hns_roce_config_global_param(hr_dev);
1946 if (ret) {
1947 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1948 ret);
2349fdd4 1949 return ret;
cfc85f3e
WHX		 1950 }
1951
1952 /* Get pf resource owned by every pf */
1953 ret = hns_roce_query_pf_resource(hr_dev);
1954 if (ret) {
1955 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1956 ret);
1957 return ret;
1958 }
1959
dfaf2854 1960 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
0e40dc2f
YL		 1961 ret = hns_roce_query_pf_timer_resource(hr_dev);
1962 if (ret) {
1963 dev_err(hr_dev->dev,
1964 "Query pf timer resource fail, ret = %d.\n",
1965 ret);
1966 return ret;
1967 }
cfc85f3e 1968
0c1c3880
LO		 1969 ret = hns_roce_set_vf_switch_param(hr_dev, 0);
1970 if (ret) {
1971 dev_err(hr_dev->dev,
1972 "Set function switch param fail, ret = %d.\n",
1973 ret);
1974 return ret;
1975 }
1976 }
3a63c964
LO		 1977
1978 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
1979 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e 1980
cfc85f3e
WHX		 1981 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1982 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
5c1f167a
LO		 1983 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1984 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
cfc85f3e 1985
80a78570 1986 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
ff795f71
WHX		 1987 caps->pbl_buf_pg_sz = 0;
1988 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
a5073d60
YL		 1989 caps->eqe_ba_pg_sz = 0;
1990 caps->eqe_buf_pg_sz = 0;
1991 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1992 caps->tsq_buf_pg_sz = 0;
aa84fa18 1993
80a78570
LO		 1994 ret = hns_roce_query_pf_caps(hr_dev);
1995 if (ret)
1996 set_default_caps(hr_dev);
384f8818 1997
99e713f8
LO		 1998 ret = hns_roce_alloc_vf_resource(hr_dev);
1999 if (ret) {
2000 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
2001 ret);
2002 return ret;
2003 }
2004
a81fba28
WHX		 2005 ret = hns_roce_v2_set_bt(hr_dev);
2006 if (ret)
2007 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
2008 ret);
2009
2010 return ret;
cfc85f3e
WHX		 2011}
2012
6b63597d 2013static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
2014 enum hns_roce_link_table_type type)
2015{
2016 struct hns_roce_cmq_desc desc[2];
2017 struct hns_roce_cfg_llm_a *req_a =
2018 (struct hns_roce_cfg_llm_a *)desc[0].data;
2019 struct hns_roce_cfg_llm_b *req_b =
2020 (struct hns_roce_cfg_llm_b *)desc[1].data;
2021 struct hns_roce_v2_priv *priv = hr_dev->priv;
2022 struct hns_roce_link_table *link_tbl;
2023 struct hns_roce_link_table_entry *entry;
2024 enum hns_roce_opcode_type opcode;
2025 u32 page_num;
2026 int i;
2027
2028 switch (type) {
2029 case TSQ_LINK_TABLE:
2030 link_tbl = &priv->tsq;
2031 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2032 break;
ded58ff9 2033 case TPQ_LINK_TABLE:
2034 link_tbl = &priv->tpq;
2035 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
2036 break;
6b63597d 2037 default:
2038 return -EINVAL;
2039 }
2040
2041 page_num = link_tbl->npages;
2042 entry = link_tbl->table.buf;
2043 memset(req_a, 0, sizeof(*req_a));
2044 memset(req_b, 0, sizeof(*req_b));
2045
2046 for (i = 0; i < 2; i++) {
2047 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
2048
2049 if (i == 0)
2050 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2051 else
2052 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2053
2054 if (i == 0) {
bfe86035
LC		 2055 req_a->base_addr_l =
2056 cpu_to_le32(link_tbl->table.map & 0xffffffff);
2057 req_a->base_addr_h =
2058 cpu_to_le32(link_tbl->table.map >> 32);
6b63597d 2059 roce_set_field(req_a->depth_pgsz_init_en,
60262b10 2060 CFG_LLM_QUE_DEPTH_M, CFG_LLM_QUE_DEPTH_S,
6b63597d 2061 link_tbl->npages);
2062 roce_set_field(req_a->depth_pgsz_init_en,
60262b10 2063 CFG_LLM_QUE_PGSZ_M, CFG_LLM_QUE_PGSZ_S,
6b63597d 2064 link_tbl->pg_sz);
bfe86035
LC		 2065 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0);
2066 req_a->head_ba_h_nxtptr =
2067 cpu_to_le32(entry[0].blk_ba1_nxt_ptr);
60262b10 2068 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M,
6b63597d 2069 CFG_LLM_HEAD_PTR_S, 0);
2070 } else {
bfe86035
LC		 2071 req_b->tail_ba_l =
2072 cpu_to_le32(entry[page_num - 1].blk_ba0);
60262b10 2073 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M,
6b63597d 2074 CFG_LLM_TAIL_BA_H_S,
2075 entry[page_num - 1].blk_ba1_nxt_ptr &
60262b10
LO		 2076 HNS_ROCE_LINK_TABLE_BA1_M);
2077 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M,
6b63597d 2078 CFG_LLM_TAIL_PTR_S,
2079 (entry[page_num - 2].blk_ba1_nxt_ptr &
60262b10
LO		 2080 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
2081 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
6b63597d 2082 }
2083 }
60262b10
LO		 2084 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M,
2085 CFG_LLM_INIT_EN_S, 1);
6b63597d 2086
2087 return hns_roce_cmq_send(hr_dev, desc, 2);
2088}
2089
2090static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
2091 enum hns_roce_link_table_type type)
2092{
2093 struct hns_roce_v2_priv *priv = hr_dev->priv;
2094 struct hns_roce_link_table *link_tbl;
2095 struct hns_roce_link_table_entry *entry;
2096 struct device *dev = hr_dev->dev;
2097 u32 buf_chk_sz;
2098 dma_addr_t t;
ded58ff9 2099 int func_num = 1;
6b63597d 2100 int pg_num_a;
2101 int pg_num_b;
2102 int pg_num;
2103 int size;
2104 int i;
2105
2106 switch (type) {
2107 case TSQ_LINK_TABLE:
2108 link_tbl = &priv->tsq;
2109 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
2110 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
2111 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
2112 break;
ded58ff9 2113 case TPQ_LINK_TABLE:
2114 link_tbl = &priv->tpq;
2115 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
2116 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
2117 pg_num_b = 2 * 4 * func_num + 2;
2118 break;
6b63597d 2119 default:
2120 return -EINVAL;
2121 }
2122
2123 pg_num = max(pg_num_a, pg_num_b);
2124 size = pg_num * sizeof(struct hns_roce_link_table_entry);
2125
2126 link_tbl->table.buf = dma_alloc_coherent(dev, size,
2127 &link_tbl->table.map,
2128 GFP_KERNEL);
2129 if (!link_tbl->table.buf)
2130 goto out;
2131
2132 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
2133 GFP_KERNEL);
2134 if (!link_tbl->pg_list)
2135 goto err_kcalloc_failed;
2136
2137 entry = link_tbl->table.buf;
2138 for (i = 0; i < pg_num; ++i) {
2139 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
2140 &t, GFP_KERNEL);
2141 if (!link_tbl->pg_list[i].buf)
2142 goto err_alloc_buf_failed;
2143
2144 link_tbl->pg_list[i].map = t;
6b63597d 2145
bfe86035
LC		 2146 entry[i].blk_ba0 = (u32)(t >> 12);
2147 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44);
6b63597d 2148
2149 if (i < (pg_num - 1))
bfe86035
LC		 2150 entry[i].blk_ba1_nxt_ptr |=
2151 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S;
2152
6b63597d 2153 }
2154 link_tbl->npages = pg_num;
2155 link_tbl->pg_sz = buf_chk_sz;
2156
2157 return hns_roce_config_link_table(hr_dev, type);
2158
2159err_alloc_buf_failed:
2160 for (i -= 1; i >= 0; i--)
2161 dma_free_coherent(dev, buf_chk_sz,
2162 link_tbl->pg_list[i].buf,
2163 link_tbl->pg_list[i].map);
2164 kfree(link_tbl->pg_list);
2165
2166err_kcalloc_failed:
2167 dma_free_coherent(dev, size, link_tbl->table.buf,
2168 link_tbl->table.map);
2169
2170out:
2171 return -ENOMEM;
2172}
2173
2174static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
2175 struct hns_roce_link_table *link_tbl)
2176{
2177 struct device *dev = hr_dev->dev;
2178 int size;
2179 int i;
2180
2181 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
2182
2183 for (i = 0; i < link_tbl->npages; ++i)
2184 if (link_tbl->pg_list[i].buf)
2185 dma_free_coherent(dev, link_tbl->pg_sz,
2186 link_tbl->pg_list[i].buf,
2187 link_tbl->pg_list[i].map);
2188 kfree(link_tbl->pg_list);
2189
2190 dma_free_coherent(dev, size, link_tbl->table.buf,
2191 link_tbl->table.map);
2192}
2193
2194static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2195{
ded58ff9 2196 struct hns_roce_v2_priv *priv = hr_dev->priv;
0e40dc2f
YL		 2197 int qpc_count, cqc_count;
2198 int ret, i;
6b63597d 2199
2200 /* TSQ includes SQ doorbell and ack doorbell */
2201 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 2202 if (ret) {
6b63597d 2203 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 2204 return ret;
2205 }
2206
2207 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
2208 if (ret) {
2209 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
2210 goto err_tpq_init_failed;
2211 }
2212
6def7de6 2213 /* Alloc memory for QPC Timer buffer space chunk */
0e40dc2f
YL		 2214 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2215 qpc_count++) {
2216 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2217 qpc_count);
2218 if (ret) {
2219 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2220 goto err_qpc_timer_failed;
2221 }
2222 }
2223
6def7de6 2224 /* Alloc memory for CQC Timer buffer space chunk */
0e40dc2f
YL		 2225 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2226 cqc_count++) {
2227 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2228 cqc_count);
2229 if (ret) {
2230 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2231 goto err_cqc_timer_failed;
2232 }
2233 }
2234
ded58ff9 2235 return 0;
2236
0e40dc2f
YL		 2237err_cqc_timer_failed:
2238 for (i = 0; i < cqc_count; i++)
2239 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2240
2241err_qpc_timer_failed:
2242 for (i = 0; i < qpc_count; i++)
2243 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2244
2245 hns_roce_free_link_table(hr_dev, &priv->tpq);
2246
ded58ff9 2247err_tpq_init_failed:
2248 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 2249
2250 return ret;
2251}
2252
2253static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2254{
2255 struct hns_roce_v2_priv *priv = hr_dev->priv;
2256
dfaf2854 2257 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B)
89a6da3c
LC		 2258 hns_roce_function_clear(hr_dev);
2259
ded58ff9 2260 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 2261 hns_roce_free_link_table(hr_dev, &priv->tsq);
2262}
2263
f747b689
LO		 2264static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
2265{
2266 struct hns_roce_cmq_desc desc;
2267 struct hns_roce_mbox_status *mb_st =
2268 (struct hns_roce_mbox_status *)desc.data;
2269 enum hns_roce_cmd_return_status status;
2270
2271 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
2272
2273 status = hns_roce_cmq_send(hr_dev, &desc, 1);
2274 if (status)
2275 return status;
2276
bfe86035 2277 return le32_to_cpu(mb_st->mb_status_hw_run);
f747b689
LO		 2278}
2279
a680f2f3
WHX		 2280static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
2281{
f747b689 2282 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2283
2284 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
2285}
2286
2287static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
2288{
f747b689 2289 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2290
2291 return status & HNS_ROCE_HW_MB_STATUS_MASK;
2292}
2293
f747b689
LO		 2294static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
2295 u64 out_param, u32 in_modifier, u8 op_modifier,
2296 u16 op, u16 token, int event)
2297{
2298 struct hns_roce_cmq_desc desc;
2299 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2300
2301 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2302
bfe86035
LC		 2303 mb->in_param_l = cpu_to_le32(in_param);
2304 mb->in_param_h = cpu_to_le32(in_param >> 32);
2305 mb->out_param_l = cpu_to_le32(out_param);
2306 mb->out_param_h = cpu_to_le32(out_param >> 32);
f747b689
LO		 2307 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
2308 mb->token_event_en = cpu_to_le32(event << 16 | token);
2309
2310 return hns_roce_cmq_send(hr_dev, &desc, 1);
2311}
2312
a680f2f3
WHX		 2313static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
2314 u64 out_param, u32 in_modifier, u8 op_modifier,
2315 u16 op, u16 token, int event)
2316{
2317 struct device *dev = hr_dev->dev;
a680f2f3 2318 unsigned long end;
f747b689 2319 int ret;
a680f2f3
WHX		 2320
2321 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
2322 while (hns_roce_v2_cmd_pending(hr_dev)) {
2323 if (time_after(jiffies, end)) {
2324 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
2325 (int)end);
2326 return -EAGAIN;
2327 }
2328 cond_resched();
2329 }
2330
f747b689
LO		 2331 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
2332 op_modifier, op, token, event);
2333 if (ret)
2334 dev_err(dev, "Post mailbox fail(%d)\n", ret);
a680f2f3 2335
f747b689 2336 return ret;
a680f2f3
WHX		 2337}
2338
2339static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
2340 unsigned long timeout)
2341{
2342 struct device *dev = hr_dev->dev;
617cf24f 2343 unsigned long end;
a680f2f3
WHX		 2344 u32 status;
2345
2346 end = msecs_to_jiffies(timeout) + jiffies;
2347 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
2348 cond_resched();
2349
2350 if (hns_roce_v2_cmd_pending(hr_dev)) {
2351 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
2352 return -ETIMEDOUT;
2353 }
2354
2355 status = hns_roce_v2_cmd_complete(hr_dev);
2356 if (status != 0x1) {
6a04aed6
WHX		 2357 if (status == CMD_RST_PRC_EBUSY)
2358 return status;
2359
a680f2f3
WHX		 2360 dev_err(dev, "mailbox status 0x%x!\n", status);
2361 return -EBUSY;
2362 }
2363
2364 return 0;
2365}
2366
4db134a3 2367static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
2368 int gid_index, const union ib_gid *gid,
2369 enum hns_roce_sgid_type sgid_type)
2370{
2371 struct hns_roce_cmq_desc desc;
2372 struct hns_roce_cfg_sgid_tb *sgid_tb =
2373 (struct hns_roce_cfg_sgid_tb *)desc.data;
2374 u32 *p;
2375
2376 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2377
60262b10 2378 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M,
4db134a3 2379 CFG_SGID_TB_TABLE_IDX_S, gid_index);
60262b10 2380 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M,
4db134a3 2381 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2382
2383 p = (u32 *)&gid->raw[0];
2384 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
2385
2386 p = (u32 *)&gid->raw[4];
2387 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
2388
2389 p = (u32 *)&gid->raw[8];
2390 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
2391
2392 p = (u32 *)&gid->raw[0xc];
2393 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
2394
2395 return hns_roce_cmq_send(hr_dev, &desc, 1);
2396}
2397
b5ff0f61 2398static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 2399 int gid_index, const union ib_gid *gid,
b5ff0f61 2400 const struct ib_gid_attr *attr)
7afddafa 2401{
b5ff0f61 2402 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 2403 int ret;
7afddafa 2404
b5ff0f61
WHX		 2405 if (!gid || !attr)
2406 return -EINVAL;
2407
2408 if (attr->gid_type == IB_GID_TYPE_ROCE)
2409 sgid_type = GID_TYPE_FLAG_ROCE_V1;
2410
2411 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2412 if (ipv6_addr_v4mapped((void *)gid))
2413 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
2414 else
2415 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
2416 }
2417
4db134a3 2418 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
2419 if (ret)
ae1c6148
LO		 2420 ibdev_err(&hr_dev->ib_dev,
2421 "failed to configure sgid table, ret = %d!\n",
2422 ret);
b5ff0f61 2423
4db134a3 2424 return ret;
7afddafa
WHX		 2425}
2426
a74dc41d
WHX		 2427static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
2428 u8 *addr)
7afddafa 2429{
e8e8b652 2430 struct hns_roce_cmq_desc desc;
2431 struct hns_roce_cfg_smac_tb *smac_tb =
2432 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 2433 u16 reg_smac_h;
2434 u32 reg_smac_l;
e8e8b652 2435
2436 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 2437
2438 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 2439 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 2440
e8e8b652 2441 memset(smac_tb, 0, sizeof(*smac_tb));
2442 roce_set_field(smac_tb->tb_idx_rsv,
2443 CFG_SMAC_TB_IDX_M,
2444 CFG_SMAC_TB_IDX_S, phy_port);
2445 roce_set_field(smac_tb->vf_smac_h_rsv,
2446 CFG_SMAC_TB_VF_SMAC_H_M,
2447 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
bfe86035 2448 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
a74dc41d 2449
e8e8b652 2450 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 2451}
2452
ca088320
YL		 2453static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry,
2454 struct hns_roce_mr *mr)
3958cc56 2455{
3856ec55 2456 struct sg_dma_page_iter sg_iter;
db270c41 2457 u64 page_addr;
3958cc56 2458 u64 *pages;
3856ec55 2459 int i;
3958cc56 2460
ca088320
YL		 2461 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2462 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2463 roce_set_field(mpt_entry->byte_48_mode_ba,
2464 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
2465 upper_32_bits(mr->pbl_ba >> 3));
2466
2467 pages = (u64 *)__get_free_page(GFP_KERNEL);
2468 if (!pages)
2469 return -ENOMEM;
2470
2471 i = 0;
3856ec55
SS		 2472 for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
2473 page_addr = sg_page_iter_dma_address(&sg_iter);
2474 pages[i] = page_addr >> 6;
2475
2476 /* Record the first 2 entry directly to MTPT table */
2477 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
2478 goto found;
2479 i++;
ca088320
YL		 2480 }
2481found:
2482 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
2483 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
2484 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
2485
2486 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
2487 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
2488 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
2489 roce_set_field(mpt_entry->byte_64_buf_pa1,
2490 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2491 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2492 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2493
2494 free_page((unsigned long)pages);
2495
2496 return 0;
2497}
2498
2499static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
2500 unsigned long mtpt_idx)
2501{
2502 struct hns_roce_v2_mpt_entry *mpt_entry;
2503 int ret;
2504
3958cc56
WHX		 2505 mpt_entry = mb_buf;
2506 memset(mpt_entry, 0, sizeof(*mpt_entry));
2507
2508 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2509 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2510 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2511 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
2512 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
2513 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2514 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 2515 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2516 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 2517 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2518 V2_MPT_BYTE_4_PD_S, mr->pd);
3958cc56
WHX		 2519
2520 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
82342e49 2521 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0);
e93df010 2522 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 2523 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
2524 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 2525 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
2526 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 2527 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2528 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
2529 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2530 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
2531 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2532 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
3958cc56
WHX		 2533
2534 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
2535 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 2536 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
2537 1);
3958cc56
WHX		 2538
2539 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
2540 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
2541 mpt_entry->lkey = cpu_to_le32(mr->key);
2542 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
2543 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
2544
2545 if (mr->type == MR_TYPE_DMA)
2546 return 0;
2547
ca088320 2548 ret = set_mtpt_pbl(mpt_entry, mr);
3958cc56 2549
ca088320 2550 return ret;
3958cc56
WHX		 2551}
2552
a2c80b7b
WHX		 2553static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
2554 struct hns_roce_mr *mr, int flags,
2555 u32 pdn, int mr_access_flags, u64 iova,
2556 u64 size, void *mb_buf)
2557{
2558 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
ca088320 2559 int ret = 0;
a2c80b7b 2560
ab22bf05
YL		 2561 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2562 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2563
a2c80b7b
WHX		 2564 if (flags & IB_MR_REREG_PD) {
2565 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2566 V2_MPT_BYTE_4_PD_S, pdn);
2567 mr->pd = pdn;
2568 }
2569
2570 if (flags & IB_MR_REREG_ACCESS) {
2571 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2572 V2_MPT_BYTE_8_BIND_EN_S,
2573 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
2574 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
ca088320
YL		 2575 V2_MPT_BYTE_8_ATOMIC_EN_S,
2576 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
a2c80b7b 2577 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
ca088320 2578 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
a2c80b7b 2579 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
ca088320 2580 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
a2c80b7b 2581 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
ca088320 2582 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
a2c80b7b
WHX		 2583 }
2584
2585 if (flags & IB_MR_REREG_TRANS) {
2586 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
2587 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
2588 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
2589 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
2590
a2c80b7b
WHX		 2591 mr->iova = iova;
2592 mr->size = size;
ca088320
YL		 2593
2594 ret = set_mtpt_pbl(mpt_entry, mr);
a2c80b7b
WHX		 2595 }
2596
ca088320 2597 return ret;
a2c80b7b
WHX		 2598}
2599
68a997c5
YL		 2600static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
2601{
2602 struct hns_roce_v2_mpt_entry *mpt_entry;
2603
2604 mpt_entry = mb_buf;
2605 memset(mpt_entry, 0, sizeof(*mpt_entry));
2606
2607 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2608 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2609 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2610 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
2611 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2612 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2613 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2614 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2615 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2616 V2_MPT_BYTE_4_PD_S, mr->pd);
2617
2618 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
2619 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2620 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2621
2622 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
2623 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2624 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
2625 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2626
2627 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2628
2629 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2630 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
2631 V2_MPT_BYTE_48_PBL_BA_H_S,
2632 upper_32_bits(mr->pbl_ba >> 3));
2633
2634 roce_set_field(mpt_entry->byte_64_buf_pa1,
2635 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2636 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2637 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2638
2639 return 0;
2640}
2641
c7c28191
YL		 2642static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
2643{
2644 struct hns_roce_v2_mpt_entry *mpt_entry;
2645
2646 mpt_entry = mb_buf;
2647 memset(mpt_entry, 0, sizeof(*mpt_entry));
2648
2649 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2650 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2651 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2652 V2_MPT_BYTE_4_PD_S, mw->pdn);
60262b10 2653 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
c7c28191 2654 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
60262b10
LO		 2655 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
2656 mw->pbl_hop_num);
c7c28191
YL		 2657 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2658 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2659 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2660 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2661
2662 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2663 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2664
2665 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2666 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
2667 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2668 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
2669 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2670
2671 roce_set_field(mpt_entry->byte_64_buf_pa1,
2672 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2673 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2674 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2675
2676 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2677
2678 return 0;
2679}
2680
93aa2187
WHX		 2681static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2682{
18a96d25 2683 return hns_roce_buf_offset(&hr_cq->buf, n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
93aa2187
WHX		 2684}
2685
2686static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2687{
2688 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2689
2690 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2691 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
e2b2744a 2692 !!(n & hr_cq->cq_depth)) ? cqe : NULL;
93aa2187
WHX		 2693}
2694
2695static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
2696{
2697 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
2698}
2699
c7bcb134
LO		 2700static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
2701{
6fd610c5 2702 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
c7bcb134
LO		 2703}
2704
2705static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index)
2706{
c7bcb134
LO		 2707 /* always called with interrupts disabled. */
2708 spin_lock(&srq->lock);
2709
97545b10 2710 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
c7bcb134
LO		 2711 srq->tail++;
2712
2713 spin_unlock(&srq->lock);
2714}
2715
93aa2187
WHX		 2716static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2717{
b14c95be 2718 *hr_cq->set_ci_db = cons_index & V2_CQ_DB_PARAMETER_CONS_IDX_M;
93aa2187
WHX		 2719}
2720
926a01dc
WHX		 2721static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2722 struct hns_roce_srq *srq)
2723{
2724 struct hns_roce_v2_cqe *cqe, *dest;
2725 u32 prod_index;
2726 int nfreed = 0;
c7bcb134 2727 int wqe_index;
926a01dc
WHX		 2728 u8 owner_bit;
2729
2730 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2731 ++prod_index) {
d7e5ca88 2732 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
926a01dc
WHX		 2733 break;
2734 }
2735
2736 /*
2737 * Now backwards through the CQ, removing CQ entries
2738 * that match our QP by overwriting them with next entries.
2739 */
2740 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2741 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2742 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2743 V2_CQE_BYTE_16_LCL_QPN_S) &
2744 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
c7bcb134
LO		 2745 if (srq &&
2746 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) {
2747 wqe_index = roce_get_field(cqe->byte_4,
2748 V2_CQE_BYTE_4_WQE_INDX_M,
2749 V2_CQE_BYTE_4_WQE_INDX_S);
2750 hns_roce_free_srq_wqe(srq, wqe_index);
2751 }
926a01dc
WHX		 2752 ++nfreed;
2753 } else if (nfreed) {
2754 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2755 hr_cq->ib_cq.cqe);
2756 owner_bit = roce_get_bit(dest->byte_4,
2757 V2_CQE_BYTE_4_OWNER_S);
2758 memcpy(dest, cqe, sizeof(*cqe));
2759 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2760 owner_bit);
2761 }
2762 }
2763
2764 if (nfreed) {
2765 hr_cq->cons_index += nfreed;
2766 /*
2767 * Make sure update of buffer contents is done before
2768 * updating consumer index.
2769 */
2770 wmb();
2771 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2772 }
2773}
2774
2775static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2776 struct hns_roce_srq *srq)
2777{
2778 spin_lock_irq(&hr_cq->lock);
2779 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2780 spin_unlock_irq(&hr_cq->lock);
2781}
2782
93aa2187
WHX		 2783static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2784 struct hns_roce_cq *hr_cq, void *mb_buf,
e2b2744a 2785 u64 *mtts, dma_addr_t dma_handle)
93aa2187
WHX		 2786{
2787 struct hns_roce_v2_cq_context *cq_context;
2788
2789 cq_context = mb_buf;
2790 memset(cq_context, 0, sizeof(*cq_context));
2791
2792 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2793 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2794 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2795 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187 2796 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
60262b10 2797 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth));
93aa2187 2798 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
e2b2744a 2799 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector);
93aa2187
WHX		 2800
2801 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2802 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2803
bfe86035 2804 cq_context->cqe_cur_blk_addr = cpu_to_le32(mtts[0] >> PAGE_ADDR_SHIFT);
93aa2187
WHX		 2805
2806 roce_set_field(cq_context->byte_16_hop_addr,
2807 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2808 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
bfe86035 2809 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
93aa2187
WHX		 2810 roce_set_field(cq_context->byte_16_hop_addr,
2811 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2812 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2813 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2814
bfe86035 2815 cq_context->cqe_nxt_blk_addr = cpu_to_le32(mtts[1] >> PAGE_ADDR_SHIFT);
93aa2187
WHX		 2816 roce_set_field(cq_context->byte_24_pgsz_addr,
2817 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2818 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
bfe86035 2819 mtts[1] >> (32 + PAGE_ADDR_SHIFT));
93aa2187
WHX		 2820 roce_set_field(cq_context->byte_24_pgsz_addr,
2821 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2822 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 2823 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2824 roce_set_field(cq_context->byte_24_pgsz_addr,
2825 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2826 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 2827 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187 2828
bfe86035 2829 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3);
93aa2187
WHX		 2830
2831 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2832 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2833
9b44703d
YL		 2834 if (hr_cq->db_en)
2835 roce_set_bit(cq_context->byte_44_db_record,
2836 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
2837
2838 roce_set_field(cq_context->byte_44_db_record,
2839 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2840 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2841 ((u32)hr_cq->db.dma) >> 1);
bfe86035 2842 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32);
9b44703d 2843
a5073d60
YL		 2844 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2845 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2846 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2847 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2848 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2849 V2_CQC_BYTE_56_CQ_PERIOD_M,
2850 V2_CQC_BYTE_56_CQ_PERIOD_S,
2851 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2852}
2853
2854static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2855 enum ib_cq_notify_flags flags)
2856{
d3743fa9 2857 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 2858 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2859 u32 notification_flag;
bfe86035 2860 __le32 doorbell[2];
93aa2187
WHX		 2861
2862 doorbell[0] = 0;
2863 doorbell[1] = 0;
2864
2865 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2866 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2867 /*
2868 * flags = 0; Notification Flag = 1, next
2869 * flags = 1; Notification Flag = 0, solocited
2870 */
2871 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2872 hr_cq->cqn);
2873 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2874 HNS_ROCE_V2_CQ_DB_NTR);
2875 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2876 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2877 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2878 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2879 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2880 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2881 notification_flag);
2882
d3743fa9 2883 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l);
93aa2187
WHX		 2884
2885 return 0;
2886}
2887
0009c2db 2888static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2889 struct hns_roce_qp **cur_qp,
2890 struct ib_wc *wc)
2891{
2892 struct hns_roce_rinl_sge *sge_list;
2893 u32 wr_num, wr_cnt, sge_num;
2894 u32 sge_cnt, data_len, size;
2895 void *wqe_buf;
2896
2897 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2898 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2899 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2900
2901 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2902 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
6c6e3921 2903 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt);
0009c2db 2904 data_len = wc->byte_len;
2905
2906 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2907 size = min(sge_list[sge_cnt].len, data_len);
2908 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2909
2910 data_len -= size;
2911 wqe_buf += size;
2912 }
2913
2914 if (data_len) {
2915 wc->status = IB_WC_LOC_LEN_ERR;
2916 return -EAGAIN;
2917 }
2918
2919 return 0;
2920}
2921
626903e9
XW		 2922static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
2923 int num_entries, struct ib_wc *wc)
2924{
2925 unsigned int left;
2926 int npolled = 0;
2927
2928 left = wq->head - wq->tail;
2929 if (left == 0)
2930 return 0;
2931
2932 left = min_t(unsigned int, (unsigned int)num_entries, left);
2933 while (npolled < left) {
2934 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2935 wc->status = IB_WC_WR_FLUSH_ERR;
2936 wc->vendor_err = 0;
2937 wc->qp = &hr_qp->ibqp;
2938
2939 wq->tail++;
2940 wc++;
2941 npolled++;
2942 }
2943
2944 return npolled;
2945}
2946
2947static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
2948 struct ib_wc *wc)
2949{
2950 struct hns_roce_qp *hr_qp;
2951 int npolled = 0;
2952
2953 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
2954 npolled += sw_comp(hr_qp, &hr_qp->sq,
2955 num_entries - npolled, wc + npolled);
2956 if (npolled >= num_entries)
2957 goto out;
2958 }
2959
2960 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
2961 npolled += sw_comp(hr_qp, &hr_qp->rq,
2962 num_entries - npolled, wc + npolled);
2963 if (npolled >= num_entries)
2964 goto out;
2965 }
2966
2967out:
2968 return npolled;
2969}
2970
93aa2187
WHX		 2971static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2972 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2973{
b5374286 2974 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
c7bcb134 2975 struct hns_roce_srq *srq = NULL;
93aa2187
WHX		 2976 struct hns_roce_v2_cqe *cqe;
2977 struct hns_roce_qp *hr_qp;
2978 struct hns_roce_wq *wq;
2979 int is_send;
2980 u16 wqe_ctr;
2981 u32 opcode;
2982 u32 status;
2983 int qpn;
0009c2db 2984 int ret;
93aa2187
WHX		 2985
2986 /* Find cqe according to consumer index */
2987 cqe = next_cqe_sw_v2(hr_cq);
2988 if (!cqe)
2989 return -EAGAIN;
2990
2991 ++hr_cq->cons_index;
2992 /* Memory barrier */
2993 rmb();
2994
2995 /* 0->SQ, 1->RQ */
2996 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2997
2998 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2999 V2_CQE_BYTE_16_LCL_QPN_S);
3000
3001 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
93aa2187
WHX		 3002 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3003 if (unlikely(!hr_qp)) {
ae1c6148
LO		 3004 ibdev_err(&hr_dev->ib_dev,
3005 "CQ %06lx with entry for unknown QPN %06x\n",
3006 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK);
93aa2187
WHX		 3007 return -EINVAL;
3008 }
3009 *cur_qp = hr_qp;
3010 }
3011
b5374286 3012 hr_qp = *cur_qp;
93aa2187
WHX		 3013 wc->qp = &(*cur_qp)->ibqp;
3014 wc->vendor_err = 0;
3015
c7bcb134
LO		 3016 if (is_send) {
3017 wq = &(*cur_qp)->sq;
3018 if ((*cur_qp)->sq_signal_bits) {
3019 /*
3020 * If sg_signal_bit is 1,
3021 * firstly tail pointer updated to wqe
3022 * which current cqe correspond to
3023 */
3024 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3025 V2_CQE_BYTE_4_WQE_INDX_M,
3026 V2_CQE_BYTE_4_WQE_INDX_S);
3027 wq->tail += (wqe_ctr - (u16)wq->tail) &
3028 (wq->wqe_cnt - 1);
3029 }
3030
3031 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3032 ++wq->tail;
3033 } else if ((*cur_qp)->ibqp.srq) {
3034 srq = to_hr_srq((*cur_qp)->ibqp.srq);
bfe86035
LC		 3035 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3036 V2_CQE_BYTE_4_WQE_INDX_M,
3037 V2_CQE_BYTE_4_WQE_INDX_S);
c7bcb134
LO		 3038 wc->wr_id = srq->wrid[wqe_ctr];
3039 hns_roce_free_srq_wqe(srq, wqe_ctr);
3040 } else {
3041 /* Update tail pointer, record wr_id */
3042 wq = &(*cur_qp)->rq;
3043 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3044 ++wq->tail;
3045 }
3046
93aa2187
WHX		 3047 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
3048 V2_CQE_BYTE_4_STATUS_S);
3049 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
3050 case HNS_ROCE_CQE_V2_SUCCESS:
3051 wc->status = IB_WC_SUCCESS;
3052 break;
3053 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
3054 wc->status = IB_WC_LOC_LEN_ERR;
3055 break;
3056 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
3057 wc->status = IB_WC_LOC_QP_OP_ERR;
3058 break;
3059 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
3060 wc->status = IB_WC_LOC_PROT_ERR;
3061 break;
3062 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
3063 wc->status = IB_WC_WR_FLUSH_ERR;
3064 break;
3065 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
3066 wc->status = IB_WC_MW_BIND_ERR;
3067 break;
3068 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
3069 wc->status = IB_WC_BAD_RESP_ERR;
3070 break;
3071 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
3072 wc->status = IB_WC_LOC_ACCESS_ERR;
3073 break;
3074 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
3075 wc->status = IB_WC_REM_INV_REQ_ERR;
3076 break;
3077 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
3078 wc->status = IB_WC_REM_ACCESS_ERR;
3079 break;
3080 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
3081 wc->status = IB_WC_REM_OP_ERR;
3082 break;
3083 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
3084 wc->status = IB_WC_RETRY_EXC_ERR;
3085 break;
3086 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
3087 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
3088 break;
3089 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
3090 wc->status = IB_WC_REM_ABORT_ERR;
3091 break;
3092 default:
3093 wc->status = IB_WC_GENERAL_ERR;
3094 break;
3095 }
3096
b5374286
YL		 3097 /*
3098 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets
3099 * into errored mode. Hence, as a workaround to this hardware
3100 * limitation, driver needs to assist in flushing. But the flushing
3101 * operation uses mailbox to convey the QP state to the hardware and
3102 * which can sleep due to the mutex protection around the mailbox calls.
3103 * Hence, use the deferred flush for now. Once wc error detected, the
3104 * flushing operation is needed.
3105 */
3106 if (wc->status != IB_WC_SUCCESS &&
3107 wc->status != IB_WC_WR_FLUSH_ERR) {
ae1c6148
LO		 3108 ibdev_err(&hr_dev->ib_dev, "error cqe status is: 0x%x\n",
3109 status & HNS_ROCE_V2_CQE_STATUS_MASK);
b5374286
YL		 3110
3111 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &hr_qp->flush_flag))
3112 init_flush_work(hr_dev, hr_qp);
3113
3114 return 0;
0425e3e6
YL		 3115 }
3116
3117 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 3118 return 0;
3119
3120 if (is_send) {
3121 wc->wc_flags = 0;
3122 /* SQ corresponding to CQE */
3123 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3124 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
3125 case HNS_ROCE_SQ_OPCODE_SEND:
3126 wc->opcode = IB_WC_SEND;
3127 break;
3128 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
3129 wc->opcode = IB_WC_SEND;
3130 break;
3131 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
3132 wc->opcode = IB_WC_SEND;
3133 wc->wc_flags |= IB_WC_WITH_IMM;
3134 break;
3135 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
3136 wc->opcode = IB_WC_RDMA_READ;
3137 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3138 break;
3139 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
3140 wc->opcode = IB_WC_RDMA_WRITE;
3141 break;
3142 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
3143 wc->opcode = IB_WC_RDMA_WRITE;
3144 wc->wc_flags |= IB_WC_WITH_IMM;
3145 break;
3146 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
3147 wc->opcode = IB_WC_LOCAL_INV;
3148 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3149 break;
3150 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
3151 wc->opcode = IB_WC_COMP_SWAP;
3152 wc->byte_len = 8;
3153 break;
3154 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
3155 wc->opcode = IB_WC_FETCH_ADD;
3156 wc->byte_len = 8;
3157 break;
3158 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
3159 wc->opcode = IB_WC_MASKED_COMP_SWAP;
3160 wc->byte_len = 8;
3161 break;
3162 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
3163 wc->opcode = IB_WC_MASKED_FETCH_ADD;
3164 wc->byte_len = 8;
3165 break;
3166 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
3167 wc->opcode = IB_WC_REG_MR;
3168 break;
3169 case HNS_ROCE_SQ_OPCODE_BIND_MW:
3170 wc->opcode = IB_WC_REG_MR;
3171 break;
3172 default:
3173 wc->status = IB_WC_GENERAL_ERR;
3174 break;
3175 }
93aa2187
WHX		 3176 } else {
3177 /* RQ correspond to CQE */
3178 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3179
3180 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3181 V2_CQE_BYTE_4_OPCODE_S);
3182 switch (opcode & 0x1f) {
3183 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3184 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3185 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3186 wc->ex.imm_data =
3187 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3188 break;
3189 case HNS_ROCE_V2_OPCODE_SEND:
3190 wc->opcode = IB_WC_RECV;
3191 wc->wc_flags = 0;
3192 break;
3193 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3194 wc->opcode = IB_WC_RECV;
3195 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3196 wc->ex.imm_data =
3197 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3198 break;
3199 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3200 wc->opcode = IB_WC_RECV;
3201 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 3202 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 3203 break;
3204 default:
3205 wc->status = IB_WC_GENERAL_ERR;
3206 break;
3207 }
3208
0009c2db 3209 if ((wc->qp->qp_type == IB_QPT_RC ||
3210 wc->qp->qp_type == IB_QPT_UC) &&
3211 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
3212 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3213 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3214 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
3215 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
3216 if (ret)
3217 return -EAGAIN;
3218 }
3219
93aa2187
WHX		 3220 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
3221 V2_CQE_BYTE_32_SL_S);
3222 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
3223 V2_CQE_BYTE_32_RMT_QPN_M,
3224 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 3225 wc->slid = 0;
93aa2187
WHX		 3226 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
3227 V2_CQE_BYTE_32_GRH_S) ?
3228 IB_WC_GRH : 0);
6c1f08b3 3229 wc->port_num = roce_get_field(cqe->byte_32,
3230 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
3231 wc->pkey_index = 0;
cd4a70bb 3232
944e6409
LO		 3233 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
3234 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
3235 V2_CQE_BYTE_28_VID_M,
3236 V2_CQE_BYTE_28_VID_S);
0e1aa6f0 3237 wc->wc_flags |= IB_WC_WITH_VLAN;
944e6409
LO		 3238 } else {
3239 wc->vlan_id = 0xffff;
3240 }
3241
2eade675 3242 wc->network_hdr_type = roce_get_field(cqe->byte_28,
3243 V2_CQE_BYTE_28_PORT_TYPE_M,
3244 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 3245 }
3246
3247 return 0;
3248}
3249
3250static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3251 struct ib_wc *wc)
3252{
626903e9 3253 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 3254 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3255 struct hns_roce_qp *cur_qp = NULL;
3256 unsigned long flags;
3257 int npolled;
3258
3259 spin_lock_irqsave(&hr_cq->lock, flags);
3260
626903e9
XW		 3261 /*
3262 * When the device starts to reset, the state is RST_DOWN. At this time,
3263 * there may still be some valid CQEs in the hardware that are not
3264 * polled. Therefore, it is not allowed to switch to the software mode
3265 * immediately. When the state changes to UNINIT, CQE no longer exists
3266 * in the hardware, and then switch to software mode.
3267 */
3268 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3269 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3270 goto out;
3271 }
3272
93aa2187
WHX		 3273 for (npolled = 0; npolled < num_entries; ++npolled) {
3274 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3275 break;
3276 }
3277
3278 if (npolled) {
3279 /* Memory barrier */
3280 wmb();
3281 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
3282 }
3283
626903e9 3284out:
93aa2187
WHX		 3285 spin_unlock_irqrestore(&hr_cq->lock, flags);
3286
3287 return npolled;
3288}
3289
260c3b34
YL		 3290static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3291 int step_idx)
3292{
3293 int op;
3294
3295 if (type == HEM_TYPE_SCCC && step_idx)
3296 return -EINVAL;
3297
3298 switch (type) {
3299 case HEM_TYPE_QPC:
3300 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
3301 break;
3302 case HEM_TYPE_MTPT:
3303 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
3304 break;
3305 case HEM_TYPE_CQC:
3306 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
3307 break;
3308 case HEM_TYPE_SRQC:
3309 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3310 break;
3311 case HEM_TYPE_SCCC:
3312 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3313 break;
3314 case HEM_TYPE_QPC_TIMER:
3315 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3316 break;
3317 case HEM_TYPE_CQC_TIMER:
3318 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3319 break;
3320 default:
3321 dev_warn(hr_dev->dev,
3322 "Table %d not to be written by mailbox!\n", type);
3323 return -EINVAL;
3324 }
3325
3326 return op + step_idx;
3327}
3328
a81fba28
WHX		 3329static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
3330 struct hns_roce_hem_table *table, int obj,
3331 int step_idx)
3332{
a81fba28
WHX		 3333 struct hns_roce_cmd_mailbox *mailbox;
3334 struct hns_roce_hem_iter iter;
3335 struct hns_roce_hem_mhop mhop;
3336 struct hns_roce_hem *hem;
3337 unsigned long mhop_obj = obj;
3338 int i, j, k;
3339 int ret = 0;
3340 u64 hem_idx = 0;
3341 u64 l1_idx = 0;
3342 u64 bt_ba = 0;
3343 u32 chunk_ba_num;
3344 u32 hop_num;
260c3b34 3345 int op;
a81fba28
WHX		 3346
3347 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3348 return 0;
3349
3350 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
3351 i = mhop.l0_idx;
3352 j = mhop.l1_idx;
3353 k = mhop.l2_idx;
3354 hop_num = mhop.hop_num;
3355 chunk_ba_num = mhop.bt_chunk_size / 8;
3356
3357 if (hop_num == 2) {
3358 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
3359 k;
3360 l1_idx = i * chunk_ba_num + j;
3361 } else if (hop_num == 1) {
3362 hem_idx = i * chunk_ba_num + j;
3363 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
3364 hem_idx = i;
3365 }
3366
260c3b34
YL		 3367 op = get_op_for_set_hem(hr_dev, table->type, step_idx);
3368 if (op == -EINVAL)
a81fba28 3369 return 0;
a81fba28
WHX		 3370
3371 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3372 if (IS_ERR(mailbox))
3373 return PTR_ERR(mailbox);
3374
6ac16e40
YL		 3375 if (table->type == HEM_TYPE_SCCC)
3376 obj = mhop.l0_idx;
3377
a81fba28
WHX		 3378 if (check_whether_last_step(hop_num, step_idx)) {
3379 hem = table->hem[hem_idx];
3380 for (hns_roce_hem_first(hem, &iter);
3381 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
3382 bt_ba = hns_roce_hem_addr(&iter);
3383
3384 /* configure the ba, tag, and op */
3385 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
3386 obj, 0, op,
3387 HNS_ROCE_CMD_TIMEOUT_MSECS);
3388 }
3389 } else {
3390 if (step_idx == 0)
3391 bt_ba = table->bt_l0_dma_addr[i];
3392 else if (step_idx == 1 && hop_num == 2)
3393 bt_ba = table->bt_l1_dma_addr[l1_idx];
3394
3395 /* configure the ba, tag, and op */
3396 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
3397 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
3398 }
3399
3400 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3401 return ret;
3402}
3403
3404static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
3405 struct hns_roce_hem_table *table, int obj,
3406 int step_idx)
3407{
3408 struct device *dev = hr_dev->dev;
3409 struct hns_roce_cmd_mailbox *mailbox;
617cf24f 3410 int ret;
a81fba28
WHX		 3411 u16 op = 0xff;
3412
3413 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3414 return 0;
3415
3416 switch (table->type) {
3417 case HEM_TYPE_QPC:
3418 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
3419 break;
3420 case HEM_TYPE_MTPT:
3421 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
3422 break;
3423 case HEM_TYPE_CQC:
3424 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
3425 break;
6a157f7d 3426 case HEM_TYPE_SCCC:
0e40dc2f
YL		 3427 case HEM_TYPE_QPC_TIMER:
3428 case HEM_TYPE_CQC_TIMER:
6a157f7d 3429 break;
a81fba28
WHX		 3430 case HEM_TYPE_SRQC:
3431 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
3432 break;
3433 default:
3434 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
3435 table->type);
3436 return 0;
3437 }
6a157f7d 3438
0e40dc2f
YL		 3439 if (table->type == HEM_TYPE_SCCC ||
3440 table->type == HEM_TYPE_QPC_TIMER ||
3441 table->type == HEM_TYPE_CQC_TIMER)
6a157f7d
YL		 3442 return 0;
3443
a81fba28
WHX		 3444 op += step_idx;
3445
3446 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3447 if (IS_ERR(mailbox))
3448 return PTR_ERR(mailbox);
3449
3450 /* configure the tag and op */
3451 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3452 HNS_ROCE_CMD_TIMEOUT_MSECS);
3453
3454 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3455 return ret;
3456}
3457
926a01dc 3458static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
926a01dc
WHX		 3459 struct hns_roce_v2_qp_context *context,
3460 struct hns_roce_qp *hr_qp)
3461{
3462 struct hns_roce_cmd_mailbox *mailbox;
3463 int ret;
3464
3465 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3466 if (IS_ERR(mailbox))
3467 return PTR_ERR(mailbox);
3468
3469 memcpy(mailbox->buf, context, sizeof(*context) * 2);
3470
3471 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
3472 HNS_ROCE_CMD_MODIFY_QPC,
3473 HNS_ROCE_CMD_TIMEOUT_MSECS);
3474
3475 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3476
3477 return ret;
3478}
3479
ace1c541 3480static void set_access_flags(struct hns_roce_qp *hr_qp,
3481 struct hns_roce_v2_qp_context *context,
3482 struct hns_roce_v2_qp_context *qpc_mask,
3483 const struct ib_qp_attr *attr, int attr_mask)
3484{
3485 u8 dest_rd_atomic;
3486 u32 access_flags;
3487
c2799119 3488 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 3489 attr->max_dest_rd_atomic : hr_qp->resp_depth;
3490
c2799119 3491 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 3492 attr->qp_access_flags : hr_qp->atomic_rd_en;
3493
3494 if (!dest_rd_atomic)
3495 access_flags &= IB_ACCESS_REMOTE_WRITE;
3496
3497 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3498 !!(access_flags & IB_ACCESS_REMOTE_READ));
3499 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
3500
3501 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3502 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3503 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
3504
3505 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3506 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3507 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
7db82697
JZ		 3508 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S,
3509 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3510 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0);
ace1c541 3511}
3512
99441ab5
XW		 3513static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
3514 struct hns_roce_v2_qp_context *context,
3515 struct hns_roce_v2_qp_context *qpc_mask)
3516{
3517 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
3518 roce_set_field(context->byte_4_sqpn_tst,
3519 V2_QPC_BYTE_4_SGE_SHIFT_M,
3520 V2_QPC_BYTE_4_SGE_SHIFT_S,
3521 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3522 else
3523 roce_set_field(context->byte_4_sqpn_tst,
3524 V2_QPC_BYTE_4_SGE_SHIFT_M,
3525 V2_QPC_BYTE_4_SGE_SHIFT_S,
3526 hr_qp->sq.max_gs >
3527 HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE ?
3528 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3529
99441ab5
XW		 3530 roce_set_field(context->byte_20_smac_sgid_idx,
3531 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3532 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
99441ab5
XW		 3533
3534 roce_set_field(context->byte_20_smac_sgid_idx,
3535 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
3536 (hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3537 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT ||
3538 hr_qp->ibqp.srq) ? 0 :
3539 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
99441ab5
XW		 3540}
3541
926a01dc
WHX		 3542static void modify_qp_reset_to_init(struct ib_qp *ibqp,
3543 const struct ib_qp_attr *attr,
0fa95a9a 3544 int attr_mask,
926a01dc
WHX		 3545 struct hns_roce_v2_qp_context *context,
3546 struct hns_roce_v2_qp_context *qpc_mask)
3547{
ecaaf1e2 3548 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 3549 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3550
3551 /*
3552 * In v2 engine, software pass context and context mask to hardware
3553 * when modifying qp. If software need modify some fields in context,
3554 * we should set all bits of the relevant fields in context mask to
3555 * 0 at the same time, else set them to 0x1.
3556 */
3557 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3558 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
926a01dc 3559
926a01dc
WHX		 3560 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3561 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
926a01dc
WHX		 3562
3563 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3564 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
926a01dc
WHX		 3565
3566 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3567 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
926a01dc 3568
99441ab5 3569 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
926a01dc
WHX		 3570
3571 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 3572 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3573 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
926a01dc 3574
f4c5d869 3575 if (hr_qp->rdb_en)
e088a685
YL		 3576 roce_set_bit(context->byte_68_rq_db,
3577 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
e088a685
YL		 3578
3579 roce_set_field(context->byte_68_rq_db,
3580 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3581 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
3582 ((u32)hr_qp->rdb.dma) >> 1);
bfe86035 3583 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32);
e088a685 3584
ecaaf1e2 3585 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
3586 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 3587
3588 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3589 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
926a01dc
WHX		 3590 if (ibqp->srq) {
3591 roce_set_field(context->byte_76_srqn_op_en,
3592 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3593 to_hr_srq(ibqp->srq)->srqn);
926a01dc
WHX		 3594 roce_set_bit(context->byte_76_srqn_op_en,
3595 V2_QPC_BYTE_76_SRQ_EN_S, 1);
f4c5d869 3596 }
926a01dc
WHX		 3597
3598 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3599 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
926a01dc 3600
68a997c5 3601 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
926a01dc
WHX		 3602
3603 hr_qp->access_flags = attr->qp_access_flags;
926a01dc
WHX		 3604 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3605 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3606}
3607
3608static void modify_qp_init_to_init(struct ib_qp *ibqp,
3609 const struct ib_qp_attr *attr, int attr_mask,
3610 struct hns_roce_v2_qp_context *context,
3611 struct hns_roce_v2_qp_context *qpc_mask)
3612{
3613 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3614
3615 /*
3616 * In v2 engine, software pass context and context mask to hardware
3617 * when modifying qp. If software need modify some fields in context,
3618 * we should set all bits of the relevant fields in context mask to
3619 * 0 at the same time, else set them to 0x1.
3620 */
3621 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3622 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3623 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3624 V2_QPC_BYTE_4_TST_S, 0);
3625
926a01dc
WHX		 3626 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3627 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3628 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3629 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3630 0);
3631
3632 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3633 !!(attr->qp_access_flags &
3634 IB_ACCESS_REMOTE_WRITE));
3635 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3636 0);
3637
3638 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3639 !!(attr->qp_access_flags &
3640 IB_ACCESS_REMOTE_ATOMIC));
3641 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3642 0);
7db82697
JZ		 3643 roce_set_bit(context->byte_76_srqn_op_en,
3644 V2_QPC_BYTE_76_EXT_ATE_S,
3645 !!(attr->qp_access_flags &
3646 IB_ACCESS_REMOTE_ATOMIC));
3647 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3648 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3649 } else {
3650 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3651 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3652 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3653 0);
3654
3655 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3656 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3657 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3658 0);
3659
3660 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3661 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3662 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3663 0);
7db82697
JZ		 3664 roce_set_bit(context->byte_76_srqn_op_en,
3665 V2_QPC_BYTE_76_EXT_ATE_S,
3666 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3667 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3668 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3669 }
3670
926a01dc
WHX		 3671 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3672 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3673 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3674 V2_QPC_BYTE_16_PD_S, 0);
3675
3676 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3677 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3678 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3679 V2_QPC_BYTE_80_RX_CQN_S, 0);
3680
3681 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3682 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3683 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3684 V2_QPC_BYTE_252_TX_CQN_S, 0);
3685
3686 if (ibqp->srq) {
3687 roce_set_bit(context->byte_76_srqn_op_en,
3688 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3689 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3690 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3691 roce_set_field(context->byte_76_srqn_op_en,
3692 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3693 to_hr_srq(ibqp->srq)->srqn);
3694 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3695 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3696 }
3697
926a01dc
WHX		 3698 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3699 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3700 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3701 V2_QPC_BYTE_4_SQPN_S, 0);
3702
b6dd9b34 3703 if (attr_mask & IB_QP_DEST_QPN) {
3704 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3705 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3706 roce_set_field(qpc_mask->byte_56_dqpn_err,
3707 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3708 }
926a01dc
WHX		 3709}
3710
8d18ad83
LO		 3711static bool check_wqe_rq_mtt_count(struct hns_roce_dev *hr_dev,
3712 struct hns_roce_qp *hr_qp, int mtt_cnt,
3713 u32 page_size)
3714{
ae1c6148 3715 struct ib_device *ibdev = &hr_dev->ib_dev;
8d18ad83
LO		 3716
3717 if (hr_qp->rq.wqe_cnt < 1)
3718 return true;
3719
3720 if (mtt_cnt < 1) {
ae1c6148
LO		 3721 ibdev_err(ibdev, "failed to find RQWQE buf ba of QP(0x%lx)\n",
3722 hr_qp->qpn);
8d18ad83
LO		 3723 return false;
3724 }
3725
3726 if (mtt_cnt < MTT_MIN_COUNT &&
3727 (hr_qp->rq.offset + page_size) < hr_qp->buff_size) {
ae1c6148
LO		 3728 ibdev_err(ibdev,
3729 "failed to find next RQWQE buf ba of QP(0x%lx)\n",
3730 hr_qp->qpn);
8d18ad83
LO		 3731 return false;
3732 }
3733
3734 return true;
3735}
3736
926a01dc
WHX		 3737static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3738 const struct ib_qp_attr *attr, int attr_mask,
3739 struct hns_roce_v2_qp_context *context,
3740 struct hns_roce_v2_qp_context *qpc_mask)
3741{
3742 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3743 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3744 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 3745 struct ib_device *ibdev = &hr_dev->ib_dev;
8d18ad83 3746 u64 mtts[MTT_MIN_COUNT] = { 0 };
e92f2c18 3747 dma_addr_t dma_handle_3;
926a01dc 3748 dma_addr_t dma_handle_2;
8d18ad83 3749 u64 wqe_sge_ba;
926a01dc
WHX		 3750 u32 page_size;
3751 u8 port_num;
e92f2c18 3752 u64 *mtts_3;
926a01dc 3753 u64 *mtts_2;
8d18ad83 3754 int count;
926a01dc
WHX		 3755 u8 *dmac;
3756 u8 *smac;
3757 int port;
3758
3759 /* Search qp buf's mtts */
d563099e 3760 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift;
8d18ad83
LO		 3761 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
3762 hr_qp->rq.offset / page_size, mtts,
3763 MTT_MIN_COUNT, &wqe_sge_ba);
3764 if (!ibqp->srq)
3765 if (!check_wqe_rq_mtt_count(hr_dev, hr_qp, count, page_size))
3766 return -EINVAL;
926a01dc
WHX		 3767
3768 /* Search IRRL's mtts */
3769 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3770 hr_qp->qpn, &dma_handle_2);
3771 if (!mtts_2) {
ae1c6148 3772 ibdev_err(ibdev, "failed to find QP irrl_table\n");
926a01dc
WHX		 3773 return -EINVAL;
3774 }
3775
e92f2c18 3776 /* Search TRRL's mtts */
3777 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3778 hr_qp->qpn, &dma_handle_3);
3779 if (!mtts_3) {
ae1c6148 3780 ibdev_err(ibdev, "failed to find QP trrl_table\n");
e92f2c18 3781 return -EINVAL;
3782 }
3783
734f3863 3784 if (attr_mask & IB_QP_ALT_PATH) {
ae1c6148
LO		 3785 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error\n",
3786 attr_mask);
926a01dc
WHX		 3787 return -EINVAL;
3788 }
3789
3790 dmac = (u8 *)attr->ah_attr.roce.dmac;
bfe86035 3791 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
926a01dc
WHX		 3792 qpc_mask->wqe_sge_ba = 0;
3793
3794 /*
3795 * In v2 engine, software pass context and context mask to hardware
3796 * when modifying qp. If software need modify some fields in context,
3797 * we should set all bits of the relevant fields in context mask to
3798 * 0 at the same time, else set them to 0x1.
3799 */
3800 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
8d18ad83 3801 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3));
926a01dc
WHX		 3802 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3803 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3804
3805 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3806 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
8d18ad83
LO		 3807 hr_dev->caps.wqe_sq_hop_num == HNS_ROCE_HOP_NUM_0 ?
3808 0 : hr_dev->caps.wqe_sq_hop_num);
926a01dc
WHX		 3809 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3810 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3811
3812 roce_set_field(context->byte_20_smac_sgid_idx,
3813 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3814 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
8d18ad83
LO		 3815 ((ibqp->qp_type == IB_QPT_GSI) ||
3816 hr_qp->sq.max_gs > HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ?
3817 hr_dev->caps.wqe_sge_hop_num : 0);
926a01dc
WHX		 3818 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3819 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3820 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3821
3822 roce_set_field(context->byte_20_smac_sgid_idx,
3823 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3824 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
8d18ad83
LO		 3825 hr_dev->caps.wqe_rq_hop_num == HNS_ROCE_HOP_NUM_0 ?
3826 0 : hr_dev->caps.wqe_rq_hop_num);
926a01dc
WHX		 3827 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3828 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3829 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3830
3831 roce_set_field(context->byte_16_buf_ba_pg_sz,
3832 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3833 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
d563099e 3834 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
926a01dc
WHX		 3835 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3836 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3837 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3838
3839 roce_set_field(context->byte_16_buf_ba_pg_sz,
3840 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3841 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
d563099e 3842 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
926a01dc
WHX		 3843 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3844 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3845 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3846
d563099e 3847 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
926a01dc
WHX		 3848 qpc_mask->rq_cur_blk_addr = 0;
3849
3850 roce_set_field(context->byte_92_srq_info,
3851 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3852 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
d563099e 3853 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
926a01dc
WHX		 3854 roce_set_field(qpc_mask->byte_92_srq_info,
3855 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3856 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3857
d563099e 3858 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
926a01dc
WHX		 3859 qpc_mask->rq_nxt_blk_addr = 0;
3860
3861 roce_set_field(context->byte_104_rq_sge,
3862 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3863 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
d563099e 3864 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
926a01dc
WHX		 3865 roce_set_field(qpc_mask->byte_104_rq_sge,
3866 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3867 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3868
e92f2c18 3869 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3870 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3871 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3872 V2_QPC_BYTE_132_TRRL_BA_S, 0);
bfe86035 3873 context->trrl_ba = cpu_to_le32(dma_handle_3 >> (16 + 4));
e92f2c18 3874 qpc_mask->trrl_ba = 0;
3875 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3876 V2_QPC_BYTE_140_TRRL_BA_S,
3877 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3878 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3879 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3880
bfe86035 3881 context->irrl_ba = cpu_to_le32(dma_handle_2 >> 6);
926a01dc
WHX		 3882 qpc_mask->irrl_ba = 0;
3883 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3884 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3885 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3886 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3887 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3888
3889 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3890 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3891
3892 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3893 hr_qp->sq_signal_bits);
3894 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3895 0);
3896
3897 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3898
3899 smac = (u8 *)hr_dev->dev_addr[port];
3900 /* when dmac equals smac or loop_idc is 1, it should loopback */
3901 if (ether_addr_equal_unaligned(dmac, smac) ||
3902 hr_dev->loop_idc == 0x1) {
3903 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3904 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3905 }
3906
b6dd9b34 3907 if (attr_mask & IB_QP_DEST_QPN) {
3908 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3909 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3910 roce_set_field(qpc_mask->byte_56_dqpn_err,
3911 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3912 }
926a01dc
WHX		 3913
3914 /* Configure GID index */
3915 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3916 roce_set_field(context->byte_20_smac_sgid_idx,
60262b10 3917 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
926a01dc
WHX		 3918 hns_get_gid_index(hr_dev, port_num - 1,
3919 grh->sgid_index));
3920 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
60262b10 3921 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
2a3d923f 3922 memcpy(&(context->dmac), dmac, sizeof(u32));
926a01dc
WHX		 3923 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3924 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3925 qpc_mask->dmac = 0;
3926 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3927 V2_QPC_BYTE_52_DMAC_S, 0);
3928
2a3d923f 3929 /* mtu*(2^LP_PKTN_INI) should not bigger than 1 message length 64kb */
926a01dc 3930 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
9d04d56c 3931 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
926a01dc
WHX		 3932 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3933 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3934
0fa95a9a 3935 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3936 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3937 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3938 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3939 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3940 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3941
926a01dc
WHX		 3942 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3943 V2_QPC_BYTE_24_MTU_S, 0);
3944
926a01dc
WHX		 3945 roce_set_field(context->byte_84_rq_ci_pi,
3946 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3947 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3948 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3949 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3950 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3951
3952 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3953 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3954 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3955 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3956 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3957 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3958 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3959 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3960 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3961 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3962
3963 context->rq_rnr_timer = 0;
3964 qpc_mask->rq_rnr_timer = 0;
3965
926a01dc
WHX		 3966 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3967 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3968 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3969 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3970
2a3d923f 3971 /* rocee send 2^lp_sgen_ini segs every time */
926a01dc
WHX		 3972 roce_set_field(context->byte_168_irrl_idx,
3973 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3974 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3975 roce_set_field(qpc_mask->byte_168_irrl_idx,
3976 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3977 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3978
926a01dc
WHX		 3979 return 0;
3980}
3981
3982static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3983 const struct ib_qp_attr *attr, int attr_mask,
3984 struct hns_roce_v2_qp_context *context,
3985 struct hns_roce_v2_qp_context *qpc_mask)
3986{
3987 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3988 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 3989 struct ib_device *ibdev = &hr_dev->ib_dev;
8d18ad83
LO		 3990 u64 sge_cur_blk = 0;
3991 u64 sq_cur_blk = 0;
befb63b4 3992 u32 page_size;
8d18ad83 3993 int count;
926a01dc
WHX		 3994
3995 /* Search qp buf's mtts */
8d18ad83
LO		 3996 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
3997 if (count < 1) {
d563099e 3998 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf\n",
ae1c6148 3999 hr_qp->qpn);
926a01dc
WHX		 4000 return -EINVAL;
4001 }
4002
8d18ad83 4003 if (hr_qp->sge.offset) {
d563099e 4004 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift;
8d18ad83
LO		 4005 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
4006 hr_qp->sge.offset / page_size,
4007 &sge_cur_blk, 1, NULL);
4008 if (count < 1) {
d563099e 4009 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf\n",
ae1c6148 4010 hr_qp->qpn);
8d18ad83
LO		 4011 return -EINVAL;
4012 }
4013 }
4014
734f3863 4015 /* Not support alternate path and path migration */
d398d4ca 4016 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
ae1c6148 4017 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
926a01dc
WHX		 4018 return -EINVAL;
4019 }
4020
4021 /*
4022 * In v2 engine, software pass context and context mask to hardware
4023 * when modifying qp. If software need modify some fields in context,
4024 * we should set all bits of the relevant fields in context mask to
4025 * 0 at the same time, else set them to 0x1.
4026 */
d563099e 4027 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
926a01dc
WHX		 4028 roce_set_field(context->byte_168_irrl_idx,
4029 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
4030 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
d563099e 4031 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
926a01dc
WHX		 4032 qpc_mask->sq_cur_blk_addr = 0;
4033 roce_set_field(qpc_mask->byte_168_irrl_idx,
4034 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
4035 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
4036
2a3d923f
LO		 4037 context->sq_cur_sge_blk_addr = ((ibqp->qp_type == IB_QPT_GSI) ||
4038 hr_qp->sq.max_gs > HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ?
d563099e 4039 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk)) : 0;
befb63b4 4040 roce_set_field(context->byte_184_irrl_idx,
4041 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
4042 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
2a3d923f
LO		 4043 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs >
4044 HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ?
d563099e 4045 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)) : 0);
befb63b4 4046 qpc_mask->sq_cur_sge_blk_addr = 0;
4047 roce_set_field(qpc_mask->byte_184_irrl_idx,
4048 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
4049 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
4050
bfe86035 4051 context->rx_sq_cur_blk_addr =
d563099e 4052 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
926a01dc
WHX		 4053 roce_set_field(context->byte_232_irrl_sge,
4054 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
4055 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
d563099e 4056 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
926a01dc
WHX		 4057 qpc_mask->rx_sq_cur_blk_addr = 0;
4058 roce_set_field(qpc_mask->byte_232_irrl_sge,
4059 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
4060 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
4061
4062 /*
4063 * Set some fields in context to zero, Because the default values
4064 * of all fields in context are zero, we need not set them to 0 again.
4065 * but we should set the relevant fields of context mask to 0.
4066 */
4067 roce_set_field(qpc_mask->byte_232_irrl_sge,
4068 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
4069 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
4070
4071 roce_set_field(qpc_mask->byte_240_irrl_tail,
4072 V2_QPC_BYTE_240_RX_ACK_MSN_M,
4073 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
4074
926a01dc
WHX		 4075 roce_set_field(qpc_mask->byte_248_ack_psn,
4076 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
4077 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
4078 roce_set_bit(qpc_mask->byte_248_ack_psn,
4079 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
4080 roce_set_field(qpc_mask->byte_248_ack_psn,
4081 V2_QPC_BYTE_248_IRRL_PSN_M,
4082 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
4083
4084 roce_set_field(qpc_mask->byte_240_irrl_tail,
4085 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
4086 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
4087
926a01dc
WHX		 4088 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4089 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
4090 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
4091
4092 roce_set_bit(qpc_mask->byte_248_ack_psn,
4093 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
4094
4095 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
4096 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
4097
926a01dc
WHX		 4098 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4099 V2_QPC_BYTE_212_LSN_S, 0x100);
4100 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4101 V2_QPC_BYTE_212_LSN_S, 0);
4102
926a01dc
WHX		 4103 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
4104 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
926a01dc
WHX		 4105
4106 return 0;
4107}
4108
233673e4
LO		 4109static inline bool hns_roce_v2_check_qp_stat(enum ib_qp_state cur_state,
4110 enum ib_qp_state new_state)
4111{
4112
4113 if ((cur_state != IB_QPS_RESET &&
4114 (new_state == IB_QPS_ERR || new_state == IB_QPS_RESET)) ||
4115 ((cur_state == IB_QPS_RTS || cur_state == IB_QPS_SQD) &&
4116 (new_state == IB_QPS_RTS || new_state == IB_QPS_SQD)) ||
4117 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS))
4118 return true;
4119
4120 return false;
4121
4122}
4123
606bf89e
LO		 4124static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4125 const struct ib_qp_attr *attr,
4126 int attr_mask,
4127 struct hns_roce_v2_qp_context *context,
4128 struct hns_roce_v2_qp_context *qpc_mask)
926a01dc 4129{
606bf89e 4130 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
926a01dc
WHX		 4131 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4132 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 4133 struct ib_device *ibdev = &hr_dev->ib_dev;
606bf89e
LO		 4134 const struct ib_gid_attr *gid_attr = NULL;
4135 int is_roce_protocol;
32883228 4136 u16 vlan_id = 0xffff;
606bf89e 4137 bool is_udp = false;
606bf89e
LO		 4138 u8 ib_port;
4139 u8 hr_port;
4140 int ret;
926a01dc 4141
606bf89e
LO		 4142 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4143 hr_port = ib_port - 1;
4144 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4145 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4146
4147 if (is_roce_protocol) {
4148 gid_attr = attr->ah_attr.grh.sgid_attr;
32883228 4149 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
606bf89e
LO		 4150 if (ret)
4151 return ret;
4152
4153 if (gid_attr)
4154 is_udp = (gid_attr->gid_type ==
4155 IB_GID_TYPE_ROCE_UDP_ENCAP);
4156 }
4157
32883228 4158 if (vlan_id < VLAN_N_VID) {
606bf89e
LO		 4159 roce_set_bit(context->byte_76_srqn_op_en,
4160 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
4161 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
4162 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
4163 roce_set_bit(context->byte_168_irrl_idx,
4164 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
4165 roce_set_bit(qpc_mask->byte_168_irrl_idx,
4166 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
4167 }
4168
4169 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
32883228 4170 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id);
606bf89e
LO		 4171 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
4172 V2_QPC_BYTE_24_VLAN_ID_S, 0);
4173
4174 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
ae1c6148
LO		 4175 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4176 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
606bf89e
LO		 4177 return -EINVAL;
4178 }
4179
4180 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
ae1c6148 4181 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
606bf89e
LO		 4182 return -EINVAL;
4183 }
4184
4185 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4186 V2_QPC_BYTE_52_UDPSPN_S,
4187 is_udp ? 0x12b7 : 0);
4188
4189 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4190 V2_QPC_BYTE_52_UDPSPN_S, 0);
4191
4192 roce_set_field(context->byte_20_smac_sgid_idx,
4193 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
4194 grh->sgid_index);
4195
4196 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4197 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
4198
4199 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4200 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
4201 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4202 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
4203
dfaf2854 4204 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B && is_udp)
606bf89e
LO		 4205 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4206 V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2);
4207 else
4208 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4209 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
4210 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4211 V2_QPC_BYTE_24_TC_S, 0);
4212 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4213 V2_QPC_BYTE_28_FL_S, grh->flow_label);
4214 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4215 V2_QPC_BYTE_28_FL_S, 0);
4216 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4217 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4218 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4219 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr));
4220 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4221 V2_QPC_BYTE_28_SL_S, 0);
4222 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4223
4224 return 0;
4225}
4226
4227static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4228 const struct ib_qp_attr *attr,
4229 int attr_mask,
4230 enum ib_qp_state cur_state,
4231 enum ib_qp_state new_state,
4232 struct hns_roce_v2_qp_context *context,
4233 struct hns_roce_v2_qp_context *qpc_mask)
4234{
4235 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4236 int ret = 0;
926a01dc 4237
926a01dc 4238 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
9f507101 4239 memset(qpc_mask, 0, sizeof(*qpc_mask));
0fa95a9a 4240 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
4241 qpc_mask);
926a01dc
WHX		 4242 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4243 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
4244 qpc_mask);
4245 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4246 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4247 qpc_mask);
4248 if (ret)
4249 goto out;
4250 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4251 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
4252 qpc_mask);
4253 if (ret)
4254 goto out;
233673e4 4255 } else if (hns_roce_v2_check_qp_stat(cur_state, new_state)) {
926a01dc
WHX		 4256 /* Nothing */
4257 ;
4258 } else {
ae1c6148 4259 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
ac7cbf96 4260 ret = -EINVAL;
926a01dc
WHX		 4261 goto out;
4262 }
4263
606bf89e
LO		 4264out:
4265 return ret;
4266}
9c6ccc03 4267
606bf89e
LO		 4268static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
4269 const struct ib_qp_attr *attr,
4270 int attr_mask,
4271 struct hns_roce_v2_qp_context *context,
4272 struct hns_roce_v2_qp_context *qpc_mask)
4273{
4274 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4275 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4276 int ret = 0;
0425e3e6 4277
610b8967 4278 if (attr_mask & IB_QP_AV) {
606bf89e
LO		 4279 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
4280 qpc_mask);
4281 if (ret)
4282 return ret;
610b8967
LO		 4283 }
4284
5b01b243
LO		 4285 if (attr_mask & IB_QP_TIMEOUT) {
4286 if (attr->timeout < 31) {
4287 roce_set_field(context->byte_28_at_fl,
4288 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4289 attr->timeout);
4290 roce_set_field(qpc_mask->byte_28_at_fl,
4291 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4292 0);
4293 } else {
ae1c6148
LO		 4294 ibdev_warn(&hr_dev->ib_dev,
4295 "Local ACK timeout shall be 0 to 30.\n");
5b01b243
LO		 4296 }
4297 }
4298
4299 if (attr_mask & IB_QP_RETRY_CNT) {
4300 roce_set_field(context->byte_212_lsn,
4301 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4302 V2_QPC_BYTE_212_RETRY_NUM_INIT_S,
4303 attr->retry_cnt);
4304 roce_set_field(qpc_mask->byte_212_lsn,
4305 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4306 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
4307
4308 roce_set_field(context->byte_212_lsn,
4309 V2_QPC_BYTE_212_RETRY_CNT_M,
60262b10 4310 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
5b01b243
LO		 4311 roce_set_field(qpc_mask->byte_212_lsn,
4312 V2_QPC_BYTE_212_RETRY_CNT_M,
4313 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
4314 }
4315
4316 if (attr_mask & IB_QP_RNR_RETRY) {
4317 roce_set_field(context->byte_244_rnr_rxack,
4318 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4319 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
4320 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4321 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4322 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
4323
4324 roce_set_field(context->byte_244_rnr_rxack,
4325 V2_QPC_BYTE_244_RNR_CNT_M,
4326 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
4327 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4328 V2_QPC_BYTE_244_RNR_CNT_M,
4329 V2_QPC_BYTE_244_RNR_CNT_S, 0);
4330 }
4331
606bf89e 4332 /* RC&UC&UD required attr */
f04cc178
LO		 4333 if (attr_mask & IB_QP_SQ_PSN) {
4334 roce_set_field(context->byte_172_sq_psn,
4335 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4336 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
4337 roce_set_field(qpc_mask->byte_172_sq_psn,
4338 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4339 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
4340
4341 roce_set_field(context->byte_196_sq_psn,
4342 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4343 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
4344 roce_set_field(qpc_mask->byte_196_sq_psn,
4345 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4346 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
4347
4348 roce_set_field(context->byte_220_retry_psn_msn,
4349 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4350 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
4351 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4352 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4353 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
4354
4355 roce_set_field(context->byte_224_retry_msg,
4356 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4357 V2_QPC_BYTE_224_RETRY_MSG_PSN_S,
2a3d923f 4358 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S);
f04cc178
LO		 4359 roce_set_field(qpc_mask->byte_224_retry_msg,
4360 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4361 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
4362
4363 roce_set_field(context->byte_224_retry_msg,
4364 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4365 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S,
4366 attr->sq_psn);
4367 roce_set_field(qpc_mask->byte_224_retry_msg,
4368 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4369 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
4370
4371 roce_set_field(context->byte_244_rnr_rxack,
4372 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4373 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
4374 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4375 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4376 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
4377 }
4378
5b01b243
LO		 4379 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
4380 attr->max_dest_rd_atomic) {
4381 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4382 V2_QPC_BYTE_140_RR_MAX_S,
4383 fls(attr->max_dest_rd_atomic - 1));
4384 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4385 V2_QPC_BYTE_140_RR_MAX_S, 0);
4386 }
4387
4388 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
4389 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
4390 V2_QPC_BYTE_208_SR_MAX_S,
4391 fls(attr->max_rd_atomic - 1));
4392 roce_set_field(qpc_mask->byte_208_irrl,
4393 V2_QPC_BYTE_208_SR_MAX_M,
4394 V2_QPC_BYTE_208_SR_MAX_S, 0);
4395 }
4396
ace1c541 4397 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4398 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4399
5b01b243
LO		 4400 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
4401 roce_set_field(context->byte_80_rnr_rx_cqn,
4402 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4403 V2_QPC_BYTE_80_MIN_RNR_TIME_S,
4404 attr->min_rnr_timer);
4405 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
4406 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4407 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
4408 }
4409
601f3e6d
LO		 4410 /* RC&UC required attr */
4411 if (attr_mask & IB_QP_RQ_PSN) {
4412 roce_set_field(context->byte_108_rx_reqepsn,
4413 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4414 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
4415 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4416 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4417 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
4418
4419 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
4420 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
4421 roce_set_field(qpc_mask->byte_152_raq,
4422 V2_QPC_BYTE_152_RAQ_PSN_M,
4423 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
4424 }
4425
5b01b243 4426 if (attr_mask & IB_QP_QKEY) {
bfe86035 4427 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5b01b243
LO		 4428 qpc_mask->qkey_xrcd = 0;
4429 hr_qp->qkey = attr->qkey;
4430 }
4431
606bf89e
LO		 4432 return ret;
4433}
4434
4435static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
4436 const struct ib_qp_attr *attr,
4437 int attr_mask)
4438{
4439 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4440 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4441
4442 if (attr_mask & IB_QP_ACCESS_FLAGS)
4443 hr_qp->atomic_rd_en = attr->qp_access_flags;
4444
4445 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4446 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4447 if (attr_mask & IB_QP_PORT) {
4448 hr_qp->port = attr->port_num - 1;
4449 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4450 }
4451}
4452
4453static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
4454 const struct ib_qp_attr *attr,
4455 int attr_mask, enum ib_qp_state cur_state,
4456 enum ib_qp_state new_state)
4457{
4458 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4459 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d
LC		 4460 struct hns_roce_v2_qp_context ctx[2];
4461 struct hns_roce_v2_qp_context *context = ctx;
4462 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
ae1c6148 4463 struct ib_device *ibdev = &hr_dev->ib_dev;
b5374286
YL		 4464 unsigned long sq_flag = 0;
4465 unsigned long rq_flag = 0;
b5c229dc 4466 int ret;
606bf89e 4467
606bf89e
LO		 4468 /*
4469 * In v2 engine, software pass context and context mask to hardware
4470 * when modifying qp. If software need modify some fields in context,
4471 * we should set all bits of the relevant fields in context mask to
4472 * 0 at the same time, else set them to 0x1.
4473 */
4b42d05d 4474 memset(context, 0, sizeof(*context));
606bf89e
LO		 4475 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
4476 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
4477 new_state, context, qpc_mask);
4478 if (ret)
4479 goto out;
4480
4481 /* When QP state is err, SQ and RQ WQE should be flushed */
4482 if (new_state == IB_QPS_ERR) {
b5374286 4483 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
b5374286 4484 hr_qp->state = IB_QPS_ERR;
606bf89e
LO		 4485 roce_set_field(context->byte_160_sq_ci_pi,
4486 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4487 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
4488 hr_qp->sq.head);
4489 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
4490 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4491 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
75c994e6 4492 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
606bf89e
LO		 4493
4494 if (!ibqp->srq) {
75c994e6 4495 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4496 roce_set_field(context->byte_84_rq_ci_pi,
4497 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4498 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
4499 hr_qp->rq.head);
4500 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
4501 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4502 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
75c994e6 4503 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4504 }
4505 }
4506
4507 /* Configure the optional fields */
4508 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
4509 qpc_mask);
4510 if (ret)
4511 goto out;
4512
c7bcb134
LO		 4513 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S,
4514 ibqp->srq ? 1 : 0);
4515 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4516 V2_QPC_BYTE_108_INV_CREDIT_S, 0);
4517
926a01dc 4518 /* Every status migrate must change state */
2362ccee 4519 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 4520 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 4521 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 4522 V2_QPC_BYTE_60_QP_ST_S, 0);
4523
4524 /* SW pass context to HW */
032b0574 4525 ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp);
926a01dc 4526 if (ret) {
ae1c6148 4527 ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret);
926a01dc
WHX		 4528 goto out;
4529 }
4530
4531 hr_qp->state = new_state;
4532
606bf89e 4533 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
926a01dc
WHX		 4534
4535 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
4536 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
4537 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
4538 if (ibqp->send_cq != ibqp->recv_cq)
4539 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4540 hr_qp->qpn, NULL);
4541
4542 hr_qp->rq.head = 0;
4543 hr_qp->rq.tail = 0;
4544 hr_qp->sq.head = 0;
4545 hr_qp->sq.tail = 0;
926a01dc 4546 hr_qp->next_sge = 0;
e088a685
YL		 4547 if (hr_qp->rq.wqe_cnt)
4548 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 4549 }
4550
4551out:
926a01dc
WHX		 4552 return ret;
4553}
4554
4555static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
4556{
4557 switch (state) {
4558 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
4559 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
4560 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
4561 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
4562 case HNS_ROCE_QP_ST_SQ_DRAINING:
4563 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
4564 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
4565 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
4566 default: return -1;
4567 }
4568}
4569
4570static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
4571 struct hns_roce_qp *hr_qp,
4572 struct hns_roce_v2_qp_context *hr_context)
4573{
4574 struct hns_roce_cmd_mailbox *mailbox;
4575 int ret;
4576
4577 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4578 if (IS_ERR(mailbox))
4579 return PTR_ERR(mailbox);
4580
4581 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
4582 HNS_ROCE_CMD_QUERY_QPC,
4583 HNS_ROCE_CMD_TIMEOUT_MSECS);
ae1c6148 4584 if (ret)
926a01dc 4585 goto out;
926a01dc
WHX		 4586
4587 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
4588
4589out:
4590 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4591 return ret;
4592}
4593
4594static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4595 int qp_attr_mask,
4596 struct ib_qp_init_attr *qp_init_attr)
4597{
4598 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4599 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d 4600 struct hns_roce_v2_qp_context context = {};
ae1c6148 4601 struct ib_device *ibdev = &hr_dev->ib_dev;
926a01dc
WHX		 4602 int tmp_qp_state;
4603 int state;
4604 int ret;
4605
926a01dc
WHX		 4606 memset(qp_attr, 0, sizeof(*qp_attr));
4607 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4608
4609 mutex_lock(&hr_qp->mutex);
4610
4611 if (hr_qp->state == IB_QPS_RESET) {
4612 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 4613 ret = 0;
926a01dc
WHX		 4614 goto done;
4615 }
4616
4b42d05d 4617 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context);
926a01dc 4618 if (ret) {
ae1c6148 4619 ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret);
926a01dc
WHX		 4620 ret = -EINVAL;
4621 goto out;
4622 }
4623
4b42d05d 4624 state = roce_get_field(context.byte_60_qpst_tempid,
926a01dc
WHX		 4625 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
4626 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
4627 if (tmp_qp_state == -1) {
ae1c6148 4628 ibdev_err(ibdev, "Illegal ib_qp_state\n");
926a01dc
WHX		 4629 ret = -EINVAL;
4630 goto out;
4631 }
4632 hr_qp->state = (u8)tmp_qp_state;
4633 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
4b42d05d 4634 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4635 V2_QPC_BYTE_24_MTU_M,
4636 V2_QPC_BYTE_24_MTU_S);
4637 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 4638 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 4639 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
4640 qp_attr->qkey = V2_QKEY_VAL;
4641
4b42d05d 4642 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn,
926a01dc
WHX		 4643 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4644 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
4b42d05d 4645 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn,
926a01dc
WHX		 4646 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4647 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
4b42d05d 4648 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err,
926a01dc
WHX		 4649 V2_QPC_BYTE_56_DQPN_M,
4650 V2_QPC_BYTE_56_DQPN_S);
4b42d05d 4651 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4652 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) |
4b42d05d 4653 ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4654 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) |
4b42d05d 4655 ((roce_get_bit(context.byte_76_srqn_op_en,
2a3d923f
LO		 4656 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S);
4657
926a01dc
WHX		 4658 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
4659 hr_qp->ibqp.qp_type == IB_QPT_UC) {
4660 struct ib_global_route *grh =
4661 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
4662
4663 rdma_ah_set_sl(&qp_attr->ah_attr,
4b42d05d 4664 roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4665 V2_QPC_BYTE_28_SL_M,
4666 V2_QPC_BYTE_28_SL_S));
4b42d05d 4667 grh->flow_label = roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4668 V2_QPC_BYTE_28_FL_M,
4669 V2_QPC_BYTE_28_FL_S);
4b42d05d 4670 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx,
926a01dc
WHX		 4671 V2_QPC_BYTE_20_SGID_IDX_M,
4672 V2_QPC_BYTE_20_SGID_IDX_S);
4b42d05d 4673 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4674 V2_QPC_BYTE_24_HOP_LIMIT_M,
4675 V2_QPC_BYTE_24_HOP_LIMIT_S);
4b42d05d 4676 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4677 V2_QPC_BYTE_24_TC_M,
4678 V2_QPC_BYTE_24_TC_S);
4679
4b42d05d 4680 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
926a01dc
WHX		 4681 }
4682
4683 qp_attr->port_num = hr_qp->port + 1;
4684 qp_attr->sq_draining = 0;
4b42d05d 4685 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl,
926a01dc
WHX		 4686 V2_QPC_BYTE_208_SR_MAX_M,
4687 V2_QPC_BYTE_208_SR_MAX_S);
4b42d05d 4688 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq,
926a01dc
WHX		 4689 V2_QPC_BYTE_140_RR_MAX_M,
4690 V2_QPC_BYTE_140_RR_MAX_S);
4b42d05d 4691 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn,
926a01dc
WHX		 4692 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4693 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4b42d05d 4694 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4695 V2_QPC_BYTE_28_AT_M,
4696 V2_QPC_BYTE_28_AT_S);
4b42d05d 4697 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn,
926a01dc
WHX		 4698 V2_QPC_BYTE_212_RETRY_CNT_M,
4699 V2_QPC_BYTE_212_RETRY_CNT_S);
bfe86035 4700 qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer);
926a01dc
WHX		 4701
4702done:
4703 qp_attr->cur_qp_state = qp_attr->qp_state;
4704 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4705 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4706
4707 if (!ibqp->uobject) {
4708 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4709 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4710 } else {
4711 qp_attr->cap.max_send_wr = 0;
4712 qp_attr->cap.max_send_sge = 0;
4713 }
4714
4715 qp_init_attr->cap = qp_attr->cap;
4716
4717out:
4718 mutex_unlock(&hr_qp->mutex);
926a01dc
WHX		 4719 return ret;
4720}
4721
4722static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4723 struct hns_roce_qp *hr_qp,
bdeacabd 4724 struct ib_udata *udata)
926a01dc 4725{
db50077b 4726 struct ib_device *ibdev = &hr_dev->ib_dev;
ae1c6148 4727 struct hns_roce_cq *send_cq, *recv_cq;
626903e9 4728 unsigned long flags;
d302c6e3 4729 int ret = 0;
926a01dc
WHX		 4730
4731 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4732 /* Modify qp to reset before destroying qp */
4733 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4734 hr_qp->state, IB_QPS_RESET);
d302c6e3 4735 if (ret)
ae1c6148
LO		 4736 ibdev_err(ibdev,
4737 "failed to modify QP to RST, ret = %d\n",
4738 ret);
926a01dc
WHX		 4739 }
4740
626903e9
XW		 4741 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
4742 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
926a01dc 4743
626903e9 4744 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
926a01dc
WHX		 4745 hns_roce_lock_cqs(send_cq, recv_cq);
4746
bdeacabd 4747 if (!udata) {
626903e9
XW		 4748 if (recv_cq)
4749 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
4750 (hr_qp->ibqp.srq ?
4751 to_hr_srq(hr_qp->ibqp.srq) :
4752 NULL));
4753
4754 if (send_cq && send_cq != recv_cq)
926a01dc 4755 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
626903e9 4756
926a01dc
WHX		 4757 }
4758
4759 hns_roce_qp_remove(hr_dev, hr_qp);
4760
4761 hns_roce_unlock_cqs(send_cq, recv_cq);
626903e9 4762 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
926a01dc 4763
d302c6e3 4764 return ret;
926a01dc
WHX		 4765}
4766
c4367a26 4767static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
926a01dc
WHX		 4768{
4769 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4770 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4771 int ret;
4772
bdeacabd 4773 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
d302c6e3 4774 if (ret)
ae1c6148
LO		 4775 ibdev_err(&hr_dev->ib_dev,
4776 "failed to destroy QP 0x%06lx, ret = %d\n",
db50077b 4777 hr_qp->qpn, ret);
926a01dc 4778
e365b26c 4779 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
926a01dc
WHX		 4780
4781 return 0;
4782}
4783
aa84fa18 4784static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
ae1c6148 4785 struct hns_roce_qp *hr_qp)
aa84fa18 4786{
ae1c6148 4787 struct ib_device *ibdev = &hr_dev->ib_dev;
da91ddfd 4788 struct hns_roce_sccc_clr_done *resp;
aa84fa18
YL		 4789 struct hns_roce_sccc_clr *clr;
4790 struct hns_roce_cmq_desc desc;
4791 int ret, i;
4792
4793 mutex_lock(&hr_dev->qp_table.scc_mutex);
4794
4795 /* set scc ctx clear done flag */
4796 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
aa84fa18
YL		 4797 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4798 if (ret) {
ae1c6148 4799 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4800 goto out;
4801 }
4802
4803 /* clear scc context */
4804 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
4805 clr = (struct hns_roce_sccc_clr *)desc.data;
4806 clr->qpn = cpu_to_le32(hr_qp->qpn);
4807 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4808 if (ret) {
ae1c6148 4809 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4810 goto out;
4811 }
4812
4813 /* query scc context clear is done or not */
4814 resp = (struct hns_roce_sccc_clr_done *)desc.data;
4815 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
4816 hns_roce_cmq_setup_basic_desc(&desc,
4817 HNS_ROCE_OPC_QUERY_SCCC, true);
4818 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4819 if (ret) {
ae1c6148
LO		 4820 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
4821 ret);
aa84fa18
YL		 4822 goto out;
4823 }
4824
4825 if (resp->clr_done)
4826 goto out;
4827
4828 msleep(20);
4829 }
4830
ae1c6148 4831 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n");
aa84fa18
YL		 4832 ret = -ETIMEDOUT;
4833
4834out:
4835 mutex_unlock(&hr_dev->qp_table.scc_mutex);
4836 return ret;
4837}
4838
b156269d 4839static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
4840{
4841 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
4842 struct hns_roce_v2_cq_context *cq_context;
4843 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
4844 struct hns_roce_v2_cq_context *cqc_mask;
4845 struct hns_roce_cmd_mailbox *mailbox;
4846 int ret;
4847
4848 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4849 if (IS_ERR(mailbox))
4850 return PTR_ERR(mailbox);
4851
4852 cq_context = mailbox->buf;
4853 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
4854
4855 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
4856
4857 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4858 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4859 cq_count);
4860 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4861 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4862 0);
4863 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4864 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4865 cq_period);
4866 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4867 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4868 0);
4869
4870 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
4871 HNS_ROCE_CMD_MODIFY_CQC,
4872 HNS_ROCE_CMD_TIMEOUT_MSECS);
4873 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4874 if (ret)
ae1c6148
LO		 4875 ibdev_err(&hr_dev->ib_dev,
4876 "failed to process cmd when modifying CQ, ret = %d\n",
4877 ret);
b156269d 4878
4879 return ret;
4880}
4881
0425e3e6
YL		 4882static void hns_roce_irq_work_handle(struct work_struct *work)
4883{
4884 struct hns_roce_work *irq_work =
4885 container_of(work, struct hns_roce_work, work);
ae1c6148 4886 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
0425e3e6 4887 u32 qpn = irq_work->qpn;
b00a92c8 4888 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4889
4890 switch (irq_work->event_type) {
b00a92c8 4891 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
ae1c6148 4892 ibdev_info(ibdev, "Path migrated succeeded.\n");
b00a92c8 4893 break;
4894 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
ae1c6148 4895 ibdev_warn(ibdev, "Path migration failed.\n");
b00a92c8 4896 break;
4897 case HNS_ROCE_EVENT_TYPE_COMM_EST:
b00a92c8 4898 break;
4899 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
ae1c6148 4900 ibdev_warn(ibdev, "Send queue drained.\n");
b00a92c8 4901 break;
0425e3e6 4902 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
ae1c6148
LO		 4903 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n",
4904 qpn, irq_work->sub_type);
b00a92c8 4905 break;
0425e3e6 4906 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
ae1c6148
LO		 4907 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n",
4908 qpn);
b00a92c8 4909 break;
0425e3e6 4910 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
ae1c6148
LO		 4911 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n",
4912 qpn, irq_work->sub_type);
b00a92c8 4913 break;
4914 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
ae1c6148 4915 ibdev_warn(ibdev, "SRQ limit reach.\n");
b00a92c8 4916 break;
4917 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
ae1c6148 4918 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
b00a92c8 4919 break;
4920 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
ae1c6148 4921 ibdev_err(ibdev, "SRQ catas error.\n");
b00a92c8 4922 break;
4923 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
ae1c6148 4924 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn);
b00a92c8 4925 break;
4926 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
ae1c6148 4927 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn);
b00a92c8 4928 break;
4929 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
ae1c6148 4930 ibdev_warn(ibdev, "DB overflow.\n");
b00a92c8 4931 break;
4932 case HNS_ROCE_EVENT_TYPE_FLR:
ae1c6148 4933 ibdev_warn(ibdev, "Function level reset.\n");
0425e3e6
YL		 4934 break;
4935 default:
4936 break;
4937 }
4938
4939 kfree(irq_work);
4940}
4941
4942static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4943 struct hns_roce_eq *eq,
4944 u32 qpn, u32 cqn)
0425e3e6
YL		 4945{
4946 struct hns_roce_work *irq_work;
4947
4948 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4949 if (!irq_work)
4950 return;
4951
4952 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4953 irq_work->hr_dev = hr_dev;
4954 irq_work->qpn = qpn;
b00a92c8 4955 irq_work->cqn = cqn;
0425e3e6
YL		 4956 irq_work->event_type = eq->event_type;
4957 irq_work->sub_type = eq->sub_type;
4958 queue_work(hr_dev->irq_workq, &(irq_work->work));
4959}
4960
a5073d60
YL		 4961static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4962{
d3743fa9 4963 struct hns_roce_dev *hr_dev = eq->hr_dev;
880f133c 4964 __le32 doorbell[2] = {};
a5073d60
YL		 4965
4966 if (eq->type_flag == HNS_ROCE_AEQ) {
4967 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4968 HNS_ROCE_V2_EQ_DB_CMD_S,
4969 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4970 HNS_ROCE_EQ_DB_CMD_AEQ :
4971 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4972 } else {
4973 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4974 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4975
4976 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4977 HNS_ROCE_V2_EQ_DB_CMD_S,
4978 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4979 HNS_ROCE_EQ_DB_CMD_CEQ :
4980 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4981 }
4982
4983 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4984 HNS_ROCE_V2_EQ_DB_PARA_S,
4985 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4986
d3743fa9 4987 hns_roce_write64(hr_dev, doorbell, eq->doorbell);
a5073d60
YL		 4988}
4989
a5073d60
YL		 4990static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4991{
4992 struct hns_roce_aeqe *aeqe;
4993
477a0a38 4994 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a
XW		 4995 (eq->cons_index & (eq->entries - 1)) *
4996 HNS_ROCE_AEQ_ENTRY_SIZE);
4997
a5073d60
YL		 4998 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4999 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5000}
5001
5002static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5003 struct hns_roce_eq *eq)
5004{
5005 struct device *dev = hr_dev->dev;
e7f40440 5006 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 5007 int aeqe_found = 0;
5008 int event_type;
0425e3e6 5009 int sub_type;
81fce629 5010 u32 srqn;
0425e3e6
YL		 5011 u32 qpn;
5012 u32 cqn;
a5073d60 5013
e7f40440 5014 while (aeqe) {
4044a3f4
YL		 5015 /* Make sure we read AEQ entry after we have checked the
5016 * ownership bit
5017 */
5018 dma_rmb();
a5073d60
YL		 5019
5020 event_type = roce_get_field(aeqe->asyn,
5021 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
5022 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 5023 sub_type = roce_get_field(aeqe->asyn,
5024 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
5025 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
5026 qpn = roce_get_field(aeqe->event.qp_event.qp,
5027 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5028 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5029 cqn = roce_get_field(aeqe->event.cq_event.cq,
5030 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5031 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
81fce629
LO		 5032 srqn = roce_get_field(aeqe->event.srq_event.srq,
5033 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5034 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 5035
5036 switch (event_type) {
5037 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 5038 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 5039 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5040 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5041 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
81fce629 5042 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
a5073d60
YL		 5043 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5044 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 5045 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 5046 break;
5047 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
a5073d60 5048 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
81fce629 5049 hns_roce_srq_event(hr_dev, srqn, event_type);
a5073d60
YL		 5050 break;
5051 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5052 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 5053 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 5054 break;
5055 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 5056 break;
5057 case HNS_ROCE_EVENT_TYPE_MB:
5058 hns_roce_cmd_event(hr_dev,
5059 le16_to_cpu(aeqe->event.cmd.token),
5060 aeqe->event.cmd.status,
5061 le64_to_cpu(aeqe->event.cmd.out_param));
5062 break;
5063 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 5064 break;
5065 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 5066 break;
5067 default:
5068 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
5069 event_type, eq->eqn, eq->cons_index);
5070 break;
790b57f6 5071 }
a5073d60 5072
0425e3e6
YL		 5073 eq->event_type = event_type;
5074 eq->sub_type = sub_type;
a5073d60
YL		 5075 ++eq->cons_index;
5076 aeqe_found = 1;
5077
249f2f92 5078 if (eq->cons_index > (2 * eq->entries - 1))
a5073d60 5079 eq->cons_index = 0;
249f2f92 5080
b00a92c8 5081 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
e7f40440
LC		 5082
5083 aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 5084 }
5085
5086 set_eq_cons_index_v2(eq);
5087 return aeqe_found;
5088}
5089
a5073d60
YL		 5090static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
5091{
5092 struct hns_roce_ceqe *ceqe;
5093
477a0a38 5094 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a
XW		 5095 (eq->cons_index & (eq->entries - 1)) *
5096 HNS_ROCE_CEQ_ENTRY_SIZE);
a5073d60
YL		 5097 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
5098 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
5099}
5100
5101static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
5102 struct hns_roce_eq *eq)
5103{
e7f40440 5104 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5105 int ceqe_found = 0;
5106 u32 cqn;
5107
e7f40440 5108 while (ceqe) {
4044a3f4
YL		 5109 /* Make sure we read CEQ entry after we have checked the
5110 * ownership bit
5111 */
5112 dma_rmb();
5113
60262b10 5114 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M,
a5073d60
YL		 5115 HNS_ROCE_V2_CEQE_COMP_CQN_S);
5116
5117 hns_roce_cq_completion(hr_dev, cqn);
5118
5119 ++eq->cons_index;
5120 ceqe_found = 1;
5121
bceda6e6 5122 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1))
a5073d60 5123 eq->cons_index = 0;
e7f40440
LC		 5124
5125 ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5126 }
5127
5128 set_eq_cons_index_v2(eq);
5129
5130 return ceqe_found;
5131}
5132
5133static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
5134{
5135 struct hns_roce_eq *eq = eq_ptr;
5136 struct hns_roce_dev *hr_dev = eq->hr_dev;
5137 int int_work = 0;
5138
5139 if (eq->type_flag == HNS_ROCE_CEQ)
5140 /* Completion event interrupt */
5141 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
5142 else
5143 /* Asychronous event interrupt */
5144 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5145
5146 return IRQ_RETVAL(int_work);
5147}
5148
5149static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5150{
5151 struct hns_roce_dev *hr_dev = dev_id;
5152 struct device *dev = hr_dev->dev;
5153 int int_work = 0;
5154 u32 int_st;
5155 u32 int_en;
5156
5157 /* Abnormal interrupt */
5158 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5159 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5160
bfe86035 5161 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
2b9acb9a
XT		 5162 struct pci_dev *pdev = hr_dev->pci_dev;
5163 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5164 const struct hnae3_ae_ops *ops = ae_dev->ops;
5165
a5073d60
YL		 5166 dev_err(dev, "AEQ overflow!\n");
5167
bfe86035 5168 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S;
a5073d60
YL		 5169 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5170
2b9acb9a
XT		 5171 /* Set reset level for reset_event() */
5172 if (ops->set_default_reset_request)
5173 ops->set_default_reset_request(ae_dev,
5174 HNAE3_FUNC_RESET);
5175 if (ops->reset_event)
5176 ops->reset_event(pdev, NULL);
5177
bfe86035 5178 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5179 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5180
5181 int_work = 1;
bfe86035 5182 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
a5073d60
YL		 5183 dev_err(dev, "BUS ERR!\n");
5184
bfe86035 5185 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S;
a5073d60
YL		 5186 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5187
bfe86035 5188 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5189 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5190
5191 int_work = 1;
bfe86035 5192 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
a5073d60
YL		 5193 dev_err(dev, "OTHER ERR!\n");
5194
bfe86035 5195 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S;
a5073d60
YL		 5196 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5197
bfe86035 5198 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5199 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5200
5201 int_work = 1;
5202 } else
5203 dev_err(dev, "There is no abnormal irq found!\n");
5204
5205 return IRQ_RETVAL(int_work);
5206}
5207
5208static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5209 int eq_num, int enable_flag)
5210{
5211 int i;
5212
5213 if (enable_flag == EQ_ENABLE) {
5214 for (i = 0; i < eq_num; i++)
5215 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5216 i * EQ_REG_OFFSET,
5217 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
5218
5219 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5220 HNS_ROCE_V2_VF_ABN_INT_EN_M);
5221 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5222 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
5223 } else {
5224 for (i = 0; i < eq_num; i++)
5225 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5226 i * EQ_REG_OFFSET,
5227 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
5228
5229 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5230 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
5231 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5232 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
5233 }
5234}
5235
5236static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5237{
5238 struct device *dev = hr_dev->dev;
5239 int ret;
5240
5241 if (eqn < hr_dev->caps.num_comp_vectors)
5242 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5243 0, HNS_ROCE_CMD_DESTROY_CEQC,
5244 HNS_ROCE_CMD_TIMEOUT_MSECS);
5245 else
5246 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5247 0, HNS_ROCE_CMD_DESTROY_AEQC,
5248 HNS_ROCE_CMD_TIMEOUT_MSECS);
5249 if (ret)
5250 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5251}
5252
d7e2d343 5253static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
a5073d60 5254{
477a0a38 5255 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
a5073d60
YL		 5256}
5257
477a0a38
XW		 5258static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
5259 void *mb_buf)
a5073d60 5260{
477a0a38 5261 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
a5073d60 5262 struct hns_roce_eq_context *eqc;
477a0a38 5263 u64 bt_ba = 0;
d7e2d343 5264 int count;
a5073d60
YL		 5265
5266 eqc = mb_buf;
5267 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5268
5269 /* init eqc */
5270 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
a5073d60
YL		 5271 eq->cons_index = 0;
5272 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5273 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5274 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
a5073d60
YL		 5275 eq->shift = ilog2((unsigned int)eq->entries);
5276
cc23267a 5277 /* if not multi-hop, eqe buffer only use one trunk */
477a0a38
XW		 5278 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
5279 &bt_ba);
5280 if (count < 1) {
5281 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
5282 return -ENOBUFS;
d7e2d343 5283 }
a5073d60
YL		 5284
5285 /* set eqc state */
60262b10 5286 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S,
a5073d60
YL		 5287 HNS_ROCE_V2_EQ_STATE_VALID);
5288
5289 /* set eqe hop num */
60262b10 5290 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M,
a5073d60
YL		 5291 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
5292
5293 /* set eqc over_ignore */
60262b10 5294 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M,
a5073d60
YL		 5295 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
5296
5297 /* set eqc coalesce */
60262b10 5298 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M,
a5073d60
YL		 5299 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
5300
5301 /* set eqc arm_state */
60262b10 5302 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M,
a5073d60
YL		 5303 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
5304
5305 /* set eqn */
60262b10
LO		 5306 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S,
5307 eq->eqn);
a5073d60
YL		 5308
5309 /* set eqe_cnt */
60262b10
LO		 5310 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M,
5311 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT);
a5073d60
YL		 5312
5313 /* set eqe_ba_pg_sz */
60262b10 5314 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db 5315 HNS_ROCE_EQC_BA_PG_SZ_S,
477a0a38 5316 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
a5073d60
YL		 5317
5318 /* set eqe_buf_pg_sz */
60262b10 5319 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db 5320 HNS_ROCE_EQC_BUF_PG_SZ_S,
477a0a38 5321 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
a5073d60
YL		 5322
5323 /* set eq_producer_idx */
60262b10
LO		 5324 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M,
5325 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX);
a5073d60
YL		 5326
5327 /* set eq_max_cnt */
60262b10 5328 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M,
a5073d60
YL		 5329 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
5330
5331 /* set eq_period */
60262b10 5332 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M,
a5073d60
YL		 5333 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
5334
5335 /* set eqe_report_timer */
60262b10 5336 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M,
a5073d60
YL		 5337 HNS_ROCE_EQC_REPORT_TIMER_S,
5338 HNS_ROCE_EQ_INIT_REPORT_TIMER);
5339
477a0a38 5340 /* set bt_ba [34:3] */
60262b10 5341 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M,
477a0a38 5342 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3);
a5073d60 5343
477a0a38 5344 /* set bt_ba [64:35] */
60262b10 5345 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M,
477a0a38 5346 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35);
a5073d60
YL		 5347
5348 /* set eq shift */
60262b10
LO		 5349 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S,
5350 eq->shift);
a5073d60
YL		 5351
5352 /* set eq MSI_IDX */
60262b10
LO		 5353 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M,
5354 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX);
a5073d60
YL		 5355
5356 /* set cur_eqe_ba [27:12] */
60262b10 5357 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M,
477a0a38 5358 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12);
a5073d60
YL		 5359
5360 /* set cur_eqe_ba [59:28] */
60262b10 5361 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M,
477a0a38 5362 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28);
a5073d60
YL		 5363
5364 /* set cur_eqe_ba [63:60] */
60262b10 5365 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M,
477a0a38 5366 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60);
a5073d60
YL		 5367
5368 /* set eq consumer idx */
60262b10
LO		 5369 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
5370 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
a5073d60
YL		 5371
5372 /* set nex_eqe_ba[43:12] */
60262b10 5373 roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
477a0a38 5374 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
a5073d60
YL		 5375
5376 /* set nex_eqe_ba[63:44] */
60262b10 5377 roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
477a0a38 5378 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
a5073d60 5379
477a0a38 5380 return 0;
d7e2d343 5381}
a5073d60 5382
d7e2d343
XW		 5383static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5384{
477a0a38
XW		 5385 struct hns_roce_buf_attr buf_attr = {};
5386 int err;
a5073d60 5387
477a0a38
XW		 5388 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
5389 eq->hop_num = 0;
5390 else
5391 eq->hop_num = hr_dev->caps.eqe_hop_num;
a5073d60 5392
477a0a38
XW		 5393 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_ADDR_SHIFT;
5394 buf_attr.region[0].size = eq->entries * eq->eqe_size;
5395 buf_attr.region[0].hopnum = eq->hop_num;
5396 buf_attr.region_count = 1;
5397 buf_attr.fixed_page = true;
d7e2d343 5398
477a0a38
XW		 5399 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
5400 hr_dev->caps.srqwqe_ba_pg_sz +
5401 PAGE_ADDR_SHIFT, NULL, 0);
5402 if (err)
5403 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err);
a5073d60 5404
477a0a38 5405 return err;
a5073d60
YL		 5406}
5407
5408static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5409 struct hns_roce_eq *eq,
5410 unsigned int eq_cmd)
5411{
a5073d60 5412 struct hns_roce_cmd_mailbox *mailbox;
a5073d60
YL		 5413 int ret;
5414
5415 /* Allocate mailbox memory */
5416 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
477a0a38
XW		 5417 if (IS_ERR_OR_NULL(mailbox))
5418 return -ENOMEM;
a5073d60 5419
d7e2d343 5420 ret = alloc_eq_buf(hr_dev, eq);
477a0a38 5421 if (ret)
d7e2d343 5422 goto free_cmd_mbox;
477a0a38
XW		 5423
5424 ret = config_eqc(hr_dev, eq, mailbox->buf);
5425 if (ret)
5426 goto err_cmd_mbox;
a5073d60
YL		 5427
5428 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5429 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5430 if (ret) {
d7e2d343 5431 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5432 goto err_cmd_mbox;
5433 }
5434
5435 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5436
5437 return 0;
5438
5439err_cmd_mbox:
d7e2d343 5440 free_eq_buf(hr_dev, eq);
a5073d60
YL		 5441
5442free_cmd_mbox:
5443 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5444
5445 return ret;
5446}
5447
33db6f94
YL		 5448static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
5449 int comp_num, int aeq_num, int other_num)
5450{
5451 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5452 int i, j;
5453 int ret;
5454
5455 for (i = 0; i < irq_num; i++) {
5456 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5457 GFP_KERNEL);
5458 if (!hr_dev->irq_names[i]) {
5459 ret = -ENOMEM;
5460 goto err_kzalloc_failed;
5461 }
5462 }
5463
6def7de6 5464 /* irq contains: abnormal + AEQ + CEQ */
bebdb83f 5465 for (j = 0; j < other_num; j++)
60262b10
LO		 5466 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5467 "hns-abn-%d", j);
bebdb83f
LC		 5468
5469 for (j = other_num; j < (other_num + aeq_num); j++)
60262b10
LO		 5470 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5471 "hns-aeq-%d", j - other_num);
bebdb83f
LC		 5472
5473 for (j = (other_num + aeq_num); j < irq_num; j++)
60262b10
LO		 5474 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5475 "hns-ceq-%d", j - other_num - aeq_num);
33db6f94
YL		 5476
5477 for (j = 0; j < irq_num; j++) {
5478 if (j < other_num)
5479 ret = request_irq(hr_dev->irq[j],
5480 hns_roce_v2_msix_interrupt_abn,
5481 0, hr_dev->irq_names[j], hr_dev);
5482
5483 else if (j < (other_num + comp_num))
5484 ret = request_irq(eq_table->eq[j - other_num].irq,
5485 hns_roce_v2_msix_interrupt_eq,
5486 0, hr_dev->irq_names[j + aeq_num],
5487 &eq_table->eq[j - other_num]);
5488 else
5489 ret = request_irq(eq_table->eq[j - other_num].irq,
5490 hns_roce_v2_msix_interrupt_eq,
5491 0, hr_dev->irq_names[j - comp_num],
5492 &eq_table->eq[j - other_num]);
5493 if (ret) {
5494 dev_err(hr_dev->dev, "Request irq error!\n");
5495 goto err_request_failed;
5496 }
5497 }
5498
5499 return 0;
5500
5501err_request_failed:
5502 for (j -= 1; j >= 0; j--)
5503 if (j < other_num)
5504 free_irq(hr_dev->irq[j], hr_dev);
5505 else
5506 free_irq(eq_table->eq[j - other_num].irq,
5507 &eq_table->eq[j - other_num]);
5508
5509err_kzalloc_failed:
5510 for (i -= 1; i >= 0; i--)
5511 kfree(hr_dev->irq_names[i]);
5512
5513 return ret;
5514}
5515
5516static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
5517{
5518 int irq_num;
5519 int eq_num;
5520 int i;
5521
5522 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5523 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5524
5525 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5526 free_irq(hr_dev->irq[i], hr_dev);
5527
5528 for (i = 0; i < eq_num; i++)
5529 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
5530
5531 for (i = 0; i < irq_num; i++)
5532 kfree(hr_dev->irq_names[i]);
5533}
5534
a5073d60
YL		 5535static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5536{
5537 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5538 struct device *dev = hr_dev->dev;
5539 struct hns_roce_eq *eq;
5540 unsigned int eq_cmd;
5541 int irq_num;
5542 int eq_num;
5543 int other_num;
5544 int comp_num;
5545 int aeq_num;
33db6f94 5546 int i;
a5073d60
YL		 5547 int ret;
5548
5549 other_num = hr_dev->caps.num_other_vectors;
5550 comp_num = hr_dev->caps.num_comp_vectors;
5551 aeq_num = hr_dev->caps.num_aeq_vectors;
5552
5553 eq_num = comp_num + aeq_num;
5554 irq_num = eq_num + other_num;
5555
5556 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5557 if (!eq_table->eq)
5558 return -ENOMEM;
5559
a5073d60 5560 /* create eq */
33db6f94
YL		 5561 for (i = 0; i < eq_num; i++) {
5562 eq = &eq_table->eq[i];
a5073d60 5563 eq->hr_dev = hr_dev;
33db6f94
YL		 5564 eq->eqn = i;
5565 if (i < comp_num) {
a5073d60
YL		 5566 /* CEQ */
5567 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5568 eq->type_flag = HNS_ROCE_CEQ;
5569 eq->entries = hr_dev->caps.ceqe_depth;
5570 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
33db6f94 5571 eq->irq = hr_dev->irq[i + other_num + aeq_num];
a5073d60
YL		 5572 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5573 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5574 } else {
5575 /* AEQ */
5576 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5577 eq->type_flag = HNS_ROCE_AEQ;
5578 eq->entries = hr_dev->caps.aeqe_depth;
5579 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
33db6f94 5580 eq->irq = hr_dev->irq[i - comp_num + other_num];
a5073d60
YL		 5581 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5582 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5583 }
5584
5585 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5586 if (ret) {
5587 dev_err(dev, "eq create failed.\n");
5588 goto err_create_eq_fail;
5589 }
5590 }
5591
5592 /* enable irq */
5593 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5594
33db6f94
YL		 5595 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num,
5596 aeq_num, other_num);
5597 if (ret) {
5598 dev_err(dev, "Request irq failed.\n");
5599 goto err_request_irq_fail;
a5073d60
YL		 5600 }
5601
ffd541d4 5602 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
0425e3e6
YL		 5603 if (!hr_dev->irq_workq) {
5604 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5605 ret = -ENOMEM;
33db6f94 5606 goto err_create_wq_fail;
0425e3e6
YL		 5607 }
5608
a5073d60
YL		 5609 return 0;
5610
33db6f94
YL		 5611err_create_wq_fail:
5612 __hns_roce_free_irq(hr_dev);
5613
a5073d60 5614err_request_irq_fail:
33db6f94 5615 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
a5073d60
YL		 5616
5617err_create_eq_fail:
a5073d60 5618 for (i -= 1; i >= 0; i--)
d7e2d343 5619 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5620 kfree(eq_table->eq);
5621
5622 return ret;
5623}
5624
5625static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5626{
5627 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
a5073d60
YL		 5628 int eq_num;
5629 int i;
5630
5631 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
a5073d60
YL		 5632
5633 /* Disable irq */
5634 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5635
33db6f94 5636 __hns_roce_free_irq(hr_dev);
a5073d60
YL		 5637
5638 for (i = 0; i < eq_num; i++) {
5639 hns_roce_v2_destroy_eqc(hr_dev, i);
5640
d7e2d343 5641 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5642 }
5643
a5073d60 5644 kfree(eq_table->eq);
0425e3e6
YL		 5645
5646 flush_workqueue(hr_dev->irq_workq);
5647 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5648}
5649
c7bcb134
LO		 5650static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
5651 struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
5652 u32 cqn, void *mb_buf, u64 *mtts_wqe,
5653 u64 *mtts_idx, dma_addr_t dma_handle_wqe,
5654 dma_addr_t dma_handle_idx)
5655{
5656 struct hns_roce_srq_context *srq_context;
5657
5658 srq_context = mb_buf;
5659 memset(srq_context, 0, sizeof(*srq_context));
5660
5661 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M,
5662 SRQC_BYTE_4_SRQ_ST_S, 1);
5663
5664 roce_set_field(srq_context->byte_4_srqn_srqst,
5665 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M,
5666 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S,
5667 (hr_dev->caps.srqwqe_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5668 hr_dev->caps.srqwqe_hop_num));
5669 roce_set_field(srq_context->byte_4_srqn_srqst,
5670 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S,
d938d785 5671 ilog2(srq->wqe_cnt));
c7bcb134
LO		 5672
5673 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M,
5674 SRQC_BYTE_4_SRQN_S, srq->srqn);
5675
5676 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5677 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5678
5679 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
5680 SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
5681
5682 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));
5683
5684 roce_set_field(srq_context->byte_24_wqe_bt_ba,
5685 SRQC_BYTE_24_SRQ_WQE_BT_BA_M,
5686 SRQC_BYTE_24_SRQ_WQE_BT_BA_S,
bfe86035 5687 dma_handle_wqe >> 35);
c7bcb134
LO		 5688
5689 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
5690 SRQC_BYTE_28_PD_S, pdn);
5691 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
5692 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
5693 fls(srq->max_gs - 1));
5694
bfe86035 5695 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3);
c7bcb134
LO		 5696 roce_set_field(srq_context->rsv_idx_bt_ba,
5697 SRQC_BYTE_36_SRQ_IDX_BT_BA_M,
5698 SRQC_BYTE_36_SRQ_IDX_BT_BA_S,
bfe86035 5699 dma_handle_idx >> 35);
c7bcb134 5700
c7bcb134 5701 srq_context->idx_cur_blk_addr =
6fd610c5 5702 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0]));
c7bcb134
LO		 5703 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5704 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M,
5705 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S,
6fd610c5 5706 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
c7bcb134
LO		 5707 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5708 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M,
5709 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S,
5710 hr_dev->caps.idx_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5711 hr_dev->caps.idx_hop_num);
5712
6fd610c5
XW		 5713 roce_set_field(
5714 srq_context->byte_44_idxbufpgsz_addr,
5715 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
5716 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
5717 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift));
5718 roce_set_field(
5719 srq_context->byte_44_idxbufpgsz_addr,
5720 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
5721 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
5722 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift));
c7bcb134 5723
c7bcb134 5724 srq_context->idx_nxt_blk_addr =
6fd610c5 5725 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1]));
c7bcb134
LO		 5726 roce_set_field(srq_context->rsv_idxnxtblkaddr,
5727 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M,
5728 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S,
6fd610c5 5729 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
c7bcb134
LO		 5730 roce_set_field(srq_context->byte_56_xrc_cqn,
5731 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
5732 cqn);
5733 roce_set_field(srq_context->byte_56_xrc_cqn,
5734 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
5735 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
6fd610c5 5736 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
c7bcb134
LO		 5737 roce_set_field(srq_context->byte_56_xrc_cqn,
5738 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M,
5739 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S,
6fd610c5 5740 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
c7bcb134
LO		 5741
5742 roce_set_bit(srq_context->db_record_addr_record_en,
5743 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0);
5744}
5745
5746static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5747 struct ib_srq_attr *srq_attr,
5748 enum ib_srq_attr_mask srq_attr_mask,
5749 struct ib_udata *udata)
5750{
5751 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5752 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5753 struct hns_roce_srq_context *srq_context;
5754 struct hns_roce_srq_context *srqc_mask;
5755 struct hns_roce_cmd_mailbox *mailbox;
5756 int ret;
5757
5758 if (srq_attr_mask & IB_SRQ_LIMIT) {
d938d785 5759 if (srq_attr->srq_limit >= srq->wqe_cnt)
c7bcb134
LO		 5760 return -EINVAL;
5761
5762 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5763 if (IS_ERR(mailbox))
5764 return PTR_ERR(mailbox);
5765
5766 srq_context = mailbox->buf;
5767 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5768
5769 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5770
5771 roce_set_field(srq_context->byte_8_limit_wl,
5772 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5773 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit);
5774 roce_set_field(srqc_mask->byte_8_limit_wl,
5775 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5776 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5777
5778 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5779 HNS_ROCE_CMD_MODIFY_SRQC,
5780 HNS_ROCE_CMD_TIMEOUT_MSECS);
5781 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5782 if (ret) {
ae1c6148
LO		 5783 ibdev_err(&hr_dev->ib_dev,
5784 "failed to process cmd when modifying SRQ, ret = %d\n",
5785 ret);
c7bcb134
LO		 5786 return ret;
5787 }
5788 }
5789
5790 return 0;
5791}
5792
c3c668e7 5793static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
c7bcb134
LO		 5794{
5795 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5796 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5797 struct hns_roce_srq_context *srq_context;
5798 struct hns_roce_cmd_mailbox *mailbox;
5799 int limit_wl;
5800 int ret;
5801
5802 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5803 if (IS_ERR(mailbox))
5804 return PTR_ERR(mailbox);
5805
5806 srq_context = mailbox->buf;
5807 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5808 HNS_ROCE_CMD_QUERY_SRQC,
5809 HNS_ROCE_CMD_TIMEOUT_MSECS);
5810 if (ret) {
ae1c6148
LO		 5811 ibdev_err(&hr_dev->ib_dev,
5812 "failed to process cmd when querying SRQ, ret = %d\n",
5813 ret);
c7bcb134
LO		 5814 goto out;
5815 }
5816
5817 limit_wl = roce_get_field(srq_context->byte_8_limit_wl,
5818 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5819 SRQC_BYTE_8_SRQ_LIMIT_WL_S);
5820
5821 attr->srq_limit = limit_wl;
d938d785 5822 attr->max_wr = srq->wqe_cnt - 1;
c7bcb134
LO		 5823 attr->max_sge = srq->max_gs;
5824
5825 memcpy(srq_context, mailbox->buf, sizeof(*srq_context));
5826
5827out:
5828 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5829 return ret;
5830}
5831
97545b10
LO		 5832static int find_empty_entry(struct hns_roce_idx_que *idx_que,
5833 unsigned long size)
c7bcb134 5834{
97545b10 5835 int wqe_idx;
c7bcb134 5836
97545b10
LO		 5837 if (unlikely(bitmap_full(idx_que->bitmap, size)))
5838 return -ENOSPC;
5839
5840 wqe_idx = find_first_zero_bit(idx_que->bitmap, size);
5841
5842 bitmap_set(idx_que->bitmap, wqe_idx, 1);
c7bcb134 5843
97545b10 5844 return wqe_idx;
c7bcb134
LO		 5845}
5846
5847static void fill_idx_queue(struct hns_roce_idx_que *idx_que,
5848 int cur_idx, int wqe_idx)
5849{
5850 unsigned int *addr;
5851
6fd610c5 5852 addr = (unsigned int *)hns_roce_buf_offset(idx_que->mtr.kmem,
c7bcb134
LO		 5853 cur_idx * idx_que->entry_sz);
5854 *addr = wqe_idx;
5855}
5856
5857static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
5858 const struct ib_recv_wr *wr,
5859 const struct ib_recv_wr **bad_wr)
5860{
d3743fa9 5861 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
c7bcb134
LO		 5862 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5863 struct hns_roce_v2_wqe_data_seg *dseg;
5864 struct hns_roce_v2_db srq_db;
5865 unsigned long flags;
5866 int ret = 0;
5867 int wqe_idx;
5868 void *wqe;
5869 int nreq;
5870 int ind;
5871 int i;
5872
5873 spin_lock_irqsave(&srq->lock, flags);
5874
d938d785 5875 ind = srq->head & (srq->wqe_cnt - 1);
c7bcb134
LO		 5876
5877 for (nreq = 0; wr; ++nreq, wr = wr->next) {
5878 if (unlikely(wr->num_sge > srq->max_gs)) {
5879 ret = -EINVAL;
5880 *bad_wr = wr;
5881 break;
5882 }
5883
5884 if (unlikely(srq->head == srq->tail)) {
5885 ret = -ENOMEM;
5886 *bad_wr = wr;
5887 break;
5888 }
5889
d938d785 5890 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt);
97545b10
LO		 5891 if (wqe_idx < 0) {
5892 ret = -ENOMEM;
5893 *bad_wr = wr;
5894 break;
5895 }
5896
c7bcb134
LO		 5897 fill_idx_queue(&srq->idx_que, ind, wqe_idx);
5898 wqe = get_srq_wqe(srq, wqe_idx);
5899 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
5900
5901 for (i = 0; i < wr->num_sge; ++i) {
5902 dseg[i].len = cpu_to_le32(wr->sg_list[i].length);
5903 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey);
5904 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr);
5905 }
5906
5907 if (i < srq->max_gs) {
4f18904c
LO		 5908 dseg[i].len = 0;
5909 dseg[i].lkey = cpu_to_le32(0x100);
5910 dseg[i].addr = 0;
c7bcb134
LO		 5911 }
5912
5913 srq->wrid[wqe_idx] = wr->wr_id;
d938d785 5914 ind = (ind + 1) & (srq->wqe_cnt - 1);
c7bcb134
LO		 5915 }
5916
5917 if (likely(nreq)) {
5918 srq->head += nreq;
5919
5920 /*
5921 * Make sure that descriptors are written before
5922 * doorbell record.
5923 */
5924 wmb();
5925
bfe86035
LC		 5926 srq_db.byte_4 =
5927 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S |
5928 (srq->srqn & V2_DB_BYTE_4_TAG_M));
5929 srq_db.parameter = cpu_to_le32(srq->head);
c7bcb134 5930
d3743fa9 5931 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l);
c7bcb134
LO		 5932
5933 }
5934
5935 spin_unlock_irqrestore(&srq->lock, flags);
5936
5937 return ret;
5938}
5939
e1c9a0dc
LO		 5940static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = {
5941 .query_cqc_info = hns_roce_v2_query_cqc_info,
5942};
5943
7f645a58
KH		 5944static const struct ib_device_ops hns_roce_v2_dev_ops = {
5945 .destroy_qp = hns_roce_v2_destroy_qp,
5946 .modify_cq = hns_roce_v2_modify_cq,
5947 .poll_cq = hns_roce_v2_poll_cq,
5948 .post_recv = hns_roce_v2_post_recv,
5949 .post_send = hns_roce_v2_post_send,
5950 .query_qp = hns_roce_v2_query_qp,
5951 .req_notify_cq = hns_roce_v2_req_notify_cq,
5952};
5953
5954static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
5955 .modify_srq = hns_roce_v2_modify_srq,
5956 .post_srq_recv = hns_roce_v2_post_srq_recv,
5957 .query_srq = hns_roce_v2_query_srq,
5958};
5959
a04ff739
WHX		 5960static const struct hns_roce_hw hns_roce_hw_v2 = {
5961 .cmq_init = hns_roce_v2_cmq_init,
5962 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5963 .hw_profile = hns_roce_v2_profile,
6b63597d 5964 .hw_init = hns_roce_v2_init,
5965 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5966 .post_mbox = hns_roce_v2_post_mbox,
5967 .chk_mbox = hns_roce_v2_chk_mbox,
6a04aed6 5968 .rst_prc_mbox = hns_roce_v2_rst_process_cmd,
7afddafa
WHX		 5969 .set_gid = hns_roce_v2_set_gid,
5970 .set_mac = hns_roce_v2_set_mac,
3958cc56 5971 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5972 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 5973 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 5974 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 5975 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5976 .set_hem = hns_roce_v2_set_hem,
5977 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5978 .modify_qp = hns_roce_v2_modify_qp,
5979 .query_qp = hns_roce_v2_query_qp,
5980 .destroy_qp = hns_roce_v2_destroy_qp,
aa84fa18 5981 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
b156269d 5982 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5983 .post_send = hns_roce_v2_post_send,
5984 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5985 .req_notify_cq = hns_roce_v2_req_notify_cq,
5986 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5987 .init_eq = hns_roce_v2_init_eq_table,
5988 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
c7bcb134
LO		 5989 .write_srqc = hns_roce_v2_write_srqc,
5990 .modify_srq = hns_roce_v2_modify_srq,
5991 .query_srq = hns_roce_v2_query_srq,
5992 .post_srq_recv = hns_roce_v2_post_srq_recv,
7f645a58
KH		 5993 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
5994 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
a04ff739 5995};
dd74282d
WHX		 5996
5997static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5998 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5999 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 6000 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6001 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 6002 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6003 /* required last entry */
6004 {0, }
6005};
6006
f97a62c3 6007MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6008
301cc7eb 6009static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
dd74282d
WHX		 6010 struct hnae3_handle *handle)
6011{
d061effc 6012 struct hns_roce_v2_priv *priv = hr_dev->priv;
a5073d60 6013 int i;
dd74282d 6014
301cc7eb
LC		 6015 hr_dev->pci_dev = handle->pdev;
6016 hr_dev->dev = &handle->pdev->dev;
dd74282d 6017 hr_dev->hw = &hns_roce_hw_v2;
e1c9a0dc 6018 hr_dev->dfx = &hns_roce_dfx_hw_v2;
2d407888
WHX		 6019 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6020 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 6021
6022 /* Get info from NIC driver. */
6023 hr_dev->reg_base = handle->rinfo.roce_io_base;
6024 hr_dev->caps.num_ports = 1;
6025 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6026 hr_dev->iboe.phy_port[0] = 0;
6027
d4994d2f 6028 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6029 hr_dev->iboe.netdevs[0]->dev_addr);
6030
a5073d60
YL		 6031 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
6032 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6033 i + handle->rinfo.base_vector);
6034
dd74282d 6035 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 6036 hr_dev->cmd_mod = 1;
dd74282d
WHX		 6037 hr_dev->loop_idc = 0;
6038
d061effc
WHX		 6039 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6040 priv->handle = handle;
dd74282d
WHX		 6041}
6042
d061effc 6043static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
dd74282d
WHX		 6044{
6045 struct hns_roce_dev *hr_dev;
6046 int ret;
6047
459cc69f 6048 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
dd74282d
WHX		 6049 if (!hr_dev)
6050 return -ENOMEM;
6051
a04ff739
WHX		 6052 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6053 if (!hr_dev->priv) {
6054 ret = -ENOMEM;
6055 goto error_failed_kzalloc;
6056 }
6057
301cc7eb 6058 hns_roce_hw_v2_get_cfg(hr_dev, handle);
dd74282d
WHX		 6059
6060 ret = hns_roce_init(hr_dev);
6061 if (ret) {
6062 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6063 goto error_failed_get_cfg;
6064 }
6065
d061effc
WHX		 6066 handle->priv = hr_dev;
6067
dd74282d
WHX		 6068 return 0;
6069
6070error_failed_get_cfg:
a04ff739
WHX		 6071 kfree(hr_dev->priv);
6072
6073error_failed_kzalloc:
dd74282d
WHX		 6074 ib_dealloc_device(&hr_dev->ib_dev);
6075
6076 return ret;
6077}
6078
d061effc 6079static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
dd74282d
WHX		 6080 bool reset)
6081{
6082 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
6083
cb7a94c9
WHX		 6084 if (!hr_dev)
6085 return;
6086
d061effc 6087 handle->priv = NULL;
626903e9
XW		 6088
6089 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6090 hns_roce_handle_device_err(hr_dev);
6091
dd74282d 6092 hns_roce_exit(hr_dev);
a04ff739 6093 kfree(hr_dev->priv);
dd74282d
WHX		 6094 ib_dealloc_device(&hr_dev->ib_dev);
6095}
6096
d061effc
WHX		 6097static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6098{
6099 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
07c2339a 6100 const struct pci_device_id *id;
d061effc
WHX		 6101 struct device *dev = &handle->pdev->dev;
6102 int ret;
6103
6104 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6105
6106 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6107 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6108 goto reset_chk_err;
6109 }
6110
07c2339a
LO		 6111 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6112 if (!id)
6113 return 0;
6114
d061effc
WHX		 6115 ret = __hns_roce_hw_v2_init_instance(handle);
6116 if (ret) {
6117 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6118 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6119 if (ops->ae_dev_resetting(handle) ||
6120 ops->get_hw_reset_stat(handle))
6121 goto reset_chk_err;
6122 else
6123 return ret;
6124 }
6125
6126 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6127
6128
6129 return 0;
6130
6131reset_chk_err:
6132 dev_err(dev, "Device is busy in resetting state.\n"
6133 "please retry later.\n");
6134
6135 return -EBUSY;
6136}
6137
6138static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6139 bool reset)
6140{
6141 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6142 return;
6143
6144 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6145
6146 __hns_roce_hw_v2_uninit_instance(handle, reset);
6147
6148 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6149}
cb7a94c9
WHX		 6150static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6151{
d061effc 6152 struct hns_roce_dev *hr_dev;
cb7a94c9 6153
d061effc
WHX		 6154 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6155 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6156 return 0;
cb7a94c9
WHX		 6157 }
6158
d061effc
WHX		 6159 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6160 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6161
6162 hr_dev = (struct hns_roce_dev *)handle->priv;
6163 if (!hr_dev)
6164 return 0;
6165
726be12f 6166 hr_dev->is_reset = true;
cb7a94c9 6167 hr_dev->active = false;
d3743fa9 6168 hr_dev->dis_db = true;
cb7a94c9 6169
626903e9 6170 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
cb7a94c9
WHX		 6171
6172 return 0;
6173}
6174
6175static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6176{
d061effc 6177 struct device *dev = &handle->pdev->dev;
cb7a94c9
WHX		 6178 int ret;
6179
d061effc
WHX		 6180 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6181 &handle->rinfo.state)) {
6182 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6183 return 0;
6184 }
6185
6186 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6187
6188 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6189 ret = __hns_roce_hw_v2_init_instance(handle);
cb7a94c9
WHX		 6190 if (ret) {
6191 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6192 * callback function, RoCE Engine reinitialize. If RoCE reinit
6193 * failed, we should inform NIC driver.
6194 */
6195 handle->priv = NULL;
d061effc
WHX		 6196 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6197 } else {
6198 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6199 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
cb7a94c9
WHX		 6200 }
6201
6202 return ret;
6203}
6204
6205static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6206{
d061effc
WHX		 6207 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6208 return 0;
6209
6210 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6211 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
90c559b1 6212 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
d061effc
WHX		 6213 __hns_roce_hw_v2_uninit_instance(handle, false);
6214
cb7a94c9
WHX		 6215 return 0;
6216}
6217
6218static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6219 enum hnae3_reset_notify_type type)
6220{
6221 int ret = 0;
6222
6223 switch (type) {
6224 case HNAE3_DOWN_CLIENT:
6225 ret = hns_roce_hw_v2_reset_notify_down(handle);
6226 break;
6227 case HNAE3_INIT_CLIENT:
6228 ret = hns_roce_hw_v2_reset_notify_init(handle);
6229 break;
6230 case HNAE3_UNINIT_CLIENT:
6231 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6232 break;
6233 default:
6234 break;
6235 }
6236
6237 return ret;
6238}
6239
dd74282d
WHX		 6240static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6241 .init_instance = hns_roce_hw_v2_init_instance,
6242 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 6243 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 6244};
6245
6246static struct hnae3_client hns_roce_hw_v2_client = {
6247 .name = "hns_roce_hw_v2",
6248 .type = HNAE3_CLIENT_ROCE,
6249 .ops = &hns_roce_hw_v2_ops,
6250};
6251
6252static int __init hns_roce_hw_v2_init(void)
6253{
6254 return hnae3_register_client(&hns_roce_hw_v2_client);
6255}
6256
6257static void __exit hns_roce_hw_v2_exit(void)
6258{
6259 hnae3_unregister_client(&hns_roce_hw_v2_client);
6260}
6261
6262module_init(hns_roce_hw_v2_init);
6263module_exit(hns_roce_hw_v2_exit);
6264
6265MODULE_LICENSE("Dual BSD/GPL");
6266MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6267MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6268MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6269MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)