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RDMA: Handle SRQ allocations by IB/core
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
dd74282d 40#include <rdma/ib_umem.h>
bdeacabd 41#include <rdma/uverbs_ioctl.h>
dd74282d
WHX		 42
43#include "hnae3.h"
44#include "hns_roce_common.h"
45#include "hns_roce_device.h"
46#include "hns_roce_cmd.h"
47#include "hns_roce_hem.h"
a04ff739 48#include "hns_roce_hw_v2.h"
dd74282d 49
2d407888
WHX		 50static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
51 struct ib_sge *sg)
52{
53 dseg->lkey = cpu_to_le32(sg->lkey);
54 dseg->addr = cpu_to_le64(sg->addr);
55 dseg->len = cpu_to_le32(sg->length);
56}
57
68a997c5
YL		 58static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
59 struct hns_roce_wqe_frmr_seg *fseg,
60 const struct ib_reg_wr *wr)
61{
62 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
63
64 /* use ib_access_flags */
65 roce_set_bit(rc_sq_wqe->byte_4,
66 V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
67 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
68 roce_set_bit(rc_sq_wqe->byte_4,
69 V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
70 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
71 roce_set_bit(rc_sq_wqe->byte_4,
72 V2_RC_FRMR_WQE_BYTE_4_RR_S,
73 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
74 roce_set_bit(rc_sq_wqe->byte_4,
75 V2_RC_FRMR_WQE_BYTE_4_RW_S,
76 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
77 roce_set_bit(rc_sq_wqe->byte_4,
78 V2_RC_FRMR_WQE_BYTE_4_LW_S,
79 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
80
81 /* Data structure reuse may lead to confusion */
82 rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff);
83 rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32);
84
85 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
86 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
87 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
88 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
89
90 fseg->pbl_size = cpu_to_le32(mr->pbl_size);
91 roce_set_field(fseg->mode_buf_pg_sz,
92 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
93 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
94 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
95 roce_set_bit(fseg->mode_buf_pg_sz,
96 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
97}
98
384f8818
LO		 99static void set_atomic_seg(struct hns_roce_wqe_atomic_seg *aseg,
100 const struct ib_atomic_wr *wr)
101{
102 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
103 aseg->fetchadd_swap_data = cpu_to_le64(wr->swap);
104 aseg->cmp_data = cpu_to_le64(wr->compare_add);
105 } else {
106 aseg->fetchadd_swap_data = cpu_to_le64(wr->compare_add);
107 aseg->cmp_data = 0;
108 }
109}
110
f696bf6d 111static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
0b25c9cc
WHX		 112 unsigned int *sge_ind)
113{
114 struct hns_roce_v2_wqe_data_seg *dseg;
115 struct ib_sge *sg;
116 int num_in_wqe = 0;
117 int extend_sge_num;
118 int fi_sge_num;
119 int se_sge_num;
120 int shift;
121 int i;
122
123 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
124 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
125 extend_sge_num = wr->num_sge - num_in_wqe;
126 sg = wr->sg_list + num_in_wqe;
127 shift = qp->hr_buf.page_shift;
128
129 /*
130 * Check whether wr->num_sge sges are in the same page. If not, we
131 * should calculate how many sges in the first page and the second
132 * page.
133 */
134 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
135 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
136 (uintptr_t)dseg) /
137 sizeof(struct hns_roce_v2_wqe_data_seg);
138 if (extend_sge_num > fi_sge_num) {
139 se_sge_num = extend_sge_num - fi_sge_num;
140 for (i = 0; i < fi_sge_num; i++) {
141 set_data_seg_v2(dseg++, sg + i);
142 (*sge_ind)++;
143 }
144 dseg = get_send_extend_sge(qp,
145 (*sge_ind) & (qp->sge.sge_cnt - 1));
146 for (i = 0; i < se_sge_num; i++) {
147 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
148 (*sge_ind)++;
149 }
150 } else {
151 for (i = 0; i < extend_sge_num; i++) {
152 set_data_seg_v2(dseg++, sg + i);
153 (*sge_ind)++;
154 }
155 }
156}
157
f696bf6d 158static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 159 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
160 void *wqe, unsigned int *sge_ind,
d34ac5cd 161 const struct ib_send_wr **bad_wr)
7bdee415 162{
163 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
164 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
165 struct hns_roce_qp *qp = to_hr_qp(ibqp);
166 int i;
167
168 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 169 if (le32_to_cpu(rc_sq_wqe->msg_len) >
170 hr_dev->caps.max_sq_inline) {
7bdee415 171 *bad_wr = wr;
172 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
173 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
174 return -EINVAL;
175 }
176
328d405b 177 if (wr->opcode == IB_WR_RDMA_READ) {
c80e0661 178 *bad_wr = wr;
328d405b 179 dev_err(hr_dev->dev, "Not support inline data!\n");
180 return -EINVAL;
181 }
182
7bdee415 183 for (i = 0; i < wr->num_sge; i++) {
184 memcpy(wqe, ((void *)wr->sg_list[i].addr),
185 wr->sg_list[i].length);
186 wqe += wr->sg_list[i].length;
187 }
188
189 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
190 1);
191 } else {
0b25c9cc 192 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 193 for (i = 0; i < wr->num_sge; i++) {
194 if (likely(wr->sg_list[i].length)) {
195 set_data_seg_v2(dseg, wr->sg_list + i);
196 dseg++;
197 }
198 }
199 } else {
200 roce_set_field(rc_sq_wqe->byte_20,
201 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
202 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
203 (*sge_ind) & (qp->sge.sge_cnt - 1));
204
0b25c9cc 205 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 206 if (likely(wr->sg_list[i].length)) {
207 set_data_seg_v2(dseg, wr->sg_list + i);
208 dseg++;
209 }
210 }
211
0b25c9cc 212 set_extend_sge(qp, wr, sge_ind);
7bdee415 213 }
214
215 roce_set_field(rc_sq_wqe->byte_16,
216 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
217 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
218 }
219
220 return 0;
221}
222
0425e3e6
YL		 223static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
224 const struct ib_qp_attr *attr,
225 int attr_mask, enum ib_qp_state cur_state,
226 enum ib_qp_state new_state);
227
d34ac5cd
BVA		 228static int hns_roce_v2_post_send(struct ib_qp *ibqp,
229 const struct ib_send_wr *wr,
230 const struct ib_send_wr **bad_wr)
2d407888
WHX		 231{
232 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
7bdee415 233 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
234 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
2d407888
WHX		 235 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
236 struct hns_roce_qp *qp = to_hr_qp(ibqp);
68a997c5 237 struct hns_roce_wqe_frmr_seg *fseg;
2d407888
WHX		 238 struct device *dev = hr_dev->dev;
239 struct hns_roce_v2_db sq_db;
0425e3e6 240 struct ib_qp_attr attr;
2d407888 241 unsigned int sge_ind = 0;
e8d18533 242 unsigned int owner_bit;
2d407888
WHX		 243 unsigned long flags;
244 unsigned int ind;
245 void *wqe = NULL;
7bdee415 246 bool loopback;
0425e3e6 247 int attr_mask;
55ba49cb 248 u32 tmp_len;
2d407888 249 int ret = 0;
b9c1ea40 250 u32 hr_op;
7bdee415 251 u8 *smac;
2d407888
WHX		 252 int nreq;
253 int i;
254
7bdee415 255 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
256 ibqp->qp_type != IB_QPT_GSI &&
257 ibqp->qp_type != IB_QPT_UD)) {
2d407888 258 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
137ae320 259 *bad_wr = wr;
2d407888
WHX		 260 return -EOPNOTSUPP;
261 }
262
10bd2ade
YL		 263 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT ||
264 qp->state == IB_QPS_RTR)) {
2d407888
WHX		 265 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
266 *bad_wr = wr;
267 return -EINVAL;
268 }
269
270 spin_lock_irqsave(&qp->sq.lock, flags);
271 ind = qp->sq_next_wqe;
272 sge_ind = qp->next_sge;
273
274 for (nreq = 0; wr; ++nreq, wr = wr->next) {
275 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
276 ret = -ENOMEM;
277 *bad_wr = wr;
278 goto out;
279 }
280
281 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
282 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
283 wr->num_sge, qp->sq.max_gs);
284 ret = -EINVAL;
285 *bad_wr = wr;
286 goto out;
287 }
288
289 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
290 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
291 wr->wr_id;
292
634f6390 293 owner_bit =
294 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
55ba49cb 295 tmp_len = 0;
2d407888 296
7bdee415 297 /* Corresponding to the QP type, wqe process separately */
298 if (ibqp->qp_type == IB_QPT_GSI) {
299 ud_sq_wqe = wqe;
300 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
301
302 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
303 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
304 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
305 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
306 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
307 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
308 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
309 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
310 roce_set_field(ud_sq_wqe->byte_48,
311 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
312 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
313 ah->av.mac[4]);
314 roce_set_field(ud_sq_wqe->byte_48,
315 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
316 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
317 ah->av.mac[5]);
318
319 /* MAC loopback */
320 smac = (u8 *)hr_dev->dev_addr[qp->port];
321 loopback = ether_addr_equal_unaligned(ah->av.mac,
322 smac) ? 1 : 0;
323
324 roce_set_bit(ud_sq_wqe->byte_40,
325 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
326
327 roce_set_field(ud_sq_wqe->byte_4,
328 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
329 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
330 HNS_ROCE_V2_WQE_OP_SEND);
2d407888 331
7bdee415 332 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 333 tmp_len += wr->sg_list[i].length;
492b2bd0 334
8b9b8d14 335 ud_sq_wqe->msg_len =
336 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len);
337
338 switch (wr->opcode) {
339 case IB_WR_SEND_WITH_IMM:
340 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 341 ud_sq_wqe->immtdata =
342 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 343 break;
344 default:
345 ud_sq_wqe->immtdata = 0;
346 break;
347 }
651487c2 348
7bdee415 349 /* Set sig attr */
350 roce_set_bit(ud_sq_wqe->byte_4,
351 V2_UD_SEND_WQE_BYTE_4_CQE_S,
352 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
a49d761f 353
7bdee415 354 /* Set se attr */
355 roce_set_bit(ud_sq_wqe->byte_4,
356 V2_UD_SEND_WQE_BYTE_4_SE_S,
357 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
e8d18533 358
7bdee415 359 roce_set_bit(ud_sq_wqe->byte_4,
360 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
361
362 roce_set_field(ud_sq_wqe->byte_16,
363 V2_UD_SEND_WQE_BYTE_16_PD_M,
364 V2_UD_SEND_WQE_BYTE_16_PD_S,
365 to_hr_pd(ibqp->pd)->pdn);
366
367 roce_set_field(ud_sq_wqe->byte_16,
368 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
369 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
370 wr->num_sge);
371
372 roce_set_field(ud_sq_wqe->byte_20,
373 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
374 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
375 sge_ind & (qp->sge.sge_cnt - 1));
376
377 roce_set_field(ud_sq_wqe->byte_24,
378 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
379 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
380 ud_sq_wqe->qkey =
8b9b8d14 381 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
382 qp->qkey : ud_wr(wr)->remote_qkey);
7bdee415 383 roce_set_field(ud_sq_wqe->byte_32,
384 V2_UD_SEND_WQE_BYTE_32_DQPN_M,
385 V2_UD_SEND_WQE_BYTE_32_DQPN_S,
386 ud_wr(wr)->remote_qpn);
387
388 roce_set_field(ud_sq_wqe->byte_36,
389 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
390 V2_UD_SEND_WQE_BYTE_36_VLAN_S,
8b9b8d14 391 le16_to_cpu(ah->av.vlan));
7bdee415 392 roce_set_field(ud_sq_wqe->byte_36,
393 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
394 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
395 ah->av.hop_limit);
396 roce_set_field(ud_sq_wqe->byte_36,
397 V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
398 V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
cdfa4ad5
LO		 399 ah->av.sl_tclass_flowlabel >>
400 HNS_ROCE_TCLASS_SHIFT);
7bdee415 401 roce_set_field(ud_sq_wqe->byte_40,
402 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
cdfa4ad5
LO		 403 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
404 ah->av.sl_tclass_flowlabel &
405 HNS_ROCE_FLOW_LABEL_MASK);
7bdee415 406 roce_set_field(ud_sq_wqe->byte_40,
407 V2_UD_SEND_WQE_BYTE_40_SL_M,
408 V2_UD_SEND_WQE_BYTE_40_SL_S,
8b9b8d14 409 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
410 HNS_ROCE_SL_SHIFT);
7bdee415 411 roce_set_field(ud_sq_wqe->byte_40,
412 V2_UD_SEND_WQE_BYTE_40_PORTN_M,
413 V2_UD_SEND_WQE_BYTE_40_PORTN_S,
414 qp->port);
415
8320deb8
LO		 416 roce_set_bit(ud_sq_wqe->byte_40,
417 V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
418 ah->av.vlan_en ? 1 : 0);
7bdee415 419 roce_set_field(ud_sq_wqe->byte_48,
420 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
421 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
422 hns_get_gid_index(hr_dev, qp->phy_port,
423 ah->av.gid_index));
424
425 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
426 GID_LEN_V2);
427
0b25c9cc 428 set_extend_sge(qp, wr, &sge_ind);
7bdee415 429 ind++;
430 } else if (ibqp->qp_type == IB_QPT_RC) {
431 rc_sq_wqe = wqe;
432 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
433 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 434 tmp_len += wr->sg_list[i].length;
435
436 rc_sq_wqe->msg_len =
437 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len);
7bdee415 438
8b9b8d14 439 switch (wr->opcode) {
440 case IB_WR_SEND_WITH_IMM:
441 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 442 rc_sq_wqe->immtdata =
443 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 444 break;
445 case IB_WR_SEND_WITH_INV:
446 rc_sq_wqe->inv_key =
447 cpu_to_le32(wr->ex.invalidate_rkey);
448 break;
449 default:
450 rc_sq_wqe->immtdata = 0;
451 break;
452 }
7bdee415 453
454 roce_set_bit(rc_sq_wqe->byte_4,
455 V2_RC_SEND_WQE_BYTE_4_FENCE_S,
456 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
457
458 roce_set_bit(rc_sq_wqe->byte_4,
459 V2_RC_SEND_WQE_BYTE_4_SE_S,
460 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
461
462 roce_set_bit(rc_sq_wqe->byte_4,
463 V2_RC_SEND_WQE_BYTE_4_CQE_S,
464 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
465
466 roce_set_bit(rc_sq_wqe->byte_4,
467 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
468
384f8818 469 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
7bdee415 470 switch (wr->opcode) {
471 case IB_WR_RDMA_READ:
b9c1ea40 472 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
7bdee415 473 rc_sq_wqe->rkey =
474 cpu_to_le32(rdma_wr(wr)->rkey);
475 rc_sq_wqe->va =
476 cpu_to_le64(rdma_wr(wr)->remote_addr);
477 break;
478 case IB_WR_RDMA_WRITE:
b9c1ea40 479 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
7bdee415 480 rc_sq_wqe->rkey =
481 cpu_to_le32(rdma_wr(wr)->rkey);
482 rc_sq_wqe->va =
483 cpu_to_le64(rdma_wr(wr)->remote_addr);
484 break;
485 case IB_WR_RDMA_WRITE_WITH_IMM:
b9c1ea40 486 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
7bdee415 487 rc_sq_wqe->rkey =
488 cpu_to_le32(rdma_wr(wr)->rkey);
489 rc_sq_wqe->va =
490 cpu_to_le64(rdma_wr(wr)->remote_addr);
491 break;
492 case IB_WR_SEND:
b9c1ea40 493 hr_op = HNS_ROCE_V2_WQE_OP_SEND;
7bdee415 494 break;
495 case IB_WR_SEND_WITH_INV:
b9c1ea40 496 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
7bdee415 497 break;
498 case IB_WR_SEND_WITH_IMM:
b9c1ea40 499 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
7bdee415 500 break;
501 case IB_WR_LOCAL_INV:
b9c1ea40 502 hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
e93df010
LO		 503 roce_set_bit(rc_sq_wqe->byte_4,
504 V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
505 rc_sq_wqe->inv_key =
506 cpu_to_le32(wr->ex.invalidate_rkey);
7bdee415 507 break;
68a997c5
YL		 508 case IB_WR_REG_MR:
509 hr_op = HNS_ROCE_V2_WQE_OP_FAST_REG_PMR;
510 fseg = wqe;
511 set_frmr_seg(rc_sq_wqe, fseg, reg_wr(wr));
512 break;
7bdee415 513 case IB_WR_ATOMIC_CMP_AND_SWP:
b9c1ea40 514 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
384f8818
LO		 515 rc_sq_wqe->rkey =
516 cpu_to_le32(atomic_wr(wr)->rkey);
517 rc_sq_wqe->va =
d9581bf3 518 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 519 break;
520 case IB_WR_ATOMIC_FETCH_AND_ADD:
b9c1ea40 521 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
384f8818
LO		 522 rc_sq_wqe->rkey =
523 cpu_to_le32(atomic_wr(wr)->rkey);
524 rc_sq_wqe->va =
d9581bf3 525 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 526 break;
527 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
b9c1ea40
LO		 528 hr_op =
529 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
7bdee415 530 break;
531 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
b9c1ea40
LO		 532 hr_op =
533 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
7bdee415 534 break;
535 default:
b9c1ea40 536 hr_op = HNS_ROCE_V2_WQE_OP_MASK;
7bdee415 537 break;
2d407888
WHX		 538 }
539
b9c1ea40
LO		 540 roce_set_field(rc_sq_wqe->byte_4,
541 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
542 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
2d407888 543
d9581bf3
LO		 544 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
545 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
546 struct hns_roce_v2_wqe_data_seg *dseg;
547
548 dseg = wqe;
549 set_data_seg_v2(dseg, wr->sg_list);
550 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
551 set_atomic_seg(wqe, atomic_wr(wr));
552 roce_set_field(rc_sq_wqe->byte_16,
553 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
554 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
555 wr->num_sge);
68a997c5 556 } else if (wr->opcode != IB_WR_REG_MR) {
d9581bf3
LO		 557 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe,
558 wqe, &sge_ind, bad_wr);
559 if (ret)
560 goto out;
561 }
562
7bdee415 563 ind++;
2d407888 564 } else {
7bdee415 565 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
566 spin_unlock_irqrestore(&qp->sq.lock, flags);
137ae320 567 *bad_wr = wr;
7bdee415 568 return -EOPNOTSUPP;
2d407888 569 }
2d407888
WHX		 570 }
571
572out:
573 if (likely(nreq)) {
574 qp->sq.head += nreq;
575 /* Memory barrier */
576 wmb();
577
578 sq_db.byte_4 = 0;
579 sq_db.parameter = 0;
580
581 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
582 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
583 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
584 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
cc3391cb 585 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
586 V2_DB_PARAMETER_IDX_S,
2d407888
WHX		 587 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
588 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
589 V2_DB_PARAMETER_SL_S, qp->sl);
590
d3743fa9 591 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l);
2d407888
WHX		 592
593 qp->sq_next_wqe = ind;
594 qp->next_sge = sge_ind;
0425e3e6
YL		 595
596 if (qp->state == IB_QPS_ERR) {
597 attr_mask = IB_QP_STATE;
598 attr.qp_state = IB_QPS_ERR;
599
600 ret = hns_roce_v2_modify_qp(&qp->ibqp, &attr, attr_mask,
601 qp->state, IB_QPS_ERR);
602 if (ret) {
603 spin_unlock_irqrestore(&qp->sq.lock, flags);
604 *bad_wr = wr;
605 return ret;
606 }
607 }
2d407888
WHX		 608 }
609
610 spin_unlock_irqrestore(&qp->sq.lock, flags);
611
612 return ret;
613}
614
d34ac5cd
BVA		 615static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
616 const struct ib_recv_wr *wr,
617 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 618{
619 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
620 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
621 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 622 struct hns_roce_rinl_sge *sge_list;
2d407888 623 struct device *dev = hr_dev->dev;
0425e3e6 624 struct ib_qp_attr attr;
2d407888
WHX		 625 unsigned long flags;
626 void *wqe = NULL;
0425e3e6 627 int attr_mask;
2d407888
WHX		 628 int ret = 0;
629 int nreq;
630 int ind;
631 int i;
632
633 spin_lock_irqsave(&hr_qp->rq.lock, flags);
634 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
635
ced07769 636 if (hr_qp->state == IB_QPS_RESET) {
2d407888
WHX		 637 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
638 *bad_wr = wr;
639 return -EINVAL;
640 }
641
642 for (nreq = 0; wr; ++nreq, wr = wr->next) {
643 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
644 hr_qp->ibqp.recv_cq)) {
645 ret = -ENOMEM;
646 *bad_wr = wr;
647 goto out;
648 }
649
650 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
651 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
652 wr->num_sge, hr_qp->rq.max_gs);
653 ret = -EINVAL;
654 *bad_wr = wr;
655 goto out;
656 }
657
658 wqe = get_recv_wqe(hr_qp, ind);
659 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
660 for (i = 0; i < wr->num_sge; i++) {
661 if (!wr->sg_list[i].length)
662 continue;
663 set_data_seg_v2(dseg, wr->sg_list + i);
664 dseg++;
665 }
666
667 if (i < hr_qp->rq.max_gs) {
778cc5a8 668 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
669 dseg->addr = 0;
2d407888
WHX		 670 }
671
0009c2db 672 /* rq support inline data */
ecaaf1e2 673 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
674 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
675 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
676 (u32)wr->num_sge;
677 for (i = 0; i < wr->num_sge; i++) {
678 sge_list[i].addr =
679 (void *)(u64)wr->sg_list[i].addr;
680 sge_list[i].len = wr->sg_list[i].length;
681 }
0009c2db 682 }
683
2d407888
WHX		 684 hr_qp->rq.wrid[ind] = wr->wr_id;
685
686 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
687 }
688
689out:
690 if (likely(nreq)) {
691 hr_qp->rq.head += nreq;
692 /* Memory barrier */
693 wmb();
694
472bc0fb 695 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
0425e3e6
YL		 696
697 if (hr_qp->state == IB_QPS_ERR) {
698 attr_mask = IB_QP_STATE;
699 attr.qp_state = IB_QPS_ERR;
700
701 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr,
702 attr_mask, hr_qp->state,
703 IB_QPS_ERR);
704 if (ret) {
705 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
706 *bad_wr = wr;
707 return ret;
708 }
709 }
2d407888
WHX		 710 }
711 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
712
713 return ret;
714}
715
6a04aed6
WHX		 716static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
717 unsigned long instance_stage,
718 unsigned long reset_stage)
719{
720 /* When hardware reset has been completed once or more, we should stop
d3743fa9 721 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
6a04aed6
WHX		 722 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
723 * stage of soft reset process, we should exit with error, and then
724 * HNAE3_INIT_CLIENT related process can rollback the operation like
725 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
726 * process will exit with error to notify NIC driver to reschedule soft
727 * reset process once again.
728 */
729 hr_dev->is_reset = true;
d3743fa9 730 hr_dev->dis_db = true;
6a04aed6
WHX		 731
732 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
733 instance_stage == HNS_ROCE_STATE_INIT)
734 return CMD_RST_PRC_EBUSY;
735
736 return CMD_RST_PRC_SUCCESS;
737}
738
739static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
740 unsigned long instance_stage,
741 unsigned long reset_stage)
742{
743 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
744 struct hnae3_handle *handle = priv->handle;
745 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
746
d3743fa9
WHX		 747 /* When hardware reset is detected, we should stop sending mailbox&cmq&
748 * doorbell to hardware. If now in .init_instance() function, we should
6a04aed6
WHX		 749 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
750 * process, we should exit with error, and then HNAE3_INIT_CLIENT
751 * related process can rollback the operation like notifing hardware to
752 * free resources, HNAE3_INIT_CLIENT related process will exit with
753 * error to notify NIC driver to reschedule soft reset process once
754 * again.
755 */
d3743fa9 756 hr_dev->dis_db = true;
6a04aed6
WHX		 757 if (!ops->get_hw_reset_stat(handle))
758 hr_dev->is_reset = true;
759
760 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
761 instance_stage == HNS_ROCE_STATE_INIT)
762 return CMD_RST_PRC_EBUSY;
763
764 return CMD_RST_PRC_SUCCESS;
765}
766
767static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
768{
769 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
770 struct hnae3_handle *handle = priv->handle;
771 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
772
773 /* When software reset is detected at .init_instance() function, we
d3743fa9
WHX		 774 * should stop sending mailbox&cmq&doorbell to hardware, and exit
775 * with error.
6a04aed6 776 */
d3743fa9 777 hr_dev->dis_db = true;
6a04aed6
WHX		 778 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
779 hr_dev->is_reset = true;
780
781 return CMD_RST_PRC_EBUSY;
782}
783
784static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
785{
786 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
787 struct hnae3_handle *handle = priv->handle;
788 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
789 unsigned long instance_stage; /* the current instance stage */
790 unsigned long reset_stage; /* the current reset stage */
791 unsigned long reset_cnt;
792 bool sw_resetting;
793 bool hw_resetting;
794
795 if (hr_dev->is_reset)
796 return CMD_RST_PRC_SUCCESS;
797
798 /* Get information about reset from NIC driver or RoCE driver itself,
799 * the meaning of the following variables from NIC driver are described
800 * as below:
801 * reset_cnt -- The count value of completed hardware reset.
802 * hw_resetting -- Whether hardware device is resetting now.
803 * sw_resetting -- Whether NIC's software reset process is running now.
804 */
805 instance_stage = handle->rinfo.instance_state;
806 reset_stage = handle->rinfo.reset_state;
807 reset_cnt = ops->ae_dev_reset_cnt(handle);
808 hw_resetting = ops->get_hw_reset_stat(handle);
809 sw_resetting = ops->ae_dev_resetting(handle);
810
811 if (reset_cnt != hr_dev->reset_cnt)
812 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
813 reset_stage);
814 else if (hw_resetting)
815 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
816 reset_stage);
817 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
818 return hns_roce_v2_cmd_sw_resetting(hr_dev);
819
820 return 0;
821}
822
a04ff739
WHX		 823static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
824{
825 int ntu = ring->next_to_use;
826 int ntc = ring->next_to_clean;
827 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
828
829 return ring->desc_num - used - 1;
830}
831
832static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
833 struct hns_roce_v2_cmq_ring *ring)
834{
835 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
836
837 ring->desc = kzalloc(size, GFP_KERNEL);
838 if (!ring->desc)
839 return -ENOMEM;
840
841 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
842 DMA_BIDIRECTIONAL);
843 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
844 ring->desc_dma_addr = 0;
845 kfree(ring->desc);
846 ring->desc = NULL;
847 return -ENOMEM;
848 }
849
850 return 0;
851}
852
853static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
854 struct hns_roce_v2_cmq_ring *ring)
855{
856 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
857 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
858 DMA_BIDIRECTIONAL);
90e7a4d5 859
860 ring->desc_dma_addr = 0;
a04ff739
WHX		 861 kfree(ring->desc);
862}
863
864static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
865{
866 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
867 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
868 &priv->cmq.csq : &priv->cmq.crq;
869
870 ring->flag = ring_type;
871 ring->next_to_clean = 0;
872 ring->next_to_use = 0;
873
874 return hns_roce_alloc_cmq_desc(hr_dev, ring);
875}
876
877static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
878{
879 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
880 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
881 &priv->cmq.csq : &priv->cmq.crq;
882 dma_addr_t dma = ring->desc_dma_addr;
883
884 if (ring_type == TYPE_CSQ) {
885 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
886 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
887 upper_32_bits(dma));
888 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
889 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
890 HNS_ROCE_CMQ_ENABLE);
891 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
892 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
893 } else {
894 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
895 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
896 upper_32_bits(dma));
897 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
898 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
899 HNS_ROCE_CMQ_ENABLE);
900 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
901 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
902 }
903}
904
905static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
906{
907 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
908 int ret;
909
910 /* Setup the queue entries for command queue */
426c4146
LO		 911 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
912 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 913
914 /* Setup the lock for command queue */
915 spin_lock_init(&priv->cmq.csq.lock);
916 spin_lock_init(&priv->cmq.crq.lock);
917
918 /* Setup Tx write back timeout */
919 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
920
921 /* Init CSQ */
922 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
923 if (ret) {
924 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
925 return ret;
926 }
927
928 /* Init CRQ */
929 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
930 if (ret) {
931 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
932 goto err_crq;
933 }
934
935 /* Init CSQ REG */
936 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
937
938 /* Init CRQ REG */
939 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
940
941 return 0;
942
943err_crq:
944 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
945
946 return ret;
947}
948
949static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
950{
951 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
952
953 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
954 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
955}
956
281d0ccf
CIK		 957static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
958 enum hns_roce_opcode_type opcode,
959 bool is_read)
a04ff739
WHX		 960{
961 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
962 desc->opcode = cpu_to_le16(opcode);
963 desc->flag =
964 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
965 if (is_read)
966 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
967 else
968 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
969}
970
971static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
972{
973 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
974 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
975
976 return head == priv->cmq.csq.next_to_use;
977}
978
979static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
980{
981 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
982 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
983 struct hns_roce_cmq_desc *desc;
984 u16 ntc = csq->next_to_clean;
985 u32 head;
986 int clean = 0;
987
988 desc = &csq->desc[ntc];
989 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
990 while (head != ntc) {
991 memset(desc, 0, sizeof(*desc));
992 ntc++;
993 if (ntc == csq->desc_num)
994 ntc = 0;
995 desc = &csq->desc[ntc];
996 clean++;
997 }
998 csq->next_to_clean = ntc;
999
1000 return clean;
1001}
1002
6a04aed6
WHX		 1003static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1004 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 1005{
1006 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1007 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1008 struct hns_roce_cmq_desc *desc_to_use;
1009 bool complete = false;
1010 u32 timeout = 0;
1011 int handle = 0;
1012 u16 desc_ret;
1013 int ret = 0;
1014 int ntc;
1015
1016 spin_lock_bh(&csq->lock);
1017
1018 if (num > hns_roce_cmq_space(csq)) {
1019 spin_unlock_bh(&csq->lock);
1020 return -EBUSY;
1021 }
1022
1023 /*
1024 * Record the location of desc in the cmq for this time
1025 * which will be use for hardware to write back
1026 */
1027 ntc = csq->next_to_use;
1028
1029 while (handle < num) {
1030 desc_to_use = &csq->desc[csq->next_to_use];
1031 *desc_to_use = desc[handle];
1032 dev_dbg(hr_dev->dev, "set cmq desc:\n");
1033 csq->next_to_use++;
1034 if (csq->next_to_use == csq->desc_num)
1035 csq->next_to_use = 0;
1036 handle++;
1037 }
1038
1039 /* Write to hardware */
1040 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
1041
1042 /*
1043 * If the command is sync, wait for the firmware to write back,
1044 * if multi descriptors to be sent, use the first one to check
1045 */
1046 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
1047 do {
1048 if (hns_roce_cmq_csq_done(hr_dev))
1049 break;
988e175b 1050 udelay(1);
a04ff739
WHX		 1051 timeout++;
1052 } while (timeout < priv->cmq.tx_timeout);
1053 }
1054
1055 if (hns_roce_cmq_csq_done(hr_dev)) {
1056 complete = true;
1057 handle = 0;
1058 while (handle < num) {
1059 /* get the result of hardware write back */
1060 desc_to_use = &csq->desc[ntc];
1061 desc[handle] = *desc_to_use;
1062 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
1063 desc_ret = desc[handle].retval;
1064 if (desc_ret == CMD_EXEC_SUCCESS)
1065 ret = 0;
1066 else
1067 ret = -EIO;
1068 priv->cmq.last_status = desc_ret;
1069 ntc++;
1070 handle++;
1071 if (ntc == csq->desc_num)
1072 ntc = 0;
1073 }
1074 }
1075
1076 if (!complete)
1077 ret = -EAGAIN;
1078
1079 /* clean the command send queue */
1080 handle = hns_roce_cmq_csq_clean(hr_dev);
1081 if (handle != num)
1082 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
1083 handle, num);
1084
1085 spin_unlock_bh(&csq->lock);
1086
1087 return ret;
1088}
1089
e95e52a1 1090static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
6a04aed6
WHX		 1091 struct hns_roce_cmq_desc *desc, int num)
1092{
1093 int retval;
1094 int ret;
1095
1096 ret = hns_roce_v2_rst_process_cmd(hr_dev);
1097 if (ret == CMD_RST_PRC_SUCCESS)
1098 return 0;
1099 if (ret == CMD_RST_PRC_EBUSY)
1100 return ret;
1101
1102 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1103 if (ret) {
1104 retval = hns_roce_v2_rst_process_cmd(hr_dev);
1105 if (retval == CMD_RST_PRC_SUCCESS)
1106 return 0;
1107 else if (retval == CMD_RST_PRC_EBUSY)
1108 return retval;
1109 }
1110
1111 return ret;
1112}
1113
281d0ccf 1114static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 1115{
1116 struct hns_roce_query_version *resp;
1117 struct hns_roce_cmq_desc desc;
1118 int ret;
1119
1120 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1121 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1122 if (ret)
1123 return ret;
1124
1125 resp = (struct hns_roce_query_version *)desc.data;
1126 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 1127 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1128
1129 return 0;
1130}
1131
1132static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1133{
1134 struct hns_roce_query_fw_info *resp;
1135 struct hns_roce_cmq_desc desc;
1136 int ret;
1137
1138 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1139 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1140 if (ret)
1141 return ret;
1142
1143 resp = (struct hns_roce_query_fw_info *)desc.data;
1144 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1145
1146 return 0;
1147}
1148
1149static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1150{
1151 struct hns_roce_cfg_global_param *req;
1152 struct hns_roce_cmq_desc desc;
1153
1154 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1155 false);
1156
1157 req = (struct hns_roce_cfg_global_param *)desc.data;
1158 memset(req, 0, sizeof(*req));
1159 roce_set_field(req->time_cfg_udp_port,
1160 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1161 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1162 roce_set_field(req->time_cfg_udp_port,
1163 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1164 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1165
1166 return hns_roce_cmq_send(hr_dev, &desc, 1);
1167}
1168
1169static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1170{
1171 struct hns_roce_cmq_desc desc[2];
6b63597d 1172 struct hns_roce_pf_res_a *req_a;
1173 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1174 int ret;
1175 int i;
1176
1177 for (i = 0; i < 2; i++) {
1178 hns_roce_cmq_setup_basic_desc(&desc[i],
1179 HNS_ROCE_OPC_QUERY_PF_RES, true);
1180
1181 if (i == 0)
1182 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1183 else
1184 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1185 }
1186
1187 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1188 if (ret)
1189 return ret;
1190
6b63597d 1191 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1192 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1193
6b63597d 1194 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1195 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1196 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1197 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1198 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1199 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1200 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1201 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1202 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1203 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1204 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1205 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1206
6b63597d 1207 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1208 PF_RES_DATA_3_PF_SL_NUM_M,
1209 PF_RES_DATA_3_PF_SL_NUM_S);
6a157f7d
YL		 1210 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,
1211 PF_RES_DATA_4_PF_SCCC_BT_NUM_M,
1212 PF_RES_DATA_4_PF_SCCC_BT_NUM_S);
6b63597d 1213
cfc85f3e
WHX		 1214 return 0;
1215}
1216
0e40dc2f
YL		 1217static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
1218{
1219 struct hns_roce_pf_timer_res_a *req_a;
1220 struct hns_roce_cmq_desc desc[2];
1221 int ret, i;
1222
1223 for (i = 0; i < 2; i++) {
1224 hns_roce_cmq_setup_basic_desc(&desc[i],
1225 HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1226 true);
1227
1228 if (i == 0)
1229 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1230 else
1231 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1232 }
1233
1234 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1235 if (ret)
1236 return ret;
1237
1238 req_a = (struct hns_roce_pf_timer_res_a *)desc[0].data;
1239
1240 hr_dev->caps.qpc_timer_bt_num =
1241 roce_get_field(req_a->qpc_timer_bt_idx_num,
1242 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
1243 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
1244 hr_dev->caps.cqc_timer_bt_num =
1245 roce_get_field(req_a->cqc_timer_bt_idx_num,
1246 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
1247 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
1248
1249 return 0;
1250}
1251
0c1c3880
LO		 1252static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1253 int vf_id)
1254{
1255 struct hns_roce_cmq_desc desc;
1256 struct hns_roce_vf_switch *swt;
1257 int ret;
1258
1259 swt = (struct hns_roce_vf_switch *)desc.data;
1260 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1261 swt->rocee_sel |= cpu_to_le16(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1262 roce_set_field(swt->fun_id,
1263 VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1264 VF_SWITCH_DATA_FUN_ID_VF_ID_S,
1265 vf_id);
1266 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1267 if (ret)
1268 return ret;
1269 desc.flag =
1270 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1271 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1272 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
1273 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 1);
1274 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1275
1276 return hns_roce_cmq_send(hr_dev, &desc, 1);
1277}
1278
cfc85f3e
WHX		 1279static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1280{
1281 struct hns_roce_cmq_desc desc[2];
1282 struct hns_roce_vf_res_a *req_a;
1283 struct hns_roce_vf_res_b *req_b;
1284 int i;
1285
1286 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1287 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1288 memset(req_a, 0, sizeof(*req_a));
1289 memset(req_b, 0, sizeof(*req_b));
1290 for (i = 0; i < 2; i++) {
1291 hns_roce_cmq_setup_basic_desc(&desc[i],
1292 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1293
1294 if (i == 0)
1295 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1296 else
1297 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1298
1299 if (i == 0) {
1300 roce_set_field(req_a->vf_qpc_bt_idx_num,
1301 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1302 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1303 roce_set_field(req_a->vf_qpc_bt_idx_num,
1304 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1305 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
1306 HNS_ROCE_VF_QPC_BT_NUM);
1307
1308 roce_set_field(req_a->vf_srqc_bt_idx_num,
1309 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1310 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1311 roce_set_field(req_a->vf_srqc_bt_idx_num,
1312 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1313 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1314 HNS_ROCE_VF_SRQC_BT_NUM);
1315
1316 roce_set_field(req_a->vf_cqc_bt_idx_num,
1317 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1318 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1319 roce_set_field(req_a->vf_cqc_bt_idx_num,
1320 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1321 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
1322 HNS_ROCE_VF_CQC_BT_NUM);
1323
1324 roce_set_field(req_a->vf_mpt_bt_idx_num,
1325 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1326 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1327 roce_set_field(req_a->vf_mpt_bt_idx_num,
1328 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1329 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
1330 HNS_ROCE_VF_MPT_BT_NUM);
1331
1332 roce_set_field(req_a->vf_eqc_bt_idx_num,
1333 VF_RES_A_DATA_5_VF_EQC_IDX_M,
1334 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1335 roce_set_field(req_a->vf_eqc_bt_idx_num,
1336 VF_RES_A_DATA_5_VF_EQC_NUM_M,
1337 VF_RES_A_DATA_5_VF_EQC_NUM_S,
1338 HNS_ROCE_VF_EQC_NUM);
1339 } else {
1340 roce_set_field(req_b->vf_smac_idx_num,
1341 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1342 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1343 roce_set_field(req_b->vf_smac_idx_num,
1344 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1345 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
1346 HNS_ROCE_VF_SMAC_NUM);
1347
1348 roce_set_field(req_b->vf_sgid_idx_num,
1349 VF_RES_B_DATA_2_VF_SGID_IDX_M,
1350 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1351 roce_set_field(req_b->vf_sgid_idx_num,
1352 VF_RES_B_DATA_2_VF_SGID_NUM_M,
1353 VF_RES_B_DATA_2_VF_SGID_NUM_S,
1354 HNS_ROCE_VF_SGID_NUM);
1355
1356 roce_set_field(req_b->vf_qid_idx_sl_num,
1357 VF_RES_B_DATA_3_VF_QID_IDX_M,
1358 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1359 roce_set_field(req_b->vf_qid_idx_sl_num,
1360 VF_RES_B_DATA_3_VF_SL_NUM_M,
1361 VF_RES_B_DATA_3_VF_SL_NUM_S,
1362 HNS_ROCE_VF_SL_NUM);
6a157f7d
YL		 1363
1364 roce_set_field(req_b->vf_sccc_idx_num,
1365 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,
1366 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);
1367 roce_set_field(req_b->vf_sccc_idx_num,
1368 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,
1369 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,
1370 HNS_ROCE_VF_SCCC_BT_NUM);
cfc85f3e
WHX		 1371 }
1372 }
1373
1374 return hns_roce_cmq_send(hr_dev, desc, 2);
1375}
1376
a81fba28
WHX		 1377static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1378{
1379 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1380 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1381 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1382 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
6a157f7d 1383 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;
a81fba28
WHX		 1384 struct hns_roce_cfg_bt_attr *req;
1385 struct hns_roce_cmq_desc desc;
1386
1387 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1388 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1389 memset(req, 0, sizeof(*req));
1390
1391 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1392 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1393 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1394 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1395 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1396 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1397 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1398 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1399 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1400
1401 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1402 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1403 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1404 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1405 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1406 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1407 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1408 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1409 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1410
1411 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1412 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1413 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1414 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1415 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1416 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1417 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1418 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1419 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1420
1421 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1422 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1423 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1424 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1425 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1426 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1427 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1428 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1429 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1430
6a157f7d
YL		 1431 roce_set_field(req->vf_sccc_cfg,
1432 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,
1433 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,
1434 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1435 roce_set_field(req->vf_sccc_cfg,
1436 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,
1437 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,
1438 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1439 roce_set_field(req->vf_sccc_cfg,
1440 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,
1441 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,
1442 sccc_hop_num ==
1443 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);
1444
a81fba28
WHX		 1445 return hns_roce_cmq_send(hr_dev, &desc, 1);
1446}
1447
cfc85f3e
WHX		 1448static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1449{
1450 struct hns_roce_caps *caps = &hr_dev->caps;
1451 int ret;
1452
1453 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 1454 if (ret) {
1455 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
1456 ret);
1457 return ret;
1458 }
1459
1460 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 1461 if (ret) {
1462 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1463 ret);
1464 return ret;
1465 }
1466
1467 ret = hns_roce_config_global_param(hr_dev);
1468 if (ret) {
1469 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1470 ret);
2349fdd4 1471 return ret;
cfc85f3e
WHX		 1472 }
1473
1474 /* Get pf resource owned by every pf */
1475 ret = hns_roce_query_pf_resource(hr_dev);
1476 if (ret) {
1477 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1478 ret);
1479 return ret;
1480 }
1481
0e40dc2f
YL		 1482 if (hr_dev->pci_dev->revision == 0x21) {
1483 ret = hns_roce_query_pf_timer_resource(hr_dev);
1484 if (ret) {
1485 dev_err(hr_dev->dev,
1486 "Query pf timer resource fail, ret = %d.\n",
1487 ret);
1488 return ret;
1489 }
1490 }
1491
cfc85f3e
WHX		 1492 ret = hns_roce_alloc_vf_resource(hr_dev);
1493 if (ret) {
1494 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
1495 ret);
1496 return ret;
1497 }
1498
0c1c3880
LO		 1499 if (hr_dev->pci_dev->revision == 0x21) {
1500 ret = hns_roce_set_vf_switch_param(hr_dev, 0);
1501 if (ret) {
1502 dev_err(hr_dev->dev,
1503 "Set function switch param fail, ret = %d.\n",
1504 ret);
1505 return ret;
1506 }
1507 }
3a63c964
LO		 1508
1509 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
1510 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e
WHX		 1511
1512 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1513 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1514 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
5c1f167a 1515 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
704e0e61 1516 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
cfc85f3e 1517 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
5c1f167a 1518 caps->max_srqwqes = HNS_ROCE_V2_MAX_SRQWQE_NUM;
cfc85f3e 1519 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
05ad5482 1520 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
cfc85f3e
WHX		 1521 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1522 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
5c1f167a 1523 caps->max_srq_sg = HNS_ROCE_V2_MAX_SRQ_SGE_NUM;
cfc85f3e
WHX		 1524 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1525 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
a5073d60
YL		 1526 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1527 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1528 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
cfc85f3e
WHX		 1529 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1530 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1531 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
5c1f167a
LO		 1532 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1533 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
cfc85f3e
WHX		 1534 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1535 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1536 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1537 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1538 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1539 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1540 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1541 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 1542 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e 1543 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
5c1f167a 1544 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
cfc85f3e
WHX		 1545 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1546 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
5c1f167a 1547 caps->idx_entry_sz = 4;
cfc85f3e
WHX		 1548 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1549 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1550 caps->reserved_lkey = 0;
1551 caps->reserved_pds = 0;
1552 caps->reserved_mrws = 1;
1553 caps->reserved_uars = 0;
1554 caps->reserved_cqs = 0;
5c1f167a 1555 caps->reserved_srqs = 0;
06ef0ee4 1556 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
cfc85f3e 1557
a25d13cb
SX		 1558 caps->qpc_ba_pg_sz = 0;
1559 caps->qpc_buf_pg_sz = 0;
1560 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1561 caps->srqc_ba_pg_sz = 0;
1562 caps->srqc_buf_pg_sz = 0;
1563 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
1564 caps->cqc_ba_pg_sz = 0;
1565 caps->cqc_buf_pg_sz = 0;
1566 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1567 caps->mpt_ba_pg_sz = 0;
1568 caps->mpt_buf_pg_sz = 0;
1569 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
91fb4d83 1570 caps->pbl_ba_pg_sz = 2;
ff795f71
WHX		 1571 caps->pbl_buf_pg_sz = 0;
1572 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 1573 caps->mtt_ba_pg_sz = 0;
1574 caps->mtt_buf_pg_sz = 0;
1575 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1576 caps->cqe_ba_pg_sz = 0;
1577 caps->cqe_buf_pg_sz = 0;
1578 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
c7bcb134
LO		 1579 caps->srqwqe_ba_pg_sz = 0;
1580 caps->srqwqe_buf_pg_sz = 0;
1581 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
1582 caps->idx_ba_pg_sz = 0;
1583 caps->idx_buf_pg_sz = 0;
1584 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
a5073d60
YL		 1585 caps->eqe_ba_pg_sz = 0;
1586 caps->eqe_buf_pg_sz = 0;
1587 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1588 caps->tsq_buf_pg_sz = 0;
29a1fe5d 1589 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 1590
023c1477 1591 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
0009c2db 1592 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
e088a685 1593 HNS_ROCE_CAP_FLAG_RQ_INLINE |
0425e3e6
YL		 1594 HNS_ROCE_CAP_FLAG_RECORD_DB |
1595 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
c7c28191
YL		 1596
1597 if (hr_dev->pci_dev->revision == 0x21)
68a997c5
YL		 1598 caps->flags |= HNS_ROCE_CAP_FLAG_MW |
1599 HNS_ROCE_CAP_FLAG_FRMR;
c7c28191 1600
cfc85f3e 1601 caps->pkey_table_len[0] = 1;
b5ff0f61 1602 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
a5073d60
YL		 1603 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1604 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
cfc85f3e
WHX		 1605 caps->local_ca_ack_delay = 0;
1606 caps->max_mtu = IB_MTU_4096;
1607
d16da119
LO		 1608 caps->max_srqs = HNS_ROCE_V2_MAX_SRQ;
1609 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1610 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1611
6a157f7d 1612 if (hr_dev->pci_dev->revision == 0x21) {
d16da119 1613 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC |
aa84fa18
YL		 1614 HNS_ROCE_CAP_FLAG_SRQ |
1615 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
1616
0e40dc2f
YL		 1617 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1618 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1619 caps->qpc_timer_ba_pg_sz = 0;
1620 caps->qpc_timer_buf_pg_sz = 0;
1621 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1622 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1623 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1624 caps->cqc_timer_ba_pg_sz = 0;
1625 caps->cqc_timer_buf_pg_sz = 0;
1626 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1627
6a157f7d
YL		 1628 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
1629 caps->sccc_ba_pg_sz = 0;
1630 caps->sccc_buf_pg_sz = 0;
1631 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
1632 }
384f8818 1633
a81fba28
WHX		 1634 ret = hns_roce_v2_set_bt(hr_dev);
1635 if (ret)
1636 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
1637 ret);
1638
1639 return ret;
cfc85f3e
WHX		 1640}
1641
6b63597d 1642static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
1643 enum hns_roce_link_table_type type)
1644{
1645 struct hns_roce_cmq_desc desc[2];
1646 struct hns_roce_cfg_llm_a *req_a =
1647 (struct hns_roce_cfg_llm_a *)desc[0].data;
1648 struct hns_roce_cfg_llm_b *req_b =
1649 (struct hns_roce_cfg_llm_b *)desc[1].data;
1650 struct hns_roce_v2_priv *priv = hr_dev->priv;
1651 struct hns_roce_link_table *link_tbl;
1652 struct hns_roce_link_table_entry *entry;
1653 enum hns_roce_opcode_type opcode;
1654 u32 page_num;
1655 int i;
1656
1657 switch (type) {
1658 case TSQ_LINK_TABLE:
1659 link_tbl = &priv->tsq;
1660 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
1661 break;
ded58ff9 1662 case TPQ_LINK_TABLE:
1663 link_tbl = &priv->tpq;
1664 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
1665 break;
6b63597d 1666 default:
1667 return -EINVAL;
1668 }
1669
1670 page_num = link_tbl->npages;
1671 entry = link_tbl->table.buf;
1672 memset(req_a, 0, sizeof(*req_a));
1673 memset(req_b, 0, sizeof(*req_b));
1674
1675 for (i = 0; i < 2; i++) {
1676 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
1677
1678 if (i == 0)
1679 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1680 else
1681 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1682
1683 if (i == 0) {
1684 req_a->base_addr_l = link_tbl->table.map & 0xffffffff;
1685 req_a->base_addr_h = (link_tbl->table.map >> 32) &
1686 0xffffffff;
1687 roce_set_field(req_a->depth_pgsz_init_en,
1688 CFG_LLM_QUE_DEPTH_M,
1689 CFG_LLM_QUE_DEPTH_S,
1690 link_tbl->npages);
1691 roce_set_field(req_a->depth_pgsz_init_en,
1692 CFG_LLM_QUE_PGSZ_M,
1693 CFG_LLM_QUE_PGSZ_S,
1694 link_tbl->pg_sz);
1695 req_a->head_ba_l = entry[0].blk_ba0;
1696 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr;
1697 roce_set_field(req_a->head_ptr,
1698 CFG_LLM_HEAD_PTR_M,
1699 CFG_LLM_HEAD_PTR_S, 0);
1700 } else {
1701 req_b->tail_ba_l = entry[page_num - 1].blk_ba0;
1702 roce_set_field(req_b->tail_ba_h,
1703 CFG_LLM_TAIL_BA_H_M,
1704 CFG_LLM_TAIL_BA_H_S,
1705 entry[page_num - 1].blk_ba1_nxt_ptr &
1706 HNS_ROCE_LINK_TABLE_BA1_M);
1707 roce_set_field(req_b->tail_ptr,
1708 CFG_LLM_TAIL_PTR_M,
1709 CFG_LLM_TAIL_PTR_S,
1710 (entry[page_num - 2].blk_ba1_nxt_ptr &
1711 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
1712 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
1713 }
1714 }
1715 roce_set_field(req_a->depth_pgsz_init_en,
1716 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1);
1717
1718 return hns_roce_cmq_send(hr_dev, desc, 2);
1719}
1720
1721static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
1722 enum hns_roce_link_table_type type)
1723{
1724 struct hns_roce_v2_priv *priv = hr_dev->priv;
1725 struct hns_roce_link_table *link_tbl;
1726 struct hns_roce_link_table_entry *entry;
1727 struct device *dev = hr_dev->dev;
1728 u32 buf_chk_sz;
1729 dma_addr_t t;
ded58ff9 1730 int func_num = 1;
6b63597d 1731 int pg_num_a;
1732 int pg_num_b;
1733 int pg_num;
1734 int size;
1735 int i;
1736
1737 switch (type) {
1738 case TSQ_LINK_TABLE:
1739 link_tbl = &priv->tsq;
1740 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
1741 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
1742 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
1743 break;
ded58ff9 1744 case TPQ_LINK_TABLE:
1745 link_tbl = &priv->tpq;
1746 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
1747 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
1748 pg_num_b = 2 * 4 * func_num + 2;
1749 break;
6b63597d 1750 default:
1751 return -EINVAL;
1752 }
1753
1754 pg_num = max(pg_num_a, pg_num_b);
1755 size = pg_num * sizeof(struct hns_roce_link_table_entry);
1756
1757 link_tbl->table.buf = dma_alloc_coherent(dev, size,
1758 &link_tbl->table.map,
1759 GFP_KERNEL);
1760 if (!link_tbl->table.buf)
1761 goto out;
1762
1763 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
1764 GFP_KERNEL);
1765 if (!link_tbl->pg_list)
1766 goto err_kcalloc_failed;
1767
1768 entry = link_tbl->table.buf;
1769 for (i = 0; i < pg_num; ++i) {
1770 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
1771 &t, GFP_KERNEL);
1772 if (!link_tbl->pg_list[i].buf)
1773 goto err_alloc_buf_failed;
1774
1775 link_tbl->pg_list[i].map = t;
1776 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz);
1777
1778 entry[i].blk_ba0 = (t >> 12) & 0xffffffff;
1779 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1780 HNS_ROCE_LINK_TABLE_BA1_M,
1781 HNS_ROCE_LINK_TABLE_BA1_S,
1782 t >> 44);
1783
1784 if (i < (pg_num - 1))
1785 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1786 HNS_ROCE_LINK_TABLE_NXT_PTR_M,
1787 HNS_ROCE_LINK_TABLE_NXT_PTR_S,
1788 i + 1);
1789 }
1790 link_tbl->npages = pg_num;
1791 link_tbl->pg_sz = buf_chk_sz;
1792
1793 return hns_roce_config_link_table(hr_dev, type);
1794
1795err_alloc_buf_failed:
1796 for (i -= 1; i >= 0; i--)
1797 dma_free_coherent(dev, buf_chk_sz,
1798 link_tbl->pg_list[i].buf,
1799 link_tbl->pg_list[i].map);
1800 kfree(link_tbl->pg_list);
1801
1802err_kcalloc_failed:
1803 dma_free_coherent(dev, size, link_tbl->table.buf,
1804 link_tbl->table.map);
1805
1806out:
1807 return -ENOMEM;
1808}
1809
1810static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
1811 struct hns_roce_link_table *link_tbl)
1812{
1813 struct device *dev = hr_dev->dev;
1814 int size;
1815 int i;
1816
1817 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
1818
1819 for (i = 0; i < link_tbl->npages; ++i)
1820 if (link_tbl->pg_list[i].buf)
1821 dma_free_coherent(dev, link_tbl->pg_sz,
1822 link_tbl->pg_list[i].buf,
1823 link_tbl->pg_list[i].map);
1824 kfree(link_tbl->pg_list);
1825
1826 dma_free_coherent(dev, size, link_tbl->table.buf,
1827 link_tbl->table.map);
1828}
1829
1830static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
1831{
ded58ff9 1832 struct hns_roce_v2_priv *priv = hr_dev->priv;
0e40dc2f
YL		 1833 int qpc_count, cqc_count;
1834 int ret, i;
6b63597d 1835
1836 /* TSQ includes SQ doorbell and ack doorbell */
1837 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 1838 if (ret) {
6b63597d 1839 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 1840 return ret;
1841 }
1842
1843 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
1844 if (ret) {
1845 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
1846 goto err_tpq_init_failed;
1847 }
1848
0e40dc2f
YL		 1849 /* Alloc memory for QPC Timer buffer space chunk*/
1850 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
1851 qpc_count++) {
1852 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
1853 qpc_count);
1854 if (ret) {
1855 dev_err(hr_dev->dev, "QPC Timer get failed\n");
1856 goto err_qpc_timer_failed;
1857 }
1858 }
1859
1860 /* Alloc memory for CQC Timer buffer space chunk*/
1861 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
1862 cqc_count++) {
1863 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
1864 cqc_count);
1865 if (ret) {
1866 dev_err(hr_dev->dev, "CQC Timer get failed\n");
1867 goto err_cqc_timer_failed;
1868 }
1869 }
1870
ded58ff9 1871 return 0;
1872
0e40dc2f
YL		 1873err_cqc_timer_failed:
1874 for (i = 0; i < cqc_count; i++)
1875 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
1876
1877err_qpc_timer_failed:
1878 for (i = 0; i < qpc_count; i++)
1879 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
1880
1881 hns_roce_free_link_table(hr_dev, &priv->tpq);
1882
ded58ff9 1883err_tpq_init_failed:
1884 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 1885
1886 return ret;
1887}
1888
1889static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
1890{
1891 struct hns_roce_v2_priv *priv = hr_dev->priv;
1892
ded58ff9 1893 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 1894 hns_roce_free_link_table(hr_dev, &priv->tsq);
1895}
1896
f747b689
LO		 1897static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
1898{
1899 struct hns_roce_cmq_desc desc;
1900 struct hns_roce_mbox_status *mb_st =
1901 (struct hns_roce_mbox_status *)desc.data;
1902 enum hns_roce_cmd_return_status status;
1903
1904 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
1905
1906 status = hns_roce_cmq_send(hr_dev, &desc, 1);
1907 if (status)
1908 return status;
1909
1910 return cpu_to_le32(mb_st->mb_status_hw_run);
1911}
1912
a680f2f3
WHX		 1913static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
1914{
f747b689 1915 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 1916
1917 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
1918}
1919
1920static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
1921{
f747b689 1922 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 1923
1924 return status & HNS_ROCE_HW_MB_STATUS_MASK;
1925}
1926
f747b689
LO		 1927static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
1928 u64 out_param, u32 in_modifier, u8 op_modifier,
1929 u16 op, u16 token, int event)
1930{
1931 struct hns_roce_cmq_desc desc;
1932 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
1933
1934 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
1935
1936 mb->in_param_l = cpu_to_le64(in_param);
1937 mb->in_param_h = cpu_to_le64(in_param) >> 32;
1938 mb->out_param_l = cpu_to_le64(out_param);
1939 mb->out_param_h = cpu_to_le64(out_param) >> 32;
1940 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
1941 mb->token_event_en = cpu_to_le32(event << 16 | token);
1942
1943 return hns_roce_cmq_send(hr_dev, &desc, 1);
1944}
1945
a680f2f3
WHX		 1946static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1947 u64 out_param, u32 in_modifier, u8 op_modifier,
1948 u16 op, u16 token, int event)
1949{
1950 struct device *dev = hr_dev->dev;
a680f2f3 1951 unsigned long end;
f747b689 1952 int ret;
a680f2f3
WHX		 1953
1954 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1955 while (hns_roce_v2_cmd_pending(hr_dev)) {
1956 if (time_after(jiffies, end)) {
1957 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1958 (int)end);
1959 return -EAGAIN;
1960 }
1961 cond_resched();
1962 }
1963
f747b689
LO		 1964 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
1965 op_modifier, op, token, event);
1966 if (ret)
1967 dev_err(dev, "Post mailbox fail(%d)\n", ret);
a680f2f3 1968
f747b689 1969 return ret;
a680f2f3
WHX		 1970}
1971
1972static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1973 unsigned long timeout)
1974{
1975 struct device *dev = hr_dev->dev;
1976 unsigned long end = 0;
1977 u32 status;
1978
1979 end = msecs_to_jiffies(timeout) + jiffies;
1980 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1981 cond_resched();
1982
1983 if (hns_roce_v2_cmd_pending(hr_dev)) {
1984 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1985 return -ETIMEDOUT;
1986 }
1987
1988 status = hns_roce_v2_cmd_complete(hr_dev);
1989 if (status != 0x1) {
6a04aed6
WHX		 1990 if (status == CMD_RST_PRC_EBUSY)
1991 return status;
1992
a680f2f3
WHX		 1993 dev_err(dev, "mailbox status 0x%x!\n", status);
1994 return -EBUSY;
1995 }
1996
1997 return 0;
1998}
1999
4db134a3 2000static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
2001 int gid_index, const union ib_gid *gid,
2002 enum hns_roce_sgid_type sgid_type)
2003{
2004 struct hns_roce_cmq_desc desc;
2005 struct hns_roce_cfg_sgid_tb *sgid_tb =
2006 (struct hns_roce_cfg_sgid_tb *)desc.data;
2007 u32 *p;
2008
2009 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2010
2011 roce_set_field(sgid_tb->table_idx_rsv,
2012 CFG_SGID_TB_TABLE_IDX_M,
2013 CFG_SGID_TB_TABLE_IDX_S, gid_index);
2014 roce_set_field(sgid_tb->vf_sgid_type_rsv,
2015 CFG_SGID_TB_VF_SGID_TYPE_M,
2016 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2017
2018 p = (u32 *)&gid->raw[0];
2019 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
2020
2021 p = (u32 *)&gid->raw[4];
2022 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
2023
2024 p = (u32 *)&gid->raw[8];
2025 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
2026
2027 p = (u32 *)&gid->raw[0xc];
2028 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
2029
2030 return hns_roce_cmq_send(hr_dev, &desc, 1);
2031}
2032
b5ff0f61 2033static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 2034 int gid_index, const union ib_gid *gid,
b5ff0f61 2035 const struct ib_gid_attr *attr)
7afddafa 2036{
b5ff0f61 2037 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 2038 int ret;
7afddafa 2039
b5ff0f61
WHX		 2040 if (!gid || !attr)
2041 return -EINVAL;
2042
2043 if (attr->gid_type == IB_GID_TYPE_ROCE)
2044 sgid_type = GID_TYPE_FLAG_ROCE_V1;
2045
2046 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2047 if (ipv6_addr_v4mapped((void *)gid))
2048 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
2049 else
2050 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
2051 }
2052
4db134a3 2053 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
2054 if (ret)
2055 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);
b5ff0f61 2056
4db134a3 2057 return ret;
7afddafa
WHX		 2058}
2059
a74dc41d
WHX		 2060static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
2061 u8 *addr)
7afddafa 2062{
e8e8b652 2063 struct hns_roce_cmq_desc desc;
2064 struct hns_roce_cfg_smac_tb *smac_tb =
2065 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 2066 u16 reg_smac_h;
2067 u32 reg_smac_l;
e8e8b652 2068
2069 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 2070
2071 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 2072 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 2073
e8e8b652 2074 memset(smac_tb, 0, sizeof(*smac_tb));
2075 roce_set_field(smac_tb->tb_idx_rsv,
2076 CFG_SMAC_TB_IDX_M,
2077 CFG_SMAC_TB_IDX_S, phy_port);
2078 roce_set_field(smac_tb->vf_smac_h_rsv,
2079 CFG_SMAC_TB_VF_SMAC_H_M,
2080 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
2081 smac_tb->vf_smac_l = reg_smac_l;
a74dc41d 2082
e8e8b652 2083 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 2084}
2085
ca088320
YL		 2086static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry,
2087 struct hns_roce_mr *mr)
3958cc56 2088{
3856ec55 2089 struct sg_dma_page_iter sg_iter;
db270c41 2090 u64 page_addr;
3958cc56 2091 u64 *pages;
3856ec55 2092 int i;
3958cc56 2093
ca088320
YL		 2094 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2095 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2096 roce_set_field(mpt_entry->byte_48_mode_ba,
2097 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
2098 upper_32_bits(mr->pbl_ba >> 3));
2099
2100 pages = (u64 *)__get_free_page(GFP_KERNEL);
2101 if (!pages)
2102 return -ENOMEM;
2103
2104 i = 0;
3856ec55
SS		 2105 for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
2106 page_addr = sg_page_iter_dma_address(&sg_iter);
2107 pages[i] = page_addr >> 6;
2108
2109 /* Record the first 2 entry directly to MTPT table */
2110 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
2111 goto found;
2112 i++;
ca088320
YL		 2113 }
2114found:
2115 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
2116 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
2117 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
2118
2119 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
2120 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
2121 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
2122 roce_set_field(mpt_entry->byte_64_buf_pa1,
2123 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2124 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2125 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2126
2127 free_page((unsigned long)pages);
2128
2129 return 0;
2130}
2131
2132static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
2133 unsigned long mtpt_idx)
2134{
2135 struct hns_roce_v2_mpt_entry *mpt_entry;
2136 int ret;
2137
3958cc56
WHX		 2138 mpt_entry = mb_buf;
2139 memset(mpt_entry, 0, sizeof(*mpt_entry));
2140
2141 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2142 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2143 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2144 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
2145 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
2146 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2147 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 2148 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2149 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 2150 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2151 V2_MPT_BYTE_4_PD_S, mr->pd);
3958cc56
WHX		 2152
2153 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
82342e49 2154 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0);
e93df010 2155 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 2156 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
2157 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 2158 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
2159 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 2160 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2161 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
2162 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2163 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
2164 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2165 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
3958cc56
WHX		 2166
2167 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
2168 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 2169 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
2170 1);
3958cc56
WHX		 2171
2172 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
2173 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
2174 mpt_entry->lkey = cpu_to_le32(mr->key);
2175 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
2176 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
2177
2178 if (mr->type == MR_TYPE_DMA)
2179 return 0;
2180
ca088320 2181 ret = set_mtpt_pbl(mpt_entry, mr);
3958cc56 2182
ca088320 2183 return ret;
3958cc56
WHX		 2184}
2185
a2c80b7b
WHX		 2186static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
2187 struct hns_roce_mr *mr, int flags,
2188 u32 pdn, int mr_access_flags, u64 iova,
2189 u64 size, void *mb_buf)
2190{
2191 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
ca088320 2192 int ret = 0;
a2c80b7b 2193
ab22bf05
YL		 2194 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2195 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2196
a2c80b7b
WHX		 2197 if (flags & IB_MR_REREG_PD) {
2198 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2199 V2_MPT_BYTE_4_PD_S, pdn);
2200 mr->pd = pdn;
2201 }
2202
2203 if (flags & IB_MR_REREG_ACCESS) {
2204 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2205 V2_MPT_BYTE_8_BIND_EN_S,
2206 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
2207 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
ca088320
YL		 2208 V2_MPT_BYTE_8_ATOMIC_EN_S,
2209 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
a2c80b7b 2210 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
ca088320 2211 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
a2c80b7b 2212 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
ca088320 2213 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
a2c80b7b 2214 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
ca088320 2215 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
a2c80b7b
WHX		 2216 }
2217
2218 if (flags & IB_MR_REREG_TRANS) {
2219 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
2220 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
2221 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
2222 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
2223
a2c80b7b
WHX		 2224 mr->iova = iova;
2225 mr->size = size;
ca088320
YL		 2226
2227 ret = set_mtpt_pbl(mpt_entry, mr);
a2c80b7b
WHX		 2228 }
2229
ca088320 2230 return ret;
a2c80b7b
WHX		 2231}
2232
68a997c5
YL		 2233static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
2234{
2235 struct hns_roce_v2_mpt_entry *mpt_entry;
2236
2237 mpt_entry = mb_buf;
2238 memset(mpt_entry, 0, sizeof(*mpt_entry));
2239
2240 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2241 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2242 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2243 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
2244 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2245 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2246 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2247 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2248 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2249 V2_MPT_BYTE_4_PD_S, mr->pd);
2250
2251 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
2252 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2253 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2254
2255 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
2256 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2257 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
2258 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2259
2260 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2261
2262 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2263 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
2264 V2_MPT_BYTE_48_PBL_BA_H_S,
2265 upper_32_bits(mr->pbl_ba >> 3));
2266
2267 roce_set_field(mpt_entry->byte_64_buf_pa1,
2268 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2269 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2270 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2271
2272 return 0;
2273}
2274
c7c28191
YL		 2275static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
2276{
2277 struct hns_roce_v2_mpt_entry *mpt_entry;
2278
2279 mpt_entry = mb_buf;
2280 memset(mpt_entry, 0, sizeof(*mpt_entry));
2281
2282 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2283 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2284 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2285 V2_MPT_BYTE_4_PD_S, mw->pdn);
2286 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2287 V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2288 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
2289 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ?
2290 0 : mw->pbl_hop_num);
2291 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2292 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2293 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2294 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2295
2296 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2297 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2298
2299 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2300 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
2301 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2302 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
2303 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2304
2305 roce_set_field(mpt_entry->byte_64_buf_pa1,
2306 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2307 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2308 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2309
2310 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2311
2312 return 0;
2313}
2314
93aa2187
WHX		 2315static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2316{
2317 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2318 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
2319}
2320
2321static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2322{
2323 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2324
2325 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2326 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
2327 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
2328}
2329
2330static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
2331{
2332 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
2333}
2334
c7bcb134
LO		 2335static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
2336{
2337 return hns_roce_buf_offset(&srq->buf, n << srq->wqe_shift);
2338}
2339
2340static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index)
2341{
2342 u32 bitmap_num;
2343 int bit_num;
2344
2345 /* always called with interrupts disabled. */
2346 spin_lock(&srq->lock);
2347
2348 bitmap_num = wqe_index / (sizeof(u64) * 8);
2349 bit_num = wqe_index % (sizeof(u64) * 8);
2350 srq->idx_que.bitmap[bitmap_num] |= (1ULL << bit_num);
2351 srq->tail++;
2352
2353 spin_unlock(&srq->lock);
2354}
2355
93aa2187
WHX		 2356static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2357{
86188a88 2358 *hr_cq->set_ci_db = cons_index & 0xffffff;
93aa2187
WHX		 2359}
2360
926a01dc
WHX		 2361static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2362 struct hns_roce_srq *srq)
2363{
2364 struct hns_roce_v2_cqe *cqe, *dest;
2365 u32 prod_index;
2366 int nfreed = 0;
c7bcb134 2367 int wqe_index;
926a01dc
WHX		 2368 u8 owner_bit;
2369
2370 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2371 ++prod_index) {
2372 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2373 break;
2374 }
2375
2376 /*
2377 * Now backwards through the CQ, removing CQ entries
2378 * that match our QP by overwriting them with next entries.
2379 */
2380 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2381 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2382 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2383 V2_CQE_BYTE_16_LCL_QPN_S) &
2384 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
c7bcb134
LO		 2385 if (srq &&
2386 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) {
2387 wqe_index = roce_get_field(cqe->byte_4,
2388 V2_CQE_BYTE_4_WQE_INDX_M,
2389 V2_CQE_BYTE_4_WQE_INDX_S);
2390 hns_roce_free_srq_wqe(srq, wqe_index);
2391 }
926a01dc
WHX		 2392 ++nfreed;
2393 } else if (nfreed) {
2394 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2395 hr_cq->ib_cq.cqe);
2396 owner_bit = roce_get_bit(dest->byte_4,
2397 V2_CQE_BYTE_4_OWNER_S);
2398 memcpy(dest, cqe, sizeof(*cqe));
2399 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2400 owner_bit);
2401 }
2402 }
2403
2404 if (nfreed) {
2405 hr_cq->cons_index += nfreed;
2406 /*
2407 * Make sure update of buffer contents is done before
2408 * updating consumer index.
2409 */
2410 wmb();
2411 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2412 }
2413}
2414
2415static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2416 struct hns_roce_srq *srq)
2417{
2418 spin_lock_irq(&hr_cq->lock);
2419 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2420 spin_unlock_irq(&hr_cq->lock);
2421}
2422
93aa2187
WHX		 2423static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2424 struct hns_roce_cq *hr_cq, void *mb_buf,
2425 u64 *mtts, dma_addr_t dma_handle, int nent,
2426 u32 vector)
2427{
2428 struct hns_roce_v2_cq_context *cq_context;
2429
2430 cq_context = mb_buf;
2431 memset(cq_context, 0, sizeof(*cq_context));
2432
2433 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2434 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2435 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2436 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187
WHX		 2437 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
2438 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
2439 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
2440 V2_CQC_BYTE_4_CEQN_S, vector);
2441 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
2442
2443 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2444 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2445
2446 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2447 cq_context->cqe_cur_blk_addr =
2448 cpu_to_le32(cq_context->cqe_cur_blk_addr);
2449
2450 roce_set_field(cq_context->byte_16_hop_addr,
2451 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2452 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
2453 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
2454 roce_set_field(cq_context->byte_16_hop_addr,
2455 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2456 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2457 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2458
2459 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
2460 roce_set_field(cq_context->byte_24_pgsz_addr,
2461 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2462 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
2463 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
2464 roce_set_field(cq_context->byte_24_pgsz_addr,
2465 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2466 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 2467 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2468 roce_set_field(cq_context->byte_24_pgsz_addr,
2469 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2470 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 2471 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2472
2473 cq_context->cqe_ba = (u32)(dma_handle >> 3);
2474
2475 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2476 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2477
9b44703d
YL		 2478 if (hr_cq->db_en)
2479 roce_set_bit(cq_context->byte_44_db_record,
2480 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
2481
2482 roce_set_field(cq_context->byte_44_db_record,
2483 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2484 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2485 ((u32)hr_cq->db.dma) >> 1);
2486 cq_context->db_record_addr = hr_cq->db.dma >> 32;
2487
a5073d60
YL		 2488 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2489 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2490 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2491 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2492 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2493 V2_CQC_BYTE_56_CQ_PERIOD_M,
2494 V2_CQC_BYTE_56_CQ_PERIOD_S,
2495 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2496}
2497
2498static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2499 enum ib_cq_notify_flags flags)
2500{
d3743fa9 2501 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 2502 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2503 u32 notification_flag;
2504 u32 doorbell[2];
2505
2506 doorbell[0] = 0;
2507 doorbell[1] = 0;
2508
2509 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2510 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2511 /*
2512 * flags = 0; Notification Flag = 1, next
2513 * flags = 1; Notification Flag = 0, solocited
2514 */
2515 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2516 hr_cq->cqn);
2517 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2518 HNS_ROCE_V2_CQ_DB_NTR);
2519 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2520 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2521 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2522 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2523 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2524 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2525 notification_flag);
2526
d3743fa9 2527 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l);
93aa2187
WHX		 2528
2529 return 0;
2530}
2531
0009c2db 2532static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2533 struct hns_roce_qp **cur_qp,
2534 struct ib_wc *wc)
2535{
2536 struct hns_roce_rinl_sge *sge_list;
2537 u32 wr_num, wr_cnt, sge_num;
2538 u32 sge_cnt, data_len, size;
2539 void *wqe_buf;
2540
2541 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2542 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2543 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2544
2545 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2546 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
2547 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt);
2548 data_len = wc->byte_len;
2549
2550 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2551 size = min(sge_list[sge_cnt].len, data_len);
2552 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2553
2554 data_len -= size;
2555 wqe_buf += size;
2556 }
2557
2558 if (data_len) {
2559 wc->status = IB_WC_LOC_LEN_ERR;
2560 return -EAGAIN;
2561 }
2562
2563 return 0;
2564}
2565
93aa2187
WHX		 2566static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2567 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2568{
c7bcb134 2569 struct hns_roce_srq *srq = NULL;
93aa2187
WHX		 2570 struct hns_roce_dev *hr_dev;
2571 struct hns_roce_v2_cqe *cqe;
2572 struct hns_roce_qp *hr_qp;
2573 struct hns_roce_wq *wq;
0425e3e6
YL		 2574 struct ib_qp_attr attr;
2575 int attr_mask;
93aa2187
WHX		 2576 int is_send;
2577 u16 wqe_ctr;
2578 u32 opcode;
2579 u32 status;
2580 int qpn;
0009c2db 2581 int ret;
93aa2187
WHX		 2582
2583 /* Find cqe according to consumer index */
2584 cqe = next_cqe_sw_v2(hr_cq);
2585 if (!cqe)
2586 return -EAGAIN;
2587
2588 ++hr_cq->cons_index;
2589 /* Memory barrier */
2590 rmb();
2591
2592 /* 0->SQ, 1->RQ */
2593 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2594
2595 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2596 V2_CQE_BYTE_16_LCL_QPN_S);
2597
2598 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2599 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2600 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2601 if (unlikely(!hr_qp)) {
2602 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
2603 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
2604 return -EINVAL;
2605 }
2606 *cur_qp = hr_qp;
2607 }
2608
2609 wc->qp = &(*cur_qp)->ibqp;
2610 wc->vendor_err = 0;
2611
c7bcb134
LO		 2612 if (is_send) {
2613 wq = &(*cur_qp)->sq;
2614 if ((*cur_qp)->sq_signal_bits) {
2615 /*
2616 * If sg_signal_bit is 1,
2617 * firstly tail pointer updated to wqe
2618 * which current cqe correspond to
2619 */
2620 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
2621 V2_CQE_BYTE_4_WQE_INDX_M,
2622 V2_CQE_BYTE_4_WQE_INDX_S);
2623 wq->tail += (wqe_ctr - (u16)wq->tail) &
2624 (wq->wqe_cnt - 1);
2625 }
2626
2627 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2628 ++wq->tail;
2629 } else if ((*cur_qp)->ibqp.srq) {
2630 srq = to_hr_srq((*cur_qp)->ibqp.srq);
2631 wqe_ctr = le16_to_cpu(roce_get_field(cqe->byte_4,
2632 V2_CQE_BYTE_4_WQE_INDX_M,
2633 V2_CQE_BYTE_4_WQE_INDX_S));
2634 wc->wr_id = srq->wrid[wqe_ctr];
2635 hns_roce_free_srq_wqe(srq, wqe_ctr);
2636 } else {
2637 /* Update tail pointer, record wr_id */
2638 wq = &(*cur_qp)->rq;
2639 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2640 ++wq->tail;
2641 }
2642
93aa2187
WHX		 2643 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
2644 V2_CQE_BYTE_4_STATUS_S);
2645 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
2646 case HNS_ROCE_CQE_V2_SUCCESS:
2647 wc->status = IB_WC_SUCCESS;
2648 break;
2649 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
2650 wc->status = IB_WC_LOC_LEN_ERR;
2651 break;
2652 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
2653 wc->status = IB_WC_LOC_QP_OP_ERR;
2654 break;
2655 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
2656 wc->status = IB_WC_LOC_PROT_ERR;
2657 break;
2658 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
2659 wc->status = IB_WC_WR_FLUSH_ERR;
2660 break;
2661 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
2662 wc->status = IB_WC_MW_BIND_ERR;
2663 break;
2664 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
2665 wc->status = IB_WC_BAD_RESP_ERR;
2666 break;
2667 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
2668 wc->status = IB_WC_LOC_ACCESS_ERR;
2669 break;
2670 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
2671 wc->status = IB_WC_REM_INV_REQ_ERR;
2672 break;
2673 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
2674 wc->status = IB_WC_REM_ACCESS_ERR;
2675 break;
2676 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
2677 wc->status = IB_WC_REM_OP_ERR;
2678 break;
2679 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
2680 wc->status = IB_WC_RETRY_EXC_ERR;
2681 break;
2682 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
2683 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2684 break;
2685 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
2686 wc->status = IB_WC_REM_ABORT_ERR;
2687 break;
2688 default:
2689 wc->status = IB_WC_GENERAL_ERR;
2690 break;
2691 }
2692
0425e3e6
YL		 2693 /* flush cqe if wc status is error, excluding flush error */
2694 if ((wc->status != IB_WC_SUCCESS) &&
2695 (wc->status != IB_WC_WR_FLUSH_ERR)) {
2696 attr_mask = IB_QP_STATE;
2697 attr.qp_state = IB_QPS_ERR;
2698 return hns_roce_v2_modify_qp(&(*cur_qp)->ibqp,
2699 &attr, attr_mask,
2700 (*cur_qp)->state, IB_QPS_ERR);
2701 }
2702
2703 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 2704 return 0;
2705
2706 if (is_send) {
2707 wc->wc_flags = 0;
2708 /* SQ corresponding to CQE */
2709 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2710 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
2711 case HNS_ROCE_SQ_OPCODE_SEND:
2712 wc->opcode = IB_WC_SEND;
2713 break;
2714 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
2715 wc->opcode = IB_WC_SEND;
2716 break;
2717 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
2718 wc->opcode = IB_WC_SEND;
2719 wc->wc_flags |= IB_WC_WITH_IMM;
2720 break;
2721 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
2722 wc->opcode = IB_WC_RDMA_READ;
2723 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2724 break;
2725 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
2726 wc->opcode = IB_WC_RDMA_WRITE;
2727 break;
2728 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
2729 wc->opcode = IB_WC_RDMA_WRITE;
2730 wc->wc_flags |= IB_WC_WITH_IMM;
2731 break;
2732 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
2733 wc->opcode = IB_WC_LOCAL_INV;
2734 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2735 break;
2736 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
2737 wc->opcode = IB_WC_COMP_SWAP;
2738 wc->byte_len = 8;
2739 break;
2740 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
2741 wc->opcode = IB_WC_FETCH_ADD;
2742 wc->byte_len = 8;
2743 break;
2744 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
2745 wc->opcode = IB_WC_MASKED_COMP_SWAP;
2746 wc->byte_len = 8;
2747 break;
2748 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
2749 wc->opcode = IB_WC_MASKED_FETCH_ADD;
2750 wc->byte_len = 8;
2751 break;
2752 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
2753 wc->opcode = IB_WC_REG_MR;
2754 break;
2755 case HNS_ROCE_SQ_OPCODE_BIND_MW:
2756 wc->opcode = IB_WC_REG_MR;
2757 break;
2758 default:
2759 wc->status = IB_WC_GENERAL_ERR;
2760 break;
2761 }
93aa2187
WHX		 2762 } else {
2763 /* RQ correspond to CQE */
2764 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2765
2766 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2767 V2_CQE_BYTE_4_OPCODE_S);
2768 switch (opcode & 0x1f) {
2769 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
2770 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2771 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2772 wc->ex.imm_data =
2773 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2774 break;
2775 case HNS_ROCE_V2_OPCODE_SEND:
2776 wc->opcode = IB_WC_RECV;
2777 wc->wc_flags = 0;
2778 break;
2779 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
2780 wc->opcode = IB_WC_RECV;
2781 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2782 wc->ex.imm_data =
2783 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2784 break;
2785 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
2786 wc->opcode = IB_WC_RECV;
2787 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 2788 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 2789 break;
2790 default:
2791 wc->status = IB_WC_GENERAL_ERR;
2792 break;
2793 }
2794
0009c2db 2795 if ((wc->qp->qp_type == IB_QPT_RC ||
2796 wc->qp->qp_type == IB_QPT_UC) &&
2797 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
2798 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
2799 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
2800 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
2801 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
2802 if (ret)
2803 return -EAGAIN;
2804 }
2805
93aa2187
WHX		 2806 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
2807 V2_CQE_BYTE_32_SL_S);
2808 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
2809 V2_CQE_BYTE_32_RMT_QPN_M,
2810 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 2811 wc->slid = 0;
93aa2187
WHX		 2812 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
2813 V2_CQE_BYTE_32_GRH_S) ?
2814 IB_WC_GRH : 0);
6c1f08b3 2815 wc->port_num = roce_get_field(cqe->byte_32,
2816 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
2817 wc->pkey_index = 0;
2eade675 2818 memcpy(wc->smac, cqe->smac, 4);
2819 wc->smac[4] = roce_get_field(cqe->byte_28,
2820 V2_CQE_BYTE_28_SMAC_4_M,
2821 V2_CQE_BYTE_28_SMAC_4_S);
2822 wc->smac[5] = roce_get_field(cqe->byte_28,
2823 V2_CQE_BYTE_28_SMAC_5_M,
2824 V2_CQE_BYTE_28_SMAC_5_S);
944e6409
LO		 2825 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
2826 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
2827 V2_CQE_BYTE_28_VID_M,
2828 V2_CQE_BYTE_28_VID_S);
2829 } else {
2830 wc->vlan_id = 0xffff;
2831 }
2832
2eade675 2833 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
2834 wc->network_hdr_type = roce_get_field(cqe->byte_28,
2835 V2_CQE_BYTE_28_PORT_TYPE_M,
2836 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 2837 }
2838
2839 return 0;
2840}
2841
2842static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
2843 struct ib_wc *wc)
2844{
2845 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2846 struct hns_roce_qp *cur_qp = NULL;
2847 unsigned long flags;
2848 int npolled;
2849
2850 spin_lock_irqsave(&hr_cq->lock, flags);
2851
2852 for (npolled = 0; npolled < num_entries; ++npolled) {
2853 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
2854 break;
2855 }
2856
2857 if (npolled) {
2858 /* Memory barrier */
2859 wmb();
2860 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2861 }
2862
2863 spin_unlock_irqrestore(&hr_cq->lock, flags);
2864
2865 return npolled;
2866}
2867
a81fba28
WHX		 2868static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
2869 struct hns_roce_hem_table *table, int obj,
2870 int step_idx)
2871{
2872 struct device *dev = hr_dev->dev;
2873 struct hns_roce_cmd_mailbox *mailbox;
2874 struct hns_roce_hem_iter iter;
2875 struct hns_roce_hem_mhop mhop;
2876 struct hns_roce_hem *hem;
2877 unsigned long mhop_obj = obj;
2878 int i, j, k;
2879 int ret = 0;
2880 u64 hem_idx = 0;
2881 u64 l1_idx = 0;
2882 u64 bt_ba = 0;
2883 u32 chunk_ba_num;
2884 u32 hop_num;
2885 u16 op = 0xff;
2886
2887 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2888 return 0;
2889
2890 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
2891 i = mhop.l0_idx;
2892 j = mhop.l1_idx;
2893 k = mhop.l2_idx;
2894 hop_num = mhop.hop_num;
2895 chunk_ba_num = mhop.bt_chunk_size / 8;
2896
2897 if (hop_num == 2) {
2898 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
2899 k;
2900 l1_idx = i * chunk_ba_num + j;
2901 } else if (hop_num == 1) {
2902 hem_idx = i * chunk_ba_num + j;
2903 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
2904 hem_idx = i;
2905 }
2906
2907 switch (table->type) {
2908 case HEM_TYPE_QPC:
2909 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
2910 break;
2911 case HEM_TYPE_MTPT:
2912 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
2913 break;
2914 case HEM_TYPE_CQC:
2915 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
2916 break;
2917 case HEM_TYPE_SRQC:
2918 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
2919 break;
6a157f7d
YL		 2920 case HEM_TYPE_SCCC:
2921 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
2922 break;
0e40dc2f
YL		 2923 case HEM_TYPE_QPC_TIMER:
2924 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
2925 break;
2926 case HEM_TYPE_CQC_TIMER:
2927 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
2928 break;
a81fba28
WHX		 2929 default:
2930 dev_warn(dev, "Table %d not to be written by mailbox!\n",
2931 table->type);
2932 return 0;
2933 }
6a157f7d
YL		 2934
2935 if (table->type == HEM_TYPE_SCCC && step_idx)
2936 return 0;
2937
a81fba28
WHX		 2938 op += step_idx;
2939
2940 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2941 if (IS_ERR(mailbox))
2942 return PTR_ERR(mailbox);
2943
6ac16e40
YL		 2944 if (table->type == HEM_TYPE_SCCC)
2945 obj = mhop.l0_idx;
2946
a81fba28
WHX		 2947 if (check_whether_last_step(hop_num, step_idx)) {
2948 hem = table->hem[hem_idx];
2949 for (hns_roce_hem_first(hem, &iter);
2950 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
2951 bt_ba = hns_roce_hem_addr(&iter);
2952
2953 /* configure the ba, tag, and op */
2954 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
2955 obj, 0, op,
2956 HNS_ROCE_CMD_TIMEOUT_MSECS);
2957 }
2958 } else {
2959 if (step_idx == 0)
2960 bt_ba = table->bt_l0_dma_addr[i];
2961 else if (step_idx == 1 && hop_num == 2)
2962 bt_ba = table->bt_l1_dma_addr[l1_idx];
2963
2964 /* configure the ba, tag, and op */
2965 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
2966 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
2967 }
2968
2969 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2970 return ret;
2971}
2972
2973static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
2974 struct hns_roce_hem_table *table, int obj,
2975 int step_idx)
2976{
2977 struct device *dev = hr_dev->dev;
2978 struct hns_roce_cmd_mailbox *mailbox;
2979 int ret = 0;
2980 u16 op = 0xff;
2981
2982 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2983 return 0;
2984
2985 switch (table->type) {
2986 case HEM_TYPE_QPC:
2987 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
2988 break;
2989 case HEM_TYPE_MTPT:
2990 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
2991 break;
2992 case HEM_TYPE_CQC:
2993 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
2994 break;
6a157f7d 2995 case HEM_TYPE_SCCC:
0e40dc2f
YL		 2996 case HEM_TYPE_QPC_TIMER:
2997 case HEM_TYPE_CQC_TIMER:
6a157f7d 2998 break;
a81fba28
WHX		 2999 case HEM_TYPE_SRQC:
3000 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
3001 break;
3002 default:
3003 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
3004 table->type);
3005 return 0;
3006 }
6a157f7d 3007
0e40dc2f
YL		 3008 if (table->type == HEM_TYPE_SCCC ||
3009 table->type == HEM_TYPE_QPC_TIMER ||
3010 table->type == HEM_TYPE_CQC_TIMER)
6a157f7d
YL		 3011 return 0;
3012
a81fba28
WHX		 3013 op += step_idx;
3014
3015 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3016 if (IS_ERR(mailbox))
3017 return PTR_ERR(mailbox);
3018
3019 /* configure the tag and op */
3020 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3021 HNS_ROCE_CMD_TIMEOUT_MSECS);
3022
3023 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3024 return ret;
3025}
3026
926a01dc
WHX		 3027static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
3028 struct hns_roce_mtt *mtt,
3029 enum ib_qp_state cur_state,
3030 enum ib_qp_state new_state,
3031 struct hns_roce_v2_qp_context *context,
3032 struct hns_roce_qp *hr_qp)
3033{
3034 struct hns_roce_cmd_mailbox *mailbox;
3035 int ret;
3036
3037 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3038 if (IS_ERR(mailbox))
3039 return PTR_ERR(mailbox);
3040
3041 memcpy(mailbox->buf, context, sizeof(*context) * 2);
3042
3043 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
3044 HNS_ROCE_CMD_MODIFY_QPC,
3045 HNS_ROCE_CMD_TIMEOUT_MSECS);
3046
3047 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3048
3049 return ret;
3050}
3051
ace1c541 3052static void set_access_flags(struct hns_roce_qp *hr_qp,
3053 struct hns_roce_v2_qp_context *context,
3054 struct hns_roce_v2_qp_context *qpc_mask,
3055 const struct ib_qp_attr *attr, int attr_mask)
3056{
3057 u8 dest_rd_atomic;
3058 u32 access_flags;
3059
c2799119 3060 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 3061 attr->max_dest_rd_atomic : hr_qp->resp_depth;
3062
c2799119 3063 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 3064 attr->qp_access_flags : hr_qp->atomic_rd_en;
3065
3066 if (!dest_rd_atomic)
3067 access_flags &= IB_ACCESS_REMOTE_WRITE;
3068
3069 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3070 !!(access_flags & IB_ACCESS_REMOTE_READ));
3071 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
3072
3073 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3074 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3075 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
3076
3077 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3078 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3079 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
3080}
3081
926a01dc
WHX		 3082static void modify_qp_reset_to_init(struct ib_qp *ibqp,
3083 const struct ib_qp_attr *attr,
0fa95a9a 3084 int attr_mask,
926a01dc
WHX		 3085 struct hns_roce_v2_qp_context *context,
3086 struct hns_roce_v2_qp_context *qpc_mask)
3087{
ecaaf1e2 3088 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 3089 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3090
3091 /*
3092 * In v2 engine, software pass context and context mask to hardware
3093 * when modifying qp. If software need modify some fields in context,
3094 * we should set all bits of the relevant fields in context mask to
3095 * 0 at the same time, else set them to 0x1.
3096 */
3097 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3098 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3099 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3100 V2_QPC_BYTE_4_TST_S, 0);
3101
0fa95a9a 3102 if (ibqp->qp_type == IB_QPT_GSI)
3103 roce_set_field(context->byte_4_sqpn_tst,
3104 V2_QPC_BYTE_4_SGE_SHIFT_M,
3105 V2_QPC_BYTE_4_SGE_SHIFT_S,
3106 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3107 else
3108 roce_set_field(context->byte_4_sqpn_tst,
3109 V2_QPC_BYTE_4_SGE_SHIFT_M,
3110 V2_QPC_BYTE_4_SGE_SHIFT_S,
3111 hr_qp->sq.max_gs > 2 ?
3112 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3113
926a01dc
WHX		 3114 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
3115 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
3116
3117 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3118 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3119 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3120 V2_QPC_BYTE_4_SQPN_S, 0);
3121
3122 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3123 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3124 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3125 V2_QPC_BYTE_16_PD_S, 0);
3126
3127 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3128 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
3129 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3130 V2_QPC_BYTE_20_RQWS_S, 0);
3131
3132 roce_set_field(context->byte_20_smac_sgid_idx,
3133 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3134 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
3135 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3136 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
3137
3138 roce_set_field(context->byte_20_smac_sgid_idx,
3139 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
c7bcb134
LO		 3140 (hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3141 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT || ibqp->srq) ? 0 :
926a01dc
WHX		 3142 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
3143 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3144 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
3145
3146 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 3147 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3148 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
3149 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3150 V2_QPC_BYTE_24_VLAN_ID_S, 0);
926a01dc
WHX		 3151
3152 /*
3153 * Set some fields in context to zero, Because the default values
3154 * of all fields in context are zero, we need not set them to 0 again.
3155 * but we should set the relevant fields of context mask to 0.
3156 */
3157 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
3158 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
3159 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
3160 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
3161
2362ccee
LO		 3162 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_TEMPID_M,
3163 V2_QPC_BYTE_60_TEMPID_S, 0);
3164
3165 roce_set_field(qpc_mask->byte_60_qpst_tempid,
3166 V2_QPC_BYTE_60_SCC_TOKEN_M, V2_QPC_BYTE_60_SCC_TOKEN_S,
3167 0);
3168 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
3169 V2_QPC_BYTE_60_SQ_DB_DOING_S, 0);
3170 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
3171 V2_QPC_BYTE_60_RQ_DB_DOING_S, 0);
926a01dc
WHX		 3172 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
3173 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
3174
e088a685
YL		 3175 if (hr_qp->rdb_en) {
3176 roce_set_bit(context->byte_68_rq_db,
3177 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
3178 roce_set_bit(qpc_mask->byte_68_rq_db,
3179 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0);
3180 }
3181
3182 roce_set_field(context->byte_68_rq_db,
3183 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3184 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
3185 ((u32)hr_qp->rdb.dma) >> 1);
3186 roce_set_field(qpc_mask->byte_68_rq_db,
3187 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3188 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0);
3189 context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
3190 qpc_mask->rq_db_record_addr = 0;
3191
ecaaf1e2 3192 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
3193 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 3194 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
3195
3196 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3197 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3198 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3199 V2_QPC_BYTE_80_RX_CQN_S, 0);
3200 if (ibqp->srq) {
3201 roce_set_field(context->byte_76_srqn_op_en,
3202 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3203 to_hr_srq(ibqp->srq)->srqn);
3204 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3205 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3206 roce_set_bit(context->byte_76_srqn_op_en,
3207 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3208 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3209 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3210 }
3211
3212 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3213 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3214 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3215 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3216 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3217 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3218
3219 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
3220 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
3221
3222 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3223 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3224
3225 roce_set_field(qpc_mask->byte_104_rq_sge,
3226 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
3227 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
3228
3229 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3230 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3231 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3232 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3233 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3234 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3235 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
3236
3237 qpc_mask->rq_rnr_timer = 0;
3238 qpc_mask->rx_msg_len = 0;
3239 qpc_mask->rx_rkey_pkt_info = 0;
3240 qpc_mask->rx_va = 0;
3241
3242 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3243 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3244 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3245 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3246
2362ccee
LO		 3247 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S,
3248 0);
926a01dc
WHX		 3249 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
3250 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
3251 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
3252 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
3253
3254 roce_set_field(qpc_mask->byte_144_raq,
3255 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
3256 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
926a01dc
WHX		 3257 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
3258 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
3259 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
3260
3261 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
3262 V2_QPC_BYTE_148_RQ_MSN_S, 0);
3263 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
3264 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
3265
3266 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3267 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3268 roce_set_field(qpc_mask->byte_152_raq,
3269 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
3270 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
3271
3272 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
3273 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
3274
3275 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3276 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3277 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
3278 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3279 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
3280 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
3281
2362ccee
LO		 3282 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3283 V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S, 0);
3284 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3285 V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S, 0);
3286 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3287 V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S, 0);
926a01dc
WHX		 3288 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3289 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 3290 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3291 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 3292 roce_set_field(qpc_mask->byte_168_irrl_idx,
3293 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
3294 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
3295
3296 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3297 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
3298 roce_set_field(qpc_mask->byte_172_sq_psn,
3299 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3300 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
3301
3302 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
3303 0);
3304
68a997c5
YL		 3305 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
3306 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 0);
3307
926a01dc
WHX		 3308 roce_set_field(qpc_mask->byte_176_msg_pktn,
3309 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
3310 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
3311 roce_set_field(qpc_mask->byte_176_msg_pktn,
3312 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
3313 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
3314
3315 roce_set_field(qpc_mask->byte_184_irrl_idx,
3316 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
3317 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
3318
3319 qpc_mask->cur_sge_offset = 0;
3320
3321 roce_set_field(qpc_mask->byte_192_ext_sge,
3322 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
3323 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
3324 roce_set_field(qpc_mask->byte_192_ext_sge,
3325 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
3326 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
3327
3328 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3329 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3330
3331 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
3332 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
3333 roce_set_field(qpc_mask->byte_200_sq_max,
3334 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
3335 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
3336
3337 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
3338 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
3339
3340 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3341 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3342
3343 qpc_mask->sq_timer = 0;
3344
3345 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3346 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3347 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3348 roce_set_field(qpc_mask->byte_232_irrl_sge,
3349 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3350 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3351
2362ccee
LO		 3352 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_SO_LP_VLD_S,
3353 0);
3354 roce_set_bit(qpc_mask->byte_232_irrl_sge,
3355 V2_QPC_BYTE_232_FENCE_LP_VLD_S, 0);
3356 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_IRRL_LP_VLD_S,
3357 0);
3358
926a01dc
WHX		 3359 qpc_mask->irrl_cur_sge_offset = 0;
3360
3361 roce_set_field(qpc_mask->byte_240_irrl_tail,
3362 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3363 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3364 roce_set_field(qpc_mask->byte_240_irrl_tail,
3365 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
3366 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
3367 roce_set_field(qpc_mask->byte_240_irrl_tail,
3368 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3369 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3370
3371 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
3372 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3373 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
3374 0);
3375 roce_set_field(qpc_mask->byte_248_ack_psn,
3376 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3377 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3378 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
3379 0);
3380 roce_set_bit(qpc_mask->byte_248_ack_psn,
3381 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3382 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
3383 0);
3384
3385 hr_qp->access_flags = attr->qp_access_flags;
926a01dc
WHX		 3386 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3387 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
3388 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3389 V2_QPC_BYTE_252_TX_CQN_S, 0);
3390
3391 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
3392 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
3393
3394 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3395 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
3396 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
3397 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3398 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
3399 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
3400}
3401
3402static void modify_qp_init_to_init(struct ib_qp *ibqp,
3403 const struct ib_qp_attr *attr, int attr_mask,
3404 struct hns_roce_v2_qp_context *context,
3405 struct hns_roce_v2_qp_context *qpc_mask)
3406{
3407 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3408
3409 /*
3410 * In v2 engine, software pass context and context mask to hardware
3411 * when modifying qp. If software need modify some fields in context,
3412 * we should set all bits of the relevant fields in context mask to
3413 * 0 at the same time, else set them to 0x1.
3414 */
3415 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3416 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3417 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3418 V2_QPC_BYTE_4_TST_S, 0);
3419
0fa95a9a 3420 if (ibqp->qp_type == IB_QPT_GSI)
3421 roce_set_field(context->byte_4_sqpn_tst,
3422 V2_QPC_BYTE_4_SGE_SHIFT_M,
3423 V2_QPC_BYTE_4_SGE_SHIFT_S,
3424 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3425 else
3426 roce_set_field(context->byte_4_sqpn_tst,
3427 V2_QPC_BYTE_4_SGE_SHIFT_M,
3428 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
3429 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3430
926a01dc
WHX		 3431 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
3432 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
3433
3434 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3435 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3436 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3437 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3438 0);
3439
3440 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3441 !!(attr->qp_access_flags &
3442 IB_ACCESS_REMOTE_WRITE));
3443 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3444 0);
3445
3446 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3447 !!(attr->qp_access_flags &
3448 IB_ACCESS_REMOTE_ATOMIC));
3449 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3450 0);
3451 } else {
3452 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3453 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3454 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3455 0);
3456
3457 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3458 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3459 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3460 0);
3461
3462 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3463 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3464 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3465 0);
3466 }
3467
3468 roce_set_field(context->byte_20_smac_sgid_idx,
3469 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3470 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
3471 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3472 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
3473
3474 roce_set_field(context->byte_20_smac_sgid_idx,
3475 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
c7bcb134
LO		 3476 (hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3477 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT || ibqp->srq) ? 0 :
926a01dc
WHX		 3478 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
3479 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3480 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
3481
3482 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3483 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3484 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3485 V2_QPC_BYTE_16_PD_S, 0);
3486
3487 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3488 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3489 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3490 V2_QPC_BYTE_80_RX_CQN_S, 0);
3491
3492 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3493 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3494 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3495 V2_QPC_BYTE_252_TX_CQN_S, 0);
3496
3497 if (ibqp->srq) {
3498 roce_set_bit(context->byte_76_srqn_op_en,
3499 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3500 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3501 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3502 roce_set_field(context->byte_76_srqn_op_en,
3503 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3504 to_hr_srq(ibqp->srq)->srqn);
3505 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3506 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3507 }
3508
926a01dc
WHX		 3509 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3510 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3511 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3512 V2_QPC_BYTE_4_SQPN_S, 0);
3513
b6dd9b34 3514 if (attr_mask & IB_QP_DEST_QPN) {
3515 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3516 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3517 roce_set_field(qpc_mask->byte_56_dqpn_err,
3518 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3519 }
926a01dc
WHX		 3520}
3521
3522static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3523 const struct ib_qp_attr *attr, int attr_mask,
3524 struct hns_roce_v2_qp_context *context,
3525 struct hns_roce_v2_qp_context *qpc_mask)
3526{
3527 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3528 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3529 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3530 struct device *dev = hr_dev->dev;
e92f2c18 3531 dma_addr_t dma_handle_3;
926a01dc
WHX		 3532 dma_addr_t dma_handle_2;
3533 dma_addr_t dma_handle;
3534 u32 page_size;
3535 u8 port_num;
e92f2c18 3536 u64 *mtts_3;
926a01dc
WHX		 3537 u64 *mtts_2;
3538 u64 *mtts;
3539 u8 *dmac;
3540 u8 *smac;
3541 int port;
3542
3543 /* Search qp buf's mtts */
3544 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3545 hr_qp->mtt.first_seg, &dma_handle);
3546 if (!mtts) {
3547 dev_err(dev, "qp buf pa find failed\n");
3548 return -EINVAL;
3549 }
3550
3551 /* Search IRRL's mtts */
3552 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3553 hr_qp->qpn, &dma_handle_2);
3554 if (!mtts_2) {
3555 dev_err(dev, "qp irrl_table find failed\n");
3556 return -EINVAL;
3557 }
3558
e92f2c18 3559 /* Search TRRL's mtts */
3560 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3561 hr_qp->qpn, &dma_handle_3);
3562 if (!mtts_3) {
3563 dev_err(dev, "qp trrl_table find failed\n");
3564 return -EINVAL;
3565 }
3566
734f3863 3567 if (attr_mask & IB_QP_ALT_PATH) {
926a01dc
WHX		 3568 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
3569 return -EINVAL;
3570 }
3571
3572 dmac = (u8 *)attr->ah_attr.roce.dmac;
3573 context->wqe_sge_ba = (u32)(dma_handle >> 3);
3574 qpc_mask->wqe_sge_ba = 0;
3575
3576 /*
3577 * In v2 engine, software pass context and context mask to hardware
3578 * when modifying qp. If software need modify some fields in context,
3579 * we should set all bits of the relevant fields in context mask to
3580 * 0 at the same time, else set them to 0x1.
3581 */
3582 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3583 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
3584 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3585 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3586
3587 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3588 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
3589 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3590 0 : hr_dev->caps.mtt_hop_num);
3591 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3592 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3593
3594 roce_set_field(context->byte_20_smac_sgid_idx,
3595 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3596 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
0fa95a9a 3597 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
3598 hr_dev->caps.mtt_hop_num : 0);
926a01dc
WHX		 3599 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3600 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3601 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3602
3603 roce_set_field(context->byte_20_smac_sgid_idx,
3604 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3605 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
3606 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3607 0 : hr_dev->caps.mtt_hop_num);
3608 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3609 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3610 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3611
3612 roce_set_field(context->byte_16_buf_ba_pg_sz,
3613 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3614 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
5e6e78db 3615 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3616 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3617 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3618 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3619
3620 roce_set_field(context->byte_16_buf_ba_pg_sz,
3621 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3622 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
5e6e78db 3623 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3624 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3625 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3626 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3627
926a01dc
WHX		 3628 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
3629 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
3630 >> PAGE_ADDR_SHIFT);
3631 qpc_mask->rq_cur_blk_addr = 0;
3632
3633 roce_set_field(context->byte_92_srq_info,
3634 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3635 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
3636 mtts[hr_qp->rq.offset / page_size]
3637 >> (32 + PAGE_ADDR_SHIFT));
3638 roce_set_field(qpc_mask->byte_92_srq_info,
3639 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3640 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3641
3642 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
3643 >> PAGE_ADDR_SHIFT);
3644 qpc_mask->rq_nxt_blk_addr = 0;
3645
3646 roce_set_field(context->byte_104_rq_sge,
3647 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3648 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
3649 mtts[hr_qp->rq.offset / page_size + 1]
3650 >> (32 + PAGE_ADDR_SHIFT));
3651 roce_set_field(qpc_mask->byte_104_rq_sge,
3652 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3653 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3654
e92f2c18 3655 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3656 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3657 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3658 V2_QPC_BYTE_132_TRRL_BA_S, 0);
3659 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
3660 qpc_mask->trrl_ba = 0;
3661 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3662 V2_QPC_BYTE_140_TRRL_BA_S,
3663 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3664 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3665 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3666
d5514246 3667 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 3668 qpc_mask->irrl_ba = 0;
3669 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3670 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3671 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3672 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3673 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3674
3675 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3676 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3677
3678 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3679 hr_qp->sq_signal_bits);
3680 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3681 0);
3682
3683 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3684
3685 smac = (u8 *)hr_dev->dev_addr[port];
3686 /* when dmac equals smac or loop_idc is 1, it should loopback */
3687 if (ether_addr_equal_unaligned(dmac, smac) ||
3688 hr_dev->loop_idc == 0x1) {
3689 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3690 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3691 }
3692
b6dd9b34 3693 if (attr_mask & IB_QP_DEST_QPN) {
3694 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3695 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3696 roce_set_field(qpc_mask->byte_56_dqpn_err,
3697 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3698 }
926a01dc
WHX		 3699
3700 /* Configure GID index */
3701 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3702 roce_set_field(context->byte_20_smac_sgid_idx,
3703 V2_QPC_BYTE_20_SGID_IDX_M,
3704 V2_QPC_BYTE_20_SGID_IDX_S,
3705 hns_get_gid_index(hr_dev, port_num - 1,
3706 grh->sgid_index));
3707 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3708 V2_QPC_BYTE_20_SGID_IDX_M,
3709 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3710 memcpy(&(context->dmac), dmac, 4);
3711 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3712 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3713 qpc_mask->dmac = 0;
3714 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3715 V2_QPC_BYTE_52_DMAC_S, 0);
3716
3717 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3718 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
3719 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3720 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3721
0fa95a9a 3722 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3723 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3724 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3725 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3726 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3727 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3728
926a01dc
WHX		 3729 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3730 V2_QPC_BYTE_24_MTU_S, 0);
3731
926a01dc
WHX		 3732 roce_set_field(context->byte_84_rq_ci_pi,
3733 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3734 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3735 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3736 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3737 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3738
3739 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3740 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3741 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3742 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3743 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3744 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3745 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3746 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3747 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3748 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3749
3750 context->rq_rnr_timer = 0;
3751 qpc_mask->rq_rnr_timer = 0;
3752
926a01dc
WHX		 3753 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3754 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3755 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3756 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3757
3758 roce_set_field(context->byte_168_irrl_idx,
3759 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3760 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3761 roce_set_field(qpc_mask->byte_168_irrl_idx,
3762 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3763 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3764
926a01dc
WHX		 3765 return 0;
3766}
3767
3768static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3769 const struct ib_qp_attr *attr, int attr_mask,
3770 struct hns_roce_v2_qp_context *context,
3771 struct hns_roce_v2_qp_context *qpc_mask)
3772{
3773 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3774 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3775 struct device *dev = hr_dev->dev;
3776 dma_addr_t dma_handle;
befb63b4 3777 u32 page_size;
926a01dc
WHX		 3778 u64 *mtts;
3779
3780 /* Search qp buf's mtts */
3781 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3782 hr_qp->mtt.first_seg, &dma_handle);
3783 if (!mtts) {
3784 dev_err(dev, "qp buf pa find failed\n");
3785 return -EINVAL;
3786 }
3787
734f3863 3788 /* Not support alternate path and path migration */
3789 if ((attr_mask & IB_QP_ALT_PATH) ||
3790 (attr_mask & IB_QP_PATH_MIG_STATE)) {
926a01dc
WHX		 3791 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
3792 return -EINVAL;
3793 }
3794
3795 /*
3796 * In v2 engine, software pass context and context mask to hardware
3797 * when modifying qp. If software need modify some fields in context,
3798 * we should set all bits of the relevant fields in context mask to
3799 * 0 at the same time, else set them to 0x1.
3800 */
926a01dc
WHX		 3801 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3802 roce_set_field(context->byte_168_irrl_idx,
3803 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3804 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3805 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3806 qpc_mask->sq_cur_blk_addr = 0;
3807 roce_set_field(qpc_mask->byte_168_irrl_idx,
3808 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3809 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3810
befb63b4 3811 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
0fa95a9a 3812 context->sq_cur_sge_blk_addr =
3813 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3814 ((u32)(mtts[hr_qp->sge.offset / page_size]
3815 >> PAGE_ADDR_SHIFT)) : 0;
3816 roce_set_field(context->byte_184_irrl_idx,
3817 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3818 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
0fa95a9a 3819 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3820 (mtts[hr_qp->sge.offset / page_size] >>
3821 (32 + PAGE_ADDR_SHIFT)) : 0);
3822 qpc_mask->sq_cur_sge_blk_addr = 0;
3823 roce_set_field(qpc_mask->byte_184_irrl_idx,
3824 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3825 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3826
926a01dc
WHX		 3827 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3828 roce_set_field(context->byte_232_irrl_sge,
3829 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3830 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3831 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3832 qpc_mask->rx_sq_cur_blk_addr = 0;
3833 roce_set_field(qpc_mask->byte_232_irrl_sge,
3834 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3835 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3836
3837 /*
3838 * Set some fields in context to zero, Because the default values
3839 * of all fields in context are zero, we need not set them to 0 again.
3840 * but we should set the relevant fields of context mask to 0.
3841 */
3842 roce_set_field(qpc_mask->byte_232_irrl_sge,
3843 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3844 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3845
3846 roce_set_field(qpc_mask->byte_240_irrl_tail,
3847 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3848 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3849
926a01dc
WHX		 3850 roce_set_field(qpc_mask->byte_248_ack_psn,
3851 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3852 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3853 roce_set_bit(qpc_mask->byte_248_ack_psn,
3854 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
3855 roce_set_field(qpc_mask->byte_248_ack_psn,
3856 V2_QPC_BYTE_248_IRRL_PSN_M,
3857 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3858
3859 roce_set_field(qpc_mask->byte_240_irrl_tail,
3860 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3861 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3862
926a01dc
WHX		 3863 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3864 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3865 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3866
3867 roce_set_bit(qpc_mask->byte_248_ack_psn,
3868 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3869
3870 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3871 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3872
926a01dc
WHX		 3873 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3874 V2_QPC_BYTE_212_LSN_S, 0x100);
3875 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3876 V2_QPC_BYTE_212_LSN_S, 0);
3877
926a01dc
WHX		 3878 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3879 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
926a01dc
WHX		 3880
3881 return 0;
3882}
3883
233673e4
LO		 3884static inline bool hns_roce_v2_check_qp_stat(enum ib_qp_state cur_state,
3885 enum ib_qp_state new_state)
3886{
3887
3888 if ((cur_state != IB_QPS_RESET &&
3889 (new_state == IB_QPS_ERR || new_state == IB_QPS_RESET)) ||
3890 ((cur_state == IB_QPS_RTS || cur_state == IB_QPS_SQD) &&
3891 (new_state == IB_QPS_RTS || new_state == IB_QPS_SQD)) ||
3892 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS))
3893 return true;
3894
3895 return false;
3896
3897}
3898
926a01dc
WHX		 3899static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
3900 const struct ib_qp_attr *attr,
3901 int attr_mask, enum ib_qp_state cur_state,
3902 enum ib_qp_state new_state)
3903{
3904 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3905 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3906 struct hns_roce_v2_qp_context *context;
3907 struct hns_roce_v2_qp_context *qpc_mask;
3908 struct device *dev = hr_dev->dev;
3909 int ret = -EINVAL;
3910
4e69cf1f 3911 context = kcalloc(2, sizeof(*context), GFP_ATOMIC);
926a01dc
WHX		 3912 if (!context)
3913 return -ENOMEM;
3914
3915 qpc_mask = context + 1;
3916 /*
3917 * In v2 engine, software pass context and context mask to hardware
3918 * when modifying qp. If software need modify some fields in context,
3919 * we should set all bits of the relevant fields in context mask to
3920 * 0 at the same time, else set them to 0x1.
3921 */
3922 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
3923 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
9f507101 3924 memset(qpc_mask, 0, sizeof(*qpc_mask));
0fa95a9a 3925 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
3926 qpc_mask);
926a01dc
WHX		 3927 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3928 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
3929 qpc_mask);
3930 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3931 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
3932 qpc_mask);
3933 if (ret)
3934 goto out;
3935 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3936 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
3937 qpc_mask);
3938 if (ret)
3939 goto out;
233673e4 3940 } else if (hns_roce_v2_check_qp_stat(cur_state, new_state)) {
926a01dc
WHX		 3941 /* Nothing */
3942 ;
3943 } else {
3944 dev_err(dev, "Illegal state for QP!\n");
ac7cbf96 3945 ret = -EINVAL;
926a01dc
WHX		 3946 goto out;
3947 }
3948
0425e3e6
YL		 3949 /* When QP state is err, SQ and RQ WQE should be flushed */
3950 if (new_state == IB_QPS_ERR) {
3951 roce_set_field(context->byte_160_sq_ci_pi,
3952 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3953 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
3954 hr_qp->sq.head);
3955 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3956 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3957 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
9c6ccc03
LO		 3958
3959 if (!ibqp->srq) {
3960 roce_set_field(context->byte_84_rq_ci_pi,
0425e3e6
YL		 3961 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3962 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
3963 hr_qp->rq.head);
9c6ccc03 3964 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
0425e3e6
YL		 3965 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3966 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
9c6ccc03 3967 }
0425e3e6
YL		 3968 }
3969
610b8967
LO		 3970 if (attr_mask & IB_QP_AV) {
3971 const struct ib_global_route *grh =
3972 rdma_ah_read_grh(&attr->ah_attr);
3973 const struct ib_gid_attr *gid_attr = NULL;
610b8967
LO		 3974 int is_roce_protocol;
3975 u16 vlan = 0xffff;
3976 u8 ib_port;
3977 u8 hr_port;
3978
3979 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num :
3980 hr_qp->port + 1;
3981 hr_port = ib_port - 1;
3982 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
3983 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
3984
3985 if (is_roce_protocol) {
3986 gid_attr = attr->ah_attr.grh.sgid_attr;
3987 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
610b8967
LO		 3988 }
3989
caf3e406
LO		 3990 if (is_vlan_dev(gid_attr->ndev)) {
3991 roce_set_bit(context->byte_76_srqn_op_en,
3992 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
3993 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3994 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
3995 roce_set_bit(context->byte_168_irrl_idx,
3996 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
3997 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3998 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
3999 }
4000
c8e46f8d
LO		 4001 roce_set_field(context->byte_24_mtu_tc,
4002 V2_QPC_BYTE_24_VLAN_ID_M,
4003 V2_QPC_BYTE_24_VLAN_ID_S, vlan);
4004 roce_set_field(qpc_mask->byte_24_mtu_tc,
4005 V2_QPC_BYTE_24_VLAN_ID_M,
4006 V2_QPC_BYTE_24_VLAN_ID_S, 0);
4007
610b8967
LO		 4008 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4009 dev_err(hr_dev->dev,
4010 "sgid_index(%u) too large. max is %d\n",
4011 grh->sgid_index,
4012 hr_dev->caps.gid_table_len[hr_port]);
4013 ret = -EINVAL;
4014 goto out;
4015 }
4016
4017 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4018 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n");
4019 ret = -EINVAL;
4020 goto out;
4021 }
4022
4023 roce_set_field(context->byte_52_udpspn_dmac,
4024 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S,
4025 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ?
4026 0 : 0x12b7);
4027
4028 roce_set_field(qpc_mask->byte_52_udpspn_dmac,
4029 V2_QPC_BYTE_52_UDPSPN_M,
4030 V2_QPC_BYTE_52_UDPSPN_S, 0);
4031
4032 roce_set_field(context->byte_20_smac_sgid_idx,
4033 V2_QPC_BYTE_20_SGID_IDX_M,
4034 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index);
4035
4036 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4037 V2_QPC_BYTE_20_SGID_IDX_M,
4038 V2_QPC_BYTE_20_SGID_IDX_S, 0);
4039
4040 roce_set_field(context->byte_24_mtu_tc,
4041 V2_QPC_BYTE_24_HOP_LIMIT_M,
4042 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
4043 roce_set_field(qpc_mask->byte_24_mtu_tc,
4044 V2_QPC_BYTE_24_HOP_LIMIT_M,
4045 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
4046
157b52a0
LO		 4047 if (hr_dev->pci_dev->revision == 0x21 &&
4048 gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
4049 roce_set_field(context->byte_24_mtu_tc,
4050 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
4051 grh->traffic_class >> 2);
4052 else
4053 roce_set_field(context->byte_24_mtu_tc,
4054 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
4055 grh->traffic_class);
610b8967
LO		 4056 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4057 V2_QPC_BYTE_24_TC_S, 0);
4058 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4059 V2_QPC_BYTE_28_FL_S, grh->flow_label);
4060 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4061 V2_QPC_BYTE_28_FL_S, 0);
4062 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4063 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4064 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4065 V2_QPC_BYTE_28_SL_S,
4066 rdma_ah_get_sl(&attr->ah_attr));
4067 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4068 V2_QPC_BYTE_28_SL_S, 0);
4069 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4070 }
4071
5b01b243
LO		 4072 if (attr_mask & IB_QP_TIMEOUT) {
4073 if (attr->timeout < 31) {
4074 roce_set_field(context->byte_28_at_fl,
4075 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4076 attr->timeout);
4077 roce_set_field(qpc_mask->byte_28_at_fl,
4078 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4079 0);
4080 } else {
4081 dev_warn(dev, "Local ACK timeout shall be 0 to 30.\n");
4082 }
4083 }
4084
4085 if (attr_mask & IB_QP_RETRY_CNT) {
4086 roce_set_field(context->byte_212_lsn,
4087 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4088 V2_QPC_BYTE_212_RETRY_NUM_INIT_S,
4089 attr->retry_cnt);
4090 roce_set_field(qpc_mask->byte_212_lsn,
4091 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4092 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
4093
4094 roce_set_field(context->byte_212_lsn,
4095 V2_QPC_BYTE_212_RETRY_CNT_M,
4096 V2_QPC_BYTE_212_RETRY_CNT_S,
4097 attr->retry_cnt);
4098 roce_set_field(qpc_mask->byte_212_lsn,
4099 V2_QPC_BYTE_212_RETRY_CNT_M,
4100 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
4101 }
4102
4103 if (attr_mask & IB_QP_RNR_RETRY) {
4104 roce_set_field(context->byte_244_rnr_rxack,
4105 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4106 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
4107 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4108 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4109 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
4110
4111 roce_set_field(context->byte_244_rnr_rxack,
4112 V2_QPC_BYTE_244_RNR_CNT_M,
4113 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
4114 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4115 V2_QPC_BYTE_244_RNR_CNT_M,
4116 V2_QPC_BYTE_244_RNR_CNT_S, 0);
4117 }
4118
f04cc178
LO		 4119 if (attr_mask & IB_QP_SQ_PSN) {
4120 roce_set_field(context->byte_172_sq_psn,
4121 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4122 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
4123 roce_set_field(qpc_mask->byte_172_sq_psn,
4124 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4125 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
4126
4127 roce_set_field(context->byte_196_sq_psn,
4128 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4129 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
4130 roce_set_field(qpc_mask->byte_196_sq_psn,
4131 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4132 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
4133
4134 roce_set_field(context->byte_220_retry_psn_msn,
4135 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4136 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
4137 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4138 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4139 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
4140
4141 roce_set_field(context->byte_224_retry_msg,
4142 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4143 V2_QPC_BYTE_224_RETRY_MSG_PSN_S,
4144 attr->sq_psn >> 16);
4145 roce_set_field(qpc_mask->byte_224_retry_msg,
4146 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4147 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
4148
4149 roce_set_field(context->byte_224_retry_msg,
4150 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4151 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S,
4152 attr->sq_psn);
4153 roce_set_field(qpc_mask->byte_224_retry_msg,
4154 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4155 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
4156
4157 roce_set_field(context->byte_244_rnr_rxack,
4158 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4159 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
4160 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4161 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4162 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
4163 }
4164
5b01b243
LO		 4165 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
4166 attr->max_dest_rd_atomic) {
4167 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4168 V2_QPC_BYTE_140_RR_MAX_S,
4169 fls(attr->max_dest_rd_atomic - 1));
4170 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4171 V2_QPC_BYTE_140_RR_MAX_S, 0);
4172 }
4173
4174 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
4175 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
4176 V2_QPC_BYTE_208_SR_MAX_S,
4177 fls(attr->max_rd_atomic - 1));
4178 roce_set_field(qpc_mask->byte_208_irrl,
4179 V2_QPC_BYTE_208_SR_MAX_M,
4180 V2_QPC_BYTE_208_SR_MAX_S, 0);
4181 }
4182
ace1c541 4183 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4184 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4185
5b01b243
LO		 4186 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
4187 roce_set_field(context->byte_80_rnr_rx_cqn,
4188 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4189 V2_QPC_BYTE_80_MIN_RNR_TIME_S,
4190 attr->min_rnr_timer);
4191 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
4192 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4193 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
4194 }
4195
601f3e6d
LO		 4196 /* RC&UC required attr */
4197 if (attr_mask & IB_QP_RQ_PSN) {
4198 roce_set_field(context->byte_108_rx_reqepsn,
4199 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4200 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
4201 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4202 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4203 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
4204
4205 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
4206 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
4207 roce_set_field(qpc_mask->byte_152_raq,
4208 V2_QPC_BYTE_152_RAQ_PSN_M,
4209 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
4210 }
4211
5b01b243
LO		 4212 if (attr_mask & IB_QP_QKEY) {
4213 context->qkey_xrcd = attr->qkey;
4214 qpc_mask->qkey_xrcd = 0;
4215 hr_qp->qkey = attr->qkey;
4216 }
4217
c7bcb134
LO		 4218 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S,
4219 ibqp->srq ? 1 : 0);
4220 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4221 V2_QPC_BYTE_108_INV_CREDIT_S, 0);
4222
926a01dc 4223 /* Every status migrate must change state */
2362ccee 4224 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 4225 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 4226 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 4227 V2_QPC_BYTE_60_QP_ST_S, 0);
4228
4229 /* SW pass context to HW */
4230 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
4231 context, hr_qp);
4232 if (ret) {
4233 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
4234 goto out;
4235 }
4236
4237 hr_qp->state = new_state;
4238
ace1c541 4239 if (attr_mask & IB_QP_ACCESS_FLAGS)
4240 hr_qp->atomic_rd_en = attr->qp_access_flags;
4241
926a01dc
WHX		 4242 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4243 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4244 if (attr_mask & IB_QP_PORT) {
4245 hr_qp->port = attr->port_num - 1;
4246 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4247 }
4248
4249 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
4250 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
4251 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
4252 if (ibqp->send_cq != ibqp->recv_cq)
4253 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4254 hr_qp->qpn, NULL);
4255
4256 hr_qp->rq.head = 0;
4257 hr_qp->rq.tail = 0;
4258 hr_qp->sq.head = 0;
4259 hr_qp->sq.tail = 0;
4260 hr_qp->sq_next_wqe = 0;
4261 hr_qp->next_sge = 0;
e088a685
YL		 4262 if (hr_qp->rq.wqe_cnt)
4263 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 4264 }
4265
4266out:
4267 kfree(context);
4268 return ret;
4269}
4270
4271static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
4272{
4273 switch (state) {
4274 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
4275 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
4276 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
4277 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
4278 case HNS_ROCE_QP_ST_SQ_DRAINING:
4279 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
4280 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
4281 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
4282 default: return -1;
4283 }
4284}
4285
4286static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
4287 struct hns_roce_qp *hr_qp,
4288 struct hns_roce_v2_qp_context *hr_context)
4289{
4290 struct hns_roce_cmd_mailbox *mailbox;
4291 int ret;
4292
4293 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4294 if (IS_ERR(mailbox))
4295 return PTR_ERR(mailbox);
4296
4297 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
4298 HNS_ROCE_CMD_QUERY_QPC,
4299 HNS_ROCE_CMD_TIMEOUT_MSECS);
4300 if (ret) {
4301 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
4302 goto out;
4303 }
4304
4305 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
4306
4307out:
4308 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4309 return ret;
4310}
4311
4312static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4313 int qp_attr_mask,
4314 struct ib_qp_init_attr *qp_init_attr)
4315{
4316 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4317 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4318 struct hns_roce_v2_qp_context *context;
4319 struct device *dev = hr_dev->dev;
4320 int tmp_qp_state;
4321 int state;
4322 int ret;
4323
4324 context = kzalloc(sizeof(*context), GFP_KERNEL);
4325 if (!context)
4326 return -ENOMEM;
4327
4328 memset(qp_attr, 0, sizeof(*qp_attr));
4329 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4330
4331 mutex_lock(&hr_qp->mutex);
4332
4333 if (hr_qp->state == IB_QPS_RESET) {
4334 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 4335 ret = 0;
926a01dc
WHX		 4336 goto done;
4337 }
4338
4339 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
4340 if (ret) {
4341 dev_err(dev, "query qpc error\n");
4342 ret = -EINVAL;
4343 goto out;
4344 }
4345
2362ccee 4346 state = roce_get_field(context->byte_60_qpst_tempid,
926a01dc
WHX		 4347 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
4348 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
4349 if (tmp_qp_state == -1) {
4350 dev_err(dev, "Illegal ib_qp_state\n");
4351 ret = -EINVAL;
4352 goto out;
4353 }
4354 hr_qp->state = (u8)tmp_qp_state;
4355 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
4356 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
4357 V2_QPC_BYTE_24_MTU_M,
4358 V2_QPC_BYTE_24_MTU_S);
4359 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 4360 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 4361 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
4362 qp_attr->qkey = V2_QKEY_VAL;
4363
4364 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
4365 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4366 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
4367 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
4368 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4369 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
4370 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
4371 V2_QPC_BYTE_56_DQPN_M,
4372 V2_QPC_BYTE_56_DQPN_S);
4373 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
4374 V2_QPC_BYTE_76_RRE_S)) << 2) |
4375 ((roce_get_bit(context->byte_76_srqn_op_en,
4376 V2_QPC_BYTE_76_RWE_S)) << 1) |
4377 ((roce_get_bit(context->byte_76_srqn_op_en,
4378 V2_QPC_BYTE_76_ATE_S)) << 3);
4379 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
4380 hr_qp->ibqp.qp_type == IB_QPT_UC) {
4381 struct ib_global_route *grh =
4382 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
4383
4384 rdma_ah_set_sl(&qp_attr->ah_attr,
4385 roce_get_field(context->byte_28_at_fl,
4386 V2_QPC_BYTE_28_SL_M,
4387 V2_QPC_BYTE_28_SL_S));
4388 grh->flow_label = roce_get_field(context->byte_28_at_fl,
4389 V2_QPC_BYTE_28_FL_M,
4390 V2_QPC_BYTE_28_FL_S);
4391 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
4392 V2_QPC_BYTE_20_SGID_IDX_M,
4393 V2_QPC_BYTE_20_SGID_IDX_S);
4394 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
4395 V2_QPC_BYTE_24_HOP_LIMIT_M,
4396 V2_QPC_BYTE_24_HOP_LIMIT_S);
4397 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
4398 V2_QPC_BYTE_24_TC_M,
4399 V2_QPC_BYTE_24_TC_S);
4400
4401 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
4402 }
4403
4404 qp_attr->port_num = hr_qp->port + 1;
4405 qp_attr->sq_draining = 0;
4406 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
4407 V2_QPC_BYTE_208_SR_MAX_M,
4408 V2_QPC_BYTE_208_SR_MAX_S);
4409 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
4410 V2_QPC_BYTE_140_RR_MAX_M,
4411 V2_QPC_BYTE_140_RR_MAX_S);
4412 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
4413 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4414 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4415 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
4416 V2_QPC_BYTE_28_AT_M,
4417 V2_QPC_BYTE_28_AT_S);
4418 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
4419 V2_QPC_BYTE_212_RETRY_CNT_M,
4420 V2_QPC_BYTE_212_RETRY_CNT_S);
4421 qp_attr->rnr_retry = context->rq_rnr_timer;
4422
4423done:
4424 qp_attr->cur_qp_state = qp_attr->qp_state;
4425 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4426 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4427
4428 if (!ibqp->uobject) {
4429 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4430 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4431 } else {
4432 qp_attr->cap.max_send_wr = 0;
4433 qp_attr->cap.max_send_sge = 0;
4434 }
4435
4436 qp_init_attr->cap = qp_attr->cap;
4437
4438out:
4439 mutex_unlock(&hr_qp->mutex);
4440 kfree(context);
4441 return ret;
4442}
4443
4444static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4445 struct hns_roce_qp *hr_qp,
bdeacabd 4446 struct ib_udata *udata)
926a01dc
WHX		 4447{
4448 struct hns_roce_cq *send_cq, *recv_cq;
4449 struct device *dev = hr_dev->dev;
4450 int ret;
4451
4452 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4453 /* Modify qp to reset before destroying qp */
4454 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4455 hr_qp->state, IB_QPS_RESET);
4456 if (ret) {
4457 dev_err(dev, "modify QP %06lx to ERR failed.\n",
4458 hr_qp->qpn);
4459 return ret;
4460 }
4461 }
4462
4463 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
4464 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
4465
4466 hns_roce_lock_cqs(send_cq, recv_cq);
4467
bdeacabd 4468 if (!udata) {
926a01dc
WHX		 4469 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
4470 to_hr_srq(hr_qp->ibqp.srq) : NULL);
4471 if (send_cq != recv_cq)
4472 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
4473 }
4474
4475 hns_roce_qp_remove(hr_dev, hr_qp);
4476
4477 hns_roce_unlock_cqs(send_cq, recv_cq);
4478
4479 hns_roce_qp_free(hr_dev, hr_qp);
4480
4481 /* Not special_QP, free their QPN */
4482 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
4483 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
4484 (hr_qp->ibqp.qp_type == IB_QPT_UD))
4485 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
4486
4487 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
4488
bdeacabd
SR		 4489 if (udata) {
4490 struct hns_roce_ucontext *context =
4491 rdma_udata_to_drv_context(
4492 udata,
4493 struct hns_roce_ucontext,
4494 ibucontext);
4495
0425e3e6 4496 if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1))
bdeacabd 4497 hns_roce_db_unmap_user(context, &hr_qp->sdb);
0425e3e6 4498
e088a685 4499 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1))
bdeacabd 4500 hns_roce_db_unmap_user(context, &hr_qp->rdb);
926a01dc
WHX		 4501 ib_umem_release(hr_qp->umem);
4502 } else {
4503 kfree(hr_qp->sq.wrid);
4504 kfree(hr_qp->rq.wrid);
4505 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
472bc0fb
YL		 4506 if (hr_qp->rq.wqe_cnt)
4507 hns_roce_free_db(hr_dev, &hr_qp->rdb);
926a01dc
WHX		 4508 }
4509
c7bcb134
LO		 4510 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) &&
4511 hr_qp->rq.wqe_cnt) {
0009c2db 4512 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
4513 kfree(hr_qp->rq_inl_buf.wqe_list);
4514 }
4515
926a01dc
WHX		 4516 return 0;
4517}
4518
c4367a26 4519static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
926a01dc
WHX		 4520{
4521 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4522 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4523 int ret;
4524
bdeacabd 4525 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
926a01dc
WHX		 4526 if (ret) {
4527 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
4528 return ret;
4529 }
4530
4531 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
4532 kfree(hr_to_hr_sqp(hr_qp));
4533 else
4534 kfree(hr_qp);
4535
4536 return 0;
4537}
4538
aa84fa18
YL		 4539static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
4540 struct hns_roce_qp *hr_qp)
4541{
da91ddfd 4542 struct hns_roce_sccc_clr_done *resp;
aa84fa18
YL		 4543 struct hns_roce_sccc_clr *clr;
4544 struct hns_roce_cmq_desc desc;
4545 int ret, i;
4546
4547 mutex_lock(&hr_dev->qp_table.scc_mutex);
4548
4549 /* set scc ctx clear done flag */
4550 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
aa84fa18
YL		 4551 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4552 if (ret) {
4553 dev_err(hr_dev->dev, "Reset SCC ctx failed(%d)\n", ret);
4554 goto out;
4555 }
4556
4557 /* clear scc context */
4558 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
4559 clr = (struct hns_roce_sccc_clr *)desc.data;
4560 clr->qpn = cpu_to_le32(hr_qp->qpn);
4561 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4562 if (ret) {
4563 dev_err(hr_dev->dev, "Clear SCC ctx failed(%d)\n", ret);
4564 goto out;
4565 }
4566
4567 /* query scc context clear is done or not */
4568 resp = (struct hns_roce_sccc_clr_done *)desc.data;
4569 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
4570 hns_roce_cmq_setup_basic_desc(&desc,
4571 HNS_ROCE_OPC_QUERY_SCCC, true);
4572 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4573 if (ret) {
4574 dev_err(hr_dev->dev, "Query clr cmq failed(%d)\n", ret);
4575 goto out;
4576 }
4577
4578 if (resp->clr_done)
4579 goto out;
4580
4581 msleep(20);
4582 }
4583
4584 dev_err(hr_dev->dev, "Query SCC clr done flag overtime.\n");
4585 ret = -ETIMEDOUT;
4586
4587out:
4588 mutex_unlock(&hr_dev->qp_table.scc_mutex);
4589 return ret;
4590}
4591
b156269d 4592static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
4593{
4594 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
4595 struct hns_roce_v2_cq_context *cq_context;
4596 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
4597 struct hns_roce_v2_cq_context *cqc_mask;
4598 struct hns_roce_cmd_mailbox *mailbox;
4599 int ret;
4600
4601 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4602 if (IS_ERR(mailbox))
4603 return PTR_ERR(mailbox);
4604
4605 cq_context = mailbox->buf;
4606 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
4607
4608 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
4609
4610 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4611 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4612 cq_count);
4613 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4614 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4615 0);
4616 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4617 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4618 cq_period);
4619 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4620 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4621 0);
4622
4623 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
4624 HNS_ROCE_CMD_MODIFY_CQC,
4625 HNS_ROCE_CMD_TIMEOUT_MSECS);
4626 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4627 if (ret)
4628 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
4629
4630 return ret;
4631}
4632
0425e3e6
YL		 4633static void hns_roce_set_qps_to_err(struct hns_roce_dev *hr_dev, u32 qpn)
4634{
4635 struct hns_roce_qp *hr_qp;
4636 struct ib_qp_attr attr;
4637 int attr_mask;
4638 int ret;
4639
4640 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
4641 if (!hr_qp) {
4642 dev_warn(hr_dev->dev, "no hr_qp can be found!\n");
4643 return;
4644 }
4645
4646 if (hr_qp->ibqp.uobject) {
4647 if (hr_qp->sdb_en == 1) {
4648 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
9c6ccc03
LO		 4649 if (hr_qp->rdb_en == 1)
4650 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
0425e3e6
YL		 4651 } else {
4652 dev_warn(hr_dev->dev, "flush cqe is unsupported in userspace!\n");
4653 return;
4654 }
4655 }
4656
4657 attr_mask = IB_QP_STATE;
4658 attr.qp_state = IB_QPS_ERR;
4659 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, attr_mask,
4660 hr_qp->state, IB_QPS_ERR);
4661 if (ret)
4662 dev_err(hr_dev->dev, "failed to modify qp %d to err state.\n",
4663 qpn);
4664}
4665
4666static void hns_roce_irq_work_handle(struct work_struct *work)
4667{
4668 struct hns_roce_work *irq_work =
4669 container_of(work, struct hns_roce_work, work);
b00a92c8 4670 struct device *dev = irq_work->hr_dev->dev;
0425e3e6 4671 u32 qpn = irq_work->qpn;
b00a92c8 4672 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4673
4674 switch (irq_work->event_type) {
b00a92c8 4675 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4676 dev_info(dev, "Path migrated succeeded.\n");
4677 break;
4678 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4679 dev_warn(dev, "Path migration failed.\n");
4680 break;
4681 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4682 dev_info(dev, "Communication established.\n");
4683 break;
4684 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4685 dev_warn(dev, "Send queue drained.\n");
4686 break;
0425e3e6 4687 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
e95c716c
YL		 4688 dev_err(dev, "Local work queue 0x%x catas error, sub_type:%d\n",
4689 qpn, irq_work->sub_type);
b00a92c8 4690 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
b00a92c8 4691 break;
0425e3e6 4692 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
e95c716c
YL		 4693 dev_err(dev, "Invalid request local work queue 0x%x error.\n",
4694 qpn);
b00a92c8 4695 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4696 break;
0425e3e6 4697 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
e95c716c
YL		 4698 dev_err(dev, "Local access violation work queue 0x%x error, sub_type:%d\n",
4699 qpn, irq_work->sub_type);
0425e3e6 4700 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
b00a92c8 4701 break;
4702 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4703 dev_warn(dev, "SRQ limit reach.\n");
4704 break;
4705 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4706 dev_warn(dev, "SRQ last wqe reach.\n");
4707 break;
4708 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4709 dev_err(dev, "SRQ catas error.\n");
4710 break;
4711 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4712 dev_err(dev, "CQ 0x%x access err.\n", cqn);
4713 break;
4714 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4715 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4716 break;
4717 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4718 dev_warn(dev, "DB overflow.\n");
4719 break;
4720 case HNS_ROCE_EVENT_TYPE_FLR:
4721 dev_warn(dev, "Function level reset.\n");
0425e3e6
YL		 4722 break;
4723 default:
4724 break;
4725 }
4726
4727 kfree(irq_work);
4728}
4729
4730static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4731 struct hns_roce_eq *eq,
4732 u32 qpn, u32 cqn)
0425e3e6
YL		 4733{
4734 struct hns_roce_work *irq_work;
4735
4736 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4737 if (!irq_work)
4738 return;
4739
4740 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4741 irq_work->hr_dev = hr_dev;
4742 irq_work->qpn = qpn;
b00a92c8 4743 irq_work->cqn = cqn;
0425e3e6
YL		 4744 irq_work->event_type = eq->event_type;
4745 irq_work->sub_type = eq->sub_type;
4746 queue_work(hr_dev->irq_workq, &(irq_work->work));
4747}
4748
a5073d60
YL		 4749static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4750{
d3743fa9 4751 struct hns_roce_dev *hr_dev = eq->hr_dev;
a5073d60
YL		 4752 u32 doorbell[2];
4753
4754 doorbell[0] = 0;
4755 doorbell[1] = 0;
4756
4757 if (eq->type_flag == HNS_ROCE_AEQ) {
4758 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4759 HNS_ROCE_V2_EQ_DB_CMD_S,
4760 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4761 HNS_ROCE_EQ_DB_CMD_AEQ :
4762 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4763 } else {
4764 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4765 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4766
4767 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4768 HNS_ROCE_V2_EQ_DB_CMD_S,
4769 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4770 HNS_ROCE_EQ_DB_CMD_CEQ :
4771 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4772 }
4773
4774 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4775 HNS_ROCE_V2_EQ_DB_PARA_S,
4776 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4777
d3743fa9 4778 hns_roce_write64(hr_dev, doorbell, eq->doorbell);
a5073d60
YL		 4779}
4780
a5073d60
YL		 4781static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry)
4782{
4783 u32 buf_chk_sz;
4784 unsigned long off;
4785
4786 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4787 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4788
4789 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) +
4790 off % buf_chk_sz);
4791}
4792
4793static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry)
4794{
4795 u32 buf_chk_sz;
4796 unsigned long off;
4797
4798 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4799
4800 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4801
4802 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4803 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) +
4804 off % buf_chk_sz);
4805 else
4806 return (struct hns_roce_aeqe *)((u8 *)
4807 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz);
4808}
4809
4810static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4811{
4812 struct hns_roce_aeqe *aeqe;
4813
4814 if (!eq->hop_num)
4815 aeqe = get_aeqe_v2(eq, eq->cons_index);
4816 else
4817 aeqe = mhop_get_aeqe(eq, eq->cons_index);
4818
4819 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4820 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4821}
4822
4823static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4824 struct hns_roce_eq *eq)
4825{
4826 struct device *dev = hr_dev->dev;
4827 struct hns_roce_aeqe *aeqe;
4828 int aeqe_found = 0;
4829 int event_type;
0425e3e6 4830 int sub_type;
81fce629 4831 u32 srqn;
0425e3e6
YL		 4832 u32 qpn;
4833 u32 cqn;
a5073d60
YL		 4834
4835 while ((aeqe = next_aeqe_sw_v2(eq))) {
4044a3f4
YL		 4836
4837 /* Make sure we read AEQ entry after we have checked the
4838 * ownership bit
4839 */
4840 dma_rmb();
a5073d60
YL		 4841
4842 event_type = roce_get_field(aeqe->asyn,
4843 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
4844 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 4845 sub_type = roce_get_field(aeqe->asyn,
4846 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
4847 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
4848 qpn = roce_get_field(aeqe->event.qp_event.qp,
4849 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4850 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4851 cqn = roce_get_field(aeqe->event.cq_event.cq,
4852 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4853 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
81fce629
LO		 4854 srqn = roce_get_field(aeqe->event.srq_event.srq,
4855 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4856 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 4857
4858 switch (event_type) {
4859 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 4860 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 4861 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4862 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4863 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
81fce629 4864 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
a5073d60
YL		 4865 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4866 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4867 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 4868 break;
4869 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
a5073d60 4870 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
81fce629 4871 hns_roce_srq_event(hr_dev, srqn, event_type);
a5073d60
YL		 4872 break;
4873 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4874 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 4875 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 4876 break;
4877 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 4878 break;
4879 case HNS_ROCE_EVENT_TYPE_MB:
4880 hns_roce_cmd_event(hr_dev,
4881 le16_to_cpu(aeqe->event.cmd.token),
4882 aeqe->event.cmd.status,
4883 le64_to_cpu(aeqe->event.cmd.out_param));
4884 break;
4885 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 4886 break;
4887 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 4888 break;
4889 default:
4890 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4891 event_type, eq->eqn, eq->cons_index);
4892 break;
790b57f6 4893 }
a5073d60 4894
0425e3e6
YL		 4895 eq->event_type = event_type;
4896 eq->sub_type = sub_type;
a5073d60
YL		 4897 ++eq->cons_index;
4898 aeqe_found = 1;
4899
4900 if (eq->cons_index > (2 * eq->entries - 1)) {
4901 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4902 eq->cons_index = 0;
4903 }
b00a92c8 4904 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
a5073d60
YL		 4905 }
4906
4907 set_eq_cons_index_v2(eq);
4908 return aeqe_found;
4909}
4910
4911static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry)
4912{
4913 u32 buf_chk_sz;
4914 unsigned long off;
4915
4916 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4917 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4918
4919 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) +
4920 off % buf_chk_sz);
4921}
4922
4923static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry)
4924{
4925 u32 buf_chk_sz;
4926 unsigned long off;
4927
4928 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4929
4930 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4931
4932 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4933 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) +
4934 off % buf_chk_sz);
4935 else
4936 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off /
4937 buf_chk_sz]) + off % buf_chk_sz);
4938}
4939
4940static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
4941{
4942 struct hns_roce_ceqe *ceqe;
4943
4944 if (!eq->hop_num)
4945 ceqe = get_ceqe_v2(eq, eq->cons_index);
4946 else
4947 ceqe = mhop_get_ceqe(eq, eq->cons_index);
4948
4949 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
4950 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4951}
4952
4953static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
4954 struct hns_roce_eq *eq)
4955{
4956 struct device *dev = hr_dev->dev;
4957 struct hns_roce_ceqe *ceqe;
4958 int ceqe_found = 0;
4959 u32 cqn;
4960
4961 while ((ceqe = next_ceqe_sw_v2(eq))) {
4962
4044a3f4
YL		 4963 /* Make sure we read CEQ entry after we have checked the
4964 * ownership bit
4965 */
4966 dma_rmb();
4967
a5073d60
YL		 4968 cqn = roce_get_field(ceqe->comp,
4969 HNS_ROCE_V2_CEQE_COMP_CQN_M,
4970 HNS_ROCE_V2_CEQE_COMP_CQN_S);
4971
4972 hns_roce_cq_completion(hr_dev, cqn);
4973
4974 ++eq->cons_index;
4975 ceqe_found = 1;
4976
4977 if (eq->cons_index > (2 * eq->entries - 1)) {
4978 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4979 eq->cons_index = 0;
4980 }
4981 }
4982
4983 set_eq_cons_index_v2(eq);
4984
4985 return ceqe_found;
4986}
4987
4988static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
4989{
4990 struct hns_roce_eq *eq = eq_ptr;
4991 struct hns_roce_dev *hr_dev = eq->hr_dev;
4992 int int_work = 0;
4993
4994 if (eq->type_flag == HNS_ROCE_CEQ)
4995 /* Completion event interrupt */
4996 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
4997 else
4998 /* Asychronous event interrupt */
4999 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5000
5001 return IRQ_RETVAL(int_work);
5002}
5003
5004static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5005{
5006 struct hns_roce_dev *hr_dev = dev_id;
5007 struct device *dev = hr_dev->dev;
5008 int int_work = 0;
5009 u32 int_st;
5010 u32 int_en;
5011
5012 /* Abnormal interrupt */
5013 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5014 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5015
5016 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
2b9acb9a
XT		 5017 struct pci_dev *pdev = hr_dev->pci_dev;
5018 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5019 const struct hnae3_ae_ops *ops = ae_dev->ops;
5020
a5073d60
YL		 5021 dev_err(dev, "AEQ overflow!\n");
5022
5023 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
5024 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5025
2b9acb9a
XT		 5026 /* Set reset level for reset_event() */
5027 if (ops->set_default_reset_request)
5028 ops->set_default_reset_request(ae_dev,
5029 HNAE3_FUNC_RESET);
5030 if (ops->reset_event)
5031 ops->reset_event(pdev, NULL);
5032
a5073d60
YL		 5033 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
5034 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5035
5036 int_work = 1;
5037 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
5038 dev_err(dev, "BUS ERR!\n");
5039
5040 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
5041 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5042
a5073d60
YL		 5043 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
5044 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5045
5046 int_work = 1;
5047 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
5048 dev_err(dev, "OTHER ERR!\n");
5049
5050 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
5051 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5052
a5073d60
YL		 5053 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
5054 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5055
5056 int_work = 1;
5057 } else
5058 dev_err(dev, "There is no abnormal irq found!\n");
5059
5060 return IRQ_RETVAL(int_work);
5061}
5062
5063static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5064 int eq_num, int enable_flag)
5065{
5066 int i;
5067
5068 if (enable_flag == EQ_ENABLE) {
5069 for (i = 0; i < eq_num; i++)
5070 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5071 i * EQ_REG_OFFSET,
5072 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
5073
5074 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5075 HNS_ROCE_V2_VF_ABN_INT_EN_M);
5076 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5077 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
5078 } else {
5079 for (i = 0; i < eq_num; i++)
5080 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5081 i * EQ_REG_OFFSET,
5082 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
5083
5084 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5085 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
5086 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5087 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
5088 }
5089}
5090
5091static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5092{
5093 struct device *dev = hr_dev->dev;
5094 int ret;
5095
5096 if (eqn < hr_dev->caps.num_comp_vectors)
5097 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5098 0, HNS_ROCE_CMD_DESTROY_CEQC,
5099 HNS_ROCE_CMD_TIMEOUT_MSECS);
5100 else
5101 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5102 0, HNS_ROCE_CMD_DESTROY_AEQC,
5103 HNS_ROCE_CMD_TIMEOUT_MSECS);
5104 if (ret)
5105 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5106}
5107
5108static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev,
5109 struct hns_roce_eq *eq)
5110{
5111 struct device *dev = hr_dev->dev;
5112 u64 idx;
5113 u64 size;
5114 u32 buf_chk_sz;
5115 u32 bt_chk_sz;
5116 u32 mhop_num;
5117 int eqe_alloc;
a5073d60
YL		 5118 int i = 0;
5119 int j = 0;
5120
5121 mhop_num = hr_dev->caps.eqe_hop_num;
5122 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5123 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
a5073d60
YL		 5124
5125 /* hop_num = 0 */
5126 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
5127 dma_free_coherent(dev, (unsigned int)(eq->entries *
5128 eq->eqe_size), eq->bt_l0, eq->l0_dma);
5129 return;
5130 }
5131
5132 /* hop_num = 1 or hop = 2 */
5133 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5134 if (mhop_num == 1) {
5135 for (i = 0; i < eq->l0_last_num; i++) {
5136 if (i == eq->l0_last_num - 1) {
5137 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
5138 size = (eq->entries - eqe_alloc) * eq->eqe_size;
5139 dma_free_coherent(dev, size, eq->buf[i],
5140 eq->buf_dma[i]);
5141 break;
5142 }
5143 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
5144 eq->buf_dma[i]);
5145 }
5146 } else if (mhop_num == 2) {
5147 for (i = 0; i < eq->l0_last_num; i++) {
5148 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5149 eq->l1_dma[i]);
5150
5151 for (j = 0; j < bt_chk_sz / 8; j++) {
5152 idx = i * (bt_chk_sz / 8) + j;
5153 if ((i == eq->l0_last_num - 1)
5154 && j == eq->l1_last_num - 1) {
5155 eqe_alloc = (buf_chk_sz / eq->eqe_size)
5156 * idx;
5157 size = (eq->entries - eqe_alloc)
5158 * eq->eqe_size;
5159 dma_free_coherent(dev, size,
5160 eq->buf[idx],
5161 eq->buf_dma[idx]);
5162 break;
5163 }
5164 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
5165 eq->buf_dma[idx]);
5166 }
5167 }
5168 }
5169 kfree(eq->buf_dma);
5170 kfree(eq->buf);
5171 kfree(eq->l1_dma);
5172 kfree(eq->bt_l1);
5173 eq->buf_dma = NULL;
5174 eq->buf = NULL;
5175 eq->l1_dma = NULL;
5176 eq->bt_l1 = NULL;
5177}
5178
5179static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev,
5180 struct hns_roce_eq *eq)
5181{
5182 u32 buf_chk_sz;
5183
5184 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
5185
5186 if (hr_dev->caps.eqe_hop_num) {
5187 hns_roce_mhop_free_eq(hr_dev, eq);
5188 return;
5189 }
5190
5191 if (eq->buf_list)
5192 dma_free_coherent(hr_dev->dev, buf_chk_sz,
5193 eq->buf_list->buf, eq->buf_list->map);
5194}
5195
5196static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
5197 struct hns_roce_eq *eq,
5198 void *mb_buf)
5199{
5200 struct hns_roce_eq_context *eqc;
5201
5202 eqc = mb_buf;
5203 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5204
5205 /* init eqc */
5206 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
5207 eq->hop_num = hr_dev->caps.eqe_hop_num;
5208 eq->cons_index = 0;
5209 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5210 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5211 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
5212 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz;
5213 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz;
5214 eq->shift = ilog2((unsigned int)eq->entries);
5215
5216 if (!eq->hop_num)
5217 eq->eqe_ba = eq->buf_list->map;
5218 else
5219 eq->eqe_ba = eq->l0_dma;
5220
5221 /* set eqc state */
5222 roce_set_field(eqc->byte_4,
5223 HNS_ROCE_EQC_EQ_ST_M,
5224 HNS_ROCE_EQC_EQ_ST_S,
5225 HNS_ROCE_V2_EQ_STATE_VALID);
5226
5227 /* set eqe hop num */
5228 roce_set_field(eqc->byte_4,
5229 HNS_ROCE_EQC_HOP_NUM_M,
5230 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
5231
5232 /* set eqc over_ignore */
5233 roce_set_field(eqc->byte_4,
5234 HNS_ROCE_EQC_OVER_IGNORE_M,
5235 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
5236
5237 /* set eqc coalesce */
5238 roce_set_field(eqc->byte_4,
5239 HNS_ROCE_EQC_COALESCE_M,
5240 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
5241
5242 /* set eqc arm_state */
5243 roce_set_field(eqc->byte_4,
5244 HNS_ROCE_EQC_ARM_ST_M,
5245 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
5246
5247 /* set eqn */
5248 roce_set_field(eqc->byte_4,
5249 HNS_ROCE_EQC_EQN_M,
5250 HNS_ROCE_EQC_EQN_S, eq->eqn);
5251
5252 /* set eqe_cnt */
5253 roce_set_field(eqc->byte_4,
5254 HNS_ROCE_EQC_EQE_CNT_M,
5255 HNS_ROCE_EQC_EQE_CNT_S,
5256 HNS_ROCE_EQ_INIT_EQE_CNT);
5257
5258 /* set eqe_ba_pg_sz */
5259 roce_set_field(eqc->byte_8,
5260 HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db
YL		 5261 HNS_ROCE_EQC_BA_PG_SZ_S,
5262 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 5263
5264 /* set eqe_buf_pg_sz */
5265 roce_set_field(eqc->byte_8,
5266 HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db
YL		 5267 HNS_ROCE_EQC_BUF_PG_SZ_S,
5268 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 5269
5270 /* set eq_producer_idx */
5271 roce_set_field(eqc->byte_8,
5272 HNS_ROCE_EQC_PROD_INDX_M,
5273 HNS_ROCE_EQC_PROD_INDX_S,
5274 HNS_ROCE_EQ_INIT_PROD_IDX);
5275
5276 /* set eq_max_cnt */
5277 roce_set_field(eqc->byte_12,
5278 HNS_ROCE_EQC_MAX_CNT_M,
5279 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
5280
5281 /* set eq_period */
5282 roce_set_field(eqc->byte_12,
5283 HNS_ROCE_EQC_PERIOD_M,
5284 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
5285
5286 /* set eqe_report_timer */
5287 roce_set_field(eqc->eqe_report_timer,
5288 HNS_ROCE_EQC_REPORT_TIMER_M,
5289 HNS_ROCE_EQC_REPORT_TIMER_S,
5290 HNS_ROCE_EQ_INIT_REPORT_TIMER);
5291
5292 /* set eqe_ba [34:3] */
5293 roce_set_field(eqc->eqe_ba0,
5294 HNS_ROCE_EQC_EQE_BA_L_M,
5295 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3);
5296
5297 /* set eqe_ba [64:35] */
5298 roce_set_field(eqc->eqe_ba1,
5299 HNS_ROCE_EQC_EQE_BA_H_M,
5300 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35);
5301
5302 /* set eq shift */
5303 roce_set_field(eqc->byte_28,
5304 HNS_ROCE_EQC_SHIFT_M,
5305 HNS_ROCE_EQC_SHIFT_S, eq->shift);
5306
5307 /* set eq MSI_IDX */
5308 roce_set_field(eqc->byte_28,
5309 HNS_ROCE_EQC_MSI_INDX_M,
5310 HNS_ROCE_EQC_MSI_INDX_S,
5311 HNS_ROCE_EQ_INIT_MSI_IDX);
5312
5313 /* set cur_eqe_ba [27:12] */
5314 roce_set_field(eqc->byte_28,
5315 HNS_ROCE_EQC_CUR_EQE_BA_L_M,
5316 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12);
5317
5318 /* set cur_eqe_ba [59:28] */
5319 roce_set_field(eqc->byte_32,
5320 HNS_ROCE_EQC_CUR_EQE_BA_M_M,
5321 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28);
5322
5323 /* set cur_eqe_ba [63:60] */
5324 roce_set_field(eqc->byte_36,
5325 HNS_ROCE_EQC_CUR_EQE_BA_H_M,
5326 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60);
5327
5328 /* set eq consumer idx */
5329 roce_set_field(eqc->byte_36,
5330 HNS_ROCE_EQC_CONS_INDX_M,
5331 HNS_ROCE_EQC_CONS_INDX_S,
5332 HNS_ROCE_EQ_INIT_CONS_IDX);
5333
5334 /* set nex_eqe_ba[43:12] */
5335 roce_set_field(eqc->nxt_eqe_ba0,
5336 HNS_ROCE_EQC_NXT_EQE_BA_L_M,
5337 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12);
5338
5339 /* set nex_eqe_ba[63:44] */
5340 roce_set_field(eqc->nxt_eqe_ba1,
5341 HNS_ROCE_EQC_NXT_EQE_BA_H_M,
5342 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44);
5343}
5344
5345static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev,
5346 struct hns_roce_eq *eq)
5347{
5348 struct device *dev = hr_dev->dev;
5349 int eq_alloc_done = 0;
5350 int eq_buf_cnt = 0;
5351 int eqe_alloc;
5352 u32 buf_chk_sz;
5353 u32 bt_chk_sz;
5354 u32 mhop_num;
5355 u64 size;
5356 u64 idx;
5357 int ba_num;
5358 int bt_num;
5359 int record_i;
5360 int record_j;
5361 int i = 0;
5362 int j = 0;
5363
5364 mhop_num = hr_dev->caps.eqe_hop_num;
5365 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5366 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
5367
5368 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1)
5369 / buf_chk_sz;
5370 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8);
5371
5372 /* hop_num = 0 */
5373 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
5374 if (eq->entries > buf_chk_sz / eq->eqe_size) {
5375 dev_err(dev, "eq entries %d is larger than buf_pg_sz!",
5376 eq->entries);
5377 return -EINVAL;
5378 }
5379 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size,
5380 &(eq->l0_dma), GFP_KERNEL);
5381 if (!eq->bt_l0)
5382 return -ENOMEM;
5383
5384 eq->cur_eqe_ba = eq->l0_dma;
5385 eq->nxt_eqe_ba = 0;
5386
5387 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size);
5388
5389 return 0;
5390 }
5391
5392 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL);
5393 if (!eq->buf_dma)
5394 return -ENOMEM;
5395 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL);
5396 if (!eq->buf)
5397 goto err_kcalloc_buf;
5398
5399 if (mhop_num == 2) {
5400 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL);
5401 if (!eq->l1_dma)
5402 goto err_kcalloc_l1_dma;
5403
5404 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL);
5405 if (!eq->bt_l1)
5406 goto err_kcalloc_bt_l1;
5407 }
5408
5409 /* alloc L0 BT */
5410 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL);
5411 if (!eq->bt_l0)
5412 goto err_dma_alloc_l0;
5413
5414 if (mhop_num == 1) {
5415 if (ba_num > (bt_chk_sz / 8))
5416 dev_err(dev, "ba_num %d is too large for 1 hop\n",
5417 ba_num);
5418
5419 /* alloc buf */
5420 for (i = 0; i < bt_chk_sz / 8; i++) {
5421 if (eq_buf_cnt + 1 < ba_num) {
5422 size = buf_chk_sz;
5423 } else {
5424 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
5425 size = (eq->entries - eqe_alloc) * eq->eqe_size;
5426 }
750afb08 5427 eq->buf[i] = dma_alloc_coherent(dev, size,
a5073d60
YL		 5428 &(eq->buf_dma[i]),
5429 GFP_KERNEL);
5430 if (!eq->buf[i])
5431 goto err_dma_alloc_buf;
5432
a5073d60
YL		 5433 *(eq->bt_l0 + i) = eq->buf_dma[i];
5434
5435 eq_buf_cnt++;
5436 if (eq_buf_cnt >= ba_num)
5437 break;
5438 }
5439 eq->cur_eqe_ba = eq->buf_dma[0];
5440 eq->nxt_eqe_ba = eq->buf_dma[1];
5441
5442 } else if (mhop_num == 2) {
5443 /* alloc L1 BT and buf */
5444 for (i = 0; i < bt_chk_sz / 8; i++) {
5445 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz,
5446 &(eq->l1_dma[i]),
5447 GFP_KERNEL);
5448 if (!eq->bt_l1[i])
5449 goto err_dma_alloc_l1;
5450 *(eq->bt_l0 + i) = eq->l1_dma[i];
5451
5452 for (j = 0; j < bt_chk_sz / 8; j++) {
5453 idx = i * bt_chk_sz / 8 + j;
5454 if (eq_buf_cnt + 1 < ba_num) {
5455 size = buf_chk_sz;
5456 } else {
5457 eqe_alloc = (buf_chk_sz / eq->eqe_size)
5458 * idx;
5459 size = (eq->entries - eqe_alloc)
5460 * eq->eqe_size;
5461 }
750afb08
LC		 5462 eq->buf[idx] = dma_alloc_coherent(dev, size,
5463 &(eq->buf_dma[idx]),
5464 GFP_KERNEL);
a5073d60
YL		 5465 if (!eq->buf[idx])
5466 goto err_dma_alloc_buf;
5467
a5073d60
YL		 5468 *(eq->bt_l1[i] + j) = eq->buf_dma[idx];
5469
5470 eq_buf_cnt++;
5471 if (eq_buf_cnt >= ba_num) {
5472 eq_alloc_done = 1;
5473 break;
5474 }
5475 }
5476
5477 if (eq_alloc_done)
5478 break;
5479 }
5480 eq->cur_eqe_ba = eq->buf_dma[0];
5481 eq->nxt_eqe_ba = eq->buf_dma[1];
5482 }
5483
5484 eq->l0_last_num = i + 1;
5485 if (mhop_num == 2)
5486 eq->l1_last_num = j + 1;
5487
5488 return 0;
5489
5490err_dma_alloc_l1:
5491 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5492 eq->bt_l0 = NULL;
5493 eq->l0_dma = 0;
5494 for (i -= 1; i >= 0; i--) {
5495 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5496 eq->l1_dma[i]);
5497
5498 for (j = 0; j < bt_chk_sz / 8; j++) {
5499 idx = i * bt_chk_sz / 8 + j;
5500 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
5501 eq->buf_dma[idx]);
5502 }
5503 }
5504 goto err_dma_alloc_l0;
5505
5506err_dma_alloc_buf:
5507 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5508 eq->bt_l0 = NULL;
5509 eq->l0_dma = 0;
5510
5511 if (mhop_num == 1)
38759d61 5512 for (i -= 1; i >= 0; i--)
a5073d60
YL		 5513 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
5514 eq->buf_dma[i]);
5515 else if (mhop_num == 2) {
5516 record_i = i;
5517 record_j = j;
5518 for (; i >= 0; i--) {
5519 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5520 eq->l1_dma[i]);
5521
5522 for (j = 0; j < bt_chk_sz / 8; j++) {
5523 if (i == record_i && j >= record_j)
5524 break;
5525
5526 idx = i * bt_chk_sz / 8 + j;
5527 dma_free_coherent(dev, buf_chk_sz,
5528 eq->buf[idx],
5529 eq->buf_dma[idx]);
5530 }
5531 }
5532 }
5533
5534err_dma_alloc_l0:
5535 kfree(eq->bt_l1);
5536 eq->bt_l1 = NULL;
5537
5538err_kcalloc_bt_l1:
5539 kfree(eq->l1_dma);
5540 eq->l1_dma = NULL;
5541
5542err_kcalloc_l1_dma:
5543 kfree(eq->buf);
5544 eq->buf = NULL;
5545
5546err_kcalloc_buf:
5547 kfree(eq->buf_dma);
5548 eq->buf_dma = NULL;
5549
5550 return -ENOMEM;
5551}
5552
5553static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5554 struct hns_roce_eq *eq,
5555 unsigned int eq_cmd)
5556{
5557 struct device *dev = hr_dev->dev;
5558 struct hns_roce_cmd_mailbox *mailbox;
5559 u32 buf_chk_sz = 0;
5560 int ret;
5561
5562 /* Allocate mailbox memory */
5563 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5564 if (IS_ERR(mailbox))
5565 return PTR_ERR(mailbox);
5566
5567 if (!hr_dev->caps.eqe_hop_num) {
5568 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5569
5570 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list),
5571 GFP_KERNEL);
5572 if (!eq->buf_list) {
5573 ret = -ENOMEM;
5574 goto free_cmd_mbox;
5575 }
5576
750afb08 5577 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz,
a5073d60
YL		 5578 &(eq->buf_list->map),
5579 GFP_KERNEL);
5580 if (!eq->buf_list->buf) {
5581 ret = -ENOMEM;
5582 goto err_alloc_buf;
5583 }
5584
a5073d60
YL		 5585 } else {
5586 ret = hns_roce_mhop_alloc_eq(hr_dev, eq);
5587 if (ret) {
5588 ret = -ENOMEM;
5589 goto free_cmd_mbox;
5590 }
5591 }
5592
5593 hns_roce_config_eqc(hr_dev, eq, mailbox->buf);
5594
5595 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5596 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5597 if (ret) {
ab178849 5598 dev_err(dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5599 goto err_cmd_mbox;
5600 }
5601
5602 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5603
5604 return 0;
5605
5606err_cmd_mbox:
5607 if (!hr_dev->caps.eqe_hop_num)
5608 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf,
5609 eq->buf_list->map);
5610 else {
5611 hns_roce_mhop_free_eq(hr_dev, eq);
5612 goto free_cmd_mbox;
5613 }
5614
5615err_alloc_buf:
5616 kfree(eq->buf_list);
5617
5618free_cmd_mbox:
5619 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5620
5621 return ret;
5622}
5623
5624static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5625{
5626 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5627 struct device *dev = hr_dev->dev;
5628 struct hns_roce_eq *eq;
5629 unsigned int eq_cmd;
5630 int irq_num;
5631 int eq_num;
5632 int other_num;
5633 int comp_num;
5634 int aeq_num;
5635 int i, j, k;
5636 int ret;
5637
5638 other_num = hr_dev->caps.num_other_vectors;
5639 comp_num = hr_dev->caps.num_comp_vectors;
5640 aeq_num = hr_dev->caps.num_aeq_vectors;
5641
5642 eq_num = comp_num + aeq_num;
5643 irq_num = eq_num + other_num;
5644
5645 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5646 if (!eq_table->eq)
5647 return -ENOMEM;
5648
5649 for (i = 0; i < irq_num; i++) {
5650 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5651 GFP_KERNEL);
5652 if (!hr_dev->irq_names[i]) {
5653 ret = -ENOMEM;
5654 goto err_failed_kzalloc;
5655 }
5656 }
5657
5658 /* create eq */
5659 for (j = 0; j < eq_num; j++) {
5660 eq = &eq_table->eq[j];
5661 eq->hr_dev = hr_dev;
5662 eq->eqn = j;
5663 if (j < comp_num) {
5664 /* CEQ */
5665 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5666 eq->type_flag = HNS_ROCE_CEQ;
5667 eq->entries = hr_dev->caps.ceqe_depth;
5668 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
5669 eq->irq = hr_dev->irq[j + other_num + aeq_num];
5670 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5671 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5672 } else {
5673 /* AEQ */
5674 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5675 eq->type_flag = HNS_ROCE_AEQ;
5676 eq->entries = hr_dev->caps.aeqe_depth;
5677 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
5678 eq->irq = hr_dev->irq[j - comp_num + other_num];
5679 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5680 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5681 }
5682
5683 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5684 if (ret) {
5685 dev_err(dev, "eq create failed.\n");
5686 goto err_create_eq_fail;
5687 }
5688 }
5689
5690 /* enable irq */
5691 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5692
5693 /* irq contains: abnormal + AEQ + CEQ*/
5694 for (k = 0; k < irq_num; k++)
5695 if (k < other_num)
5696 snprintf((char *)hr_dev->irq_names[k],
5697 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k);
5698 else if (k < (other_num + aeq_num))
5699 snprintf((char *)hr_dev->irq_names[k],
5700 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d",
5701 k - other_num);
5702 else
5703 snprintf((char *)hr_dev->irq_names[k],
5704 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d",
5705 k - other_num - aeq_num);
5706
5707 for (k = 0; k < irq_num; k++) {
5708 if (k < other_num)
5709 ret = request_irq(hr_dev->irq[k],
5710 hns_roce_v2_msix_interrupt_abn,
5711 0, hr_dev->irq_names[k], hr_dev);
5712
5713 else if (k < (other_num + comp_num))
5714 ret = request_irq(eq_table->eq[k - other_num].irq,
5715 hns_roce_v2_msix_interrupt_eq,
5716 0, hr_dev->irq_names[k + aeq_num],
5717 &eq_table->eq[k - other_num]);
5718 else
5719 ret = request_irq(eq_table->eq[k - other_num].irq,
5720 hns_roce_v2_msix_interrupt_eq,
5721 0, hr_dev->irq_names[k - comp_num],
5722 &eq_table->eq[k - other_num]);
5723 if (ret) {
5724 dev_err(dev, "Request irq error!\n");
5725 goto err_request_irq_fail;
5726 }
5727 }
5728
0425e3e6
YL		 5729 hr_dev->irq_workq =
5730 create_singlethread_workqueue("hns_roce_irq_workqueue");
5731 if (!hr_dev->irq_workq) {
5732 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5733 ret = -ENOMEM;
0425e3e6
YL		 5734 goto err_request_irq_fail;
5735 }
5736
a5073d60
YL		 5737 return 0;
5738
5739err_request_irq_fail:
5740 for (k -= 1; k >= 0; k--)
5741 if (k < other_num)
5742 free_irq(hr_dev->irq[k], hr_dev);
5743 else
5744 free_irq(eq_table->eq[k - other_num].irq,
5745 &eq_table->eq[k - other_num]);
5746
5747err_create_eq_fail:
5748 for (j -= 1; j >= 0; j--)
5749 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]);
5750
5751err_failed_kzalloc:
5752 for (i -= 1; i >= 0; i--)
5753 kfree(hr_dev->irq_names[i]);
5754 kfree(eq_table->eq);
5755
5756 return ret;
5757}
5758
5759static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5760{
5761 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5762 int irq_num;
5763 int eq_num;
5764 int i;
5765
5766 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5767 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5768
5769 /* Disable irq */
5770 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5771
5772 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5773 free_irq(hr_dev->irq[i], hr_dev);
5774
5775 for (i = 0; i < eq_num; i++) {
5776 hns_roce_v2_destroy_eqc(hr_dev, i);
5777
5778 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]);
5779
5780 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]);
5781 }
5782
5783 for (i = 0; i < irq_num; i++)
5784 kfree(hr_dev->irq_names[i]);
5785
5786 kfree(eq_table->eq);
0425e3e6
YL		 5787
5788 flush_workqueue(hr_dev->irq_workq);
5789 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5790}
5791
c7bcb134
LO		 5792static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
5793 struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
5794 u32 cqn, void *mb_buf, u64 *mtts_wqe,
5795 u64 *mtts_idx, dma_addr_t dma_handle_wqe,
5796 dma_addr_t dma_handle_idx)
5797{
5798 struct hns_roce_srq_context *srq_context;
5799
5800 srq_context = mb_buf;
5801 memset(srq_context, 0, sizeof(*srq_context));
5802
5803 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M,
5804 SRQC_BYTE_4_SRQ_ST_S, 1);
5805
5806 roce_set_field(srq_context->byte_4_srqn_srqst,
5807 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M,
5808 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S,
5809 (hr_dev->caps.srqwqe_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5810 hr_dev->caps.srqwqe_hop_num));
5811 roce_set_field(srq_context->byte_4_srqn_srqst,
5812 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S,
5813 ilog2(srq->max));
5814
5815 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M,
5816 SRQC_BYTE_4_SRQN_S, srq->srqn);
5817
5818 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5819 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5820
5821 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
5822 SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
5823
5824 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));
5825
5826 roce_set_field(srq_context->byte_24_wqe_bt_ba,
5827 SRQC_BYTE_24_SRQ_WQE_BT_BA_M,
5828 SRQC_BYTE_24_SRQ_WQE_BT_BA_S,
5829 cpu_to_le32(dma_handle_wqe >> 35));
5830
5831 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
5832 SRQC_BYTE_28_PD_S, pdn);
5833 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
5834 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
5835 fls(srq->max_gs - 1));
5836
5837 srq_context->idx_bt_ba = (u32)(dma_handle_idx >> 3);
5838 srq_context->idx_bt_ba = cpu_to_le32(srq_context->idx_bt_ba);
5839 roce_set_field(srq_context->rsv_idx_bt_ba,
5840 SRQC_BYTE_36_SRQ_IDX_BT_BA_M,
5841 SRQC_BYTE_36_SRQ_IDX_BT_BA_S,
5842 cpu_to_le32(dma_handle_idx >> 35));
5843
5844 srq_context->idx_cur_blk_addr = (u32)(mtts_idx[0] >> PAGE_ADDR_SHIFT);
5845 srq_context->idx_cur_blk_addr =
5846 cpu_to_le32(srq_context->idx_cur_blk_addr);
5847 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5848 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M,
5849 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S,
5850 cpu_to_le32((mtts_idx[0]) >> (32 + PAGE_ADDR_SHIFT)));
5851 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5852 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M,
5853 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S,
5854 hr_dev->caps.idx_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5855 hr_dev->caps.idx_hop_num);
5856
5857 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5858 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
5859 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
5860 hr_dev->caps.idx_ba_pg_sz);
5861 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5862 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
5863 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
5864 hr_dev->caps.idx_buf_pg_sz);
5865
5866 srq_context->idx_nxt_blk_addr = (u32)(mtts_idx[1] >> PAGE_ADDR_SHIFT);
5867 srq_context->idx_nxt_blk_addr =
5868 cpu_to_le32(srq_context->idx_nxt_blk_addr);
5869 roce_set_field(srq_context->rsv_idxnxtblkaddr,
5870 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M,
5871 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S,
5872 cpu_to_le32((mtts_idx[1]) >> (32 + PAGE_ADDR_SHIFT)));
5873 roce_set_field(srq_context->byte_56_xrc_cqn,
5874 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
5875 cqn);
5876 roce_set_field(srq_context->byte_56_xrc_cqn,
5877 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
5878 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
5879 hr_dev->caps.srqwqe_ba_pg_sz + PG_SHIFT_OFFSET);
5880 roce_set_field(srq_context->byte_56_xrc_cqn,
5881 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M,
5882 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S,
5883 hr_dev->caps.srqwqe_buf_pg_sz + PG_SHIFT_OFFSET);
5884
5885 roce_set_bit(srq_context->db_record_addr_record_en,
5886 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0);
5887}
5888
5889static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5890 struct ib_srq_attr *srq_attr,
5891 enum ib_srq_attr_mask srq_attr_mask,
5892 struct ib_udata *udata)
5893{
5894 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5895 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5896 struct hns_roce_srq_context *srq_context;
5897 struct hns_roce_srq_context *srqc_mask;
5898 struct hns_roce_cmd_mailbox *mailbox;
5899 int ret;
5900
5901 if (srq_attr_mask & IB_SRQ_LIMIT) {
5902 if (srq_attr->srq_limit >= srq->max)
5903 return -EINVAL;
5904
5905 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5906 if (IS_ERR(mailbox))
5907 return PTR_ERR(mailbox);
5908
5909 srq_context = mailbox->buf;
5910 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5911
5912 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5913
5914 roce_set_field(srq_context->byte_8_limit_wl,
5915 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5916 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit);
5917 roce_set_field(srqc_mask->byte_8_limit_wl,
5918 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5919 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5920
5921 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5922 HNS_ROCE_CMD_MODIFY_SRQC,
5923 HNS_ROCE_CMD_TIMEOUT_MSECS);
5924 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5925 if (ret) {
5926 dev_err(hr_dev->dev,
5927 "MODIFY SRQ Failed to cmd mailbox.\n");
5928 return ret;
5929 }
5930 }
5931
5932 return 0;
5933}
5934
c3c668e7 5935static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
c7bcb134
LO		 5936{
5937 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5938 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5939 struct hns_roce_srq_context *srq_context;
5940 struct hns_roce_cmd_mailbox *mailbox;
5941 int limit_wl;
5942 int ret;
5943
5944 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5945 if (IS_ERR(mailbox))
5946 return PTR_ERR(mailbox);
5947
5948 srq_context = mailbox->buf;
5949 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5950 HNS_ROCE_CMD_QUERY_SRQC,
5951 HNS_ROCE_CMD_TIMEOUT_MSECS);
5952 if (ret) {
5953 dev_err(hr_dev->dev, "QUERY SRQ cmd process error\n");
5954 goto out;
5955 }
5956
5957 limit_wl = roce_get_field(srq_context->byte_8_limit_wl,
5958 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5959 SRQC_BYTE_8_SRQ_LIMIT_WL_S);
5960
5961 attr->srq_limit = limit_wl;
5962 attr->max_wr = srq->max - 1;
5963 attr->max_sge = srq->max_gs;
5964
5965 memcpy(srq_context, mailbox->buf, sizeof(*srq_context));
5966
5967out:
5968 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5969 return ret;
5970}
5971
5972static int find_empty_entry(struct hns_roce_idx_que *idx_que)
5973{
5974 int bit_num;
5975 int i;
5976
5977 /* bitmap[i] is set zero if all bits are allocated */
5978 for (i = 0; idx_que->bitmap[i] == 0; ++i)
5979 ;
5980 bit_num = ffs(idx_que->bitmap[i]);
5981 idx_que->bitmap[i] &= ~(1ULL << (bit_num - 1));
5982
5983 return i * sizeof(u64) * 8 + (bit_num - 1);
5984}
5985
5986static void fill_idx_queue(struct hns_roce_idx_que *idx_que,
5987 int cur_idx, int wqe_idx)
5988{
5989 unsigned int *addr;
5990
5991 addr = (unsigned int *)hns_roce_buf_offset(&idx_que->idx_buf,
5992 cur_idx * idx_que->entry_sz);
5993 *addr = wqe_idx;
5994}
5995
5996static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
5997 const struct ib_recv_wr *wr,
5998 const struct ib_recv_wr **bad_wr)
5999{
d3743fa9 6000 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
c7bcb134
LO		 6001 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
6002 struct hns_roce_v2_wqe_data_seg *dseg;
6003 struct hns_roce_v2_db srq_db;
6004 unsigned long flags;
6005 int ret = 0;
6006 int wqe_idx;
6007 void *wqe;
6008 int nreq;
6009 int ind;
6010 int i;
6011
6012 spin_lock_irqsave(&srq->lock, flags);
6013
6014 ind = srq->head & (srq->max - 1);
6015
6016 for (nreq = 0; wr; ++nreq, wr = wr->next) {
6017 if (unlikely(wr->num_sge > srq->max_gs)) {
6018 ret = -EINVAL;
6019 *bad_wr = wr;
6020 break;
6021 }
6022
6023 if (unlikely(srq->head == srq->tail)) {
6024 ret = -ENOMEM;
6025 *bad_wr = wr;
6026 break;
6027 }
6028
6029 wqe_idx = find_empty_entry(&srq->idx_que);
6030 fill_idx_queue(&srq->idx_que, ind, wqe_idx);
6031 wqe = get_srq_wqe(srq, wqe_idx);
6032 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
6033
6034 for (i = 0; i < wr->num_sge; ++i) {
6035 dseg[i].len = cpu_to_le32(wr->sg_list[i].length);
6036 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey);
6037 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr);
6038 }
6039
6040 if (i < srq->max_gs) {
6041 dseg->len = 0;
6042 dseg->lkey = cpu_to_le32(0x100);
6043 dseg->addr = 0;
6044 }
6045
6046 srq->wrid[wqe_idx] = wr->wr_id;
6047 ind = (ind + 1) & (srq->max - 1);
6048 }
6049
6050 if (likely(nreq)) {
6051 srq->head += nreq;
6052
6053 /*
6054 * Make sure that descriptors are written before
6055 * doorbell record.
6056 */
6057 wmb();
6058
6059 srq_db.byte_4 = HNS_ROCE_V2_SRQ_DB << 24 | srq->srqn;
6060 srq_db.parameter = srq->head;
6061
d3743fa9 6062 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l);
c7bcb134
LO		 6063
6064 }
6065
6066 spin_unlock_irqrestore(&srq->lock, flags);
6067
6068 return ret;
6069}
6070
7f645a58
KH		 6071static const struct ib_device_ops hns_roce_v2_dev_ops = {
6072 .destroy_qp = hns_roce_v2_destroy_qp,
6073 .modify_cq = hns_roce_v2_modify_cq,
6074 .poll_cq = hns_roce_v2_poll_cq,
6075 .post_recv = hns_roce_v2_post_recv,
6076 .post_send = hns_roce_v2_post_send,
6077 .query_qp = hns_roce_v2_query_qp,
6078 .req_notify_cq = hns_roce_v2_req_notify_cq,
6079};
6080
6081static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6082 .modify_srq = hns_roce_v2_modify_srq,
6083 .post_srq_recv = hns_roce_v2_post_srq_recv,
6084 .query_srq = hns_roce_v2_query_srq,
6085};
6086
a04ff739
WHX		 6087static const struct hns_roce_hw hns_roce_hw_v2 = {
6088 .cmq_init = hns_roce_v2_cmq_init,
6089 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 6090 .hw_profile = hns_roce_v2_profile,
6b63597d 6091 .hw_init = hns_roce_v2_init,
6092 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 6093 .post_mbox = hns_roce_v2_post_mbox,
6094 .chk_mbox = hns_roce_v2_chk_mbox,
6a04aed6 6095 .rst_prc_mbox = hns_roce_v2_rst_process_cmd,
7afddafa
WHX		 6096 .set_gid = hns_roce_v2_set_gid,
6097 .set_mac = hns_roce_v2_set_mac,
3958cc56 6098 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 6099 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 6100 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 6101 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 6102 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 6103 .set_hem = hns_roce_v2_set_hem,
6104 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 6105 .modify_qp = hns_roce_v2_modify_qp,
6106 .query_qp = hns_roce_v2_query_qp,
6107 .destroy_qp = hns_roce_v2_destroy_qp,
aa84fa18 6108 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
b156269d 6109 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 6110 .post_send = hns_roce_v2_post_send,
6111 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 6112 .req_notify_cq = hns_roce_v2_req_notify_cq,
6113 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 6114 .init_eq = hns_roce_v2_init_eq_table,
6115 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
c7bcb134
LO		 6116 .write_srqc = hns_roce_v2_write_srqc,
6117 .modify_srq = hns_roce_v2_modify_srq,
6118 .query_srq = hns_roce_v2_query_srq,
6119 .post_srq_recv = hns_roce_v2_post_srq_recv,
7f645a58
KH		 6120 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6121 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
a04ff739 6122};
dd74282d
WHX		 6123
6124static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6125 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6126 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 6127 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6128 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 6129 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6130 /* required last entry */
6131 {0, }
6132};
6133
f97a62c3 6134MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6135
dd74282d
WHX		 6136static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6137 struct hnae3_handle *handle)
6138{
d061effc 6139 struct hns_roce_v2_priv *priv = hr_dev->priv;
a5073d60 6140 int i;
dd74282d 6141
dd74282d 6142 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 6143 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6144 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 6145
6146 /* Get info from NIC driver. */
6147 hr_dev->reg_base = handle->rinfo.roce_io_base;
6148 hr_dev->caps.num_ports = 1;
6149 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6150 hr_dev->iboe.phy_port[0] = 0;
6151
d4994d2f 6152 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6153 hr_dev->iboe.netdevs[0]->dev_addr);
6154
a5073d60
YL		 6155 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
6156 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6157 i + handle->rinfo.base_vector);
6158
dd74282d 6159 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 6160 hr_dev->cmd_mod = 1;
dd74282d
WHX		 6161 hr_dev->loop_idc = 0;
6162
d061effc
WHX		 6163 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6164 priv->handle = handle;
6165
dd74282d
WHX		 6166 return 0;
6167}
6168
d061effc 6169static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
dd74282d
WHX		 6170{
6171 struct hns_roce_dev *hr_dev;
6172 int ret;
6173
459cc69f 6174 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
dd74282d
WHX		 6175 if (!hr_dev)
6176 return -ENOMEM;
6177
a04ff739
WHX		 6178 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6179 if (!hr_dev->priv) {
6180 ret = -ENOMEM;
6181 goto error_failed_kzalloc;
6182 }
6183
dd74282d
WHX		 6184 hr_dev->pci_dev = handle->pdev;
6185 hr_dev->dev = &handle->pdev->dev;
dd74282d
WHX		 6186
6187 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
6188 if (ret) {
6189 dev_err(hr_dev->dev, "Get Configuration failed!\n");
6190 goto error_failed_get_cfg;
6191 }
6192
6193 ret = hns_roce_init(hr_dev);
6194 if (ret) {
6195 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6196 goto error_failed_get_cfg;
6197 }
6198
d061effc
WHX		 6199 handle->priv = hr_dev;
6200
dd74282d
WHX		 6201 return 0;
6202
6203error_failed_get_cfg:
a04ff739
WHX		 6204 kfree(hr_dev->priv);
6205
6206error_failed_kzalloc:
dd74282d
WHX		 6207 ib_dealloc_device(&hr_dev->ib_dev);
6208
6209 return ret;
6210}
6211
d061effc 6212static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
dd74282d
WHX		 6213 bool reset)
6214{
6215 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
6216
cb7a94c9
WHX		 6217 if (!hr_dev)
6218 return;
6219
d061effc 6220 handle->priv = NULL;
dd74282d 6221 hns_roce_exit(hr_dev);
a04ff739 6222 kfree(hr_dev->priv);
dd74282d
WHX		 6223 ib_dealloc_device(&hr_dev->ib_dev);
6224}
6225
d061effc
WHX		 6226static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6227{
6228 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
07c2339a 6229 const struct pci_device_id *id;
d061effc
WHX		 6230 struct device *dev = &handle->pdev->dev;
6231 int ret;
6232
6233 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6234
6235 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6236 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6237 goto reset_chk_err;
6238 }
6239
07c2339a
LO		 6240 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6241 if (!id)
6242 return 0;
6243
d061effc
WHX		 6244 ret = __hns_roce_hw_v2_init_instance(handle);
6245 if (ret) {
6246 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6247 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6248 if (ops->ae_dev_resetting(handle) ||
6249 ops->get_hw_reset_stat(handle))
6250 goto reset_chk_err;
6251 else
6252 return ret;
6253 }
6254
6255 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6256
6257
6258 return 0;
6259
6260reset_chk_err:
6261 dev_err(dev, "Device is busy in resetting state.\n"
6262 "please retry later.\n");
6263
6264 return -EBUSY;
6265}
6266
6267static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6268 bool reset)
6269{
6270 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6271 return;
6272
6273 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6274
6275 __hns_roce_hw_v2_uninit_instance(handle, reset);
6276
6277 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6278}
cb7a94c9
WHX		 6279static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6280{
d061effc 6281 struct hns_roce_dev *hr_dev;
cb7a94c9
WHX		 6282 struct ib_event event;
6283
d061effc
WHX		 6284 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6285 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6286 return 0;
cb7a94c9
WHX		 6287 }
6288
d061effc
WHX		 6289 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6290 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6291
6292 hr_dev = (struct hns_roce_dev *)handle->priv;
6293 if (!hr_dev)
6294 return 0;
6295
cb7a94c9 6296 hr_dev->active = false;
d3743fa9 6297 hr_dev->dis_db = true;
cb7a94c9
WHX		 6298
6299 event.event = IB_EVENT_DEVICE_FATAL;
6300 event.device = &hr_dev->ib_dev;
6301 event.element.port_num = 1;
6302 ib_dispatch_event(&event);
6303
6304 return 0;
6305}
6306
6307static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6308{
d061effc 6309 struct device *dev = &handle->pdev->dev;
cb7a94c9
WHX		 6310 int ret;
6311
d061effc
WHX		 6312 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6313 &handle->rinfo.state)) {
6314 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6315 return 0;
6316 }
6317
6318 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6319
6320 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6321 ret = __hns_roce_hw_v2_init_instance(handle);
cb7a94c9
WHX		 6322 if (ret) {
6323 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6324 * callback function, RoCE Engine reinitialize. If RoCE reinit
6325 * failed, we should inform NIC driver.
6326 */
6327 handle->priv = NULL;
d061effc
WHX		 6328 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6329 } else {
6330 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6331 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
cb7a94c9
WHX		 6332 }
6333
6334 return ret;
6335}
6336
6337static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6338{
d061effc
WHX		 6339 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6340 return 0;
6341
6342 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6343 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
cb7a94c9 6344 msleep(100);
d061effc
WHX		 6345 __hns_roce_hw_v2_uninit_instance(handle, false);
6346
cb7a94c9
WHX		 6347 return 0;
6348}
6349
6350static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6351 enum hnae3_reset_notify_type type)
6352{
6353 int ret = 0;
6354
6355 switch (type) {
6356 case HNAE3_DOWN_CLIENT:
6357 ret = hns_roce_hw_v2_reset_notify_down(handle);
6358 break;
6359 case HNAE3_INIT_CLIENT:
6360 ret = hns_roce_hw_v2_reset_notify_init(handle);
6361 break;
6362 case HNAE3_UNINIT_CLIENT:
6363 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6364 break;
6365 default:
6366 break;
6367 }
6368
6369 return ret;
6370}
6371
dd74282d
WHX		 6372static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6373 .init_instance = hns_roce_hw_v2_init_instance,
6374 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 6375 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 6376};
6377
6378static struct hnae3_client hns_roce_hw_v2_client = {
6379 .name = "hns_roce_hw_v2",
6380 .type = HNAE3_CLIENT_ROCE,
6381 .ops = &hns_roce_hw_v2_ops,
6382};
6383
6384static int __init hns_roce_hw_v2_init(void)
6385{
6386 return hnae3_register_client(&hns_roce_hw_v2_client);
6387}
6388
6389static void __exit hns_roce_hw_v2_exit(void)
6390{
6391 hnae3_unregister_client(&hns_roce_hw_v2_client);
6392}
6393
6394module_init(hns_roce_hw_v2_init);
6395module_exit(hns_roce_hw_v2_exit);
6396
6397MODULE_LICENSE("Dual BSD/GPL");
6398MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6399MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6400MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6401MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)