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RDMA/hns: Init SRQ table for hip08
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
dd74282d
WHX		 40#include <rdma/ib_umem.h>
41
42#include "hnae3.h"
43#include "hns_roce_common.h"
44#include "hns_roce_device.h"
45#include "hns_roce_cmd.h"
46#include "hns_roce_hem.h"
a04ff739 47#include "hns_roce_hw_v2.h"
dd74282d 48
2d407888
WHX		 49static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
50 struct ib_sge *sg)
51{
52 dseg->lkey = cpu_to_le32(sg->lkey);
53 dseg->addr = cpu_to_le64(sg->addr);
54 dseg->len = cpu_to_le32(sg->length);
55}
56
68a997c5
YL		 57static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
58 struct hns_roce_wqe_frmr_seg *fseg,
59 const struct ib_reg_wr *wr)
60{
61 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
62
63 /* use ib_access_flags */
64 roce_set_bit(rc_sq_wqe->byte_4,
65 V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
66 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
67 roce_set_bit(rc_sq_wqe->byte_4,
68 V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
69 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
70 roce_set_bit(rc_sq_wqe->byte_4,
71 V2_RC_FRMR_WQE_BYTE_4_RR_S,
72 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
73 roce_set_bit(rc_sq_wqe->byte_4,
74 V2_RC_FRMR_WQE_BYTE_4_RW_S,
75 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
76 roce_set_bit(rc_sq_wqe->byte_4,
77 V2_RC_FRMR_WQE_BYTE_4_LW_S,
78 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
79
80 /* Data structure reuse may lead to confusion */
81 rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff);
82 rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32);
83
84 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
85 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
86 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
87 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
88
89 fseg->pbl_size = cpu_to_le32(mr->pbl_size);
90 roce_set_field(fseg->mode_buf_pg_sz,
91 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
92 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
93 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
94 roce_set_bit(fseg->mode_buf_pg_sz,
95 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
96}
97
384f8818
LO		 98static void set_atomic_seg(struct hns_roce_wqe_atomic_seg *aseg,
99 const struct ib_atomic_wr *wr)
100{
101 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
102 aseg->fetchadd_swap_data = cpu_to_le64(wr->swap);
103 aseg->cmp_data = cpu_to_le64(wr->compare_add);
104 } else {
105 aseg->fetchadd_swap_data = cpu_to_le64(wr->compare_add);
106 aseg->cmp_data = 0;
107 }
108}
109
f696bf6d 110static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
0b25c9cc
WHX		 111 unsigned int *sge_ind)
112{
113 struct hns_roce_v2_wqe_data_seg *dseg;
114 struct ib_sge *sg;
115 int num_in_wqe = 0;
116 int extend_sge_num;
117 int fi_sge_num;
118 int se_sge_num;
119 int shift;
120 int i;
121
122 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
123 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
124 extend_sge_num = wr->num_sge - num_in_wqe;
125 sg = wr->sg_list + num_in_wqe;
126 shift = qp->hr_buf.page_shift;
127
128 /*
129 * Check whether wr->num_sge sges are in the same page. If not, we
130 * should calculate how many sges in the first page and the second
131 * page.
132 */
133 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
134 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
135 (uintptr_t)dseg) /
136 sizeof(struct hns_roce_v2_wqe_data_seg);
137 if (extend_sge_num > fi_sge_num) {
138 se_sge_num = extend_sge_num - fi_sge_num;
139 for (i = 0; i < fi_sge_num; i++) {
140 set_data_seg_v2(dseg++, sg + i);
141 (*sge_ind)++;
142 }
143 dseg = get_send_extend_sge(qp,
144 (*sge_ind) & (qp->sge.sge_cnt - 1));
145 for (i = 0; i < se_sge_num; i++) {
146 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
147 (*sge_ind)++;
148 }
149 } else {
150 for (i = 0; i < extend_sge_num; i++) {
151 set_data_seg_v2(dseg++, sg + i);
152 (*sge_ind)++;
153 }
154 }
155}
156
f696bf6d 157static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 158 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
159 void *wqe, unsigned int *sge_ind,
d34ac5cd 160 const struct ib_send_wr **bad_wr)
7bdee415 161{
162 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
163 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
164 struct hns_roce_qp *qp = to_hr_qp(ibqp);
165 int i;
166
167 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 168 if (le32_to_cpu(rc_sq_wqe->msg_len) >
169 hr_dev->caps.max_sq_inline) {
7bdee415 170 *bad_wr = wr;
171 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
172 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
173 return -EINVAL;
174 }
175
328d405b 176 if (wr->opcode == IB_WR_RDMA_READ) {
c80e0661 177 *bad_wr = wr;
328d405b 178 dev_err(hr_dev->dev, "Not support inline data!\n");
179 return -EINVAL;
180 }
181
7bdee415 182 for (i = 0; i < wr->num_sge; i++) {
183 memcpy(wqe, ((void *)wr->sg_list[i].addr),
184 wr->sg_list[i].length);
185 wqe += wr->sg_list[i].length;
186 }
187
188 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
189 1);
190 } else {
0b25c9cc 191 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 192 for (i = 0; i < wr->num_sge; i++) {
193 if (likely(wr->sg_list[i].length)) {
194 set_data_seg_v2(dseg, wr->sg_list + i);
195 dseg++;
196 }
197 }
198 } else {
199 roce_set_field(rc_sq_wqe->byte_20,
200 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
201 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
202 (*sge_ind) & (qp->sge.sge_cnt - 1));
203
0b25c9cc 204 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 205 if (likely(wr->sg_list[i].length)) {
206 set_data_seg_v2(dseg, wr->sg_list + i);
207 dseg++;
208 }
209 }
210
0b25c9cc 211 set_extend_sge(qp, wr, sge_ind);
7bdee415 212 }
213
214 roce_set_field(rc_sq_wqe->byte_16,
215 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
216 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
217 }
218
219 return 0;
220}
221
0425e3e6
YL		 222static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
223 const struct ib_qp_attr *attr,
224 int attr_mask, enum ib_qp_state cur_state,
225 enum ib_qp_state new_state);
226
d34ac5cd
BVA		 227static int hns_roce_v2_post_send(struct ib_qp *ibqp,
228 const struct ib_send_wr *wr,
229 const struct ib_send_wr **bad_wr)
2d407888
WHX		 230{
231 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
7bdee415 232 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
233 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
2d407888
WHX		 234 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
235 struct hns_roce_qp *qp = to_hr_qp(ibqp);
68a997c5 236 struct hns_roce_wqe_frmr_seg *fseg;
2d407888
WHX		 237 struct device *dev = hr_dev->dev;
238 struct hns_roce_v2_db sq_db;
0425e3e6 239 struct ib_qp_attr attr;
2d407888 240 unsigned int sge_ind = 0;
e8d18533 241 unsigned int owner_bit;
2d407888
WHX		 242 unsigned long flags;
243 unsigned int ind;
244 void *wqe = NULL;
7bdee415 245 bool loopback;
0425e3e6 246 int attr_mask;
55ba49cb 247 u32 tmp_len;
2d407888 248 int ret = 0;
b9c1ea40 249 u32 hr_op;
7bdee415 250 u8 *smac;
2d407888
WHX		 251 int nreq;
252 int i;
253
7bdee415 254 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
255 ibqp->qp_type != IB_QPT_GSI &&
256 ibqp->qp_type != IB_QPT_UD)) {
2d407888 257 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
137ae320 258 *bad_wr = wr;
2d407888
WHX		 259 return -EOPNOTSUPP;
260 }
261
10bd2ade
YL		 262 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT ||
263 qp->state == IB_QPS_RTR)) {
2d407888
WHX		 264 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
265 *bad_wr = wr;
266 return -EINVAL;
267 }
268
269 spin_lock_irqsave(&qp->sq.lock, flags);
270 ind = qp->sq_next_wqe;
271 sge_ind = qp->next_sge;
272
273 for (nreq = 0; wr; ++nreq, wr = wr->next) {
274 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
275 ret = -ENOMEM;
276 *bad_wr = wr;
277 goto out;
278 }
279
280 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
281 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
282 wr->num_sge, qp->sq.max_gs);
283 ret = -EINVAL;
284 *bad_wr = wr;
285 goto out;
286 }
287
288 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
289 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
290 wr->wr_id;
291
634f6390 292 owner_bit =
293 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
55ba49cb 294 tmp_len = 0;
2d407888 295
7bdee415 296 /* Corresponding to the QP type, wqe process separately */
297 if (ibqp->qp_type == IB_QPT_GSI) {
298 ud_sq_wqe = wqe;
299 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
300
301 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
302 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
303 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
304 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
305 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
306 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
307 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
308 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
309 roce_set_field(ud_sq_wqe->byte_48,
310 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
311 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
312 ah->av.mac[4]);
313 roce_set_field(ud_sq_wqe->byte_48,
314 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
315 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
316 ah->av.mac[5]);
317
318 /* MAC loopback */
319 smac = (u8 *)hr_dev->dev_addr[qp->port];
320 loopback = ether_addr_equal_unaligned(ah->av.mac,
321 smac) ? 1 : 0;
322
323 roce_set_bit(ud_sq_wqe->byte_40,
324 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
325
326 roce_set_field(ud_sq_wqe->byte_4,
327 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
328 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
329 HNS_ROCE_V2_WQE_OP_SEND);
2d407888 330
7bdee415 331 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 332 tmp_len += wr->sg_list[i].length;
492b2bd0 333
8b9b8d14 334 ud_sq_wqe->msg_len =
335 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len);
336
337 switch (wr->opcode) {
338 case IB_WR_SEND_WITH_IMM:
339 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 340 ud_sq_wqe->immtdata =
341 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 342 break;
343 default:
344 ud_sq_wqe->immtdata = 0;
345 break;
346 }
651487c2 347
7bdee415 348 /* Set sig attr */
349 roce_set_bit(ud_sq_wqe->byte_4,
350 V2_UD_SEND_WQE_BYTE_4_CQE_S,
351 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
a49d761f 352
7bdee415 353 /* Set se attr */
354 roce_set_bit(ud_sq_wqe->byte_4,
355 V2_UD_SEND_WQE_BYTE_4_SE_S,
356 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
e8d18533 357
7bdee415 358 roce_set_bit(ud_sq_wqe->byte_4,
359 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
360
361 roce_set_field(ud_sq_wqe->byte_16,
362 V2_UD_SEND_WQE_BYTE_16_PD_M,
363 V2_UD_SEND_WQE_BYTE_16_PD_S,
364 to_hr_pd(ibqp->pd)->pdn);
365
366 roce_set_field(ud_sq_wqe->byte_16,
367 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
368 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
369 wr->num_sge);
370
371 roce_set_field(ud_sq_wqe->byte_20,
372 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
373 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
374 sge_ind & (qp->sge.sge_cnt - 1));
375
376 roce_set_field(ud_sq_wqe->byte_24,
377 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
378 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
379 ud_sq_wqe->qkey =
8b9b8d14 380 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
381 qp->qkey : ud_wr(wr)->remote_qkey);
7bdee415 382 roce_set_field(ud_sq_wqe->byte_32,
383 V2_UD_SEND_WQE_BYTE_32_DQPN_M,
384 V2_UD_SEND_WQE_BYTE_32_DQPN_S,
385 ud_wr(wr)->remote_qpn);
386
387 roce_set_field(ud_sq_wqe->byte_36,
388 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
389 V2_UD_SEND_WQE_BYTE_36_VLAN_S,
8b9b8d14 390 le16_to_cpu(ah->av.vlan));
7bdee415 391 roce_set_field(ud_sq_wqe->byte_36,
392 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
393 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
394 ah->av.hop_limit);
395 roce_set_field(ud_sq_wqe->byte_36,
396 V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
397 V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
cdfa4ad5
LO		 398 ah->av.sl_tclass_flowlabel >>
399 HNS_ROCE_TCLASS_SHIFT);
7bdee415 400 roce_set_field(ud_sq_wqe->byte_40,
401 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
cdfa4ad5
LO		 402 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
403 ah->av.sl_tclass_flowlabel &
404 HNS_ROCE_FLOW_LABEL_MASK);
7bdee415 405 roce_set_field(ud_sq_wqe->byte_40,
406 V2_UD_SEND_WQE_BYTE_40_SL_M,
407 V2_UD_SEND_WQE_BYTE_40_SL_S,
8b9b8d14 408 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
409 HNS_ROCE_SL_SHIFT);
7bdee415 410 roce_set_field(ud_sq_wqe->byte_40,
411 V2_UD_SEND_WQE_BYTE_40_PORTN_M,
412 V2_UD_SEND_WQE_BYTE_40_PORTN_S,
413 qp->port);
414
8320deb8
LO		 415 roce_set_bit(ud_sq_wqe->byte_40,
416 V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
417 ah->av.vlan_en ? 1 : 0);
7bdee415 418 roce_set_field(ud_sq_wqe->byte_48,
419 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
420 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
421 hns_get_gid_index(hr_dev, qp->phy_port,
422 ah->av.gid_index));
423
424 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
425 GID_LEN_V2);
426
0b25c9cc 427 set_extend_sge(qp, wr, &sge_ind);
7bdee415 428 ind++;
429 } else if (ibqp->qp_type == IB_QPT_RC) {
430 rc_sq_wqe = wqe;
431 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
432 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 433 tmp_len += wr->sg_list[i].length;
434
435 rc_sq_wqe->msg_len =
436 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len);
7bdee415 437
8b9b8d14 438 switch (wr->opcode) {
439 case IB_WR_SEND_WITH_IMM:
440 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 441 rc_sq_wqe->immtdata =
442 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 443 break;
444 case IB_WR_SEND_WITH_INV:
445 rc_sq_wqe->inv_key =
446 cpu_to_le32(wr->ex.invalidate_rkey);
447 break;
448 default:
449 rc_sq_wqe->immtdata = 0;
450 break;
451 }
7bdee415 452
453 roce_set_bit(rc_sq_wqe->byte_4,
454 V2_RC_SEND_WQE_BYTE_4_FENCE_S,
455 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
456
457 roce_set_bit(rc_sq_wqe->byte_4,
458 V2_RC_SEND_WQE_BYTE_4_SE_S,
459 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
460
461 roce_set_bit(rc_sq_wqe->byte_4,
462 V2_RC_SEND_WQE_BYTE_4_CQE_S,
463 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
464
465 roce_set_bit(rc_sq_wqe->byte_4,
466 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
467
384f8818 468 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
7bdee415 469 switch (wr->opcode) {
470 case IB_WR_RDMA_READ:
b9c1ea40 471 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
7bdee415 472 rc_sq_wqe->rkey =
473 cpu_to_le32(rdma_wr(wr)->rkey);
474 rc_sq_wqe->va =
475 cpu_to_le64(rdma_wr(wr)->remote_addr);
476 break;
477 case IB_WR_RDMA_WRITE:
b9c1ea40 478 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
7bdee415 479 rc_sq_wqe->rkey =
480 cpu_to_le32(rdma_wr(wr)->rkey);
481 rc_sq_wqe->va =
482 cpu_to_le64(rdma_wr(wr)->remote_addr);
483 break;
484 case IB_WR_RDMA_WRITE_WITH_IMM:
b9c1ea40 485 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
7bdee415 486 rc_sq_wqe->rkey =
487 cpu_to_le32(rdma_wr(wr)->rkey);
488 rc_sq_wqe->va =
489 cpu_to_le64(rdma_wr(wr)->remote_addr);
490 break;
491 case IB_WR_SEND:
b9c1ea40 492 hr_op = HNS_ROCE_V2_WQE_OP_SEND;
7bdee415 493 break;
494 case IB_WR_SEND_WITH_INV:
b9c1ea40 495 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
7bdee415 496 break;
497 case IB_WR_SEND_WITH_IMM:
b9c1ea40 498 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
7bdee415 499 break;
500 case IB_WR_LOCAL_INV:
b9c1ea40 501 hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
e93df010
LO		 502 roce_set_bit(rc_sq_wqe->byte_4,
503 V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
504 rc_sq_wqe->inv_key =
505 cpu_to_le32(wr->ex.invalidate_rkey);
7bdee415 506 break;
68a997c5
YL		 507 case IB_WR_REG_MR:
508 hr_op = HNS_ROCE_V2_WQE_OP_FAST_REG_PMR;
509 fseg = wqe;
510 set_frmr_seg(rc_sq_wqe, fseg, reg_wr(wr));
511 break;
7bdee415 512 case IB_WR_ATOMIC_CMP_AND_SWP:
b9c1ea40 513 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
384f8818
LO		 514 rc_sq_wqe->rkey =
515 cpu_to_le32(atomic_wr(wr)->rkey);
516 rc_sq_wqe->va =
d9581bf3 517 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 518 break;
519 case IB_WR_ATOMIC_FETCH_AND_ADD:
b9c1ea40 520 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
384f8818
LO		 521 rc_sq_wqe->rkey =
522 cpu_to_le32(atomic_wr(wr)->rkey);
523 rc_sq_wqe->va =
d9581bf3 524 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 525 break;
526 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
b9c1ea40
LO		 527 hr_op =
528 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
7bdee415 529 break;
530 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
b9c1ea40
LO		 531 hr_op =
532 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
7bdee415 533 break;
534 default:
b9c1ea40 535 hr_op = HNS_ROCE_V2_WQE_OP_MASK;
7bdee415 536 break;
2d407888
WHX		 537 }
538
b9c1ea40
LO		 539 roce_set_field(rc_sq_wqe->byte_4,
540 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
541 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
2d407888 542
d9581bf3
LO		 543 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
544 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
545 struct hns_roce_v2_wqe_data_seg *dseg;
546
547 dseg = wqe;
548 set_data_seg_v2(dseg, wr->sg_list);
549 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
550 set_atomic_seg(wqe, atomic_wr(wr));
551 roce_set_field(rc_sq_wqe->byte_16,
552 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
553 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
554 wr->num_sge);
68a997c5 555 } else if (wr->opcode != IB_WR_REG_MR) {
d9581bf3
LO		 556 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe,
557 wqe, &sge_ind, bad_wr);
558 if (ret)
559 goto out;
560 }
561
7bdee415 562 ind++;
2d407888 563 } else {
7bdee415 564 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
565 spin_unlock_irqrestore(&qp->sq.lock, flags);
137ae320 566 *bad_wr = wr;
7bdee415 567 return -EOPNOTSUPP;
2d407888 568 }
2d407888
WHX		 569 }
570
571out:
572 if (likely(nreq)) {
573 qp->sq.head += nreq;
574 /* Memory barrier */
575 wmb();
576
577 sq_db.byte_4 = 0;
578 sq_db.parameter = 0;
579
580 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
581 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
582 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
583 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
cc3391cb 584 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
585 V2_DB_PARAMETER_IDX_S,
2d407888
WHX		 586 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
587 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
588 V2_DB_PARAMETER_SL_S, qp->sl);
589
8b9b8d14 590 hns_roce_write64_k((__le32 *)&sq_db, qp->sq.db_reg_l);
2d407888
WHX		 591
592 qp->sq_next_wqe = ind;
593 qp->next_sge = sge_ind;
0425e3e6
YL		 594
595 if (qp->state == IB_QPS_ERR) {
596 attr_mask = IB_QP_STATE;
597 attr.qp_state = IB_QPS_ERR;
598
599 ret = hns_roce_v2_modify_qp(&qp->ibqp, &attr, attr_mask,
600 qp->state, IB_QPS_ERR);
601 if (ret) {
602 spin_unlock_irqrestore(&qp->sq.lock, flags);
603 *bad_wr = wr;
604 return ret;
605 }
606 }
2d407888
WHX		 607 }
608
609 spin_unlock_irqrestore(&qp->sq.lock, flags);
610
611 return ret;
612}
613
d34ac5cd
BVA		 614static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
615 const struct ib_recv_wr *wr,
616 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 617{
618 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
619 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
620 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 621 struct hns_roce_rinl_sge *sge_list;
2d407888 622 struct device *dev = hr_dev->dev;
0425e3e6 623 struct ib_qp_attr attr;
2d407888
WHX		 624 unsigned long flags;
625 void *wqe = NULL;
0425e3e6 626 int attr_mask;
2d407888
WHX		 627 int ret = 0;
628 int nreq;
629 int ind;
630 int i;
631
632 spin_lock_irqsave(&hr_qp->rq.lock, flags);
633 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
634
ced07769 635 if (hr_qp->state == IB_QPS_RESET) {
2d407888
WHX		 636 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
637 *bad_wr = wr;
638 return -EINVAL;
639 }
640
641 for (nreq = 0; wr; ++nreq, wr = wr->next) {
642 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
643 hr_qp->ibqp.recv_cq)) {
644 ret = -ENOMEM;
645 *bad_wr = wr;
646 goto out;
647 }
648
649 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
650 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
651 wr->num_sge, hr_qp->rq.max_gs);
652 ret = -EINVAL;
653 *bad_wr = wr;
654 goto out;
655 }
656
657 wqe = get_recv_wqe(hr_qp, ind);
658 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
659 for (i = 0; i < wr->num_sge; i++) {
660 if (!wr->sg_list[i].length)
661 continue;
662 set_data_seg_v2(dseg, wr->sg_list + i);
663 dseg++;
664 }
665
666 if (i < hr_qp->rq.max_gs) {
778cc5a8 667 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
668 dseg->addr = 0;
2d407888
WHX		 669 }
670
0009c2db 671 /* rq support inline data */
ecaaf1e2 672 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
673 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
674 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
675 (u32)wr->num_sge;
676 for (i = 0; i < wr->num_sge; i++) {
677 sge_list[i].addr =
678 (void *)(u64)wr->sg_list[i].addr;
679 sge_list[i].len = wr->sg_list[i].length;
680 }
0009c2db 681 }
682
2d407888
WHX		 683 hr_qp->rq.wrid[ind] = wr->wr_id;
684
685 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
686 }
687
688out:
689 if (likely(nreq)) {
690 hr_qp->rq.head += nreq;
691 /* Memory barrier */
692 wmb();
693
472bc0fb 694 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
0425e3e6
YL		 695
696 if (hr_qp->state == IB_QPS_ERR) {
697 attr_mask = IB_QP_STATE;
698 attr.qp_state = IB_QPS_ERR;
699
700 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr,
701 attr_mask, hr_qp->state,
702 IB_QPS_ERR);
703 if (ret) {
704 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
705 *bad_wr = wr;
706 return ret;
707 }
708 }
2d407888
WHX		 709 }
710 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
711
712 return ret;
713}
714
a04ff739
WHX		 715static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
716{
717 int ntu = ring->next_to_use;
718 int ntc = ring->next_to_clean;
719 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
720
721 return ring->desc_num - used - 1;
722}
723
724static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
725 struct hns_roce_v2_cmq_ring *ring)
726{
727 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
728
729 ring->desc = kzalloc(size, GFP_KERNEL);
730 if (!ring->desc)
731 return -ENOMEM;
732
733 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
734 DMA_BIDIRECTIONAL);
735 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
736 ring->desc_dma_addr = 0;
737 kfree(ring->desc);
738 ring->desc = NULL;
739 return -ENOMEM;
740 }
741
742 return 0;
743}
744
745static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
746 struct hns_roce_v2_cmq_ring *ring)
747{
748 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
749 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
750 DMA_BIDIRECTIONAL);
90e7a4d5 751
752 ring->desc_dma_addr = 0;
a04ff739
WHX		 753 kfree(ring->desc);
754}
755
756static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
757{
758 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
759 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
760 &priv->cmq.csq : &priv->cmq.crq;
761
762 ring->flag = ring_type;
763 ring->next_to_clean = 0;
764 ring->next_to_use = 0;
765
766 return hns_roce_alloc_cmq_desc(hr_dev, ring);
767}
768
769static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
770{
771 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
772 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
773 &priv->cmq.csq : &priv->cmq.crq;
774 dma_addr_t dma = ring->desc_dma_addr;
775
776 if (ring_type == TYPE_CSQ) {
777 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
778 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
779 upper_32_bits(dma));
780 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
781 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
782 HNS_ROCE_CMQ_ENABLE);
783 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
784 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
785 } else {
786 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
787 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
788 upper_32_bits(dma));
789 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
790 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
791 HNS_ROCE_CMQ_ENABLE);
792 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
793 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
794 }
795}
796
797static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
798{
799 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
800 int ret;
801
802 /* Setup the queue entries for command queue */
426c4146
LO		 803 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
804 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 805
806 /* Setup the lock for command queue */
807 spin_lock_init(&priv->cmq.csq.lock);
808 spin_lock_init(&priv->cmq.crq.lock);
809
810 /* Setup Tx write back timeout */
811 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
812
813 /* Init CSQ */
814 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
815 if (ret) {
816 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
817 return ret;
818 }
819
820 /* Init CRQ */
821 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
822 if (ret) {
823 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
824 goto err_crq;
825 }
826
827 /* Init CSQ REG */
828 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
829
830 /* Init CRQ REG */
831 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
832
833 return 0;
834
835err_crq:
836 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
837
838 return ret;
839}
840
841static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
842{
843 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
844
845 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
846 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
847}
848
281d0ccf
CIK		 849static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
850 enum hns_roce_opcode_type opcode,
851 bool is_read)
a04ff739
WHX		 852{
853 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
854 desc->opcode = cpu_to_le16(opcode);
855 desc->flag =
856 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
857 if (is_read)
858 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
859 else
860 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
861}
862
863static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
864{
865 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
866 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
867
868 return head == priv->cmq.csq.next_to_use;
869}
870
871static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
872{
873 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
874 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
875 struct hns_roce_cmq_desc *desc;
876 u16 ntc = csq->next_to_clean;
877 u32 head;
878 int clean = 0;
879
880 desc = &csq->desc[ntc];
881 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
882 while (head != ntc) {
883 memset(desc, 0, sizeof(*desc));
884 ntc++;
885 if (ntc == csq->desc_num)
886 ntc = 0;
887 desc = &csq->desc[ntc];
888 clean++;
889 }
890 csq->next_to_clean = ntc;
891
892 return clean;
893}
894
281d0ccf
CIK		 895static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
896 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 897{
898 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
899 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
900 struct hns_roce_cmq_desc *desc_to_use;
901 bool complete = false;
902 u32 timeout = 0;
903 int handle = 0;
904 u16 desc_ret;
905 int ret = 0;
906 int ntc;
907
cb7a94c9
WHX		 908 if (hr_dev->is_reset)
909 return 0;
910
a04ff739
WHX		 911 spin_lock_bh(&csq->lock);
912
913 if (num > hns_roce_cmq_space(csq)) {
914 spin_unlock_bh(&csq->lock);
915 return -EBUSY;
916 }
917
918 /*
919 * Record the location of desc in the cmq for this time
920 * which will be use for hardware to write back
921 */
922 ntc = csq->next_to_use;
923
924 while (handle < num) {
925 desc_to_use = &csq->desc[csq->next_to_use];
926 *desc_to_use = desc[handle];
927 dev_dbg(hr_dev->dev, "set cmq desc:\n");
928 csq->next_to_use++;
929 if (csq->next_to_use == csq->desc_num)
930 csq->next_to_use = 0;
931 handle++;
932 }
933
934 /* Write to hardware */
935 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
936
937 /*
938 * If the command is sync, wait for the firmware to write back,
939 * if multi descriptors to be sent, use the first one to check
940 */
941 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
942 do {
943 if (hns_roce_cmq_csq_done(hr_dev))
944 break;
988e175b 945 udelay(1);
a04ff739
WHX		 946 timeout++;
947 } while (timeout < priv->cmq.tx_timeout);
948 }
949
950 if (hns_roce_cmq_csq_done(hr_dev)) {
951 complete = true;
952 handle = 0;
953 while (handle < num) {
954 /* get the result of hardware write back */
955 desc_to_use = &csq->desc[ntc];
956 desc[handle] = *desc_to_use;
957 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
958 desc_ret = desc[handle].retval;
959 if (desc_ret == CMD_EXEC_SUCCESS)
960 ret = 0;
961 else
962 ret = -EIO;
963 priv->cmq.last_status = desc_ret;
964 ntc++;
965 handle++;
966 if (ntc == csq->desc_num)
967 ntc = 0;
968 }
969 }
970
971 if (!complete)
972 ret = -EAGAIN;
973
974 /* clean the command send queue */
975 handle = hns_roce_cmq_csq_clean(hr_dev);
976 if (handle != num)
977 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
978 handle, num);
979
980 spin_unlock_bh(&csq->lock);
981
982 return ret;
983}
984
281d0ccf 985static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 986{
987 struct hns_roce_query_version *resp;
988 struct hns_roce_cmq_desc desc;
989 int ret;
990
991 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
992 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
993 if (ret)
994 return ret;
995
996 resp = (struct hns_roce_query_version *)desc.data;
997 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 998 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
999
1000 return 0;
1001}
1002
1003static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1004{
1005 struct hns_roce_query_fw_info *resp;
1006 struct hns_roce_cmq_desc desc;
1007 int ret;
1008
1009 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1010 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1011 if (ret)
1012 return ret;
1013
1014 resp = (struct hns_roce_query_fw_info *)desc.data;
1015 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1016
1017 return 0;
1018}
1019
1020static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1021{
1022 struct hns_roce_cfg_global_param *req;
1023 struct hns_roce_cmq_desc desc;
1024
1025 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1026 false);
1027
1028 req = (struct hns_roce_cfg_global_param *)desc.data;
1029 memset(req, 0, sizeof(*req));
1030 roce_set_field(req->time_cfg_udp_port,
1031 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1032 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1033 roce_set_field(req->time_cfg_udp_port,
1034 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1035 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1036
1037 return hns_roce_cmq_send(hr_dev, &desc, 1);
1038}
1039
1040static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1041{
1042 struct hns_roce_cmq_desc desc[2];
6b63597d 1043 struct hns_roce_pf_res_a *req_a;
1044 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1045 int ret;
1046 int i;
1047
1048 for (i = 0; i < 2; i++) {
1049 hns_roce_cmq_setup_basic_desc(&desc[i],
1050 HNS_ROCE_OPC_QUERY_PF_RES, true);
1051
1052 if (i == 0)
1053 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1054 else
1055 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1056 }
1057
1058 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1059 if (ret)
1060 return ret;
1061
6b63597d 1062 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1063 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1064
6b63597d 1065 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1066 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1067 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1068 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1069 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1070 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1071 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1072 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1073 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1074 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1075 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1076 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1077
6b63597d 1078 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1079 PF_RES_DATA_3_PF_SL_NUM_M,
1080 PF_RES_DATA_3_PF_SL_NUM_S);
1081
cfc85f3e
WHX		 1082 return 0;
1083}
1084
1085static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1086{
1087 struct hns_roce_cmq_desc desc[2];
1088 struct hns_roce_vf_res_a *req_a;
1089 struct hns_roce_vf_res_b *req_b;
1090 int i;
1091
1092 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1093 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1094 memset(req_a, 0, sizeof(*req_a));
1095 memset(req_b, 0, sizeof(*req_b));
1096 for (i = 0; i < 2; i++) {
1097 hns_roce_cmq_setup_basic_desc(&desc[i],
1098 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1099
1100 if (i == 0)
1101 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1102 else
1103 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1104
1105 if (i == 0) {
1106 roce_set_field(req_a->vf_qpc_bt_idx_num,
1107 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1108 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1109 roce_set_field(req_a->vf_qpc_bt_idx_num,
1110 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1111 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
1112 HNS_ROCE_VF_QPC_BT_NUM);
1113
1114 roce_set_field(req_a->vf_srqc_bt_idx_num,
1115 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1116 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1117 roce_set_field(req_a->vf_srqc_bt_idx_num,
1118 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1119 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1120 HNS_ROCE_VF_SRQC_BT_NUM);
1121
1122 roce_set_field(req_a->vf_cqc_bt_idx_num,
1123 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1124 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1125 roce_set_field(req_a->vf_cqc_bt_idx_num,
1126 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1127 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
1128 HNS_ROCE_VF_CQC_BT_NUM);
1129
1130 roce_set_field(req_a->vf_mpt_bt_idx_num,
1131 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1132 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1133 roce_set_field(req_a->vf_mpt_bt_idx_num,
1134 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1135 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
1136 HNS_ROCE_VF_MPT_BT_NUM);
1137
1138 roce_set_field(req_a->vf_eqc_bt_idx_num,
1139 VF_RES_A_DATA_5_VF_EQC_IDX_M,
1140 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1141 roce_set_field(req_a->vf_eqc_bt_idx_num,
1142 VF_RES_A_DATA_5_VF_EQC_NUM_M,
1143 VF_RES_A_DATA_5_VF_EQC_NUM_S,
1144 HNS_ROCE_VF_EQC_NUM);
1145 } else {
1146 roce_set_field(req_b->vf_smac_idx_num,
1147 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1148 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1149 roce_set_field(req_b->vf_smac_idx_num,
1150 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1151 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
1152 HNS_ROCE_VF_SMAC_NUM);
1153
1154 roce_set_field(req_b->vf_sgid_idx_num,
1155 VF_RES_B_DATA_2_VF_SGID_IDX_M,
1156 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1157 roce_set_field(req_b->vf_sgid_idx_num,
1158 VF_RES_B_DATA_2_VF_SGID_NUM_M,
1159 VF_RES_B_DATA_2_VF_SGID_NUM_S,
1160 HNS_ROCE_VF_SGID_NUM);
1161
1162 roce_set_field(req_b->vf_qid_idx_sl_num,
1163 VF_RES_B_DATA_3_VF_QID_IDX_M,
1164 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1165 roce_set_field(req_b->vf_qid_idx_sl_num,
1166 VF_RES_B_DATA_3_VF_SL_NUM_M,
1167 VF_RES_B_DATA_3_VF_SL_NUM_S,
1168 HNS_ROCE_VF_SL_NUM);
1169 }
1170 }
1171
1172 return hns_roce_cmq_send(hr_dev, desc, 2);
1173}
1174
a81fba28
WHX		 1175static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1176{
1177 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1178 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1179 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1180 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
1181 struct hns_roce_cfg_bt_attr *req;
1182 struct hns_roce_cmq_desc desc;
1183
1184 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1185 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1186 memset(req, 0, sizeof(*req));
1187
1188 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1189 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1190 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1191 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1192 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1193 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1194 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1195 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1196 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1197
1198 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1199 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1200 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1201 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1202 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1203 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1204 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1205 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1206 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1207
1208 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1209 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1210 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1211 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1212 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1213 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1214 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1215 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1216 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1217
1218 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1219 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1220 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1221 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1222 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1223 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1224 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1225 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1226 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1227
1228 return hns_roce_cmq_send(hr_dev, &desc, 1);
1229}
1230
cfc85f3e
WHX		 1231static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1232{
1233 struct hns_roce_caps *caps = &hr_dev->caps;
1234 int ret;
1235
1236 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 1237 if (ret) {
1238 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
1239 ret);
1240 return ret;
1241 }
1242
1243 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 1244 if (ret) {
1245 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1246 ret);
1247 return ret;
1248 }
1249
1250 ret = hns_roce_config_global_param(hr_dev);
1251 if (ret) {
1252 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1253 ret);
2349fdd4 1254 return ret;
cfc85f3e
WHX		 1255 }
1256
1257 /* Get pf resource owned by every pf */
1258 ret = hns_roce_query_pf_resource(hr_dev);
1259 if (ret) {
1260 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1261 ret);
1262 return ret;
1263 }
1264
1265 ret = hns_roce_alloc_vf_resource(hr_dev);
1266 if (ret) {
1267 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
1268 ret);
1269 return ret;
1270 }
1271
3a63c964
LO		 1272
1273 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
1274 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e
WHX		 1275
1276 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1277 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1278 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
5c1f167a 1279 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
cfc85f3e 1280 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
5c1f167a 1281 caps->max_srqwqes = HNS_ROCE_V2_MAX_SRQWQE_NUM;
cfc85f3e 1282 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
05ad5482 1283 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
cfc85f3e
WHX		 1284 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1285 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
5c1f167a 1286 caps->max_srq_sg = HNS_ROCE_V2_MAX_SRQ_SGE_NUM;
cfc85f3e
WHX		 1287 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1288 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
a5073d60
YL		 1289 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1290 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1291 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
cfc85f3e
WHX		 1292 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1293 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1294 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
5c1f167a
LO		 1295 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1296 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
cfc85f3e
WHX		 1297 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1298 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1299 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1300 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1301 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1302 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1303 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1304 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 1305 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e 1306 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
5c1f167a 1307 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
cfc85f3e
WHX		 1308 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1309 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
5c1f167a 1310 caps->idx_entry_sz = 4;
cfc85f3e
WHX		 1311 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1312 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1313 caps->reserved_lkey = 0;
1314 caps->reserved_pds = 0;
1315 caps->reserved_mrws = 1;
1316 caps->reserved_uars = 0;
1317 caps->reserved_cqs = 0;
5c1f167a 1318 caps->reserved_srqs = 0;
06ef0ee4 1319 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
cfc85f3e 1320
a25d13cb
SX		 1321 caps->qpc_ba_pg_sz = 0;
1322 caps->qpc_buf_pg_sz = 0;
1323 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1324 caps->srqc_ba_pg_sz = 0;
1325 caps->srqc_buf_pg_sz = 0;
1326 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
1327 caps->cqc_ba_pg_sz = 0;
1328 caps->cqc_buf_pg_sz = 0;
1329 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1330 caps->mpt_ba_pg_sz = 0;
1331 caps->mpt_buf_pg_sz = 0;
1332 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
ff795f71
WHX		 1333 caps->pbl_ba_pg_sz = 0;
1334 caps->pbl_buf_pg_sz = 0;
1335 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 1336 caps->mtt_ba_pg_sz = 0;
1337 caps->mtt_buf_pg_sz = 0;
1338 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1339 caps->cqe_ba_pg_sz = 0;
1340 caps->cqe_buf_pg_sz = 0;
1341 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
a5073d60
YL		 1342 caps->eqe_ba_pg_sz = 0;
1343 caps->eqe_buf_pg_sz = 0;
1344 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1345 caps->tsq_buf_pg_sz = 0;
29a1fe5d 1346 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 1347
023c1477 1348 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
0009c2db 1349 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
e088a685 1350 HNS_ROCE_CAP_FLAG_RQ_INLINE |
0425e3e6
YL		 1351 HNS_ROCE_CAP_FLAG_RECORD_DB |
1352 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
c7c28191
YL		 1353
1354 if (hr_dev->pci_dev->revision == 0x21)
68a997c5
YL		 1355 caps->flags |= HNS_ROCE_CAP_FLAG_MW |
1356 HNS_ROCE_CAP_FLAG_FRMR;
c7c28191 1357
cfc85f3e 1358 caps->pkey_table_len[0] = 1;
b5ff0f61 1359 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
a5073d60
YL		 1360 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1361 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
cfc85f3e
WHX		 1362 caps->local_ca_ack_delay = 0;
1363 caps->max_mtu = IB_MTU_4096;
1364
d16da119
LO		 1365 caps->max_srqs = HNS_ROCE_V2_MAX_SRQ;
1366 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1367 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1368
384f8818 1369 if (hr_dev->pci_dev->revision == 0x21)
d16da119
LO		 1370 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC |
1371 HNS_ROCE_CAP_FLAG_SRQ;
384f8818 1372
a81fba28
WHX		 1373 ret = hns_roce_v2_set_bt(hr_dev);
1374 if (ret)
1375 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
1376 ret);
1377
1378 return ret;
cfc85f3e
WHX		 1379}
1380
6b63597d 1381static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
1382 enum hns_roce_link_table_type type)
1383{
1384 struct hns_roce_cmq_desc desc[2];
1385 struct hns_roce_cfg_llm_a *req_a =
1386 (struct hns_roce_cfg_llm_a *)desc[0].data;
1387 struct hns_roce_cfg_llm_b *req_b =
1388 (struct hns_roce_cfg_llm_b *)desc[1].data;
1389 struct hns_roce_v2_priv *priv = hr_dev->priv;
1390 struct hns_roce_link_table *link_tbl;
1391 struct hns_roce_link_table_entry *entry;
1392 enum hns_roce_opcode_type opcode;
1393 u32 page_num;
1394 int i;
1395
1396 switch (type) {
1397 case TSQ_LINK_TABLE:
1398 link_tbl = &priv->tsq;
1399 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
1400 break;
ded58ff9 1401 case TPQ_LINK_TABLE:
1402 link_tbl = &priv->tpq;
1403 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
1404 break;
6b63597d 1405 default:
1406 return -EINVAL;
1407 }
1408
1409 page_num = link_tbl->npages;
1410 entry = link_tbl->table.buf;
1411 memset(req_a, 0, sizeof(*req_a));
1412 memset(req_b, 0, sizeof(*req_b));
1413
1414 for (i = 0; i < 2; i++) {
1415 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
1416
1417 if (i == 0)
1418 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1419 else
1420 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1421
1422 if (i == 0) {
1423 req_a->base_addr_l = link_tbl->table.map & 0xffffffff;
1424 req_a->base_addr_h = (link_tbl->table.map >> 32) &
1425 0xffffffff;
1426 roce_set_field(req_a->depth_pgsz_init_en,
1427 CFG_LLM_QUE_DEPTH_M,
1428 CFG_LLM_QUE_DEPTH_S,
1429 link_tbl->npages);
1430 roce_set_field(req_a->depth_pgsz_init_en,
1431 CFG_LLM_QUE_PGSZ_M,
1432 CFG_LLM_QUE_PGSZ_S,
1433 link_tbl->pg_sz);
1434 req_a->head_ba_l = entry[0].blk_ba0;
1435 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr;
1436 roce_set_field(req_a->head_ptr,
1437 CFG_LLM_HEAD_PTR_M,
1438 CFG_LLM_HEAD_PTR_S, 0);
1439 } else {
1440 req_b->tail_ba_l = entry[page_num - 1].blk_ba0;
1441 roce_set_field(req_b->tail_ba_h,
1442 CFG_LLM_TAIL_BA_H_M,
1443 CFG_LLM_TAIL_BA_H_S,
1444 entry[page_num - 1].blk_ba1_nxt_ptr &
1445 HNS_ROCE_LINK_TABLE_BA1_M);
1446 roce_set_field(req_b->tail_ptr,
1447 CFG_LLM_TAIL_PTR_M,
1448 CFG_LLM_TAIL_PTR_S,
1449 (entry[page_num - 2].blk_ba1_nxt_ptr &
1450 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
1451 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
1452 }
1453 }
1454 roce_set_field(req_a->depth_pgsz_init_en,
1455 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1);
1456
1457 return hns_roce_cmq_send(hr_dev, desc, 2);
1458}
1459
1460static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
1461 enum hns_roce_link_table_type type)
1462{
1463 struct hns_roce_v2_priv *priv = hr_dev->priv;
1464 struct hns_roce_link_table *link_tbl;
1465 struct hns_roce_link_table_entry *entry;
1466 struct device *dev = hr_dev->dev;
1467 u32 buf_chk_sz;
1468 dma_addr_t t;
ded58ff9 1469 int func_num = 1;
6b63597d 1470 int pg_num_a;
1471 int pg_num_b;
1472 int pg_num;
1473 int size;
1474 int i;
1475
1476 switch (type) {
1477 case TSQ_LINK_TABLE:
1478 link_tbl = &priv->tsq;
1479 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
1480 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
1481 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
1482 break;
ded58ff9 1483 case TPQ_LINK_TABLE:
1484 link_tbl = &priv->tpq;
1485 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
1486 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
1487 pg_num_b = 2 * 4 * func_num + 2;
1488 break;
6b63597d 1489 default:
1490 return -EINVAL;
1491 }
1492
1493 pg_num = max(pg_num_a, pg_num_b);
1494 size = pg_num * sizeof(struct hns_roce_link_table_entry);
1495
1496 link_tbl->table.buf = dma_alloc_coherent(dev, size,
1497 &link_tbl->table.map,
1498 GFP_KERNEL);
1499 if (!link_tbl->table.buf)
1500 goto out;
1501
1502 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
1503 GFP_KERNEL);
1504 if (!link_tbl->pg_list)
1505 goto err_kcalloc_failed;
1506
1507 entry = link_tbl->table.buf;
1508 for (i = 0; i < pg_num; ++i) {
1509 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
1510 &t, GFP_KERNEL);
1511 if (!link_tbl->pg_list[i].buf)
1512 goto err_alloc_buf_failed;
1513
1514 link_tbl->pg_list[i].map = t;
1515 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz);
1516
1517 entry[i].blk_ba0 = (t >> 12) & 0xffffffff;
1518 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1519 HNS_ROCE_LINK_TABLE_BA1_M,
1520 HNS_ROCE_LINK_TABLE_BA1_S,
1521 t >> 44);
1522
1523 if (i < (pg_num - 1))
1524 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1525 HNS_ROCE_LINK_TABLE_NXT_PTR_M,
1526 HNS_ROCE_LINK_TABLE_NXT_PTR_S,
1527 i + 1);
1528 }
1529 link_tbl->npages = pg_num;
1530 link_tbl->pg_sz = buf_chk_sz;
1531
1532 return hns_roce_config_link_table(hr_dev, type);
1533
1534err_alloc_buf_failed:
1535 for (i -= 1; i >= 0; i--)
1536 dma_free_coherent(dev, buf_chk_sz,
1537 link_tbl->pg_list[i].buf,
1538 link_tbl->pg_list[i].map);
1539 kfree(link_tbl->pg_list);
1540
1541err_kcalloc_failed:
1542 dma_free_coherent(dev, size, link_tbl->table.buf,
1543 link_tbl->table.map);
1544
1545out:
1546 return -ENOMEM;
1547}
1548
1549static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
1550 struct hns_roce_link_table *link_tbl)
1551{
1552 struct device *dev = hr_dev->dev;
1553 int size;
1554 int i;
1555
1556 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
1557
1558 for (i = 0; i < link_tbl->npages; ++i)
1559 if (link_tbl->pg_list[i].buf)
1560 dma_free_coherent(dev, link_tbl->pg_sz,
1561 link_tbl->pg_list[i].buf,
1562 link_tbl->pg_list[i].map);
1563 kfree(link_tbl->pg_list);
1564
1565 dma_free_coherent(dev, size, link_tbl->table.buf,
1566 link_tbl->table.map);
1567}
1568
1569static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
1570{
ded58ff9 1571 struct hns_roce_v2_priv *priv = hr_dev->priv;
6b63597d 1572 int ret;
1573
1574 /* TSQ includes SQ doorbell and ack doorbell */
1575 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 1576 if (ret) {
6b63597d 1577 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 1578 return ret;
1579 }
1580
1581 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
1582 if (ret) {
1583 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
1584 goto err_tpq_init_failed;
1585 }
1586
1587 return 0;
1588
1589err_tpq_init_failed:
1590 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 1591
1592 return ret;
1593}
1594
1595static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
1596{
1597 struct hns_roce_v2_priv *priv = hr_dev->priv;
1598
ded58ff9 1599 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 1600 hns_roce_free_link_table(hr_dev, &priv->tsq);
1601}
1602
a680f2f3
WHX		 1603static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
1604{
1605 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1606
1607 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
1608}
1609
1610static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
1611{
1612 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
1613
1614 return status & HNS_ROCE_HW_MB_STATUS_MASK;
1615}
1616
1617static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1618 u64 out_param, u32 in_modifier, u8 op_modifier,
1619 u16 op, u16 token, int event)
1620{
1621 struct device *dev = hr_dev->dev;
cc4ed08b
BVA		 1622 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base +
1623 ROCEE_VF_MB_CFG0_REG);
a680f2f3
WHX		 1624 unsigned long end;
1625 u32 val0 = 0;
1626 u32 val1 = 0;
1627
1628 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1629 while (hns_roce_v2_cmd_pending(hr_dev)) {
1630 if (time_after(jiffies, end)) {
1631 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1632 (int)end);
1633 return -EAGAIN;
1634 }
1635 cond_resched();
1636 }
1637
1638 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK,
1639 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier);
1640 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK,
1641 HNS_ROCE_VF_MB4_CMD_SHIFT, op);
1642 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK,
1643 HNS_ROCE_VF_MB5_EVENT_SHIFT, event);
1644 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK,
1645 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token);
1646
71591d12
AS		 1647 writeq(in_param, hcr + 0);
1648 writeq(out_param, hcr + 2);
a680f2f3
WHX		 1649
1650 /* Memory barrier */
1651 wmb();
1652
71591d12
AS		 1653 writel(val0, hcr + 4);
1654 writel(val1, hcr + 5);
a680f2f3
WHX		 1655
1656 mmiowb();
1657
1658 return 0;
1659}
1660
1661static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1662 unsigned long timeout)
1663{
1664 struct device *dev = hr_dev->dev;
1665 unsigned long end = 0;
1666 u32 status;
1667
1668 end = msecs_to_jiffies(timeout) + jiffies;
1669 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1670 cond_resched();
1671
1672 if (hns_roce_v2_cmd_pending(hr_dev)) {
1673 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1674 return -ETIMEDOUT;
1675 }
1676
1677 status = hns_roce_v2_cmd_complete(hr_dev);
1678 if (status != 0x1) {
1679 dev_err(dev, "mailbox status 0x%x!\n", status);
1680 return -EBUSY;
1681 }
1682
1683 return 0;
1684}
1685
4db134a3 1686static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
1687 int gid_index, const union ib_gid *gid,
1688 enum hns_roce_sgid_type sgid_type)
1689{
1690 struct hns_roce_cmq_desc desc;
1691 struct hns_roce_cfg_sgid_tb *sgid_tb =
1692 (struct hns_roce_cfg_sgid_tb *)desc.data;
1693 u32 *p;
1694
1695 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
1696
1697 roce_set_field(sgid_tb->table_idx_rsv,
1698 CFG_SGID_TB_TABLE_IDX_M,
1699 CFG_SGID_TB_TABLE_IDX_S, gid_index);
1700 roce_set_field(sgid_tb->vf_sgid_type_rsv,
1701 CFG_SGID_TB_VF_SGID_TYPE_M,
1702 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
1703
1704 p = (u32 *)&gid->raw[0];
1705 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
1706
1707 p = (u32 *)&gid->raw[4];
1708 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
1709
1710 p = (u32 *)&gid->raw[8];
1711 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
1712
1713 p = (u32 *)&gid->raw[0xc];
1714 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
1715
1716 return hns_roce_cmq_send(hr_dev, &desc, 1);
1717}
1718
b5ff0f61 1719static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 1720 int gid_index, const union ib_gid *gid,
b5ff0f61 1721 const struct ib_gid_attr *attr)
7afddafa 1722{
b5ff0f61 1723 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 1724 int ret;
7afddafa 1725
b5ff0f61
WHX		 1726 if (!gid || !attr)
1727 return -EINVAL;
1728
1729 if (attr->gid_type == IB_GID_TYPE_ROCE)
1730 sgid_type = GID_TYPE_FLAG_ROCE_V1;
1731
1732 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
1733 if (ipv6_addr_v4mapped((void *)gid))
1734 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
1735 else
1736 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
1737 }
1738
4db134a3 1739 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
1740 if (ret)
1741 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);
b5ff0f61 1742
4db134a3 1743 return ret;
7afddafa
WHX		 1744}
1745
a74dc41d
WHX		 1746static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1747 u8 *addr)
7afddafa 1748{
e8e8b652 1749 struct hns_roce_cmq_desc desc;
1750 struct hns_roce_cfg_smac_tb *smac_tb =
1751 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 1752 u16 reg_smac_h;
1753 u32 reg_smac_l;
e8e8b652 1754
1755 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 1756
1757 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 1758 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 1759
e8e8b652 1760 memset(smac_tb, 0, sizeof(*smac_tb));
1761 roce_set_field(smac_tb->tb_idx_rsv,
1762 CFG_SMAC_TB_IDX_M,
1763 CFG_SMAC_TB_IDX_S, phy_port);
1764 roce_set_field(smac_tb->vf_smac_h_rsv,
1765 CFG_SMAC_TB_VF_SMAC_H_M,
1766 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
1767 smac_tb->vf_smac_l = reg_smac_l;
a74dc41d 1768
e8e8b652 1769 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 1770}
1771
3958cc56
WHX		 1772static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1773 unsigned long mtpt_idx)
1774{
1775 struct hns_roce_v2_mpt_entry *mpt_entry;
1776 struct scatterlist *sg;
db270c41 1777 u64 page_addr;
3958cc56 1778 u64 *pages;
db270c41
WHX		 1779 int i, j;
1780 int len;
3958cc56 1781 int entry;
3958cc56
WHX		 1782
1783 mpt_entry = mb_buf;
1784 memset(mpt_entry, 0, sizeof(*mpt_entry));
1785
1786 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1787 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
1788 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1789 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
1790 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
1791 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1792 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 1793 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1794 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1795 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1796 V2_MPT_BYTE_4_PD_S, mr->pd);
1797 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
1798
1799 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
1800 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
e93df010 1801 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 1802 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
1803 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 1804 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
1805 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 1806 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1807 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1808 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1809 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1810 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1811 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1812 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
1813
1814 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
1815 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 1816 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
1817 1);
3958cc56
WHX		 1818 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
1819
1820 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
1821 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
1822 mpt_entry->lkey = cpu_to_le32(mr->key);
1823 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
1824 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
1825
1826 if (mr->type == MR_TYPE_DMA)
1827 return 0;
1828
1829 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1830
1831 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1832 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1833 V2_MPT_BYTE_48_PBL_BA_H_S,
1834 upper_32_bits(mr->pbl_ba >> 3));
1835 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
1836
1837 pages = (u64 *)__get_free_page(GFP_KERNEL);
1838 if (!pages)
1839 return -ENOMEM;
1840
1841 i = 0;
1842 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
db270c41
WHX		 1843 len = sg_dma_len(sg) >> PAGE_SHIFT;
1844 for (j = 0; j < len; ++j) {
1845 page_addr = sg_dma_address(sg) +
1846 (j << mr->umem->page_shift);
1847 pages[i] = page_addr >> 6;
1848
1849 /* Record the first 2 entry directly to MTPT table */
1850 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1851 goto found;
1852 i++;
1853 }
3958cc56
WHX		 1854 }
1855
db270c41 1856found:
3958cc56
WHX		 1857 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1858 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1859 V2_MPT_BYTE_56_PA0_H_S,
1860 upper_32_bits(pages[0]));
1861 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
1862
1863 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
1864 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
1865 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
1866
1867 free_page((unsigned long)pages);
1868
1869 roce_set_field(mpt_entry->byte_64_buf_pa1,
1870 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
5e6e78db
YL		 1871 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1872 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 1873 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
1874
1875 return 0;
1876}
1877
a2c80b7b
WHX		 1878static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
1879 struct hns_roce_mr *mr, int flags,
1880 u32 pdn, int mr_access_flags, u64 iova,
1881 u64 size, void *mb_buf)
1882{
1883 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
1884
1885 if (flags & IB_MR_REREG_PD) {
1886 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1887 V2_MPT_BYTE_4_PD_S, pdn);
1888 mr->pd = pdn;
1889 }
1890
1891 if (flags & IB_MR_REREG_ACCESS) {
1892 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1893 V2_MPT_BYTE_8_BIND_EN_S,
1894 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
1895 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1896 V2_MPT_BYTE_8_ATOMIC_EN_S,
1897 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
1898 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1899 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
1900 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1901 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1902 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1903 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1904 }
1905
1906 if (flags & IB_MR_REREG_TRANS) {
1907 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
1908 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
1909 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
1910 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
1911
1912 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1913 mpt_entry->pbl_ba_l =
1914 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1915 roce_set_field(mpt_entry->byte_48_mode_ba,
1916 V2_MPT_BYTE_48_PBL_BA_H_M,
1917 V2_MPT_BYTE_48_PBL_BA_H_S,
1918 upper_32_bits(mr->pbl_ba >> 3));
1919 mpt_entry->byte_48_mode_ba =
1920 cpu_to_le32(mpt_entry->byte_48_mode_ba);
1921
1922 mr->iova = iova;
1923 mr->size = size;
1924 }
1925
1926 return 0;
1927}
1928
68a997c5
YL		 1929static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
1930{
1931 struct hns_roce_v2_mpt_entry *mpt_entry;
1932
1933 mpt_entry = mb_buf;
1934 memset(mpt_entry, 0, sizeof(*mpt_entry));
1935
1936 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1937 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
1938 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1939 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
1940 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1941 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1942 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1943 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
1944 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1945 V2_MPT_BYTE_4_PD_S, mr->pd);
1946
1947 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
1948 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1949 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
1950
1951 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
1952 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
1953 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
1954 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
1955
1956 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1957
1958 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1959 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1960 V2_MPT_BYTE_48_PBL_BA_H_S,
1961 upper_32_bits(mr->pbl_ba >> 3));
1962
1963 roce_set_field(mpt_entry->byte_64_buf_pa1,
1964 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
1965 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
1966 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
1967
1968 return 0;
1969}
1970
c7c28191
YL		 1971static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
1972{
1973 struct hns_roce_v2_mpt_entry *mpt_entry;
1974
1975 mpt_entry = mb_buf;
1976 memset(mpt_entry, 0, sizeof(*mpt_entry));
1977
1978 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1979 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
1980 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1981 V2_MPT_BYTE_4_PD_S, mw->pdn);
1982 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1983 V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1984 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
1985 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ?
1986 0 : mw->pbl_hop_num);
1987 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1988 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1989 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
1990 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
1991
1992 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1993 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
1994
1995 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
1996 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
1997 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
1998 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
1999 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2000
2001 roce_set_field(mpt_entry->byte_64_buf_pa1,
2002 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2003 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2004 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2005
2006 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2007
2008 return 0;
2009}
2010
93aa2187
WHX		 2011static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2012{
2013 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2014 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
2015}
2016
2017static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2018{
2019 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2020
2021 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2022 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
2023 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
2024}
2025
2026static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
2027{
2028 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
2029}
2030
2031static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2032{
86188a88 2033 *hr_cq->set_ci_db = cons_index & 0xffffff;
93aa2187
WHX		 2034}
2035
926a01dc
WHX		 2036static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2037 struct hns_roce_srq *srq)
2038{
2039 struct hns_roce_v2_cqe *cqe, *dest;
2040 u32 prod_index;
2041 int nfreed = 0;
2042 u8 owner_bit;
2043
2044 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2045 ++prod_index) {
2046 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2047 break;
2048 }
2049
2050 /*
2051 * Now backwards through the CQ, removing CQ entries
2052 * that match our QP by overwriting them with next entries.
2053 */
2054 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2055 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2056 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2057 V2_CQE_BYTE_16_LCL_QPN_S) &
2058 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
2059 /* In v1 engine, not support SRQ */
2060 ++nfreed;
2061 } else if (nfreed) {
2062 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2063 hr_cq->ib_cq.cqe);
2064 owner_bit = roce_get_bit(dest->byte_4,
2065 V2_CQE_BYTE_4_OWNER_S);
2066 memcpy(dest, cqe, sizeof(*cqe));
2067 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2068 owner_bit);
2069 }
2070 }
2071
2072 if (nfreed) {
2073 hr_cq->cons_index += nfreed;
2074 /*
2075 * Make sure update of buffer contents is done before
2076 * updating consumer index.
2077 */
2078 wmb();
2079 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2080 }
2081}
2082
2083static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2084 struct hns_roce_srq *srq)
2085{
2086 spin_lock_irq(&hr_cq->lock);
2087 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2088 spin_unlock_irq(&hr_cq->lock);
2089}
2090
93aa2187
WHX		 2091static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2092 struct hns_roce_cq *hr_cq, void *mb_buf,
2093 u64 *mtts, dma_addr_t dma_handle, int nent,
2094 u32 vector)
2095{
2096 struct hns_roce_v2_cq_context *cq_context;
2097
2098 cq_context = mb_buf;
2099 memset(cq_context, 0, sizeof(*cq_context));
2100
2101 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2102 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2103 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2104 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187
WHX		 2105 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
2106 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
2107 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
2108 V2_CQC_BYTE_4_CEQN_S, vector);
2109 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
2110
2111 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2112 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2113
2114 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2115 cq_context->cqe_cur_blk_addr =
2116 cpu_to_le32(cq_context->cqe_cur_blk_addr);
2117
2118 roce_set_field(cq_context->byte_16_hop_addr,
2119 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2120 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
2121 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
2122 roce_set_field(cq_context->byte_16_hop_addr,
2123 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2124 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2125 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2126
2127 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
2128 roce_set_field(cq_context->byte_24_pgsz_addr,
2129 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2130 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
2131 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
2132 roce_set_field(cq_context->byte_24_pgsz_addr,
2133 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2134 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 2135 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2136 roce_set_field(cq_context->byte_24_pgsz_addr,
2137 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2138 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 2139 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2140
2141 cq_context->cqe_ba = (u32)(dma_handle >> 3);
2142
2143 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2144 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2145
9b44703d
YL		 2146 if (hr_cq->db_en)
2147 roce_set_bit(cq_context->byte_44_db_record,
2148 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
2149
2150 roce_set_field(cq_context->byte_44_db_record,
2151 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2152 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2153 ((u32)hr_cq->db.dma) >> 1);
2154 cq_context->db_record_addr = hr_cq->db.dma >> 32;
2155
a5073d60
YL		 2156 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2157 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2158 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2159 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2160 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2161 V2_CQC_BYTE_56_CQ_PERIOD_M,
2162 V2_CQC_BYTE_56_CQ_PERIOD_S,
2163 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2164}
2165
2166static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2167 enum ib_cq_notify_flags flags)
2168{
2169 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2170 u32 notification_flag;
2171 u32 doorbell[2];
2172
2173 doorbell[0] = 0;
2174 doorbell[1] = 0;
2175
2176 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2177 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2178 /*
2179 * flags = 0; Notification Flag = 1, next
2180 * flags = 1; Notification Flag = 0, solocited
2181 */
2182 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2183 hr_cq->cqn);
2184 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2185 HNS_ROCE_V2_CQ_DB_NTR);
2186 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2187 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2188 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2189 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2190 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2191 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2192 notification_flag);
2193
2194 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2195
2196 return 0;
2197}
2198
0009c2db 2199static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2200 struct hns_roce_qp **cur_qp,
2201 struct ib_wc *wc)
2202{
2203 struct hns_roce_rinl_sge *sge_list;
2204 u32 wr_num, wr_cnt, sge_num;
2205 u32 sge_cnt, data_len, size;
2206 void *wqe_buf;
2207
2208 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2209 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2210 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2211
2212 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2213 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
2214 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt);
2215 data_len = wc->byte_len;
2216
2217 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2218 size = min(sge_list[sge_cnt].len, data_len);
2219 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2220
2221 data_len -= size;
2222 wqe_buf += size;
2223 }
2224
2225 if (data_len) {
2226 wc->status = IB_WC_LOC_LEN_ERR;
2227 return -EAGAIN;
2228 }
2229
2230 return 0;
2231}
2232
93aa2187
WHX		 2233static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2234 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2235{
2236 struct hns_roce_dev *hr_dev;
2237 struct hns_roce_v2_cqe *cqe;
2238 struct hns_roce_qp *hr_qp;
2239 struct hns_roce_wq *wq;
0425e3e6
YL		 2240 struct ib_qp_attr attr;
2241 int attr_mask;
93aa2187
WHX		 2242 int is_send;
2243 u16 wqe_ctr;
2244 u32 opcode;
2245 u32 status;
2246 int qpn;
0009c2db 2247 int ret;
93aa2187
WHX		 2248
2249 /* Find cqe according to consumer index */
2250 cqe = next_cqe_sw_v2(hr_cq);
2251 if (!cqe)
2252 return -EAGAIN;
2253
2254 ++hr_cq->cons_index;
2255 /* Memory barrier */
2256 rmb();
2257
2258 /* 0->SQ, 1->RQ */
2259 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2260
2261 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2262 V2_CQE_BYTE_16_LCL_QPN_S);
2263
2264 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2265 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2266 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2267 if (unlikely(!hr_qp)) {
2268 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
2269 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
2270 return -EINVAL;
2271 }
2272 *cur_qp = hr_qp;
2273 }
2274
2275 wc->qp = &(*cur_qp)->ibqp;
2276 wc->vendor_err = 0;
2277
2278 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
2279 V2_CQE_BYTE_4_STATUS_S);
2280 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
2281 case HNS_ROCE_CQE_V2_SUCCESS:
2282 wc->status = IB_WC_SUCCESS;
2283 break;
2284 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
2285 wc->status = IB_WC_LOC_LEN_ERR;
2286 break;
2287 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
2288 wc->status = IB_WC_LOC_QP_OP_ERR;
2289 break;
2290 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
2291 wc->status = IB_WC_LOC_PROT_ERR;
2292 break;
2293 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
2294 wc->status = IB_WC_WR_FLUSH_ERR;
2295 break;
2296 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
2297 wc->status = IB_WC_MW_BIND_ERR;
2298 break;
2299 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
2300 wc->status = IB_WC_BAD_RESP_ERR;
2301 break;
2302 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
2303 wc->status = IB_WC_LOC_ACCESS_ERR;
2304 break;
2305 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
2306 wc->status = IB_WC_REM_INV_REQ_ERR;
2307 break;
2308 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
2309 wc->status = IB_WC_REM_ACCESS_ERR;
2310 break;
2311 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
2312 wc->status = IB_WC_REM_OP_ERR;
2313 break;
2314 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
2315 wc->status = IB_WC_RETRY_EXC_ERR;
2316 break;
2317 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
2318 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2319 break;
2320 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
2321 wc->status = IB_WC_REM_ABORT_ERR;
2322 break;
2323 default:
2324 wc->status = IB_WC_GENERAL_ERR;
2325 break;
2326 }
2327
0425e3e6
YL		 2328 /* flush cqe if wc status is error, excluding flush error */
2329 if ((wc->status != IB_WC_SUCCESS) &&
2330 (wc->status != IB_WC_WR_FLUSH_ERR)) {
2331 attr_mask = IB_QP_STATE;
2332 attr.qp_state = IB_QPS_ERR;
2333 return hns_roce_v2_modify_qp(&(*cur_qp)->ibqp,
2334 &attr, attr_mask,
2335 (*cur_qp)->state, IB_QPS_ERR);
2336 }
2337
2338 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 2339 return 0;
2340
2341 if (is_send) {
2342 wc->wc_flags = 0;
2343 /* SQ corresponding to CQE */
2344 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2345 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
2346 case HNS_ROCE_SQ_OPCODE_SEND:
2347 wc->opcode = IB_WC_SEND;
2348 break;
2349 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
2350 wc->opcode = IB_WC_SEND;
2351 break;
2352 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
2353 wc->opcode = IB_WC_SEND;
2354 wc->wc_flags |= IB_WC_WITH_IMM;
2355 break;
2356 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
2357 wc->opcode = IB_WC_RDMA_READ;
2358 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2359 break;
2360 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
2361 wc->opcode = IB_WC_RDMA_WRITE;
2362 break;
2363 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
2364 wc->opcode = IB_WC_RDMA_WRITE;
2365 wc->wc_flags |= IB_WC_WITH_IMM;
2366 break;
2367 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
2368 wc->opcode = IB_WC_LOCAL_INV;
2369 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2370 break;
2371 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
2372 wc->opcode = IB_WC_COMP_SWAP;
2373 wc->byte_len = 8;
2374 break;
2375 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
2376 wc->opcode = IB_WC_FETCH_ADD;
2377 wc->byte_len = 8;
2378 break;
2379 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
2380 wc->opcode = IB_WC_MASKED_COMP_SWAP;
2381 wc->byte_len = 8;
2382 break;
2383 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
2384 wc->opcode = IB_WC_MASKED_FETCH_ADD;
2385 wc->byte_len = 8;
2386 break;
2387 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
2388 wc->opcode = IB_WC_REG_MR;
2389 break;
2390 case HNS_ROCE_SQ_OPCODE_BIND_MW:
2391 wc->opcode = IB_WC_REG_MR;
2392 break;
2393 default:
2394 wc->status = IB_WC_GENERAL_ERR;
2395 break;
2396 }
2397
2398 wq = &(*cur_qp)->sq;
2399 if ((*cur_qp)->sq_signal_bits) {
2400 /*
2401 * If sg_signal_bit is 1,
2402 * firstly tail pointer updated to wqe
2403 * which current cqe correspond to
2404 */
2405 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
2406 V2_CQE_BYTE_4_WQE_INDX_M,
2407 V2_CQE_BYTE_4_WQE_INDX_S);
2408 wq->tail += (wqe_ctr - (u16)wq->tail) &
2409 (wq->wqe_cnt - 1);
2410 }
2411
2412 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2413 ++wq->tail;
2414 } else {
2415 /* RQ correspond to CQE */
2416 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2417
2418 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2419 V2_CQE_BYTE_4_OPCODE_S);
2420 switch (opcode & 0x1f) {
2421 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
2422 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2423 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2424 wc->ex.imm_data =
2425 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2426 break;
2427 case HNS_ROCE_V2_OPCODE_SEND:
2428 wc->opcode = IB_WC_RECV;
2429 wc->wc_flags = 0;
2430 break;
2431 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
2432 wc->opcode = IB_WC_RECV;
2433 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2434 wc->ex.imm_data =
2435 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2436 break;
2437 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
2438 wc->opcode = IB_WC_RECV;
2439 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 2440 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 2441 break;
2442 default:
2443 wc->status = IB_WC_GENERAL_ERR;
2444 break;
2445 }
2446
0009c2db 2447 if ((wc->qp->qp_type == IB_QPT_RC ||
2448 wc->qp->qp_type == IB_QPT_UC) &&
2449 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
2450 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
2451 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
2452 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
2453 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
2454 if (ret)
2455 return -EAGAIN;
2456 }
2457
93aa2187
WHX		 2458 /* Update tail pointer, record wr_id */
2459 wq = &(*cur_qp)->rq;
2460 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2461 ++wq->tail;
2462
2463 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
2464 V2_CQE_BYTE_32_SL_S);
2465 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
2466 V2_CQE_BYTE_32_RMT_QPN_M,
2467 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 2468 wc->slid = 0;
93aa2187
WHX		 2469 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
2470 V2_CQE_BYTE_32_GRH_S) ?
2471 IB_WC_GRH : 0);
6c1f08b3 2472 wc->port_num = roce_get_field(cqe->byte_32,
2473 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
2474 wc->pkey_index = 0;
2eade675 2475 memcpy(wc->smac, cqe->smac, 4);
2476 wc->smac[4] = roce_get_field(cqe->byte_28,
2477 V2_CQE_BYTE_28_SMAC_4_M,
2478 V2_CQE_BYTE_28_SMAC_4_S);
2479 wc->smac[5] = roce_get_field(cqe->byte_28,
2480 V2_CQE_BYTE_28_SMAC_5_M,
2481 V2_CQE_BYTE_28_SMAC_5_S);
944e6409
LO		 2482 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
2483 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
2484 V2_CQE_BYTE_28_VID_M,
2485 V2_CQE_BYTE_28_VID_S);
2486 } else {
2487 wc->vlan_id = 0xffff;
2488 }
2489
2eade675 2490 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
2491 wc->network_hdr_type = roce_get_field(cqe->byte_28,
2492 V2_CQE_BYTE_28_PORT_TYPE_M,
2493 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 2494 }
2495
2496 return 0;
2497}
2498
2499static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
2500 struct ib_wc *wc)
2501{
2502 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2503 struct hns_roce_qp *cur_qp = NULL;
2504 unsigned long flags;
2505 int npolled;
2506
2507 spin_lock_irqsave(&hr_cq->lock, flags);
2508
2509 for (npolled = 0; npolled < num_entries; ++npolled) {
2510 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
2511 break;
2512 }
2513
2514 if (npolled) {
2515 /* Memory barrier */
2516 wmb();
2517 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2518 }
2519
2520 spin_unlock_irqrestore(&hr_cq->lock, flags);
2521
2522 return npolled;
2523}
2524
a81fba28
WHX		 2525static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
2526 struct hns_roce_hem_table *table, int obj,
2527 int step_idx)
2528{
2529 struct device *dev = hr_dev->dev;
2530 struct hns_roce_cmd_mailbox *mailbox;
2531 struct hns_roce_hem_iter iter;
2532 struct hns_roce_hem_mhop mhop;
2533 struct hns_roce_hem *hem;
2534 unsigned long mhop_obj = obj;
2535 int i, j, k;
2536 int ret = 0;
2537 u64 hem_idx = 0;
2538 u64 l1_idx = 0;
2539 u64 bt_ba = 0;
2540 u32 chunk_ba_num;
2541 u32 hop_num;
2542 u16 op = 0xff;
2543
2544 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2545 return 0;
2546
2547 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
2548 i = mhop.l0_idx;
2549 j = mhop.l1_idx;
2550 k = mhop.l2_idx;
2551 hop_num = mhop.hop_num;
2552 chunk_ba_num = mhop.bt_chunk_size / 8;
2553
2554 if (hop_num == 2) {
2555 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
2556 k;
2557 l1_idx = i * chunk_ba_num + j;
2558 } else if (hop_num == 1) {
2559 hem_idx = i * chunk_ba_num + j;
2560 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
2561 hem_idx = i;
2562 }
2563
2564 switch (table->type) {
2565 case HEM_TYPE_QPC:
2566 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
2567 break;
2568 case HEM_TYPE_MTPT:
2569 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
2570 break;
2571 case HEM_TYPE_CQC:
2572 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
2573 break;
2574 case HEM_TYPE_SRQC:
2575 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
2576 break;
2577 default:
2578 dev_warn(dev, "Table %d not to be written by mailbox!\n",
2579 table->type);
2580 return 0;
2581 }
2582 op += step_idx;
2583
2584 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2585 if (IS_ERR(mailbox))
2586 return PTR_ERR(mailbox);
2587
2588 if (check_whether_last_step(hop_num, step_idx)) {
2589 hem = table->hem[hem_idx];
2590 for (hns_roce_hem_first(hem, &iter);
2591 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
2592 bt_ba = hns_roce_hem_addr(&iter);
2593
2594 /* configure the ba, tag, and op */
2595 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
2596 obj, 0, op,
2597 HNS_ROCE_CMD_TIMEOUT_MSECS);
2598 }
2599 } else {
2600 if (step_idx == 0)
2601 bt_ba = table->bt_l0_dma_addr[i];
2602 else if (step_idx == 1 && hop_num == 2)
2603 bt_ba = table->bt_l1_dma_addr[l1_idx];
2604
2605 /* configure the ba, tag, and op */
2606 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
2607 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
2608 }
2609
2610 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2611 return ret;
2612}
2613
2614static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
2615 struct hns_roce_hem_table *table, int obj,
2616 int step_idx)
2617{
2618 struct device *dev = hr_dev->dev;
2619 struct hns_roce_cmd_mailbox *mailbox;
2620 int ret = 0;
2621 u16 op = 0xff;
2622
2623 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2624 return 0;
2625
2626 switch (table->type) {
2627 case HEM_TYPE_QPC:
2628 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
2629 break;
2630 case HEM_TYPE_MTPT:
2631 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
2632 break;
2633 case HEM_TYPE_CQC:
2634 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
2635 break;
2636 case HEM_TYPE_SRQC:
2637 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
2638 break;
2639 default:
2640 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
2641 table->type);
2642 return 0;
2643 }
2644 op += step_idx;
2645
2646 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2647 if (IS_ERR(mailbox))
2648 return PTR_ERR(mailbox);
2649
2650 /* configure the tag and op */
2651 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
2652 HNS_ROCE_CMD_TIMEOUT_MSECS);
2653
2654 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2655 return ret;
2656}
2657
926a01dc
WHX		 2658static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
2659 struct hns_roce_mtt *mtt,
2660 enum ib_qp_state cur_state,
2661 enum ib_qp_state new_state,
2662 struct hns_roce_v2_qp_context *context,
2663 struct hns_roce_qp *hr_qp)
2664{
2665 struct hns_roce_cmd_mailbox *mailbox;
2666 int ret;
2667
2668 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2669 if (IS_ERR(mailbox))
2670 return PTR_ERR(mailbox);
2671
2672 memcpy(mailbox->buf, context, sizeof(*context) * 2);
2673
2674 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2675 HNS_ROCE_CMD_MODIFY_QPC,
2676 HNS_ROCE_CMD_TIMEOUT_MSECS);
2677
2678 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2679
2680 return ret;
2681}
2682
ace1c541 2683static void set_access_flags(struct hns_roce_qp *hr_qp,
2684 struct hns_roce_v2_qp_context *context,
2685 struct hns_roce_v2_qp_context *qpc_mask,
2686 const struct ib_qp_attr *attr, int attr_mask)
2687{
2688 u8 dest_rd_atomic;
2689 u32 access_flags;
2690
c2799119 2691 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 2692 attr->max_dest_rd_atomic : hr_qp->resp_depth;
2693
c2799119 2694 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 2695 attr->qp_access_flags : hr_qp->atomic_rd_en;
2696
2697 if (!dest_rd_atomic)
2698 access_flags &= IB_ACCESS_REMOTE_WRITE;
2699
2700 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2701 !!(access_flags & IB_ACCESS_REMOTE_READ));
2702 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
2703
2704 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2705 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
2706 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
2707
2708 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2709 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
2710 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
2711}
2712
926a01dc
WHX		 2713static void modify_qp_reset_to_init(struct ib_qp *ibqp,
2714 const struct ib_qp_attr *attr,
0fa95a9a 2715 int attr_mask,
926a01dc
WHX		 2716 struct hns_roce_v2_qp_context *context,
2717 struct hns_roce_v2_qp_context *qpc_mask)
2718{
ecaaf1e2 2719 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 2720 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2721
2722 /*
2723 * In v2 engine, software pass context and context mask to hardware
2724 * when modifying qp. If software need modify some fields in context,
2725 * we should set all bits of the relevant fields in context mask to
2726 * 0 at the same time, else set them to 0x1.
2727 */
2728 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2729 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2730 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2731 V2_QPC_BYTE_4_TST_S, 0);
2732
0fa95a9a 2733 if (ibqp->qp_type == IB_QPT_GSI)
2734 roce_set_field(context->byte_4_sqpn_tst,
2735 V2_QPC_BYTE_4_SGE_SHIFT_M,
2736 V2_QPC_BYTE_4_SGE_SHIFT_S,
2737 ilog2((unsigned int)hr_qp->sge.sge_cnt));
2738 else
2739 roce_set_field(context->byte_4_sqpn_tst,
2740 V2_QPC_BYTE_4_SGE_SHIFT_M,
2741 V2_QPC_BYTE_4_SGE_SHIFT_S,
2742 hr_qp->sq.max_gs > 2 ?
2743 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2744
926a01dc
WHX		 2745 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2746 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2747
2748 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2749 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2750 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2751 V2_QPC_BYTE_4_SQPN_S, 0);
2752
2753 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2754 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2755 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2756 V2_QPC_BYTE_16_PD_S, 0);
2757
2758 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2759 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
2760 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
2761 V2_QPC_BYTE_20_RQWS_S, 0);
2762
2763 roce_set_field(context->byte_20_smac_sgid_idx,
2764 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2765 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2766 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2767 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2768
2769 roce_set_field(context->byte_20_smac_sgid_idx,
2770 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2771 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2772 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2773 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2774
2775 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 2776 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2777 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
2778 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
2779 V2_QPC_BYTE_24_VLAN_ID_S, 0);
926a01dc
WHX		 2780
2781 /*
2782 * Set some fields in context to zero, Because the default values
2783 * of all fields in context are zero, we need not set them to 0 again.
2784 * but we should set the relevant fields of context mask to 0.
2785 */
2786 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
2787 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
2788 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
2789 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
2790
2362ccee
LO		 2791 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_TEMPID_M,
2792 V2_QPC_BYTE_60_TEMPID_S, 0);
2793
2794 roce_set_field(qpc_mask->byte_60_qpst_tempid,
2795 V2_QPC_BYTE_60_SCC_TOKEN_M, V2_QPC_BYTE_60_SCC_TOKEN_S,
2796 0);
2797 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2798 V2_QPC_BYTE_60_SQ_DB_DOING_S, 0);
2799 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
2800 V2_QPC_BYTE_60_RQ_DB_DOING_S, 0);
926a01dc
WHX		 2801 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
2802 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
2803
0fa95a9a 2804 if (attr_mask & IB_QP_QKEY) {
2805 context->qkey_xrcd = attr->qkey;
2806 qpc_mask->qkey_xrcd = 0;
2807 hr_qp->qkey = attr->qkey;
2808 }
2809
e088a685
YL		 2810 if (hr_qp->rdb_en) {
2811 roce_set_bit(context->byte_68_rq_db,
2812 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
2813 roce_set_bit(qpc_mask->byte_68_rq_db,
2814 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0);
2815 }
2816
2817 roce_set_field(context->byte_68_rq_db,
2818 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2819 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
2820 ((u32)hr_qp->rdb.dma) >> 1);
2821 roce_set_field(qpc_mask->byte_68_rq_db,
2822 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
2823 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0);
2824 context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
2825 qpc_mask->rq_db_record_addr = 0;
2826
ecaaf1e2 2827 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
2828 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 2829 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
2830
2831 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2832 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2833 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2834 V2_QPC_BYTE_80_RX_CQN_S, 0);
2835 if (ibqp->srq) {
2836 roce_set_field(context->byte_76_srqn_op_en,
2837 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2838 to_hr_srq(ibqp->srq)->srqn);
2839 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2840 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2841 roce_set_bit(context->byte_76_srqn_op_en,
2842 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2843 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2844 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2845 }
2846
2847 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2848 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2849 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
2850 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2851 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
2852 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
2853
2854 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
2855 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
2856
2857 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
2858 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
2859
2860 roce_set_field(qpc_mask->byte_104_rq_sge,
2861 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
2862 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
2863
2864 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2865 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
2866 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2867 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
2868 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
2869 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2870 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
2871
2872 qpc_mask->rq_rnr_timer = 0;
2873 qpc_mask->rx_msg_len = 0;
2874 qpc_mask->rx_rkey_pkt_info = 0;
2875 qpc_mask->rx_va = 0;
2876
2877 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2878 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2879 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2880 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2881
2362ccee
LO		 2882 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S,
2883 0);
926a01dc
WHX		 2884 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
2885 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
2886 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
2887 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
2888
2889 roce_set_field(qpc_mask->byte_144_raq,
2890 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
2891 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
926a01dc
WHX		 2892 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
2893 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
2894 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
2895
2896 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
2897 V2_QPC_BYTE_148_RQ_MSN_S, 0);
2898 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
2899 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
2900
2901 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2902 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2903 roce_set_field(qpc_mask->byte_152_raq,
2904 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
2905 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
2906
2907 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
2908 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
2909
2910 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2911 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
2912 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
2913 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2914 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
2915 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
2916
2362ccee
LO		 2917 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2918 V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S, 0);
2919 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2920 V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S, 0);
2921 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2922 V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S, 0);
926a01dc
WHX		 2923 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2924 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 2925 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2926 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 2927 roce_set_field(qpc_mask->byte_168_irrl_idx,
2928 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
2929 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
2930
2931 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2932 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
2933 roce_set_field(qpc_mask->byte_172_sq_psn,
2934 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2935 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
2936
2937 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
2938 0);
2939
68a997c5
YL		 2940 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
2941 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 0);
2942
926a01dc
WHX		 2943 roce_set_field(qpc_mask->byte_176_msg_pktn,
2944 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
2945 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
2946 roce_set_field(qpc_mask->byte_176_msg_pktn,
2947 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
2948 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
2949
2950 roce_set_field(qpc_mask->byte_184_irrl_idx,
2951 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
2952 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
2953
2954 qpc_mask->cur_sge_offset = 0;
2955
2956 roce_set_field(qpc_mask->byte_192_ext_sge,
2957 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
2958 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
2959 roce_set_field(qpc_mask->byte_192_ext_sge,
2960 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
2961 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
2962
2963 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2964 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2965
2966 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
2967 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
2968 roce_set_field(qpc_mask->byte_200_sq_max,
2969 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
2970 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
2971
2972 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
2973 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
2974
2975 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2976 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2977
2978 qpc_mask->sq_timer = 0;
2979
2980 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2981 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2982 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2983 roce_set_field(qpc_mask->byte_232_irrl_sge,
2984 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2985 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2986
2362ccee
LO		 2987 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_SO_LP_VLD_S,
2988 0);
2989 roce_set_bit(qpc_mask->byte_232_irrl_sge,
2990 V2_QPC_BYTE_232_FENCE_LP_VLD_S, 0);
2991 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_IRRL_LP_VLD_S,
2992 0);
2993
926a01dc
WHX		 2994 qpc_mask->irrl_cur_sge_offset = 0;
2995
2996 roce_set_field(qpc_mask->byte_240_irrl_tail,
2997 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2998 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2999 roce_set_field(qpc_mask->byte_240_irrl_tail,
3000 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
3001 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
3002 roce_set_field(qpc_mask->byte_240_irrl_tail,
3003 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3004 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3005
3006 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
3007 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3008 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
3009 0);
3010 roce_set_field(qpc_mask->byte_248_ack_psn,
3011 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3012 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3013 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
3014 0);
3015 roce_set_bit(qpc_mask->byte_248_ack_psn,
3016 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3017 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
3018 0);
3019
3020 hr_qp->access_flags = attr->qp_access_flags;
3021 hr_qp->pkey_index = attr->pkey_index;
3022 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3023 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
3024 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3025 V2_QPC_BYTE_252_TX_CQN_S, 0);
3026
3027 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
3028 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
3029
3030 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3031 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
3032 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
3033 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3034 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
3035 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
3036}
3037
3038static void modify_qp_init_to_init(struct ib_qp *ibqp,
3039 const struct ib_qp_attr *attr, int attr_mask,
3040 struct hns_roce_v2_qp_context *context,
3041 struct hns_roce_v2_qp_context *qpc_mask)
3042{
3043 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3044
3045 /*
3046 * In v2 engine, software pass context and context mask to hardware
3047 * when modifying qp. If software need modify some fields in context,
3048 * we should set all bits of the relevant fields in context mask to
3049 * 0 at the same time, else set them to 0x1.
3050 */
3051 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3052 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3053 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3054 V2_QPC_BYTE_4_TST_S, 0);
3055
0fa95a9a 3056 if (ibqp->qp_type == IB_QPT_GSI)
3057 roce_set_field(context->byte_4_sqpn_tst,
3058 V2_QPC_BYTE_4_SGE_SHIFT_M,
3059 V2_QPC_BYTE_4_SGE_SHIFT_S,
3060 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3061 else
3062 roce_set_field(context->byte_4_sqpn_tst,
3063 V2_QPC_BYTE_4_SGE_SHIFT_M,
3064 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
3065 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3066
926a01dc
WHX		 3067 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
3068 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
3069
3070 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3071 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3072 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3073 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3074 0);
3075
3076 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3077 !!(attr->qp_access_flags &
3078 IB_ACCESS_REMOTE_WRITE));
3079 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3080 0);
3081
3082 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3083 !!(attr->qp_access_flags &
3084 IB_ACCESS_REMOTE_ATOMIC));
3085 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3086 0);
3087 } else {
3088 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3089 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3090 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3091 0);
3092
3093 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3094 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3095 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3096 0);
3097
3098 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3099 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3100 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3101 0);
3102 }
3103
3104 roce_set_field(context->byte_20_smac_sgid_idx,
3105 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3106 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
3107 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3108 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
3109
3110 roce_set_field(context->byte_20_smac_sgid_idx,
3111 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
3112 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
3113 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3114 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
3115
3116 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3117 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3118 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3119 V2_QPC_BYTE_16_PD_S, 0);
3120
3121 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3122 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3123 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3124 V2_QPC_BYTE_80_RX_CQN_S, 0);
3125
3126 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3127 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3128 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3129 V2_QPC_BYTE_252_TX_CQN_S, 0);
3130
3131 if (ibqp->srq) {
3132 roce_set_bit(context->byte_76_srqn_op_en,
3133 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3134 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3135 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3136 roce_set_field(context->byte_76_srqn_op_en,
3137 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3138 to_hr_srq(ibqp->srq)->srqn);
3139 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3140 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3141 }
3142
0fa95a9a 3143 if (attr_mask & IB_QP_QKEY) {
3144 context->qkey_xrcd = attr->qkey;
3145 qpc_mask->qkey_xrcd = 0;
3146 }
926a01dc
WHX		 3147
3148 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3149 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3150 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3151 V2_QPC_BYTE_4_SQPN_S, 0);
3152
b6dd9b34 3153 if (attr_mask & IB_QP_DEST_QPN) {
3154 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3155 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3156 roce_set_field(qpc_mask->byte_56_dqpn_err,
3157 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3158 }
926a01dc
WHX		 3159}
3160
3161static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3162 const struct ib_qp_attr *attr, int attr_mask,
3163 struct hns_roce_v2_qp_context *context,
3164 struct hns_roce_v2_qp_context *qpc_mask)
3165{
3166 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3167 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3168 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3169 struct device *dev = hr_dev->dev;
e92f2c18 3170 dma_addr_t dma_handle_3;
926a01dc
WHX		 3171 dma_addr_t dma_handle_2;
3172 dma_addr_t dma_handle;
3173 u32 page_size;
3174 u8 port_num;
e92f2c18 3175 u64 *mtts_3;
926a01dc
WHX		 3176 u64 *mtts_2;
3177 u64 *mtts;
3178 u8 *dmac;
3179 u8 *smac;
3180 int port;
3181
3182 /* Search qp buf's mtts */
3183 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3184 hr_qp->mtt.first_seg, &dma_handle);
3185 if (!mtts) {
3186 dev_err(dev, "qp buf pa find failed\n");
3187 return -EINVAL;
3188 }
3189
3190 /* Search IRRL's mtts */
3191 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3192 hr_qp->qpn, &dma_handle_2);
3193 if (!mtts_2) {
3194 dev_err(dev, "qp irrl_table find failed\n");
3195 return -EINVAL;
3196 }
3197
e92f2c18 3198 /* Search TRRL's mtts */
3199 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3200 hr_qp->qpn, &dma_handle_3);
3201 if (!mtts_3) {
3202 dev_err(dev, "qp trrl_table find failed\n");
3203 return -EINVAL;
3204 }
3205
734f3863 3206 if (attr_mask & IB_QP_ALT_PATH) {
926a01dc
WHX		 3207 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
3208 return -EINVAL;
3209 }
3210
3211 dmac = (u8 *)attr->ah_attr.roce.dmac;
3212 context->wqe_sge_ba = (u32)(dma_handle >> 3);
3213 qpc_mask->wqe_sge_ba = 0;
3214
3215 /*
3216 * In v2 engine, software pass context and context mask to hardware
3217 * when modifying qp. If software need modify some fields in context,
3218 * we should set all bits of the relevant fields in context mask to
3219 * 0 at the same time, else set them to 0x1.
3220 */
3221 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3222 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
3223 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3224 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3225
3226 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3227 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
3228 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3229 0 : hr_dev->caps.mtt_hop_num);
3230 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3231 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3232
3233 roce_set_field(context->byte_20_smac_sgid_idx,
3234 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3235 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
0fa95a9a 3236 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
3237 hr_dev->caps.mtt_hop_num : 0);
926a01dc
WHX		 3238 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3239 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3240 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3241
3242 roce_set_field(context->byte_20_smac_sgid_idx,
3243 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3244 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
3245 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3246 0 : hr_dev->caps.mtt_hop_num);
3247 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3248 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3249 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3250
3251 roce_set_field(context->byte_16_buf_ba_pg_sz,
3252 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3253 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
5e6e78db 3254 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3255 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3256 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3257 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3258
3259 roce_set_field(context->byte_16_buf_ba_pg_sz,
3260 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3261 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
5e6e78db 3262 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3263 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3264 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3265 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3266
3267 roce_set_field(context->byte_80_rnr_rx_cqn,
3268 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3269 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
3270 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
3271 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3272 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
3273
3274 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
3275 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
3276 >> PAGE_ADDR_SHIFT);
3277 qpc_mask->rq_cur_blk_addr = 0;
3278
3279 roce_set_field(context->byte_92_srq_info,
3280 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3281 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
3282 mtts[hr_qp->rq.offset / page_size]
3283 >> (32 + PAGE_ADDR_SHIFT));
3284 roce_set_field(qpc_mask->byte_92_srq_info,
3285 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3286 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3287
3288 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
3289 >> PAGE_ADDR_SHIFT);
3290 qpc_mask->rq_nxt_blk_addr = 0;
3291
3292 roce_set_field(context->byte_104_rq_sge,
3293 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3294 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
3295 mtts[hr_qp->rq.offset / page_size + 1]
3296 >> (32 + PAGE_ADDR_SHIFT));
3297 roce_set_field(qpc_mask->byte_104_rq_sge,
3298 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3299 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3300
3301 roce_set_field(context->byte_108_rx_reqepsn,
3302 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3303 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
3304 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3305 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3306 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
3307
e92f2c18 3308 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3309 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3310 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3311 V2_QPC_BYTE_132_TRRL_BA_S, 0);
3312 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
3313 qpc_mask->trrl_ba = 0;
3314 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3315 V2_QPC_BYTE_140_TRRL_BA_S,
3316 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3317 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3318 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3319
d5514246 3320 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 3321 qpc_mask->irrl_ba = 0;
3322 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3323 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3324 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3325 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3326 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3327
3328 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3329 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3330
3331 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3332 hr_qp->sq_signal_bits);
3333 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3334 0);
3335
3336 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3337
3338 smac = (u8 *)hr_dev->dev_addr[port];
3339 /* when dmac equals smac or loop_idc is 1, it should loopback */
3340 if (ether_addr_equal_unaligned(dmac, smac) ||
3341 hr_dev->loop_idc == 0x1) {
3342 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3343 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3344 }
3345
4f3f7a70 3346 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
3347 attr->max_dest_rd_atomic) {
3348 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3349 V2_QPC_BYTE_140_RR_MAX_S,
3350 fls(attr->max_dest_rd_atomic - 1));
3351 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3352 V2_QPC_BYTE_140_RR_MAX_S, 0);
3353 }
926a01dc 3354
b6dd9b34 3355 if (attr_mask & IB_QP_DEST_QPN) {
3356 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3357 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3358 roce_set_field(qpc_mask->byte_56_dqpn_err,
3359 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3360 }
926a01dc
WHX		 3361
3362 /* Configure GID index */
3363 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3364 roce_set_field(context->byte_20_smac_sgid_idx,
3365 V2_QPC_BYTE_20_SGID_IDX_M,
3366 V2_QPC_BYTE_20_SGID_IDX_S,
3367 hns_get_gid_index(hr_dev, port_num - 1,
3368 grh->sgid_index));
3369 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3370 V2_QPC_BYTE_20_SGID_IDX_M,
3371 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3372 memcpy(&(context->dmac), dmac, 4);
3373 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3374 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3375 qpc_mask->dmac = 0;
3376 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3377 V2_QPC_BYTE_52_DMAC_S, 0);
3378
3379 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3380 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
3381 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3382 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3383
0fa95a9a 3384 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3385 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3386 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3387 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3388 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3389 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3390
926a01dc
WHX		 3391 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3392 V2_QPC_BYTE_24_MTU_S, 0);
3393
926a01dc
WHX		 3394 roce_set_field(context->byte_84_rq_ci_pi,
3395 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3396 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3397 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3398 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3399 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3400
3401 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3402 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3403 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3404 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3405 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3406 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3407 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3408 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3409 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3410 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3411
3412 context->rq_rnr_timer = 0;
3413 qpc_mask->rq_rnr_timer = 0;
3414
3415 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3416 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
3417 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3418 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3419
3420 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3421 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3422 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3423 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3424
3425 roce_set_field(context->byte_168_irrl_idx,
3426 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3427 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3428 roce_set_field(qpc_mask->byte_168_irrl_idx,
3429 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3430 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3431
926a01dc
WHX		 3432 return 0;
3433}
3434
3435static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3436 const struct ib_qp_attr *attr, int attr_mask,
3437 struct hns_roce_v2_qp_context *context,
3438 struct hns_roce_v2_qp_context *qpc_mask)
3439{
3440 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3441 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3442 struct device *dev = hr_dev->dev;
3443 dma_addr_t dma_handle;
befb63b4 3444 u32 page_size;
926a01dc
WHX		 3445 u64 *mtts;
3446
3447 /* Search qp buf's mtts */
3448 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3449 hr_qp->mtt.first_seg, &dma_handle);
3450 if (!mtts) {
3451 dev_err(dev, "qp buf pa find failed\n");
3452 return -EINVAL;
3453 }
3454
734f3863 3455 /* Not support alternate path and path migration */
3456 if ((attr_mask & IB_QP_ALT_PATH) ||
3457 (attr_mask & IB_QP_PATH_MIG_STATE)) {
926a01dc
WHX		 3458 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
3459 return -EINVAL;
3460 }
3461
3462 /*
3463 * In v2 engine, software pass context and context mask to hardware
3464 * when modifying qp. If software need modify some fields in context,
3465 * we should set all bits of the relevant fields in context mask to
3466 * 0 at the same time, else set them to 0x1.
3467 */
926a01dc
WHX		 3468 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3469 roce_set_field(context->byte_168_irrl_idx,
3470 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3471 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3472 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3473 qpc_mask->sq_cur_blk_addr = 0;
3474 roce_set_field(qpc_mask->byte_168_irrl_idx,
3475 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3476 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3477
befb63b4 3478 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
0fa95a9a 3479 context->sq_cur_sge_blk_addr =
3480 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3481 ((u32)(mtts[hr_qp->sge.offset / page_size]
3482 >> PAGE_ADDR_SHIFT)) : 0;
3483 roce_set_field(context->byte_184_irrl_idx,
3484 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3485 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
0fa95a9a 3486 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3487 (mtts[hr_qp->sge.offset / page_size] >>
3488 (32 + PAGE_ADDR_SHIFT)) : 0);
3489 qpc_mask->sq_cur_sge_blk_addr = 0;
3490 roce_set_field(qpc_mask->byte_184_irrl_idx,
3491 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3492 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3493
926a01dc
WHX		 3494 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3495 roce_set_field(context->byte_232_irrl_sge,
3496 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3497 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3498 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3499 qpc_mask->rx_sq_cur_blk_addr = 0;
3500 roce_set_field(qpc_mask->byte_232_irrl_sge,
3501 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3502 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3503
3504 /*
3505 * Set some fields in context to zero, Because the default values
3506 * of all fields in context are zero, we need not set them to 0 again.
3507 * but we should set the relevant fields of context mask to 0.
3508 */
3509 roce_set_field(qpc_mask->byte_232_irrl_sge,
3510 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3511 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3512
3513 roce_set_field(qpc_mask->byte_240_irrl_tail,
3514 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3515 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3516
3517 roce_set_field(context->byte_244_rnr_rxack,
3518 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3519 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
3520 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3521 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3522 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
3523
3524 roce_set_field(qpc_mask->byte_248_ack_psn,
3525 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3526 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3527 roce_set_bit(qpc_mask->byte_248_ack_psn,
3528 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
3529 roce_set_field(qpc_mask->byte_248_ack_psn,
3530 V2_QPC_BYTE_248_IRRL_PSN_M,
3531 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3532
3533 roce_set_field(qpc_mask->byte_240_irrl_tail,
3534 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3535 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3536
3537 roce_set_field(context->byte_220_retry_psn_msn,
3538 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3539 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
3540 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3541 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3542 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
3543
3544 roce_set_field(context->byte_224_retry_msg,
3545 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3546 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
3547 roce_set_field(qpc_mask->byte_224_retry_msg,
3548 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3549 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
3550
3551 roce_set_field(context->byte_224_retry_msg,
3552 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3553 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
3554 roce_set_field(qpc_mask->byte_224_retry_msg,
3555 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3556 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
3557
3558 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3559 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3560 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3561
3562 roce_set_bit(qpc_mask->byte_248_ack_psn,
3563 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3564
3565 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3566 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3567
3568 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3569 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
3570 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3571 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
3572
3573 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3574 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
3575 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3576 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
3577
3578 roce_set_field(context->byte_244_rnr_rxack,
3579 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3580 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
3581 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3582 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3583 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
3584
3585 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3586 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
3587 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3588 V2_QPC_BYTE_244_RNR_CNT_S, 0);
3589
3590 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3591 V2_QPC_BYTE_212_LSN_S, 0x100);
3592 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3593 V2_QPC_BYTE_212_LSN_S, 0);
3594
28726461 3595 if (attr_mask & IB_QP_TIMEOUT) {
926a01dc
WHX		 3596 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3597 V2_QPC_BYTE_28_AT_S, attr->timeout);
28726461 3598 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
3599 V2_QPC_BYTE_28_AT_S, 0);
3600 }
926a01dc 3601
926a01dc
WHX		 3602 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3603 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
3604 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3605 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
3606
3607 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3608 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3609 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3610 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
3611 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3612 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
3613
4f3f7a70 3614 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
3615 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
3616 V2_QPC_BYTE_208_SR_MAX_S,
3617 fls(attr->max_rd_atomic - 1));
3618 roce_set_field(qpc_mask->byte_208_irrl,
3619 V2_QPC_BYTE_208_SR_MAX_M,
3620 V2_QPC_BYTE_208_SR_MAX_S, 0);
3621 }
926a01dc
WHX		 3622 return 0;
3623}
3624
3625static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
3626 const struct ib_qp_attr *attr,
3627 int attr_mask, enum ib_qp_state cur_state,
3628 enum ib_qp_state new_state)
3629{
3630 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3631 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3632 struct hns_roce_v2_qp_context *context;
3633 struct hns_roce_v2_qp_context *qpc_mask;
3634 struct device *dev = hr_dev->dev;
3635 int ret = -EINVAL;
3636
6396bb22 3637 context = kcalloc(2, sizeof(*context), GFP_KERNEL);
926a01dc
WHX		 3638 if (!context)
3639 return -ENOMEM;
3640
3641 qpc_mask = context + 1;
3642 /*
3643 * In v2 engine, software pass context and context mask to hardware
3644 * when modifying qp. If software need modify some fields in context,
3645 * we should set all bits of the relevant fields in context mask to
3646 * 0 at the same time, else set them to 0x1.
3647 */
3648 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
3649 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
0fa95a9a 3650 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
3651 qpc_mask);
926a01dc
WHX		 3652 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3653 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
3654 qpc_mask);
3655 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3656 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
3657 qpc_mask);
3658 if (ret)
3659 goto out;
3660 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3661 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
3662 qpc_mask);
3663 if (ret)
3664 goto out;
3665 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) ||
3666 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) ||
3667 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) ||
3668 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) ||
3669 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) ||
3670 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3671 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3672 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3673 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3674 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3675 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3676 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3677 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) ||
6e1a7094 3678 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR) ||
3679 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR)) {
926a01dc
WHX		 3680 /* Nothing */
3681 ;
3682 } else {
3683 dev_err(dev, "Illegal state for QP!\n");
ac7cbf96 3684 ret = -EINVAL;
926a01dc
WHX		 3685 goto out;
3686 }
3687
0425e3e6
YL		 3688 /* When QP state is err, SQ and RQ WQE should be flushed */
3689 if (new_state == IB_QPS_ERR) {
3690 roce_set_field(context->byte_160_sq_ci_pi,
3691 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3692 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
3693 hr_qp->sq.head);
3694 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3695 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3696 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
3697 roce_set_field(context->byte_84_rq_ci_pi,
3698 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3699 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
3700 hr_qp->rq.head);
3701 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3702 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3703 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3704 }
3705
610b8967
LO		 3706 if (attr_mask & IB_QP_AV) {
3707 const struct ib_global_route *grh =
3708 rdma_ah_read_grh(&attr->ah_attr);
3709 const struct ib_gid_attr *gid_attr = NULL;
3710 u8 src_mac[ETH_ALEN];
3711 int is_roce_protocol;
3712 u16 vlan = 0xffff;
3713 u8 ib_port;
3714 u8 hr_port;
3715
3716 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num :
3717 hr_qp->port + 1;
3718 hr_port = ib_port - 1;
3719 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
3720 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
3721
3722 if (is_roce_protocol) {
3723 gid_attr = attr->ah_attr.grh.sgid_attr;
3724 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
3725 memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN);
3726 }
3727
caf3e406
LO		 3728 if (is_vlan_dev(gid_attr->ndev)) {
3729 roce_set_bit(context->byte_76_srqn_op_en,
3730 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
3731 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3732 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
3733 roce_set_bit(context->byte_168_irrl_idx,
3734 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
3735 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3736 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
3737 }
3738
c8e46f8d
LO		 3739 roce_set_field(context->byte_24_mtu_tc,
3740 V2_QPC_BYTE_24_VLAN_ID_M,
3741 V2_QPC_BYTE_24_VLAN_ID_S, vlan);
3742 roce_set_field(qpc_mask->byte_24_mtu_tc,
3743 V2_QPC_BYTE_24_VLAN_ID_M,
3744 V2_QPC_BYTE_24_VLAN_ID_S, 0);
3745
610b8967
LO		 3746 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
3747 dev_err(hr_dev->dev,
3748 "sgid_index(%u) too large. max is %d\n",
3749 grh->sgid_index,
3750 hr_dev->caps.gid_table_len[hr_port]);
3751 ret = -EINVAL;
3752 goto out;
3753 }
3754
3755 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
3756 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n");
3757 ret = -EINVAL;
3758 goto out;
3759 }
3760
3761 roce_set_field(context->byte_52_udpspn_dmac,
3762 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S,
3763 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3764 0 : 0x12b7);
3765
3766 roce_set_field(qpc_mask->byte_52_udpspn_dmac,
3767 V2_QPC_BYTE_52_UDPSPN_M,
3768 V2_QPC_BYTE_52_UDPSPN_S, 0);
3769
3770 roce_set_field(context->byte_20_smac_sgid_idx,
3771 V2_QPC_BYTE_20_SGID_IDX_M,
3772 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index);
3773
3774 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3775 V2_QPC_BYTE_20_SGID_IDX_M,
3776 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3777
3778 roce_set_field(context->byte_24_mtu_tc,
3779 V2_QPC_BYTE_24_HOP_LIMIT_M,
3780 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
3781 roce_set_field(qpc_mask->byte_24_mtu_tc,
3782 V2_QPC_BYTE_24_HOP_LIMIT_M,
3783 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
3784
157b52a0
LO		 3785 if (hr_dev->pci_dev->revision == 0x21 &&
3786 gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
3787 roce_set_field(context->byte_24_mtu_tc,
3788 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
3789 grh->traffic_class >> 2);
3790 else
3791 roce_set_field(context->byte_24_mtu_tc,
3792 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
3793 grh->traffic_class);
610b8967
LO		 3794 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
3795 V2_QPC_BYTE_24_TC_S, 0);
3796 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3797 V2_QPC_BYTE_28_FL_S, grh->flow_label);
3798 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
3799 V2_QPC_BYTE_28_FL_S, 0);
3800 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
3801 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
3802 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3803 V2_QPC_BYTE_28_SL_S,
3804 rdma_ah_get_sl(&attr->ah_attr));
3805 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
3806 V2_QPC_BYTE_28_SL_S, 0);
3807 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3808 }
3809
ace1c541 3810 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3811 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
3812
926a01dc 3813 /* Every status migrate must change state */
2362ccee 3814 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 3815 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 3816 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 3817 V2_QPC_BYTE_60_QP_ST_S, 0);
3818
3819 /* SW pass context to HW */
3820 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
3821 context, hr_qp);
3822 if (ret) {
3823 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
3824 goto out;
3825 }
3826
3827 hr_qp->state = new_state;
3828
ace1c541 3829 if (attr_mask & IB_QP_ACCESS_FLAGS)
3830 hr_qp->atomic_rd_en = attr->qp_access_flags;
3831
926a01dc
WHX		 3832 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3833 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3834 if (attr_mask & IB_QP_PORT) {
3835 hr_qp->port = attr->port_num - 1;
3836 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3837 }
3838
3839 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3840 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3841 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3842 if (ibqp->send_cq != ibqp->recv_cq)
3843 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
3844 hr_qp->qpn, NULL);
3845
3846 hr_qp->rq.head = 0;
3847 hr_qp->rq.tail = 0;
3848 hr_qp->sq.head = 0;
3849 hr_qp->sq.tail = 0;
3850 hr_qp->sq_next_wqe = 0;
3851 hr_qp->next_sge = 0;
e088a685
YL		 3852 if (hr_qp->rq.wqe_cnt)
3853 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 3854 }
3855
3856out:
3857 kfree(context);
3858 return ret;
3859}
3860
3861static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
3862{
3863 switch (state) {
3864 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
3865 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
3866 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
3867 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
3868 case HNS_ROCE_QP_ST_SQ_DRAINING:
3869 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
3870 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
3871 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
3872 default: return -1;
3873 }
3874}
3875
3876static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
3877 struct hns_roce_qp *hr_qp,
3878 struct hns_roce_v2_qp_context *hr_context)
3879{
3880 struct hns_roce_cmd_mailbox *mailbox;
3881 int ret;
3882
3883 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3884 if (IS_ERR(mailbox))
3885 return PTR_ERR(mailbox);
3886
3887 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3888 HNS_ROCE_CMD_QUERY_QPC,
3889 HNS_ROCE_CMD_TIMEOUT_MSECS);
3890 if (ret) {
3891 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
3892 goto out;
3893 }
3894
3895 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3896
3897out:
3898 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3899 return ret;
3900}
3901
3902static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3903 int qp_attr_mask,
3904 struct ib_qp_init_attr *qp_init_attr)
3905{
3906 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3907 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3908 struct hns_roce_v2_qp_context *context;
3909 struct device *dev = hr_dev->dev;
3910 int tmp_qp_state;
3911 int state;
3912 int ret;
3913
3914 context = kzalloc(sizeof(*context), GFP_KERNEL);
3915 if (!context)
3916 return -ENOMEM;
3917
3918 memset(qp_attr, 0, sizeof(*qp_attr));
3919 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3920
3921 mutex_lock(&hr_qp->mutex);
3922
3923 if (hr_qp->state == IB_QPS_RESET) {
3924 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 3925 ret = 0;
926a01dc
WHX		 3926 goto done;
3927 }
3928
3929 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
3930 if (ret) {
3931 dev_err(dev, "query qpc error\n");
3932 ret = -EINVAL;
3933 goto out;
3934 }
3935
2362ccee 3936 state = roce_get_field(context->byte_60_qpst_tempid,
926a01dc
WHX		 3937 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
3938 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
3939 if (tmp_qp_state == -1) {
3940 dev_err(dev, "Illegal ib_qp_state\n");
3941 ret = -EINVAL;
3942 goto out;
3943 }
3944 hr_qp->state = (u8)tmp_qp_state;
3945 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3946 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
3947 V2_QPC_BYTE_24_MTU_M,
3948 V2_QPC_BYTE_24_MTU_S);
3949 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 3950 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 3951 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3952 qp_attr->qkey = V2_QKEY_VAL;
3953
3954 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
3955 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3956 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
3957 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
3958 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3959 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
3960 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
3961 V2_QPC_BYTE_56_DQPN_M,
3962 V2_QPC_BYTE_56_DQPN_S);
3963 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
3964 V2_QPC_BYTE_76_RRE_S)) << 2) |
3965 ((roce_get_bit(context->byte_76_srqn_op_en,
3966 V2_QPC_BYTE_76_RWE_S)) << 1) |
3967 ((roce_get_bit(context->byte_76_srqn_op_en,
3968 V2_QPC_BYTE_76_ATE_S)) << 3);
3969 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3970 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3971 struct ib_global_route *grh =
3972 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3973
3974 rdma_ah_set_sl(&qp_attr->ah_attr,
3975 roce_get_field(context->byte_28_at_fl,
3976 V2_QPC_BYTE_28_SL_M,
3977 V2_QPC_BYTE_28_SL_S));
3978 grh->flow_label = roce_get_field(context->byte_28_at_fl,
3979 V2_QPC_BYTE_28_FL_M,
3980 V2_QPC_BYTE_28_FL_S);
3981 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
3982 V2_QPC_BYTE_20_SGID_IDX_M,
3983 V2_QPC_BYTE_20_SGID_IDX_S);
3984 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
3985 V2_QPC_BYTE_24_HOP_LIMIT_M,
3986 V2_QPC_BYTE_24_HOP_LIMIT_S);
3987 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
3988 V2_QPC_BYTE_24_TC_M,
3989 V2_QPC_BYTE_24_TC_S);
3990
3991 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
3992 }
3993
3994 qp_attr->port_num = hr_qp->port + 1;
3995 qp_attr->sq_draining = 0;
3996 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
3997 V2_QPC_BYTE_208_SR_MAX_M,
3998 V2_QPC_BYTE_208_SR_MAX_S);
3999 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
4000 V2_QPC_BYTE_140_RR_MAX_M,
4001 V2_QPC_BYTE_140_RR_MAX_S);
4002 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
4003 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4004 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4005 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
4006 V2_QPC_BYTE_28_AT_M,
4007 V2_QPC_BYTE_28_AT_S);
4008 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
4009 V2_QPC_BYTE_212_RETRY_CNT_M,
4010 V2_QPC_BYTE_212_RETRY_CNT_S);
4011 qp_attr->rnr_retry = context->rq_rnr_timer;
4012
4013done:
4014 qp_attr->cur_qp_state = qp_attr->qp_state;
4015 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4016 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4017
4018 if (!ibqp->uobject) {
4019 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4020 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4021 } else {
4022 qp_attr->cap.max_send_wr = 0;
4023 qp_attr->cap.max_send_sge = 0;
4024 }
4025
4026 qp_init_attr->cap = qp_attr->cap;
4027
4028out:
4029 mutex_unlock(&hr_qp->mutex);
4030 kfree(context);
4031 return ret;
4032}
4033
4034static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4035 struct hns_roce_qp *hr_qp,
4036 int is_user)
4037{
4038 struct hns_roce_cq *send_cq, *recv_cq;
4039 struct device *dev = hr_dev->dev;
4040 int ret;
4041
4042 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4043 /* Modify qp to reset before destroying qp */
4044 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4045 hr_qp->state, IB_QPS_RESET);
4046 if (ret) {
4047 dev_err(dev, "modify QP %06lx to ERR failed.\n",
4048 hr_qp->qpn);
4049 return ret;
4050 }
4051 }
4052
4053 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
4054 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
4055
4056 hns_roce_lock_cqs(send_cq, recv_cq);
4057
4058 if (!is_user) {
4059 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
4060 to_hr_srq(hr_qp->ibqp.srq) : NULL);
4061 if (send_cq != recv_cq)
4062 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
4063 }
4064
4065 hns_roce_qp_remove(hr_dev, hr_qp);
4066
4067 hns_roce_unlock_cqs(send_cq, recv_cq);
4068
4069 hns_roce_qp_free(hr_dev, hr_qp);
4070
4071 /* Not special_QP, free their QPN */
4072 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
4073 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
4074 (hr_qp->ibqp.qp_type == IB_QPT_UD))
4075 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
4076
4077 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
4078
4079 if (is_user) {
0425e3e6
YL		 4080 if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1))
4081 hns_roce_db_unmap_user(
4082 to_hr_ucontext(hr_qp->ibqp.uobject->context),
4083 &hr_qp->sdb);
4084
e088a685
YL		 4085 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1))
4086 hns_roce_db_unmap_user(
4087 to_hr_ucontext(hr_qp->ibqp.uobject->context),
4088 &hr_qp->rdb);
926a01dc
WHX		 4089 ib_umem_release(hr_qp->umem);
4090 } else {
4091 kfree(hr_qp->sq.wrid);
4092 kfree(hr_qp->rq.wrid);
4093 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
472bc0fb
YL		 4094 if (hr_qp->rq.wqe_cnt)
4095 hns_roce_free_db(hr_dev, &hr_qp->rdb);
926a01dc
WHX		 4096 }
4097
0009c2db 4098 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
4099 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
4100 kfree(hr_qp->rq_inl_buf.wqe_list);
4101 }
4102
926a01dc
WHX		 4103 return 0;
4104}
4105
4106static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
4107{
4108 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4109 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4110 int ret;
4111
4112 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
4113 if (ret) {
4114 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
4115 return ret;
4116 }
4117
4118 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
4119 kfree(hr_to_hr_sqp(hr_qp));
4120 else
4121 kfree(hr_qp);
4122
4123 return 0;
4124}
4125
b156269d 4126static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
4127{
4128 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
4129 struct hns_roce_v2_cq_context *cq_context;
4130 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
4131 struct hns_roce_v2_cq_context *cqc_mask;
4132 struct hns_roce_cmd_mailbox *mailbox;
4133 int ret;
4134
4135 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4136 if (IS_ERR(mailbox))
4137 return PTR_ERR(mailbox);
4138
4139 cq_context = mailbox->buf;
4140 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
4141
4142 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
4143
4144 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4145 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4146 cq_count);
4147 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4148 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4149 0);
4150 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4151 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4152 cq_period);
4153 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4154 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4155 0);
4156
4157 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
4158 HNS_ROCE_CMD_MODIFY_CQC,
4159 HNS_ROCE_CMD_TIMEOUT_MSECS);
4160 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4161 if (ret)
4162 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
4163
4164 return ret;
4165}
4166
0425e3e6
YL		 4167static void hns_roce_set_qps_to_err(struct hns_roce_dev *hr_dev, u32 qpn)
4168{
4169 struct hns_roce_qp *hr_qp;
4170 struct ib_qp_attr attr;
4171 int attr_mask;
4172 int ret;
4173
4174 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
4175 if (!hr_qp) {
4176 dev_warn(hr_dev->dev, "no hr_qp can be found!\n");
4177 return;
4178 }
4179
4180 if (hr_qp->ibqp.uobject) {
4181 if (hr_qp->sdb_en == 1) {
4182 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
4183 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
4184 } else {
4185 dev_warn(hr_dev->dev, "flush cqe is unsupported in userspace!\n");
4186 return;
4187 }
4188 }
4189
4190 attr_mask = IB_QP_STATE;
4191 attr.qp_state = IB_QPS_ERR;
4192 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, attr_mask,
4193 hr_qp->state, IB_QPS_ERR);
4194 if (ret)
4195 dev_err(hr_dev->dev, "failed to modify qp %d to err state.\n",
4196 qpn);
4197}
4198
4199static void hns_roce_irq_work_handle(struct work_struct *work)
4200{
4201 struct hns_roce_work *irq_work =
4202 container_of(work, struct hns_roce_work, work);
b00a92c8 4203 struct device *dev = irq_work->hr_dev->dev;
0425e3e6 4204 u32 qpn = irq_work->qpn;
b00a92c8 4205 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4206
4207 switch (irq_work->event_type) {
b00a92c8 4208 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4209 dev_info(dev, "Path migrated succeeded.\n");
4210 break;
4211 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4212 dev_warn(dev, "Path migration failed.\n");
4213 break;
4214 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4215 dev_info(dev, "Communication established.\n");
4216 break;
4217 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4218 dev_warn(dev, "Send queue drained.\n");
4219 break;
0425e3e6 4220 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
b00a92c8 4221 dev_err(dev, "Local work queue catastrophic error.\n");
4222 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4223 switch (irq_work->sub_type) {
4224 case HNS_ROCE_LWQCE_QPC_ERROR:
4225 dev_err(dev, "QP %d, QPC error.\n", qpn);
4226 break;
4227 case HNS_ROCE_LWQCE_MTU_ERROR:
4228 dev_err(dev, "QP %d, MTU error.\n", qpn);
4229 break;
4230 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4231 dev_err(dev, "QP %d, WQE BA addr error.\n", qpn);
4232 break;
4233 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4234 dev_err(dev, "QP %d, WQE addr error.\n", qpn);
4235 break;
4236 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4237 dev_err(dev, "QP %d, WQE shift error.\n", qpn);
4238 break;
4239 default:
4240 dev_err(dev, "Unhandled sub_event type %d.\n",
4241 irq_work->sub_type);
4242 break;
4243 }
4244 break;
0425e3e6 4245 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
b00a92c8 4246 dev_err(dev, "Invalid request local work queue error.\n");
4247 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4248 break;
0425e3e6 4249 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4250 dev_err(dev, "Local access violation work queue error.\n");
0425e3e6 4251 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
b00a92c8 4252 switch (irq_work->sub_type) {
4253 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4254 dev_err(dev, "QP %d, R_key violation.\n", qpn);
4255 break;
4256 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4257 dev_err(dev, "QP %d, length error.\n", qpn);
4258 break;
4259 case HNS_ROCE_LAVWQE_VA_ERROR:
4260 dev_err(dev, "QP %d, VA error.\n", qpn);
4261 break;
4262 case HNS_ROCE_LAVWQE_PD_ERROR:
4263 dev_err(dev, "QP %d, PD error.\n", qpn);
4264 break;
4265 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4266 dev_err(dev, "QP %d, rw acc error.\n", qpn);
4267 break;
4268 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4269 dev_err(dev, "QP %d, key state error.\n", qpn);
4270 break;
4271 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4272 dev_err(dev, "QP %d, MR operation error.\n", qpn);
4273 break;
4274 default:
4275 dev_err(dev, "Unhandled sub_event type %d.\n",
4276 irq_work->sub_type);
4277 break;
4278 }
4279 break;
4280 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4281 dev_warn(dev, "SRQ limit reach.\n");
4282 break;
4283 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4284 dev_warn(dev, "SRQ last wqe reach.\n");
4285 break;
4286 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4287 dev_err(dev, "SRQ catas error.\n");
4288 break;
4289 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4290 dev_err(dev, "CQ 0x%x access err.\n", cqn);
4291 break;
4292 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4293 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4294 break;
4295 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4296 dev_warn(dev, "DB overflow.\n");
4297 break;
4298 case HNS_ROCE_EVENT_TYPE_FLR:
4299 dev_warn(dev, "Function level reset.\n");
0425e3e6
YL		 4300 break;
4301 default:
4302 break;
4303 }
4304
4305 kfree(irq_work);
4306}
4307
4308static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4309 struct hns_roce_eq *eq,
4310 u32 qpn, u32 cqn)
0425e3e6
YL		 4311{
4312 struct hns_roce_work *irq_work;
4313
4314 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4315 if (!irq_work)
4316 return;
4317
4318 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4319 irq_work->hr_dev = hr_dev;
4320 irq_work->qpn = qpn;
b00a92c8 4321 irq_work->cqn = cqn;
0425e3e6
YL		 4322 irq_work->event_type = eq->event_type;
4323 irq_work->sub_type = eq->sub_type;
4324 queue_work(hr_dev->irq_workq, &(irq_work->work));
4325}
4326
a5073d60
YL		 4327static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4328{
4329 u32 doorbell[2];
4330
4331 doorbell[0] = 0;
4332 doorbell[1] = 0;
4333
4334 if (eq->type_flag == HNS_ROCE_AEQ) {
4335 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4336 HNS_ROCE_V2_EQ_DB_CMD_S,
4337 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4338 HNS_ROCE_EQ_DB_CMD_AEQ :
4339 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4340 } else {
4341 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4342 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4343
4344 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4345 HNS_ROCE_V2_EQ_DB_CMD_S,
4346 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4347 HNS_ROCE_EQ_DB_CMD_CEQ :
4348 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4349 }
4350
4351 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4352 HNS_ROCE_V2_EQ_DB_PARA_S,
4353 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4354
4355 hns_roce_write64_k(doorbell, eq->doorbell);
a5073d60
YL		 4356}
4357
a5073d60
YL		 4358static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry)
4359{
4360 u32 buf_chk_sz;
4361 unsigned long off;
4362
4363 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4364 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4365
4366 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) +
4367 off % buf_chk_sz);
4368}
4369
4370static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry)
4371{
4372 u32 buf_chk_sz;
4373 unsigned long off;
4374
4375 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4376
4377 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4378
4379 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4380 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) +
4381 off % buf_chk_sz);
4382 else
4383 return (struct hns_roce_aeqe *)((u8 *)
4384 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz);
4385}
4386
4387static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4388{
4389 struct hns_roce_aeqe *aeqe;
4390
4391 if (!eq->hop_num)
4392 aeqe = get_aeqe_v2(eq, eq->cons_index);
4393 else
4394 aeqe = mhop_get_aeqe(eq, eq->cons_index);
4395
4396 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4397 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4398}
4399
4400static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4401 struct hns_roce_eq *eq)
4402{
4403 struct device *dev = hr_dev->dev;
4404 struct hns_roce_aeqe *aeqe;
4405 int aeqe_found = 0;
4406 int event_type;
0425e3e6
YL		 4407 int sub_type;
4408 u32 qpn;
4409 u32 cqn;
a5073d60
YL		 4410
4411 while ((aeqe = next_aeqe_sw_v2(eq))) {
4044a3f4
YL		 4412
4413 /* Make sure we read AEQ entry after we have checked the
4414 * ownership bit
4415 */
4416 dma_rmb();
a5073d60
YL		 4417
4418 event_type = roce_get_field(aeqe->asyn,
4419 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
4420 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 4421 sub_type = roce_get_field(aeqe->asyn,
4422 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
4423 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
4424 qpn = roce_get_field(aeqe->event.qp_event.qp,
4425 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4426 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4427 cqn = roce_get_field(aeqe->event.cq_event.cq,
4428 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4429 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 4430
4431 switch (event_type) {
4432 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 4433 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 4434 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4435 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4436 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4437 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4438 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4439 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 4440 break;
4441 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4442 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4443 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
a5073d60
YL		 4444 break;
4445 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4446 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 4447 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 4448 break;
4449 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 4450 break;
4451 case HNS_ROCE_EVENT_TYPE_MB:
4452 hns_roce_cmd_event(hr_dev,
4453 le16_to_cpu(aeqe->event.cmd.token),
4454 aeqe->event.cmd.status,
4455 le64_to_cpu(aeqe->event.cmd.out_param));
4456 break;
4457 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 4458 break;
4459 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 4460 break;
4461 default:
4462 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4463 event_type, eq->eqn, eq->cons_index);
4464 break;
4465 };
4466
0425e3e6
YL		 4467 eq->event_type = event_type;
4468 eq->sub_type = sub_type;
a5073d60
YL		 4469 ++eq->cons_index;
4470 aeqe_found = 1;
4471
4472 if (eq->cons_index > (2 * eq->entries - 1)) {
4473 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4474 eq->cons_index = 0;
4475 }
b00a92c8 4476 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
a5073d60
YL		 4477 }
4478
4479 set_eq_cons_index_v2(eq);
4480 return aeqe_found;
4481}
4482
4483static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry)
4484{
4485 u32 buf_chk_sz;
4486 unsigned long off;
4487
4488 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4489 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4490
4491 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) +
4492 off % buf_chk_sz);
4493}
4494
4495static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry)
4496{
4497 u32 buf_chk_sz;
4498 unsigned long off;
4499
4500 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4501
4502 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4503
4504 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4505 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) +
4506 off % buf_chk_sz);
4507 else
4508 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off /
4509 buf_chk_sz]) + off % buf_chk_sz);
4510}
4511
4512static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
4513{
4514 struct hns_roce_ceqe *ceqe;
4515
4516 if (!eq->hop_num)
4517 ceqe = get_ceqe_v2(eq, eq->cons_index);
4518 else
4519 ceqe = mhop_get_ceqe(eq, eq->cons_index);
4520
4521 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
4522 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4523}
4524
4525static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
4526 struct hns_roce_eq *eq)
4527{
4528 struct device *dev = hr_dev->dev;
4529 struct hns_roce_ceqe *ceqe;
4530 int ceqe_found = 0;
4531 u32 cqn;
4532
4533 while ((ceqe = next_ceqe_sw_v2(eq))) {
4534
4044a3f4
YL		 4535 /* Make sure we read CEQ entry after we have checked the
4536 * ownership bit
4537 */
4538 dma_rmb();
4539
a5073d60
YL		 4540 cqn = roce_get_field(ceqe->comp,
4541 HNS_ROCE_V2_CEQE_COMP_CQN_M,
4542 HNS_ROCE_V2_CEQE_COMP_CQN_S);
4543
4544 hns_roce_cq_completion(hr_dev, cqn);
4545
4546 ++eq->cons_index;
4547 ceqe_found = 1;
4548
4549 if (eq->cons_index > (2 * eq->entries - 1)) {
4550 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4551 eq->cons_index = 0;
4552 }
4553 }
4554
4555 set_eq_cons_index_v2(eq);
4556
4557 return ceqe_found;
4558}
4559
4560static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
4561{
4562 struct hns_roce_eq *eq = eq_ptr;
4563 struct hns_roce_dev *hr_dev = eq->hr_dev;
4564 int int_work = 0;
4565
4566 if (eq->type_flag == HNS_ROCE_CEQ)
4567 /* Completion event interrupt */
4568 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
4569 else
4570 /* Asychronous event interrupt */
4571 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
4572
4573 return IRQ_RETVAL(int_work);
4574}
4575
4576static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
4577{
4578 struct hns_roce_dev *hr_dev = dev_id;
4579 struct device *dev = hr_dev->dev;
4580 int int_work = 0;
4581 u32 int_st;
4582 u32 int_en;
4583
4584 /* Abnormal interrupt */
4585 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
4586 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
4587
4588 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
4589 dev_err(dev, "AEQ overflow!\n");
4590
4591 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
4592 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4593
a5073d60
YL		 4594 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4595 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4596
4597 int_work = 1;
4598 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
4599 dev_err(dev, "BUS ERR!\n");
4600
4601 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
4602 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4603
a5073d60
YL		 4604 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4605 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4606
4607 int_work = 1;
4608 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
4609 dev_err(dev, "OTHER ERR!\n");
4610
4611 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
4612 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
4613
a5073d60
YL		 4614 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
4615 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
4616
4617 int_work = 1;
4618 } else
4619 dev_err(dev, "There is no abnormal irq found!\n");
4620
4621 return IRQ_RETVAL(int_work);
4622}
4623
4624static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
4625 int eq_num, int enable_flag)
4626{
4627 int i;
4628
4629 if (enable_flag == EQ_ENABLE) {
4630 for (i = 0; i < eq_num; i++)
4631 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4632 i * EQ_REG_OFFSET,
4633 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
4634
4635 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4636 HNS_ROCE_V2_VF_ABN_INT_EN_M);
4637 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4638 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
4639 } else {
4640 for (i = 0; i < eq_num; i++)
4641 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
4642 i * EQ_REG_OFFSET,
4643 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
4644
4645 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
4646 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
4647 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
4648 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
4649 }
4650}
4651
4652static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
4653{
4654 struct device *dev = hr_dev->dev;
4655 int ret;
4656
4657 if (eqn < hr_dev->caps.num_comp_vectors)
4658 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4659 0, HNS_ROCE_CMD_DESTROY_CEQC,
4660 HNS_ROCE_CMD_TIMEOUT_MSECS);
4661 else
4662 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
4663 0, HNS_ROCE_CMD_DESTROY_AEQC,
4664 HNS_ROCE_CMD_TIMEOUT_MSECS);
4665 if (ret)
4666 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
4667}
4668
4669static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev,
4670 struct hns_roce_eq *eq)
4671{
4672 struct device *dev = hr_dev->dev;
4673 u64 idx;
4674 u64 size;
4675 u32 buf_chk_sz;
4676 u32 bt_chk_sz;
4677 u32 mhop_num;
4678 int eqe_alloc;
a5073d60
YL		 4679 int i = 0;
4680 int j = 0;
4681
4682 mhop_num = hr_dev->caps.eqe_hop_num;
4683 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4684 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
a5073d60
YL		 4685
4686 /* hop_num = 0 */
4687 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4688 dma_free_coherent(dev, (unsigned int)(eq->entries *
4689 eq->eqe_size), eq->bt_l0, eq->l0_dma);
4690 return;
4691 }
4692
4693 /* hop_num = 1 or hop = 2 */
4694 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
4695 if (mhop_num == 1) {
4696 for (i = 0; i < eq->l0_last_num; i++) {
4697 if (i == eq->l0_last_num - 1) {
4698 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4699 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4700 dma_free_coherent(dev, size, eq->buf[i],
4701 eq->buf_dma[i]);
4702 break;
4703 }
4704 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
4705 eq->buf_dma[i]);
4706 }
4707 } else if (mhop_num == 2) {
4708 for (i = 0; i < eq->l0_last_num; i++) {
4709 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
4710 eq->l1_dma[i]);
4711
4712 for (j = 0; j < bt_chk_sz / 8; j++) {
4713 idx = i * (bt_chk_sz / 8) + j;
4714 if ((i == eq->l0_last_num - 1)
4715 && j == eq->l1_last_num - 1) {
4716 eqe_alloc = (buf_chk_sz / eq->eqe_size)
4717 * idx;
4718 size = (eq->entries - eqe_alloc)
4719 * eq->eqe_size;
4720 dma_free_coherent(dev, size,
4721 eq->buf[idx],
4722 eq->buf_dma[idx]);
4723 break;
4724 }
4725 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
4726 eq->buf_dma[idx]);
4727 }
4728 }
4729 }
4730 kfree(eq->buf_dma);
4731 kfree(eq->buf);
4732 kfree(eq->l1_dma);
4733 kfree(eq->bt_l1);
4734 eq->buf_dma = NULL;
4735 eq->buf = NULL;
4736 eq->l1_dma = NULL;
4737 eq->bt_l1 = NULL;
4738}
4739
4740static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev,
4741 struct hns_roce_eq *eq)
4742{
4743 u32 buf_chk_sz;
4744
4745 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4746
4747 if (hr_dev->caps.eqe_hop_num) {
4748 hns_roce_mhop_free_eq(hr_dev, eq);
4749 return;
4750 }
4751
4752 if (eq->buf_list)
4753 dma_free_coherent(hr_dev->dev, buf_chk_sz,
4754 eq->buf_list->buf, eq->buf_list->map);
4755}
4756
4757static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
4758 struct hns_roce_eq *eq,
4759 void *mb_buf)
4760{
4761 struct hns_roce_eq_context *eqc;
4762
4763 eqc = mb_buf;
4764 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
4765
4766 /* init eqc */
4767 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
4768 eq->hop_num = hr_dev->caps.eqe_hop_num;
4769 eq->cons_index = 0;
4770 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
4771 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
4772 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
4773 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz;
4774 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz;
4775 eq->shift = ilog2((unsigned int)eq->entries);
4776
4777 if (!eq->hop_num)
4778 eq->eqe_ba = eq->buf_list->map;
4779 else
4780 eq->eqe_ba = eq->l0_dma;
4781
4782 /* set eqc state */
4783 roce_set_field(eqc->byte_4,
4784 HNS_ROCE_EQC_EQ_ST_M,
4785 HNS_ROCE_EQC_EQ_ST_S,
4786 HNS_ROCE_V2_EQ_STATE_VALID);
4787
4788 /* set eqe hop num */
4789 roce_set_field(eqc->byte_4,
4790 HNS_ROCE_EQC_HOP_NUM_M,
4791 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
4792
4793 /* set eqc over_ignore */
4794 roce_set_field(eqc->byte_4,
4795 HNS_ROCE_EQC_OVER_IGNORE_M,
4796 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
4797
4798 /* set eqc coalesce */
4799 roce_set_field(eqc->byte_4,
4800 HNS_ROCE_EQC_COALESCE_M,
4801 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
4802
4803 /* set eqc arm_state */
4804 roce_set_field(eqc->byte_4,
4805 HNS_ROCE_EQC_ARM_ST_M,
4806 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
4807
4808 /* set eqn */
4809 roce_set_field(eqc->byte_4,
4810 HNS_ROCE_EQC_EQN_M,
4811 HNS_ROCE_EQC_EQN_S, eq->eqn);
4812
4813 /* set eqe_cnt */
4814 roce_set_field(eqc->byte_4,
4815 HNS_ROCE_EQC_EQE_CNT_M,
4816 HNS_ROCE_EQC_EQE_CNT_S,
4817 HNS_ROCE_EQ_INIT_EQE_CNT);
4818
4819 /* set eqe_ba_pg_sz */
4820 roce_set_field(eqc->byte_8,
4821 HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db
YL		 4822 HNS_ROCE_EQC_BA_PG_SZ_S,
4823 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4824
4825 /* set eqe_buf_pg_sz */
4826 roce_set_field(eqc->byte_8,
4827 HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db
YL		 4828 HNS_ROCE_EQC_BUF_PG_SZ_S,
4829 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 4830
4831 /* set eq_producer_idx */
4832 roce_set_field(eqc->byte_8,
4833 HNS_ROCE_EQC_PROD_INDX_M,
4834 HNS_ROCE_EQC_PROD_INDX_S,
4835 HNS_ROCE_EQ_INIT_PROD_IDX);
4836
4837 /* set eq_max_cnt */
4838 roce_set_field(eqc->byte_12,
4839 HNS_ROCE_EQC_MAX_CNT_M,
4840 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
4841
4842 /* set eq_period */
4843 roce_set_field(eqc->byte_12,
4844 HNS_ROCE_EQC_PERIOD_M,
4845 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
4846
4847 /* set eqe_report_timer */
4848 roce_set_field(eqc->eqe_report_timer,
4849 HNS_ROCE_EQC_REPORT_TIMER_M,
4850 HNS_ROCE_EQC_REPORT_TIMER_S,
4851 HNS_ROCE_EQ_INIT_REPORT_TIMER);
4852
4853 /* set eqe_ba [34:3] */
4854 roce_set_field(eqc->eqe_ba0,
4855 HNS_ROCE_EQC_EQE_BA_L_M,
4856 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3);
4857
4858 /* set eqe_ba [64:35] */
4859 roce_set_field(eqc->eqe_ba1,
4860 HNS_ROCE_EQC_EQE_BA_H_M,
4861 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35);
4862
4863 /* set eq shift */
4864 roce_set_field(eqc->byte_28,
4865 HNS_ROCE_EQC_SHIFT_M,
4866 HNS_ROCE_EQC_SHIFT_S, eq->shift);
4867
4868 /* set eq MSI_IDX */
4869 roce_set_field(eqc->byte_28,
4870 HNS_ROCE_EQC_MSI_INDX_M,
4871 HNS_ROCE_EQC_MSI_INDX_S,
4872 HNS_ROCE_EQ_INIT_MSI_IDX);
4873
4874 /* set cur_eqe_ba [27:12] */
4875 roce_set_field(eqc->byte_28,
4876 HNS_ROCE_EQC_CUR_EQE_BA_L_M,
4877 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12);
4878
4879 /* set cur_eqe_ba [59:28] */
4880 roce_set_field(eqc->byte_32,
4881 HNS_ROCE_EQC_CUR_EQE_BA_M_M,
4882 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28);
4883
4884 /* set cur_eqe_ba [63:60] */
4885 roce_set_field(eqc->byte_36,
4886 HNS_ROCE_EQC_CUR_EQE_BA_H_M,
4887 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60);
4888
4889 /* set eq consumer idx */
4890 roce_set_field(eqc->byte_36,
4891 HNS_ROCE_EQC_CONS_INDX_M,
4892 HNS_ROCE_EQC_CONS_INDX_S,
4893 HNS_ROCE_EQ_INIT_CONS_IDX);
4894
4895 /* set nex_eqe_ba[43:12] */
4896 roce_set_field(eqc->nxt_eqe_ba0,
4897 HNS_ROCE_EQC_NXT_EQE_BA_L_M,
4898 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12);
4899
4900 /* set nex_eqe_ba[63:44] */
4901 roce_set_field(eqc->nxt_eqe_ba1,
4902 HNS_ROCE_EQC_NXT_EQE_BA_H_M,
4903 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44);
4904}
4905
4906static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev,
4907 struct hns_roce_eq *eq)
4908{
4909 struct device *dev = hr_dev->dev;
4910 int eq_alloc_done = 0;
4911 int eq_buf_cnt = 0;
4912 int eqe_alloc;
4913 u32 buf_chk_sz;
4914 u32 bt_chk_sz;
4915 u32 mhop_num;
4916 u64 size;
4917 u64 idx;
4918 int ba_num;
4919 int bt_num;
4920 int record_i;
4921 int record_j;
4922 int i = 0;
4923 int j = 0;
4924
4925 mhop_num = hr_dev->caps.eqe_hop_num;
4926 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
4927 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
4928
4929 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1)
4930 / buf_chk_sz;
4931 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8);
4932
4933 /* hop_num = 0 */
4934 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
4935 if (eq->entries > buf_chk_sz / eq->eqe_size) {
4936 dev_err(dev, "eq entries %d is larger than buf_pg_sz!",
4937 eq->entries);
4938 return -EINVAL;
4939 }
4940 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size,
4941 &(eq->l0_dma), GFP_KERNEL);
4942 if (!eq->bt_l0)
4943 return -ENOMEM;
4944
4945 eq->cur_eqe_ba = eq->l0_dma;
4946 eq->nxt_eqe_ba = 0;
4947
4948 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size);
4949
4950 return 0;
4951 }
4952
4953 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL);
4954 if (!eq->buf_dma)
4955 return -ENOMEM;
4956 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL);
4957 if (!eq->buf)
4958 goto err_kcalloc_buf;
4959
4960 if (mhop_num == 2) {
4961 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL);
4962 if (!eq->l1_dma)
4963 goto err_kcalloc_l1_dma;
4964
4965 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL);
4966 if (!eq->bt_l1)
4967 goto err_kcalloc_bt_l1;
4968 }
4969
4970 /* alloc L0 BT */
4971 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL);
4972 if (!eq->bt_l0)
4973 goto err_dma_alloc_l0;
4974
4975 if (mhop_num == 1) {
4976 if (ba_num > (bt_chk_sz / 8))
4977 dev_err(dev, "ba_num %d is too large for 1 hop\n",
4978 ba_num);
4979
4980 /* alloc buf */
4981 for (i = 0; i < bt_chk_sz / 8; i++) {
4982 if (eq_buf_cnt + 1 < ba_num) {
4983 size = buf_chk_sz;
4984 } else {
4985 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
4986 size = (eq->entries - eqe_alloc) * eq->eqe_size;
4987 }
6d10550c 4988 eq->buf[i] = dma_zalloc_coherent(dev, size,
a5073d60
YL		 4989 &(eq->buf_dma[i]),
4990 GFP_KERNEL);
4991 if (!eq->buf[i])
4992 goto err_dma_alloc_buf;
4993
a5073d60
YL		 4994 *(eq->bt_l0 + i) = eq->buf_dma[i];
4995
4996 eq_buf_cnt++;
4997 if (eq_buf_cnt >= ba_num)
4998 break;
4999 }
5000 eq->cur_eqe_ba = eq->buf_dma[0];
5001 eq->nxt_eqe_ba = eq->buf_dma[1];
5002
5003 } else if (mhop_num == 2) {
5004 /* alloc L1 BT and buf */
5005 for (i = 0; i < bt_chk_sz / 8; i++) {
5006 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz,
5007 &(eq->l1_dma[i]),
5008 GFP_KERNEL);
5009 if (!eq->bt_l1[i])
5010 goto err_dma_alloc_l1;
5011 *(eq->bt_l0 + i) = eq->l1_dma[i];
5012
5013 for (j = 0; j < bt_chk_sz / 8; j++) {
5014 idx = i * bt_chk_sz / 8 + j;
5015 if (eq_buf_cnt + 1 < ba_num) {
5016 size = buf_chk_sz;
5017 } else {
5018 eqe_alloc = (buf_chk_sz / eq->eqe_size)
5019 * idx;
5020 size = (eq->entries - eqe_alloc)
5021 * eq->eqe_size;
5022 }
6d10550c 5023 eq->buf[idx] = dma_zalloc_coherent(dev, size,
a5073d60
YL		 5024 &(eq->buf_dma[idx]),
5025 GFP_KERNEL);
5026 if (!eq->buf[idx])
5027 goto err_dma_alloc_buf;
5028
a5073d60
YL		 5029 *(eq->bt_l1[i] + j) = eq->buf_dma[idx];
5030
5031 eq_buf_cnt++;
5032 if (eq_buf_cnt >= ba_num) {
5033 eq_alloc_done = 1;
5034 break;
5035 }
5036 }
5037
5038 if (eq_alloc_done)
5039 break;
5040 }
5041 eq->cur_eqe_ba = eq->buf_dma[0];
5042 eq->nxt_eqe_ba = eq->buf_dma[1];
5043 }
5044
5045 eq->l0_last_num = i + 1;
5046 if (mhop_num == 2)
5047 eq->l1_last_num = j + 1;
5048
5049 return 0;
5050
5051err_dma_alloc_l1:
5052 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5053 eq->bt_l0 = NULL;
5054 eq->l0_dma = 0;
5055 for (i -= 1; i >= 0; i--) {
5056 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5057 eq->l1_dma[i]);
5058
5059 for (j = 0; j < bt_chk_sz / 8; j++) {
5060 idx = i * bt_chk_sz / 8 + j;
5061 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
5062 eq->buf_dma[idx]);
5063 }
5064 }
5065 goto err_dma_alloc_l0;
5066
5067err_dma_alloc_buf:
5068 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5069 eq->bt_l0 = NULL;
5070 eq->l0_dma = 0;
5071
5072 if (mhop_num == 1)
38759d61 5073 for (i -= 1; i >= 0; i--)
a5073d60
YL		 5074 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
5075 eq->buf_dma[i]);
5076 else if (mhop_num == 2) {
5077 record_i = i;
5078 record_j = j;
5079 for (; i >= 0; i--) {
5080 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5081 eq->l1_dma[i]);
5082
5083 for (j = 0; j < bt_chk_sz / 8; j++) {
5084 if (i == record_i && j >= record_j)
5085 break;
5086
5087 idx = i * bt_chk_sz / 8 + j;
5088 dma_free_coherent(dev, buf_chk_sz,
5089 eq->buf[idx],
5090 eq->buf_dma[idx]);
5091 }
5092 }
5093 }
5094
5095err_dma_alloc_l0:
5096 kfree(eq->bt_l1);
5097 eq->bt_l1 = NULL;
5098
5099err_kcalloc_bt_l1:
5100 kfree(eq->l1_dma);
5101 eq->l1_dma = NULL;
5102
5103err_kcalloc_l1_dma:
5104 kfree(eq->buf);
5105 eq->buf = NULL;
5106
5107err_kcalloc_buf:
5108 kfree(eq->buf_dma);
5109 eq->buf_dma = NULL;
5110
5111 return -ENOMEM;
5112}
5113
5114static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5115 struct hns_roce_eq *eq,
5116 unsigned int eq_cmd)
5117{
5118 struct device *dev = hr_dev->dev;
5119 struct hns_roce_cmd_mailbox *mailbox;
5120 u32 buf_chk_sz = 0;
5121 int ret;
5122
5123 /* Allocate mailbox memory */
5124 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5125 if (IS_ERR(mailbox))
5126 return PTR_ERR(mailbox);
5127
5128 if (!hr_dev->caps.eqe_hop_num) {
5129 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5130
5131 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list),
5132 GFP_KERNEL);
5133 if (!eq->buf_list) {
5134 ret = -ENOMEM;
5135 goto free_cmd_mbox;
5136 }
5137
6d10550c 5138 eq->buf_list->buf = dma_zalloc_coherent(dev, buf_chk_sz,
a5073d60
YL		 5139 &(eq->buf_list->map),
5140 GFP_KERNEL);
5141 if (!eq->buf_list->buf) {
5142 ret = -ENOMEM;
5143 goto err_alloc_buf;
5144 }
5145
a5073d60
YL		 5146 } else {
5147 ret = hns_roce_mhop_alloc_eq(hr_dev, eq);
5148 if (ret) {
5149 ret = -ENOMEM;
5150 goto free_cmd_mbox;
5151 }
5152 }
5153
5154 hns_roce_config_eqc(hr_dev, eq, mailbox->buf);
5155
5156 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5157 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5158 if (ret) {
ab178849 5159 dev_err(dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5160 goto err_cmd_mbox;
5161 }
5162
5163 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5164
5165 return 0;
5166
5167err_cmd_mbox:
5168 if (!hr_dev->caps.eqe_hop_num)
5169 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf,
5170 eq->buf_list->map);
5171 else {
5172 hns_roce_mhop_free_eq(hr_dev, eq);
5173 goto free_cmd_mbox;
5174 }
5175
5176err_alloc_buf:
5177 kfree(eq->buf_list);
5178
5179free_cmd_mbox:
5180 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5181
5182 return ret;
5183}
5184
5185static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5186{
5187 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5188 struct device *dev = hr_dev->dev;
5189 struct hns_roce_eq *eq;
5190 unsigned int eq_cmd;
5191 int irq_num;
5192 int eq_num;
5193 int other_num;
5194 int comp_num;
5195 int aeq_num;
5196 int i, j, k;
5197 int ret;
5198
5199 other_num = hr_dev->caps.num_other_vectors;
5200 comp_num = hr_dev->caps.num_comp_vectors;
5201 aeq_num = hr_dev->caps.num_aeq_vectors;
5202
5203 eq_num = comp_num + aeq_num;
5204 irq_num = eq_num + other_num;
5205
5206 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5207 if (!eq_table->eq)
5208 return -ENOMEM;
5209
5210 for (i = 0; i < irq_num; i++) {
5211 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5212 GFP_KERNEL);
5213 if (!hr_dev->irq_names[i]) {
5214 ret = -ENOMEM;
5215 goto err_failed_kzalloc;
5216 }
5217 }
5218
5219 /* create eq */
5220 for (j = 0; j < eq_num; j++) {
5221 eq = &eq_table->eq[j];
5222 eq->hr_dev = hr_dev;
5223 eq->eqn = j;
5224 if (j < comp_num) {
5225 /* CEQ */
5226 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5227 eq->type_flag = HNS_ROCE_CEQ;
5228 eq->entries = hr_dev->caps.ceqe_depth;
5229 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
5230 eq->irq = hr_dev->irq[j + other_num + aeq_num];
5231 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5232 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5233 } else {
5234 /* AEQ */
5235 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5236 eq->type_flag = HNS_ROCE_AEQ;
5237 eq->entries = hr_dev->caps.aeqe_depth;
5238 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
5239 eq->irq = hr_dev->irq[j - comp_num + other_num];
5240 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5241 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5242 }
5243
5244 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5245 if (ret) {
5246 dev_err(dev, "eq create failed.\n");
5247 goto err_create_eq_fail;
5248 }
5249 }
5250
5251 /* enable irq */
5252 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5253
5254 /* irq contains: abnormal + AEQ + CEQ*/
5255 for (k = 0; k < irq_num; k++)
5256 if (k < other_num)
5257 snprintf((char *)hr_dev->irq_names[k],
5258 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k);
5259 else if (k < (other_num + aeq_num))
5260 snprintf((char *)hr_dev->irq_names[k],
5261 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d",
5262 k - other_num);
5263 else
5264 snprintf((char *)hr_dev->irq_names[k],
5265 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d",
5266 k - other_num - aeq_num);
5267
5268 for (k = 0; k < irq_num; k++) {
5269 if (k < other_num)
5270 ret = request_irq(hr_dev->irq[k],
5271 hns_roce_v2_msix_interrupt_abn,
5272 0, hr_dev->irq_names[k], hr_dev);
5273
5274 else if (k < (other_num + comp_num))
5275 ret = request_irq(eq_table->eq[k - other_num].irq,
5276 hns_roce_v2_msix_interrupt_eq,
5277 0, hr_dev->irq_names[k + aeq_num],
5278 &eq_table->eq[k - other_num]);
5279 else
5280 ret = request_irq(eq_table->eq[k - other_num].irq,
5281 hns_roce_v2_msix_interrupt_eq,
5282 0, hr_dev->irq_names[k - comp_num],
5283 &eq_table->eq[k - other_num]);
5284 if (ret) {
5285 dev_err(dev, "Request irq error!\n");
5286 goto err_request_irq_fail;
5287 }
5288 }
5289
0425e3e6
YL		 5290 hr_dev->irq_workq =
5291 create_singlethread_workqueue("hns_roce_irq_workqueue");
5292 if (!hr_dev->irq_workq) {
5293 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5294 ret = -ENOMEM;
0425e3e6
YL		 5295 goto err_request_irq_fail;
5296 }
5297
a5073d60
YL		 5298 return 0;
5299
5300err_request_irq_fail:
5301 for (k -= 1; k >= 0; k--)
5302 if (k < other_num)
5303 free_irq(hr_dev->irq[k], hr_dev);
5304 else
5305 free_irq(eq_table->eq[k - other_num].irq,
5306 &eq_table->eq[k - other_num]);
5307
5308err_create_eq_fail:
5309 for (j -= 1; j >= 0; j--)
5310 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]);
5311
5312err_failed_kzalloc:
5313 for (i -= 1; i >= 0; i--)
5314 kfree(hr_dev->irq_names[i]);
5315 kfree(eq_table->eq);
5316
5317 return ret;
5318}
5319
5320static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5321{
5322 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5323 int irq_num;
5324 int eq_num;
5325 int i;
5326
5327 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5328 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5329
5330 /* Disable irq */
5331 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5332
5333 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5334 free_irq(hr_dev->irq[i], hr_dev);
5335
5336 for (i = 0; i < eq_num; i++) {
5337 hns_roce_v2_destroy_eqc(hr_dev, i);
5338
5339 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]);
5340
5341 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]);
5342 }
5343
5344 for (i = 0; i < irq_num; i++)
5345 kfree(hr_dev->irq_names[i]);
5346
5347 kfree(eq_table->eq);
0425e3e6
YL		 5348
5349 flush_workqueue(hr_dev->irq_workq);
5350 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5351}
5352
a04ff739
WHX		 5353static const struct hns_roce_hw hns_roce_hw_v2 = {
5354 .cmq_init = hns_roce_v2_cmq_init,
5355 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5356 .hw_profile = hns_roce_v2_profile,
6b63597d 5357 .hw_init = hns_roce_v2_init,
5358 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5359 .post_mbox = hns_roce_v2_post_mbox,
5360 .chk_mbox = hns_roce_v2_chk_mbox,
7afddafa
WHX		 5361 .set_gid = hns_roce_v2_set_gid,
5362 .set_mac = hns_roce_v2_set_mac,
3958cc56 5363 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5364 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 5365 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 5366 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 5367 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5368 .set_hem = hns_roce_v2_set_hem,
5369 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5370 .modify_qp = hns_roce_v2_modify_qp,
5371 .query_qp = hns_roce_v2_query_qp,
5372 .destroy_qp = hns_roce_v2_destroy_qp,
b156269d 5373 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5374 .post_send = hns_roce_v2_post_send,
5375 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5376 .req_notify_cq = hns_roce_v2_req_notify_cq,
5377 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5378 .init_eq = hns_roce_v2_init_eq_table,
5379 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
a04ff739 5380};
dd74282d
WHX		 5381
5382static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5383 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5384 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 5385 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
5386 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 5387 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
5388 /* required last entry */
5389 {0, }
5390};
5391
f97a62c3 5392MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
5393
dd74282d
WHX		 5394static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
5395 struct hnae3_handle *handle)
5396{
5397 const struct pci_device_id *id;
a5073d60 5398 int i;
dd74282d
WHX		 5399
5400 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
5401 if (!id) {
5402 dev_err(hr_dev->dev, "device is not compatible!\n");
5403 return -ENXIO;
5404 }
5405
5406 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 5407 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
5408 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 5409
5410 /* Get info from NIC driver. */
5411 hr_dev->reg_base = handle->rinfo.roce_io_base;
5412 hr_dev->caps.num_ports = 1;
5413 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
5414 hr_dev->iboe.phy_port[0] = 0;
5415
d4994d2f 5416 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
5417 hr_dev->iboe.netdevs[0]->dev_addr);
5418
a5073d60
YL		 5419 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
5420 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
5421 i + handle->rinfo.base_vector);
5422
dd74282d 5423 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 5424 hr_dev->cmd_mod = 1;
dd74282d
WHX		 5425 hr_dev->loop_idc = 0;
5426
5427 return 0;
5428}
5429
5430static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
5431{
5432 struct hns_roce_dev *hr_dev;
5433 int ret;
5434
5435 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
5436 if (!hr_dev)
5437 return -ENOMEM;
5438
a04ff739
WHX		 5439 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
5440 if (!hr_dev->priv) {
5441 ret = -ENOMEM;
5442 goto error_failed_kzalloc;
5443 }
5444
dd74282d
WHX		 5445 hr_dev->pci_dev = handle->pdev;
5446 hr_dev->dev = &handle->pdev->dev;
5447 handle->priv = hr_dev;
5448
5449 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
5450 if (ret) {
5451 dev_err(hr_dev->dev, "Get Configuration failed!\n");
5452 goto error_failed_get_cfg;
5453 }
5454
5455 ret = hns_roce_init(hr_dev);
5456 if (ret) {
5457 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
5458 goto error_failed_get_cfg;
5459 }
5460
5461 return 0;
5462
5463error_failed_get_cfg:
a04ff739
WHX		 5464 kfree(hr_dev->priv);
5465
5466error_failed_kzalloc:
dd74282d
WHX		 5467 ib_dealloc_device(&hr_dev->ib_dev);
5468
5469 return ret;
5470}
5471
5472static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
5473 bool reset)
5474{
5475 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5476
cb7a94c9
WHX		 5477 if (!hr_dev)
5478 return;
5479
dd74282d 5480 hns_roce_exit(hr_dev);
a04ff739 5481 kfree(hr_dev->priv);
dd74282d
WHX		 5482 ib_dealloc_device(&hr_dev->ib_dev);
5483}
5484
cb7a94c9
WHX		 5485static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
5486{
5487 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
5488 struct ib_event event;
5489
5490 if (!hr_dev) {
5491 dev_err(&handle->pdev->dev,
5492 "Input parameter handle->priv is NULL!\n");
5493 return -EINVAL;
5494 }
5495
5496 hr_dev->active = false;
5497 hr_dev->is_reset = true;
5498
5499 event.event = IB_EVENT_DEVICE_FATAL;
5500 event.device = &hr_dev->ib_dev;
5501 event.element.port_num = 1;
5502 ib_dispatch_event(&event);
5503
5504 return 0;
5505}
5506
5507static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
5508{
5509 int ret;
5510
5511 ret = hns_roce_hw_v2_init_instance(handle);
5512 if (ret) {
5513 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
5514 * callback function, RoCE Engine reinitialize. If RoCE reinit
5515 * failed, we should inform NIC driver.
5516 */
5517 handle->priv = NULL;
5518 dev_err(&handle->pdev->dev,
5519 "In reset process RoCE reinit failed %d.\n", ret);
5520 }
5521
5522 return ret;
5523}
5524
5525static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
5526{
5527 msleep(100);
5528 hns_roce_hw_v2_uninit_instance(handle, false);
5529 return 0;
5530}
5531
5532static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
5533 enum hnae3_reset_notify_type type)
5534{
5535 int ret = 0;
5536
5537 switch (type) {
5538 case HNAE3_DOWN_CLIENT:
5539 ret = hns_roce_hw_v2_reset_notify_down(handle);
5540 break;
5541 case HNAE3_INIT_CLIENT:
5542 ret = hns_roce_hw_v2_reset_notify_init(handle);
5543 break;
5544 case HNAE3_UNINIT_CLIENT:
5545 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
5546 break;
5547 default:
5548 break;
5549 }
5550
5551 return ret;
5552}
5553
dd74282d
WHX		 5554static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
5555 .init_instance = hns_roce_hw_v2_init_instance,
5556 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 5557 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 5558};
5559
5560static struct hnae3_client hns_roce_hw_v2_client = {
5561 .name = "hns_roce_hw_v2",
5562 .type = HNAE3_CLIENT_ROCE,
5563 .ops = &hns_roce_hw_v2_ops,
5564};
5565
5566static int __init hns_roce_hw_v2_init(void)
5567{
5568 return hnae3_register_client(&hns_roce_hw_v2_client);
5569}
5570
5571static void __exit hns_roce_hw_v2_exit(void)
5572{
5573 hnae3_unregister_client(&hns_roce_hw_v2_client);
5574}
5575
5576module_init(hns_roce_hw_v2_init);
5577module_exit(hns_roce_hw_v2_exit);
5578
5579MODULE_LICENSE("Dual BSD/GPL");
5580MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5581MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5582MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
5583MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)