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dd74282d WHX |
1 | /* |
2 | * Copyright (c) 2016-2017 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/acpi.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/kernel.h> | |
0b25c9cc | 37 | #include <linux/types.h> |
d4994d2f | 38 | #include <net/addrconf.h> |
610b8967 | 39 | #include <rdma/ib_addr.h> |
a70c0739 | 40 | #include <rdma/ib_cache.h> |
dd74282d | 41 | #include <rdma/ib_umem.h> |
bdeacabd | 42 | #include <rdma/uverbs_ioctl.h> |
dd74282d WHX |
43 | |
44 | #include "hnae3.h" | |
45 | #include "hns_roce_common.h" | |
46 | #include "hns_roce_device.h" | |
47 | #include "hns_roce_cmd.h" | |
48 | #include "hns_roce_hem.h" | |
a04ff739 | 49 | #include "hns_roce_hw_v2.h" |
dd74282d | 50 | |
2d407888 WHX |
51 | static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, |
52 | struct ib_sge *sg) | |
53 | { | |
54 | dseg->lkey = cpu_to_le32(sg->lkey); | |
55 | dseg->addr = cpu_to_le64(sg->addr); | |
56 | dseg->len = cpu_to_le32(sg->length); | |
57 | } | |
58 | ||
e363f7de XW |
59 | /* |
60 | * mapped-value = 1 + real-value | |
61 | * The hns wr opcode real value is start from 0, In order to distinguish between | |
62 | * initialized and uninitialized map values, we plus 1 to the actual value when | |
63 | * defining the mapping, so that the validity can be identified by checking the | |
64 | * mapped value is greater than 0. | |
65 | */ | |
66 | #define HR_OPC_MAP(ib_key, hr_key) \ | |
67 | [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key | |
68 | ||
69 | static const u32 hns_roce_op_code[] = { | |
70 | HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE), | |
71 | HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM), | |
72 | HR_OPC_MAP(SEND, SEND), | |
73 | HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM), | |
74 | HR_OPC_MAP(RDMA_READ, RDMA_READ), | |
75 | HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP), | |
76 | HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD), | |
77 | HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV), | |
78 | HR_OPC_MAP(LOCAL_INV, LOCAL_INV), | |
79 | HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP), | |
80 | HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD), | |
81 | HR_OPC_MAP(REG_MR, FAST_REG_PMR), | |
82 | }; | |
83 | ||
84 | static u32 to_hr_opcode(u32 ib_opcode) | |
85 | { | |
86 | if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code)) | |
87 | return HNS_ROCE_V2_WQE_OP_MASK; | |
88 | ||
89 | return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 : | |
90 | HNS_ROCE_V2_WQE_OP_MASK; | |
91 | } | |
92 | ||
68a997c5 | 93 | static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, |
00a59d30 | 94 | void *wqe, const struct ib_reg_wr *wr) |
68a997c5 YL |
95 | { |
96 | struct hns_roce_mr *mr = to_hr_mr(wr->mr); | |
00a59d30 | 97 | struct hns_roce_wqe_frmr_seg *fseg = wqe; |
68a997c5 YL |
98 | |
99 | /* use ib_access_flags */ | |
60262b10 | 100 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S, |
68a997c5 | 101 | wr->access & IB_ACCESS_MW_BIND ? 1 : 0); |
60262b10 | 102 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S, |
68a997c5 | 103 | wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); |
60262b10 | 104 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S, |
68a997c5 | 105 | wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0); |
60262b10 | 106 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S, |
68a997c5 | 107 | wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0); |
60262b10 | 108 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S, |
68a997c5 YL |
109 | wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0); |
110 | ||
111 | /* Data structure reuse may lead to confusion */ | |
112 | rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff); | |
113 | rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32); | |
114 | ||
115 | rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff); | |
116 | rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32); | |
117 | rc_sq_wqe->rkey = cpu_to_le32(wr->key); | |
118 | rc_sq_wqe->va = cpu_to_le64(wr->mr->iova); | |
119 | ||
120 | fseg->pbl_size = cpu_to_le32(mr->pbl_size); | |
121 | roce_set_field(fseg->mode_buf_pg_sz, | |
122 | V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M, | |
123 | V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S, | |
124 | mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET); | |
125 | roce_set_bit(fseg->mode_buf_pg_sz, | |
126 | V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0); | |
127 | } | |
128 | ||
00a59d30 XW |
129 | static void set_atomic_seg(const struct ib_send_wr *wr, void *wqe, |
130 | struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, | |
131 | int valid_num_sge) | |
384f8818 | 132 | { |
00a59d30 XW |
133 | struct hns_roce_wqe_atomic_seg *aseg; |
134 | ||
135 | set_data_seg_v2(wqe, wr->sg_list); | |
136 | aseg = wqe + sizeof(struct hns_roce_v2_wqe_data_seg); | |
137 | ||
138 | if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { | |
139 | aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap); | |
140 | aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add); | |
384f8818 | 141 | } else { |
00a59d30 XW |
142 | aseg->fetchadd_swap_data = |
143 | cpu_to_le64(atomic_wr(wr)->compare_add); | |
384f8818 LO |
144 | aseg->cmp_data = 0; |
145 | } | |
00a59d30 XW |
146 | |
147 | roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, | |
148 | V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); | |
384f8818 LO |
149 | } |
150 | ||
f696bf6d | 151 | static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr, |
468d020e | 152 | unsigned int *sge_ind, int valid_num_sge) |
0b25c9cc WHX |
153 | { |
154 | struct hns_roce_v2_wqe_data_seg *dseg; | |
155 | struct ib_sge *sg; | |
156 | int num_in_wqe = 0; | |
157 | int extend_sge_num; | |
158 | int fi_sge_num; | |
159 | int se_sge_num; | |
160 | int shift; | |
161 | int i; | |
162 | ||
163 | if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) | |
164 | num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; | |
468d020e | 165 | extend_sge_num = valid_num_sge - num_in_wqe; |
0b25c9cc | 166 | sg = wr->sg_list + num_in_wqe; |
d563099e | 167 | shift = qp->mtr.hem_cfg.buf_pg_shift; |
0b25c9cc WHX |
168 | |
169 | /* | |
170 | * Check whether wr->num_sge sges are in the same page. If not, we | |
171 | * should calculate how many sges in the first page and the second | |
172 | * page. | |
173 | */ | |
6c6e3921 | 174 | dseg = hns_roce_get_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1)); |
0b25c9cc WHX |
175 | fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) - |
176 | (uintptr_t)dseg) / | |
177 | sizeof(struct hns_roce_v2_wqe_data_seg); | |
178 | if (extend_sge_num > fi_sge_num) { | |
179 | se_sge_num = extend_sge_num - fi_sge_num; | |
180 | for (i = 0; i < fi_sge_num; i++) { | |
181 | set_data_seg_v2(dseg++, sg + i); | |
182 | (*sge_ind)++; | |
183 | } | |
6c6e3921 | 184 | dseg = hns_roce_get_extend_sge(qp, |
0b25c9cc WHX |
185 | (*sge_ind) & (qp->sge.sge_cnt - 1)); |
186 | for (i = 0; i < se_sge_num; i++) { | |
187 | set_data_seg_v2(dseg++, sg + fi_sge_num + i); | |
188 | (*sge_ind)++; | |
189 | } | |
190 | } else { | |
191 | for (i = 0; i < extend_sge_num; i++) { | |
192 | set_data_seg_v2(dseg++, sg + i); | |
193 | (*sge_ind)++; | |
194 | } | |
195 | } | |
196 | } | |
197 | ||
f696bf6d | 198 | static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
7bdee415 | 199 | struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, |
200 | void *wqe, unsigned int *sge_ind, | |
00a59d30 | 201 | int valid_num_sge) |
7bdee415 | 202 | { |
203 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
204 | struct hns_roce_v2_wqe_data_seg *dseg = wqe; | |
00a59d30 | 205 | struct ib_device *ibdev = &hr_dev->ib_dev; |
7bdee415 | 206 | struct hns_roce_qp *qp = to_hr_qp(ibqp); |
468d020e | 207 | int j = 0; |
7bdee415 | 208 | int i; |
209 | ||
468d020e | 210 | if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) { |
8b9b8d14 | 211 | if (le32_to_cpu(rc_sq_wqe->msg_len) > |
212 | hr_dev->caps.max_sq_inline) { | |
00a59d30 XW |
213 | ibdev_err(ibdev, "inline len(1-%d)=%d, illegal", |
214 | rc_sq_wqe->msg_len, | |
215 | hr_dev->caps.max_sq_inline); | |
7bdee415 | 216 | return -EINVAL; |
217 | } | |
218 | ||
328d405b | 219 | if (wr->opcode == IB_WR_RDMA_READ) { |
00a59d30 | 220 | ibdev_err(ibdev, "Not support inline data!\n"); |
328d405b | 221 | return -EINVAL; |
222 | } | |
223 | ||
7bdee415 | 224 | for (i = 0; i < wr->num_sge; i++) { |
225 | memcpy(wqe, ((void *)wr->sg_list[i].addr), | |
226 | wr->sg_list[i].length); | |
227 | wqe += wr->sg_list[i].length; | |
228 | } | |
229 | ||
230 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S, | |
231 | 1); | |
232 | } else { | |
468d020e | 233 | if (valid_num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) { |
7bdee415 | 234 | for (i = 0; i < wr->num_sge; i++) { |
235 | if (likely(wr->sg_list[i].length)) { | |
236 | set_data_seg_v2(dseg, wr->sg_list + i); | |
237 | dseg++; | |
238 | } | |
239 | } | |
240 | } else { | |
241 | roce_set_field(rc_sq_wqe->byte_20, | |
242 | V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, | |
243 | V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, | |
244 | (*sge_ind) & (qp->sge.sge_cnt - 1)); | |
245 | ||
468d020e LO |
246 | for (i = 0; i < wr->num_sge && |
247 | j < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) { | |
7bdee415 | 248 | if (likely(wr->sg_list[i].length)) { |
249 | set_data_seg_v2(dseg, wr->sg_list + i); | |
250 | dseg++; | |
468d020e | 251 | j++; |
7bdee415 | 252 | } |
253 | } | |
254 | ||
468d020e | 255 | set_extend_sge(qp, wr, sge_ind, valid_num_sge); |
7bdee415 | 256 | } |
257 | ||
258 | roce_set_field(rc_sq_wqe->byte_16, | |
259 | V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M, | |
468d020e | 260 | V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); |
7bdee415 | 261 | } |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
626903e9 XW |
266 | static int check_send_valid(struct hns_roce_dev *hr_dev, |
267 | struct hns_roce_qp *hr_qp) | |
268 | { | |
ae1c6148 | 269 | struct ib_device *ibdev = &hr_dev->ib_dev; |
626903e9 | 270 | struct ib_qp *ibqp = &hr_qp->ibqp; |
626903e9 XW |
271 | |
272 | if (unlikely(ibqp->qp_type != IB_QPT_RC && | |
273 | ibqp->qp_type != IB_QPT_GSI && | |
274 | ibqp->qp_type != IB_QPT_UD)) { | |
ae1c6148 LO |
275 | ibdev_err(ibdev, "Not supported QP(0x%x)type!\n", |
276 | ibqp->qp_type); | |
626903e9 XW |
277 | return -EOPNOTSUPP; |
278 | } else if (unlikely(hr_qp->state == IB_QPS_RESET || | |
279 | hr_qp->state == IB_QPS_INIT || | |
280 | hr_qp->state == IB_QPS_RTR)) { | |
ae1c6148 LO |
281 | ibdev_err(ibdev, "failed to post WQE, QP state %d!\n", |
282 | hr_qp->state); | |
626903e9 XW |
283 | return -EINVAL; |
284 | } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) { | |
ae1c6148 LO |
285 | ibdev_err(ibdev, "failed to post WQE, dev state %d!\n", |
286 | hr_dev->state); | |
626903e9 XW |
287 | return -EIO; |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
d6a3627e XW |
293 | static inline int calc_wr_sge_num(const struct ib_send_wr *wr, u32 *sge_len) |
294 | { | |
295 | int valid_num = 0; | |
296 | u32 len = 0; | |
297 | int i; | |
298 | ||
299 | for (i = 0; i < wr->num_sge; i++) { | |
300 | if (likely(wr->sg_list[i].length)) { | |
301 | len += wr->sg_list[i].length; | |
302 | valid_num++; | |
303 | } | |
304 | } | |
305 | ||
306 | *sge_len = len; | |
307 | return valid_num; | |
308 | } | |
309 | ||
310 | static inline int set_ud_wqe(struct hns_roce_qp *qp, | |
311 | const struct ib_send_wr *wr, | |
312 | void *wqe, unsigned int *sge_idx, | |
313 | unsigned int owner_bit) | |
314 | { | |
315 | struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); | |
316 | struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah); | |
317 | struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe; | |
318 | unsigned int curr_idx = *sge_idx; | |
319 | int valid_num_sge; | |
320 | u32 msg_len = 0; | |
321 | bool loopback; | |
322 | u8 *smac; | |
323 | ||
324 | valid_num_sge = calc_wr_sge_num(wr, &msg_len); | |
325 | memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe)); | |
326 | ||
327 | roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M, | |
328 | V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]); | |
329 | roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M, | |
330 | V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]); | |
331 | roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M, | |
332 | V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]); | |
333 | roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M, | |
334 | V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]); | |
335 | roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M, | |
336 | V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]); | |
337 | roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M, | |
338 | V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]); | |
339 | ||
340 | /* MAC loopback */ | |
341 | smac = (u8 *)hr_dev->dev_addr[qp->port]; | |
342 | loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0; | |
343 | ||
344 | roce_set_bit(ud_sq_wqe->byte_40, | |
345 | V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback); | |
346 | ||
347 | roce_set_field(ud_sq_wqe->byte_4, | |
348 | V2_UD_SEND_WQE_BYTE_4_OPCODE_M, | |
349 | V2_UD_SEND_WQE_BYTE_4_OPCODE_S, | |
350 | HNS_ROCE_V2_WQE_OP_SEND); | |
351 | ||
352 | ud_sq_wqe->msg_len = cpu_to_le32(msg_len); | |
353 | ||
354 | switch (wr->opcode) { | |
355 | case IB_WR_SEND_WITH_IMM: | |
356 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
357 | ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); | |
358 | break; | |
359 | default: | |
360 | ud_sq_wqe->immtdata = 0; | |
361 | break; | |
362 | } | |
363 | ||
364 | /* Set sig attr */ | |
365 | roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S, | |
366 | (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); | |
367 | ||
368 | /* Set se attr */ | |
369 | roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S, | |
370 | (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); | |
371 | ||
372 | roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S, | |
373 | owner_bit); | |
374 | ||
375 | roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M, | |
376 | V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn); | |
377 | ||
378 | roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M, | |
379 | V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge); | |
380 | ||
381 | roce_set_field(ud_sq_wqe->byte_20, | |
382 | V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M, | |
383 | V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S, | |
384 | curr_idx & (qp->sge.sge_cnt - 1)); | |
385 | ||
386 | roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M, | |
387 | V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0); | |
388 | ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ? | |
389 | qp->qkey : ud_wr(wr)->remote_qkey); | |
390 | roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M, | |
391 | V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn); | |
392 | ||
393 | roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M, | |
394 | V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id); | |
395 | roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M, | |
396 | V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit); | |
397 | roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M, | |
398 | V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass); | |
399 | roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M, | |
400 | V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel); | |
401 | roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M, | |
402 | V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl); | |
403 | roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M, | |
404 | V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port); | |
405 | ||
406 | roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S, | |
407 | ah->av.vlan_en ? 1 : 0); | |
408 | roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M, | |
409 | V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index); | |
410 | ||
411 | memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2); | |
412 | ||
413 | set_extend_sge(qp, wr, &curr_idx, valid_num_sge); | |
414 | ||
415 | *sge_idx = curr_idx; | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | static inline int set_rc_wqe(struct hns_roce_qp *qp, | |
421 | const struct ib_send_wr *wr, | |
422 | void *wqe, unsigned int *sge_idx, | |
423 | unsigned int owner_bit) | |
424 | { | |
425 | struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; | |
426 | unsigned int curr_idx = *sge_idx; | |
427 | int valid_num_sge; | |
428 | u32 msg_len = 0; | |
429 | int ret = 0; | |
430 | ||
431 | valid_num_sge = calc_wr_sge_num(wr, &msg_len); | |
432 | memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe)); | |
433 | ||
434 | rc_sq_wqe->msg_len = cpu_to_le32(msg_len); | |
435 | ||
436 | switch (wr->opcode) { | |
437 | case IB_WR_SEND_WITH_IMM: | |
438 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
439 | rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data)); | |
440 | break; | |
441 | case IB_WR_SEND_WITH_INV: | |
442 | rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); | |
443 | break; | |
444 | default: | |
445 | rc_sq_wqe->immtdata = 0; | |
446 | break; | |
447 | } | |
448 | ||
449 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S, | |
450 | (wr->send_flags & IB_SEND_FENCE) ? 1 : 0); | |
451 | ||
452 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S, | |
453 | (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0); | |
454 | ||
455 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S, | |
456 | (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0); | |
457 | ||
458 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S, | |
459 | owner_bit); | |
460 | ||
461 | wqe += sizeof(struct hns_roce_v2_rc_send_wqe); | |
462 | switch (wr->opcode) { | |
463 | case IB_WR_RDMA_READ: | |
464 | case IB_WR_RDMA_WRITE: | |
465 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
466 | rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey); | |
467 | rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr); | |
468 | break; | |
469 | case IB_WR_LOCAL_INV: | |
470 | roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1); | |
471 | rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey); | |
472 | break; | |
473 | case IB_WR_REG_MR: | |
474 | set_frmr_seg(rc_sq_wqe, wqe, reg_wr(wr)); | |
475 | break; | |
476 | case IB_WR_ATOMIC_CMP_AND_SWP: | |
477 | case IB_WR_ATOMIC_FETCH_AND_ADD: | |
478 | rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey); | |
479 | rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr); | |
480 | break; | |
481 | default: | |
482 | break; | |
483 | } | |
484 | ||
485 | roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M, | |
486 | V2_RC_SEND_WQE_BYTE_4_OPCODE_S, | |
487 | to_hr_opcode(wr->opcode)); | |
488 | ||
489 | if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP || | |
490 | wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) | |
491 | set_atomic_seg(wr, wqe, rc_sq_wqe, valid_num_sge); | |
492 | else if (wr->opcode != IB_WR_REG_MR) | |
493 | ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe, | |
494 | wqe, &curr_idx, valid_num_sge); | |
495 | ||
496 | *sge_idx = curr_idx; | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
75c994e6 YL |
501 | static inline void update_sq_db(struct hns_roce_dev *hr_dev, |
502 | struct hns_roce_qp *qp) | |
503 | { | |
504 | /* | |
505 | * Hip08 hardware cannot flush the WQEs in SQ if the QP state | |
506 | * gets into errored mode. Hence, as a workaround to this | |
507 | * hardware limitation, driver needs to assist in flushing. But | |
508 | * the flushing operation uses mailbox to convey the QP state to | |
509 | * the hardware and which can sleep due to the mutex protection | |
510 | * around the mailbox calls. Hence, use the deferred flush for | |
511 | * now. | |
512 | */ | |
513 | if (qp->state == IB_QPS_ERR) { | |
514 | if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) | |
515 | init_flush_work(hr_dev, qp); | |
516 | } else { | |
517 | struct hns_roce_v2_db sq_db = {}; | |
518 | ||
519 | roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M, | |
520 | V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); | |
521 | roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, | |
522 | V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); | |
523 | roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, | |
524 | V2_DB_PARAMETER_IDX_S, | |
525 | qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)); | |
526 | roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, | |
527 | V2_DB_PARAMETER_SL_S, qp->sl); | |
528 | ||
529 | hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l); | |
530 | } | |
531 | } | |
532 | ||
d34ac5cd BVA |
533 | static int hns_roce_v2_post_send(struct ib_qp *ibqp, |
534 | const struct ib_send_wr *wr, | |
535 | const struct ib_send_wr **bad_wr) | |
2d407888 WHX |
536 | { |
537 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
d6a3627e | 538 | struct ib_device *ibdev = &hr_dev->ib_dev; |
2d407888 | 539 | struct hns_roce_qp *qp = to_hr_qp(ibqp); |
d6a3627e | 540 | unsigned long flags = 0; |
e8d18533 | 541 | unsigned int owner_bit; |
47688202 YL |
542 | unsigned int sge_idx; |
543 | unsigned int wqe_idx; | |
2d407888 | 544 | void *wqe = NULL; |
2d407888 | 545 | int nreq; |
626903e9 | 546 | int ret; |
2d407888 | 547 | |
626903e9 | 548 | spin_lock_irqsave(&qp->sq.lock, flags); |
2d407888 | 549 | |
626903e9 XW |
550 | ret = check_send_valid(hr_dev, qp); |
551 | if (ret) { | |
2d407888 | 552 | *bad_wr = wr; |
626903e9 XW |
553 | nreq = 0; |
554 | goto out; | |
2d407888 WHX |
555 | } |
556 | ||
47688202 | 557 | sge_idx = qp->next_sge; |
2d407888 WHX |
558 | |
559 | for (nreq = 0; wr; ++nreq, wr = wr->next) { | |
560 | if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { | |
561 | ret = -ENOMEM; | |
562 | *bad_wr = wr; | |
563 | goto out; | |
564 | } | |
565 | ||
47688202 YL |
566 | wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1); |
567 | ||
2d407888 | 568 | if (unlikely(wr->num_sge > qp->sq.max_gs)) { |
d6a3627e XW |
569 | ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n", |
570 | wr->num_sge, qp->sq.max_gs); | |
2d407888 WHX |
571 | ret = -EINVAL; |
572 | *bad_wr = wr; | |
573 | goto out; | |
574 | } | |
575 | ||
6c6e3921 | 576 | wqe = hns_roce_get_send_wqe(qp, wqe_idx); |
47688202 | 577 | qp->sq.wrid[wqe_idx] = wr->wr_id; |
634f6390 | 578 | owner_bit = |
579 | ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1); | |
468d020e | 580 | |
7bdee415 | 581 | /* Corresponding to the QP type, wqe process separately */ |
d6a3627e XW |
582 | if (ibqp->qp_type == IB_QPT_GSI) |
583 | ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit); | |
584 | else if (ibqp->qp_type == IB_QPT_RC) | |
585 | ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit); | |
d6a3627e XW |
586 | |
587 | if (ret) { | |
588 | *bad_wr = wr; | |
589 | goto out; | |
590 | } | |
2d407888 WHX |
591 | } |
592 | ||
593 | out: | |
594 | if (likely(nreq)) { | |
595 | qp->sq.head += nreq; | |
75c994e6 | 596 | qp->next_sge = sge_idx; |
2d407888 WHX |
597 | /* Memory barrier */ |
598 | wmb(); | |
75c994e6 | 599 | update_sq_db(hr_dev, qp); |
2d407888 WHX |
600 | } |
601 | ||
602 | spin_unlock_irqrestore(&qp->sq.lock, flags); | |
603 | ||
604 | return ret; | |
605 | } | |
606 | ||
626903e9 XW |
607 | static int check_recv_valid(struct hns_roce_dev *hr_dev, |
608 | struct hns_roce_qp *hr_qp) | |
609 | { | |
610 | if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) | |
611 | return -EIO; | |
612 | else if (hr_qp->state == IB_QPS_RESET) | |
613 | return -EINVAL; | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
d34ac5cd BVA |
618 | static int hns_roce_v2_post_recv(struct ib_qp *ibqp, |
619 | const struct ib_recv_wr *wr, | |
620 | const struct ib_recv_wr **bad_wr) | |
2d407888 WHX |
621 | { |
622 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
623 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
ae1c6148 | 624 | struct ib_device *ibdev = &hr_dev->ib_dev; |
2d407888 | 625 | struct hns_roce_v2_wqe_data_seg *dseg; |
0009c2db | 626 | struct hns_roce_rinl_sge *sge_list; |
2d407888 WHX |
627 | unsigned long flags; |
628 | void *wqe = NULL; | |
47688202 | 629 | u32 wqe_idx; |
2d407888 | 630 | int nreq; |
626903e9 | 631 | int ret; |
2d407888 WHX |
632 | int i; |
633 | ||
634 | spin_lock_irqsave(&hr_qp->rq.lock, flags); | |
2d407888 | 635 | |
626903e9 XW |
636 | ret = check_recv_valid(hr_dev, hr_qp); |
637 | if (ret) { | |
2d407888 | 638 | *bad_wr = wr; |
626903e9 XW |
639 | nreq = 0; |
640 | goto out; | |
2d407888 WHX |
641 | } |
642 | ||
643 | for (nreq = 0; wr; ++nreq, wr = wr->next) { | |
644 | if (hns_roce_wq_overflow(&hr_qp->rq, nreq, | |
645 | hr_qp->ibqp.recv_cq)) { | |
646 | ret = -ENOMEM; | |
647 | *bad_wr = wr; | |
648 | goto out; | |
649 | } | |
650 | ||
47688202 YL |
651 | wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1); |
652 | ||
2d407888 | 653 | if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) { |
ae1c6148 LO |
654 | ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n", |
655 | wr->num_sge, hr_qp->rq.max_gs); | |
2d407888 WHX |
656 | ret = -EINVAL; |
657 | *bad_wr = wr; | |
658 | goto out; | |
659 | } | |
660 | ||
6c6e3921 | 661 | wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx); |
2d407888 WHX |
662 | dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; |
663 | for (i = 0; i < wr->num_sge; i++) { | |
664 | if (!wr->sg_list[i].length) | |
665 | continue; | |
666 | set_data_seg_v2(dseg, wr->sg_list + i); | |
667 | dseg++; | |
668 | } | |
669 | ||
670 | if (i < hr_qp->rq.max_gs) { | |
778cc5a8 | 671 | dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY); |
672 | dseg->addr = 0; | |
2d407888 WHX |
673 | } |
674 | ||
0009c2db | 675 | /* rq support inline data */ |
ecaaf1e2 | 676 | if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) { |
47688202 YL |
677 | sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list; |
678 | hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt = | |
ecaaf1e2 | 679 | (u32)wr->num_sge; |
680 | for (i = 0; i < wr->num_sge; i++) { | |
681 | sge_list[i].addr = | |
682 | (void *)(u64)wr->sg_list[i].addr; | |
683 | sge_list[i].len = wr->sg_list[i].length; | |
684 | } | |
0009c2db | 685 | } |
686 | ||
47688202 | 687 | hr_qp->rq.wrid[wqe_idx] = wr->wr_id; |
2d407888 WHX |
688 | } |
689 | ||
690 | out: | |
691 | if (likely(nreq)) { | |
692 | hr_qp->rq.head += nreq; | |
693 | /* Memory barrier */ | |
694 | wmb(); | |
695 | ||
b5374286 YL |
696 | /* |
697 | * Hip08 hardware cannot flush the WQEs in RQ if the QP state | |
698 | * gets into errored mode. Hence, as a workaround to this | |
699 | * hardware limitation, driver needs to assist in flushing. But | |
700 | * the flushing operation uses mailbox to convey the QP state to | |
701 | * the hardware and which can sleep due to the mutex protection | |
702 | * around the mailbox calls. Hence, use the deferred flush for | |
703 | * now. | |
704 | */ | |
75c994e6 | 705 | if (hr_qp->state == IB_QPS_ERR) { |
b5374286 YL |
706 | if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, |
707 | &hr_qp->flush_flag)) | |
708 | init_flush_work(hr_dev, hr_qp); | |
75c994e6 YL |
709 | } else { |
710 | *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff; | |
711 | } | |
2d407888 WHX |
712 | } |
713 | spin_unlock_irqrestore(&hr_qp->rq.lock, flags); | |
714 | ||
715 | return ret; | |
716 | } | |
717 | ||
6a04aed6 WHX |
718 | static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, |
719 | unsigned long instance_stage, | |
720 | unsigned long reset_stage) | |
721 | { | |
722 | /* When hardware reset has been completed once or more, we should stop | |
d3743fa9 | 723 | * sending mailbox&cmq&doorbell to hardware. If now in .init_instance() |
6a04aed6 WHX |
724 | * function, we should exit with error. If now at HNAE3_INIT_CLIENT |
725 | * stage of soft reset process, we should exit with error, and then | |
726 | * HNAE3_INIT_CLIENT related process can rollback the operation like | |
727 | * notifing hardware to free resources, HNAE3_INIT_CLIENT related | |
728 | * process will exit with error to notify NIC driver to reschedule soft | |
729 | * reset process once again. | |
730 | */ | |
731 | hr_dev->is_reset = true; | |
d3743fa9 | 732 | hr_dev->dis_db = true; |
6a04aed6 WHX |
733 | |
734 | if (reset_stage == HNS_ROCE_STATE_RST_INIT || | |
735 | instance_stage == HNS_ROCE_STATE_INIT) | |
736 | return CMD_RST_PRC_EBUSY; | |
737 | ||
738 | return CMD_RST_PRC_SUCCESS; | |
739 | } | |
740 | ||
741 | static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, | |
742 | unsigned long instance_stage, | |
743 | unsigned long reset_stage) | |
744 | { | |
745 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
746 | struct hnae3_handle *handle = priv->handle; | |
747 | const struct hnae3_ae_ops *ops = handle->ae_algo->ops; | |
748 | ||
d3743fa9 WHX |
749 | /* When hardware reset is detected, we should stop sending mailbox&cmq& |
750 | * doorbell to hardware. If now in .init_instance() function, we should | |
6a04aed6 WHX |
751 | * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset |
752 | * process, we should exit with error, and then HNAE3_INIT_CLIENT | |
753 | * related process can rollback the operation like notifing hardware to | |
754 | * free resources, HNAE3_INIT_CLIENT related process will exit with | |
755 | * error to notify NIC driver to reschedule soft reset process once | |
756 | * again. | |
757 | */ | |
d3743fa9 | 758 | hr_dev->dis_db = true; |
6a04aed6 WHX |
759 | if (!ops->get_hw_reset_stat(handle)) |
760 | hr_dev->is_reset = true; | |
761 | ||
762 | if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT || | |
763 | instance_stage == HNS_ROCE_STATE_INIT) | |
764 | return CMD_RST_PRC_EBUSY; | |
765 | ||
766 | return CMD_RST_PRC_SUCCESS; | |
767 | } | |
768 | ||
769 | static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) | |
770 | { | |
771 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
772 | struct hnae3_handle *handle = priv->handle; | |
773 | const struct hnae3_ae_ops *ops = handle->ae_algo->ops; | |
774 | ||
775 | /* When software reset is detected at .init_instance() function, we | |
d3743fa9 WHX |
776 | * should stop sending mailbox&cmq&doorbell to hardware, and exit |
777 | * with error. | |
6a04aed6 | 778 | */ |
d3743fa9 | 779 | hr_dev->dis_db = true; |
6a04aed6 WHX |
780 | if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt) |
781 | hr_dev->is_reset = true; | |
782 | ||
783 | return CMD_RST_PRC_EBUSY; | |
784 | } | |
785 | ||
786 | static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev) | |
787 | { | |
788 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
789 | struct hnae3_handle *handle = priv->handle; | |
790 | const struct hnae3_ae_ops *ops = handle->ae_algo->ops; | |
791 | unsigned long instance_stage; /* the current instance stage */ | |
792 | unsigned long reset_stage; /* the current reset stage */ | |
793 | unsigned long reset_cnt; | |
794 | bool sw_resetting; | |
795 | bool hw_resetting; | |
796 | ||
797 | if (hr_dev->is_reset) | |
798 | return CMD_RST_PRC_SUCCESS; | |
799 | ||
800 | /* Get information about reset from NIC driver or RoCE driver itself, | |
801 | * the meaning of the following variables from NIC driver are described | |
802 | * as below: | |
803 | * reset_cnt -- The count value of completed hardware reset. | |
804 | * hw_resetting -- Whether hardware device is resetting now. | |
805 | * sw_resetting -- Whether NIC's software reset process is running now. | |
806 | */ | |
807 | instance_stage = handle->rinfo.instance_state; | |
808 | reset_stage = handle->rinfo.reset_state; | |
809 | reset_cnt = ops->ae_dev_reset_cnt(handle); | |
810 | hw_resetting = ops->get_hw_reset_stat(handle); | |
811 | sw_resetting = ops->ae_dev_resetting(handle); | |
812 | ||
813 | if (reset_cnt != hr_dev->reset_cnt) | |
814 | return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage, | |
815 | reset_stage); | |
816 | else if (hw_resetting) | |
817 | return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage, | |
818 | reset_stage); | |
819 | else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) | |
820 | return hns_roce_v2_cmd_sw_resetting(hr_dev); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
a04ff739 WHX |
825 | static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring) |
826 | { | |
827 | int ntu = ring->next_to_use; | |
828 | int ntc = ring->next_to_clean; | |
829 | int used = (ntu - ntc + ring->desc_num) % ring->desc_num; | |
830 | ||
831 | return ring->desc_num - used - 1; | |
832 | } | |
833 | ||
834 | static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, | |
835 | struct hns_roce_v2_cmq_ring *ring) | |
836 | { | |
837 | int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc); | |
838 | ||
839 | ring->desc = kzalloc(size, GFP_KERNEL); | |
840 | if (!ring->desc) | |
841 | return -ENOMEM; | |
842 | ||
843 | ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size, | |
844 | DMA_BIDIRECTIONAL); | |
845 | if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) { | |
846 | ring->desc_dma_addr = 0; | |
847 | kfree(ring->desc); | |
848 | ring->desc = NULL; | |
849 | return -ENOMEM; | |
850 | } | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, | |
856 | struct hns_roce_v2_cmq_ring *ring) | |
857 | { | |
858 | dma_unmap_single(hr_dev->dev, ring->desc_dma_addr, | |
859 | ring->desc_num * sizeof(struct hns_roce_cmq_desc), | |
860 | DMA_BIDIRECTIONAL); | |
90e7a4d5 | 861 | |
862 | ring->desc_dma_addr = 0; | |
a04ff739 WHX |
863 | kfree(ring->desc); |
864 | } | |
865 | ||
866 | static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type) | |
867 | { | |
868 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
869 | struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? | |
870 | &priv->cmq.csq : &priv->cmq.crq; | |
871 | ||
872 | ring->flag = ring_type; | |
873 | ring->next_to_clean = 0; | |
874 | ring->next_to_use = 0; | |
875 | ||
876 | return hns_roce_alloc_cmq_desc(hr_dev, ring); | |
877 | } | |
878 | ||
879 | static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type) | |
880 | { | |
881 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
882 | struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ? | |
883 | &priv->cmq.csq : &priv->cmq.crq; | |
884 | dma_addr_t dma = ring->desc_dma_addr; | |
885 | ||
886 | if (ring_type == TYPE_CSQ) { | |
887 | roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma); | |
888 | roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, | |
889 | upper_32_bits(dma)); | |
890 | roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG, | |
2288b3b3 | 891 | ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); |
a04ff739 WHX |
892 | roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0); |
893 | roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0); | |
894 | } else { | |
895 | roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma); | |
896 | roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG, | |
897 | upper_32_bits(dma)); | |
898 | roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG, | |
2288b3b3 | 899 | ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S); |
a04ff739 WHX |
900 | roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0); |
901 | roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0); | |
902 | } | |
903 | } | |
904 | ||
905 | static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) | |
906 | { | |
907 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
908 | int ret; | |
909 | ||
910 | /* Setup the queue entries for command queue */ | |
426c4146 LO |
911 | priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM; |
912 | priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM; | |
a04ff739 WHX |
913 | |
914 | /* Setup the lock for command queue */ | |
915 | spin_lock_init(&priv->cmq.csq.lock); | |
916 | spin_lock_init(&priv->cmq.crq.lock); | |
917 | ||
918 | /* Setup Tx write back timeout */ | |
919 | priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT; | |
920 | ||
921 | /* Init CSQ */ | |
922 | ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ); | |
923 | if (ret) { | |
924 | dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret); | |
925 | return ret; | |
926 | } | |
927 | ||
928 | /* Init CRQ */ | |
929 | ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ); | |
930 | if (ret) { | |
931 | dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret); | |
932 | goto err_crq; | |
933 | } | |
934 | ||
935 | /* Init CSQ REG */ | |
936 | hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ); | |
937 | ||
938 | /* Init CRQ REG */ | |
939 | hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ); | |
940 | ||
941 | return 0; | |
942 | ||
943 | err_crq: | |
944 | hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); | |
945 | ||
946 | return ret; | |
947 | } | |
948 | ||
949 | static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) | |
950 | { | |
951 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
952 | ||
953 | hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq); | |
954 | hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq); | |
955 | } | |
956 | ||
281d0ccf CIK |
957 | static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, |
958 | enum hns_roce_opcode_type opcode, | |
959 | bool is_read) | |
a04ff739 WHX |
960 | { |
961 | memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); | |
962 | desc->opcode = cpu_to_le16(opcode); | |
963 | desc->flag = | |
964 | cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); | |
965 | if (is_read) | |
966 | desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); | |
967 | else | |
968 | desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); | |
969 | } | |
970 | ||
971 | static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) | |
972 | { | |
973 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
974 | u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); | |
975 | ||
976 | return head == priv->cmq.csq.next_to_use; | |
977 | } | |
978 | ||
979 | static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev) | |
980 | { | |
981 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
982 | struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; | |
983 | struct hns_roce_cmq_desc *desc; | |
984 | u16 ntc = csq->next_to_clean; | |
985 | u32 head; | |
986 | int clean = 0; | |
987 | ||
988 | desc = &csq->desc[ntc]; | |
989 | head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG); | |
990 | while (head != ntc) { | |
991 | memset(desc, 0, sizeof(*desc)); | |
992 | ntc++; | |
993 | if (ntc == csq->desc_num) | |
994 | ntc = 0; | |
995 | desc = &csq->desc[ntc]; | |
996 | clean++; | |
997 | } | |
998 | csq->next_to_clean = ntc; | |
999 | ||
1000 | return clean; | |
1001 | } | |
1002 | ||
6a04aed6 WHX |
1003 | static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, |
1004 | struct hns_roce_cmq_desc *desc, int num) | |
a04ff739 WHX |
1005 | { |
1006 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
1007 | struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq; | |
1008 | struct hns_roce_cmq_desc *desc_to_use; | |
1009 | bool complete = false; | |
1010 | u32 timeout = 0; | |
1011 | int handle = 0; | |
1012 | u16 desc_ret; | |
1013 | int ret = 0; | |
1014 | int ntc; | |
1015 | ||
1016 | spin_lock_bh(&csq->lock); | |
1017 | ||
1018 | if (num > hns_roce_cmq_space(csq)) { | |
1019 | spin_unlock_bh(&csq->lock); | |
1020 | return -EBUSY; | |
1021 | } | |
1022 | ||
1023 | /* | |
1024 | * Record the location of desc in the cmq for this time | |
1025 | * which will be use for hardware to write back | |
1026 | */ | |
1027 | ntc = csq->next_to_use; | |
1028 | ||
1029 | while (handle < num) { | |
1030 | desc_to_use = &csq->desc[csq->next_to_use]; | |
1031 | *desc_to_use = desc[handle]; | |
1032 | dev_dbg(hr_dev->dev, "set cmq desc:\n"); | |
1033 | csq->next_to_use++; | |
1034 | if (csq->next_to_use == csq->desc_num) | |
1035 | csq->next_to_use = 0; | |
1036 | handle++; | |
1037 | } | |
1038 | ||
1039 | /* Write to hardware */ | |
1040 | roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); | |
1041 | ||
1042 | /* | |
1043 | * If the command is sync, wait for the firmware to write back, | |
1044 | * if multi descriptors to be sent, use the first one to check | |
1045 | */ | |
bfe86035 | 1046 | if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { |
a04ff739 WHX |
1047 | do { |
1048 | if (hns_roce_cmq_csq_done(hr_dev)) | |
1049 | break; | |
988e175b | 1050 | udelay(1); |
a04ff739 WHX |
1051 | timeout++; |
1052 | } while (timeout < priv->cmq.tx_timeout); | |
1053 | } | |
1054 | ||
1055 | if (hns_roce_cmq_csq_done(hr_dev)) { | |
1056 | complete = true; | |
1057 | handle = 0; | |
1058 | while (handle < num) { | |
1059 | /* get the result of hardware write back */ | |
1060 | desc_to_use = &csq->desc[ntc]; | |
1061 | desc[handle] = *desc_to_use; | |
1062 | dev_dbg(hr_dev->dev, "Get cmq desc:\n"); | |
bfe86035 | 1063 | desc_ret = le16_to_cpu(desc[handle].retval); |
a04ff739 WHX |
1064 | if (desc_ret == CMD_EXEC_SUCCESS) |
1065 | ret = 0; | |
1066 | else | |
1067 | ret = -EIO; | |
1068 | priv->cmq.last_status = desc_ret; | |
1069 | ntc++; | |
1070 | handle++; | |
1071 | if (ntc == csq->desc_num) | |
1072 | ntc = 0; | |
1073 | } | |
1074 | } | |
1075 | ||
1076 | if (!complete) | |
1077 | ret = -EAGAIN; | |
1078 | ||
1079 | /* clean the command send queue */ | |
1080 | handle = hns_roce_cmq_csq_clean(hr_dev); | |
1081 | if (handle != num) | |
1082 | dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n", | |
1083 | handle, num); | |
1084 | ||
1085 | spin_unlock_bh(&csq->lock); | |
1086 | ||
1087 | return ret; | |
1088 | } | |
1089 | ||
e95e52a1 | 1090 | static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, |
6a04aed6 WHX |
1091 | struct hns_roce_cmq_desc *desc, int num) |
1092 | { | |
1093 | int retval; | |
1094 | int ret; | |
1095 | ||
1096 | ret = hns_roce_v2_rst_process_cmd(hr_dev); | |
1097 | if (ret == CMD_RST_PRC_SUCCESS) | |
1098 | return 0; | |
1099 | if (ret == CMD_RST_PRC_EBUSY) | |
b417c087 | 1100 | return -EBUSY; |
6a04aed6 WHX |
1101 | |
1102 | ret = __hns_roce_cmq_send(hr_dev, desc, num); | |
1103 | if (ret) { | |
1104 | retval = hns_roce_v2_rst_process_cmd(hr_dev); | |
1105 | if (retval == CMD_RST_PRC_SUCCESS) | |
1106 | return 0; | |
1107 | else if (retval == CMD_RST_PRC_EBUSY) | |
b417c087 | 1108 | return -EBUSY; |
6a04aed6 WHX |
1109 | } |
1110 | ||
1111 | return ret; | |
1112 | } | |
1113 | ||
281d0ccf | 1114 | static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) |
cfc85f3e WHX |
1115 | { |
1116 | struct hns_roce_query_version *resp; | |
1117 | struct hns_roce_cmq_desc desc; | |
1118 | int ret; | |
1119 | ||
1120 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true); | |
1121 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); | |
1122 | if (ret) | |
1123 | return ret; | |
1124 | ||
1125 | resp = (struct hns_roce_query_version *)desc.data; | |
bfe86035 | 1126 | hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version); |
3a63c964 LO |
1127 | hr_dev->vendor_id = hr_dev->pci_dev->vendor; |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
e075da5e LC |
1132 | static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev) |
1133 | { | |
1134 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
1135 | struct hnae3_handle *handle = priv->handle; | |
1136 | const struct hnae3_ae_ops *ops = handle->ae_algo->ops; | |
1137 | unsigned long reset_cnt; | |
1138 | bool sw_resetting; | |
1139 | bool hw_resetting; | |
1140 | ||
1141 | reset_cnt = ops->ae_dev_reset_cnt(handle); | |
1142 | hw_resetting = ops->get_hw_reset_stat(handle); | |
1143 | sw_resetting = ops->ae_dev_resetting(handle); | |
1144 | ||
1145 | if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting) | |
1146 | return true; | |
1147 | ||
1148 | return false; | |
1149 | } | |
1150 | ||
1151 | static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval, | |
1152 | int flag) | |
1153 | { | |
1154 | struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; | |
1155 | struct hnae3_handle *handle = priv->handle; | |
1156 | const struct hnae3_ae_ops *ops = handle->ae_algo->ops; | |
1157 | unsigned long instance_stage; | |
1158 | unsigned long reset_cnt; | |
1159 | unsigned long end; | |
1160 | bool sw_resetting; | |
1161 | bool hw_resetting; | |
1162 | ||
1163 | instance_stage = handle->rinfo.instance_state; | |
1164 | reset_cnt = ops->ae_dev_reset_cnt(handle); | |
1165 | hw_resetting = ops->get_hw_reset_stat(handle); | |
1166 | sw_resetting = ops->ae_dev_resetting(handle); | |
1167 | ||
1168 | if (reset_cnt != hr_dev->reset_cnt) { | |
1169 | hr_dev->dis_db = true; | |
1170 | hr_dev->is_reset = true; | |
1171 | dev_info(hr_dev->dev, "Func clear success after reset.\n"); | |
1172 | } else if (hw_resetting) { | |
1173 | hr_dev->dis_db = true; | |
1174 | ||
1175 | dev_warn(hr_dev->dev, | |
1176 | "Func clear is pending, device in resetting state.\n"); | |
1177 | end = HNS_ROCE_V2_HW_RST_TIMEOUT; | |
1178 | while (end) { | |
1179 | if (!ops->get_hw_reset_stat(handle)) { | |
1180 | hr_dev->is_reset = true; | |
1181 | dev_info(hr_dev->dev, | |
1182 | "Func clear success after reset.\n"); | |
1183 | return; | |
1184 | } | |
1185 | msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); | |
1186 | end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; | |
1187 | } | |
1188 | ||
1189 | dev_warn(hr_dev->dev, "Func clear failed.\n"); | |
1190 | } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) { | |
1191 | hr_dev->dis_db = true; | |
1192 | ||
1193 | dev_warn(hr_dev->dev, | |
1194 | "Func clear is pending, device in resetting state.\n"); | |
1195 | end = HNS_ROCE_V2_HW_RST_TIMEOUT; | |
1196 | while (end) { | |
1197 | if (ops->ae_dev_reset_cnt(handle) != | |
1198 | hr_dev->reset_cnt) { | |
1199 | hr_dev->is_reset = true; | |
1200 | dev_info(hr_dev->dev, | |
1201 | "Func clear success after sw reset\n"); | |
1202 | return; | |
1203 | } | |
1204 | msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT); | |
1205 | end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT; | |
1206 | } | |
1207 | ||
1208 | dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n"); | |
1209 | } else { | |
1210 | if (retval && !flag) | |
1211 | dev_warn(hr_dev->dev, | |
1212 | "Func clear read failed, ret = %d.\n", retval); | |
1213 | ||
1214 | dev_warn(hr_dev->dev, "Func clear failed.\n"); | |
1215 | } | |
1216 | } | |
89a6da3c LC |
1217 | static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) |
1218 | { | |
e075da5e | 1219 | bool fclr_write_fail_flag = false; |
89a6da3c LC |
1220 | struct hns_roce_func_clear *resp; |
1221 | struct hns_roce_cmq_desc desc; | |
1222 | unsigned long end; | |
e075da5e LC |
1223 | int ret = 0; |
1224 | ||
1225 | if (hns_roce_func_clr_chk_rst(hr_dev)) | |
1226 | goto out; | |
89a6da3c LC |
1227 | |
1228 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false); | |
1229 | resp = (struct hns_roce_func_clear *)desc.data; | |
1230 | ||
1231 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); | |
1232 | if (ret) { | |
e075da5e | 1233 | fclr_write_fail_flag = true; |
89a6da3c LC |
1234 | dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n", |
1235 | ret); | |
e075da5e | 1236 | goto out; |
89a6da3c LC |
1237 | } |
1238 | ||
1239 | msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL); | |
1240 | end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS; | |
1241 | while (end) { | |
e075da5e LC |
1242 | if (hns_roce_func_clr_chk_rst(hr_dev)) |
1243 | goto out; | |
89a6da3c LC |
1244 | msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT); |
1245 | end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT; | |
1246 | ||
1247 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, | |
1248 | true); | |
1249 | ||
1250 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); | |
1251 | if (ret) | |
1252 | continue; | |
1253 | ||
1254 | if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) { | |
1255 | hr_dev->is_reset = true; | |
1256 | return; | |
1257 | } | |
1258 | } | |
1259 | ||
e075da5e | 1260 | out: |
e075da5e | 1261 | hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag); |
89a6da3c LC |
1262 | } |
1263 | ||
3a63c964 LO |
1264 | static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) |
1265 | { | |
1266 | struct hns_roce_query_fw_info *resp; | |
1267 | struct hns_roce_cmq_desc desc; | |
1268 | int ret; | |
1269 | ||
1270 | hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true); | |
1271 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); | |
1272 | if (ret) | |
1273 | return ret; | |
1274 | ||
1275 | resp = (struct hns_roce_query_fw_info *)desc.data; | |
1276 | hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); | |
cfc85f3e WHX |
1277 | |
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) | |
1282 | { | |
1283 | struct hns_roce_cfg_global_param *req; | |
1284 | struct hns_roce_cmq_desc desc; | |
1285 | ||
1286 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM, | |
1287 | false); | |
1288 | ||
1289 | req = (struct hns_roce_cfg_global_param *)desc.data; | |
1290 | memset(req, 0, sizeof(*req)); | |
1291 | roce_set_field(req->time_cfg_udp_port, | |
1292 | CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M, | |
1293 | CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8); | |
1294 | roce_set_field(req->time_cfg_udp_port, | |
1295 | CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M, | |
1296 | CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7); | |
1297 | ||
1298 | return hns_roce_cmq_send(hr_dev, &desc, 1); | |
1299 | } | |
1300 | ||
1301 | static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) | |
1302 | { | |
1303 | struct hns_roce_cmq_desc desc[2]; | |
6b63597d | 1304 | struct hns_roce_pf_res_a *req_a; |
1305 | struct hns_roce_pf_res_b *req_b; | |
cfc85f3e WHX |
1306 | int ret; |
1307 | int i; | |
1308 | ||
1309 | for (i = 0; i < 2; i++) { | |
1310 | hns_roce_cmq_setup_basic_desc(&desc[i], | |
1311 | HNS_ROCE_OPC_QUERY_PF_RES, true); | |
1312 | ||
1313 | if (i == 0) | |
1314 | desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
1315 | else | |
1316 | desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
1317 | } | |
1318 | ||
1319 | ret = hns_roce_cmq_send(hr_dev, desc, 2); | |
1320 | if (ret) | |
1321 | return ret; | |
1322 | ||
6b63597d | 1323 | req_a = (struct hns_roce_pf_res_a *)desc[0].data; |
1324 | req_b = (struct hns_roce_pf_res_b *)desc[1].data; | |
cfc85f3e | 1325 | |
6b63597d | 1326 | hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num, |
cfc85f3e WHX |
1327 | PF_RES_DATA_1_PF_QPC_BT_NUM_M, |
1328 | PF_RES_DATA_1_PF_QPC_BT_NUM_S); | |
6b63597d | 1329 | hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num, |
cfc85f3e WHX |
1330 | PF_RES_DATA_2_PF_SRQC_BT_NUM_M, |
1331 | PF_RES_DATA_2_PF_SRQC_BT_NUM_S); | |
6b63597d | 1332 | hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num, |
cfc85f3e WHX |
1333 | PF_RES_DATA_3_PF_CQC_BT_NUM_M, |
1334 | PF_RES_DATA_3_PF_CQC_BT_NUM_S); | |
6b63597d | 1335 | hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num, |
cfc85f3e WHX |
1336 | PF_RES_DATA_4_PF_MPT_BT_NUM_M, |
1337 | PF_RES_DATA_4_PF_MPT_BT_NUM_S); | |
1338 | ||
6b63597d | 1339 | hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num, |
1340 | PF_RES_DATA_3_PF_SL_NUM_M, | |
1341 | PF_RES_DATA_3_PF_SL_NUM_S); | |
6a157f7d YL |
1342 | hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num, |
1343 | PF_RES_DATA_4_PF_SCCC_BT_NUM_M, | |
1344 | PF_RES_DATA_4_PF_SCCC_BT_NUM_S); | |
6b63597d | 1345 | |
cfc85f3e WHX |
1346 | return 0; |
1347 | } | |
1348 | ||
0e40dc2f YL |
1349 | static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev) |
1350 | { | |
1351 | struct hns_roce_pf_timer_res_a *req_a; | |
1352 | struct hns_roce_cmq_desc desc[2]; | |
1353 | int ret, i; | |
1354 | ||
1355 | for (i = 0; i < 2; i++) { | |
1356 | hns_roce_cmq_setup_basic_desc(&desc[i], | |
1357 | HNS_ROCE_OPC_QUERY_PF_TIMER_RES, | |
1358 | true); | |
1359 | ||
1360 | if (i == 0) | |
1361 | desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
1362 | else | |
1363 | desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
1364 | } | |
1365 | ||
1366 | ret = hns_roce_cmq_send(hr_dev, desc, 2); | |
1367 | if (ret) | |
1368 | return ret; | |
1369 | ||
1370 | req_a = (struct hns_roce_pf_timer_res_a *)desc[0].data; | |
1371 | ||
1372 | hr_dev->caps.qpc_timer_bt_num = | |
1373 | roce_get_field(req_a->qpc_timer_bt_idx_num, | |
1374 | PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M, | |
1375 | PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S); | |
1376 | hr_dev->caps.cqc_timer_bt_num = | |
1377 | roce_get_field(req_a->cqc_timer_bt_idx_num, | |
1378 | PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M, | |
1379 | PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S); | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
60262b10 | 1384 | static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id) |
0c1c3880 LO |
1385 | { |
1386 | struct hns_roce_cmq_desc desc; | |
1387 | struct hns_roce_vf_switch *swt; | |
1388 | int ret; | |
1389 | ||
1390 | swt = (struct hns_roce_vf_switch *)desc.data; | |
1391 | hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true); | |
bfe86035 | 1392 | swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL); |
60262b10 LO |
1393 | roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M, |
1394 | VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id); | |
0c1c3880 LO |
1395 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); |
1396 | if (ret) | |
1397 | return ret; | |
60262b10 | 1398 | |
0c1c3880 LO |
1399 | desc.flag = |
1400 | cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); | |
1401 | desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); | |
1402 | roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); | |
d967e262 | 1403 | roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); |
0c1c3880 LO |
1404 | roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1); |
1405 | ||
1406 | return hns_roce_cmq_send(hr_dev, &desc, 1); | |
1407 | } | |
1408 | ||
cfc85f3e WHX |
1409 | static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) |
1410 | { | |
1411 | struct hns_roce_cmq_desc desc[2]; | |
1412 | struct hns_roce_vf_res_a *req_a; | |
1413 | struct hns_roce_vf_res_b *req_b; | |
1414 | int i; | |
1415 | ||
1416 | req_a = (struct hns_roce_vf_res_a *)desc[0].data; | |
1417 | req_b = (struct hns_roce_vf_res_b *)desc[1].data; | |
1418 | memset(req_a, 0, sizeof(*req_a)); | |
1419 | memset(req_b, 0, sizeof(*req_b)); | |
1420 | for (i = 0; i < 2; i++) { | |
1421 | hns_roce_cmq_setup_basic_desc(&desc[i], | |
1422 | HNS_ROCE_OPC_ALLOC_VF_RES, false); | |
1423 | ||
1424 | if (i == 0) | |
1425 | desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
1426 | else | |
1427 | desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
cfc85f3e WHX |
1428 | } |
1429 | ||
99e713f8 LO |
1430 | roce_set_field(req_a->vf_qpc_bt_idx_num, |
1431 | VF_RES_A_DATA_1_VF_QPC_BT_IDX_M, | |
1432 | VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0); | |
1433 | roce_set_field(req_a->vf_qpc_bt_idx_num, | |
1434 | VF_RES_A_DATA_1_VF_QPC_BT_NUM_M, | |
1435 | VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM); | |
1436 | ||
1437 | roce_set_field(req_a->vf_srqc_bt_idx_num, | |
1438 | VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M, | |
1439 | VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0); | |
1440 | roce_set_field(req_a->vf_srqc_bt_idx_num, | |
1441 | VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M, | |
1442 | VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S, | |
1443 | HNS_ROCE_VF_SRQC_BT_NUM); | |
1444 | ||
1445 | roce_set_field(req_a->vf_cqc_bt_idx_num, | |
1446 | VF_RES_A_DATA_3_VF_CQC_BT_IDX_M, | |
1447 | VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0); | |
1448 | roce_set_field(req_a->vf_cqc_bt_idx_num, | |
1449 | VF_RES_A_DATA_3_VF_CQC_BT_NUM_M, | |
1450 | VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM); | |
1451 | ||
1452 | roce_set_field(req_a->vf_mpt_bt_idx_num, | |
1453 | VF_RES_A_DATA_4_VF_MPT_BT_IDX_M, | |
1454 | VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0); | |
1455 | roce_set_field(req_a->vf_mpt_bt_idx_num, | |
1456 | VF_RES_A_DATA_4_VF_MPT_BT_NUM_M, | |
1457 | VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM); | |
1458 | ||
1459 | roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M, | |
1460 | VF_RES_A_DATA_5_VF_EQC_IDX_S, 0); | |
1461 | roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M, | |
1462 | VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM); | |
1463 | ||
1464 | roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M, | |
1465 | VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0); | |
1466 | roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M, | |
1467 | VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM); | |
1468 | ||
1469 | roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M, | |
1470 | VF_RES_B_DATA_2_VF_SGID_IDX_S, 0); | |
1471 | roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M, | |
1472 | VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM); | |
1473 | ||
1474 | roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M, | |
1475 | VF_RES_B_DATA_3_VF_QID_IDX_S, 0); | |
1476 | roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M, | |
1477 | VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM); | |
1478 | ||
1479 | roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M, | |
1480 | VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0); | |
1481 | roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M, | |
1482 | VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S, | |
1483 | HNS_ROCE_VF_SCCC_BT_NUM); | |
1484 | ||
cfc85f3e WHX |
1485 | return hns_roce_cmq_send(hr_dev, desc, 2); |
1486 | } | |
1487 | ||
a81fba28 WHX |
1488 | static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) |
1489 | { | |
1490 | u8 srqc_hop_num = hr_dev->caps.srqc_hop_num; | |
1491 | u8 qpc_hop_num = hr_dev->caps.qpc_hop_num; | |
1492 | u8 cqc_hop_num = hr_dev->caps.cqc_hop_num; | |
1493 | u8 mpt_hop_num = hr_dev->caps.mpt_hop_num; | |
6a157f7d | 1494 | u8 sccc_hop_num = hr_dev->caps.sccc_hop_num; |
a81fba28 WHX |
1495 | struct hns_roce_cfg_bt_attr *req; |
1496 | struct hns_roce_cmq_desc desc; | |
1497 | ||
1498 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false); | |
1499 | req = (struct hns_roce_cfg_bt_attr *)desc.data; | |
1500 | memset(req, 0, sizeof(*req)); | |
1501 | ||
1502 | roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M, | |
1503 | CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S, | |
5e6e78db | 1504 | hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1505 | roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M, |
1506 | CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S, | |
5e6e78db | 1507 | hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1508 | roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M, |
1509 | CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S, | |
1510 | qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num); | |
1511 | ||
1512 | roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M, | |
1513 | CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S, | |
5e6e78db | 1514 | hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1515 | roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M, |
1516 | CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S, | |
5e6e78db | 1517 | hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1518 | roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M, |
1519 | CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S, | |
1520 | srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num); | |
1521 | ||
1522 | roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M, | |
1523 | CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S, | |
5e6e78db | 1524 | hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1525 | roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M, |
1526 | CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S, | |
5e6e78db | 1527 | hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1528 | roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M, |
1529 | CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S, | |
1530 | cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num); | |
1531 | ||
1532 | roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M, | |
1533 | CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S, | |
5e6e78db | 1534 | hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1535 | roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M, |
1536 | CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S, | |
5e6e78db | 1537 | hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET); |
a81fba28 WHX |
1538 | roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M, |
1539 | CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S, | |
1540 | mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num); | |
1541 | ||
6a157f7d YL |
1542 | roce_set_field(req->vf_sccc_cfg, |
1543 | CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M, | |
1544 | CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S, | |
1545 | hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET); | |
1546 | roce_set_field(req->vf_sccc_cfg, | |
1547 | CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M, | |
1548 | CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S, | |
1549 | hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET); | |
1550 | roce_set_field(req->vf_sccc_cfg, | |
1551 | CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M, | |
1552 | CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S, | |
1553 | sccc_hop_num == | |
1554 | HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num); | |
1555 | ||
a81fba28 WHX |
1556 | return hns_roce_cmq_send(hr_dev, &desc, 1); |
1557 | } | |
1558 | ||
ba6bb7e9 LO |
1559 | static void set_default_caps(struct hns_roce_dev *hr_dev) |
1560 | { | |
1561 | struct hns_roce_caps *caps = &hr_dev->caps; | |
1562 | ||
1563 | caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM; | |
1564 | caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM; | |
1565 | caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM; | |
1566 | caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM; | |
1567 | caps->min_cqes = HNS_ROCE_MIN_CQE_NUM; | |
1568 | caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM; | |
1569 | caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM; | |
1570 | caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM; | |
1571 | caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM; | |
1572 | caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; | |
1573 | caps->num_uars = HNS_ROCE_V2_UAR_NUM; | |
1574 | caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM; | |
1575 | caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM; | |
1576 | caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM; | |
1577 | caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM; | |
1578 | caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM; | |
1579 | caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; | |
1580 | caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; | |
1581 | caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; | |
1582 | caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; | |
1583 | caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM; | |
1584 | caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA; | |
1585 | caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA; | |
1586 | caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ; | |
1587 | caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ; | |
1588 | caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ; | |
1589 | caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ; | |
1590 | caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ; | |
7db82697 | 1591 | caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ; |
ba6bb7e9 LO |
1592 | caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ; |
1593 | caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ; | |
1594 | caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ; | |
1595 | caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; | |
1596 | caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ; | |
1597 | caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE; | |
1598 | caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED; | |
1599 | caps->reserved_lkey = 0; | |
1600 | caps->reserved_pds = 0; | |
1601 | caps->reserved_mrws = 1; | |
1602 | caps->reserved_uars = 0; | |
1603 | caps->reserved_cqs = 0; | |
1604 | caps->reserved_srqs = 0; | |
1605 | caps->reserved_qps = HNS_ROCE_V2_RSV_QPS; | |
1606 | ||
1607 | caps->qpc_ba_pg_sz = 0; | |
1608 | caps->qpc_buf_pg_sz = 0; | |
1609 | caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; | |
1610 | caps->srqc_ba_pg_sz = 0; | |
1611 | caps->srqc_buf_pg_sz = 0; | |
1612 | caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; | |
1613 | caps->cqc_ba_pg_sz = 0; | |
1614 | caps->cqc_buf_pg_sz = 0; | |
1615 | caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; | |
1616 | caps->mpt_ba_pg_sz = 0; | |
1617 | caps->mpt_buf_pg_sz = 0; | |
1618 | caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM; | |
1619 | caps->mtt_ba_pg_sz = 0; | |
1620 | caps->mtt_buf_pg_sz = 0; | |
1621 | caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM; | |
1622 | caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM; | |
1623 | caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM; | |
1624 | caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM; | |
1625 | caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K; | |
1626 | caps->cqe_buf_pg_sz = 0; | |
1627 | caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM; | |
1628 | caps->srqwqe_ba_pg_sz = 0; | |
1629 | caps->srqwqe_buf_pg_sz = 0; | |
1630 | caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM; | |
1631 | caps->idx_ba_pg_sz = 0; | |
1632 | caps->idx_buf_pg_sz = 0; | |
1633 | caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM; | |
1634 | caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE; | |
1635 | ||
1636 | caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR | | |
1637 | HNS_ROCE_CAP_FLAG_ROCE_V1_V2 | | |
1638 | HNS_ROCE_CAP_FLAG_RQ_INLINE | | |
1639 | HNS_ROCE_CAP_FLAG_RECORD_DB | | |
1640 | HNS_ROCE_CAP_FLAG_SQ_RECORD_DB; | |
1641 | ||
1642 | caps->pkey_table_len[0] = 1; | |
1643 | caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; | |
1644 | caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM; | |
1645 | caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM; | |
1646 | caps->local_ca_ack_delay = 0; | |
1647 | caps->max_mtu = IB_MTU_4096; | |
1648 | ||
1649 | caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR; | |
1650 | caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE; | |
1651 | ||
dfaf2854 | 1652 | if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) { |
ba6bb7e9 LO |
1653 | caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW | |
1654 | HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR | | |
1655 | HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL; | |
1656 | ||
1657 | caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM; | |
1658 | caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; | |
1659 | caps->qpc_timer_ba_pg_sz = 0; | |
1660 | caps->qpc_timer_buf_pg_sz = 0; | |
1661 | caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; | |
1662 | caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM; | |
1663 | caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; | |
1664 | caps->cqc_timer_ba_pg_sz = 0; | |
1665 | caps->cqc_timer_buf_pg_sz = 0; | |
1666 | caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; | |
1667 | ||
1668 | caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ; | |
1669 | caps->sccc_ba_pg_sz = 0; | |
1670 | caps->sccc_buf_pg_sz = 0; | |
1671 | caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM; | |
1672 | } | |
1673 | } | |
1674 | ||
1675 | static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num, | |
1676 | int *buf_page_size, int *bt_page_size, u32 hem_type) | |
1677 | { | |
1678 | u64 obj_per_chunk; | |
1679 | int bt_chunk_size = 1 << PAGE_SHIFT; | |
1680 | int buf_chunk_size = 1 << PAGE_SHIFT; | |
1681 | int obj_per_chunk_default = buf_chunk_size / obj_size; | |
1682 | ||
1683 | *buf_page_size = 0; | |
1684 | *bt_page_size = 0; | |
1685 | ||
1686 | switch (hop_num) { | |
1687 | case 3: | |
1688 | obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * | |
1689 | (bt_chunk_size / BA_BYTE_LEN) * | |
1690 | (bt_chunk_size / BA_BYTE_LEN) * | |
1691 | obj_per_chunk_default; | |
1692 | break; | |
1693 | case 2: | |
1694 | obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * | |
1695 | (bt_chunk_size / BA_BYTE_LEN) * | |
1696 | obj_per_chunk_default; | |
1697 | break; | |
1698 | case 1: | |
1699 | obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) * | |
1700 | obj_per_chunk_default; | |
1701 | break; | |
1702 | case HNS_ROCE_HOP_NUM_0: | |
1703 | obj_per_chunk = ctx_bt_num * obj_per_chunk_default; | |
1704 | break; | |
1705 | default: | |
1706 | pr_err("Table %d not support hop_num = %d!\n", hem_type, | |
1707 | hop_num); | |
1708 | return; | |
1709 | } | |
1710 | ||
1711 | if (hem_type >= HEM_TYPE_MTT) | |
1712 | *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); | |
1713 | else | |
1714 | *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk)); | |
1715 | } | |
1716 | ||
1717 | static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) | |
1718 | { | |
1719 | struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM]; | |
1720 | struct hns_roce_caps *caps = &hr_dev->caps; | |
1721 | struct hns_roce_query_pf_caps_a *resp_a; | |
1722 | struct hns_roce_query_pf_caps_b *resp_b; | |
1723 | struct hns_roce_query_pf_caps_c *resp_c; | |
1724 | struct hns_roce_query_pf_caps_d *resp_d; | |
1725 | struct hns_roce_query_pf_caps_e *resp_e; | |
1726 | int ctx_hop_num; | |
1727 | int pbl_hop_num; | |
1728 | int ret; | |
1729 | int i; | |
1730 | ||
1731 | for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) { | |
1732 | hns_roce_cmq_setup_basic_desc(&desc[i], | |
1733 | HNS_ROCE_OPC_QUERY_PF_CAPS_NUM, | |
1734 | true); | |
1735 | if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1)) | |
1736 | desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
1737 | else | |
1738 | desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
1739 | } | |
1740 | ||
1741 | ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM); | |
1742 | if (ret) | |
1743 | return ret; | |
1744 | ||
1745 | resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data; | |
1746 | resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data; | |
1747 | resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data; | |
1748 | resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data; | |
1749 | resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data; | |
1750 | ||
1751 | caps->local_ca_ack_delay = resp_a->local_ca_ack_delay; | |
1752 | caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg); | |
1753 | caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline); | |
1754 | caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg); | |
1755 | caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg); | |
1756 | caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer); | |
1757 | caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer); | |
1758 | caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges); | |
1759 | caps->num_aeq_vectors = resp_a->num_aeq_vectors; | |
1760 | caps->num_other_vectors = resp_a->num_other_vectors; | |
1761 | caps->max_sq_desc_sz = resp_a->max_sq_desc_sz; | |
1762 | caps->max_rq_desc_sz = resp_a->max_rq_desc_sz; | |
1763 | caps->max_srq_desc_sz = resp_a->max_srq_desc_sz; | |
1764 | caps->cq_entry_sz = resp_a->cq_entry_sz; | |
1765 | ||
1766 | caps->mtpt_entry_sz = resp_b->mtpt_entry_sz; | |
1767 | caps->irrl_entry_sz = resp_b->irrl_entry_sz; | |
1768 | caps->trrl_entry_sz = resp_b->trrl_entry_sz; | |
1769 | caps->cqc_entry_sz = resp_b->cqc_entry_sz; | |
1770 | caps->srqc_entry_sz = resp_b->srqc_entry_sz; | |
1771 | caps->idx_entry_sz = resp_b->idx_entry_sz; | |
1772 | caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz; | |
1773 | caps->max_mtu = resp_b->max_mtu; | |
1774 | caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz); | |
1775 | caps->min_cqes = resp_b->min_cqes; | |
1776 | caps->min_wqes = resp_b->min_wqes; | |
1777 | caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap); | |
1778 | caps->pkey_table_len[0] = resp_b->pkey_table_len; | |
1779 | caps->phy_num_uars = resp_b->phy_num_uars; | |
1780 | ctx_hop_num = resp_b->ctx_hop_num; | |
1781 | pbl_hop_num = resp_b->pbl_hop_num; | |
1782 | ||
1783 | caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds, | |
1784 | V2_QUERY_PF_CAPS_C_NUM_PDS_M, | |
1785 | V2_QUERY_PF_CAPS_C_NUM_PDS_S); | |
1786 | caps->flags = roce_get_field(resp_c->cap_flags_num_pds, | |
1787 | V2_QUERY_PF_CAPS_C_CAP_FLAGS_M, | |
1788 | V2_QUERY_PF_CAPS_C_CAP_FLAGS_S); | |
1789 | caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs, | |
1790 | V2_QUERY_PF_CAPS_C_NUM_CQS_M, | |
1791 | V2_QUERY_PF_CAPS_C_NUM_CQS_S); | |
1792 | caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs, | |
1793 | V2_QUERY_PF_CAPS_C_MAX_GID_M, | |
1794 | V2_QUERY_PF_CAPS_C_MAX_GID_S); | |
1795 | caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth, | |
1796 | V2_QUERY_PF_CAPS_C_CQ_DEPTH_M, | |
1797 | V2_QUERY_PF_CAPS_C_CQ_DEPTH_S); | |
1798 | caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws, | |
1799 | V2_QUERY_PF_CAPS_C_NUM_MRWS_M, | |
1800 | V2_QUERY_PF_CAPS_C_NUM_MRWS_S); | |
1801 | caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps, | |
1802 | V2_QUERY_PF_CAPS_C_NUM_QPS_M, | |
1803 | V2_QUERY_PF_CAPS_C_NUM_QPS_S); | |
1804 | caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps, | |
1805 | V2_QUERY_PF_CAPS_C_MAX_ORD_M, | |
1806 | V2_QUERY_PF_CAPS_C_MAX_ORD_S); | |
1807 | caps->max_qp_dest_rdma = caps->max_qp_init_rdma; | |
1808 | caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth); | |
1809 | caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs, | |
1810 | V2_QUERY_PF_CAPS_D_NUM_SRQS_M, | |
1811 | V2_QUERY_PF_CAPS_D_NUM_SRQS_S); | |
1812 | caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth); | |
1813 | caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth, | |
1814 | V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M, | |
1815 | V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S); | |
1816 | caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth, | |
1817 | V2_QUERY_PF_CAPS_D_NUM_CEQS_M, | |
1818 | V2_QUERY_PF_CAPS_D_NUM_CEQS_S); | |
1819 | caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth, | |
1820 | V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M, | |
1821 | V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S); | |
1822 | caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, | |
1823 | V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M, | |
1824 | V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S); | |
1825 | caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth, | |
1826 | V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M, | |
1827 | V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S); | |
1828 | caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds, | |
1829 | V2_QUERY_PF_CAPS_D_RSV_PDS_M, | |
1830 | V2_QUERY_PF_CAPS_D_RSV_PDS_S); | |
1831 | caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds, | |
1832 | V2_QUERY_PF_CAPS_D_NUM_UARS_M, | |
1833 | V2_QUERY_PF_CAPS_D_NUM_UARS_S); | |
1834 | caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps, | |
1835 | V2_QUERY_PF_CAPS_D_RSV_QPS_M, | |
1836 | V2_QUERY_PF_CAPS_D_RSV_QPS_S); | |
1837 | caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps, | |
1838 | V2_QUERY_PF_CAPS_D_RSV_UARS_M, | |
1839 | V2_QUERY_PF_CAPS_D_RSV_UARS_S); | |
1840 | caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws, | |
1841 | V2_QUERY_PF_CAPS_E_RSV_MRWS_M, | |
1842 | V2_QUERY_PF_CAPS_E_RSV_MRWS_S); | |
1843 | caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws, | |
1844 | V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M, | |
1845 | V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S); | |
1846 | caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs, | |
1847 | V2_QUERY_PF_CAPS_E_RSV_CQS_M, | |
1848 | V2_QUERY_PF_CAPS_E_RSV_CQS_S); | |
1849 | caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs, | |
1850 | V2_QUERY_PF_CAPS_E_RSV_SRQS_M, | |
1851 | V2_QUERY_PF_CAPS_E_RSV_SRQS_S); | |
1852 | caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey, | |
1853 | V2_QUERY_PF_CAPS_E_RSV_LKEYS_M, | |
1854 | V2_QUERY_PF_CAPS_E_RSV_LKEYS_S); | |
1855 | caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt); | |
1856 | caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period); | |
1857 | caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt); | |
1858 | caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period); | |
1859 | ||
1860 | caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ; | |
1861 | caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ; | |
1862 | caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ; | |
1863 | caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; | |
1864 | caps->mtt_ba_pg_sz = 0; | |
1865 | caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; | |
1866 | caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; | |
1867 | caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; | |
1868 | ||
1869 | caps->qpc_hop_num = ctx_hop_num; | |
1870 | caps->srqc_hop_num = ctx_hop_num; | |
1871 | caps->cqc_hop_num = ctx_hop_num; | |
1872 | caps->mpt_hop_num = ctx_hop_num; | |
1873 | caps->mtt_hop_num = pbl_hop_num; | |
1874 | caps->cqe_hop_num = pbl_hop_num; | |
1875 | caps->srqwqe_hop_num = pbl_hop_num; | |
1876 | caps->idx_hop_num = pbl_hop_num; | |
1877 | caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, | |
1878 | V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M, | |
1879 | V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S); | |
1880 | caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, | |
1881 | V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M, | |
1882 | V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S); | |
1883 | caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs, | |
1884 | V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M, | |
1885 | V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S); | |
1886 | ||
1887 | calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num, | |
1888 | caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz, | |
1889 | HEM_TYPE_QPC); | |
1890 | calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num, | |
1891 | caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz, | |
1892 | HEM_TYPE_MTPT); | |
1893 | calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num, | |
1894 | caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz, | |
1895 | HEM_TYPE_CQC); | |
1896 | calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num, | |
1897 | caps->srqc_bt_num, &caps->srqc_buf_pg_sz, | |
1898 | &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC); | |
1899 | ||
dfaf2854 | 1900 | if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) { |
ba6bb7e9 LO |
1901 | caps->sccc_hop_num = ctx_hop_num; |
1902 | caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0; | |
1903 | caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0; | |
1904 | ||
1905 | calc_pg_sz(caps->num_qps, caps->sccc_entry_sz, | |
1906 | caps->sccc_hop_num, caps->sccc_bt_num, | |
1907 | &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz, | |
1908 | HEM_TYPE_SCCC); | |
1909 | calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz, | |
1910 | caps->cqc_timer_hop_num, caps->cqc_timer_bt_num, | |
1911 | &caps->cqc_timer_buf_pg_sz, | |
1912 | &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER); | |
1913 | } | |
1914 | ||
1915 | calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num, | |
1916 | 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE); | |
1917 | calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz, | |
1918 | caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz, | |
1919 | &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE); | |
1920 | calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num, | |
1921 | 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX); | |
1922 | ||
1923 | return 0; | |
1924 | } | |
1925 | ||
cfc85f3e WHX |
1926 | static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) |
1927 | { | |
1928 | struct hns_roce_caps *caps = &hr_dev->caps; | |
1929 | int ret; | |
1930 | ||
1931 | ret = hns_roce_cmq_query_hw_info(hr_dev); | |
3a63c964 LO |
1932 | if (ret) { |
1933 | dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n", | |
1934 | ret); | |
1935 | return ret; | |
1936 | } | |
1937 | ||
1938 | ret = hns_roce_query_fw_ver(hr_dev); | |
cfc85f3e WHX |
1939 | if (ret) { |
1940 | dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n", | |
1941 | ret); | |
1942 | return ret; | |
1943 | } | |
1944 | ||
1945 | ret = hns_roce_config_global_param(hr_dev); | |
1946 | if (ret) { | |
1947 | dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n", | |
1948 | ret); | |
2349fdd4 | 1949 | return ret; |
cfc85f3e WHX |
1950 | } |
1951 | ||
1952 | /* Get pf resource owned by every pf */ | |
1953 | ret = hns_roce_query_pf_resource(hr_dev); | |
1954 | if (ret) { | |
1955 | dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n", | |
1956 | ret); | |
1957 | return ret; | |
1958 | } | |
1959 | ||
dfaf2854 | 1960 | if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) { |
0e40dc2f YL |
1961 | ret = hns_roce_query_pf_timer_resource(hr_dev); |
1962 | if (ret) { | |
1963 | dev_err(hr_dev->dev, | |
1964 | "Query pf timer resource fail, ret = %d.\n", | |
1965 | ret); | |
1966 | return ret; | |
1967 | } | |
cfc85f3e | 1968 | |
0c1c3880 LO |
1969 | ret = hns_roce_set_vf_switch_param(hr_dev, 0); |
1970 | if (ret) { | |
1971 | dev_err(hr_dev->dev, | |
1972 | "Set function switch param fail, ret = %d.\n", | |
1973 | ret); | |
1974 | return ret; | |
1975 | } | |
1976 | } | |
3a63c964 LO |
1977 | |
1978 | hr_dev->vendor_part_id = hr_dev->pci_dev->device; | |
1979 | hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid); | |
cfc85f3e | 1980 | |
cfc85f3e WHX |
1981 | caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS; |
1982 | caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS; | |
5c1f167a LO |
1983 | caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS; |
1984 | caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS; | |
cfc85f3e | 1985 | |
80a78570 | 1986 | caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K; |
ff795f71 WHX |
1987 | caps->pbl_buf_pg_sz = 0; |
1988 | caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM; | |
a5073d60 YL |
1989 | caps->eqe_ba_pg_sz = 0; |
1990 | caps->eqe_buf_pg_sz = 0; | |
1991 | caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM; | |
6b63597d | 1992 | caps->tsq_buf_pg_sz = 0; |
aa84fa18 | 1993 | |
80a78570 LO |
1994 | ret = hns_roce_query_pf_caps(hr_dev); |
1995 | if (ret) | |
1996 | set_default_caps(hr_dev); | |
384f8818 | 1997 | |
99e713f8 LO |
1998 | ret = hns_roce_alloc_vf_resource(hr_dev); |
1999 | if (ret) { | |
2000 | dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n", | |
2001 | ret); | |
2002 | return ret; | |
2003 | } | |
2004 | ||
a81fba28 WHX |
2005 | ret = hns_roce_v2_set_bt(hr_dev); |
2006 | if (ret) | |
2007 | dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n", | |
2008 | ret); | |
2009 | ||
2010 | return ret; | |
cfc85f3e WHX |
2011 | } |
2012 | ||
6b63597d | 2013 | static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev, |
2014 | enum hns_roce_link_table_type type) | |
2015 | { | |
2016 | struct hns_roce_cmq_desc desc[2]; | |
2017 | struct hns_roce_cfg_llm_a *req_a = | |
2018 | (struct hns_roce_cfg_llm_a *)desc[0].data; | |
2019 | struct hns_roce_cfg_llm_b *req_b = | |
2020 | (struct hns_roce_cfg_llm_b *)desc[1].data; | |
2021 | struct hns_roce_v2_priv *priv = hr_dev->priv; | |
2022 | struct hns_roce_link_table *link_tbl; | |
2023 | struct hns_roce_link_table_entry *entry; | |
2024 | enum hns_roce_opcode_type opcode; | |
2025 | u32 page_num; | |
2026 | int i; | |
2027 | ||
2028 | switch (type) { | |
2029 | case TSQ_LINK_TABLE: | |
2030 | link_tbl = &priv->tsq; | |
2031 | opcode = HNS_ROCE_OPC_CFG_EXT_LLM; | |
2032 | break; | |
ded58ff9 | 2033 | case TPQ_LINK_TABLE: |
2034 | link_tbl = &priv->tpq; | |
2035 | opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM; | |
2036 | break; | |
6b63597d | 2037 | default: |
2038 | return -EINVAL; | |
2039 | } | |
2040 | ||
2041 | page_num = link_tbl->npages; | |
2042 | entry = link_tbl->table.buf; | |
6b63597d | 2043 | |
2044 | for (i = 0; i < 2; i++) { | |
2045 | hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false); | |
2046 | ||
2047 | if (i == 0) | |
2048 | desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
2049 | else | |
2050 | desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT); | |
6b63597d | 2051 | } |
9976ea27 LO |
2052 | |
2053 | req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff); | |
2054 | req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32); | |
2055 | roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M, | |
2056 | CFG_LLM_QUE_DEPTH_S, link_tbl->npages); | |
2057 | roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M, | |
2058 | CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz); | |
60262b10 LO |
2059 | roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M, |
2060 | CFG_LLM_INIT_EN_S, 1); | |
9976ea27 LO |
2061 | req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0); |
2062 | req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr); | |
2063 | roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S, | |
2064 | 0); | |
2065 | ||
2066 | req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0); | |
2067 | roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M, | |
2068 | CFG_LLM_TAIL_BA_H_S, | |
2069 | entry[page_num - 1].blk_ba1_nxt_ptr & | |
2070 | HNS_ROCE_LINK_TABLE_BA1_M); | |
2071 | roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S, | |
2072 | (entry[page_num - 2].blk_ba1_nxt_ptr & | |
2073 | HNS_ROCE_LINK_TABLE_NXT_PTR_M) >> | |
2074 | HNS_ROCE_LINK_TABLE_NXT_PTR_S); | |
6b63597d | 2075 | |
2076 | return hns_roce_cmq_send(hr_dev, desc, 2); | |
2077 | } | |
2078 | ||
2079 | static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev, | |
2080 | enum hns_roce_link_table_type type) | |
2081 | { | |
2082 | struct hns_roce_v2_priv *priv = hr_dev->priv; | |
2083 | struct hns_roce_link_table *link_tbl; | |
2084 | struct hns_roce_link_table_entry *entry; | |
2085 | struct device *dev = hr_dev->dev; | |
2086 | u32 buf_chk_sz; | |
2087 | dma_addr_t t; | |
ded58ff9 | 2088 | int func_num = 1; |
6b63597d | 2089 | int pg_num_a; |
2090 | int pg_num_b; | |
2091 | int pg_num; | |
2092 | int size; | |
2093 | int i; | |
2094 | ||
2095 | switch (type) { | |
2096 | case TSQ_LINK_TABLE: | |
2097 | link_tbl = &priv->tsq; | |
2098 | buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT); | |
2099 | pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz; | |
2100 | pg_num_b = hr_dev->caps.sl_num * 4 + 2; | |
2101 | break; | |
ded58ff9 | 2102 | case TPQ_LINK_TABLE: |
2103 | link_tbl = &priv->tpq; | |
2104 | buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT); | |
2105 | pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz; | |
2106 | pg_num_b = 2 * 4 * func_num + 2; | |
2107 | break; | |
6b63597d | 2108 | default: |
2109 | return -EINVAL; | |
2110 | } | |
2111 | ||
2112 | pg_num = max(pg_num_a, pg_num_b); | |
2113 | size = pg_num * sizeof(struct hns_roce_link_table_entry); | |
2114 | ||
2115 | link_tbl->table.buf = dma_alloc_coherent(dev, size, | |
2116 | &link_tbl->table.map, | |
2117 | GFP_KERNEL); | |
2118 | if (!link_tbl->table.buf) | |
2119 | goto out; | |
2120 | ||
2121 | link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list), | |
2122 | GFP_KERNEL); | |
2123 | if (!link_tbl->pg_list) | |
2124 | goto err_kcalloc_failed; | |
2125 | ||
2126 | entry = link_tbl->table.buf; | |
2127 | for (i = 0; i < pg_num; ++i) { | |
2128 | link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz, | |
2129 | &t, GFP_KERNEL); | |
2130 | if (!link_tbl->pg_list[i].buf) | |
2131 | goto err_alloc_buf_failed; | |
2132 | ||
2133 | link_tbl->pg_list[i].map = t; | |
6b63597d | 2134 | |
bfe86035 LC |
2135 | entry[i].blk_ba0 = (u32)(t >> 12); |
2136 | entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44); | |
6b63597d | 2137 | |
2138 | if (i < (pg_num - 1)) | |
bfe86035 LC |
2139 | entry[i].blk_ba1_nxt_ptr |= |
2140 | (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S; | |
2141 | ||
6b63597d | 2142 | } |
2143 | link_tbl->npages = pg_num; | |
2144 | link_tbl->pg_sz = buf_chk_sz; | |
2145 | ||
2146 | return hns_roce_config_link_table(hr_dev, type); | |
2147 | ||
2148 | err_alloc_buf_failed: | |
2149 | for (i -= 1; i >= 0; i--) | |
2150 | dma_free_coherent(dev, buf_chk_sz, | |
2151 | link_tbl->pg_list[i].buf, | |
2152 | link_tbl->pg_list[i].map); | |
2153 | kfree(link_tbl->pg_list); | |
2154 | ||
2155 | err_kcalloc_failed: | |
2156 | dma_free_coherent(dev, size, link_tbl->table.buf, | |
2157 | link_tbl->table.map); | |
2158 | ||
2159 | out: | |
2160 | return -ENOMEM; | |
2161 | } | |
2162 | ||
2163 | static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev, | |
2164 | struct hns_roce_link_table *link_tbl) | |
2165 | { | |
2166 | struct device *dev = hr_dev->dev; | |
2167 | int size; | |
2168 | int i; | |
2169 | ||
2170 | size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry); | |
2171 | ||
2172 | for (i = 0; i < link_tbl->npages; ++i) | |
2173 | if (link_tbl->pg_list[i].buf) | |
2174 | dma_free_coherent(dev, link_tbl->pg_sz, | |
2175 | link_tbl->pg_list[i].buf, | |
2176 | link_tbl->pg_list[i].map); | |
2177 | kfree(link_tbl->pg_list); | |
2178 | ||
2179 | dma_free_coherent(dev, size, link_tbl->table.buf, | |
2180 | link_tbl->table.map); | |
2181 | } | |
2182 | ||
2183 | static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) | |
2184 | { | |
ded58ff9 | 2185 | struct hns_roce_v2_priv *priv = hr_dev->priv; |
0e40dc2f YL |
2186 | int qpc_count, cqc_count; |
2187 | int ret, i; | |
6b63597d | 2188 | |
2189 | /* TSQ includes SQ doorbell and ack doorbell */ | |
2190 | ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE); | |
ded58ff9 | 2191 | if (ret) { |
6b63597d | 2192 | dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret); |
ded58ff9 | 2193 | return ret; |
2194 | } | |
2195 | ||
2196 | ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE); | |
2197 | if (ret) { | |
2198 | dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret); | |
2199 | goto err_tpq_init_failed; | |
2200 | } | |
2201 | ||
6def7de6 | 2202 | /* Alloc memory for QPC Timer buffer space chunk */ |
0e40dc2f YL |
2203 | for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num; |
2204 | qpc_count++) { | |
2205 | ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table, | |
2206 | qpc_count); | |
2207 | if (ret) { | |
2208 | dev_err(hr_dev->dev, "QPC Timer get failed\n"); | |
2209 | goto err_qpc_timer_failed; | |
2210 | } | |
2211 | } | |
2212 | ||
6def7de6 | 2213 | /* Alloc memory for CQC Timer buffer space chunk */ |
0e40dc2f YL |
2214 | for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num; |
2215 | cqc_count++) { | |
2216 | ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table, | |
2217 | cqc_count); | |
2218 | if (ret) { | |
2219 | dev_err(hr_dev->dev, "CQC Timer get failed\n"); | |
2220 | goto err_cqc_timer_failed; | |
2221 | } | |
2222 | } | |
2223 | ||
ded58ff9 | 2224 | return 0; |
2225 | ||
0e40dc2f YL |
2226 | err_cqc_timer_failed: |
2227 | for (i = 0; i < cqc_count; i++) | |
2228 | hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i); | |
2229 | ||
2230 | err_qpc_timer_failed: | |
2231 | for (i = 0; i < qpc_count; i++) | |
2232 | hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i); | |
2233 | ||
2234 | hns_roce_free_link_table(hr_dev, &priv->tpq); | |
2235 | ||
ded58ff9 | 2236 | err_tpq_init_failed: |
2237 | hns_roce_free_link_table(hr_dev, &priv->tsq); | |
6b63597d | 2238 | |
2239 | return ret; | |
2240 | } | |
2241 | ||
2242 | static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) | |
2243 | { | |
2244 | struct hns_roce_v2_priv *priv = hr_dev->priv; | |
2245 | ||
dfaf2854 | 2246 | if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) |
89a6da3c LC |
2247 | hns_roce_function_clear(hr_dev); |
2248 | ||
ded58ff9 | 2249 | hns_roce_free_link_table(hr_dev, &priv->tpq); |
6b63597d | 2250 | hns_roce_free_link_table(hr_dev, &priv->tsq); |
2251 | } | |
2252 | ||
f747b689 LO |
2253 | static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev) |
2254 | { | |
2255 | struct hns_roce_cmq_desc desc; | |
2256 | struct hns_roce_mbox_status *mb_st = | |
2257 | (struct hns_roce_mbox_status *)desc.data; | |
2258 | enum hns_roce_cmd_return_status status; | |
2259 | ||
2260 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true); | |
2261 | ||
2262 | status = hns_roce_cmq_send(hr_dev, &desc, 1); | |
2263 | if (status) | |
2264 | return status; | |
2265 | ||
bfe86035 | 2266 | return le32_to_cpu(mb_st->mb_status_hw_run); |
f747b689 LO |
2267 | } |
2268 | ||
a680f2f3 WHX |
2269 | static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev) |
2270 | { | |
f747b689 | 2271 | u32 status = hns_roce_query_mbox_status(hr_dev); |
a680f2f3 WHX |
2272 | |
2273 | return status >> HNS_ROCE_HW_RUN_BIT_SHIFT; | |
2274 | } | |
2275 | ||
2276 | static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev) | |
2277 | { | |
f747b689 | 2278 | u32 status = hns_roce_query_mbox_status(hr_dev); |
a680f2f3 WHX |
2279 | |
2280 | return status & HNS_ROCE_HW_MB_STATUS_MASK; | |
2281 | } | |
2282 | ||
f747b689 LO |
2283 | static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param, |
2284 | u64 out_param, u32 in_modifier, u8 op_modifier, | |
2285 | u16 op, u16 token, int event) | |
2286 | { | |
2287 | struct hns_roce_cmq_desc desc; | |
2288 | struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data; | |
2289 | ||
2290 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false); | |
2291 | ||
bfe86035 LC |
2292 | mb->in_param_l = cpu_to_le32(in_param); |
2293 | mb->in_param_h = cpu_to_le32(in_param >> 32); | |
2294 | mb->out_param_l = cpu_to_le32(out_param); | |
2295 | mb->out_param_h = cpu_to_le32(out_param >> 32); | |
f747b689 LO |
2296 | mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op); |
2297 | mb->token_event_en = cpu_to_le32(event << 16 | token); | |
2298 | ||
2299 | return hns_roce_cmq_send(hr_dev, &desc, 1); | |
2300 | } | |
2301 | ||
a680f2f3 WHX |
2302 | static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, |
2303 | u64 out_param, u32 in_modifier, u8 op_modifier, | |
2304 | u16 op, u16 token, int event) | |
2305 | { | |
2306 | struct device *dev = hr_dev->dev; | |
a680f2f3 | 2307 | unsigned long end; |
f747b689 | 2308 | int ret; |
a680f2f3 WHX |
2309 | |
2310 | end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies; | |
2311 | while (hns_roce_v2_cmd_pending(hr_dev)) { | |
2312 | if (time_after(jiffies, end)) { | |
2313 | dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies, | |
2314 | (int)end); | |
2315 | return -EAGAIN; | |
2316 | } | |
2317 | cond_resched(); | |
2318 | } | |
2319 | ||
f747b689 LO |
2320 | ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier, |
2321 | op_modifier, op, token, event); | |
2322 | if (ret) | |
2323 | dev_err(dev, "Post mailbox fail(%d)\n", ret); | |
a680f2f3 | 2324 | |
f747b689 | 2325 | return ret; |
a680f2f3 WHX |
2326 | } |
2327 | ||
2328 | static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev, | |
2329 | unsigned long timeout) | |
2330 | { | |
2331 | struct device *dev = hr_dev->dev; | |
617cf24f | 2332 | unsigned long end; |
a680f2f3 WHX |
2333 | u32 status; |
2334 | ||
2335 | end = msecs_to_jiffies(timeout) + jiffies; | |
2336 | while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end)) | |
2337 | cond_resched(); | |
2338 | ||
2339 | if (hns_roce_v2_cmd_pending(hr_dev)) { | |
2340 | dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n"); | |
2341 | return -ETIMEDOUT; | |
2342 | } | |
2343 | ||
2344 | status = hns_roce_v2_cmd_complete(hr_dev); | |
2345 | if (status != 0x1) { | |
6a04aed6 WHX |
2346 | if (status == CMD_RST_PRC_EBUSY) |
2347 | return status; | |
2348 | ||
a680f2f3 WHX |
2349 | dev_err(dev, "mailbox status 0x%x!\n", status); |
2350 | return -EBUSY; | |
2351 | } | |
2352 | ||
2353 | return 0; | |
2354 | } | |
2355 | ||
4db134a3 | 2356 | static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev, |
2357 | int gid_index, const union ib_gid *gid, | |
2358 | enum hns_roce_sgid_type sgid_type) | |
2359 | { | |
2360 | struct hns_roce_cmq_desc desc; | |
2361 | struct hns_roce_cfg_sgid_tb *sgid_tb = | |
2362 | (struct hns_roce_cfg_sgid_tb *)desc.data; | |
2363 | u32 *p; | |
2364 | ||
2365 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false); | |
2366 | ||
60262b10 | 2367 | roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M, |
4db134a3 | 2368 | CFG_SGID_TB_TABLE_IDX_S, gid_index); |
60262b10 | 2369 | roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M, |
4db134a3 | 2370 | CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type); |
2371 | ||
2372 | p = (u32 *)&gid->raw[0]; | |
2373 | sgid_tb->vf_sgid_l = cpu_to_le32(*p); | |
2374 | ||
2375 | p = (u32 *)&gid->raw[4]; | |
2376 | sgid_tb->vf_sgid_ml = cpu_to_le32(*p); | |
2377 | ||
2378 | p = (u32 *)&gid->raw[8]; | |
2379 | sgid_tb->vf_sgid_mh = cpu_to_le32(*p); | |
2380 | ||
2381 | p = (u32 *)&gid->raw[0xc]; | |
2382 | sgid_tb->vf_sgid_h = cpu_to_le32(*p); | |
2383 | ||
2384 | return hns_roce_cmq_send(hr_dev, &desc, 1); | |
2385 | } | |
2386 | ||
b5ff0f61 | 2387 | static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port, |
f4df9a7c | 2388 | int gid_index, const union ib_gid *gid, |
b5ff0f61 | 2389 | const struct ib_gid_attr *attr) |
7afddafa | 2390 | { |
b5ff0f61 | 2391 | enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1; |
4db134a3 | 2392 | int ret; |
7afddafa | 2393 | |
b5ff0f61 WHX |
2394 | if (!gid || !attr) |
2395 | return -EINVAL; | |
2396 | ||
2397 | if (attr->gid_type == IB_GID_TYPE_ROCE) | |
2398 | sgid_type = GID_TYPE_FLAG_ROCE_V1; | |
2399 | ||
2400 | if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) { | |
2401 | if (ipv6_addr_v4mapped((void *)gid)) | |
2402 | sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4; | |
2403 | else | |
2404 | sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6; | |
2405 | } | |
2406 | ||
4db134a3 | 2407 | ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type); |
2408 | if (ret) | |
ae1c6148 LO |
2409 | ibdev_err(&hr_dev->ib_dev, |
2410 | "failed to configure sgid table, ret = %d!\n", | |
2411 | ret); | |
b5ff0f61 | 2412 | |
4db134a3 | 2413 | return ret; |
7afddafa WHX |
2414 | } |
2415 | ||
a74dc41d WHX |
2416 | static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, |
2417 | u8 *addr) | |
7afddafa | 2418 | { |
e8e8b652 | 2419 | struct hns_roce_cmq_desc desc; |
2420 | struct hns_roce_cfg_smac_tb *smac_tb = | |
2421 | (struct hns_roce_cfg_smac_tb *)desc.data; | |
7afddafa WHX |
2422 | u16 reg_smac_h; |
2423 | u32 reg_smac_l; | |
e8e8b652 | 2424 | |
2425 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false); | |
7afddafa WHX |
2426 | |
2427 | reg_smac_l = *(u32 *)(&addr[0]); | |
e8e8b652 | 2428 | reg_smac_h = *(u16 *)(&addr[4]); |
7afddafa | 2429 | |
375898e8 | 2430 | roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M, |
e8e8b652 | 2431 | CFG_SMAC_TB_IDX_S, phy_port); |
375898e8 | 2432 | roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M, |
e8e8b652 | 2433 | CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h); |
bfe86035 | 2434 | smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l); |
a74dc41d | 2435 | |
e8e8b652 | 2436 | return hns_roce_cmq_send(hr_dev, &desc, 1); |
7afddafa WHX |
2437 | } |
2438 | ||
ca088320 YL |
2439 | static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry, |
2440 | struct hns_roce_mr *mr) | |
3958cc56 | 2441 | { |
3856ec55 | 2442 | struct sg_dma_page_iter sg_iter; |
db270c41 | 2443 | u64 page_addr; |
3958cc56 | 2444 | u64 *pages; |
3856ec55 | 2445 | int i; |
3958cc56 | 2446 | |
ca088320 YL |
2447 | mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); |
2448 | mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); | |
2449 | roce_set_field(mpt_entry->byte_48_mode_ba, | |
2450 | V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S, | |
2451 | upper_32_bits(mr->pbl_ba >> 3)); | |
2452 | ||
2453 | pages = (u64 *)__get_free_page(GFP_KERNEL); | |
2454 | if (!pages) | |
2455 | return -ENOMEM; | |
2456 | ||
2457 | i = 0; | |
3856ec55 SS |
2458 | for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) { |
2459 | page_addr = sg_page_iter_dma_address(&sg_iter); | |
2460 | pages[i] = page_addr >> 6; | |
2461 | ||
2462 | /* Record the first 2 entry directly to MTPT table */ | |
2463 | if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1) | |
2464 | goto found; | |
2465 | i++; | |
ca088320 YL |
2466 | } |
2467 | found: | |
2468 | mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0])); | |
2469 | roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M, | |
2470 | V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0])); | |
2471 | ||
2472 | mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1])); | |
2473 | roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M, | |
2474 | V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1])); | |
2475 | roce_set_field(mpt_entry->byte_64_buf_pa1, | |
2476 | V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, | |
2477 | V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, | |
2478 | mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET); | |
2479 | ||
2480 | free_page((unsigned long)pages); | |
2481 | ||
2482 | return 0; | |
2483 | } | |
2484 | ||
2485 | static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, | |
2486 | unsigned long mtpt_idx) | |
2487 | { | |
2488 | struct hns_roce_v2_mpt_entry *mpt_entry; | |
2489 | int ret; | |
2490 | ||
3958cc56 WHX |
2491 | mpt_entry = mb_buf; |
2492 | memset(mpt_entry, 0, sizeof(*mpt_entry)); | |
2493 | ||
2494 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, | |
2495 | V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); | |
2496 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, | |
2497 | V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num == | |
2498 | HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num); | |
2499 | roce_set_field(mpt_entry->byte_4_pd_hop_st, | |
2500 | V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, | |
5e6e78db YL |
2501 | V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, |
2502 | mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET); | |
3958cc56 WHX |
2503 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, |
2504 | V2_MPT_BYTE_4_PD_S, mr->pd); | |
3958cc56 WHX |
2505 | |
2506 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0); | |
82342e49 | 2507 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0); |
e93df010 | 2508 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); |
3958cc56 WHX |
2509 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S, |
2510 | (mr->access & IB_ACCESS_MW_BIND ? 1 : 0)); | |
384f8818 LO |
2511 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, |
2512 | mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); | |
3958cc56 WHX |
2513 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, |
2514 | (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0)); | |
2515 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, | |
2516 | (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0)); | |
2517 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, | |
2518 | (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0)); | |
3958cc56 WHX |
2519 | |
2520 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, | |
2521 | mr->type == MR_TYPE_MR ? 0 : 1); | |
85e0274d | 2522 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S, |
2523 | 1); | |
3958cc56 WHX |
2524 | |
2525 | mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size)); | |
2526 | mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size)); | |
2527 | mpt_entry->lkey = cpu_to_le32(mr->key); | |
2528 | mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova)); | |
2529 | mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova)); | |
2530 | ||
2531 | if (mr->type == MR_TYPE_DMA) | |
2532 | return 0; | |
2533 | ||
ca088320 | 2534 | ret = set_mtpt_pbl(mpt_entry, mr); |
3958cc56 | 2535 | |
ca088320 | 2536 | return ret; |
3958cc56 WHX |
2537 | } |
2538 | ||
a2c80b7b WHX |
2539 | static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, |
2540 | struct hns_roce_mr *mr, int flags, | |
2541 | u32 pdn, int mr_access_flags, u64 iova, | |
2542 | u64 size, void *mb_buf) | |
2543 | { | |
2544 | struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf; | |
ca088320 | 2545 | int ret = 0; |
a2c80b7b | 2546 | |
ab22bf05 YL |
2547 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, |
2548 | V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID); | |
2549 | ||
a2c80b7b WHX |
2550 | if (flags & IB_MR_REREG_PD) { |
2551 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, | |
2552 | V2_MPT_BYTE_4_PD_S, pdn); | |
2553 | mr->pd = pdn; | |
2554 | } | |
2555 | ||
2556 | if (flags & IB_MR_REREG_ACCESS) { | |
2557 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, | |
2558 | V2_MPT_BYTE_8_BIND_EN_S, | |
2559 | (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0)); | |
2560 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, | |
ca088320 YL |
2561 | V2_MPT_BYTE_8_ATOMIC_EN_S, |
2562 | mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0); | |
a2c80b7b | 2563 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S, |
ca088320 | 2564 | mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0); |
a2c80b7b | 2565 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S, |
ca088320 | 2566 | mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0); |
a2c80b7b | 2567 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S, |
ca088320 | 2568 | mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0); |
a2c80b7b WHX |
2569 | } |
2570 | ||
2571 | if (flags & IB_MR_REREG_TRANS) { | |
2572 | mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova)); | |
2573 | mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova)); | |
2574 | mpt_entry->len_l = cpu_to_le32(lower_32_bits(size)); | |
2575 | mpt_entry->len_h = cpu_to_le32(upper_32_bits(size)); | |
2576 | ||
a2c80b7b WHX |
2577 | mr->iova = iova; |
2578 | mr->size = size; | |
ca088320 YL |
2579 | |
2580 | ret = set_mtpt_pbl(mpt_entry, mr); | |
a2c80b7b WHX |
2581 | } |
2582 | ||
ca088320 | 2583 | return ret; |
a2c80b7b WHX |
2584 | } |
2585 | ||
68a997c5 YL |
2586 | static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) |
2587 | { | |
2588 | struct hns_roce_v2_mpt_entry *mpt_entry; | |
2589 | ||
2590 | mpt_entry = mb_buf; | |
2591 | memset(mpt_entry, 0, sizeof(*mpt_entry)); | |
2592 | ||
2593 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, | |
2594 | V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); | |
2595 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, | |
2596 | V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1); | |
2597 | roce_set_field(mpt_entry->byte_4_pd_hop_st, | |
2598 | V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, | |
2599 | V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, | |
2600 | mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET); | |
2601 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, | |
2602 | V2_MPT_BYTE_4_PD_S, mr->pd); | |
2603 | ||
2604 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1); | |
2605 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); | |
2606 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); | |
2607 | ||
2608 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1); | |
2609 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); | |
2610 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0); | |
2611 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); | |
2612 | ||
2613 | mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size); | |
2614 | ||
2615 | mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3)); | |
2616 | roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M, | |
2617 | V2_MPT_BYTE_48_PBL_BA_H_S, | |
2618 | upper_32_bits(mr->pbl_ba >> 3)); | |
2619 | ||
2620 | roce_set_field(mpt_entry->byte_64_buf_pa1, | |
2621 | V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, | |
2622 | V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, | |
2623 | mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET); | |
2624 | ||
2625 | return 0; | |
2626 | } | |
2627 | ||
c7c28191 YL |
2628 | static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) |
2629 | { | |
2630 | struct hns_roce_v2_mpt_entry *mpt_entry; | |
2631 | ||
2632 | mpt_entry = mb_buf; | |
2633 | memset(mpt_entry, 0, sizeof(*mpt_entry)); | |
2634 | ||
2635 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M, | |
2636 | V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE); | |
2637 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M, | |
2638 | V2_MPT_BYTE_4_PD_S, mw->pdn); | |
60262b10 | 2639 | roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M, |
c7c28191 | 2640 | V2_MPT_BYTE_4_PBL_HOP_NUM_S, |
60262b10 LO |
2641 | mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : |
2642 | mw->pbl_hop_num); | |
c7c28191 YL |
2643 | roce_set_field(mpt_entry->byte_4_pd_hop_st, |
2644 | V2_MPT_BYTE_4_PBL_BA_PG_SZ_M, | |
2645 | V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, | |
2646 | mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET); | |
2647 | ||
2648 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1); | |
2649 | roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1); | |
2650 | ||
2651 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0); | |
2652 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1); | |
2653 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1); | |
2654 | roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S, | |
2655 | mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1); | |
2656 | ||
2657 | roce_set_field(mpt_entry->byte_64_buf_pa1, | |
2658 | V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M, | |
2659 | V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, | |
2660 | mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET); | |
2661 | ||
2662 | mpt_entry->lkey = cpu_to_le32(mw->rkey); | |
2663 | ||
2664 | return 0; | |
2665 | } | |
2666 | ||
93aa2187 WHX |
2667 | static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) |
2668 | { | |
744b7bdf XW |
2669 | return hns_roce_buf_offset(hr_cq->mtr.kmem, |
2670 | n * HNS_ROCE_V2_CQE_ENTRY_SIZE); | |
93aa2187 WHX |
2671 | } |
2672 | ||
2673 | static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n) | |
2674 | { | |
2675 | struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe); | |
2676 | ||
2677 | /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */ | |
2678 | return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^ | |
e2b2744a | 2679 | !!(n & hr_cq->cq_depth)) ? cqe : NULL; |
93aa2187 WHX |
2680 | } |
2681 | ||
2682 | static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq) | |
2683 | { | |
2684 | return get_sw_cqe_v2(hr_cq, hr_cq->cons_index); | |
2685 | } | |
2686 | ||
c7bcb134 LO |
2687 | static void *get_srq_wqe(struct hns_roce_srq *srq, int n) |
2688 | { | |
6fd610c5 | 2689 | return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift); |
c7bcb134 LO |
2690 | } |
2691 | ||
2692 | static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index) | |
2693 | { | |
c7bcb134 LO |
2694 | /* always called with interrupts disabled. */ |
2695 | spin_lock(&srq->lock); | |
2696 | ||
97545b10 | 2697 | bitmap_clear(srq->idx_que.bitmap, wqe_index, 1); |
c7bcb134 LO |
2698 | srq->tail++; |
2699 | ||
2700 | spin_unlock(&srq->lock); | |
2701 | } | |
2702 | ||
93aa2187 WHX |
2703 | static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) |
2704 | { | |
b14c95be | 2705 | *hr_cq->set_ci_db = cons_index & V2_CQ_DB_PARAMETER_CONS_IDX_M; |
93aa2187 WHX |
2706 | } |
2707 | ||
926a01dc WHX |
2708 | static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, |
2709 | struct hns_roce_srq *srq) | |
2710 | { | |
2711 | struct hns_roce_v2_cqe *cqe, *dest; | |
2712 | u32 prod_index; | |
2713 | int nfreed = 0; | |
c7bcb134 | 2714 | int wqe_index; |
926a01dc WHX |
2715 | u8 owner_bit; |
2716 | ||
2717 | for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index); | |
2718 | ++prod_index) { | |
d7e5ca88 | 2719 | if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe) |
926a01dc WHX |
2720 | break; |
2721 | } | |
2722 | ||
2723 | /* | |
2724 | * Now backwards through the CQ, removing CQ entries | |
2725 | * that match our QP by overwriting them with next entries. | |
2726 | */ | |
2727 | while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { | |
2728 | cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe); | |
2729 | if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, | |
2730 | V2_CQE_BYTE_16_LCL_QPN_S) & | |
2731 | HNS_ROCE_V2_CQE_QPN_MASK) == qpn) { | |
c7bcb134 LO |
2732 | if (srq && |
2733 | roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) { | |
2734 | wqe_index = roce_get_field(cqe->byte_4, | |
2735 | V2_CQE_BYTE_4_WQE_INDX_M, | |
2736 | V2_CQE_BYTE_4_WQE_INDX_S); | |
2737 | hns_roce_free_srq_wqe(srq, wqe_index); | |
2738 | } | |
926a01dc WHX |
2739 | ++nfreed; |
2740 | } else if (nfreed) { | |
2741 | dest = get_cqe_v2(hr_cq, (prod_index + nfreed) & | |
2742 | hr_cq->ib_cq.cqe); | |
2743 | owner_bit = roce_get_bit(dest->byte_4, | |
2744 | V2_CQE_BYTE_4_OWNER_S); | |
2745 | memcpy(dest, cqe, sizeof(*cqe)); | |
2746 | roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S, | |
2747 | owner_bit); | |
2748 | } | |
2749 | } | |
2750 | ||
2751 | if (nfreed) { | |
2752 | hr_cq->cons_index += nfreed; | |
2753 | /* | |
2754 | * Make sure update of buffer contents is done before | |
2755 | * updating consumer index. | |
2756 | */ | |
2757 | wmb(); | |
2758 | hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); | |
2759 | } | |
2760 | } | |
2761 | ||
2762 | static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, | |
2763 | struct hns_roce_srq *srq) | |
2764 | { | |
2765 | spin_lock_irq(&hr_cq->lock); | |
2766 | __hns_roce_v2_cq_clean(hr_cq, qpn, srq); | |
2767 | spin_unlock_irq(&hr_cq->lock); | |
2768 | } | |
2769 | ||
93aa2187 WHX |
2770 | static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, |
2771 | struct hns_roce_cq *hr_cq, void *mb_buf, | |
e2b2744a | 2772 | u64 *mtts, dma_addr_t dma_handle) |
93aa2187 WHX |
2773 | { |
2774 | struct hns_roce_v2_cq_context *cq_context; | |
2775 | ||
2776 | cq_context = mb_buf; | |
2777 | memset(cq_context, 0, sizeof(*cq_context)); | |
2778 | ||
2779 | roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M, | |
2780 | V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID); | |
a5073d60 YL |
2781 | roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M, |
2782 | V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE); | |
93aa2187 | 2783 | roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M, |
60262b10 | 2784 | V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth)); |
93aa2187 | 2785 | roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M, |
e2b2744a | 2786 | V2_CQC_BYTE_4_CEQN_S, hr_cq->vector); |
93aa2187 WHX |
2787 | |
2788 | roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M, | |
2789 | V2_CQC_BYTE_8_CQN_S, hr_cq->cqn); | |
2790 | ||
744b7bdf | 2791 | cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); |
93aa2187 WHX |
2792 | |
2793 | roce_set_field(cq_context->byte_16_hop_addr, | |
2794 | V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M, | |
2795 | V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S, | |
744b7bdf | 2796 | upper_32_bits(to_hr_hw_page_addr(mtts[0]))); |
93aa2187 WHX |
2797 | roce_set_field(cq_context->byte_16_hop_addr, |
2798 | V2_CQC_BYTE_16_CQE_HOP_NUM_M, | |
2799 | V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num == | |
2800 | HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num); | |
2801 | ||
744b7bdf | 2802 | cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); |
93aa2187 WHX |
2803 | roce_set_field(cq_context->byte_24_pgsz_addr, |
2804 | V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M, | |
2805 | V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S, | |
744b7bdf | 2806 | upper_32_bits(to_hr_hw_page_addr(mtts[1]))); |
93aa2187 WHX |
2807 | roce_set_field(cq_context->byte_24_pgsz_addr, |
2808 | V2_CQC_BYTE_24_CQE_BA_PG_SZ_M, | |
2809 | V2_CQC_BYTE_24_CQE_BA_PG_SZ_S, | |
744b7bdf | 2810 | to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift)); |
93aa2187 WHX |
2811 | roce_set_field(cq_context->byte_24_pgsz_addr, |
2812 | V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M, | |
2813 | V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S, | |
744b7bdf | 2814 | to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift)); |
93aa2187 | 2815 | |
bfe86035 | 2816 | cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3); |
93aa2187 WHX |
2817 | |
2818 | roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M, | |
2819 | V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3))); | |
a5073d60 | 2820 | |
9b44703d YL |
2821 | if (hr_cq->db_en) |
2822 | roce_set_bit(cq_context->byte_44_db_record, | |
2823 | V2_CQC_BYTE_44_DB_RECORD_EN_S, 1); | |
2824 | ||
2825 | roce_set_field(cq_context->byte_44_db_record, | |
2826 | V2_CQC_BYTE_44_DB_RECORD_ADDR_M, | |
2827 | V2_CQC_BYTE_44_DB_RECORD_ADDR_S, | |
2828 | ((u32)hr_cq->db.dma) >> 1); | |
bfe86035 | 2829 | cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32); |
9b44703d | 2830 | |
a5073d60 YL |
2831 | roce_set_field(cq_context->byte_56_cqe_period_maxcnt, |
2832 | V2_CQC_BYTE_56_CQ_MAX_CNT_M, | |
2833 | V2_CQC_BYTE_56_CQ_MAX_CNT_S, | |
2834 | HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM); | |
2835 | roce_set_field(cq_context->byte_56_cqe_period_maxcnt, | |
2836 | V2_CQC_BYTE_56_CQ_PERIOD_M, | |
2837 | V2_CQC_BYTE_56_CQ_PERIOD_S, | |
2838 | HNS_ROCE_V2_CQ_DEFAULT_INTERVAL); | |
93aa2187 WHX |
2839 | } |
2840 | ||
2841 | static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, | |
2842 | enum ib_cq_notify_flags flags) | |
2843 | { | |
d3743fa9 | 2844 | struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); |
93aa2187 WHX |
2845 | struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); |
2846 | u32 notification_flag; | |
bfe86035 | 2847 | __le32 doorbell[2]; |
93aa2187 WHX |
2848 | |
2849 | doorbell[0] = 0; | |
2850 | doorbell[1] = 0; | |
2851 | ||
2852 | notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? | |
2853 | V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL; | |
2854 | /* | |
2855 | * flags = 0; Notification Flag = 1, next | |
2856 | * flags = 1; Notification Flag = 0, solocited | |
2857 | */ | |
2858 | roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S, | |
2859 | hr_cq->cqn); | |
2860 | roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, | |
2861 | HNS_ROCE_V2_CQ_DB_NTR); | |
2862 | roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M, | |
2863 | V2_CQ_DB_PARAMETER_CONS_IDX_S, | |
2864 | hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1)); | |
2865 | roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M, | |
26beb85f | 2866 | V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3); |
93aa2187 WHX |
2867 | roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S, |
2868 | notification_flag); | |
2869 | ||
d3743fa9 | 2870 | hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l); |
93aa2187 WHX |
2871 | |
2872 | return 0; | |
2873 | } | |
2874 | ||
0009c2db | 2875 | static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe, |
2876 | struct hns_roce_qp **cur_qp, | |
2877 | struct ib_wc *wc) | |
2878 | { | |
2879 | struct hns_roce_rinl_sge *sge_list; | |
2880 | u32 wr_num, wr_cnt, sge_num; | |
2881 | u32 sge_cnt, data_len, size; | |
2882 | void *wqe_buf; | |
2883 | ||
2884 | wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M, | |
2885 | V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff; | |
2886 | wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1); | |
2887 | ||
2888 | sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list; | |
2889 | sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt; | |
6c6e3921 | 2890 | wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt); |
0009c2db | 2891 | data_len = wc->byte_len; |
2892 | ||
2893 | for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) { | |
2894 | size = min(sge_list[sge_cnt].len, data_len); | |
2895 | memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size); | |
2896 | ||
2897 | data_len -= size; | |
2898 | wqe_buf += size; | |
2899 | } | |
2900 | ||
2901 | if (data_len) { | |
2902 | wc->status = IB_WC_LOC_LEN_ERR; | |
2903 | return -EAGAIN; | |
2904 | } | |
2905 | ||
2906 | return 0; | |
2907 | } | |
2908 | ||
626903e9 XW |
2909 | static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, |
2910 | int num_entries, struct ib_wc *wc) | |
2911 | { | |
2912 | unsigned int left; | |
2913 | int npolled = 0; | |
2914 | ||
2915 | left = wq->head - wq->tail; | |
2916 | if (left == 0) | |
2917 | return 0; | |
2918 | ||
2919 | left = min_t(unsigned int, (unsigned int)num_entries, left); | |
2920 | while (npolled < left) { | |
2921 | wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; | |
2922 | wc->status = IB_WC_WR_FLUSH_ERR; | |
2923 | wc->vendor_err = 0; | |
2924 | wc->qp = &hr_qp->ibqp; | |
2925 | ||
2926 | wq->tail++; | |
2927 | wc++; | |
2928 | npolled++; | |
2929 | } | |
2930 | ||
2931 | return npolled; | |
2932 | } | |
2933 | ||
2934 | static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, | |
2935 | struct ib_wc *wc) | |
2936 | { | |
2937 | struct hns_roce_qp *hr_qp; | |
2938 | int npolled = 0; | |
2939 | ||
2940 | list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) { | |
2941 | npolled += sw_comp(hr_qp, &hr_qp->sq, | |
2942 | num_entries - npolled, wc + npolled); | |
2943 | if (npolled >= num_entries) | |
2944 | goto out; | |
2945 | } | |
2946 | ||
2947 | list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) { | |
2948 | npolled += sw_comp(hr_qp, &hr_qp->rq, | |
2949 | num_entries - npolled, wc + npolled); | |
2950 | if (npolled >= num_entries) | |
2951 | goto out; | |
2952 | } | |
2953 | ||
2954 | out: | |
2955 | return npolled; | |
2956 | } | |
2957 | ||
7c044adc LC |
2958 | static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, |
2959 | struct hns_roce_v2_cqe *cqe, struct ib_wc *wc) | |
2960 | { | |
2961 | static const struct { | |
2962 | u32 cqe_status; | |
2963 | enum ib_wc_status wc_status; | |
2964 | } map[] = { | |
2965 | { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS }, | |
2966 | { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR }, | |
2967 | { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR }, | |
2968 | { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR }, | |
2969 | { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR }, | |
2970 | { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR }, | |
2971 | { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR }, | |
2972 | { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR }, | |
2973 | { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR }, | |
2974 | { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR }, | |
2975 | { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR }, | |
2976 | { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR, | |
2977 | IB_WC_RETRY_EXC_ERR }, | |
2978 | { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR }, | |
2979 | { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR }, | |
2980 | }; | |
2981 | ||
2982 | u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M, | |
2983 | V2_CQE_BYTE_4_STATUS_S); | |
2984 | int i; | |
2985 | ||
2986 | wc->status = IB_WC_GENERAL_ERR; | |
2987 | for (i = 0; i < ARRAY_SIZE(map); i++) | |
2988 | if (cqe_status == map[i].cqe_status) { | |
2989 | wc->status = map[i].wc_status; | |
2990 | break; | |
2991 | } | |
2992 | ||
2993 | if (wc->status == IB_WC_SUCCESS || wc->status == IB_WC_WR_FLUSH_ERR) | |
2994 | return; | |
2995 | ||
2996 | ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status); | |
2997 | print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe, | |
2998 | sizeof(*cqe), false); | |
2999 | ||
3000 | /* | |
3001 | * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets | |
3002 | * into errored mode. Hence, as a workaround to this hardware | |
3003 | * limitation, driver needs to assist in flushing. But the flushing | |
3004 | * operation uses mailbox to convey the QP state to the hardware and | |
3005 | * which can sleep due to the mutex protection around the mailbox calls. | |
3006 | * Hence, use the deferred flush for now. Once wc error detected, the | |
3007 | * flushing operation is needed. | |
3008 | */ | |
3009 | if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) | |
3010 | init_flush_work(hr_dev, qp); | |
3011 | } | |
3012 | ||
93aa2187 WHX |
3013 | static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, |
3014 | struct hns_roce_qp **cur_qp, struct ib_wc *wc) | |
3015 | { | |
b5374286 | 3016 | struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device); |
c7bcb134 | 3017 | struct hns_roce_srq *srq = NULL; |
93aa2187 WHX |
3018 | struct hns_roce_v2_cqe *cqe; |
3019 | struct hns_roce_qp *hr_qp; | |
3020 | struct hns_roce_wq *wq; | |
3021 | int is_send; | |
3022 | u16 wqe_ctr; | |
3023 | u32 opcode; | |
93aa2187 | 3024 | int qpn; |
0009c2db | 3025 | int ret; |
93aa2187 WHX |
3026 | |
3027 | /* Find cqe according to consumer index */ | |
3028 | cqe = next_cqe_sw_v2(hr_cq); | |
3029 | if (!cqe) | |
3030 | return -EAGAIN; | |
3031 | ||
3032 | ++hr_cq->cons_index; | |
3033 | /* Memory barrier */ | |
3034 | rmb(); | |
3035 | ||
3036 | /* 0->SQ, 1->RQ */ | |
3037 | is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S); | |
3038 | ||
3039 | qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M, | |
3040 | V2_CQE_BYTE_16_LCL_QPN_S); | |
3041 | ||
3042 | if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) { | |
93aa2187 WHX |
3043 | hr_qp = __hns_roce_qp_lookup(hr_dev, qpn); |
3044 | if (unlikely(!hr_qp)) { | |
ae1c6148 LO |
3045 | ibdev_err(&hr_dev->ib_dev, |
3046 | "CQ %06lx with entry for unknown QPN %06x\n", | |
3047 | hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK); | |
93aa2187 WHX |
3048 | return -EINVAL; |
3049 | } | |
3050 | *cur_qp = hr_qp; | |
3051 | } | |
3052 | ||
3053 | wc->qp = &(*cur_qp)->ibqp; | |
3054 | wc->vendor_err = 0; | |
3055 | ||
c7bcb134 LO |
3056 | if (is_send) { |
3057 | wq = &(*cur_qp)->sq; | |
3058 | if ((*cur_qp)->sq_signal_bits) { | |
3059 | /* | |
3060 | * If sg_signal_bit is 1, | |
3061 | * firstly tail pointer updated to wqe | |
3062 | * which current cqe correspond to | |
3063 | */ | |
3064 | wqe_ctr = (u16)roce_get_field(cqe->byte_4, | |
3065 | V2_CQE_BYTE_4_WQE_INDX_M, | |
3066 | V2_CQE_BYTE_4_WQE_INDX_S); | |
3067 | wq->tail += (wqe_ctr - (u16)wq->tail) & | |
3068 | (wq->wqe_cnt - 1); | |
3069 | } | |
3070 | ||
3071 | wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; | |
3072 | ++wq->tail; | |
3073 | } else if ((*cur_qp)->ibqp.srq) { | |
3074 | srq = to_hr_srq((*cur_qp)->ibqp.srq); | |
bfe86035 LC |
3075 | wqe_ctr = (u16)roce_get_field(cqe->byte_4, |
3076 | V2_CQE_BYTE_4_WQE_INDX_M, | |
3077 | V2_CQE_BYTE_4_WQE_INDX_S); | |
c7bcb134 LO |
3078 | wc->wr_id = srq->wrid[wqe_ctr]; |
3079 | hns_roce_free_srq_wqe(srq, wqe_ctr); | |
3080 | } else { | |
3081 | /* Update tail pointer, record wr_id */ | |
3082 | wq = &(*cur_qp)->rq; | |
3083 | wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)]; | |
3084 | ++wq->tail; | |
3085 | } | |
3086 | ||
7c044adc LC |
3087 | get_cqe_status(hr_dev, *cur_qp, cqe, wc); |
3088 | if (wc->status != IB_WC_SUCCESS) | |
93aa2187 WHX |
3089 | return 0; |
3090 | ||
3091 | if (is_send) { | |
3092 | wc->wc_flags = 0; | |
3093 | /* SQ corresponding to CQE */ | |
3094 | switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, | |
3095 | V2_CQE_BYTE_4_OPCODE_S) & 0x1f) { | |
3096 | case HNS_ROCE_SQ_OPCODE_SEND: | |
3097 | wc->opcode = IB_WC_SEND; | |
3098 | break; | |
3099 | case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV: | |
3100 | wc->opcode = IB_WC_SEND; | |
3101 | break; | |
3102 | case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM: | |
3103 | wc->opcode = IB_WC_SEND; | |
3104 | wc->wc_flags |= IB_WC_WITH_IMM; | |
3105 | break; | |
3106 | case HNS_ROCE_SQ_OPCODE_RDMA_READ: | |
3107 | wc->opcode = IB_WC_RDMA_READ; | |
3108 | wc->byte_len = le32_to_cpu(cqe->byte_cnt); | |
3109 | break; | |
3110 | case HNS_ROCE_SQ_OPCODE_RDMA_WRITE: | |
3111 | wc->opcode = IB_WC_RDMA_WRITE; | |
3112 | break; | |
3113 | case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM: | |
3114 | wc->opcode = IB_WC_RDMA_WRITE; | |
3115 | wc->wc_flags |= IB_WC_WITH_IMM; | |
3116 | break; | |
3117 | case HNS_ROCE_SQ_OPCODE_LOCAL_INV: | |
3118 | wc->opcode = IB_WC_LOCAL_INV; | |
3119 | wc->wc_flags |= IB_WC_WITH_INVALIDATE; | |
3120 | break; | |
3121 | case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP: | |
3122 | wc->opcode = IB_WC_COMP_SWAP; | |
3123 | wc->byte_len = 8; | |
3124 | break; | |
3125 | case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD: | |
3126 | wc->opcode = IB_WC_FETCH_ADD; | |
3127 | wc->byte_len = 8; | |
3128 | break; | |
3129 | case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP: | |
3130 | wc->opcode = IB_WC_MASKED_COMP_SWAP; | |
3131 | wc->byte_len = 8; | |
3132 | break; | |
3133 | case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD: | |
3134 | wc->opcode = IB_WC_MASKED_FETCH_ADD; | |
3135 | wc->byte_len = 8; | |
3136 | break; | |
3137 | case HNS_ROCE_SQ_OPCODE_FAST_REG_WR: | |
3138 | wc->opcode = IB_WC_REG_MR; | |
3139 | break; | |
3140 | case HNS_ROCE_SQ_OPCODE_BIND_MW: | |
3141 | wc->opcode = IB_WC_REG_MR; | |
3142 | break; | |
3143 | default: | |
3144 | wc->status = IB_WC_GENERAL_ERR; | |
3145 | break; | |
3146 | } | |
93aa2187 WHX |
3147 | } else { |
3148 | /* RQ correspond to CQE */ | |
3149 | wc->byte_len = le32_to_cpu(cqe->byte_cnt); | |
3150 | ||
3151 | opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M, | |
3152 | V2_CQE_BYTE_4_OPCODE_S); | |
3153 | switch (opcode & 0x1f) { | |
3154 | case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM: | |
3155 | wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; | |
3156 | wc->wc_flags = IB_WC_WITH_IMM; | |
0c4a0e29 LO |
3157 | wc->ex.imm_data = |
3158 | cpu_to_be32(le32_to_cpu(cqe->immtdata)); | |
93aa2187 WHX |
3159 | break; |
3160 | case HNS_ROCE_V2_OPCODE_SEND: | |
3161 | wc->opcode = IB_WC_RECV; | |
3162 | wc->wc_flags = 0; | |
3163 | break; | |
3164 | case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM: | |
3165 | wc->opcode = IB_WC_RECV; | |
3166 | wc->wc_flags = IB_WC_WITH_IMM; | |
0c4a0e29 LO |
3167 | wc->ex.imm_data = |
3168 | cpu_to_be32(le32_to_cpu(cqe->immtdata)); | |
93aa2187 WHX |
3169 | break; |
3170 | case HNS_ROCE_V2_OPCODE_SEND_WITH_INV: | |
3171 | wc->opcode = IB_WC_RECV; | |
3172 | wc->wc_flags = IB_WC_WITH_INVALIDATE; | |
ccb8a29e | 3173 | wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey); |
93aa2187 WHX |
3174 | break; |
3175 | default: | |
3176 | wc->status = IB_WC_GENERAL_ERR; | |
3177 | break; | |
3178 | } | |
3179 | ||
0009c2db | 3180 | if ((wc->qp->qp_type == IB_QPT_RC || |
3181 | wc->qp->qp_type == IB_QPT_UC) && | |
3182 | (opcode == HNS_ROCE_V2_OPCODE_SEND || | |
3183 | opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM || | |
3184 | opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) && | |
3185 | (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) { | |
3186 | ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc); | |
3187 | if (ret) | |
3188 | return -EAGAIN; | |
3189 | } | |
3190 | ||
93aa2187 WHX |
3191 | wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M, |
3192 | V2_CQE_BYTE_32_SL_S); | |
3193 | wc->src_qp = (u8)roce_get_field(cqe->byte_32, | |
3194 | V2_CQE_BYTE_32_RMT_QPN_M, | |
3195 | V2_CQE_BYTE_32_RMT_QPN_S); | |
15fc056f | 3196 | wc->slid = 0; |
93aa2187 WHX |
3197 | wc->wc_flags |= (roce_get_bit(cqe->byte_32, |
3198 | V2_CQE_BYTE_32_GRH_S) ? | |
3199 | IB_WC_GRH : 0); | |
6c1f08b3 | 3200 | wc->port_num = roce_get_field(cqe->byte_32, |
3201 | V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S); | |
3202 | wc->pkey_index = 0; | |
cd4a70bb | 3203 | |
944e6409 LO |
3204 | if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) { |
3205 | wc->vlan_id = (u16)roce_get_field(cqe->byte_28, | |
3206 | V2_CQE_BYTE_28_VID_M, | |
3207 | V2_CQE_BYTE_28_VID_S); | |
0e1aa6f0 | 3208 | wc->wc_flags |= IB_WC_WITH_VLAN; |
944e6409 LO |
3209 | } else { |
3210 | wc->vlan_id = 0xffff; | |
3211 | } | |
3212 | ||
2eade675 | 3213 | wc->network_hdr_type = roce_get_field(cqe->byte_28, |
3214 | V2_CQE_BYTE_28_PORT_TYPE_M, | |
3215 | V2_CQE_BYTE_28_PORT_TYPE_S); | |
93aa2187 WHX |
3216 | } |
3217 | ||
3218 | return 0; | |
3219 | } | |
3220 | ||
3221 | static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, | |
3222 | struct ib_wc *wc) | |
3223 | { | |
626903e9 | 3224 | struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device); |
93aa2187 WHX |
3225 | struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); |
3226 | struct hns_roce_qp *cur_qp = NULL; | |
3227 | unsigned long flags; | |
3228 | int npolled; | |
3229 | ||
3230 | spin_lock_irqsave(&hr_cq->lock, flags); | |
3231 | ||
626903e9 XW |
3232 | /* |
3233 | * When the device starts to reset, the state is RST_DOWN. At this time, | |
3234 | * there may still be some valid CQEs in the hardware that are not | |
3235 | * polled. Therefore, it is not allowed to switch to the software mode | |
3236 | * immediately. When the state changes to UNINIT, CQE no longer exists | |
3237 | * in the hardware, and then switch to software mode. | |
3238 | */ | |
3239 | if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) { | |
3240 | npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc); | |
3241 | goto out; | |
3242 | } | |
3243 | ||
93aa2187 WHX |
3244 | for (npolled = 0; npolled < num_entries; ++npolled) { |
3245 | if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled)) | |
3246 | break; | |
3247 | } | |
3248 | ||
3249 | if (npolled) { | |
3250 | /* Memory barrier */ | |
3251 | wmb(); | |
3252 | hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index); | |
3253 | } | |
3254 | ||
626903e9 | 3255 | out: |
93aa2187 WHX |
3256 | spin_unlock_irqrestore(&hr_cq->lock, flags); |
3257 | ||
3258 | return npolled; | |
3259 | } | |
3260 | ||
260c3b34 YL |
3261 | static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, |
3262 | int step_idx) | |
3263 | { | |
3264 | int op; | |
3265 | ||
3266 | if (type == HEM_TYPE_SCCC && step_idx) | |
3267 | return -EINVAL; | |
3268 | ||
3269 | switch (type) { | |
3270 | case HEM_TYPE_QPC: | |
3271 | op = HNS_ROCE_CMD_WRITE_QPC_BT0; | |
3272 | break; | |
3273 | case HEM_TYPE_MTPT: | |
3274 | op = HNS_ROCE_CMD_WRITE_MPT_BT0; | |
3275 | break; | |
3276 | case HEM_TYPE_CQC: | |
3277 | op = HNS_ROCE_CMD_WRITE_CQC_BT0; | |
3278 | break; | |
3279 | case HEM_TYPE_SRQC: | |
3280 | op = HNS_ROCE_CMD_WRITE_SRQC_BT0; | |
3281 | break; | |
3282 | case HEM_TYPE_SCCC: | |
3283 | op = HNS_ROCE_CMD_WRITE_SCCC_BT0; | |
3284 | break; | |
3285 | case HEM_TYPE_QPC_TIMER: | |
3286 | op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0; | |
3287 | break; | |
3288 | case HEM_TYPE_CQC_TIMER: | |
3289 | op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0; | |
3290 | break; | |
3291 | default: | |
3292 | dev_warn(hr_dev->dev, | |
3293 | "Table %d not to be written by mailbox!\n", type); | |
3294 | return -EINVAL; | |
3295 | } | |
3296 | ||
3297 | return op + step_idx; | |
3298 | } | |
3299 | ||
a81fba28 WHX |
3300 | static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, |
3301 | struct hns_roce_hem_table *table, int obj, | |
3302 | int step_idx) | |
3303 | { | |
a81fba28 WHX |
3304 | struct hns_roce_cmd_mailbox *mailbox; |
3305 | struct hns_roce_hem_iter iter; | |
3306 | struct hns_roce_hem_mhop mhop; | |
3307 | struct hns_roce_hem *hem; | |
3308 | unsigned long mhop_obj = obj; | |
3309 | int i, j, k; | |
3310 | int ret = 0; | |
3311 | u64 hem_idx = 0; | |
3312 | u64 l1_idx = 0; | |
3313 | u64 bt_ba = 0; | |
3314 | u32 chunk_ba_num; | |
3315 | u32 hop_num; | |
260c3b34 | 3316 | int op; |
a81fba28 WHX |
3317 | |
3318 | if (!hns_roce_check_whether_mhop(hr_dev, table->type)) | |
3319 | return 0; | |
3320 | ||
3321 | hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop); | |
3322 | i = mhop.l0_idx; | |
3323 | j = mhop.l1_idx; | |
3324 | k = mhop.l2_idx; | |
3325 | hop_num = mhop.hop_num; | |
3326 | chunk_ba_num = mhop.bt_chunk_size / 8; | |
3327 | ||
3328 | if (hop_num == 2) { | |
3329 | hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num + | |
3330 | k; | |
3331 | l1_idx = i * chunk_ba_num + j; | |
3332 | } else if (hop_num == 1) { | |
3333 | hem_idx = i * chunk_ba_num + j; | |
3334 | } else if (hop_num == HNS_ROCE_HOP_NUM_0) { | |
3335 | hem_idx = i; | |
3336 | } | |
3337 | ||
260c3b34 YL |
3338 | op = get_op_for_set_hem(hr_dev, table->type, step_idx); |
3339 | if (op == -EINVAL) | |
a81fba28 | 3340 | return 0; |
a81fba28 WHX |
3341 | |
3342 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
3343 | if (IS_ERR(mailbox)) | |
3344 | return PTR_ERR(mailbox); | |
3345 | ||
6ac16e40 YL |
3346 | if (table->type == HEM_TYPE_SCCC) |
3347 | obj = mhop.l0_idx; | |
3348 | ||
a81fba28 WHX |
3349 | if (check_whether_last_step(hop_num, step_idx)) { |
3350 | hem = table->hem[hem_idx]; | |
3351 | for (hns_roce_hem_first(hem, &iter); | |
3352 | !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) { | |
3353 | bt_ba = hns_roce_hem_addr(&iter); | |
3354 | ||
3355 | /* configure the ba, tag, and op */ | |
3356 | ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, | |
3357 | obj, 0, op, | |
3358 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
3359 | } | |
3360 | } else { | |
3361 | if (step_idx == 0) | |
3362 | bt_ba = table->bt_l0_dma_addr[i]; | |
3363 | else if (step_idx == 1 && hop_num == 2) | |
3364 | bt_ba = table->bt_l1_dma_addr[l1_idx]; | |
3365 | ||
3366 | /* configure the ba, tag, and op */ | |
3367 | ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj, | |
3368 | 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS); | |
3369 | } | |
3370 | ||
3371 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
3372 | return ret; | |
3373 | } | |
3374 | ||
3375 | static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, | |
3376 | struct hns_roce_hem_table *table, int obj, | |
3377 | int step_idx) | |
3378 | { | |
3379 | struct device *dev = hr_dev->dev; | |
3380 | struct hns_roce_cmd_mailbox *mailbox; | |
617cf24f | 3381 | int ret; |
a81fba28 WHX |
3382 | u16 op = 0xff; |
3383 | ||
3384 | if (!hns_roce_check_whether_mhop(hr_dev, table->type)) | |
3385 | return 0; | |
3386 | ||
3387 | switch (table->type) { | |
3388 | case HEM_TYPE_QPC: | |
3389 | op = HNS_ROCE_CMD_DESTROY_QPC_BT0; | |
3390 | break; | |
3391 | case HEM_TYPE_MTPT: | |
3392 | op = HNS_ROCE_CMD_DESTROY_MPT_BT0; | |
3393 | break; | |
3394 | case HEM_TYPE_CQC: | |
3395 | op = HNS_ROCE_CMD_DESTROY_CQC_BT0; | |
3396 | break; | |
6a157f7d | 3397 | case HEM_TYPE_SCCC: |
0e40dc2f YL |
3398 | case HEM_TYPE_QPC_TIMER: |
3399 | case HEM_TYPE_CQC_TIMER: | |
6a157f7d | 3400 | break; |
a81fba28 WHX |
3401 | case HEM_TYPE_SRQC: |
3402 | op = HNS_ROCE_CMD_DESTROY_SRQC_BT0; | |
3403 | break; | |
3404 | default: | |
3405 | dev_warn(dev, "Table %d not to be destroyed by mailbox!\n", | |
3406 | table->type); | |
3407 | return 0; | |
3408 | } | |
6a157f7d | 3409 | |
0e40dc2f YL |
3410 | if (table->type == HEM_TYPE_SCCC || |
3411 | table->type == HEM_TYPE_QPC_TIMER || | |
3412 | table->type == HEM_TYPE_CQC_TIMER) | |
6a157f7d YL |
3413 | return 0; |
3414 | ||
a81fba28 WHX |
3415 | op += step_idx; |
3416 | ||
3417 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
3418 | if (IS_ERR(mailbox)) | |
3419 | return PTR_ERR(mailbox); | |
3420 | ||
3421 | /* configure the tag and op */ | |
3422 | ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op, | |
3423 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
3424 | ||
3425 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
3426 | return ret; | |
3427 | } | |
3428 | ||
926a01dc | 3429 | static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, |
926a01dc WHX |
3430 | struct hns_roce_v2_qp_context *context, |
3431 | struct hns_roce_qp *hr_qp) | |
3432 | { | |
3433 | struct hns_roce_cmd_mailbox *mailbox; | |
3434 | int ret; | |
3435 | ||
3436 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
3437 | if (IS_ERR(mailbox)) | |
3438 | return PTR_ERR(mailbox); | |
3439 | ||
3440 | memcpy(mailbox->buf, context, sizeof(*context) * 2); | |
3441 | ||
3442 | ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, | |
3443 | HNS_ROCE_CMD_MODIFY_QPC, | |
3444 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
3445 | ||
3446 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
3447 | ||
3448 | return ret; | |
3449 | } | |
3450 | ||
ace1c541 | 3451 | static void set_access_flags(struct hns_roce_qp *hr_qp, |
3452 | struct hns_roce_v2_qp_context *context, | |
3453 | struct hns_roce_v2_qp_context *qpc_mask, | |
3454 | const struct ib_qp_attr *attr, int attr_mask) | |
3455 | { | |
3456 | u8 dest_rd_atomic; | |
3457 | u32 access_flags; | |
3458 | ||
c2799119 | 3459 | dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ? |
ace1c541 | 3460 | attr->max_dest_rd_atomic : hr_qp->resp_depth; |
3461 | ||
c2799119 | 3462 | access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ? |
ace1c541 | 3463 | attr->qp_access_flags : hr_qp->atomic_rd_en; |
3464 | ||
3465 | if (!dest_rd_atomic) | |
3466 | access_flags &= IB_ACCESS_REMOTE_WRITE; | |
3467 | ||
3468 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, | |
3469 | !!(access_flags & IB_ACCESS_REMOTE_READ)); | |
3470 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0); | |
3471 | ||
3472 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, | |
3473 | !!(access_flags & IB_ACCESS_REMOTE_WRITE)); | |
3474 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0); | |
3475 | ||
3476 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, | |
3477 | !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
3478 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0); | |
7db82697 JZ |
3479 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, |
3480 | !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
3481 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0); | |
ace1c541 | 3482 | } |
3483 | ||
99441ab5 XW |
3484 | static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, |
3485 | struct hns_roce_v2_qp_context *context, | |
3486 | struct hns_roce_v2_qp_context *qpc_mask) | |
3487 | { | |
3488 | if (hr_qp->ibqp.qp_type == IB_QPT_GSI) | |
3489 | roce_set_field(context->byte_4_sqpn_tst, | |
3490 | V2_QPC_BYTE_4_SGE_SHIFT_M, | |
3491 | V2_QPC_BYTE_4_SGE_SHIFT_S, | |
3492 | ilog2((unsigned int)hr_qp->sge.sge_cnt)); | |
3493 | else | |
3494 | roce_set_field(context->byte_4_sqpn_tst, | |
3495 | V2_QPC_BYTE_4_SGE_SHIFT_M, | |
3496 | V2_QPC_BYTE_4_SGE_SHIFT_S, | |
3497 | hr_qp->sq.max_gs > | |
3498 | HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE ? | |
3499 | ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0); | |
3500 | ||
99441ab5 XW |
3501 | roce_set_field(context->byte_20_smac_sgid_idx, |
3502 | V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, | |
3503 | ilog2((unsigned int)hr_qp->sq.wqe_cnt)); | |
99441ab5 XW |
3504 | |
3505 | roce_set_field(context->byte_20_smac_sgid_idx, | |
3506 | V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, | |
3507 | (hr_qp->ibqp.qp_type == IB_QPT_XRC_INI || | |
3508 | hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT || | |
3509 | hr_qp->ibqp.srq) ? 0 : | |
3510 | ilog2((unsigned int)hr_qp->rq.wqe_cnt)); | |
99441ab5 XW |
3511 | } |
3512 | ||
926a01dc WHX |
3513 | static void modify_qp_reset_to_init(struct ib_qp *ibqp, |
3514 | const struct ib_qp_attr *attr, | |
0fa95a9a | 3515 | int attr_mask, |
926a01dc WHX |
3516 | struct hns_roce_v2_qp_context *context, |
3517 | struct hns_roce_v2_qp_context *qpc_mask) | |
3518 | { | |
ecaaf1e2 | 3519 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); |
926a01dc WHX |
3520 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); |
3521 | ||
3522 | /* | |
3523 | * In v2 engine, software pass context and context mask to hardware | |
3524 | * when modifying qp. If software need modify some fields in context, | |
3525 | * we should set all bits of the relevant fields in context mask to | |
3526 | * 0 at the same time, else set them to 0x1. | |
3527 | */ | |
3528 | roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, | |
3529 | V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); | |
926a01dc | 3530 | |
926a01dc WHX |
3531 | roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, |
3532 | V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); | |
926a01dc WHX |
3533 | |
3534 | roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, | |
3535 | V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); | |
926a01dc WHX |
3536 | |
3537 | roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M, | |
3538 | V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs)); | |
926a01dc | 3539 | |
99441ab5 | 3540 | set_qpc_wqe_cnt(hr_qp, context, qpc_mask); |
926a01dc WHX |
3541 | |
3542 | /* No VLAN need to set 0xFFF */ | |
c8e46f8d LO |
3543 | roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, |
3544 | V2_QPC_BYTE_24_VLAN_ID_S, 0xfff); | |
926a01dc | 3545 | |
f4c5d869 | 3546 | if (hr_qp->rdb_en) |
e088a685 YL |
3547 | roce_set_bit(context->byte_68_rq_db, |
3548 | V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1); | |
e088a685 YL |
3549 | |
3550 | roce_set_field(context->byte_68_rq_db, | |
3551 | V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M, | |
3552 | V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, | |
3553 | ((u32)hr_qp->rdb.dma) >> 1); | |
bfe86035 | 3554 | context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32); |
e088a685 | 3555 | |
ecaaf1e2 | 3556 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, |
3557 | (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0); | |
926a01dc WHX |
3558 | |
3559 | roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, | |
3560 | V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); | |
926a01dc WHX |
3561 | if (ibqp->srq) { |
3562 | roce_set_field(context->byte_76_srqn_op_en, | |
3563 | V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, | |
3564 | to_hr_srq(ibqp->srq)->srqn); | |
926a01dc WHX |
3565 | roce_set_bit(context->byte_76_srqn_op_en, |
3566 | V2_QPC_BYTE_76_SRQ_EN_S, 1); | |
f4c5d869 | 3567 | } |
926a01dc WHX |
3568 | |
3569 | roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M, | |
3570 | V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4); | |
926a01dc | 3571 | |
68a997c5 | 3572 | roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1); |
926a01dc WHX |
3573 | |
3574 | hr_qp->access_flags = attr->qp_access_flags; | |
926a01dc WHX |
3575 | roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, |
3576 | V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); | |
926a01dc WHX |
3577 | } |
3578 | ||
3579 | static void modify_qp_init_to_init(struct ib_qp *ibqp, | |
3580 | const struct ib_qp_attr *attr, int attr_mask, | |
3581 | struct hns_roce_v2_qp_context *context, | |
3582 | struct hns_roce_v2_qp_context *qpc_mask) | |
3583 | { | |
3584 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
3585 | ||
3586 | /* | |
3587 | * In v2 engine, software pass context and context mask to hardware | |
3588 | * when modifying qp. If software need modify some fields in context, | |
3589 | * we should set all bits of the relevant fields in context mask to | |
3590 | * 0 at the same time, else set them to 0x1. | |
3591 | */ | |
3592 | roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, | |
3593 | V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type)); | |
3594 | roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M, | |
3595 | V2_QPC_BYTE_4_TST_S, 0); | |
3596 | ||
926a01dc WHX |
3597 | if (attr_mask & IB_QP_ACCESS_FLAGS) { |
3598 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, | |
3599 | !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ)); | |
3600 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, | |
3601 | 0); | |
3602 | ||
3603 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, | |
3604 | !!(attr->qp_access_flags & | |
3605 | IB_ACCESS_REMOTE_WRITE)); | |
3606 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, | |
3607 | 0); | |
3608 | ||
3609 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, | |
3610 | !!(attr->qp_access_flags & | |
3611 | IB_ACCESS_REMOTE_ATOMIC)); | |
3612 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, | |
3613 | 0); | |
7db82697 JZ |
3614 | roce_set_bit(context->byte_76_srqn_op_en, |
3615 | V2_QPC_BYTE_76_EXT_ATE_S, | |
3616 | !!(attr->qp_access_flags & | |
3617 | IB_ACCESS_REMOTE_ATOMIC)); | |
3618 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, | |
3619 | V2_QPC_BYTE_76_EXT_ATE_S, 0); | |
926a01dc WHX |
3620 | } else { |
3621 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, | |
3622 | !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ)); | |
3623 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, | |
3624 | 0); | |
3625 | ||
3626 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, | |
3627 | !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE)); | |
3628 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, | |
3629 | 0); | |
3630 | ||
3631 | roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, | |
3632 | !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
3633 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, | |
3634 | 0); | |
7db82697 JZ |
3635 | roce_set_bit(context->byte_76_srqn_op_en, |
3636 | V2_QPC_BYTE_76_EXT_ATE_S, | |
3637 | !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC)); | |
3638 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, | |
3639 | V2_QPC_BYTE_76_EXT_ATE_S, 0); | |
926a01dc WHX |
3640 | } |
3641 | ||
926a01dc WHX |
3642 | roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, |
3643 | V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn); | |
3644 | roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M, | |
3645 | V2_QPC_BYTE_16_PD_S, 0); | |
3646 | ||
3647 | roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, | |
3648 | V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn); | |
3649 | roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M, | |
3650 | V2_QPC_BYTE_80_RX_CQN_S, 0); | |
3651 | ||
3652 | roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, | |
6d13b869 | 3653 | V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn); |
926a01dc WHX |
3654 | roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M, |
3655 | V2_QPC_BYTE_252_TX_CQN_S, 0); | |
3656 | ||
3657 | if (ibqp->srq) { | |
3658 | roce_set_bit(context->byte_76_srqn_op_en, | |
3659 | V2_QPC_BYTE_76_SRQ_EN_S, 1); | |
3660 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, | |
3661 | V2_QPC_BYTE_76_SRQ_EN_S, 0); | |
3662 | roce_set_field(context->byte_76_srqn_op_en, | |
3663 | V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, | |
3664 | to_hr_srq(ibqp->srq)->srqn); | |
3665 | roce_set_field(qpc_mask->byte_76_srqn_op_en, | |
3666 | V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0); | |
3667 | } | |
3668 | ||
926a01dc WHX |
3669 | roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, |
3670 | V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn); | |
3671 | roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M, | |
3672 | V2_QPC_BYTE_4_SQPN_S, 0); | |
3673 | ||
b6dd9b34 | 3674 | if (attr_mask & IB_QP_DEST_QPN) { |
3675 | roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, | |
3676 | V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn); | |
3677 | roce_set_field(qpc_mask->byte_56_dqpn_err, | |
3678 | V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); | |
3679 | } | |
926a01dc WHX |
3680 | } |
3681 | ||
8d18ad83 LO |
3682 | static bool check_wqe_rq_mtt_count(struct hns_roce_dev *hr_dev, |
3683 | struct hns_roce_qp *hr_qp, int mtt_cnt, | |
3684 | u32 page_size) | |
3685 | { | |
ae1c6148 | 3686 | struct ib_device *ibdev = &hr_dev->ib_dev; |
8d18ad83 LO |
3687 | |
3688 | if (hr_qp->rq.wqe_cnt < 1) | |
3689 | return true; | |
3690 | ||
3691 | if (mtt_cnt < 1) { | |
ae1c6148 LO |
3692 | ibdev_err(ibdev, "failed to find RQWQE buf ba of QP(0x%lx)\n", |
3693 | hr_qp->qpn); | |
8d18ad83 LO |
3694 | return false; |
3695 | } | |
3696 | ||
3697 | if (mtt_cnt < MTT_MIN_COUNT && | |
3698 | (hr_qp->rq.offset + page_size) < hr_qp->buff_size) { | |
ae1c6148 LO |
3699 | ibdev_err(ibdev, |
3700 | "failed to find next RQWQE buf ba of QP(0x%lx)\n", | |
3701 | hr_qp->qpn); | |
8d18ad83 LO |
3702 | return false; |
3703 | } | |
3704 | ||
3705 | return true; | |
3706 | } | |
3707 | ||
926a01dc WHX |
3708 | static int modify_qp_init_to_rtr(struct ib_qp *ibqp, |
3709 | const struct ib_qp_attr *attr, int attr_mask, | |
3710 | struct hns_roce_v2_qp_context *context, | |
3711 | struct hns_roce_v2_qp_context *qpc_mask) | |
3712 | { | |
3713 | const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); | |
3714 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
3715 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
ae1c6148 | 3716 | struct ib_device *ibdev = &hr_dev->ib_dev; |
8d18ad83 | 3717 | u64 mtts[MTT_MIN_COUNT] = { 0 }; |
e92f2c18 | 3718 | dma_addr_t dma_handle_3; |
926a01dc | 3719 | dma_addr_t dma_handle_2; |
8d18ad83 | 3720 | u64 wqe_sge_ba; |
926a01dc WHX |
3721 | u32 page_size; |
3722 | u8 port_num; | |
e92f2c18 | 3723 | u64 *mtts_3; |
926a01dc | 3724 | u64 *mtts_2; |
8d18ad83 | 3725 | int count; |
926a01dc WHX |
3726 | u8 *dmac; |
3727 | u8 *smac; | |
3728 | int port; | |
3729 | ||
3730 | /* Search qp buf's mtts */ | |
d563099e | 3731 | page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift; |
8d18ad83 LO |
3732 | count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, |
3733 | hr_qp->rq.offset / page_size, mtts, | |
3734 | MTT_MIN_COUNT, &wqe_sge_ba); | |
3735 | if (!ibqp->srq) | |
3736 | if (!check_wqe_rq_mtt_count(hr_dev, hr_qp, count, page_size)) | |
3737 | return -EINVAL; | |
926a01dc WHX |
3738 | |
3739 | /* Search IRRL's mtts */ | |
3740 | mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table, | |
3741 | hr_qp->qpn, &dma_handle_2); | |
3742 | if (!mtts_2) { | |
ae1c6148 | 3743 | ibdev_err(ibdev, "failed to find QP irrl_table\n"); |
926a01dc WHX |
3744 | return -EINVAL; |
3745 | } | |
3746 | ||
e92f2c18 | 3747 | /* Search TRRL's mtts */ |
3748 | mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table, | |
3749 | hr_qp->qpn, &dma_handle_3); | |
3750 | if (!mtts_3) { | |
ae1c6148 | 3751 | ibdev_err(ibdev, "failed to find QP trrl_table\n"); |
e92f2c18 | 3752 | return -EINVAL; |
3753 | } | |
3754 | ||
734f3863 | 3755 | if (attr_mask & IB_QP_ALT_PATH) { |
ae1c6148 LO |
3756 | ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error\n", |
3757 | attr_mask); | |
926a01dc WHX |
3758 | return -EINVAL; |
3759 | } | |
3760 | ||
3761 | dmac = (u8 *)attr->ah_attr.roce.dmac; | |
bfe86035 | 3762 | context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3); |
926a01dc WHX |
3763 | qpc_mask->wqe_sge_ba = 0; |
3764 | ||
3765 | /* | |
3766 | * In v2 engine, software pass context and context mask to hardware | |
3767 | * when modifying qp. If software need modify some fields in context, | |
3768 | * we should set all bits of the relevant fields in context mask to | |
3769 | * 0 at the same time, else set them to 0x1. | |
3770 | */ | |
3771 | roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, | |
8d18ad83 | 3772 | V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3)); |
926a01dc WHX |
3773 | roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M, |
3774 | V2_QPC_BYTE_12_WQE_SGE_BA_S, 0); | |
3775 | ||
3776 | roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, | |
3777 | V2_QPC_BYTE_12_SQ_HOP_NUM_S, | |
8d18ad83 LO |
3778 | hr_dev->caps.wqe_sq_hop_num == HNS_ROCE_HOP_NUM_0 ? |
3779 | 0 : hr_dev->caps.wqe_sq_hop_num); | |
926a01dc WHX |
3780 | roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M, |
3781 | V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0); | |
3782 | ||
3783 | roce_set_field(context->byte_20_smac_sgid_idx, | |
3784 | V2_QPC_BYTE_20_SGE_HOP_NUM_M, | |
3785 | V2_QPC_BYTE_20_SGE_HOP_NUM_S, | |
8d18ad83 LO |
3786 | ((ibqp->qp_type == IB_QPT_GSI) || |
3787 | hr_qp->sq.max_gs > HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ? | |
3788 | hr_dev->caps.wqe_sge_hop_num : 0); | |
926a01dc WHX |
3789 | roce_set_field(qpc_mask->byte_20_smac_sgid_idx, |
3790 | V2_QPC_BYTE_20_SGE_HOP_NUM_M, | |
3791 | V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0); | |
3792 | ||
3793 | roce_set_field(context->byte_20_smac_sgid_idx, | |
3794 | V2_QPC_BYTE_20_RQ_HOP_NUM_M, | |
3795 | V2_QPC_BYTE_20_RQ_HOP_NUM_S, | |
8d18ad83 LO |
3796 | hr_dev->caps.wqe_rq_hop_num == HNS_ROCE_HOP_NUM_0 ? |
3797 | 0 : hr_dev->caps.wqe_rq_hop_num); | |
926a01dc WHX |
3798 | roce_set_field(qpc_mask->byte_20_smac_sgid_idx, |
3799 | V2_QPC_BYTE_20_RQ_HOP_NUM_M, | |
3800 | V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0); | |
3801 | ||
3802 | roce_set_field(context->byte_16_buf_ba_pg_sz, | |
3803 | V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, | |
3804 | V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, | |
d563099e | 3805 | to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift)); |
926a01dc WHX |
3806 | roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, |
3807 | V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M, | |
3808 | V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0); | |
3809 | ||
3810 | roce_set_field(context->byte_16_buf_ba_pg_sz, | |
3811 | V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, | |
3812 | V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, | |
d563099e | 3813 | to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift)); |
926a01dc WHX |
3814 | roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, |
3815 | V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M, | |
3816 | V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0); | |
3817 | ||
d563099e | 3818 | context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0])); |
926a01dc WHX |
3819 | qpc_mask->rq_cur_blk_addr = 0; |
3820 | ||
3821 | roce_set_field(context->byte_92_srq_info, | |
3822 | V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, | |
3823 | V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, | |
d563099e | 3824 | upper_32_bits(to_hr_hw_page_addr(mtts[0]))); |
926a01dc WHX |
3825 | roce_set_field(qpc_mask->byte_92_srq_info, |
3826 | V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M, | |
3827 | V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0); | |
3828 | ||
d563099e | 3829 | context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1])); |
926a01dc WHX |
3830 | qpc_mask->rq_nxt_blk_addr = 0; |
3831 | ||
3832 | roce_set_field(context->byte_104_rq_sge, | |
3833 | V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, | |
3834 | V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, | |
d563099e | 3835 | upper_32_bits(to_hr_hw_page_addr(mtts[1]))); |
926a01dc WHX |
3836 | roce_set_field(qpc_mask->byte_104_rq_sge, |
3837 | V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M, | |
3838 | V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0); | |
3839 | ||
e92f2c18 | 3840 | roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, |
3841 | V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4); | |
3842 | roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M, | |
3843 | V2_QPC_BYTE_132_TRRL_BA_S, 0); | |
bfe86035 | 3844 | context->trrl_ba = cpu_to_le32(dma_handle_3 >> (16 + 4)); |
e92f2c18 | 3845 | qpc_mask->trrl_ba = 0; |
3846 | roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, | |
3847 | V2_QPC_BYTE_140_TRRL_BA_S, | |
3848 | (u32)(dma_handle_3 >> (32 + 16 + 4))); | |
3849 | roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M, | |
3850 | V2_QPC_BYTE_140_TRRL_BA_S, 0); | |
3851 | ||
bfe86035 | 3852 | context->irrl_ba = cpu_to_le32(dma_handle_2 >> 6); |
926a01dc WHX |
3853 | qpc_mask->irrl_ba = 0; |
3854 | roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, | |
3855 | V2_QPC_BYTE_208_IRRL_BA_S, | |
d5514246 | 3856 | dma_handle_2 >> (32 + 6)); |
926a01dc WHX |
3857 | roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M, |
3858 | V2_QPC_BYTE_208_IRRL_BA_S, 0); | |
3859 | ||
3860 | roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1); | |
3861 | roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0); | |
3862 | ||
3863 | roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, | |
3864 | hr_qp->sq_signal_bits); | |
3865 | roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S, | |
3866 | 0); | |
3867 | ||
3868 | port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port; | |
3869 | ||
3870 | smac = (u8 *)hr_dev->dev_addr[port]; | |
3871 | /* when dmac equals smac or loop_idc is 1, it should loopback */ | |
3872 | if (ether_addr_equal_unaligned(dmac, smac) || | |
3873 | hr_dev->loop_idc == 0x1) { | |
3874 | roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1); | |
3875 | roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0); | |
3876 | } | |
3877 | ||
b6dd9b34 | 3878 | if (attr_mask & IB_QP_DEST_QPN) { |
3879 | roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M, | |
3880 | V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num); | |
3881 | roce_set_field(qpc_mask->byte_56_dqpn_err, | |
3882 | V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0); | |
3883 | } | |
926a01dc WHX |
3884 | |
3885 | /* Configure GID index */ | |
3886 | port_num = rdma_ah_get_port_num(&attr->ah_attr); | |
3887 | roce_set_field(context->byte_20_smac_sgid_idx, | |
60262b10 | 3888 | V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, |
926a01dc WHX |
3889 | hns_get_gid_index(hr_dev, port_num - 1, |
3890 | grh->sgid_index)); | |
3891 | roce_set_field(qpc_mask->byte_20_smac_sgid_idx, | |
60262b10 | 3892 | V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); |
2a3d923f | 3893 | memcpy(&(context->dmac), dmac, sizeof(u32)); |
926a01dc WHX |
3894 | roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, |
3895 | V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4]))); | |
3896 | qpc_mask->dmac = 0; | |
3897 | roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M, | |
3898 | V2_QPC_BYTE_52_DMAC_S, 0); | |
3899 | ||
2a3d923f | 3900 | /* mtu*(2^LP_PKTN_INI) should not bigger than 1 message length 64kb */ |
926a01dc | 3901 | roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, |
9d04d56c | 3902 | V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); |
926a01dc WHX |
3903 | roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M, |
3904 | V2_QPC_BYTE_56_LP_PKTN_INI_S, 0); | |
3905 | ||
0fa95a9a | 3906 | if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD) |
3907 | roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, | |
3908 | V2_QPC_BYTE_24_MTU_S, IB_MTU_4096); | |
6852af86 | 3909 | else if (attr_mask & IB_QP_PATH_MTU) |
0fa95a9a | 3910 | roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, |
3911 | V2_QPC_BYTE_24_MTU_S, attr->path_mtu); | |
3912 | ||
926a01dc WHX |
3913 | roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M, |
3914 | V2_QPC_BYTE_24_MTU_S, 0); | |
3915 | ||
926a01dc WHX |
3916 | roce_set_field(context->byte_84_rq_ci_pi, |
3917 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, | |
3918 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head); | |
3919 | roce_set_field(qpc_mask->byte_84_rq_ci_pi, | |
3920 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, | |
3921 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); | |
3922 | ||
3923 | roce_set_field(qpc_mask->byte_84_rq_ci_pi, | |
3924 | V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M, | |
3925 | V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0); | |
3926 | roce_set_bit(qpc_mask->byte_108_rx_reqepsn, | |
3927 | V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0); | |
3928 | roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M, | |
3929 | V2_QPC_BYTE_96_RX_REQ_MSN_S, 0); | |
3930 | roce_set_field(qpc_mask->byte_108_rx_reqepsn, | |
3931 | V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M, | |
3932 | V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0); | |
3933 | ||
3934 | context->rq_rnr_timer = 0; | |
3935 | qpc_mask->rq_rnr_timer = 0; | |
3936 | ||
926a01dc WHX |
3937 | roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M, |
3938 | V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0); | |
3939 | roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M, | |
3940 | V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0); | |
3941 | ||
2a3d923f | 3942 | /* rocee send 2^lp_sgen_ini segs every time */ |
926a01dc WHX |
3943 | roce_set_field(context->byte_168_irrl_idx, |
3944 | V2_QPC_BYTE_168_LP_SGEN_INI_M, | |
3945 | V2_QPC_BYTE_168_LP_SGEN_INI_S, 3); | |
3946 | roce_set_field(qpc_mask->byte_168_irrl_idx, | |
3947 | V2_QPC_BYTE_168_LP_SGEN_INI_M, | |
3948 | V2_QPC_BYTE_168_LP_SGEN_INI_S, 0); | |
3949 | ||
926a01dc WHX |
3950 | return 0; |
3951 | } | |
3952 | ||
3953 | static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, | |
3954 | const struct ib_qp_attr *attr, int attr_mask, | |
3955 | struct hns_roce_v2_qp_context *context, | |
3956 | struct hns_roce_v2_qp_context *qpc_mask) | |
3957 | { | |
3958 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
3959 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
ae1c6148 | 3960 | struct ib_device *ibdev = &hr_dev->ib_dev; |
8d18ad83 LO |
3961 | u64 sge_cur_blk = 0; |
3962 | u64 sq_cur_blk = 0; | |
befb63b4 | 3963 | u32 page_size; |
8d18ad83 | 3964 | int count; |
926a01dc WHX |
3965 | |
3966 | /* Search qp buf's mtts */ | |
8d18ad83 LO |
3967 | count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL); |
3968 | if (count < 1) { | |
d563099e | 3969 | ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf\n", |
ae1c6148 | 3970 | hr_qp->qpn); |
926a01dc WHX |
3971 | return -EINVAL; |
3972 | } | |
3973 | ||
8d18ad83 | 3974 | if (hr_qp->sge.offset) { |
d563099e | 3975 | page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift; |
8d18ad83 LO |
3976 | count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, |
3977 | hr_qp->sge.offset / page_size, | |
3978 | &sge_cur_blk, 1, NULL); | |
3979 | if (count < 1) { | |
d563099e | 3980 | ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf\n", |
ae1c6148 | 3981 | hr_qp->qpn); |
8d18ad83 LO |
3982 | return -EINVAL; |
3983 | } | |
3984 | } | |
3985 | ||
734f3863 | 3986 | /* Not support alternate path and path migration */ |
d398d4ca | 3987 | if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) { |
ae1c6148 | 3988 | ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask); |
926a01dc WHX |
3989 | return -EINVAL; |
3990 | } | |
3991 | ||
3992 | /* | |
3993 | * In v2 engine, software pass context and context mask to hardware | |
3994 | * when modifying qp. If software need modify some fields in context, | |
3995 | * we should set all bits of the relevant fields in context mask to | |
3996 | * 0 at the same time, else set them to 0x1. | |
3997 | */ | |
d563099e | 3998 | context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); |
926a01dc WHX |
3999 | roce_set_field(context->byte_168_irrl_idx, |
4000 | V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, | |
4001 | V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, | |
d563099e | 4002 | upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); |
926a01dc WHX |
4003 | qpc_mask->sq_cur_blk_addr = 0; |
4004 | roce_set_field(qpc_mask->byte_168_irrl_idx, | |
4005 | V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M, | |
4006 | V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0); | |
4007 | ||
2a3d923f LO |
4008 | context->sq_cur_sge_blk_addr = ((ibqp->qp_type == IB_QPT_GSI) || |
4009 | hr_qp->sq.max_gs > HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ? | |
d563099e | 4010 | cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk)) : 0; |
befb63b4 | 4011 | roce_set_field(context->byte_184_irrl_idx, |
4012 | V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, | |
4013 | V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, | |
2a3d923f LO |
4014 | ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > |
4015 | HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) ? | |
d563099e | 4016 | upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)) : 0); |
befb63b4 | 4017 | qpc_mask->sq_cur_sge_blk_addr = 0; |
4018 | roce_set_field(qpc_mask->byte_184_irrl_idx, | |
4019 | V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M, | |
4020 | V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0); | |
4021 | ||
bfe86035 | 4022 | context->rx_sq_cur_blk_addr = |
d563099e | 4023 | cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk)); |
926a01dc WHX |
4024 | roce_set_field(context->byte_232_irrl_sge, |
4025 | V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, | |
4026 | V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, | |
d563099e | 4027 | upper_32_bits(to_hr_hw_page_addr(sq_cur_blk))); |
926a01dc WHX |
4028 | qpc_mask->rx_sq_cur_blk_addr = 0; |
4029 | roce_set_field(qpc_mask->byte_232_irrl_sge, | |
4030 | V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M, | |
4031 | V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0); | |
4032 | ||
4033 | /* | |
4034 | * Set some fields in context to zero, Because the default values | |
4035 | * of all fields in context are zero, we need not set them to 0 again. | |
4036 | * but we should set the relevant fields of context mask to 0. | |
4037 | */ | |
4038 | roce_set_field(qpc_mask->byte_232_irrl_sge, | |
4039 | V2_QPC_BYTE_232_IRRL_SGE_IDX_M, | |
4040 | V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0); | |
4041 | ||
4042 | roce_set_field(qpc_mask->byte_240_irrl_tail, | |
4043 | V2_QPC_BYTE_240_RX_ACK_MSN_M, | |
4044 | V2_QPC_BYTE_240_RX_ACK_MSN_S, 0); | |
4045 | ||
926a01dc WHX |
4046 | roce_set_field(qpc_mask->byte_248_ack_psn, |
4047 | V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M, | |
4048 | V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0); | |
4049 | roce_set_bit(qpc_mask->byte_248_ack_psn, | |
4050 | V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0); | |
4051 | roce_set_field(qpc_mask->byte_248_ack_psn, | |
4052 | V2_QPC_BYTE_248_IRRL_PSN_M, | |
4053 | V2_QPC_BYTE_248_IRRL_PSN_S, 0); | |
4054 | ||
4055 | roce_set_field(qpc_mask->byte_240_irrl_tail, | |
4056 | V2_QPC_BYTE_240_IRRL_TAIL_REAL_M, | |
4057 | V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0); | |
4058 | ||
926a01dc WHX |
4059 | roce_set_field(qpc_mask->byte_220_retry_psn_msn, |
4060 | V2_QPC_BYTE_220_RETRY_MSG_MSN_M, | |
4061 | V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0); | |
4062 | ||
4063 | roce_set_bit(qpc_mask->byte_248_ack_psn, | |
4064 | V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0); | |
4065 | ||
4066 | roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M, | |
4067 | V2_QPC_BYTE_212_CHECK_FLG_S, 0); | |
4068 | ||
926a01dc WHX |
4069 | roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, |
4070 | V2_QPC_BYTE_212_LSN_S, 0x100); | |
4071 | roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M, | |
4072 | V2_QPC_BYTE_212_LSN_S, 0); | |
4073 | ||
926a01dc WHX |
4074 | roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M, |
4075 | V2_QPC_BYTE_196_IRRL_HEAD_S, 0); | |
926a01dc WHX |
4076 | |
4077 | return 0; | |
4078 | } | |
4079 | ||
606bf89e LO |
4080 | static int hns_roce_v2_set_path(struct ib_qp *ibqp, |
4081 | const struct ib_qp_attr *attr, | |
4082 | int attr_mask, | |
4083 | struct hns_roce_v2_qp_context *context, | |
4084 | struct hns_roce_v2_qp_context *qpc_mask) | |
926a01dc | 4085 | { |
606bf89e | 4086 | const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr); |
926a01dc WHX |
4087 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); |
4088 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
ae1c6148 | 4089 | struct ib_device *ibdev = &hr_dev->ib_dev; |
606bf89e LO |
4090 | const struct ib_gid_attr *gid_attr = NULL; |
4091 | int is_roce_protocol; | |
32883228 | 4092 | u16 vlan_id = 0xffff; |
606bf89e | 4093 | bool is_udp = false; |
606bf89e LO |
4094 | u8 ib_port; |
4095 | u8 hr_port; | |
4096 | int ret; | |
926a01dc | 4097 | |
606bf89e LO |
4098 | ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1; |
4099 | hr_port = ib_port - 1; | |
4100 | is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) && | |
4101 | rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; | |
4102 | ||
4103 | if (is_roce_protocol) { | |
4104 | gid_attr = attr->ah_attr.grh.sgid_attr; | |
32883228 | 4105 | ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL); |
606bf89e LO |
4106 | if (ret) |
4107 | return ret; | |
4108 | ||
4109 | if (gid_attr) | |
4110 | is_udp = (gid_attr->gid_type == | |
4111 | IB_GID_TYPE_ROCE_UDP_ENCAP); | |
4112 | } | |
4113 | ||
32883228 | 4114 | if (vlan_id < VLAN_N_VID) { |
606bf89e LO |
4115 | roce_set_bit(context->byte_76_srqn_op_en, |
4116 | V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1); | |
4117 | roce_set_bit(qpc_mask->byte_76_srqn_op_en, | |
4118 | V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0); | |
4119 | roce_set_bit(context->byte_168_irrl_idx, | |
4120 | V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1); | |
4121 | roce_set_bit(qpc_mask->byte_168_irrl_idx, | |
4122 | V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0); | |
4123 | } | |
4124 | ||
4125 | roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, | |
32883228 | 4126 | V2_QPC_BYTE_24_VLAN_ID_S, vlan_id); |
606bf89e LO |
4127 | roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M, |
4128 | V2_QPC_BYTE_24_VLAN_ID_S, 0); | |
4129 | ||
4130 | if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) { | |
ae1c6148 LO |
4131 | ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n", |
4132 | grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]); | |
606bf89e LO |
4133 | return -EINVAL; |
4134 | } | |
4135 | ||
4136 | if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) { | |
ae1c6148 | 4137 | ibdev_err(ibdev, "ah attr is not RDMA roce type\n"); |
606bf89e LO |
4138 | return -EINVAL; |
4139 | } | |
4140 | ||
4141 | roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, | |
4142 | V2_QPC_BYTE_52_UDPSPN_S, | |
4143 | is_udp ? 0x12b7 : 0); | |
4144 | ||
4145 | roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M, | |
4146 | V2_QPC_BYTE_52_UDPSPN_S, 0); | |
4147 | ||
4148 | roce_set_field(context->byte_20_smac_sgid_idx, | |
4149 | V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, | |
4150 | grh->sgid_index); | |
4151 | ||
4152 | roce_set_field(qpc_mask->byte_20_smac_sgid_idx, | |
4153 | V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0); | |
4154 | ||
4155 | roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, | |
4156 | V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit); | |
4157 | roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M, | |
4158 | V2_QPC_BYTE_24_HOP_LIMIT_S, 0); | |
4159 | ||
dfaf2854 | 4160 | if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B && is_udp) |
606bf89e LO |
4161 | roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, |
4162 | V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2); | |
4163 | else | |
4164 | roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, | |
4165 | V2_QPC_BYTE_24_TC_S, grh->traffic_class); | |
4166 | roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M, | |
4167 | V2_QPC_BYTE_24_TC_S, 0); | |
4168 | roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, | |
4169 | V2_QPC_BYTE_28_FL_S, grh->flow_label); | |
4170 | roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M, | |
4171 | V2_QPC_BYTE_28_FL_S, 0); | |
4172 | memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw)); | |
4173 | memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw)); | |
4174 | roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, | |
4175 | V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr)); | |
4176 | roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M, | |
4177 | V2_QPC_BYTE_28_SL_S, 0); | |
4178 | hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr); | |
4179 | ||
4180 | return 0; | |
4181 | } | |
4182 | ||
357f3429 LC |
4183 | static bool check_qp_state(enum ib_qp_state cur_state, |
4184 | enum ib_qp_state new_state) | |
4185 | { | |
4186 | static const bool sm[][IB_QPS_ERR + 1] = { | |
4187 | [IB_QPS_RESET] = { [IB_QPS_RESET] = true, | |
4188 | [IB_QPS_INIT] = true }, | |
4189 | [IB_QPS_INIT] = { [IB_QPS_RESET] = true, | |
4190 | [IB_QPS_INIT] = true, | |
4191 | [IB_QPS_RTR] = true, | |
4192 | [IB_QPS_ERR] = true }, | |
4193 | [IB_QPS_RTR] = { [IB_QPS_RESET] = true, | |
4194 | [IB_QPS_RTS] = true, | |
4195 | [IB_QPS_ERR] = true }, | |
4196 | [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }, | |
4197 | [IB_QPS_SQD] = {}, | |
4198 | [IB_QPS_SQE] = {}, | |
4199 | [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true } | |
4200 | }; | |
4201 | ||
4202 | return sm[cur_state][new_state]; | |
4203 | } | |
4204 | ||
606bf89e LO |
4205 | static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, |
4206 | const struct ib_qp_attr *attr, | |
4207 | int attr_mask, | |
4208 | enum ib_qp_state cur_state, | |
4209 | enum ib_qp_state new_state, | |
4210 | struct hns_roce_v2_qp_context *context, | |
4211 | struct hns_roce_v2_qp_context *qpc_mask) | |
4212 | { | |
4213 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
4214 | int ret = 0; | |
926a01dc | 4215 | |
357f3429 LC |
4216 | if (!check_qp_state(cur_state, new_state)) { |
4217 | ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n"); | |
4218 | return -EINVAL; | |
4219 | } | |
4220 | ||
926a01dc | 4221 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { |
9f507101 | 4222 | memset(qpc_mask, 0, sizeof(*qpc_mask)); |
0fa95a9a | 4223 | modify_qp_reset_to_init(ibqp, attr, attr_mask, context, |
4224 | qpc_mask); | |
926a01dc WHX |
4225 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { |
4226 | modify_qp_init_to_init(ibqp, attr, attr_mask, context, | |
4227 | qpc_mask); | |
4228 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { | |
4229 | ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context, | |
4230 | qpc_mask); | |
926a01dc WHX |
4231 | } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { |
4232 | ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context, | |
4233 | qpc_mask); | |
926a01dc WHX |
4234 | } |
4235 | ||
606bf89e LO |
4236 | return ret; |
4237 | } | |
9c6ccc03 | 4238 | |
606bf89e LO |
4239 | static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, |
4240 | const struct ib_qp_attr *attr, | |
4241 | int attr_mask, | |
4242 | struct hns_roce_v2_qp_context *context, | |
4243 | struct hns_roce_v2_qp_context *qpc_mask) | |
4244 | { | |
4245 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
4246 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
4247 | int ret = 0; | |
0425e3e6 | 4248 | |
610b8967 | 4249 | if (attr_mask & IB_QP_AV) { |
606bf89e LO |
4250 | ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context, |
4251 | qpc_mask); | |
4252 | if (ret) | |
4253 | return ret; | |
610b8967 LO |
4254 | } |
4255 | ||
5b01b243 LO |
4256 | if (attr_mask & IB_QP_TIMEOUT) { |
4257 | if (attr->timeout < 31) { | |
4258 | roce_set_field(context->byte_28_at_fl, | |
4259 | V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, | |
4260 | attr->timeout); | |
4261 | roce_set_field(qpc_mask->byte_28_at_fl, | |
4262 | V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S, | |
4263 | 0); | |
4264 | } else { | |
ae1c6148 LO |
4265 | ibdev_warn(&hr_dev->ib_dev, |
4266 | "Local ACK timeout shall be 0 to 30.\n"); | |
5b01b243 LO |
4267 | } |
4268 | } | |
4269 | ||
4270 | if (attr_mask & IB_QP_RETRY_CNT) { | |
4271 | roce_set_field(context->byte_212_lsn, | |
4272 | V2_QPC_BYTE_212_RETRY_NUM_INIT_M, | |
4273 | V2_QPC_BYTE_212_RETRY_NUM_INIT_S, | |
4274 | attr->retry_cnt); | |
4275 | roce_set_field(qpc_mask->byte_212_lsn, | |
4276 | V2_QPC_BYTE_212_RETRY_NUM_INIT_M, | |
4277 | V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0); | |
4278 | ||
4279 | roce_set_field(context->byte_212_lsn, | |
4280 | V2_QPC_BYTE_212_RETRY_CNT_M, | |
60262b10 | 4281 | V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt); |
5b01b243 LO |
4282 | roce_set_field(qpc_mask->byte_212_lsn, |
4283 | V2_QPC_BYTE_212_RETRY_CNT_M, | |
4284 | V2_QPC_BYTE_212_RETRY_CNT_S, 0); | |
4285 | } | |
4286 | ||
4287 | if (attr_mask & IB_QP_RNR_RETRY) { | |
4288 | roce_set_field(context->byte_244_rnr_rxack, | |
4289 | V2_QPC_BYTE_244_RNR_NUM_INIT_M, | |
4290 | V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry); | |
4291 | roce_set_field(qpc_mask->byte_244_rnr_rxack, | |
4292 | V2_QPC_BYTE_244_RNR_NUM_INIT_M, | |
4293 | V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0); | |
4294 | ||
4295 | roce_set_field(context->byte_244_rnr_rxack, | |
4296 | V2_QPC_BYTE_244_RNR_CNT_M, | |
4297 | V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry); | |
4298 | roce_set_field(qpc_mask->byte_244_rnr_rxack, | |
4299 | V2_QPC_BYTE_244_RNR_CNT_M, | |
4300 | V2_QPC_BYTE_244_RNR_CNT_S, 0); | |
4301 | } | |
4302 | ||
606bf89e | 4303 | /* RC&UC&UD required attr */ |
f04cc178 LO |
4304 | if (attr_mask & IB_QP_SQ_PSN) { |
4305 | roce_set_field(context->byte_172_sq_psn, | |
4306 | V2_QPC_BYTE_172_SQ_CUR_PSN_M, | |
4307 | V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn); | |
4308 | roce_set_field(qpc_mask->byte_172_sq_psn, | |
4309 | V2_QPC_BYTE_172_SQ_CUR_PSN_M, | |
4310 | V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0); | |
4311 | ||
4312 | roce_set_field(context->byte_196_sq_psn, | |
4313 | V2_QPC_BYTE_196_SQ_MAX_PSN_M, | |
4314 | V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn); | |
4315 | roce_set_field(qpc_mask->byte_196_sq_psn, | |
4316 | V2_QPC_BYTE_196_SQ_MAX_PSN_M, | |
4317 | V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0); | |
4318 | ||
4319 | roce_set_field(context->byte_220_retry_psn_msn, | |
4320 | V2_QPC_BYTE_220_RETRY_MSG_PSN_M, | |
4321 | V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn); | |
4322 | roce_set_field(qpc_mask->byte_220_retry_psn_msn, | |
4323 | V2_QPC_BYTE_220_RETRY_MSG_PSN_M, | |
4324 | V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0); | |
4325 | ||
4326 | roce_set_field(context->byte_224_retry_msg, | |
4327 | V2_QPC_BYTE_224_RETRY_MSG_PSN_M, | |
4328 | V2_QPC_BYTE_224_RETRY_MSG_PSN_S, | |
2a3d923f | 4329 | attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S); |
f04cc178 LO |
4330 | roce_set_field(qpc_mask->byte_224_retry_msg, |
4331 | V2_QPC_BYTE_224_RETRY_MSG_PSN_M, | |
4332 | V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0); | |
4333 | ||
4334 | roce_set_field(context->byte_224_retry_msg, | |
4335 | V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, | |
4336 | V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, | |
4337 | attr->sq_psn); | |
4338 | roce_set_field(qpc_mask->byte_224_retry_msg, | |
4339 | V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M, | |
4340 | V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0); | |
4341 | ||
4342 | roce_set_field(context->byte_244_rnr_rxack, | |
4343 | V2_QPC_BYTE_244_RX_ACK_EPSN_M, | |
4344 | V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn); | |
4345 | roce_set_field(qpc_mask->byte_244_rnr_rxack, | |
4346 | V2_QPC_BYTE_244_RX_ACK_EPSN_M, | |
4347 | V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0); | |
4348 | } | |
4349 | ||
5b01b243 LO |
4350 | if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) && |
4351 | attr->max_dest_rd_atomic) { | |
4352 | roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, | |
4353 | V2_QPC_BYTE_140_RR_MAX_S, | |
4354 | fls(attr->max_dest_rd_atomic - 1)); | |
4355 | roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M, | |
4356 | V2_QPC_BYTE_140_RR_MAX_S, 0); | |
4357 | } | |
4358 | ||
4359 | if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) { | |
4360 | roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M, | |
4361 | V2_QPC_BYTE_208_SR_MAX_S, | |
4362 | fls(attr->max_rd_atomic - 1)); | |
4363 | roce_set_field(qpc_mask->byte_208_irrl, | |
4364 | V2_QPC_BYTE_208_SR_MAX_M, | |
4365 | V2_QPC_BYTE_208_SR_MAX_S, 0); | |
4366 | } | |
4367 | ||
ace1c541 | 4368 | if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) |
4369 | set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask); | |
4370 | ||
5b01b243 LO |
4371 | if (attr_mask & IB_QP_MIN_RNR_TIMER) { |
4372 | roce_set_field(context->byte_80_rnr_rx_cqn, | |
4373 | V2_QPC_BYTE_80_MIN_RNR_TIME_M, | |
4374 | V2_QPC_BYTE_80_MIN_RNR_TIME_S, | |
4375 | attr->min_rnr_timer); | |
4376 | roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, | |
4377 | V2_QPC_BYTE_80_MIN_RNR_TIME_M, | |
4378 | V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0); | |
4379 | } | |
4380 | ||
601f3e6d LO |
4381 | /* RC&UC required attr */ |
4382 | if (attr_mask & IB_QP_RQ_PSN) { | |
4383 | roce_set_field(context->byte_108_rx_reqepsn, | |
4384 | V2_QPC_BYTE_108_RX_REQ_EPSN_M, | |
4385 | V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn); | |
4386 | roce_set_field(qpc_mask->byte_108_rx_reqepsn, | |
4387 | V2_QPC_BYTE_108_RX_REQ_EPSN_M, | |
4388 | V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0); | |
4389 | ||
4390 | roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M, | |
4391 | V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1); | |
4392 | roce_set_field(qpc_mask->byte_152_raq, | |
4393 | V2_QPC_BYTE_152_RAQ_PSN_M, | |
4394 | V2_QPC_BYTE_152_RAQ_PSN_S, 0); | |
4395 | } | |
4396 | ||
5b01b243 | 4397 | if (attr_mask & IB_QP_QKEY) { |
bfe86035 | 4398 | context->qkey_xrcd = cpu_to_le32(attr->qkey); |
5b01b243 LO |
4399 | qpc_mask->qkey_xrcd = 0; |
4400 | hr_qp->qkey = attr->qkey; | |
4401 | } | |
4402 | ||
606bf89e LO |
4403 | return ret; |
4404 | } | |
4405 | ||
4406 | static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, | |
4407 | const struct ib_qp_attr *attr, | |
4408 | int attr_mask) | |
4409 | { | |
4410 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
4411 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
4412 | ||
4413 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
4414 | hr_qp->atomic_rd_en = attr->qp_access_flags; | |
4415 | ||
4416 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) | |
4417 | hr_qp->resp_depth = attr->max_dest_rd_atomic; | |
4418 | if (attr_mask & IB_QP_PORT) { | |
4419 | hr_qp->port = attr->port_num - 1; | |
4420 | hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port]; | |
4421 | } | |
4422 | } | |
4423 | ||
4424 | static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, | |
4425 | const struct ib_qp_attr *attr, | |
4426 | int attr_mask, enum ib_qp_state cur_state, | |
4427 | enum ib_qp_state new_state) | |
4428 | { | |
4429 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
4430 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
4b42d05d LC |
4431 | struct hns_roce_v2_qp_context ctx[2]; |
4432 | struct hns_roce_v2_qp_context *context = ctx; | |
4433 | struct hns_roce_v2_qp_context *qpc_mask = ctx + 1; | |
ae1c6148 | 4434 | struct ib_device *ibdev = &hr_dev->ib_dev; |
b5374286 YL |
4435 | unsigned long sq_flag = 0; |
4436 | unsigned long rq_flag = 0; | |
b5c229dc | 4437 | int ret; |
606bf89e | 4438 | |
606bf89e LO |
4439 | /* |
4440 | * In v2 engine, software pass context and context mask to hardware | |
4441 | * when modifying qp. If software need modify some fields in context, | |
4442 | * we should set all bits of the relevant fields in context mask to | |
4443 | * 0 at the same time, else set them to 0x1. | |
4444 | */ | |
4b42d05d | 4445 | memset(context, 0, sizeof(*context)); |
606bf89e LO |
4446 | memset(qpc_mask, 0xff, sizeof(*qpc_mask)); |
4447 | ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state, | |
4448 | new_state, context, qpc_mask); | |
4449 | if (ret) | |
4450 | goto out; | |
4451 | ||
4452 | /* When QP state is err, SQ and RQ WQE should be flushed */ | |
4453 | if (new_state == IB_QPS_ERR) { | |
b5374286 | 4454 | spin_lock_irqsave(&hr_qp->sq.lock, sq_flag); |
b5374286 | 4455 | hr_qp->state = IB_QPS_ERR; |
606bf89e LO |
4456 | roce_set_field(context->byte_160_sq_ci_pi, |
4457 | V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, | |
4458 | V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, | |
4459 | hr_qp->sq.head); | |
4460 | roce_set_field(qpc_mask->byte_160_sq_ci_pi, | |
4461 | V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M, | |
4462 | V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0); | |
75c994e6 | 4463 | spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag); |
606bf89e LO |
4464 | |
4465 | if (!ibqp->srq) { | |
75c994e6 | 4466 | spin_lock_irqsave(&hr_qp->rq.lock, rq_flag); |
606bf89e LO |
4467 | roce_set_field(context->byte_84_rq_ci_pi, |
4468 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, | |
4469 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, | |
4470 | hr_qp->rq.head); | |
4471 | roce_set_field(qpc_mask->byte_84_rq_ci_pi, | |
4472 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M, | |
4473 | V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0); | |
75c994e6 | 4474 | spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag); |
606bf89e LO |
4475 | } |
4476 | } | |
4477 | ||
4478 | /* Configure the optional fields */ | |
4479 | ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context, | |
4480 | qpc_mask); | |
4481 | if (ret) | |
4482 | goto out; | |
4483 | ||
c7bcb134 LO |
4484 | roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S, |
4485 | ibqp->srq ? 1 : 0); | |
4486 | roce_set_bit(qpc_mask->byte_108_rx_reqepsn, | |
4487 | V2_QPC_BYTE_108_INV_CREDIT_S, 0); | |
4488 | ||
926a01dc | 4489 | /* Every status migrate must change state */ |
2362ccee | 4490 | roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, |
926a01dc | 4491 | V2_QPC_BYTE_60_QP_ST_S, new_state); |
2362ccee | 4492 | roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M, |
926a01dc WHX |
4493 | V2_QPC_BYTE_60_QP_ST_S, 0); |
4494 | ||
4495 | /* SW pass context to HW */ | |
032b0574 | 4496 | ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp); |
926a01dc | 4497 | if (ret) { |
ae1c6148 | 4498 | ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret); |
926a01dc WHX |
4499 | goto out; |
4500 | } | |
4501 | ||
4502 | hr_qp->state = new_state; | |
4503 | ||
606bf89e | 4504 | hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask); |
926a01dc WHX |
4505 | |
4506 | if (new_state == IB_QPS_RESET && !ibqp->uobject) { | |
4507 | hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, | |
4508 | ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); | |
4509 | if (ibqp->send_cq != ibqp->recv_cq) | |
4510 | hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq), | |
4511 | hr_qp->qpn, NULL); | |
4512 | ||
4513 | hr_qp->rq.head = 0; | |
4514 | hr_qp->rq.tail = 0; | |
4515 | hr_qp->sq.head = 0; | |
4516 | hr_qp->sq.tail = 0; | |
926a01dc | 4517 | hr_qp->next_sge = 0; |
e088a685 YL |
4518 | if (hr_qp->rq.wqe_cnt) |
4519 | *hr_qp->rdb.db_record = 0; | |
926a01dc WHX |
4520 | } |
4521 | ||
4522 | out: | |
926a01dc WHX |
4523 | return ret; |
4524 | } | |
4525 | ||
a3de9e83 | 4526 | static int to_ib_qp_st(enum hns_roce_v2_qp_state state) |
926a01dc | 4527 | { |
a3de9e83 LC |
4528 | static const enum ib_qp_state map[] = { |
4529 | [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET, | |
4530 | [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT, | |
4531 | [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR, | |
4532 | [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS, | |
4533 | [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD, | |
4534 | [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE, | |
4535 | [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR, | |
4536 | [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD | |
4537 | }; | |
4538 | ||
4539 | return (state < ARRAY_SIZE(map)) ? map[state] : -1; | |
926a01dc WHX |
4540 | } |
4541 | ||
4542 | static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, | |
4543 | struct hns_roce_qp *hr_qp, | |
4544 | struct hns_roce_v2_qp_context *hr_context) | |
4545 | { | |
4546 | struct hns_roce_cmd_mailbox *mailbox; | |
4547 | int ret; | |
4548 | ||
4549 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
4550 | if (IS_ERR(mailbox)) | |
4551 | return PTR_ERR(mailbox); | |
4552 | ||
4553 | ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, | |
4554 | HNS_ROCE_CMD_QUERY_QPC, | |
4555 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
ae1c6148 | 4556 | if (ret) |
926a01dc | 4557 | goto out; |
926a01dc WHX |
4558 | |
4559 | memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); | |
4560 | ||
4561 | out: | |
4562 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
4563 | return ret; | |
4564 | } | |
4565 | ||
4566 | static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, | |
4567 | int qp_attr_mask, | |
4568 | struct ib_qp_init_attr *qp_init_attr) | |
4569 | { | |
4570 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
4571 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
4b42d05d | 4572 | struct hns_roce_v2_qp_context context = {}; |
ae1c6148 | 4573 | struct ib_device *ibdev = &hr_dev->ib_dev; |
926a01dc WHX |
4574 | int tmp_qp_state; |
4575 | int state; | |
4576 | int ret; | |
4577 | ||
926a01dc WHX |
4578 | memset(qp_attr, 0, sizeof(*qp_attr)); |
4579 | memset(qp_init_attr, 0, sizeof(*qp_init_attr)); | |
4580 | ||
4581 | mutex_lock(&hr_qp->mutex); | |
4582 | ||
4583 | if (hr_qp->state == IB_QPS_RESET) { | |
4584 | qp_attr->qp_state = IB_QPS_RESET; | |
63ea641f | 4585 | ret = 0; |
926a01dc WHX |
4586 | goto done; |
4587 | } | |
4588 | ||
4b42d05d | 4589 | ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context); |
926a01dc | 4590 | if (ret) { |
ae1c6148 | 4591 | ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret); |
926a01dc WHX |
4592 | ret = -EINVAL; |
4593 | goto out; | |
4594 | } | |
4595 | ||
4b42d05d | 4596 | state = roce_get_field(context.byte_60_qpst_tempid, |
926a01dc WHX |
4597 | V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S); |
4598 | tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state); | |
4599 | if (tmp_qp_state == -1) { | |
ae1c6148 | 4600 | ibdev_err(ibdev, "Illegal ib_qp_state\n"); |
926a01dc WHX |
4601 | ret = -EINVAL; |
4602 | goto out; | |
4603 | } | |
4604 | hr_qp->state = (u8)tmp_qp_state; | |
4605 | qp_attr->qp_state = (enum ib_qp_state)hr_qp->state; | |
4b42d05d | 4606 | qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc, |
926a01dc WHX |
4607 | V2_QPC_BYTE_24_MTU_M, |
4608 | V2_QPC_BYTE_24_MTU_S); | |
4609 | qp_attr->path_mig_state = IB_MIG_ARMED; | |
2bf910d4 | 4610 | qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; |
926a01dc WHX |
4611 | if (hr_qp->ibqp.qp_type == IB_QPT_UD) |
4612 | qp_attr->qkey = V2_QKEY_VAL; | |
4613 | ||
4b42d05d | 4614 | qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn, |
926a01dc WHX |
4615 | V2_QPC_BYTE_108_RX_REQ_EPSN_M, |
4616 | V2_QPC_BYTE_108_RX_REQ_EPSN_S); | |
4b42d05d | 4617 | qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn, |
926a01dc WHX |
4618 | V2_QPC_BYTE_172_SQ_CUR_PSN_M, |
4619 | V2_QPC_BYTE_172_SQ_CUR_PSN_S); | |
4b42d05d | 4620 | qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err, |
926a01dc WHX |
4621 | V2_QPC_BYTE_56_DQPN_M, |
4622 | V2_QPC_BYTE_56_DQPN_S); | |
4b42d05d | 4623 | qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en, |
98c09b8c | 4624 | V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) | |
4b42d05d | 4625 | ((roce_get_bit(context.byte_76_srqn_op_en, |
98c09b8c | 4626 | V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) | |
4b42d05d | 4627 | ((roce_get_bit(context.byte_76_srqn_op_en, |
2a3d923f LO |
4628 | V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S); |
4629 | ||
926a01dc WHX |
4630 | if (hr_qp->ibqp.qp_type == IB_QPT_RC || |
4631 | hr_qp->ibqp.qp_type == IB_QPT_UC) { | |
4632 | struct ib_global_route *grh = | |
4633 | rdma_ah_retrieve_grh(&qp_attr->ah_attr); | |
4634 | ||
4635 | rdma_ah_set_sl(&qp_attr->ah_attr, | |
4b42d05d | 4636 | roce_get_field(context.byte_28_at_fl, |
926a01dc WHX |
4637 | V2_QPC_BYTE_28_SL_M, |
4638 | V2_QPC_BYTE_28_SL_S)); | |
4b42d05d | 4639 | grh->flow_label = roce_get_field(context.byte_28_at_fl, |
926a01dc WHX |
4640 | V2_QPC_BYTE_28_FL_M, |
4641 | V2_QPC_BYTE_28_FL_S); | |
4b42d05d | 4642 | grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx, |
926a01dc WHX |
4643 | V2_QPC_BYTE_20_SGID_IDX_M, |
4644 | V2_QPC_BYTE_20_SGID_IDX_S); | |
4b42d05d | 4645 | grh->hop_limit = roce_get_field(context.byte_24_mtu_tc, |
926a01dc WHX |
4646 | V2_QPC_BYTE_24_HOP_LIMIT_M, |
4647 | V2_QPC_BYTE_24_HOP_LIMIT_S); | |
4b42d05d | 4648 | grh->traffic_class = roce_get_field(context.byte_24_mtu_tc, |
926a01dc WHX |
4649 | V2_QPC_BYTE_24_TC_M, |
4650 | V2_QPC_BYTE_24_TC_S); | |
4651 | ||
4b42d05d | 4652 | memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw)); |
926a01dc WHX |
4653 | } |
4654 | ||
4655 | qp_attr->port_num = hr_qp->port + 1; | |
4656 | qp_attr->sq_draining = 0; | |
4b42d05d | 4657 | qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl, |
926a01dc WHX |
4658 | V2_QPC_BYTE_208_SR_MAX_M, |
4659 | V2_QPC_BYTE_208_SR_MAX_S); | |
4b42d05d | 4660 | qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq, |
926a01dc WHX |
4661 | V2_QPC_BYTE_140_RR_MAX_M, |
4662 | V2_QPC_BYTE_140_RR_MAX_S); | |
4b42d05d | 4663 | qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn, |
926a01dc WHX |
4664 | V2_QPC_BYTE_80_MIN_RNR_TIME_M, |
4665 | V2_QPC_BYTE_80_MIN_RNR_TIME_S); | |
4b42d05d | 4666 | qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl, |
926a01dc WHX |
4667 | V2_QPC_BYTE_28_AT_M, |
4668 | V2_QPC_BYTE_28_AT_S); | |
4b42d05d | 4669 | qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn, |
926a01dc WHX |
4670 | V2_QPC_BYTE_212_RETRY_CNT_M, |
4671 | V2_QPC_BYTE_212_RETRY_CNT_S); | |
bfe86035 | 4672 | qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer); |
926a01dc WHX |
4673 | |
4674 | done: | |
4675 | qp_attr->cur_qp_state = qp_attr->qp_state; | |
4676 | qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt; | |
4677 | qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs; | |
4678 | ||
4679 | if (!ibqp->uobject) { | |
4680 | qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt; | |
4681 | qp_attr->cap.max_send_sge = hr_qp->sq.max_gs; | |
4682 | } else { | |
4683 | qp_attr->cap.max_send_wr = 0; | |
4684 | qp_attr->cap.max_send_sge = 0; | |
4685 | } | |
4686 | ||
4687 | qp_init_attr->cap = qp_attr->cap; | |
4688 | ||
4689 | out: | |
4690 | mutex_unlock(&hr_qp->mutex); | |
926a01dc WHX |
4691 | return ret; |
4692 | } | |
4693 | ||
4694 | static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, | |
4695 | struct hns_roce_qp *hr_qp, | |
bdeacabd | 4696 | struct ib_udata *udata) |
926a01dc | 4697 | { |
db50077b | 4698 | struct ib_device *ibdev = &hr_dev->ib_dev; |
ae1c6148 | 4699 | struct hns_roce_cq *send_cq, *recv_cq; |
626903e9 | 4700 | unsigned long flags; |
d302c6e3 | 4701 | int ret = 0; |
926a01dc WHX |
4702 | |
4703 | if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) { | |
4704 | /* Modify qp to reset before destroying qp */ | |
4705 | ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0, | |
4706 | hr_qp->state, IB_QPS_RESET); | |
d302c6e3 | 4707 | if (ret) |
ae1c6148 LO |
4708 | ibdev_err(ibdev, |
4709 | "failed to modify QP to RST, ret = %d\n", | |
4710 | ret); | |
926a01dc WHX |
4711 | } |
4712 | ||
626903e9 XW |
4713 | send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL; |
4714 | recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL; | |
926a01dc | 4715 | |
626903e9 | 4716 | spin_lock_irqsave(&hr_dev->qp_list_lock, flags); |
926a01dc WHX |
4717 | hns_roce_lock_cqs(send_cq, recv_cq); |
4718 | ||
bdeacabd | 4719 | if (!udata) { |
626903e9 XW |
4720 | if (recv_cq) |
4721 | __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, | |
4722 | (hr_qp->ibqp.srq ? | |
4723 | to_hr_srq(hr_qp->ibqp.srq) : | |
4724 | NULL)); | |
4725 | ||
4726 | if (send_cq && send_cq != recv_cq) | |
926a01dc | 4727 | __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL); |
626903e9 | 4728 | |
926a01dc WHX |
4729 | } |
4730 | ||
4731 | hns_roce_qp_remove(hr_dev, hr_qp); | |
4732 | ||
4733 | hns_roce_unlock_cqs(send_cq, recv_cq); | |
626903e9 | 4734 | spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags); |
926a01dc | 4735 | |
d302c6e3 | 4736 | return ret; |
926a01dc WHX |
4737 | } |
4738 | ||
c4367a26 | 4739 | static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) |
926a01dc WHX |
4740 | { |
4741 | struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); | |
4742 | struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); | |
4743 | int ret; | |
4744 | ||
bdeacabd | 4745 | ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata); |
d302c6e3 | 4746 | if (ret) |
ae1c6148 LO |
4747 | ibdev_err(&hr_dev->ib_dev, |
4748 | "failed to destroy QP 0x%06lx, ret = %d\n", | |
db50077b | 4749 | hr_qp->qpn, ret); |
926a01dc | 4750 | |
e365b26c | 4751 | hns_roce_qp_destroy(hr_dev, hr_qp, udata); |
926a01dc WHX |
4752 | |
4753 | return 0; | |
4754 | } | |
4755 | ||
aa84fa18 | 4756 | static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, |
ae1c6148 | 4757 | struct hns_roce_qp *hr_qp) |
aa84fa18 | 4758 | { |
ae1c6148 | 4759 | struct ib_device *ibdev = &hr_dev->ib_dev; |
da91ddfd | 4760 | struct hns_roce_sccc_clr_done *resp; |
aa84fa18 YL |
4761 | struct hns_roce_sccc_clr *clr; |
4762 | struct hns_roce_cmq_desc desc; | |
4763 | int ret, i; | |
4764 | ||
4765 | mutex_lock(&hr_dev->qp_table.scc_mutex); | |
4766 | ||
4767 | /* set scc ctx clear done flag */ | |
4768 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false); | |
aa84fa18 YL |
4769 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); |
4770 | if (ret) { | |
ae1c6148 | 4771 | ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret); |
aa84fa18 YL |
4772 | goto out; |
4773 | } | |
4774 | ||
4775 | /* clear scc context */ | |
4776 | hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false); | |
4777 | clr = (struct hns_roce_sccc_clr *)desc.data; | |
4778 | clr->qpn = cpu_to_le32(hr_qp->qpn); | |
4779 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); | |
4780 | if (ret) { | |
ae1c6148 | 4781 | ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret); |
aa84fa18 YL |
4782 | goto out; |
4783 | } | |
4784 | ||
4785 | /* query scc context clear is done or not */ | |
4786 | resp = (struct hns_roce_sccc_clr_done *)desc.data; | |
4787 | for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) { | |
4788 | hns_roce_cmq_setup_basic_desc(&desc, | |
4789 | HNS_ROCE_OPC_QUERY_SCCC, true); | |
4790 | ret = hns_roce_cmq_send(hr_dev, &desc, 1); | |
4791 | if (ret) { | |
ae1c6148 LO |
4792 | ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n", |
4793 | ret); | |
aa84fa18 YL |
4794 | goto out; |
4795 | } | |
4796 | ||
4797 | if (resp->clr_done) | |
4798 | goto out; | |
4799 | ||
4800 | msleep(20); | |
4801 | } | |
4802 | ||
ae1c6148 | 4803 | ibdev_err(ibdev, "Query SCC clr done flag overtime.\n"); |
aa84fa18 YL |
4804 | ret = -ETIMEDOUT; |
4805 | ||
4806 | out: | |
4807 | mutex_unlock(&hr_dev->qp_table.scc_mutex); | |
4808 | return ret; | |
4809 | } | |
4810 | ||
b156269d | 4811 | static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) |
4812 | { | |
4813 | struct hns_roce_dev *hr_dev = to_hr_dev(cq->device); | |
4814 | struct hns_roce_v2_cq_context *cq_context; | |
4815 | struct hns_roce_cq *hr_cq = to_hr_cq(cq); | |
4816 | struct hns_roce_v2_cq_context *cqc_mask; | |
4817 | struct hns_roce_cmd_mailbox *mailbox; | |
4818 | int ret; | |
4819 | ||
4820 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
4821 | if (IS_ERR(mailbox)) | |
4822 | return PTR_ERR(mailbox); | |
4823 | ||
4824 | cq_context = mailbox->buf; | |
4825 | cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1; | |
4826 | ||
4827 | memset(cqc_mask, 0xff, sizeof(*cqc_mask)); | |
4828 | ||
4829 | roce_set_field(cq_context->byte_56_cqe_period_maxcnt, | |
4830 | V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, | |
4831 | cq_count); | |
4832 | roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, | |
4833 | V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S, | |
4834 | 0); | |
4835 | roce_set_field(cq_context->byte_56_cqe_period_maxcnt, | |
4836 | V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, | |
4837 | cq_period); | |
4838 | roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt, | |
4839 | V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S, | |
4840 | 0); | |
4841 | ||
4842 | ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1, | |
4843 | HNS_ROCE_CMD_MODIFY_CQC, | |
4844 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
4845 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
4846 | if (ret) | |
ae1c6148 LO |
4847 | ibdev_err(&hr_dev->ib_dev, |
4848 | "failed to process cmd when modifying CQ, ret = %d\n", | |
4849 | ret); | |
b156269d | 4850 | |
4851 | return ret; | |
4852 | } | |
4853 | ||
0425e3e6 YL |
4854 | static void hns_roce_irq_work_handle(struct work_struct *work) |
4855 | { | |
4856 | struct hns_roce_work *irq_work = | |
4857 | container_of(work, struct hns_roce_work, work); | |
ae1c6148 | 4858 | struct ib_device *ibdev = &irq_work->hr_dev->ib_dev; |
0425e3e6 | 4859 | u32 qpn = irq_work->qpn; |
b00a92c8 | 4860 | u32 cqn = irq_work->cqn; |
0425e3e6 YL |
4861 | |
4862 | switch (irq_work->event_type) { | |
b00a92c8 | 4863 | case HNS_ROCE_EVENT_TYPE_PATH_MIG: |
ae1c6148 | 4864 | ibdev_info(ibdev, "Path migrated succeeded.\n"); |
b00a92c8 | 4865 | break; |
4866 | case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: | |
ae1c6148 | 4867 | ibdev_warn(ibdev, "Path migration failed.\n"); |
b00a92c8 | 4868 | break; |
4869 | case HNS_ROCE_EVENT_TYPE_COMM_EST: | |
b00a92c8 | 4870 | break; |
4871 | case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: | |
ae1c6148 | 4872 | ibdev_warn(ibdev, "Send queue drained.\n"); |
b00a92c8 | 4873 | break; |
0425e3e6 | 4874 | case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: |
ae1c6148 LO |
4875 | ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n", |
4876 | qpn, irq_work->sub_type); | |
b00a92c8 | 4877 | break; |
0425e3e6 | 4878 | case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: |
ae1c6148 LO |
4879 | ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n", |
4880 | qpn); | |
b00a92c8 | 4881 | break; |
0425e3e6 | 4882 | case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: |
ae1c6148 LO |
4883 | ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n", |
4884 | qpn, irq_work->sub_type); | |
b00a92c8 | 4885 | break; |
4886 | case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: | |
ae1c6148 | 4887 | ibdev_warn(ibdev, "SRQ limit reach.\n"); |
b00a92c8 | 4888 | break; |
4889 | case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: | |
ae1c6148 | 4890 | ibdev_warn(ibdev, "SRQ last wqe reach.\n"); |
b00a92c8 | 4891 | break; |
4892 | case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: | |
ae1c6148 | 4893 | ibdev_err(ibdev, "SRQ catas error.\n"); |
b00a92c8 | 4894 | break; |
4895 | case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: | |
ae1c6148 | 4896 | ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn); |
b00a92c8 | 4897 | break; |
4898 | case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: | |
ae1c6148 | 4899 | ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn); |
b00a92c8 | 4900 | break; |
4901 | case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: | |
ae1c6148 | 4902 | ibdev_warn(ibdev, "DB overflow.\n"); |
b00a92c8 | 4903 | break; |
4904 | case HNS_ROCE_EVENT_TYPE_FLR: | |
ae1c6148 | 4905 | ibdev_warn(ibdev, "Function level reset.\n"); |
0425e3e6 YL |
4906 | break; |
4907 | default: | |
4908 | break; | |
4909 | } | |
4910 | ||
4911 | kfree(irq_work); | |
4912 | } | |
4913 | ||
4914 | static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, | |
b00a92c8 | 4915 | struct hns_roce_eq *eq, |
4916 | u32 qpn, u32 cqn) | |
0425e3e6 YL |
4917 | { |
4918 | struct hns_roce_work *irq_work; | |
4919 | ||
4920 | irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC); | |
4921 | if (!irq_work) | |
4922 | return; | |
4923 | ||
4924 | INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle); | |
4925 | irq_work->hr_dev = hr_dev; | |
4926 | irq_work->qpn = qpn; | |
b00a92c8 | 4927 | irq_work->cqn = cqn; |
0425e3e6 YL |
4928 | irq_work->event_type = eq->event_type; |
4929 | irq_work->sub_type = eq->sub_type; | |
4930 | queue_work(hr_dev->irq_workq, &(irq_work->work)); | |
4931 | } | |
4932 | ||
a5073d60 YL |
4933 | static void set_eq_cons_index_v2(struct hns_roce_eq *eq) |
4934 | { | |
d3743fa9 | 4935 | struct hns_roce_dev *hr_dev = eq->hr_dev; |
880f133c | 4936 | __le32 doorbell[2] = {}; |
a5073d60 YL |
4937 | |
4938 | if (eq->type_flag == HNS_ROCE_AEQ) { | |
4939 | roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, | |
4940 | HNS_ROCE_V2_EQ_DB_CMD_S, | |
4941 | eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? | |
4942 | HNS_ROCE_EQ_DB_CMD_AEQ : | |
4943 | HNS_ROCE_EQ_DB_CMD_AEQ_ARMED); | |
4944 | } else { | |
4945 | roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M, | |
4946 | HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn); | |
4947 | ||
4948 | roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M, | |
4949 | HNS_ROCE_V2_EQ_DB_CMD_S, | |
4950 | eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ? | |
4951 | HNS_ROCE_EQ_DB_CMD_CEQ : | |
4952 | HNS_ROCE_EQ_DB_CMD_CEQ_ARMED); | |
4953 | } | |
4954 | ||
4955 | roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M, | |
4956 | HNS_ROCE_V2_EQ_DB_PARA_S, | |
4957 | (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M)); | |
4958 | ||
d3743fa9 | 4959 | hns_roce_write64(hr_dev, doorbell, eq->doorbell); |
a5073d60 YL |
4960 | } |
4961 | ||
a5073d60 YL |
4962 | static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) |
4963 | { | |
4964 | struct hns_roce_aeqe *aeqe; | |
4965 | ||
477a0a38 | 4966 | aeqe = hns_roce_buf_offset(eq->mtr.kmem, |
cc23267a XW |
4967 | (eq->cons_index & (eq->entries - 1)) * |
4968 | HNS_ROCE_AEQ_ENTRY_SIZE); | |
4969 | ||
a5073d60 YL |
4970 | return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^ |
4971 | !!(eq->cons_index & eq->entries)) ? aeqe : NULL; | |
4972 | } | |
4973 | ||
4974 | static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, | |
4975 | struct hns_roce_eq *eq) | |
4976 | { | |
4977 | struct device *dev = hr_dev->dev; | |
e7f40440 | 4978 | struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq); |
a5073d60 YL |
4979 | int aeqe_found = 0; |
4980 | int event_type; | |
0425e3e6 | 4981 | int sub_type; |
81fce629 | 4982 | u32 srqn; |
0425e3e6 YL |
4983 | u32 qpn; |
4984 | u32 cqn; | |
a5073d60 | 4985 | |
e7f40440 | 4986 | while (aeqe) { |
4044a3f4 YL |
4987 | /* Make sure we read AEQ entry after we have checked the |
4988 | * ownership bit | |
4989 | */ | |
4990 | dma_rmb(); | |
a5073d60 YL |
4991 | |
4992 | event_type = roce_get_field(aeqe->asyn, | |
4993 | HNS_ROCE_V2_AEQE_EVENT_TYPE_M, | |
4994 | HNS_ROCE_V2_AEQE_EVENT_TYPE_S); | |
0425e3e6 YL |
4995 | sub_type = roce_get_field(aeqe->asyn, |
4996 | HNS_ROCE_V2_AEQE_SUB_TYPE_M, | |
4997 | HNS_ROCE_V2_AEQE_SUB_TYPE_S); | |
4998 | qpn = roce_get_field(aeqe->event.qp_event.qp, | |
4999 | HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, | |
5000 | HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); | |
5001 | cqn = roce_get_field(aeqe->event.cq_event.cq, | |
5002 | HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, | |
5003 | HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); | |
81fce629 LO |
5004 | srqn = roce_get_field(aeqe->event.srq_event.srq, |
5005 | HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M, | |
5006 | HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S); | |
a5073d60 YL |
5007 | |
5008 | switch (event_type) { | |
5009 | case HNS_ROCE_EVENT_TYPE_PATH_MIG: | |
a5073d60 | 5010 | case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED: |
a5073d60 YL |
5011 | case HNS_ROCE_EVENT_TYPE_COMM_EST: |
5012 | case HNS_ROCE_EVENT_TYPE_SQ_DRAINED: | |
5013 | case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR: | |
81fce629 | 5014 | case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH: |
a5073d60 YL |
5015 | case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR: |
5016 | case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR: | |
b00a92c8 | 5017 | hns_roce_qp_event(hr_dev, qpn, event_type); |
a5073d60 YL |
5018 | break; |
5019 | case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH: | |
a5073d60 | 5020 | case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: |
81fce629 | 5021 | hns_roce_srq_event(hr_dev, srqn, event_type); |
a5073d60 YL |
5022 | break; |
5023 | case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR: | |
5024 | case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW: | |
b00a92c8 | 5025 | hns_roce_cq_event(hr_dev, cqn, event_type); |
a5073d60 YL |
5026 | break; |
5027 | case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW: | |
a5073d60 YL |
5028 | break; |
5029 | case HNS_ROCE_EVENT_TYPE_MB: | |
5030 | hns_roce_cmd_event(hr_dev, | |
5031 | le16_to_cpu(aeqe->event.cmd.token), | |
5032 | aeqe->event.cmd.status, | |
5033 | le64_to_cpu(aeqe->event.cmd.out_param)); | |
5034 | break; | |
5035 | case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW: | |
a5073d60 YL |
5036 | break; |
5037 | case HNS_ROCE_EVENT_TYPE_FLR: | |
a5073d60 YL |
5038 | break; |
5039 | default: | |
5040 | dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n", | |
5041 | event_type, eq->eqn, eq->cons_index); | |
5042 | break; | |
790b57f6 | 5043 | } |
a5073d60 | 5044 | |
0425e3e6 YL |
5045 | eq->event_type = event_type; |
5046 | eq->sub_type = sub_type; | |
a5073d60 YL |
5047 | ++eq->cons_index; |
5048 | aeqe_found = 1; | |
5049 | ||
249f2f92 | 5050 | if (eq->cons_index > (2 * eq->entries - 1)) |
a5073d60 | 5051 | eq->cons_index = 0; |
249f2f92 | 5052 | |
b00a92c8 | 5053 | hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn); |
e7f40440 LC |
5054 | |
5055 | aeqe = next_aeqe_sw_v2(eq); | |
a5073d60 YL |
5056 | } |
5057 | ||
5058 | set_eq_cons_index_v2(eq); | |
5059 | return aeqe_found; | |
5060 | } | |
5061 | ||
a5073d60 YL |
5062 | static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) |
5063 | { | |
5064 | struct hns_roce_ceqe *ceqe; | |
5065 | ||
477a0a38 | 5066 | ceqe = hns_roce_buf_offset(eq->mtr.kmem, |
cc23267a XW |
5067 | (eq->cons_index & (eq->entries - 1)) * |
5068 | HNS_ROCE_CEQ_ENTRY_SIZE); | |
a5073d60 YL |
5069 | return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^ |
5070 | (!!(eq->cons_index & eq->entries)) ? ceqe : NULL; | |
5071 | } | |
5072 | ||
5073 | static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev, | |
5074 | struct hns_roce_eq *eq) | |
5075 | { | |
e7f40440 | 5076 | struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq); |
a5073d60 YL |
5077 | int ceqe_found = 0; |
5078 | u32 cqn; | |
5079 | ||
e7f40440 | 5080 | while (ceqe) { |
4044a3f4 YL |
5081 | /* Make sure we read CEQ entry after we have checked the |
5082 | * ownership bit | |
5083 | */ | |
5084 | dma_rmb(); | |
5085 | ||
60262b10 | 5086 | cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M, |
a5073d60 YL |
5087 | HNS_ROCE_V2_CEQE_COMP_CQN_S); |
5088 | ||
5089 | hns_roce_cq_completion(hr_dev, cqn); | |
5090 | ||
5091 | ++eq->cons_index; | |
5092 | ceqe_found = 1; | |
5093 | ||
bceda6e6 | 5094 | if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1)) |
a5073d60 | 5095 | eq->cons_index = 0; |
e7f40440 LC |
5096 | |
5097 | ceqe = next_ceqe_sw_v2(eq); | |
a5073d60 YL |
5098 | } |
5099 | ||
5100 | set_eq_cons_index_v2(eq); | |
5101 | ||
5102 | return ceqe_found; | |
5103 | } | |
5104 | ||
5105 | static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) | |
5106 | { | |
5107 | struct hns_roce_eq *eq = eq_ptr; | |
5108 | struct hns_roce_dev *hr_dev = eq->hr_dev; | |
5109 | int int_work = 0; | |
5110 | ||
5111 | if (eq->type_flag == HNS_ROCE_CEQ) | |
5112 | /* Completion event interrupt */ | |
5113 | int_work = hns_roce_v2_ceq_int(hr_dev, eq); | |
5114 | else | |
5115 | /* Asychronous event interrupt */ | |
5116 | int_work = hns_roce_v2_aeq_int(hr_dev, eq); | |
5117 | ||
5118 | return IRQ_RETVAL(int_work); | |
5119 | } | |
5120 | ||
5121 | static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) | |
5122 | { | |
5123 | struct hns_roce_dev *hr_dev = dev_id; | |
5124 | struct device *dev = hr_dev->dev; | |
5125 | int int_work = 0; | |
5126 | u32 int_st; | |
5127 | u32 int_en; | |
5128 | ||
5129 | /* Abnormal interrupt */ | |
5130 | int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG); | |
5131 | int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG); | |
5132 | ||
bfe86035 | 5133 | if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) { |
2b9acb9a XT |
5134 | struct pci_dev *pdev = hr_dev->pci_dev; |
5135 | struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); | |
5136 | const struct hnae3_ae_ops *ops = ae_dev->ops; | |
5137 | ||
a5073d60 YL |
5138 | dev_err(dev, "AEQ overflow!\n"); |
5139 | ||
bfe86035 | 5140 | int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S; |
a5073d60 YL |
5141 | roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); |
5142 | ||
2b9acb9a XT |
5143 | /* Set reset level for reset_event() */ |
5144 | if (ops->set_default_reset_request) | |
5145 | ops->set_default_reset_request(ae_dev, | |
5146 | HNAE3_FUNC_RESET); | |
5147 | if (ops->reset_event) | |
5148 | ops->reset_event(pdev, NULL); | |
5149 | ||
bfe86035 | 5150 | int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; |
a5073d60 YL |
5151 | roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); |
5152 | ||
5153 | int_work = 1; | |
bfe86035 | 5154 | } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) { |
a5073d60 YL |
5155 | dev_err(dev, "BUS ERR!\n"); |
5156 | ||
bfe86035 | 5157 | int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S; |
a5073d60 YL |
5158 | roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); |
5159 | ||
bfe86035 | 5160 | int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; |
a5073d60 YL |
5161 | roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); |
5162 | ||
5163 | int_work = 1; | |
bfe86035 | 5164 | } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) { |
a5073d60 YL |
5165 | dev_err(dev, "OTHER ERR!\n"); |
5166 | ||
bfe86035 | 5167 | int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S; |
a5073d60 YL |
5168 | roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st); |
5169 | ||
bfe86035 | 5170 | int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S; |
a5073d60 YL |
5171 | roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en); |
5172 | ||
5173 | int_work = 1; | |
5174 | } else | |
5175 | dev_err(dev, "There is no abnormal irq found!\n"); | |
5176 | ||
5177 | return IRQ_RETVAL(int_work); | |
5178 | } | |
5179 | ||
5180 | static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, | |
5181 | int eq_num, int enable_flag) | |
5182 | { | |
5183 | int i; | |
5184 | ||
5185 | if (enable_flag == EQ_ENABLE) { | |
5186 | for (i = 0; i < eq_num; i++) | |
5187 | roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + | |
5188 | i * EQ_REG_OFFSET, | |
5189 | HNS_ROCE_V2_VF_EVENT_INT_EN_M); | |
5190 | ||
5191 | roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, | |
5192 | HNS_ROCE_V2_VF_ABN_INT_EN_M); | |
5193 | roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, | |
5194 | HNS_ROCE_V2_VF_ABN_INT_CFG_M); | |
5195 | } else { | |
5196 | for (i = 0; i < eq_num; i++) | |
5197 | roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG + | |
5198 | i * EQ_REG_OFFSET, | |
5199 | HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0); | |
5200 | ||
5201 | roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, | |
5202 | HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0); | |
5203 | roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, | |
5204 | HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0); | |
5205 | } | |
5206 | } | |
5207 | ||
5208 | static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn) | |
5209 | { | |
5210 | struct device *dev = hr_dev->dev; | |
5211 | int ret; | |
5212 | ||
5213 | if (eqn < hr_dev->caps.num_comp_vectors) | |
5214 | ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, | |
5215 | 0, HNS_ROCE_CMD_DESTROY_CEQC, | |
5216 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
5217 | else | |
5218 | ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M, | |
5219 | 0, HNS_ROCE_CMD_DESTROY_AEQC, | |
5220 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
5221 | if (ret) | |
5222 | dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn); | |
5223 | } | |
5224 | ||
d7e2d343 | 5225 | static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) |
a5073d60 | 5226 | { |
477a0a38 | 5227 | hns_roce_mtr_destroy(hr_dev, &eq->mtr); |
a5073d60 YL |
5228 | } |
5229 | ||
477a0a38 XW |
5230 | static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, |
5231 | void *mb_buf) | |
a5073d60 | 5232 | { |
477a0a38 | 5233 | u64 eqe_ba[MTT_MIN_COUNT] = { 0 }; |
a5073d60 | 5234 | struct hns_roce_eq_context *eqc; |
477a0a38 | 5235 | u64 bt_ba = 0; |
d7e2d343 | 5236 | int count; |
a5073d60 YL |
5237 | |
5238 | eqc = mb_buf; | |
5239 | memset(eqc, 0, sizeof(struct hns_roce_eq_context)); | |
5240 | ||
5241 | /* init eqc */ | |
5242 | eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG; | |
a5073d60 YL |
5243 | eq->cons_index = 0; |
5244 | eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0; | |
5245 | eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0; | |
5246 | eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED; | |
a5073d60 YL |
5247 | eq->shift = ilog2((unsigned int)eq->entries); |
5248 | ||
cc23267a | 5249 | /* if not multi-hop, eqe buffer only use one trunk */ |
477a0a38 XW |
5250 | count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT, |
5251 | &bt_ba); | |
5252 | if (count < 1) { | |
5253 | dev_err(hr_dev->dev, "failed to find EQE mtr\n"); | |
5254 | return -ENOBUFS; | |
d7e2d343 | 5255 | } |
a5073d60 YL |
5256 | |
5257 | /* set eqc state */ | |
60262b10 | 5258 | roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S, |
a5073d60 YL |
5259 | HNS_ROCE_V2_EQ_STATE_VALID); |
5260 | ||
5261 | /* set eqe hop num */ | |
60262b10 | 5262 | roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M, |
a5073d60 YL |
5263 | HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num); |
5264 | ||
5265 | /* set eqc over_ignore */ | |
60262b10 | 5266 | roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M, |
a5073d60 YL |
5267 | HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore); |
5268 | ||
5269 | /* set eqc coalesce */ | |
60262b10 | 5270 | roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M, |
a5073d60 YL |
5271 | HNS_ROCE_EQC_COALESCE_S, eq->coalesce); |
5272 | ||
5273 | /* set eqc arm_state */ | |
60262b10 | 5274 | roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M, |
a5073d60 YL |
5275 | HNS_ROCE_EQC_ARM_ST_S, eq->arm_st); |
5276 | ||
5277 | /* set eqn */ | |
60262b10 LO |
5278 | roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S, |
5279 | eq->eqn); | |
a5073d60 YL |
5280 | |
5281 | /* set eqe_cnt */ | |
60262b10 LO |
5282 | roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M, |
5283 | HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT); | |
a5073d60 YL |
5284 | |
5285 | /* set eqe_ba_pg_sz */ | |
60262b10 | 5286 | roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M, |
5e6e78db | 5287 | HNS_ROCE_EQC_BA_PG_SZ_S, |
477a0a38 | 5288 | to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift)); |
a5073d60 YL |
5289 | |
5290 | /* set eqe_buf_pg_sz */ | |
60262b10 | 5291 | roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M, |
5e6e78db | 5292 | HNS_ROCE_EQC_BUF_PG_SZ_S, |
477a0a38 | 5293 | to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift)); |
a5073d60 YL |
5294 | |
5295 | /* set eq_producer_idx */ | |
60262b10 LO |
5296 | roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M, |
5297 | HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX); | |
a5073d60 YL |
5298 | |
5299 | /* set eq_max_cnt */ | |
60262b10 | 5300 | roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M, |
a5073d60 YL |
5301 | HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt); |
5302 | ||
5303 | /* set eq_period */ | |
60262b10 | 5304 | roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M, |
a5073d60 YL |
5305 | HNS_ROCE_EQC_PERIOD_S, eq->eq_period); |
5306 | ||
5307 | /* set eqe_report_timer */ | |
60262b10 | 5308 | roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M, |
a5073d60 YL |
5309 | HNS_ROCE_EQC_REPORT_TIMER_S, |
5310 | HNS_ROCE_EQ_INIT_REPORT_TIMER); | |
5311 | ||
477a0a38 | 5312 | /* set bt_ba [34:3] */ |
60262b10 | 5313 | roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M, |
477a0a38 | 5314 | HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3); |
a5073d60 | 5315 | |
477a0a38 | 5316 | /* set bt_ba [64:35] */ |
60262b10 | 5317 | roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M, |
477a0a38 | 5318 | HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35); |
a5073d60 YL |
5319 | |
5320 | /* set eq shift */ | |
60262b10 LO |
5321 | roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S, |
5322 | eq->shift); | |
a5073d60 YL |
5323 | |
5324 | /* set eq MSI_IDX */ | |
60262b10 LO |
5325 | roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M, |
5326 | HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX); | |
a5073d60 YL |
5327 | |
5328 | /* set cur_eqe_ba [27:12] */ | |
60262b10 | 5329 | roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M, |
477a0a38 | 5330 | HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12); |
a5073d60 YL |
5331 | |
5332 | /* set cur_eqe_ba [59:28] */ | |
60262b10 | 5333 | roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M, |
477a0a38 | 5334 | HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28); |
a5073d60 YL |
5335 | |
5336 | /* set cur_eqe_ba [63:60] */ | |
60262b10 | 5337 | roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M, |
477a0a38 | 5338 | HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60); |
a5073d60 YL |
5339 | |
5340 | /* set eq consumer idx */ | |
60262b10 LO |
5341 | roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M, |
5342 | HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX); | |
a5073d60 YL |
5343 | |
5344 | /* set nex_eqe_ba[43:12] */ | |
60262b10 | 5345 | roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M, |
477a0a38 | 5346 | HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12); |
a5073d60 YL |
5347 | |
5348 | /* set nex_eqe_ba[63:44] */ | |
60262b10 | 5349 | roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M, |
477a0a38 | 5350 | HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44); |
a5073d60 | 5351 | |
477a0a38 | 5352 | return 0; |
d7e2d343 | 5353 | } |
a5073d60 | 5354 | |
d7e2d343 XW |
5355 | static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) |
5356 | { | |
477a0a38 XW |
5357 | struct hns_roce_buf_attr buf_attr = {}; |
5358 | int err; | |
a5073d60 | 5359 | |
477a0a38 XW |
5360 | if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0) |
5361 | eq->hop_num = 0; | |
5362 | else | |
5363 | eq->hop_num = hr_dev->caps.eqe_hop_num; | |
a5073d60 | 5364 | |
477a0a38 XW |
5365 | buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + PAGE_ADDR_SHIFT; |
5366 | buf_attr.region[0].size = eq->entries * eq->eqe_size; | |
5367 | buf_attr.region[0].hopnum = eq->hop_num; | |
5368 | buf_attr.region_count = 1; | |
5369 | buf_attr.fixed_page = true; | |
d7e2d343 | 5370 | |
477a0a38 XW |
5371 | err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr, |
5372 | hr_dev->caps.srqwqe_ba_pg_sz + | |
5373 | PAGE_ADDR_SHIFT, NULL, 0); | |
5374 | if (err) | |
5375 | dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err); | |
a5073d60 | 5376 | |
477a0a38 | 5377 | return err; |
a5073d60 YL |
5378 | } |
5379 | ||
5380 | static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, | |
5381 | struct hns_roce_eq *eq, | |
5382 | unsigned int eq_cmd) | |
5383 | { | |
a5073d60 | 5384 | struct hns_roce_cmd_mailbox *mailbox; |
a5073d60 YL |
5385 | int ret; |
5386 | ||
5387 | /* Allocate mailbox memory */ | |
5388 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
477a0a38 XW |
5389 | if (IS_ERR_OR_NULL(mailbox)) |
5390 | return -ENOMEM; | |
a5073d60 | 5391 | |
d7e2d343 | 5392 | ret = alloc_eq_buf(hr_dev, eq); |
477a0a38 | 5393 | if (ret) |
d7e2d343 | 5394 | goto free_cmd_mbox; |
477a0a38 XW |
5395 | |
5396 | ret = config_eqc(hr_dev, eq, mailbox->buf); | |
5397 | if (ret) | |
5398 | goto err_cmd_mbox; | |
a5073d60 YL |
5399 | |
5400 | ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0, | |
5401 | eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS); | |
5402 | if (ret) { | |
d7e2d343 | 5403 | dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n"); |
a5073d60 YL |
5404 | goto err_cmd_mbox; |
5405 | } | |
5406 | ||
5407 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
5408 | ||
5409 | return 0; | |
5410 | ||
5411 | err_cmd_mbox: | |
d7e2d343 | 5412 | free_eq_buf(hr_dev, eq); |
a5073d60 YL |
5413 | |
5414 | free_cmd_mbox: | |
5415 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
5416 | ||
5417 | return ret; | |
5418 | } | |
5419 | ||
33db6f94 YL |
5420 | static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, |
5421 | int comp_num, int aeq_num, int other_num) | |
5422 | { | |
5423 | struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; | |
5424 | int i, j; | |
5425 | int ret; | |
5426 | ||
5427 | for (i = 0; i < irq_num; i++) { | |
5428 | hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN, | |
5429 | GFP_KERNEL); | |
5430 | if (!hr_dev->irq_names[i]) { | |
5431 | ret = -ENOMEM; | |
5432 | goto err_kzalloc_failed; | |
5433 | } | |
5434 | } | |
5435 | ||
6def7de6 | 5436 | /* irq contains: abnormal + AEQ + CEQ */ |
bebdb83f | 5437 | for (j = 0; j < other_num; j++) |
60262b10 LO |
5438 | snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, |
5439 | "hns-abn-%d", j); | |
bebdb83f LC |
5440 | |
5441 | for (j = other_num; j < (other_num + aeq_num); j++) | |
60262b10 LO |
5442 | snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, |
5443 | "hns-aeq-%d", j - other_num); | |
bebdb83f LC |
5444 | |
5445 | for (j = (other_num + aeq_num); j < irq_num; j++) | |
60262b10 LO |
5446 | snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN, |
5447 | "hns-ceq-%d", j - other_num - aeq_num); | |
33db6f94 YL |
5448 | |
5449 | for (j = 0; j < irq_num; j++) { | |
5450 | if (j < other_num) | |
5451 | ret = request_irq(hr_dev->irq[j], | |
5452 | hns_roce_v2_msix_interrupt_abn, | |
5453 | 0, hr_dev->irq_names[j], hr_dev); | |
5454 | ||
5455 | else if (j < (other_num + comp_num)) | |
5456 | ret = request_irq(eq_table->eq[j - other_num].irq, | |
5457 | hns_roce_v2_msix_interrupt_eq, | |
5458 | 0, hr_dev->irq_names[j + aeq_num], | |
5459 | &eq_table->eq[j - other_num]); | |
5460 | else | |
5461 | ret = request_irq(eq_table->eq[j - other_num].irq, | |
5462 | hns_roce_v2_msix_interrupt_eq, | |
5463 | 0, hr_dev->irq_names[j - comp_num], | |
5464 | &eq_table->eq[j - other_num]); | |
5465 | if (ret) { | |
5466 | dev_err(hr_dev->dev, "Request irq error!\n"); | |
5467 | goto err_request_failed; | |
5468 | } | |
5469 | } | |
5470 | ||
5471 | return 0; | |
5472 | ||
5473 | err_request_failed: | |
5474 | for (j -= 1; j >= 0; j--) | |
5475 | if (j < other_num) | |
5476 | free_irq(hr_dev->irq[j], hr_dev); | |
5477 | else | |
5478 | free_irq(eq_table->eq[j - other_num].irq, | |
5479 | &eq_table->eq[j - other_num]); | |
5480 | ||
5481 | err_kzalloc_failed: | |
5482 | for (i -= 1; i >= 0; i--) | |
5483 | kfree(hr_dev->irq_names[i]); | |
5484 | ||
5485 | return ret; | |
5486 | } | |
5487 | ||
5488 | static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) | |
5489 | { | |
5490 | int irq_num; | |
5491 | int eq_num; | |
5492 | int i; | |
5493 | ||
5494 | eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; | |
5495 | irq_num = eq_num + hr_dev->caps.num_other_vectors; | |
5496 | ||
5497 | for (i = 0; i < hr_dev->caps.num_other_vectors; i++) | |
5498 | free_irq(hr_dev->irq[i], hr_dev); | |
5499 | ||
5500 | for (i = 0; i < eq_num; i++) | |
5501 | free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]); | |
5502 | ||
5503 | for (i = 0; i < irq_num; i++) | |
5504 | kfree(hr_dev->irq_names[i]); | |
5505 | } | |
5506 | ||
a5073d60 YL |
5507 | static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) |
5508 | { | |
5509 | struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; | |
5510 | struct device *dev = hr_dev->dev; | |
5511 | struct hns_roce_eq *eq; | |
5512 | unsigned int eq_cmd; | |
5513 | int irq_num; | |
5514 | int eq_num; | |
5515 | int other_num; | |
5516 | int comp_num; | |
5517 | int aeq_num; | |
33db6f94 | 5518 | int i; |
a5073d60 YL |
5519 | int ret; |
5520 | ||
5521 | other_num = hr_dev->caps.num_other_vectors; | |
5522 | comp_num = hr_dev->caps.num_comp_vectors; | |
5523 | aeq_num = hr_dev->caps.num_aeq_vectors; | |
5524 | ||
5525 | eq_num = comp_num + aeq_num; | |
5526 | irq_num = eq_num + other_num; | |
5527 | ||
5528 | eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL); | |
5529 | if (!eq_table->eq) | |
5530 | return -ENOMEM; | |
5531 | ||
a5073d60 | 5532 | /* create eq */ |
33db6f94 YL |
5533 | for (i = 0; i < eq_num; i++) { |
5534 | eq = &eq_table->eq[i]; | |
a5073d60 | 5535 | eq->hr_dev = hr_dev; |
33db6f94 YL |
5536 | eq->eqn = i; |
5537 | if (i < comp_num) { | |
a5073d60 YL |
5538 | /* CEQ */ |
5539 | eq_cmd = HNS_ROCE_CMD_CREATE_CEQC; | |
5540 | eq->type_flag = HNS_ROCE_CEQ; | |
5541 | eq->entries = hr_dev->caps.ceqe_depth; | |
5542 | eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE; | |
33db6f94 | 5543 | eq->irq = hr_dev->irq[i + other_num + aeq_num]; |
a5073d60 YL |
5544 | eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM; |
5545 | eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL; | |
5546 | } else { | |
5547 | /* AEQ */ | |
5548 | eq_cmd = HNS_ROCE_CMD_CREATE_AEQC; | |
5549 | eq->type_flag = HNS_ROCE_AEQ; | |
5550 | eq->entries = hr_dev->caps.aeqe_depth; | |
5551 | eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE; | |
33db6f94 | 5552 | eq->irq = hr_dev->irq[i - comp_num + other_num]; |
a5073d60 YL |
5553 | eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM; |
5554 | eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL; | |
5555 | } | |
5556 | ||
5557 | ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd); | |
5558 | if (ret) { | |
5559 | dev_err(dev, "eq create failed.\n"); | |
5560 | goto err_create_eq_fail; | |
5561 | } | |
5562 | } | |
5563 | ||
5564 | /* enable irq */ | |
5565 | hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE); | |
5566 | ||
33db6f94 YL |
5567 | ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num, |
5568 | aeq_num, other_num); | |
5569 | if (ret) { | |
5570 | dev_err(dev, "Request irq failed.\n"); | |
5571 | goto err_request_irq_fail; | |
a5073d60 YL |
5572 | } |
5573 | ||
ffd541d4 | 5574 | hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0); |
0425e3e6 YL |
5575 | if (!hr_dev->irq_workq) { |
5576 | dev_err(dev, "Create irq workqueue failed!\n"); | |
f1a31542 | 5577 | ret = -ENOMEM; |
33db6f94 | 5578 | goto err_create_wq_fail; |
0425e3e6 YL |
5579 | } |
5580 | ||
a5073d60 YL |
5581 | return 0; |
5582 | ||
33db6f94 YL |
5583 | err_create_wq_fail: |
5584 | __hns_roce_free_irq(hr_dev); | |
5585 | ||
a5073d60 | 5586 | err_request_irq_fail: |
33db6f94 | 5587 | hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); |
a5073d60 YL |
5588 | |
5589 | err_create_eq_fail: | |
a5073d60 | 5590 | for (i -= 1; i >= 0; i--) |
d7e2d343 | 5591 | free_eq_buf(hr_dev, &eq_table->eq[i]); |
a5073d60 YL |
5592 | kfree(eq_table->eq); |
5593 | ||
5594 | return ret; | |
5595 | } | |
5596 | ||
5597 | static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) | |
5598 | { | |
5599 | struct hns_roce_eq_table *eq_table = &hr_dev->eq_table; | |
a5073d60 YL |
5600 | int eq_num; |
5601 | int i; | |
5602 | ||
5603 | eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors; | |
a5073d60 YL |
5604 | |
5605 | /* Disable irq */ | |
5606 | hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE); | |
5607 | ||
33db6f94 | 5608 | __hns_roce_free_irq(hr_dev); |
a5073d60 YL |
5609 | |
5610 | for (i = 0; i < eq_num; i++) { | |
5611 | hns_roce_v2_destroy_eqc(hr_dev, i); | |
5612 | ||
d7e2d343 | 5613 | free_eq_buf(hr_dev, &eq_table->eq[i]); |
a5073d60 YL |
5614 | } |
5615 | ||
a5073d60 | 5616 | kfree(eq_table->eq); |
0425e3e6 YL |
5617 | |
5618 | flush_workqueue(hr_dev->irq_workq); | |
5619 | destroy_workqueue(hr_dev->irq_workq); | |
a5073d60 YL |
5620 | } |
5621 | ||
c7bcb134 LO |
5622 | static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev, |
5623 | struct hns_roce_srq *srq, u32 pdn, u16 xrcd, | |
5624 | u32 cqn, void *mb_buf, u64 *mtts_wqe, | |
5625 | u64 *mtts_idx, dma_addr_t dma_handle_wqe, | |
5626 | dma_addr_t dma_handle_idx) | |
5627 | { | |
5628 | struct hns_roce_srq_context *srq_context; | |
5629 | ||
5630 | srq_context = mb_buf; | |
5631 | memset(srq_context, 0, sizeof(*srq_context)); | |
5632 | ||
5633 | roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M, | |
5634 | SRQC_BYTE_4_SRQ_ST_S, 1); | |
5635 | ||
5636 | roce_set_field(srq_context->byte_4_srqn_srqst, | |
5637 | SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M, | |
5638 | SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S, | |
5639 | (hr_dev->caps.srqwqe_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : | |
5640 | hr_dev->caps.srqwqe_hop_num)); | |
5641 | roce_set_field(srq_context->byte_4_srqn_srqst, | |
5642 | SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S, | |
d938d785 | 5643 | ilog2(srq->wqe_cnt)); |
c7bcb134 LO |
5644 | |
5645 | roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M, | |
5646 | SRQC_BYTE_4_SRQN_S, srq->srqn); | |
5647 | ||
5648 | roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M, | |
5649 | SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); | |
5650 | ||
5651 | roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M, | |
5652 | SRQC_BYTE_12_SRQ_XRCD_S, xrcd); | |
5653 | ||
5654 | srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3)); | |
5655 | ||
5656 | roce_set_field(srq_context->byte_24_wqe_bt_ba, | |
5657 | SRQC_BYTE_24_SRQ_WQE_BT_BA_M, | |
5658 | SRQC_BYTE_24_SRQ_WQE_BT_BA_S, | |
bfe86035 | 5659 | dma_handle_wqe >> 35); |
c7bcb134 LO |
5660 | |
5661 | roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M, | |
5662 | SRQC_BYTE_28_PD_S, pdn); | |
5663 | roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M, | |
5664 | SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 : | |
5665 | fls(srq->max_gs - 1)); | |
5666 | ||
bfe86035 | 5667 | srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3); |
c7bcb134 LO |
5668 | roce_set_field(srq_context->rsv_idx_bt_ba, |
5669 | SRQC_BYTE_36_SRQ_IDX_BT_BA_M, | |
5670 | SRQC_BYTE_36_SRQ_IDX_BT_BA_S, | |
bfe86035 | 5671 | dma_handle_idx >> 35); |
c7bcb134 | 5672 | |
c7bcb134 | 5673 | srq_context->idx_cur_blk_addr = |
6fd610c5 | 5674 | cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0])); |
c7bcb134 LO |
5675 | roce_set_field(srq_context->byte_44_idxbufpgsz_addr, |
5676 | SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M, | |
5677 | SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S, | |
6fd610c5 | 5678 | upper_32_bits(to_hr_hw_page_addr(mtts_idx[0]))); |
c7bcb134 LO |
5679 | roce_set_field(srq_context->byte_44_idxbufpgsz_addr, |
5680 | SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M, | |
5681 | SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S, | |
5682 | hr_dev->caps.idx_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : | |
5683 | hr_dev->caps.idx_hop_num); | |
5684 | ||
6fd610c5 XW |
5685 | roce_set_field( |
5686 | srq_context->byte_44_idxbufpgsz_addr, | |
5687 | SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M, | |
5688 | SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S, | |
5689 | to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift)); | |
5690 | roce_set_field( | |
5691 | srq_context->byte_44_idxbufpgsz_addr, | |
5692 | SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M, | |
5693 | SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S, | |
5694 | to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift)); | |
c7bcb134 | 5695 | |
c7bcb134 | 5696 | srq_context->idx_nxt_blk_addr = |
6fd610c5 | 5697 | cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1])); |
c7bcb134 LO |
5698 | roce_set_field(srq_context->rsv_idxnxtblkaddr, |
5699 | SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M, | |
5700 | SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S, | |
6fd610c5 | 5701 | upper_32_bits(to_hr_hw_page_addr(mtts_idx[1]))); |
c7bcb134 LO |
5702 | roce_set_field(srq_context->byte_56_xrc_cqn, |
5703 | SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S, | |
5704 | cqn); | |
5705 | roce_set_field(srq_context->byte_56_xrc_cqn, | |
5706 | SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M, | |
5707 | SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S, | |
6fd610c5 | 5708 | to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift)); |
c7bcb134 LO |
5709 | roce_set_field(srq_context->byte_56_xrc_cqn, |
5710 | SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M, | |
5711 | SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S, | |
6fd610c5 | 5712 | to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift)); |
c7bcb134 LO |
5713 | |
5714 | roce_set_bit(srq_context->db_record_addr_record_en, | |
5715 | SRQC_BYTE_60_SRQ_RECORD_EN_S, 0); | |
5716 | } | |
5717 | ||
5718 | static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, | |
5719 | struct ib_srq_attr *srq_attr, | |
5720 | enum ib_srq_attr_mask srq_attr_mask, | |
5721 | struct ib_udata *udata) | |
5722 | { | |
5723 | struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); | |
5724 | struct hns_roce_srq *srq = to_hr_srq(ibsrq); | |
5725 | struct hns_roce_srq_context *srq_context; | |
5726 | struct hns_roce_srq_context *srqc_mask; | |
5727 | struct hns_roce_cmd_mailbox *mailbox; | |
5728 | int ret; | |
5729 | ||
5730 | if (srq_attr_mask & IB_SRQ_LIMIT) { | |
d938d785 | 5731 | if (srq_attr->srq_limit >= srq->wqe_cnt) |
c7bcb134 LO |
5732 | return -EINVAL; |
5733 | ||
5734 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
5735 | if (IS_ERR(mailbox)) | |
5736 | return PTR_ERR(mailbox); | |
5737 | ||
5738 | srq_context = mailbox->buf; | |
5739 | srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1; | |
5740 | ||
5741 | memset(srqc_mask, 0xff, sizeof(*srqc_mask)); | |
5742 | ||
5743 | roce_set_field(srq_context->byte_8_limit_wl, | |
5744 | SRQC_BYTE_8_SRQ_LIMIT_WL_M, | |
5745 | SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit); | |
5746 | roce_set_field(srqc_mask->byte_8_limit_wl, | |
5747 | SRQC_BYTE_8_SRQ_LIMIT_WL_M, | |
5748 | SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0); | |
5749 | ||
5750 | ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0, | |
5751 | HNS_ROCE_CMD_MODIFY_SRQC, | |
5752 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
5753 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
5754 | if (ret) { | |
ae1c6148 LO |
5755 | ibdev_err(&hr_dev->ib_dev, |
5756 | "failed to process cmd when modifying SRQ, ret = %d\n", | |
5757 | ret); | |
c7bcb134 LO |
5758 | return ret; |
5759 | } | |
5760 | } | |
5761 | ||
5762 | return 0; | |
5763 | } | |
5764 | ||
c3c668e7 | 5765 | static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) |
c7bcb134 LO |
5766 | { |
5767 | struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); | |
5768 | struct hns_roce_srq *srq = to_hr_srq(ibsrq); | |
5769 | struct hns_roce_srq_context *srq_context; | |
5770 | struct hns_roce_cmd_mailbox *mailbox; | |
5771 | int limit_wl; | |
5772 | int ret; | |
5773 | ||
5774 | mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); | |
5775 | if (IS_ERR(mailbox)) | |
5776 | return PTR_ERR(mailbox); | |
5777 | ||
5778 | srq_context = mailbox->buf; | |
5779 | ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0, | |
5780 | HNS_ROCE_CMD_QUERY_SRQC, | |
5781 | HNS_ROCE_CMD_TIMEOUT_MSECS); | |
5782 | if (ret) { | |
ae1c6148 LO |
5783 | ibdev_err(&hr_dev->ib_dev, |
5784 | "failed to process cmd when querying SRQ, ret = %d\n", | |
5785 | ret); | |
c7bcb134 LO |
5786 | goto out; |
5787 | } | |
5788 | ||
5789 | limit_wl = roce_get_field(srq_context->byte_8_limit_wl, | |
5790 | SRQC_BYTE_8_SRQ_LIMIT_WL_M, | |
5791 | SRQC_BYTE_8_SRQ_LIMIT_WL_S); | |
5792 | ||
5793 | attr->srq_limit = limit_wl; | |
d938d785 | 5794 | attr->max_wr = srq->wqe_cnt - 1; |
c7bcb134 LO |
5795 | attr->max_sge = srq->max_gs; |
5796 | ||
5797 | memcpy(srq_context, mailbox->buf, sizeof(*srq_context)); | |
5798 | ||
5799 | out: | |
5800 | hns_roce_free_cmd_mailbox(hr_dev, mailbox); | |
5801 | return ret; | |
5802 | } | |
5803 | ||
97545b10 LO |
5804 | static int find_empty_entry(struct hns_roce_idx_que *idx_que, |
5805 | unsigned long size) | |
c7bcb134 | 5806 | { |
97545b10 | 5807 | int wqe_idx; |
c7bcb134 | 5808 | |
97545b10 LO |
5809 | if (unlikely(bitmap_full(idx_que->bitmap, size))) |
5810 | return -ENOSPC; | |
5811 | ||
5812 | wqe_idx = find_first_zero_bit(idx_que->bitmap, size); | |
5813 | ||
5814 | bitmap_set(idx_que->bitmap, wqe_idx, 1); | |
c7bcb134 | 5815 | |
97545b10 | 5816 | return wqe_idx; |
c7bcb134 LO |
5817 | } |
5818 | ||
5819 | static void fill_idx_queue(struct hns_roce_idx_que *idx_que, | |
5820 | int cur_idx, int wqe_idx) | |
5821 | { | |
5822 | unsigned int *addr; | |
5823 | ||
6fd610c5 | 5824 | addr = (unsigned int *)hns_roce_buf_offset(idx_que->mtr.kmem, |
c7bcb134 LO |
5825 | cur_idx * idx_que->entry_sz); |
5826 | *addr = wqe_idx; | |
5827 | } | |
5828 | ||
5829 | static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, | |
5830 | const struct ib_recv_wr *wr, | |
5831 | const struct ib_recv_wr **bad_wr) | |
5832 | { | |
d3743fa9 | 5833 | struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device); |
c7bcb134 LO |
5834 | struct hns_roce_srq *srq = to_hr_srq(ibsrq); |
5835 | struct hns_roce_v2_wqe_data_seg *dseg; | |
5836 | struct hns_roce_v2_db srq_db; | |
5837 | unsigned long flags; | |
5838 | int ret = 0; | |
5839 | int wqe_idx; | |
5840 | void *wqe; | |
5841 | int nreq; | |
5842 | int ind; | |
5843 | int i; | |
5844 | ||
5845 | spin_lock_irqsave(&srq->lock, flags); | |
5846 | ||
d938d785 | 5847 | ind = srq->head & (srq->wqe_cnt - 1); |
c7bcb134 LO |
5848 | |
5849 | for (nreq = 0; wr; ++nreq, wr = wr->next) { | |
5850 | if (unlikely(wr->num_sge > srq->max_gs)) { | |
5851 | ret = -EINVAL; | |
5852 | *bad_wr = wr; | |
5853 | break; | |
5854 | } | |
5855 | ||
5856 | if (unlikely(srq->head == srq->tail)) { | |
5857 | ret = -ENOMEM; | |
5858 | *bad_wr = wr; | |
5859 | break; | |
5860 | } | |
5861 | ||
d938d785 | 5862 | wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt); |
97545b10 LO |
5863 | if (wqe_idx < 0) { |
5864 | ret = -ENOMEM; | |
5865 | *bad_wr = wr; | |
5866 | break; | |
5867 | } | |
5868 | ||
c7bcb134 LO |
5869 | fill_idx_queue(&srq->idx_que, ind, wqe_idx); |
5870 | wqe = get_srq_wqe(srq, wqe_idx); | |
5871 | dseg = (struct hns_roce_v2_wqe_data_seg *)wqe; | |
5872 | ||
5873 | for (i = 0; i < wr->num_sge; ++i) { | |
5874 | dseg[i].len = cpu_to_le32(wr->sg_list[i].length); | |
5875 | dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey); | |
5876 | dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr); | |
5877 | } | |
5878 | ||
5879 | if (i < srq->max_gs) { | |
4f18904c LO |
5880 | dseg[i].len = 0; |
5881 | dseg[i].lkey = cpu_to_le32(0x100); | |
5882 | dseg[i].addr = 0; | |
c7bcb134 LO |
5883 | } |
5884 | ||
5885 | srq->wrid[wqe_idx] = wr->wr_id; | |
d938d785 | 5886 | ind = (ind + 1) & (srq->wqe_cnt - 1); |
c7bcb134 LO |
5887 | } |
5888 | ||
5889 | if (likely(nreq)) { | |
5890 | srq->head += nreq; | |
5891 | ||
5892 | /* | |
5893 | * Make sure that descriptors are written before | |
5894 | * doorbell record. | |
5895 | */ | |
5896 | wmb(); | |
5897 | ||
bfe86035 LC |
5898 | srq_db.byte_4 = |
5899 | cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S | | |
5900 | (srq->srqn & V2_DB_BYTE_4_TAG_M)); | |
5901 | srq_db.parameter = cpu_to_le32(srq->head); | |
c7bcb134 | 5902 | |
d3743fa9 | 5903 | hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l); |
c7bcb134 LO |
5904 | |
5905 | } | |
5906 | ||
5907 | spin_unlock_irqrestore(&srq->lock, flags); | |
5908 | ||
5909 | return ret; | |
5910 | } | |
5911 | ||
e1c9a0dc LO |
5912 | static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = { |
5913 | .query_cqc_info = hns_roce_v2_query_cqc_info, | |
5914 | }; | |
5915 | ||
7f645a58 KH |
5916 | static const struct ib_device_ops hns_roce_v2_dev_ops = { |
5917 | .destroy_qp = hns_roce_v2_destroy_qp, | |
5918 | .modify_cq = hns_roce_v2_modify_cq, | |
5919 | .poll_cq = hns_roce_v2_poll_cq, | |
5920 | .post_recv = hns_roce_v2_post_recv, | |
5921 | .post_send = hns_roce_v2_post_send, | |
5922 | .query_qp = hns_roce_v2_query_qp, | |
5923 | .req_notify_cq = hns_roce_v2_req_notify_cq, | |
5924 | }; | |
5925 | ||
5926 | static const struct ib_device_ops hns_roce_v2_dev_srq_ops = { | |
5927 | .modify_srq = hns_roce_v2_modify_srq, | |
5928 | .post_srq_recv = hns_roce_v2_post_srq_recv, | |
5929 | .query_srq = hns_roce_v2_query_srq, | |
5930 | }; | |
5931 | ||
a04ff739 WHX |
5932 | static const struct hns_roce_hw hns_roce_hw_v2 = { |
5933 | .cmq_init = hns_roce_v2_cmq_init, | |
5934 | .cmq_exit = hns_roce_v2_cmq_exit, | |
cfc85f3e | 5935 | .hw_profile = hns_roce_v2_profile, |
6b63597d | 5936 | .hw_init = hns_roce_v2_init, |
5937 | .hw_exit = hns_roce_v2_exit, | |
a680f2f3 WHX |
5938 | .post_mbox = hns_roce_v2_post_mbox, |
5939 | .chk_mbox = hns_roce_v2_chk_mbox, | |
6a04aed6 | 5940 | .rst_prc_mbox = hns_roce_v2_rst_process_cmd, |
7afddafa WHX |
5941 | .set_gid = hns_roce_v2_set_gid, |
5942 | .set_mac = hns_roce_v2_set_mac, | |
3958cc56 | 5943 | .write_mtpt = hns_roce_v2_write_mtpt, |
a2c80b7b | 5944 | .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt, |
68a997c5 | 5945 | .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt, |
c7c28191 | 5946 | .mw_write_mtpt = hns_roce_v2_mw_write_mtpt, |
93aa2187 | 5947 | .write_cqc = hns_roce_v2_write_cqc, |
a81fba28 WHX |
5948 | .set_hem = hns_roce_v2_set_hem, |
5949 | .clear_hem = hns_roce_v2_clear_hem, | |
926a01dc WHX |
5950 | .modify_qp = hns_roce_v2_modify_qp, |
5951 | .query_qp = hns_roce_v2_query_qp, | |
5952 | .destroy_qp = hns_roce_v2_destroy_qp, | |
aa84fa18 | 5953 | .qp_flow_control_init = hns_roce_v2_qp_flow_control_init, |
b156269d | 5954 | .modify_cq = hns_roce_v2_modify_cq, |
2d407888 WHX |
5955 | .post_send = hns_roce_v2_post_send, |
5956 | .post_recv = hns_roce_v2_post_recv, | |
93aa2187 WHX |
5957 | .req_notify_cq = hns_roce_v2_req_notify_cq, |
5958 | .poll_cq = hns_roce_v2_poll_cq, | |
a5073d60 YL |
5959 | .init_eq = hns_roce_v2_init_eq_table, |
5960 | .cleanup_eq = hns_roce_v2_cleanup_eq_table, | |
c7bcb134 LO |
5961 | .write_srqc = hns_roce_v2_write_srqc, |
5962 | .modify_srq = hns_roce_v2_modify_srq, | |
5963 | .query_srq = hns_roce_v2_query_srq, | |
5964 | .post_srq_recv = hns_roce_v2_post_srq_recv, | |
7f645a58 KH |
5965 | .hns_roce_dev_ops = &hns_roce_v2_dev_ops, |
5966 | .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops, | |
a04ff739 | 5967 | }; |
dd74282d WHX |
5968 | |
5969 | static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = { | |
5970 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, | |
5971 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, | |
aaa31567 LO |
5972 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, |
5973 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, | |
dd74282d WHX |
5974 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, |
5975 | /* required last entry */ | |
5976 | {0, } | |
5977 | }; | |
5978 | ||
f97a62c3 | 5979 | MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); |
5980 | ||
301cc7eb | 5981 | static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, |
dd74282d WHX |
5982 | struct hnae3_handle *handle) |
5983 | { | |
d061effc | 5984 | struct hns_roce_v2_priv *priv = hr_dev->priv; |
a5073d60 | 5985 | int i; |
dd74282d | 5986 | |
301cc7eb LC |
5987 | hr_dev->pci_dev = handle->pdev; |
5988 | hr_dev->dev = &handle->pdev->dev; | |
dd74282d | 5989 | hr_dev->hw = &hns_roce_hw_v2; |
e1c9a0dc | 5990 | hr_dev->dfx = &hns_roce_dfx_hw_v2; |
2d407888 WHX |
5991 | hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG; |
5992 | hr_dev->odb_offset = hr_dev->sdb_offset; | |
dd74282d WHX |
5993 | |
5994 | /* Get info from NIC driver. */ | |
5995 | hr_dev->reg_base = handle->rinfo.roce_io_base; | |
5996 | hr_dev->caps.num_ports = 1; | |
5997 | hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; | |
5998 | hr_dev->iboe.phy_port[0] = 0; | |
5999 | ||
d4994d2f | 6000 | addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid, |
6001 | hr_dev->iboe.netdevs[0]->dev_addr); | |
6002 | ||
a5073d60 YL |
6003 | for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++) |
6004 | hr_dev->irq[i] = pci_irq_vector(handle->pdev, | |
6005 | i + handle->rinfo.base_vector); | |
6006 | ||
dd74282d | 6007 | /* cmd issue mode: 0 is poll, 1 is event */ |
a5073d60 | 6008 | hr_dev->cmd_mod = 1; |
dd74282d WHX |
6009 | hr_dev->loop_idc = 0; |
6010 | ||
d061effc WHX |
6011 | hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle); |
6012 | priv->handle = handle; | |
dd74282d WHX |
6013 | } |
6014 | ||
d061effc | 6015 | static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) |
dd74282d WHX |
6016 | { |
6017 | struct hns_roce_dev *hr_dev; | |
6018 | int ret; | |
6019 | ||
459cc69f | 6020 | hr_dev = ib_alloc_device(hns_roce_dev, ib_dev); |
dd74282d WHX |
6021 | if (!hr_dev) |
6022 | return -ENOMEM; | |
6023 | ||
a04ff739 WHX |
6024 | hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL); |
6025 | if (!hr_dev->priv) { | |
6026 | ret = -ENOMEM; | |
6027 | goto error_failed_kzalloc; | |
6028 | } | |
6029 | ||
301cc7eb | 6030 | hns_roce_hw_v2_get_cfg(hr_dev, handle); |
dd74282d WHX |
6031 | |
6032 | ret = hns_roce_init(hr_dev); | |
6033 | if (ret) { | |
6034 | dev_err(hr_dev->dev, "RoCE Engine init failed!\n"); | |
6035 | goto error_failed_get_cfg; | |
6036 | } | |
6037 | ||
d061effc WHX |
6038 | handle->priv = hr_dev; |
6039 | ||
dd74282d WHX |
6040 | return 0; |
6041 | ||
6042 | error_failed_get_cfg: | |
a04ff739 WHX |
6043 | kfree(hr_dev->priv); |
6044 | ||
6045 | error_failed_kzalloc: | |
dd74282d WHX |
6046 | ib_dealloc_device(&hr_dev->ib_dev); |
6047 | ||
6048 | return ret; | |
6049 | } | |
6050 | ||
d061effc | 6051 | static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, |
dd74282d WHX |
6052 | bool reset) |
6053 | { | |
6054 | struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv; | |
6055 | ||
cb7a94c9 WHX |
6056 | if (!hr_dev) |
6057 | return; | |
6058 | ||
d061effc | 6059 | handle->priv = NULL; |
626903e9 XW |
6060 | |
6061 | hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT; | |
6062 | hns_roce_handle_device_err(hr_dev); | |
6063 | ||
dd74282d | 6064 | hns_roce_exit(hr_dev); |
a04ff739 | 6065 | kfree(hr_dev->priv); |
dd74282d WHX |
6066 | ib_dealloc_device(&hr_dev->ib_dev); |
6067 | } | |
6068 | ||
d061effc WHX |
6069 | static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) |
6070 | { | |
6071 | const struct hnae3_ae_ops *ops = handle->ae_algo->ops; | |
07c2339a | 6072 | const struct pci_device_id *id; |
d061effc WHX |
6073 | struct device *dev = &handle->pdev->dev; |
6074 | int ret; | |
6075 | ||
6076 | handle->rinfo.instance_state = HNS_ROCE_STATE_INIT; | |
6077 | ||
6078 | if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) { | |
6079 | handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; | |
6080 | goto reset_chk_err; | |
6081 | } | |
6082 | ||
07c2339a LO |
6083 | id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev); |
6084 | if (!id) | |
6085 | return 0; | |
6086 | ||
d061effc WHX |
6087 | ret = __hns_roce_hw_v2_init_instance(handle); |
6088 | if (ret) { | |
6089 | handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; | |
6090 | dev_err(dev, "RoCE instance init failed! ret = %d\n", ret); | |
6091 | if (ops->ae_dev_resetting(handle) || | |
6092 | ops->get_hw_reset_stat(handle)) | |
6093 | goto reset_chk_err; | |
6094 | else | |
6095 | return ret; | |
6096 | } | |
6097 | ||
6098 | handle->rinfo.instance_state = HNS_ROCE_STATE_INITED; | |
6099 | ||
6100 | ||
6101 | return 0; | |
6102 | ||
6103 | reset_chk_err: | |
6104 | dev_err(dev, "Device is busy in resetting state.\n" | |
6105 | "please retry later.\n"); | |
6106 | ||
6107 | return -EBUSY; | |
6108 | } | |
6109 | ||
6110 | static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, | |
6111 | bool reset) | |
6112 | { | |
6113 | if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) | |
6114 | return; | |
6115 | ||
6116 | handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT; | |
6117 | ||
6118 | __hns_roce_hw_v2_uninit_instance(handle, reset); | |
6119 | ||
6120 | handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT; | |
6121 | } | |
cb7a94c9 WHX |
6122 | static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) |
6123 | { | |
d061effc | 6124 | struct hns_roce_dev *hr_dev; |
cb7a94c9 | 6125 | |
d061effc WHX |
6126 | if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) { |
6127 | set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); | |
6128 | return 0; | |
cb7a94c9 WHX |
6129 | } |
6130 | ||
d061effc WHX |
6131 | handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN; |
6132 | clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state); | |
6133 | ||
6134 | hr_dev = (struct hns_roce_dev *)handle->priv; | |
6135 | if (!hr_dev) | |
6136 | return 0; | |
6137 | ||
726be12f | 6138 | hr_dev->is_reset = true; |
cb7a94c9 | 6139 | hr_dev->active = false; |
d3743fa9 | 6140 | hr_dev->dis_db = true; |
cb7a94c9 | 6141 | |
626903e9 | 6142 | hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN; |
cb7a94c9 WHX |
6143 | |
6144 | return 0; | |
6145 | } | |
6146 | ||
6147 | static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) | |
6148 | { | |
d061effc | 6149 | struct device *dev = &handle->pdev->dev; |
cb7a94c9 WHX |
6150 | int ret; |
6151 | ||
d061effc WHX |
6152 | if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN, |
6153 | &handle->rinfo.state)) { | |
6154 | handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; | |
6155 | return 0; | |
6156 | } | |
6157 | ||
6158 | handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT; | |
6159 | ||
6160 | dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n"); | |
6161 | ret = __hns_roce_hw_v2_init_instance(handle); | |
cb7a94c9 WHX |
6162 | if (ret) { |
6163 | /* when reset notify type is HNAE3_INIT_CLIENT In reset notify | |
6164 | * callback function, RoCE Engine reinitialize. If RoCE reinit | |
6165 | * failed, we should inform NIC driver. | |
6166 | */ | |
6167 | handle->priv = NULL; | |
d061effc WHX |
6168 | dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret); |
6169 | } else { | |
6170 | handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED; | |
6171 | dev_info(dev, "Reset done, RoCE client reinit finished.\n"); | |
cb7a94c9 WHX |
6172 | } |
6173 | ||
6174 | return ret; | |
6175 | } | |
6176 | ||
6177 | static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) | |
6178 | { | |
d061effc WHX |
6179 | if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state)) |
6180 | return 0; | |
6181 | ||
6182 | handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT; | |
6183 | dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n"); | |
90c559b1 | 6184 | msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY); |
d061effc WHX |
6185 | __hns_roce_hw_v2_uninit_instance(handle, false); |
6186 | ||
cb7a94c9 WHX |
6187 | return 0; |
6188 | } | |
6189 | ||
6190 | static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, | |
6191 | enum hnae3_reset_notify_type type) | |
6192 | { | |
6193 | int ret = 0; | |
6194 | ||
6195 | switch (type) { | |
6196 | case HNAE3_DOWN_CLIENT: | |
6197 | ret = hns_roce_hw_v2_reset_notify_down(handle); | |
6198 | break; | |
6199 | case HNAE3_INIT_CLIENT: | |
6200 | ret = hns_roce_hw_v2_reset_notify_init(handle); | |
6201 | break; | |
6202 | case HNAE3_UNINIT_CLIENT: | |
6203 | ret = hns_roce_hw_v2_reset_notify_uninit(handle); | |
6204 | break; | |
6205 | default: | |
6206 | break; | |
6207 | } | |
6208 | ||
6209 | return ret; | |
6210 | } | |
6211 | ||
dd74282d WHX |
6212 | static const struct hnae3_client_ops hns_roce_hw_v2_ops = { |
6213 | .init_instance = hns_roce_hw_v2_init_instance, | |
6214 | .uninit_instance = hns_roce_hw_v2_uninit_instance, | |
cb7a94c9 | 6215 | .reset_notify = hns_roce_hw_v2_reset_notify, |
dd74282d WHX |
6216 | }; |
6217 | ||
6218 | static struct hnae3_client hns_roce_hw_v2_client = { | |
6219 | .name = "hns_roce_hw_v2", | |
6220 | .type = HNAE3_CLIENT_ROCE, | |
6221 | .ops = &hns_roce_hw_v2_ops, | |
6222 | }; | |
6223 | ||
6224 | static int __init hns_roce_hw_v2_init(void) | |
6225 | { | |
6226 | return hnae3_register_client(&hns_roce_hw_v2_client); | |
6227 | } | |
6228 | ||
6229 | static void __exit hns_roce_hw_v2_exit(void) | |
6230 | { | |
6231 | hnae3_unregister_client(&hns_roce_hw_v2_client); | |
6232 | } | |
6233 | ||
6234 | module_init(hns_roce_hw_v2_init); | |
6235 | module_exit(hns_roce_hw_v2_exit); | |
6236 | ||
6237 | MODULE_LICENSE("Dual BSD/GPL"); | |
6238 | MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>"); | |
6239 | MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>"); | |
6240 | MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>"); | |
6241 | MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver"); |