projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
RDMA/nes: Use for_each_sg_dma_page iterator for umem SGL
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
dd74282d
WHX		 40#include <rdma/ib_umem.h>
41
42#include "hnae3.h"
43#include "hns_roce_common.h"
44#include "hns_roce_device.h"
45#include "hns_roce_cmd.h"
46#include "hns_roce_hem.h"
a04ff739 47#include "hns_roce_hw_v2.h"
dd74282d 48
2d407888
WHX		 49static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
50 struct ib_sge *sg)
51{
52 dseg->lkey = cpu_to_le32(sg->lkey);
53 dseg->addr = cpu_to_le64(sg->addr);
54 dseg->len = cpu_to_le32(sg->length);
55}
56
68a997c5
YL		 57static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
58 struct hns_roce_wqe_frmr_seg *fseg,
59 const struct ib_reg_wr *wr)
60{
61 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
62
63 /* use ib_access_flags */
64 roce_set_bit(rc_sq_wqe->byte_4,
65 V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
66 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
67 roce_set_bit(rc_sq_wqe->byte_4,
68 V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
69 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
70 roce_set_bit(rc_sq_wqe->byte_4,
71 V2_RC_FRMR_WQE_BYTE_4_RR_S,
72 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
73 roce_set_bit(rc_sq_wqe->byte_4,
74 V2_RC_FRMR_WQE_BYTE_4_RW_S,
75 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
76 roce_set_bit(rc_sq_wqe->byte_4,
77 V2_RC_FRMR_WQE_BYTE_4_LW_S,
78 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
79
80 /* Data structure reuse may lead to confusion */
81 rc_sq_wqe->msg_len = cpu_to_le32(mr->pbl_ba & 0xffffffff);
82 rc_sq_wqe->inv_key = cpu_to_le32(mr->pbl_ba >> 32);
83
84 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
85 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
86 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
87 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
88
89 fseg->pbl_size = cpu_to_le32(mr->pbl_size);
90 roce_set_field(fseg->mode_buf_pg_sz,
91 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
92 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
93 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
94 roce_set_bit(fseg->mode_buf_pg_sz,
95 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
96}
97
384f8818
LO		 98static void set_atomic_seg(struct hns_roce_wqe_atomic_seg *aseg,
99 const struct ib_atomic_wr *wr)
100{
101 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
102 aseg->fetchadd_swap_data = cpu_to_le64(wr->swap);
103 aseg->cmp_data = cpu_to_le64(wr->compare_add);
104 } else {
105 aseg->fetchadd_swap_data = cpu_to_le64(wr->compare_add);
106 aseg->cmp_data = 0;
107 }
108}
109
f696bf6d 110static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
0b25c9cc
WHX		 111 unsigned int *sge_ind)
112{
113 struct hns_roce_v2_wqe_data_seg *dseg;
114 struct ib_sge *sg;
115 int num_in_wqe = 0;
116 int extend_sge_num;
117 int fi_sge_num;
118 int se_sge_num;
119 int shift;
120 int i;
121
122 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC)
123 num_in_wqe = HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE;
124 extend_sge_num = wr->num_sge - num_in_wqe;
125 sg = wr->sg_list + num_in_wqe;
126 shift = qp->hr_buf.page_shift;
127
128 /*
129 * Check whether wr->num_sge sges are in the same page. If not, we
130 * should calculate how many sges in the first page and the second
131 * page.
132 */
133 dseg = get_send_extend_sge(qp, (*sge_ind) & (qp->sge.sge_cnt - 1));
134 fi_sge_num = (round_up((uintptr_t)dseg, 1 << shift) -
135 (uintptr_t)dseg) /
136 sizeof(struct hns_roce_v2_wqe_data_seg);
137 if (extend_sge_num > fi_sge_num) {
138 se_sge_num = extend_sge_num - fi_sge_num;
139 for (i = 0; i < fi_sge_num; i++) {
140 set_data_seg_v2(dseg++, sg + i);
141 (*sge_ind)++;
142 }
143 dseg = get_send_extend_sge(qp,
144 (*sge_ind) & (qp->sge.sge_cnt - 1));
145 for (i = 0; i < se_sge_num; i++) {
146 set_data_seg_v2(dseg++, sg + fi_sge_num + i);
147 (*sge_ind)++;
148 }
149 } else {
150 for (i = 0; i < extend_sge_num; i++) {
151 set_data_seg_v2(dseg++, sg + i);
152 (*sge_ind)++;
153 }
154 }
155}
156
f696bf6d 157static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 158 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
159 void *wqe, unsigned int *sge_ind,
d34ac5cd 160 const struct ib_send_wr **bad_wr)
7bdee415 161{
162 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
163 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
164 struct hns_roce_qp *qp = to_hr_qp(ibqp);
165 int i;
166
167 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 168 if (le32_to_cpu(rc_sq_wqe->msg_len) >
169 hr_dev->caps.max_sq_inline) {
7bdee415 170 *bad_wr = wr;
171 dev_err(hr_dev->dev, "inline len(1-%d)=%d, illegal",
172 rc_sq_wqe->msg_len, hr_dev->caps.max_sq_inline);
173 return -EINVAL;
174 }
175
328d405b 176 if (wr->opcode == IB_WR_RDMA_READ) {
c80e0661 177 *bad_wr = wr;
328d405b 178 dev_err(hr_dev->dev, "Not support inline data!\n");
179 return -EINVAL;
180 }
181
7bdee415 182 for (i = 0; i < wr->num_sge; i++) {
183 memcpy(wqe, ((void *)wr->sg_list[i].addr),
184 wr->sg_list[i].length);
185 wqe += wr->sg_list[i].length;
186 }
187
188 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
189 1);
190 } else {
0b25c9cc 191 if (wr->num_sge <= HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE) {
7bdee415 192 for (i = 0; i < wr->num_sge; i++) {
193 if (likely(wr->sg_list[i].length)) {
194 set_data_seg_v2(dseg, wr->sg_list + i);
195 dseg++;
196 }
197 }
198 } else {
199 roce_set_field(rc_sq_wqe->byte_20,
200 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
201 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
202 (*sge_ind) & (qp->sge.sge_cnt - 1));
203
0b25c9cc 204 for (i = 0; i < HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE; i++) {
7bdee415 205 if (likely(wr->sg_list[i].length)) {
206 set_data_seg_v2(dseg, wr->sg_list + i);
207 dseg++;
208 }
209 }
210
0b25c9cc 211 set_extend_sge(qp, wr, sge_ind);
7bdee415 212 }
213
214 roce_set_field(rc_sq_wqe->byte_16,
215 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
216 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, wr->num_sge);
217 }
218
219 return 0;
220}
221
0425e3e6
YL		 222static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
223 const struct ib_qp_attr *attr,
224 int attr_mask, enum ib_qp_state cur_state,
225 enum ib_qp_state new_state);
226
d34ac5cd
BVA		 227static int hns_roce_v2_post_send(struct ib_qp *ibqp,
228 const struct ib_send_wr *wr,
229 const struct ib_send_wr **bad_wr)
2d407888
WHX		 230{
231 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
7bdee415 232 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
233 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe;
2d407888
WHX		 234 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
235 struct hns_roce_qp *qp = to_hr_qp(ibqp);
68a997c5 236 struct hns_roce_wqe_frmr_seg *fseg;
2d407888
WHX		 237 struct device *dev = hr_dev->dev;
238 struct hns_roce_v2_db sq_db;
0425e3e6 239 struct ib_qp_attr attr;
2d407888 240 unsigned int sge_ind = 0;
e8d18533 241 unsigned int owner_bit;
2d407888
WHX		 242 unsigned long flags;
243 unsigned int ind;
244 void *wqe = NULL;
7bdee415 245 bool loopback;
0425e3e6 246 int attr_mask;
55ba49cb 247 u32 tmp_len;
2d407888 248 int ret = 0;
b9c1ea40 249 u32 hr_op;
7bdee415 250 u8 *smac;
2d407888
WHX		 251 int nreq;
252 int i;
253
7bdee415 254 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
255 ibqp->qp_type != IB_QPT_GSI &&
256 ibqp->qp_type != IB_QPT_UD)) {
2d407888 257 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
137ae320 258 *bad_wr = wr;
2d407888
WHX		 259 return -EOPNOTSUPP;
260 }
261
10bd2ade
YL		 262 if (unlikely(qp->state == IB_QPS_RESET || qp->state == IB_QPS_INIT ||
263 qp->state == IB_QPS_RTR)) {
2d407888
WHX		 264 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
265 *bad_wr = wr;
266 return -EINVAL;
267 }
268
269 spin_lock_irqsave(&qp->sq.lock, flags);
270 ind = qp->sq_next_wqe;
271 sge_ind = qp->next_sge;
272
273 for (nreq = 0; wr; ++nreq, wr = wr->next) {
274 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
275 ret = -ENOMEM;
276 *bad_wr = wr;
277 goto out;
278 }
279
280 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
281 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
282 wr->num_sge, qp->sq.max_gs);
283 ret = -EINVAL;
284 *bad_wr = wr;
285 goto out;
286 }
287
288 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
289 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
290 wr->wr_id;
291
634f6390 292 owner_bit =
293 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
55ba49cb 294 tmp_len = 0;
2d407888 295
7bdee415 296 /* Corresponding to the QP type, wqe process separately */
297 if (ibqp->qp_type == IB_QPT_GSI) {
298 ud_sq_wqe = wqe;
299 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
300
301 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
302 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
303 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
304 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
305 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
306 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
307 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
308 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
309 roce_set_field(ud_sq_wqe->byte_48,
310 V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
311 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S,
312 ah->av.mac[4]);
313 roce_set_field(ud_sq_wqe->byte_48,
314 V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
315 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S,
316 ah->av.mac[5]);
317
318 /* MAC loopback */
319 smac = (u8 *)hr_dev->dev_addr[qp->port];
320 loopback = ether_addr_equal_unaligned(ah->av.mac,
321 smac) ? 1 : 0;
322
323 roce_set_bit(ud_sq_wqe->byte_40,
324 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
325
326 roce_set_field(ud_sq_wqe->byte_4,
327 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
328 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
329 HNS_ROCE_V2_WQE_OP_SEND);
2d407888 330
7bdee415 331 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 332 tmp_len += wr->sg_list[i].length;
492b2bd0 333
8b9b8d14 334 ud_sq_wqe->msg_len =
335 cpu_to_le32(le32_to_cpu(ud_sq_wqe->msg_len) + tmp_len);
336
337 switch (wr->opcode) {
338 case IB_WR_SEND_WITH_IMM:
339 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 340 ud_sq_wqe->immtdata =
341 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 342 break;
343 default:
344 ud_sq_wqe->immtdata = 0;
345 break;
346 }
651487c2 347
7bdee415 348 /* Set sig attr */
349 roce_set_bit(ud_sq_wqe->byte_4,
350 V2_UD_SEND_WQE_BYTE_4_CQE_S,
351 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
a49d761f 352
7bdee415 353 /* Set se attr */
354 roce_set_bit(ud_sq_wqe->byte_4,
355 V2_UD_SEND_WQE_BYTE_4_SE_S,
356 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
e8d18533 357
7bdee415 358 roce_set_bit(ud_sq_wqe->byte_4,
359 V2_UD_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
360
361 roce_set_field(ud_sq_wqe->byte_16,
362 V2_UD_SEND_WQE_BYTE_16_PD_M,
363 V2_UD_SEND_WQE_BYTE_16_PD_S,
364 to_hr_pd(ibqp->pd)->pdn);
365
366 roce_set_field(ud_sq_wqe->byte_16,
367 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
368 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S,
369 wr->num_sge);
370
371 roce_set_field(ud_sq_wqe->byte_20,
372 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
373 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
374 sge_ind & (qp->sge.sge_cnt - 1));
375
376 roce_set_field(ud_sq_wqe->byte_24,
377 V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
378 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
379 ud_sq_wqe->qkey =
8b9b8d14 380 cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
381 qp->qkey : ud_wr(wr)->remote_qkey);
7bdee415 382 roce_set_field(ud_sq_wqe->byte_32,
383 V2_UD_SEND_WQE_BYTE_32_DQPN_M,
384 V2_UD_SEND_WQE_BYTE_32_DQPN_S,
385 ud_wr(wr)->remote_qpn);
386
387 roce_set_field(ud_sq_wqe->byte_36,
388 V2_UD_SEND_WQE_BYTE_36_VLAN_M,
389 V2_UD_SEND_WQE_BYTE_36_VLAN_S,
8b9b8d14 390 le16_to_cpu(ah->av.vlan));
7bdee415 391 roce_set_field(ud_sq_wqe->byte_36,
392 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
393 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S,
394 ah->av.hop_limit);
395 roce_set_field(ud_sq_wqe->byte_36,
396 V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
397 V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
cdfa4ad5
LO		 398 ah->av.sl_tclass_flowlabel >>
399 HNS_ROCE_TCLASS_SHIFT);
7bdee415 400 roce_set_field(ud_sq_wqe->byte_40,
401 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
cdfa4ad5
LO		 402 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S,
403 ah->av.sl_tclass_flowlabel &
404 HNS_ROCE_FLOW_LABEL_MASK);
7bdee415 405 roce_set_field(ud_sq_wqe->byte_40,
406 V2_UD_SEND_WQE_BYTE_40_SL_M,
407 V2_UD_SEND_WQE_BYTE_40_SL_S,
8b9b8d14 408 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
409 HNS_ROCE_SL_SHIFT);
7bdee415 410 roce_set_field(ud_sq_wqe->byte_40,
411 V2_UD_SEND_WQE_BYTE_40_PORTN_M,
412 V2_UD_SEND_WQE_BYTE_40_PORTN_S,
413 qp->port);
414
8320deb8
LO		 415 roce_set_bit(ud_sq_wqe->byte_40,
416 V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
417 ah->av.vlan_en ? 1 : 0);
7bdee415 418 roce_set_field(ud_sq_wqe->byte_48,
419 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
420 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S,
421 hns_get_gid_index(hr_dev, qp->phy_port,
422 ah->av.gid_index));
423
424 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0],
425 GID_LEN_V2);
426
0b25c9cc 427 set_extend_sge(qp, wr, &sge_ind);
7bdee415 428 ind++;
429 } else if (ibqp->qp_type == IB_QPT_RC) {
430 rc_sq_wqe = wqe;
431 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
432 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 433 tmp_len += wr->sg_list[i].length;
434
435 rc_sq_wqe->msg_len =
436 cpu_to_le32(le32_to_cpu(rc_sq_wqe->msg_len) + tmp_len);
7bdee415 437
8b9b8d14 438 switch (wr->opcode) {
439 case IB_WR_SEND_WITH_IMM:
440 case IB_WR_RDMA_WRITE_WITH_IMM:
0c4a0e29
LO		 441 rc_sq_wqe->immtdata =
442 cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
8b9b8d14 443 break;
444 case IB_WR_SEND_WITH_INV:
445 rc_sq_wqe->inv_key =
446 cpu_to_le32(wr->ex.invalidate_rkey);
447 break;
448 default:
449 rc_sq_wqe->immtdata = 0;
450 break;
451 }
7bdee415 452
453 roce_set_bit(rc_sq_wqe->byte_4,
454 V2_RC_SEND_WQE_BYTE_4_FENCE_S,
455 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
456
457 roce_set_bit(rc_sq_wqe->byte_4,
458 V2_RC_SEND_WQE_BYTE_4_SE_S,
459 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
460
461 roce_set_bit(rc_sq_wqe->byte_4,
462 V2_RC_SEND_WQE_BYTE_4_CQE_S,
463 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
464
465 roce_set_bit(rc_sq_wqe->byte_4,
466 V2_RC_SEND_WQE_BYTE_4_OWNER_S, owner_bit);
467
384f8818 468 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
7bdee415 469 switch (wr->opcode) {
470 case IB_WR_RDMA_READ:
b9c1ea40 471 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
7bdee415 472 rc_sq_wqe->rkey =
473 cpu_to_le32(rdma_wr(wr)->rkey);
474 rc_sq_wqe->va =
475 cpu_to_le64(rdma_wr(wr)->remote_addr);
476 break;
477 case IB_WR_RDMA_WRITE:
b9c1ea40 478 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
7bdee415 479 rc_sq_wqe->rkey =
480 cpu_to_le32(rdma_wr(wr)->rkey);
481 rc_sq_wqe->va =
482 cpu_to_le64(rdma_wr(wr)->remote_addr);
483 break;
484 case IB_WR_RDMA_WRITE_WITH_IMM:
b9c1ea40 485 hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
7bdee415 486 rc_sq_wqe->rkey =
487 cpu_to_le32(rdma_wr(wr)->rkey);
488 rc_sq_wqe->va =
489 cpu_to_le64(rdma_wr(wr)->remote_addr);
490 break;
491 case IB_WR_SEND:
b9c1ea40 492 hr_op = HNS_ROCE_V2_WQE_OP_SEND;
7bdee415 493 break;
494 case IB_WR_SEND_WITH_INV:
b9c1ea40 495 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
7bdee415 496 break;
497 case IB_WR_SEND_WITH_IMM:
b9c1ea40 498 hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
7bdee415 499 break;
500 case IB_WR_LOCAL_INV:
b9c1ea40 501 hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
e93df010
LO		 502 roce_set_bit(rc_sq_wqe->byte_4,
503 V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
504 rc_sq_wqe->inv_key =
505 cpu_to_le32(wr->ex.invalidate_rkey);
7bdee415 506 break;
68a997c5
YL		 507 case IB_WR_REG_MR:
508 hr_op = HNS_ROCE_V2_WQE_OP_FAST_REG_PMR;
509 fseg = wqe;
510 set_frmr_seg(rc_sq_wqe, fseg, reg_wr(wr));
511 break;
7bdee415 512 case IB_WR_ATOMIC_CMP_AND_SWP:
b9c1ea40 513 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
384f8818
LO		 514 rc_sq_wqe->rkey =
515 cpu_to_le32(atomic_wr(wr)->rkey);
516 rc_sq_wqe->va =
d9581bf3 517 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 518 break;
519 case IB_WR_ATOMIC_FETCH_AND_ADD:
b9c1ea40 520 hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
384f8818
LO		 521 rc_sq_wqe->rkey =
522 cpu_to_le32(atomic_wr(wr)->rkey);
523 rc_sq_wqe->va =
d9581bf3 524 cpu_to_le64(atomic_wr(wr)->remote_addr);
7bdee415 525 break;
526 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
b9c1ea40
LO		 527 hr_op =
528 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
7bdee415 529 break;
530 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
b9c1ea40
LO		 531 hr_op =
532 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
7bdee415 533 break;
534 default:
b9c1ea40 535 hr_op = HNS_ROCE_V2_WQE_OP_MASK;
7bdee415 536 break;
2d407888
WHX		 537 }
538
b9c1ea40
LO		 539 roce_set_field(rc_sq_wqe->byte_4,
540 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
541 V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
2d407888 542
d9581bf3
LO		 543 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
544 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
545 struct hns_roce_v2_wqe_data_seg *dseg;
546
547 dseg = wqe;
548 set_data_seg_v2(dseg, wr->sg_list);
549 wqe += sizeof(struct hns_roce_v2_wqe_data_seg);
550 set_atomic_seg(wqe, atomic_wr(wr));
551 roce_set_field(rc_sq_wqe->byte_16,
552 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
553 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
554 wr->num_sge);
68a997c5 555 } else if (wr->opcode != IB_WR_REG_MR) {
d9581bf3
LO		 556 ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe,
557 wqe, &sge_ind, bad_wr);
558 if (ret)
559 goto out;
560 }
561
7bdee415 562 ind++;
2d407888 563 } else {
7bdee415 564 dev_err(dev, "Illegal qp_type(0x%x)\n", ibqp->qp_type);
565 spin_unlock_irqrestore(&qp->sq.lock, flags);
137ae320 566 *bad_wr = wr;
7bdee415 567 return -EOPNOTSUPP;
2d407888 568 }
2d407888
WHX		 569 }
570
571out:
572 if (likely(nreq)) {
573 qp->sq.head += nreq;
574 /* Memory barrier */
575 wmb();
576
577 sq_db.byte_4 = 0;
578 sq_db.parameter = 0;
579
580 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
581 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
582 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
583 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
cc3391cb 584 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
585 V2_DB_PARAMETER_IDX_S,
2d407888
WHX		 586 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
587 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
588 V2_DB_PARAMETER_SL_S, qp->sl);
589
d3743fa9 590 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l);
2d407888
WHX		 591
592 qp->sq_next_wqe = ind;
593 qp->next_sge = sge_ind;
0425e3e6
YL		 594
595 if (qp->state == IB_QPS_ERR) {
596 attr_mask = IB_QP_STATE;
597 attr.qp_state = IB_QPS_ERR;
598
599 ret = hns_roce_v2_modify_qp(&qp->ibqp, &attr, attr_mask,
600 qp->state, IB_QPS_ERR);
601 if (ret) {
602 spin_unlock_irqrestore(&qp->sq.lock, flags);
603 *bad_wr = wr;
604 return ret;
605 }
606 }
2d407888
WHX		 607 }
608
609 spin_unlock_irqrestore(&qp->sq.lock, flags);
610
611 return ret;
612}
613
d34ac5cd
BVA		 614static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
615 const struct ib_recv_wr *wr,
616 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 617{
618 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
619 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
620 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 621 struct hns_roce_rinl_sge *sge_list;
2d407888 622 struct device *dev = hr_dev->dev;
0425e3e6 623 struct ib_qp_attr attr;
2d407888
WHX		 624 unsigned long flags;
625 void *wqe = NULL;
0425e3e6 626 int attr_mask;
2d407888
WHX		 627 int ret = 0;
628 int nreq;
629 int ind;
630 int i;
631
632 spin_lock_irqsave(&hr_qp->rq.lock, flags);
633 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
634
ced07769 635 if (hr_qp->state == IB_QPS_RESET) {
2d407888
WHX		 636 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
637 *bad_wr = wr;
638 return -EINVAL;
639 }
640
641 for (nreq = 0; wr; ++nreq, wr = wr->next) {
642 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
643 hr_qp->ibqp.recv_cq)) {
644 ret = -ENOMEM;
645 *bad_wr = wr;
646 goto out;
647 }
648
649 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
650 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
651 wr->num_sge, hr_qp->rq.max_gs);
652 ret = -EINVAL;
653 *bad_wr = wr;
654 goto out;
655 }
656
657 wqe = get_recv_wqe(hr_qp, ind);
658 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
659 for (i = 0; i < wr->num_sge; i++) {
660 if (!wr->sg_list[i].length)
661 continue;
662 set_data_seg_v2(dseg, wr->sg_list + i);
663 dseg++;
664 }
665
666 if (i < hr_qp->rq.max_gs) {
778cc5a8 667 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
668 dseg->addr = 0;
2d407888
WHX		 669 }
670
0009c2db 671 /* rq support inline data */
ecaaf1e2 672 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
673 sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
674 hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
675 (u32)wr->num_sge;
676 for (i = 0; i < wr->num_sge; i++) {
677 sge_list[i].addr =
678 (void *)(u64)wr->sg_list[i].addr;
679 sge_list[i].len = wr->sg_list[i].length;
680 }
0009c2db 681 }
682
2d407888
WHX		 683 hr_qp->rq.wrid[ind] = wr->wr_id;
684
685 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
686 }
687
688out:
689 if (likely(nreq)) {
690 hr_qp->rq.head += nreq;
691 /* Memory barrier */
692 wmb();
693
472bc0fb 694 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
0425e3e6
YL		 695
696 if (hr_qp->state == IB_QPS_ERR) {
697 attr_mask = IB_QP_STATE;
698 attr.qp_state = IB_QPS_ERR;
699
700 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr,
701 attr_mask, hr_qp->state,
702 IB_QPS_ERR);
703 if (ret) {
704 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
705 *bad_wr = wr;
706 return ret;
707 }
708 }
2d407888
WHX		 709 }
710 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
711
712 return ret;
713}
714
6a04aed6
WHX		 715static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
716 unsigned long instance_stage,
717 unsigned long reset_stage)
718{
719 /* When hardware reset has been completed once or more, we should stop
d3743fa9 720 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
6a04aed6
WHX		 721 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
722 * stage of soft reset process, we should exit with error, and then
723 * HNAE3_INIT_CLIENT related process can rollback the operation like
724 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
725 * process will exit with error to notify NIC driver to reschedule soft
726 * reset process once again.
727 */
728 hr_dev->is_reset = true;
d3743fa9 729 hr_dev->dis_db = true;
6a04aed6
WHX		 730
731 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
732 instance_stage == HNS_ROCE_STATE_INIT)
733 return CMD_RST_PRC_EBUSY;
734
735 return CMD_RST_PRC_SUCCESS;
736}
737
738static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
739 unsigned long instance_stage,
740 unsigned long reset_stage)
741{
742 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
743 struct hnae3_handle *handle = priv->handle;
744 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
745
d3743fa9
WHX		 746 /* When hardware reset is detected, we should stop sending mailbox&cmq&
747 * doorbell to hardware. If now in .init_instance() function, we should
6a04aed6
WHX		 748 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
749 * process, we should exit with error, and then HNAE3_INIT_CLIENT
750 * related process can rollback the operation like notifing hardware to
751 * free resources, HNAE3_INIT_CLIENT related process will exit with
752 * error to notify NIC driver to reschedule soft reset process once
753 * again.
754 */
d3743fa9 755 hr_dev->dis_db = true;
6a04aed6
WHX		 756 if (!ops->get_hw_reset_stat(handle))
757 hr_dev->is_reset = true;
758
759 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
760 instance_stage == HNS_ROCE_STATE_INIT)
761 return CMD_RST_PRC_EBUSY;
762
763 return CMD_RST_PRC_SUCCESS;
764}
765
766static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
767{
768 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
769 struct hnae3_handle *handle = priv->handle;
770 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
771
772 /* When software reset is detected at .init_instance() function, we
d3743fa9
WHX		 773 * should stop sending mailbox&cmq&doorbell to hardware, and exit
774 * with error.
6a04aed6 775 */
d3743fa9 776 hr_dev->dis_db = true;
6a04aed6
WHX		 777 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
778 hr_dev->is_reset = true;
779
780 return CMD_RST_PRC_EBUSY;
781}
782
783static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
784{
785 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
786 struct hnae3_handle *handle = priv->handle;
787 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
788 unsigned long instance_stage; /* the current instance stage */
789 unsigned long reset_stage; /* the current reset stage */
790 unsigned long reset_cnt;
791 bool sw_resetting;
792 bool hw_resetting;
793
794 if (hr_dev->is_reset)
795 return CMD_RST_PRC_SUCCESS;
796
797 /* Get information about reset from NIC driver or RoCE driver itself,
798 * the meaning of the following variables from NIC driver are described
799 * as below:
800 * reset_cnt -- The count value of completed hardware reset.
801 * hw_resetting -- Whether hardware device is resetting now.
802 * sw_resetting -- Whether NIC's software reset process is running now.
803 */
804 instance_stage = handle->rinfo.instance_state;
805 reset_stage = handle->rinfo.reset_state;
806 reset_cnt = ops->ae_dev_reset_cnt(handle);
807 hw_resetting = ops->get_hw_reset_stat(handle);
808 sw_resetting = ops->ae_dev_resetting(handle);
809
810 if (reset_cnt != hr_dev->reset_cnt)
811 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
812 reset_stage);
813 else if (hw_resetting)
814 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
815 reset_stage);
816 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
817 return hns_roce_v2_cmd_sw_resetting(hr_dev);
818
819 return 0;
820}
821
a04ff739
WHX		 822static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
823{
824 int ntu = ring->next_to_use;
825 int ntc = ring->next_to_clean;
826 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
827
828 return ring->desc_num - used - 1;
829}
830
831static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
832 struct hns_roce_v2_cmq_ring *ring)
833{
834 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
835
836 ring->desc = kzalloc(size, GFP_KERNEL);
837 if (!ring->desc)
838 return -ENOMEM;
839
840 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
841 DMA_BIDIRECTIONAL);
842 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
843 ring->desc_dma_addr = 0;
844 kfree(ring->desc);
845 ring->desc = NULL;
846 return -ENOMEM;
847 }
848
849 return 0;
850}
851
852static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
853 struct hns_roce_v2_cmq_ring *ring)
854{
855 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
856 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
857 DMA_BIDIRECTIONAL);
90e7a4d5 858
859 ring->desc_dma_addr = 0;
a04ff739
WHX		 860 kfree(ring->desc);
861}
862
863static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
864{
865 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
866 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
867 &priv->cmq.csq : &priv->cmq.crq;
868
869 ring->flag = ring_type;
870 ring->next_to_clean = 0;
871 ring->next_to_use = 0;
872
873 return hns_roce_alloc_cmq_desc(hr_dev, ring);
874}
875
876static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
877{
878 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
879 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
880 &priv->cmq.csq : &priv->cmq.crq;
881 dma_addr_t dma = ring->desc_dma_addr;
882
883 if (ring_type == TYPE_CSQ) {
884 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
885 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
886 upper_32_bits(dma));
887 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
888 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
889 HNS_ROCE_CMQ_ENABLE);
890 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
891 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
892 } else {
893 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
894 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
895 upper_32_bits(dma));
896 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
897 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
898 HNS_ROCE_CMQ_ENABLE);
899 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
900 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
901 }
902}
903
904static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
905{
906 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
907 int ret;
908
909 /* Setup the queue entries for command queue */
426c4146
LO		 910 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
911 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 912
913 /* Setup the lock for command queue */
914 spin_lock_init(&priv->cmq.csq.lock);
915 spin_lock_init(&priv->cmq.crq.lock);
916
917 /* Setup Tx write back timeout */
918 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
919
920 /* Init CSQ */
921 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
922 if (ret) {
923 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
924 return ret;
925 }
926
927 /* Init CRQ */
928 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
929 if (ret) {
930 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
931 goto err_crq;
932 }
933
934 /* Init CSQ REG */
935 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
936
937 /* Init CRQ REG */
938 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
939
940 return 0;
941
942err_crq:
943 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
944
945 return ret;
946}
947
948static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
949{
950 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
951
952 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
953 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
954}
955
281d0ccf
CIK		 956static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
957 enum hns_roce_opcode_type opcode,
958 bool is_read)
a04ff739
WHX		 959{
960 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
961 desc->opcode = cpu_to_le16(opcode);
962 desc->flag =
963 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
964 if (is_read)
965 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
966 else
967 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
968}
969
970static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
971{
972 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
973 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
974
975 return head == priv->cmq.csq.next_to_use;
976}
977
978static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
979{
980 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
981 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
982 struct hns_roce_cmq_desc *desc;
983 u16 ntc = csq->next_to_clean;
984 u32 head;
985 int clean = 0;
986
987 desc = &csq->desc[ntc];
988 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
989 while (head != ntc) {
990 memset(desc, 0, sizeof(*desc));
991 ntc++;
992 if (ntc == csq->desc_num)
993 ntc = 0;
994 desc = &csq->desc[ntc];
995 clean++;
996 }
997 csq->next_to_clean = ntc;
998
999 return clean;
1000}
1001
6a04aed6
WHX		 1002static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1003 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 1004{
1005 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
1006 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1007 struct hns_roce_cmq_desc *desc_to_use;
1008 bool complete = false;
1009 u32 timeout = 0;
1010 int handle = 0;
1011 u16 desc_ret;
1012 int ret = 0;
1013 int ntc;
1014
1015 spin_lock_bh(&csq->lock);
1016
1017 if (num > hns_roce_cmq_space(csq)) {
1018 spin_unlock_bh(&csq->lock);
1019 return -EBUSY;
1020 }
1021
1022 /*
1023 * Record the location of desc in the cmq for this time
1024 * which will be use for hardware to write back
1025 */
1026 ntc = csq->next_to_use;
1027
1028 while (handle < num) {
1029 desc_to_use = &csq->desc[csq->next_to_use];
1030 *desc_to_use = desc[handle];
1031 dev_dbg(hr_dev->dev, "set cmq desc:\n");
1032 csq->next_to_use++;
1033 if (csq->next_to_use == csq->desc_num)
1034 csq->next_to_use = 0;
1035 handle++;
1036 }
1037
1038 /* Write to hardware */
1039 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
1040
1041 /*
1042 * If the command is sync, wait for the firmware to write back,
1043 * if multi descriptors to be sent, use the first one to check
1044 */
1045 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
1046 do {
1047 if (hns_roce_cmq_csq_done(hr_dev))
1048 break;
988e175b 1049 udelay(1);
a04ff739
WHX		 1050 timeout++;
1051 } while (timeout < priv->cmq.tx_timeout);
1052 }
1053
1054 if (hns_roce_cmq_csq_done(hr_dev)) {
1055 complete = true;
1056 handle = 0;
1057 while (handle < num) {
1058 /* get the result of hardware write back */
1059 desc_to_use = &csq->desc[ntc];
1060 desc[handle] = *desc_to_use;
1061 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
1062 desc_ret = desc[handle].retval;
1063 if (desc_ret == CMD_EXEC_SUCCESS)
1064 ret = 0;
1065 else
1066 ret = -EIO;
1067 priv->cmq.last_status = desc_ret;
1068 ntc++;
1069 handle++;
1070 if (ntc == csq->desc_num)
1071 ntc = 0;
1072 }
1073 }
1074
1075 if (!complete)
1076 ret = -EAGAIN;
1077
1078 /* clean the command send queue */
1079 handle = hns_roce_cmq_csq_clean(hr_dev);
1080 if (handle != num)
1081 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
1082 handle, num);
1083
1084 spin_unlock_bh(&csq->lock);
1085
1086 return ret;
1087}
1088
6a04aed6
WHX		 1089int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1090 struct hns_roce_cmq_desc *desc, int num)
1091{
1092 int retval;
1093 int ret;
1094
1095 ret = hns_roce_v2_rst_process_cmd(hr_dev);
1096 if (ret == CMD_RST_PRC_SUCCESS)
1097 return 0;
1098 if (ret == CMD_RST_PRC_EBUSY)
1099 return ret;
1100
1101 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1102 if (ret) {
1103 retval = hns_roce_v2_rst_process_cmd(hr_dev);
1104 if (retval == CMD_RST_PRC_SUCCESS)
1105 return 0;
1106 else if (retval == CMD_RST_PRC_EBUSY)
1107 return retval;
1108 }
1109
1110 return ret;
1111}
1112
281d0ccf 1113static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 1114{
1115 struct hns_roce_query_version *resp;
1116 struct hns_roce_cmq_desc desc;
1117 int ret;
1118
1119 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1120 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1121 if (ret)
1122 return ret;
1123
1124 resp = (struct hns_roce_query_version *)desc.data;
1125 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 1126 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1127
1128 return 0;
1129}
1130
1131static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1132{
1133 struct hns_roce_query_fw_info *resp;
1134 struct hns_roce_cmq_desc desc;
1135 int ret;
1136
1137 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1138 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1139 if (ret)
1140 return ret;
1141
1142 resp = (struct hns_roce_query_fw_info *)desc.data;
1143 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1144
1145 return 0;
1146}
1147
1148static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1149{
1150 struct hns_roce_cfg_global_param *req;
1151 struct hns_roce_cmq_desc desc;
1152
1153 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1154 false);
1155
1156 req = (struct hns_roce_cfg_global_param *)desc.data;
1157 memset(req, 0, sizeof(*req));
1158 roce_set_field(req->time_cfg_udp_port,
1159 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1160 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1161 roce_set_field(req->time_cfg_udp_port,
1162 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1163 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1164
1165 return hns_roce_cmq_send(hr_dev, &desc, 1);
1166}
1167
1168static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1169{
1170 struct hns_roce_cmq_desc desc[2];
6b63597d 1171 struct hns_roce_pf_res_a *req_a;
1172 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1173 int ret;
1174 int i;
1175
1176 for (i = 0; i < 2; i++) {
1177 hns_roce_cmq_setup_basic_desc(&desc[i],
1178 HNS_ROCE_OPC_QUERY_PF_RES, true);
1179
1180 if (i == 0)
1181 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1182 else
1183 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1184 }
1185
1186 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1187 if (ret)
1188 return ret;
1189
6b63597d 1190 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1191 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1192
6b63597d 1193 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1194 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1195 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1196 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1197 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1198 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1199 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1200 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1201 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1202 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1203 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1204 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1205
6b63597d 1206 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1207 PF_RES_DATA_3_PF_SL_NUM_M,
1208 PF_RES_DATA_3_PF_SL_NUM_S);
6a157f7d
YL		 1209 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,
1210 PF_RES_DATA_4_PF_SCCC_BT_NUM_M,
1211 PF_RES_DATA_4_PF_SCCC_BT_NUM_S);
6b63597d 1212
cfc85f3e
WHX		 1213 return 0;
1214}
1215
0e40dc2f
YL		 1216static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
1217{
1218 struct hns_roce_pf_timer_res_a *req_a;
1219 struct hns_roce_cmq_desc desc[2];
1220 int ret, i;
1221
1222 for (i = 0; i < 2; i++) {
1223 hns_roce_cmq_setup_basic_desc(&desc[i],
1224 HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1225 true);
1226
1227 if (i == 0)
1228 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1229 else
1230 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1231 }
1232
1233 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1234 if (ret)
1235 return ret;
1236
1237 req_a = (struct hns_roce_pf_timer_res_a *)desc[0].data;
1238
1239 hr_dev->caps.qpc_timer_bt_num =
1240 roce_get_field(req_a->qpc_timer_bt_idx_num,
1241 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
1242 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
1243 hr_dev->caps.cqc_timer_bt_num =
1244 roce_get_field(req_a->cqc_timer_bt_idx_num,
1245 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
1246 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
1247
1248 return 0;
1249}
1250
0c1c3880
LO		 1251static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,
1252 int vf_id)
1253{
1254 struct hns_roce_cmq_desc desc;
1255 struct hns_roce_vf_switch *swt;
1256 int ret;
1257
1258 swt = (struct hns_roce_vf_switch *)desc.data;
1259 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
1260 swt->rocee_sel |= cpu_to_le16(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
1261 roce_set_field(swt->fun_id,
1262 VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1263 VF_SWITCH_DATA_FUN_ID_VF_ID_S,
1264 vf_id);
1265 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1266 if (ret)
1267 return ret;
1268 desc.flag =
1269 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1270 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1271 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
1272 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 1);
1273 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1274
1275 return hns_roce_cmq_send(hr_dev, &desc, 1);
1276}
1277
cfc85f3e
WHX		 1278static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1279{
1280 struct hns_roce_cmq_desc desc[2];
1281 struct hns_roce_vf_res_a *req_a;
1282 struct hns_roce_vf_res_b *req_b;
1283 int i;
1284
1285 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1286 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1287 memset(req_a, 0, sizeof(*req_a));
1288 memset(req_b, 0, sizeof(*req_b));
1289 for (i = 0; i < 2; i++) {
1290 hns_roce_cmq_setup_basic_desc(&desc[i],
1291 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1292
1293 if (i == 0)
1294 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1295 else
1296 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1297
1298 if (i == 0) {
1299 roce_set_field(req_a->vf_qpc_bt_idx_num,
1300 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1301 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1302 roce_set_field(req_a->vf_qpc_bt_idx_num,
1303 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1304 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
1305 HNS_ROCE_VF_QPC_BT_NUM);
1306
1307 roce_set_field(req_a->vf_srqc_bt_idx_num,
1308 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1309 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1310 roce_set_field(req_a->vf_srqc_bt_idx_num,
1311 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1312 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1313 HNS_ROCE_VF_SRQC_BT_NUM);
1314
1315 roce_set_field(req_a->vf_cqc_bt_idx_num,
1316 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1317 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1318 roce_set_field(req_a->vf_cqc_bt_idx_num,
1319 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1320 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
1321 HNS_ROCE_VF_CQC_BT_NUM);
1322
1323 roce_set_field(req_a->vf_mpt_bt_idx_num,
1324 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1325 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1326 roce_set_field(req_a->vf_mpt_bt_idx_num,
1327 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1328 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
1329 HNS_ROCE_VF_MPT_BT_NUM);
1330
1331 roce_set_field(req_a->vf_eqc_bt_idx_num,
1332 VF_RES_A_DATA_5_VF_EQC_IDX_M,
1333 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1334 roce_set_field(req_a->vf_eqc_bt_idx_num,
1335 VF_RES_A_DATA_5_VF_EQC_NUM_M,
1336 VF_RES_A_DATA_5_VF_EQC_NUM_S,
1337 HNS_ROCE_VF_EQC_NUM);
1338 } else {
1339 roce_set_field(req_b->vf_smac_idx_num,
1340 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1341 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1342 roce_set_field(req_b->vf_smac_idx_num,
1343 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1344 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
1345 HNS_ROCE_VF_SMAC_NUM);
1346
1347 roce_set_field(req_b->vf_sgid_idx_num,
1348 VF_RES_B_DATA_2_VF_SGID_IDX_M,
1349 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1350 roce_set_field(req_b->vf_sgid_idx_num,
1351 VF_RES_B_DATA_2_VF_SGID_NUM_M,
1352 VF_RES_B_DATA_2_VF_SGID_NUM_S,
1353 HNS_ROCE_VF_SGID_NUM);
1354
1355 roce_set_field(req_b->vf_qid_idx_sl_num,
1356 VF_RES_B_DATA_3_VF_QID_IDX_M,
1357 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1358 roce_set_field(req_b->vf_qid_idx_sl_num,
1359 VF_RES_B_DATA_3_VF_SL_NUM_M,
1360 VF_RES_B_DATA_3_VF_SL_NUM_S,
1361 HNS_ROCE_VF_SL_NUM);
6a157f7d
YL		 1362
1363 roce_set_field(req_b->vf_sccc_idx_num,
1364 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,
1365 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);
1366 roce_set_field(req_b->vf_sccc_idx_num,
1367 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,
1368 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,
1369 HNS_ROCE_VF_SCCC_BT_NUM);
cfc85f3e
WHX		 1370 }
1371 }
1372
1373 return hns_roce_cmq_send(hr_dev, desc, 2);
1374}
1375
a81fba28
WHX		 1376static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1377{
1378 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1379 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1380 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1381 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
6a157f7d 1382 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;
a81fba28
WHX		 1383 struct hns_roce_cfg_bt_attr *req;
1384 struct hns_roce_cmq_desc desc;
1385
1386 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1387 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1388 memset(req, 0, sizeof(*req));
1389
1390 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1391 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1392 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1393 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1394 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1395 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1396 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1397 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1398 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1399
1400 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1401 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1402 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1403 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1404 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1405 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1406 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1407 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1408 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1409
1410 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1411 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1412 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1413 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1414 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1415 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1416 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1417 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1418 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1419
1420 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1421 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1422 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1423 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1424 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1425 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1426 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1427 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1428 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1429
6a157f7d
YL		 1430 roce_set_field(req->vf_sccc_cfg,
1431 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,
1432 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,
1433 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1434 roce_set_field(req->vf_sccc_cfg,
1435 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,
1436 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,
1437 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1438 roce_set_field(req->vf_sccc_cfg,
1439 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,
1440 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,
1441 sccc_hop_num ==
1442 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);
1443
a81fba28
WHX		 1444 return hns_roce_cmq_send(hr_dev, &desc, 1);
1445}
1446
cfc85f3e
WHX		 1447static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
1448{
1449 struct hns_roce_caps *caps = &hr_dev->caps;
1450 int ret;
1451
1452 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 1453 if (ret) {
1454 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
1455 ret);
1456 return ret;
1457 }
1458
1459 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 1460 if (ret) {
1461 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
1462 ret);
1463 return ret;
1464 }
1465
1466 ret = hns_roce_config_global_param(hr_dev);
1467 if (ret) {
1468 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
1469 ret);
2349fdd4 1470 return ret;
cfc85f3e
WHX		 1471 }
1472
1473 /* Get pf resource owned by every pf */
1474 ret = hns_roce_query_pf_resource(hr_dev);
1475 if (ret) {
1476 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
1477 ret);
1478 return ret;
1479 }
1480
0e40dc2f
YL		 1481 if (hr_dev->pci_dev->revision == 0x21) {
1482 ret = hns_roce_query_pf_timer_resource(hr_dev);
1483 if (ret) {
1484 dev_err(hr_dev->dev,
1485 "Query pf timer resource fail, ret = %d.\n",
1486 ret);
1487 return ret;
1488 }
1489 }
1490
cfc85f3e
WHX		 1491 ret = hns_roce_alloc_vf_resource(hr_dev);
1492 if (ret) {
1493 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
1494 ret);
1495 return ret;
1496 }
1497
0c1c3880
LO		 1498 if (hr_dev->pci_dev->revision == 0x21) {
1499 ret = hns_roce_set_vf_switch_param(hr_dev, 0);
1500 if (ret) {
1501 dev_err(hr_dev->dev,
1502 "Set function switch param fail, ret = %d.\n",
1503 ret);
1504 return ret;
1505 }
1506 }
3a63c964
LO		 1507
1508 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
1509 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e
WHX		 1510
1511 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1512 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1513 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
5c1f167a 1514 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
cfc85f3e 1515 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
5c1f167a 1516 caps->max_srqwqes = HNS_ROCE_V2_MAX_SRQWQE_NUM;
cfc85f3e 1517 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
05ad5482 1518 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
cfc85f3e
WHX		 1519 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1520 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
5c1f167a 1521 caps->max_srq_sg = HNS_ROCE_V2_MAX_SRQ_SGE_NUM;
cfc85f3e
WHX		 1522 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1523 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
a5073d60
YL		 1524 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1525 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1526 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
cfc85f3e
WHX		 1527 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1528 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1529 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
5c1f167a
LO		 1530 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1531 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
cfc85f3e
WHX		 1532 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1533 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1534 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1535 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1536 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1537 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1538 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1539 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 1540 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e 1541 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
5c1f167a 1542 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
cfc85f3e
WHX		 1543 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1544 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
5c1f167a 1545 caps->idx_entry_sz = 4;
cfc85f3e
WHX		 1546 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1547 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1548 caps->reserved_lkey = 0;
1549 caps->reserved_pds = 0;
1550 caps->reserved_mrws = 1;
1551 caps->reserved_uars = 0;
1552 caps->reserved_cqs = 0;
5c1f167a 1553 caps->reserved_srqs = 0;
06ef0ee4 1554 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
cfc85f3e 1555
a25d13cb
SX		 1556 caps->qpc_ba_pg_sz = 0;
1557 caps->qpc_buf_pg_sz = 0;
1558 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1559 caps->srqc_ba_pg_sz = 0;
1560 caps->srqc_buf_pg_sz = 0;
1561 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
1562 caps->cqc_ba_pg_sz = 0;
1563 caps->cqc_buf_pg_sz = 0;
1564 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1565 caps->mpt_ba_pg_sz = 0;
1566 caps->mpt_buf_pg_sz = 0;
1567 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
91fb4d83 1568 caps->pbl_ba_pg_sz = 2;
ff795f71
WHX		 1569 caps->pbl_buf_pg_sz = 0;
1570 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 1571 caps->mtt_ba_pg_sz = 0;
1572 caps->mtt_buf_pg_sz = 0;
1573 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1574 caps->cqe_ba_pg_sz = 0;
1575 caps->cqe_buf_pg_sz = 0;
1576 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
c7bcb134
LO		 1577 caps->srqwqe_ba_pg_sz = 0;
1578 caps->srqwqe_buf_pg_sz = 0;
1579 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
1580 caps->idx_ba_pg_sz = 0;
1581 caps->idx_buf_pg_sz = 0;
1582 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
a5073d60
YL		 1583 caps->eqe_ba_pg_sz = 0;
1584 caps->eqe_buf_pg_sz = 0;
1585 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 1586 caps->tsq_buf_pg_sz = 0;
29a1fe5d 1587 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 1588
023c1477 1589 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
0009c2db 1590 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
e088a685 1591 HNS_ROCE_CAP_FLAG_RQ_INLINE |
0425e3e6
YL		 1592 HNS_ROCE_CAP_FLAG_RECORD_DB |
1593 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
c7c28191
YL		 1594
1595 if (hr_dev->pci_dev->revision == 0x21)
68a997c5
YL		 1596 caps->flags |= HNS_ROCE_CAP_FLAG_MW |
1597 HNS_ROCE_CAP_FLAG_FRMR;
c7c28191 1598
cfc85f3e 1599 caps->pkey_table_len[0] = 1;
b5ff0f61 1600 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
a5073d60
YL		 1601 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1602 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
cfc85f3e
WHX		 1603 caps->local_ca_ack_delay = 0;
1604 caps->max_mtu = IB_MTU_4096;
1605
d16da119
LO		 1606 caps->max_srqs = HNS_ROCE_V2_MAX_SRQ;
1607 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1608 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1609
6a157f7d 1610 if (hr_dev->pci_dev->revision == 0x21) {
d16da119 1611 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC |
aa84fa18
YL		 1612 HNS_ROCE_CAP_FLAG_SRQ |
1613 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
1614
0e40dc2f
YL		 1615 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1616 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1617 caps->qpc_timer_ba_pg_sz = 0;
1618 caps->qpc_timer_buf_pg_sz = 0;
1619 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1620 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1621 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1622 caps->cqc_timer_ba_pg_sz = 0;
1623 caps->cqc_timer_buf_pg_sz = 0;
1624 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1625
6a157f7d
YL		 1626 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
1627 caps->sccc_ba_pg_sz = 0;
1628 caps->sccc_buf_pg_sz = 0;
1629 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
1630 }
384f8818 1631
a81fba28
WHX		 1632 ret = hns_roce_v2_set_bt(hr_dev);
1633 if (ret)
1634 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
1635 ret);
1636
1637 return ret;
cfc85f3e
WHX		 1638}
1639
6b63597d 1640static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
1641 enum hns_roce_link_table_type type)
1642{
1643 struct hns_roce_cmq_desc desc[2];
1644 struct hns_roce_cfg_llm_a *req_a =
1645 (struct hns_roce_cfg_llm_a *)desc[0].data;
1646 struct hns_roce_cfg_llm_b *req_b =
1647 (struct hns_roce_cfg_llm_b *)desc[1].data;
1648 struct hns_roce_v2_priv *priv = hr_dev->priv;
1649 struct hns_roce_link_table *link_tbl;
1650 struct hns_roce_link_table_entry *entry;
1651 enum hns_roce_opcode_type opcode;
1652 u32 page_num;
1653 int i;
1654
1655 switch (type) {
1656 case TSQ_LINK_TABLE:
1657 link_tbl = &priv->tsq;
1658 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
1659 break;
ded58ff9 1660 case TPQ_LINK_TABLE:
1661 link_tbl = &priv->tpq;
1662 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
1663 break;
6b63597d 1664 default:
1665 return -EINVAL;
1666 }
1667
1668 page_num = link_tbl->npages;
1669 entry = link_tbl->table.buf;
1670 memset(req_a, 0, sizeof(*req_a));
1671 memset(req_b, 0, sizeof(*req_b));
1672
1673 for (i = 0; i < 2; i++) {
1674 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
1675
1676 if (i == 0)
1677 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1678 else
1679 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1680
1681 if (i == 0) {
1682 req_a->base_addr_l = link_tbl->table.map & 0xffffffff;
1683 req_a->base_addr_h = (link_tbl->table.map >> 32) &
1684 0xffffffff;
1685 roce_set_field(req_a->depth_pgsz_init_en,
1686 CFG_LLM_QUE_DEPTH_M,
1687 CFG_LLM_QUE_DEPTH_S,
1688 link_tbl->npages);
1689 roce_set_field(req_a->depth_pgsz_init_en,
1690 CFG_LLM_QUE_PGSZ_M,
1691 CFG_LLM_QUE_PGSZ_S,
1692 link_tbl->pg_sz);
1693 req_a->head_ba_l = entry[0].blk_ba0;
1694 req_a->head_ba_h_nxtptr = entry[0].blk_ba1_nxt_ptr;
1695 roce_set_field(req_a->head_ptr,
1696 CFG_LLM_HEAD_PTR_M,
1697 CFG_LLM_HEAD_PTR_S, 0);
1698 } else {
1699 req_b->tail_ba_l = entry[page_num - 1].blk_ba0;
1700 roce_set_field(req_b->tail_ba_h,
1701 CFG_LLM_TAIL_BA_H_M,
1702 CFG_LLM_TAIL_BA_H_S,
1703 entry[page_num - 1].blk_ba1_nxt_ptr &
1704 HNS_ROCE_LINK_TABLE_BA1_M);
1705 roce_set_field(req_b->tail_ptr,
1706 CFG_LLM_TAIL_PTR_M,
1707 CFG_LLM_TAIL_PTR_S,
1708 (entry[page_num - 2].blk_ba1_nxt_ptr &
1709 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
1710 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
1711 }
1712 }
1713 roce_set_field(req_a->depth_pgsz_init_en,
1714 CFG_LLM_INIT_EN_M, CFG_LLM_INIT_EN_S, 1);
1715
1716 return hns_roce_cmq_send(hr_dev, desc, 2);
1717}
1718
1719static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
1720 enum hns_roce_link_table_type type)
1721{
1722 struct hns_roce_v2_priv *priv = hr_dev->priv;
1723 struct hns_roce_link_table *link_tbl;
1724 struct hns_roce_link_table_entry *entry;
1725 struct device *dev = hr_dev->dev;
1726 u32 buf_chk_sz;
1727 dma_addr_t t;
ded58ff9 1728 int func_num = 1;
6b63597d 1729 int pg_num_a;
1730 int pg_num_b;
1731 int pg_num;
1732 int size;
1733 int i;
1734
1735 switch (type) {
1736 case TSQ_LINK_TABLE:
1737 link_tbl = &priv->tsq;
1738 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
1739 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
1740 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
1741 break;
ded58ff9 1742 case TPQ_LINK_TABLE:
1743 link_tbl = &priv->tpq;
1744 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
1745 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
1746 pg_num_b = 2 * 4 * func_num + 2;
1747 break;
6b63597d 1748 default:
1749 return -EINVAL;
1750 }
1751
1752 pg_num = max(pg_num_a, pg_num_b);
1753 size = pg_num * sizeof(struct hns_roce_link_table_entry);
1754
1755 link_tbl->table.buf = dma_alloc_coherent(dev, size,
1756 &link_tbl->table.map,
1757 GFP_KERNEL);
1758 if (!link_tbl->table.buf)
1759 goto out;
1760
1761 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
1762 GFP_KERNEL);
1763 if (!link_tbl->pg_list)
1764 goto err_kcalloc_failed;
1765
1766 entry = link_tbl->table.buf;
1767 for (i = 0; i < pg_num; ++i) {
1768 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
1769 &t, GFP_KERNEL);
1770 if (!link_tbl->pg_list[i].buf)
1771 goto err_alloc_buf_failed;
1772
1773 link_tbl->pg_list[i].map = t;
1774 memset(link_tbl->pg_list[i].buf, 0, buf_chk_sz);
1775
1776 entry[i].blk_ba0 = (t >> 12) & 0xffffffff;
1777 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1778 HNS_ROCE_LINK_TABLE_BA1_M,
1779 HNS_ROCE_LINK_TABLE_BA1_S,
1780 t >> 44);
1781
1782 if (i < (pg_num - 1))
1783 roce_set_field(entry[i].blk_ba1_nxt_ptr,
1784 HNS_ROCE_LINK_TABLE_NXT_PTR_M,
1785 HNS_ROCE_LINK_TABLE_NXT_PTR_S,
1786 i + 1);
1787 }
1788 link_tbl->npages = pg_num;
1789 link_tbl->pg_sz = buf_chk_sz;
1790
1791 return hns_roce_config_link_table(hr_dev, type);
1792
1793err_alloc_buf_failed:
1794 for (i -= 1; i >= 0; i--)
1795 dma_free_coherent(dev, buf_chk_sz,
1796 link_tbl->pg_list[i].buf,
1797 link_tbl->pg_list[i].map);
1798 kfree(link_tbl->pg_list);
1799
1800err_kcalloc_failed:
1801 dma_free_coherent(dev, size, link_tbl->table.buf,
1802 link_tbl->table.map);
1803
1804out:
1805 return -ENOMEM;
1806}
1807
1808static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
1809 struct hns_roce_link_table *link_tbl)
1810{
1811 struct device *dev = hr_dev->dev;
1812 int size;
1813 int i;
1814
1815 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
1816
1817 for (i = 0; i < link_tbl->npages; ++i)
1818 if (link_tbl->pg_list[i].buf)
1819 dma_free_coherent(dev, link_tbl->pg_sz,
1820 link_tbl->pg_list[i].buf,
1821 link_tbl->pg_list[i].map);
1822 kfree(link_tbl->pg_list);
1823
1824 dma_free_coherent(dev, size, link_tbl->table.buf,
1825 link_tbl->table.map);
1826}
1827
1828static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
1829{
ded58ff9 1830 struct hns_roce_v2_priv *priv = hr_dev->priv;
0e40dc2f
YL		 1831 int qpc_count, cqc_count;
1832 int ret, i;
6b63597d 1833
1834 /* TSQ includes SQ doorbell and ack doorbell */
1835 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 1836 if (ret) {
6b63597d 1837 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 1838 return ret;
1839 }
1840
1841 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
1842 if (ret) {
1843 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
1844 goto err_tpq_init_failed;
1845 }
1846
0e40dc2f
YL		 1847 /* Alloc memory for QPC Timer buffer space chunk*/
1848 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
1849 qpc_count++) {
1850 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
1851 qpc_count);
1852 if (ret) {
1853 dev_err(hr_dev->dev, "QPC Timer get failed\n");
1854 goto err_qpc_timer_failed;
1855 }
1856 }
1857
1858 /* Alloc memory for CQC Timer buffer space chunk*/
1859 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
1860 cqc_count++) {
1861 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
1862 cqc_count);
1863 if (ret) {
1864 dev_err(hr_dev->dev, "CQC Timer get failed\n");
1865 goto err_cqc_timer_failed;
1866 }
1867 }
1868
ded58ff9 1869 return 0;
1870
0e40dc2f
YL		 1871err_cqc_timer_failed:
1872 for (i = 0; i < cqc_count; i++)
1873 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
1874
1875err_qpc_timer_failed:
1876 for (i = 0; i < qpc_count; i++)
1877 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
1878
1879 hns_roce_free_link_table(hr_dev, &priv->tpq);
1880
ded58ff9 1881err_tpq_init_failed:
1882 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 1883
1884 return ret;
1885}
1886
1887static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
1888{
1889 struct hns_roce_v2_priv *priv = hr_dev->priv;
1890
ded58ff9 1891 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 1892 hns_roce_free_link_table(hr_dev, &priv->tsq);
1893}
1894
f747b689
LO		 1895static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
1896{
1897 struct hns_roce_cmq_desc desc;
1898 struct hns_roce_mbox_status *mb_st =
1899 (struct hns_roce_mbox_status *)desc.data;
1900 enum hns_roce_cmd_return_status status;
1901
1902 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
1903
1904 status = hns_roce_cmq_send(hr_dev, &desc, 1);
1905 if (status)
1906 return status;
1907
1908 return cpu_to_le32(mb_st->mb_status_hw_run);
1909}
1910
a680f2f3
WHX		 1911static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
1912{
f747b689 1913 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 1914
1915 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
1916}
1917
1918static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
1919{
f747b689 1920 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 1921
1922 return status & HNS_ROCE_HW_MB_STATUS_MASK;
1923}
1924
f747b689
LO		 1925static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
1926 u64 out_param, u32 in_modifier, u8 op_modifier,
1927 u16 op, u16 token, int event)
1928{
1929 struct hns_roce_cmq_desc desc;
1930 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
1931
1932 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
1933
1934 mb->in_param_l = cpu_to_le64(in_param);
1935 mb->in_param_h = cpu_to_le64(in_param) >> 32;
1936 mb->out_param_l = cpu_to_le64(out_param);
1937 mb->out_param_h = cpu_to_le64(out_param) >> 32;
1938 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
1939 mb->token_event_en = cpu_to_le32(event << 16 | token);
1940
1941 return hns_roce_cmq_send(hr_dev, &desc, 1);
1942}
1943
a680f2f3
WHX		 1944static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1945 u64 out_param, u32 in_modifier, u8 op_modifier,
1946 u16 op, u16 token, int event)
1947{
1948 struct device *dev = hr_dev->dev;
a680f2f3 1949 unsigned long end;
f747b689 1950 int ret;
a680f2f3
WHX		 1951
1952 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1953 while (hns_roce_v2_cmd_pending(hr_dev)) {
1954 if (time_after(jiffies, end)) {
1955 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1956 (int)end);
1957 return -EAGAIN;
1958 }
1959 cond_resched();
1960 }
1961
f747b689
LO		 1962 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
1963 op_modifier, op, token, event);
1964 if (ret)
1965 dev_err(dev, "Post mailbox fail(%d)\n", ret);
a680f2f3 1966
f747b689 1967 return ret;
a680f2f3
WHX		 1968}
1969
1970static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1971 unsigned long timeout)
1972{
1973 struct device *dev = hr_dev->dev;
1974 unsigned long end = 0;
1975 u32 status;
1976
1977 end = msecs_to_jiffies(timeout) + jiffies;
1978 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1979 cond_resched();
1980
1981 if (hns_roce_v2_cmd_pending(hr_dev)) {
1982 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1983 return -ETIMEDOUT;
1984 }
1985
1986 status = hns_roce_v2_cmd_complete(hr_dev);
1987 if (status != 0x1) {
6a04aed6
WHX		 1988 if (status == CMD_RST_PRC_EBUSY)
1989 return status;
1990
a680f2f3
WHX		 1991 dev_err(dev, "mailbox status 0x%x!\n", status);
1992 return -EBUSY;
1993 }
1994
1995 return 0;
1996}
1997
4db134a3 1998static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
1999 int gid_index, const union ib_gid *gid,
2000 enum hns_roce_sgid_type sgid_type)
2001{
2002 struct hns_roce_cmq_desc desc;
2003 struct hns_roce_cfg_sgid_tb *sgid_tb =
2004 (struct hns_roce_cfg_sgid_tb *)desc.data;
2005 u32 *p;
2006
2007 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2008
2009 roce_set_field(sgid_tb->table_idx_rsv,
2010 CFG_SGID_TB_TABLE_IDX_M,
2011 CFG_SGID_TB_TABLE_IDX_S, gid_index);
2012 roce_set_field(sgid_tb->vf_sgid_type_rsv,
2013 CFG_SGID_TB_VF_SGID_TYPE_M,
2014 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2015
2016 p = (u32 *)&gid->raw[0];
2017 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
2018
2019 p = (u32 *)&gid->raw[4];
2020 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
2021
2022 p = (u32 *)&gid->raw[8];
2023 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
2024
2025 p = (u32 *)&gid->raw[0xc];
2026 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
2027
2028 return hns_roce_cmq_send(hr_dev, &desc, 1);
2029}
2030
b5ff0f61 2031static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 2032 int gid_index, const union ib_gid *gid,
b5ff0f61 2033 const struct ib_gid_attr *attr)
7afddafa 2034{
b5ff0f61 2035 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 2036 int ret;
7afddafa 2037
b5ff0f61
WHX		 2038 if (!gid || !attr)
2039 return -EINVAL;
2040
2041 if (attr->gid_type == IB_GID_TYPE_ROCE)
2042 sgid_type = GID_TYPE_FLAG_ROCE_V1;
2043
2044 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2045 if (ipv6_addr_v4mapped((void *)gid))
2046 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
2047 else
2048 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
2049 }
2050
4db134a3 2051 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
2052 if (ret)
2053 dev_err(hr_dev->dev, "Configure sgid table failed(%d)!\n", ret);
b5ff0f61 2054
4db134a3 2055 return ret;
7afddafa
WHX		 2056}
2057
a74dc41d
WHX		 2058static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
2059 u8 *addr)
7afddafa 2060{
e8e8b652 2061 struct hns_roce_cmq_desc desc;
2062 struct hns_roce_cfg_smac_tb *smac_tb =
2063 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 2064 u16 reg_smac_h;
2065 u32 reg_smac_l;
e8e8b652 2066
2067 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 2068
2069 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 2070 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 2071
e8e8b652 2072 memset(smac_tb, 0, sizeof(*smac_tb));
2073 roce_set_field(smac_tb->tb_idx_rsv,
2074 CFG_SMAC_TB_IDX_M,
2075 CFG_SMAC_TB_IDX_S, phy_port);
2076 roce_set_field(smac_tb->vf_smac_h_rsv,
2077 CFG_SMAC_TB_VF_SMAC_H_M,
2078 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
2079 smac_tb->vf_smac_l = reg_smac_l;
a74dc41d 2080
e8e8b652 2081 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 2082}
2083
ca088320
YL		 2084static int set_mtpt_pbl(struct hns_roce_v2_mpt_entry *mpt_entry,
2085 struct hns_roce_mr *mr)
3958cc56 2086{
3856ec55 2087 struct sg_dma_page_iter sg_iter;
db270c41 2088 u64 page_addr;
3958cc56 2089 u64 *pages;
3856ec55 2090 int i;
3958cc56 2091
ca088320
YL		 2092 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2093 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2094 roce_set_field(mpt_entry->byte_48_mode_ba,
2095 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
2096 upper_32_bits(mr->pbl_ba >> 3));
2097
2098 pages = (u64 *)__get_free_page(GFP_KERNEL);
2099 if (!pages)
2100 return -ENOMEM;
2101
2102 i = 0;
3856ec55
SS		 2103 for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
2104 page_addr = sg_page_iter_dma_address(&sg_iter);
2105 pages[i] = page_addr >> 6;
2106
2107 /* Record the first 2 entry directly to MTPT table */
2108 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
2109 goto found;
2110 i++;
ca088320
YL		 2111 }
2112found:
2113 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
2114 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
2115 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
2116
2117 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
2118 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
2119 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
2120 roce_set_field(mpt_entry->byte_64_buf_pa1,
2121 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2122 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2123 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2124
2125 free_page((unsigned long)pages);
2126
2127 return 0;
2128}
2129
2130static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
2131 unsigned long mtpt_idx)
2132{
2133 struct hns_roce_v2_mpt_entry *mpt_entry;
2134 int ret;
2135
3958cc56
WHX		 2136 mpt_entry = mb_buf;
2137 memset(mpt_entry, 0, sizeof(*mpt_entry));
2138
2139 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2140 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2141 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2142 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
2143 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
2144 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2145 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db
YL		 2146 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2147 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
3958cc56
WHX		 2148 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2149 V2_MPT_BYTE_4_PD_S, mr->pd);
3958cc56
WHX		 2150
2151 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
2152 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
e93df010 2153 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 2154 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
2155 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 2156 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
2157 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 2158 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2159 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
2160 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2161 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
2162 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2163 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
3958cc56
WHX		 2164
2165 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
2166 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 2167 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
2168 1);
3958cc56
WHX		 2169
2170 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
2171 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
2172 mpt_entry->lkey = cpu_to_le32(mr->key);
2173 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
2174 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
2175
2176 if (mr->type == MR_TYPE_DMA)
2177 return 0;
2178
ca088320 2179 ret = set_mtpt_pbl(mpt_entry, mr);
3958cc56 2180
ca088320 2181 return ret;
3958cc56
WHX		 2182}
2183
a2c80b7b
WHX		 2184static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
2185 struct hns_roce_mr *mr, int flags,
2186 u32 pdn, int mr_access_flags, u64 iova,
2187 u64 size, void *mb_buf)
2188{
2189 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
ca088320 2190 int ret = 0;
a2c80b7b
WHX		 2191
2192 if (flags & IB_MR_REREG_PD) {
2193 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2194 V2_MPT_BYTE_4_PD_S, pdn);
2195 mr->pd = pdn;
2196 }
2197
2198 if (flags & IB_MR_REREG_ACCESS) {
2199 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2200 V2_MPT_BYTE_8_BIND_EN_S,
2201 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
2202 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
ca088320
YL		 2203 V2_MPT_BYTE_8_ATOMIC_EN_S,
2204 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
a2c80b7b 2205 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
ca088320 2206 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
a2c80b7b 2207 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
ca088320 2208 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
a2c80b7b 2209 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
ca088320 2210 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
a2c80b7b
WHX		 2211 }
2212
2213 if (flags & IB_MR_REREG_TRANS) {
2214 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
2215 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
2216 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
2217 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
2218
a2c80b7b
WHX		 2219 mr->iova = iova;
2220 mr->size = size;
ca088320
YL		 2221
2222 ret = set_mtpt_pbl(mpt_entry, mr);
a2c80b7b
WHX		 2223 }
2224
ca088320 2225 return ret;
a2c80b7b
WHX		 2226}
2227
68a997c5
YL		 2228static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr)
2229{
2230 struct hns_roce_v2_mpt_entry *mpt_entry;
2231
2232 mpt_entry = mb_buf;
2233 memset(mpt_entry, 0, sizeof(*mpt_entry));
2234
2235 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2236 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2237 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2238 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
2239 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2240 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2241 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2242 mr->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2243 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2244 V2_MPT_BYTE_4_PD_S, mr->pd);
2245
2246 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
2247 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2248 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2249
2250 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
2251 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2252 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
2253 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2254
2255 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
2256
2257 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
2258 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
2259 V2_MPT_BYTE_48_PBL_BA_H_S,
2260 upper_32_bits(mr->pbl_ba >> 3));
2261
2262 roce_set_field(mpt_entry->byte_64_buf_pa1,
2263 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2264 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2265 mr->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2266
2267 return 0;
2268}
2269
c7c28191
YL		 2270static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
2271{
2272 struct hns_roce_v2_mpt_entry *mpt_entry;
2273
2274 mpt_entry = mb_buf;
2275 memset(mpt_entry, 0, sizeof(*mpt_entry));
2276
2277 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2278 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2279 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2280 V2_MPT_BYTE_4_PD_S, mw->pdn);
2281 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2282 V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2283 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
2284 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ?
2285 0 : mw->pbl_hop_num);
2286 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2287 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2288 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2289 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2290
2291 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2292 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2293
2294 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2295 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
2296 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2297 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
2298 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2299
2300 roce_set_field(mpt_entry->byte_64_buf_pa1,
2301 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2302 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2303 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2304
2305 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2306
2307 return 0;
2308}
2309
93aa2187
WHX		 2310static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2311{
2312 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2313 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
2314}
2315
2316static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2317{
2318 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2319
2320 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2321 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
2322 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
2323}
2324
2325static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
2326{
2327 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
2328}
2329
c7bcb134
LO		 2330static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
2331{
2332 return hns_roce_buf_offset(&srq->buf, n << srq->wqe_shift);
2333}
2334
2335static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index)
2336{
2337 u32 bitmap_num;
2338 int bit_num;
2339
2340 /* always called with interrupts disabled. */
2341 spin_lock(&srq->lock);
2342
2343 bitmap_num = wqe_index / (sizeof(u64) * 8);
2344 bit_num = wqe_index % (sizeof(u64) * 8);
2345 srq->idx_que.bitmap[bitmap_num] |= (1ULL << bit_num);
2346 srq->tail++;
2347
2348 spin_unlock(&srq->lock);
2349}
2350
93aa2187
WHX		 2351static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2352{
86188a88 2353 *hr_cq->set_ci_db = cons_index & 0xffffff;
93aa2187
WHX		 2354}
2355
926a01dc
WHX		 2356static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2357 struct hns_roce_srq *srq)
2358{
2359 struct hns_roce_v2_cqe *cqe, *dest;
2360 u32 prod_index;
2361 int nfreed = 0;
c7bcb134 2362 int wqe_index;
926a01dc
WHX		 2363 u8 owner_bit;
2364
2365 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2366 ++prod_index) {
2367 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2368 break;
2369 }
2370
2371 /*
2372 * Now backwards through the CQ, removing CQ entries
2373 * that match our QP by overwriting them with next entries.
2374 */
2375 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2376 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2377 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2378 V2_CQE_BYTE_16_LCL_QPN_S) &
2379 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
c7bcb134
LO		 2380 if (srq &&
2381 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) {
2382 wqe_index = roce_get_field(cqe->byte_4,
2383 V2_CQE_BYTE_4_WQE_INDX_M,
2384 V2_CQE_BYTE_4_WQE_INDX_S);
2385 hns_roce_free_srq_wqe(srq, wqe_index);
2386 }
926a01dc
WHX		 2387 ++nfreed;
2388 } else if (nfreed) {
2389 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2390 hr_cq->ib_cq.cqe);
2391 owner_bit = roce_get_bit(dest->byte_4,
2392 V2_CQE_BYTE_4_OWNER_S);
2393 memcpy(dest, cqe, sizeof(*cqe));
2394 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2395 owner_bit);
2396 }
2397 }
2398
2399 if (nfreed) {
2400 hr_cq->cons_index += nfreed;
2401 /*
2402 * Make sure update of buffer contents is done before
2403 * updating consumer index.
2404 */
2405 wmb();
2406 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2407 }
2408}
2409
2410static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2411 struct hns_roce_srq *srq)
2412{
2413 spin_lock_irq(&hr_cq->lock);
2414 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2415 spin_unlock_irq(&hr_cq->lock);
2416}
2417
93aa2187
WHX		 2418static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2419 struct hns_roce_cq *hr_cq, void *mb_buf,
2420 u64 *mtts, dma_addr_t dma_handle, int nent,
2421 u32 vector)
2422{
2423 struct hns_roce_v2_cq_context *cq_context;
2424
2425 cq_context = mb_buf;
2426 memset(cq_context, 0, sizeof(*cq_context));
2427
2428 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2429 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2430 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2431 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187
WHX		 2432 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
2433 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
2434 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
2435 V2_CQC_BYTE_4_CEQN_S, vector);
2436 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
2437
2438 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2439 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2440
2441 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2442 cq_context->cqe_cur_blk_addr =
2443 cpu_to_le32(cq_context->cqe_cur_blk_addr);
2444
2445 roce_set_field(cq_context->byte_16_hop_addr,
2446 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2447 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
2448 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
2449 roce_set_field(cq_context->byte_16_hop_addr,
2450 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2451 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2452 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2453
2454 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
2455 roce_set_field(cq_context->byte_24_pgsz_addr,
2456 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2457 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
2458 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
2459 roce_set_field(cq_context->byte_24_pgsz_addr,
2460 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2461 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
5e6e78db 2462 hr_dev->caps.cqe_ba_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2463 roce_set_field(cq_context->byte_24_pgsz_addr,
2464 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2465 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
5e6e78db 2466 hr_dev->caps.cqe_buf_pg_sz + PG_SHIFT_OFFSET);
93aa2187
WHX		 2467
2468 cq_context->cqe_ba = (u32)(dma_handle >> 3);
2469
2470 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2471 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2472
9b44703d
YL		 2473 if (hr_cq->db_en)
2474 roce_set_bit(cq_context->byte_44_db_record,
2475 V2_CQC_BYTE_44_DB_RECORD_EN_S, 1);
2476
2477 roce_set_field(cq_context->byte_44_db_record,
2478 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2479 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2480 ((u32)hr_cq->db.dma) >> 1);
2481 cq_context->db_record_addr = hr_cq->db.dma >> 32;
2482
a5073d60
YL		 2483 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2484 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2485 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2486 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2487 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2488 V2_CQC_BYTE_56_CQ_PERIOD_M,
2489 V2_CQC_BYTE_56_CQ_PERIOD_S,
2490 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2491}
2492
2493static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2494 enum ib_cq_notify_flags flags)
2495{
d3743fa9 2496 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 2497 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2498 u32 notification_flag;
2499 u32 doorbell[2];
2500
2501 doorbell[0] = 0;
2502 doorbell[1] = 0;
2503
2504 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2505 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2506 /*
2507 * flags = 0; Notification Flag = 1, next
2508 * flags = 1; Notification Flag = 0, solocited
2509 */
2510 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2511 hr_cq->cqn);
2512 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2513 HNS_ROCE_V2_CQ_DB_NTR);
2514 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
2515 V2_CQ_DB_PARAMETER_CONS_IDX_S,
2516 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2517 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2518 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2519 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2520 notification_flag);
2521
d3743fa9 2522 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l);
93aa2187
WHX		 2523
2524 return 0;
2525}
2526
0009c2db 2527static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2528 struct hns_roce_qp **cur_qp,
2529 struct ib_wc *wc)
2530{
2531 struct hns_roce_rinl_sge *sge_list;
2532 u32 wr_num, wr_cnt, sge_num;
2533 u32 sge_cnt, data_len, size;
2534 void *wqe_buf;
2535
2536 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2537 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2538 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2539
2540 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2541 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
2542 wqe_buf = get_recv_wqe(*cur_qp, wr_cnt);
2543 data_len = wc->byte_len;
2544
2545 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2546 size = min(sge_list[sge_cnt].len, data_len);
2547 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2548
2549 data_len -= size;
2550 wqe_buf += size;
2551 }
2552
2553 if (data_len) {
2554 wc->status = IB_WC_LOC_LEN_ERR;
2555 return -EAGAIN;
2556 }
2557
2558 return 0;
2559}
2560
93aa2187
WHX		 2561static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
2562 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2563{
c7bcb134 2564 struct hns_roce_srq *srq = NULL;
93aa2187
WHX		 2565 struct hns_roce_dev *hr_dev;
2566 struct hns_roce_v2_cqe *cqe;
2567 struct hns_roce_qp *hr_qp;
2568 struct hns_roce_wq *wq;
0425e3e6
YL		 2569 struct ib_qp_attr attr;
2570 int attr_mask;
93aa2187
WHX		 2571 int is_send;
2572 u16 wqe_ctr;
2573 u32 opcode;
2574 u32 status;
2575 int qpn;
0009c2db 2576 int ret;
93aa2187
WHX		 2577
2578 /* Find cqe according to consumer index */
2579 cqe = next_cqe_sw_v2(hr_cq);
2580 if (!cqe)
2581 return -EAGAIN;
2582
2583 ++hr_cq->cons_index;
2584 /* Memory barrier */
2585 rmb();
2586
2587 /* 0->SQ, 1->RQ */
2588 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
2589
2590 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2591 V2_CQE_BYTE_16_LCL_QPN_S);
2592
2593 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2594 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2595 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2596 if (unlikely(!hr_qp)) {
2597 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
2598 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
2599 return -EINVAL;
2600 }
2601 *cur_qp = hr_qp;
2602 }
2603
2604 wc->qp = &(*cur_qp)->ibqp;
2605 wc->vendor_err = 0;
2606
c7bcb134
LO		 2607 if (is_send) {
2608 wq = &(*cur_qp)->sq;
2609 if ((*cur_qp)->sq_signal_bits) {
2610 /*
2611 * If sg_signal_bit is 1,
2612 * firstly tail pointer updated to wqe
2613 * which current cqe correspond to
2614 */
2615 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
2616 V2_CQE_BYTE_4_WQE_INDX_M,
2617 V2_CQE_BYTE_4_WQE_INDX_S);
2618 wq->tail += (wqe_ctr - (u16)wq->tail) &
2619 (wq->wqe_cnt - 1);
2620 }
2621
2622 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2623 ++wq->tail;
2624 } else if ((*cur_qp)->ibqp.srq) {
2625 srq = to_hr_srq((*cur_qp)->ibqp.srq);
2626 wqe_ctr = le16_to_cpu(roce_get_field(cqe->byte_4,
2627 V2_CQE_BYTE_4_WQE_INDX_M,
2628 V2_CQE_BYTE_4_WQE_INDX_S));
2629 wc->wr_id = srq->wrid[wqe_ctr];
2630 hns_roce_free_srq_wqe(srq, wqe_ctr);
2631 } else {
2632 /* Update tail pointer, record wr_id */
2633 wq = &(*cur_qp)->rq;
2634 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2635 ++wq->tail;
2636 }
2637
93aa2187
WHX		 2638 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
2639 V2_CQE_BYTE_4_STATUS_S);
2640 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
2641 case HNS_ROCE_CQE_V2_SUCCESS:
2642 wc->status = IB_WC_SUCCESS;
2643 break;
2644 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
2645 wc->status = IB_WC_LOC_LEN_ERR;
2646 break;
2647 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
2648 wc->status = IB_WC_LOC_QP_OP_ERR;
2649 break;
2650 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
2651 wc->status = IB_WC_LOC_PROT_ERR;
2652 break;
2653 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
2654 wc->status = IB_WC_WR_FLUSH_ERR;
2655 break;
2656 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
2657 wc->status = IB_WC_MW_BIND_ERR;
2658 break;
2659 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
2660 wc->status = IB_WC_BAD_RESP_ERR;
2661 break;
2662 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
2663 wc->status = IB_WC_LOC_ACCESS_ERR;
2664 break;
2665 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
2666 wc->status = IB_WC_REM_INV_REQ_ERR;
2667 break;
2668 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
2669 wc->status = IB_WC_REM_ACCESS_ERR;
2670 break;
2671 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
2672 wc->status = IB_WC_REM_OP_ERR;
2673 break;
2674 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
2675 wc->status = IB_WC_RETRY_EXC_ERR;
2676 break;
2677 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
2678 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2679 break;
2680 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
2681 wc->status = IB_WC_REM_ABORT_ERR;
2682 break;
2683 default:
2684 wc->status = IB_WC_GENERAL_ERR;
2685 break;
2686 }
2687
0425e3e6
YL		 2688 /* flush cqe if wc status is error, excluding flush error */
2689 if ((wc->status != IB_WC_SUCCESS) &&
2690 (wc->status != IB_WC_WR_FLUSH_ERR)) {
2691 attr_mask = IB_QP_STATE;
2692 attr.qp_state = IB_QPS_ERR;
2693 return hns_roce_v2_modify_qp(&(*cur_qp)->ibqp,
2694 &attr, attr_mask,
2695 (*cur_qp)->state, IB_QPS_ERR);
2696 }
2697
2698 if (wc->status == IB_WC_WR_FLUSH_ERR)
93aa2187
WHX		 2699 return 0;
2700
2701 if (is_send) {
2702 wc->wc_flags = 0;
2703 /* SQ corresponding to CQE */
2704 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2705 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
2706 case HNS_ROCE_SQ_OPCODE_SEND:
2707 wc->opcode = IB_WC_SEND;
2708 break;
2709 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
2710 wc->opcode = IB_WC_SEND;
2711 break;
2712 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
2713 wc->opcode = IB_WC_SEND;
2714 wc->wc_flags |= IB_WC_WITH_IMM;
2715 break;
2716 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
2717 wc->opcode = IB_WC_RDMA_READ;
2718 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2719 break;
2720 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
2721 wc->opcode = IB_WC_RDMA_WRITE;
2722 break;
2723 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
2724 wc->opcode = IB_WC_RDMA_WRITE;
2725 wc->wc_flags |= IB_WC_WITH_IMM;
2726 break;
2727 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
2728 wc->opcode = IB_WC_LOCAL_INV;
2729 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2730 break;
2731 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
2732 wc->opcode = IB_WC_COMP_SWAP;
2733 wc->byte_len = 8;
2734 break;
2735 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
2736 wc->opcode = IB_WC_FETCH_ADD;
2737 wc->byte_len = 8;
2738 break;
2739 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
2740 wc->opcode = IB_WC_MASKED_COMP_SWAP;
2741 wc->byte_len = 8;
2742 break;
2743 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
2744 wc->opcode = IB_WC_MASKED_FETCH_ADD;
2745 wc->byte_len = 8;
2746 break;
2747 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
2748 wc->opcode = IB_WC_REG_MR;
2749 break;
2750 case HNS_ROCE_SQ_OPCODE_BIND_MW:
2751 wc->opcode = IB_WC_REG_MR;
2752 break;
2753 default:
2754 wc->status = IB_WC_GENERAL_ERR;
2755 break;
2756 }
93aa2187
WHX		 2757 } else {
2758 /* RQ correspond to CQE */
2759 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2760
2761 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
2762 V2_CQE_BYTE_4_OPCODE_S);
2763 switch (opcode & 0x1f) {
2764 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
2765 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2766 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2767 wc->ex.imm_data =
2768 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2769 break;
2770 case HNS_ROCE_V2_OPCODE_SEND:
2771 wc->opcode = IB_WC_RECV;
2772 wc->wc_flags = 0;
2773 break;
2774 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
2775 wc->opcode = IB_WC_RECV;
2776 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 2777 wc->ex.imm_data =
2778 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 2779 break;
2780 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
2781 wc->opcode = IB_WC_RECV;
2782 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 2783 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 2784 break;
2785 default:
2786 wc->status = IB_WC_GENERAL_ERR;
2787 break;
2788 }
2789
0009c2db 2790 if ((wc->qp->qp_type == IB_QPT_RC ||
2791 wc->qp->qp_type == IB_QPT_UC) &&
2792 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
2793 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
2794 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
2795 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
2796 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
2797 if (ret)
2798 return -EAGAIN;
2799 }
2800
93aa2187
WHX		 2801 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
2802 V2_CQE_BYTE_32_SL_S);
2803 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
2804 V2_CQE_BYTE_32_RMT_QPN_M,
2805 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 2806 wc->slid = 0;
93aa2187
WHX		 2807 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
2808 V2_CQE_BYTE_32_GRH_S) ?
2809 IB_WC_GRH : 0);
6c1f08b3 2810 wc->port_num = roce_get_field(cqe->byte_32,
2811 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
2812 wc->pkey_index = 0;
2eade675 2813 memcpy(wc->smac, cqe->smac, 4);
2814 wc->smac[4] = roce_get_field(cqe->byte_28,
2815 V2_CQE_BYTE_28_SMAC_4_M,
2816 V2_CQE_BYTE_28_SMAC_4_S);
2817 wc->smac[5] = roce_get_field(cqe->byte_28,
2818 V2_CQE_BYTE_28_SMAC_5_M,
2819 V2_CQE_BYTE_28_SMAC_5_S);
944e6409
LO		 2820 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
2821 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
2822 V2_CQE_BYTE_28_VID_M,
2823 V2_CQE_BYTE_28_VID_S);
2824 } else {
2825 wc->vlan_id = 0xffff;
2826 }
2827
2eade675 2828 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
2829 wc->network_hdr_type = roce_get_field(cqe->byte_28,
2830 V2_CQE_BYTE_28_PORT_TYPE_M,
2831 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 2832 }
2833
2834 return 0;
2835}
2836
2837static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
2838 struct ib_wc *wc)
2839{
2840 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2841 struct hns_roce_qp *cur_qp = NULL;
2842 unsigned long flags;
2843 int npolled;
2844
2845 spin_lock_irqsave(&hr_cq->lock, flags);
2846
2847 for (npolled = 0; npolled < num_entries; ++npolled) {
2848 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
2849 break;
2850 }
2851
2852 if (npolled) {
2853 /* Memory barrier */
2854 wmb();
2855 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2856 }
2857
2858 spin_unlock_irqrestore(&hr_cq->lock, flags);
2859
2860 return npolled;
2861}
2862
a81fba28
WHX		 2863static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
2864 struct hns_roce_hem_table *table, int obj,
2865 int step_idx)
2866{
2867 struct device *dev = hr_dev->dev;
2868 struct hns_roce_cmd_mailbox *mailbox;
2869 struct hns_roce_hem_iter iter;
2870 struct hns_roce_hem_mhop mhop;
2871 struct hns_roce_hem *hem;
2872 unsigned long mhop_obj = obj;
2873 int i, j, k;
2874 int ret = 0;
2875 u64 hem_idx = 0;
2876 u64 l1_idx = 0;
2877 u64 bt_ba = 0;
2878 u32 chunk_ba_num;
2879 u32 hop_num;
2880 u16 op = 0xff;
2881
2882 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2883 return 0;
2884
2885 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
2886 i = mhop.l0_idx;
2887 j = mhop.l1_idx;
2888 k = mhop.l2_idx;
2889 hop_num = mhop.hop_num;
2890 chunk_ba_num = mhop.bt_chunk_size / 8;
2891
2892 if (hop_num == 2) {
2893 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
2894 k;
2895 l1_idx = i * chunk_ba_num + j;
2896 } else if (hop_num == 1) {
2897 hem_idx = i * chunk_ba_num + j;
2898 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
2899 hem_idx = i;
2900 }
2901
2902 switch (table->type) {
2903 case HEM_TYPE_QPC:
2904 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
2905 break;
2906 case HEM_TYPE_MTPT:
2907 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
2908 break;
2909 case HEM_TYPE_CQC:
2910 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
2911 break;
2912 case HEM_TYPE_SRQC:
2913 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
2914 break;
6a157f7d
YL		 2915 case HEM_TYPE_SCCC:
2916 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
2917 break;
0e40dc2f
YL		 2918 case HEM_TYPE_QPC_TIMER:
2919 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
2920 break;
2921 case HEM_TYPE_CQC_TIMER:
2922 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
2923 break;
a81fba28
WHX		 2924 default:
2925 dev_warn(dev, "Table %d not to be written by mailbox!\n",
2926 table->type);
2927 return 0;
2928 }
6a157f7d
YL		 2929
2930 if (table->type == HEM_TYPE_SCCC && step_idx)
2931 return 0;
2932
a81fba28
WHX		 2933 op += step_idx;
2934
2935 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2936 if (IS_ERR(mailbox))
2937 return PTR_ERR(mailbox);
2938
2939 if (check_whether_last_step(hop_num, step_idx)) {
2940 hem = table->hem[hem_idx];
2941 for (hns_roce_hem_first(hem, &iter);
2942 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
2943 bt_ba = hns_roce_hem_addr(&iter);
2944
2945 /* configure the ba, tag, and op */
2946 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
2947 obj, 0, op,
2948 HNS_ROCE_CMD_TIMEOUT_MSECS);
2949 }
2950 } else {
2951 if (step_idx == 0)
2952 bt_ba = table->bt_l0_dma_addr[i];
2953 else if (step_idx == 1 && hop_num == 2)
2954 bt_ba = table->bt_l1_dma_addr[l1_idx];
2955
2956 /* configure the ba, tag, and op */
2957 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
2958 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
2959 }
2960
2961 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2962 return ret;
2963}
2964
2965static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
2966 struct hns_roce_hem_table *table, int obj,
2967 int step_idx)
2968{
2969 struct device *dev = hr_dev->dev;
2970 struct hns_roce_cmd_mailbox *mailbox;
2971 int ret = 0;
2972 u16 op = 0xff;
2973
2974 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
2975 return 0;
2976
2977 switch (table->type) {
2978 case HEM_TYPE_QPC:
2979 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
2980 break;
2981 case HEM_TYPE_MTPT:
2982 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
2983 break;
2984 case HEM_TYPE_CQC:
2985 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
2986 break;
6a157f7d 2987 case HEM_TYPE_SCCC:
0e40dc2f
YL		 2988 case HEM_TYPE_QPC_TIMER:
2989 case HEM_TYPE_CQC_TIMER:
6a157f7d 2990 break;
a81fba28
WHX		 2991 case HEM_TYPE_SRQC:
2992 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
2993 break;
2994 default:
2995 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
2996 table->type);
2997 return 0;
2998 }
6a157f7d 2999
0e40dc2f
YL		 3000 if (table->type == HEM_TYPE_SCCC ||
3001 table->type == HEM_TYPE_QPC_TIMER ||
3002 table->type == HEM_TYPE_CQC_TIMER)
6a157f7d
YL		 3003 return 0;
3004
a81fba28
WHX		 3005 op += step_idx;
3006
3007 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3008 if (IS_ERR(mailbox))
3009 return PTR_ERR(mailbox);
3010
3011 /* configure the tag and op */
3012 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3013 HNS_ROCE_CMD_TIMEOUT_MSECS);
3014
3015 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3016 return ret;
3017}
3018
926a01dc
WHX		 3019static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
3020 struct hns_roce_mtt *mtt,
3021 enum ib_qp_state cur_state,
3022 enum ib_qp_state new_state,
3023 struct hns_roce_v2_qp_context *context,
3024 struct hns_roce_qp *hr_qp)
3025{
3026 struct hns_roce_cmd_mailbox *mailbox;
3027 int ret;
3028
3029 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3030 if (IS_ERR(mailbox))
3031 return PTR_ERR(mailbox);
3032
3033 memcpy(mailbox->buf, context, sizeof(*context) * 2);
3034
3035 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
3036 HNS_ROCE_CMD_MODIFY_QPC,
3037 HNS_ROCE_CMD_TIMEOUT_MSECS);
3038
3039 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3040
3041 return ret;
3042}
3043
ace1c541 3044static void set_access_flags(struct hns_roce_qp *hr_qp,
3045 struct hns_roce_v2_qp_context *context,
3046 struct hns_roce_v2_qp_context *qpc_mask,
3047 const struct ib_qp_attr *attr, int attr_mask)
3048{
3049 u8 dest_rd_atomic;
3050 u32 access_flags;
3051
c2799119 3052 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 3053 attr->max_dest_rd_atomic : hr_qp->resp_depth;
3054
c2799119 3055 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 3056 attr->qp_access_flags : hr_qp->atomic_rd_en;
3057
3058 if (!dest_rd_atomic)
3059 access_flags &= IB_ACCESS_REMOTE_WRITE;
3060
3061 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3062 !!(access_flags & IB_ACCESS_REMOTE_READ));
3063 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
3064
3065 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3066 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3067 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
3068
3069 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3070 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3071 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
3072}
3073
926a01dc
WHX		 3074static void modify_qp_reset_to_init(struct ib_qp *ibqp,
3075 const struct ib_qp_attr *attr,
0fa95a9a 3076 int attr_mask,
926a01dc
WHX		 3077 struct hns_roce_v2_qp_context *context,
3078 struct hns_roce_v2_qp_context *qpc_mask)
3079{
ecaaf1e2 3080 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 3081 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3082
3083 /*
3084 * In v2 engine, software pass context and context mask to hardware
3085 * when modifying qp. If software need modify some fields in context,
3086 * we should set all bits of the relevant fields in context mask to
3087 * 0 at the same time, else set them to 0x1.
3088 */
3089 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3090 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3091 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3092 V2_QPC_BYTE_4_TST_S, 0);
3093
0fa95a9a 3094 if (ibqp->qp_type == IB_QPT_GSI)
3095 roce_set_field(context->byte_4_sqpn_tst,
3096 V2_QPC_BYTE_4_SGE_SHIFT_M,
3097 V2_QPC_BYTE_4_SGE_SHIFT_S,
3098 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3099 else
3100 roce_set_field(context->byte_4_sqpn_tst,
3101 V2_QPC_BYTE_4_SGE_SHIFT_M,
3102 V2_QPC_BYTE_4_SGE_SHIFT_S,
3103 hr_qp->sq.max_gs > 2 ?
3104 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3105
926a01dc
WHX		 3106 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
3107 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
3108
3109 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3110 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3111 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3112 V2_QPC_BYTE_4_SQPN_S, 0);
3113
3114 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3115 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3116 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3117 V2_QPC_BYTE_16_PD_S, 0);
3118
3119 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3120 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
3121 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3122 V2_QPC_BYTE_20_RQWS_S, 0);
3123
3124 roce_set_field(context->byte_20_smac_sgid_idx,
3125 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3126 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
3127 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3128 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
3129
3130 roce_set_field(context->byte_20_smac_sgid_idx,
3131 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
c7bcb134
LO		 3132 (hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3133 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT || ibqp->srq) ? 0 :
926a01dc
WHX		 3134 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
3135 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3136 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
3137
3138 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 3139 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3140 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
3141 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3142 V2_QPC_BYTE_24_VLAN_ID_S, 0);
926a01dc
WHX		 3143
3144 /*
3145 * Set some fields in context to zero, Because the default values
3146 * of all fields in context are zero, we need not set them to 0 again.
3147 * but we should set the relevant fields of context mask to 0.
3148 */
3149 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
3150 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
3151 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
3152 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
3153
2362ccee
LO		 3154 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_TEMPID_M,
3155 V2_QPC_BYTE_60_TEMPID_S, 0);
3156
3157 roce_set_field(qpc_mask->byte_60_qpst_tempid,
3158 V2_QPC_BYTE_60_SCC_TOKEN_M, V2_QPC_BYTE_60_SCC_TOKEN_S,
3159 0);
3160 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
3161 V2_QPC_BYTE_60_SQ_DB_DOING_S, 0);
3162 roce_set_bit(qpc_mask->byte_60_qpst_tempid,
3163 V2_QPC_BYTE_60_RQ_DB_DOING_S, 0);
926a01dc
WHX		 3164 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
3165 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
3166
0fa95a9a 3167 if (attr_mask & IB_QP_QKEY) {
3168 context->qkey_xrcd = attr->qkey;
3169 qpc_mask->qkey_xrcd = 0;
3170 hr_qp->qkey = attr->qkey;
3171 }
3172
e088a685
YL		 3173 if (hr_qp->rdb_en) {
3174 roce_set_bit(context->byte_68_rq_db,
3175 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
3176 roce_set_bit(qpc_mask->byte_68_rq_db,
3177 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 0);
3178 }
3179
3180 roce_set_field(context->byte_68_rq_db,
3181 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3182 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
3183 ((u32)hr_qp->rdb.dma) >> 1);
3184 roce_set_field(qpc_mask->byte_68_rq_db,
3185 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3186 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S, 0);
3187 context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
3188 qpc_mask->rq_db_record_addr = 0;
3189
ecaaf1e2 3190 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
3191 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 3192 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
3193
3194 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3195 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3196 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3197 V2_QPC_BYTE_80_RX_CQN_S, 0);
3198 if (ibqp->srq) {
3199 roce_set_field(context->byte_76_srqn_op_en,
3200 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3201 to_hr_srq(ibqp->srq)->srqn);
3202 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3203 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3204 roce_set_bit(context->byte_76_srqn_op_en,
3205 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3206 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3207 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3208 }
3209
3210 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3211 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3212 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3213 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3214 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3215 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3216
3217 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
3218 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
3219
3220 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3221 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3222
3223 roce_set_field(qpc_mask->byte_104_rq_sge,
3224 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
3225 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
3226
3227 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3228 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3229 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3230 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3231 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3232 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3233 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
3234
3235 qpc_mask->rq_rnr_timer = 0;
3236 qpc_mask->rx_msg_len = 0;
3237 qpc_mask->rx_rkey_pkt_info = 0;
3238 qpc_mask->rx_va = 0;
3239
3240 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3241 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3242 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3243 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3244
2362ccee
LO		 3245 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S,
3246 0);
926a01dc
WHX		 3247 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
3248 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
3249 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
3250 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
3251
3252 roce_set_field(qpc_mask->byte_144_raq,
3253 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
3254 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
926a01dc
WHX		 3255 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
3256 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
3257 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
3258
3259 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
3260 V2_QPC_BYTE_148_RQ_MSN_S, 0);
3261 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
3262 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
3263
3264 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3265 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3266 roce_set_field(qpc_mask->byte_152_raq,
3267 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
3268 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
3269
3270 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
3271 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
3272
3273 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3274 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
3275 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
3276 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
3277 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
3278 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
3279
2362ccee
LO		 3280 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3281 V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S, 0);
3282 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3283 V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S, 0);
3284 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3285 V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S, 0);
926a01dc
WHX		 3286 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3287 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 3288 roce_set_bit(qpc_mask->byte_168_irrl_idx,
3289 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 3290 roce_set_field(qpc_mask->byte_168_irrl_idx,
3291 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
3292 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
3293
3294 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3295 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
3296 roce_set_field(qpc_mask->byte_172_sq_psn,
3297 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3298 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
3299
3300 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
3301 0);
3302
68a997c5
YL		 3303 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
3304 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 0);
3305
926a01dc
WHX		 3306 roce_set_field(qpc_mask->byte_176_msg_pktn,
3307 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
3308 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
3309 roce_set_field(qpc_mask->byte_176_msg_pktn,
3310 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
3311 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
3312
3313 roce_set_field(qpc_mask->byte_184_irrl_idx,
3314 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
3315 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
3316
3317 qpc_mask->cur_sge_offset = 0;
3318
3319 roce_set_field(qpc_mask->byte_192_ext_sge,
3320 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
3321 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
3322 roce_set_field(qpc_mask->byte_192_ext_sge,
3323 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
3324 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
3325
3326 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3327 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3328
3329 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
3330 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
3331 roce_set_field(qpc_mask->byte_200_sq_max,
3332 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
3333 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
3334
3335 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
3336 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
3337
3338 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3339 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3340
3341 qpc_mask->sq_timer = 0;
3342
3343 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3344 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3345 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3346 roce_set_field(qpc_mask->byte_232_irrl_sge,
3347 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3348 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3349
2362ccee
LO		 3350 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_SO_LP_VLD_S,
3351 0);
3352 roce_set_bit(qpc_mask->byte_232_irrl_sge,
3353 V2_QPC_BYTE_232_FENCE_LP_VLD_S, 0);
3354 roce_set_bit(qpc_mask->byte_232_irrl_sge, V2_QPC_BYTE_232_IRRL_LP_VLD_S,
3355 0);
3356
926a01dc
WHX		 3357 qpc_mask->irrl_cur_sge_offset = 0;
3358
3359 roce_set_field(qpc_mask->byte_240_irrl_tail,
3360 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3361 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3362 roce_set_field(qpc_mask->byte_240_irrl_tail,
3363 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
3364 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
3365 roce_set_field(qpc_mask->byte_240_irrl_tail,
3366 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3367 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3368
3369 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
3370 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3371 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
3372 0);
3373 roce_set_field(qpc_mask->byte_248_ack_psn,
3374 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3375 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3376 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
3377 0);
3378 roce_set_bit(qpc_mask->byte_248_ack_psn,
3379 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3380 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
3381 0);
3382
3383 hr_qp->access_flags = attr->qp_access_flags;
3384 hr_qp->pkey_index = attr->pkey_index;
3385 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3386 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
3387 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3388 V2_QPC_BYTE_252_TX_CQN_S, 0);
3389
3390 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
3391 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
3392
3393 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3394 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
3395 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
3396 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
3397 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
3398 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
3399}
3400
3401static void modify_qp_init_to_init(struct ib_qp *ibqp,
3402 const struct ib_qp_attr *attr, int attr_mask,
3403 struct hns_roce_v2_qp_context *context,
3404 struct hns_roce_v2_qp_context *qpc_mask)
3405{
3406 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3407
3408 /*
3409 * In v2 engine, software pass context and context mask to hardware
3410 * when modifying qp. If software need modify some fields in context,
3411 * we should set all bits of the relevant fields in context mask to
3412 * 0 at the same time, else set them to 0x1.
3413 */
3414 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3415 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3416 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3417 V2_QPC_BYTE_4_TST_S, 0);
3418
0fa95a9a 3419 if (ibqp->qp_type == IB_QPT_GSI)
3420 roce_set_field(context->byte_4_sqpn_tst,
3421 V2_QPC_BYTE_4_SGE_SHIFT_M,
3422 V2_QPC_BYTE_4_SGE_SHIFT_S,
3423 ilog2((unsigned int)hr_qp->sge.sge_cnt));
3424 else
3425 roce_set_field(context->byte_4_sqpn_tst,
3426 V2_QPC_BYTE_4_SGE_SHIFT_M,
3427 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
3428 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
3429
926a01dc
WHX		 3430 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
3431 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
3432
3433 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3434 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3435 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3436 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3437 0);
3438
3439 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3440 !!(attr->qp_access_flags &
3441 IB_ACCESS_REMOTE_WRITE));
3442 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3443 0);
3444
3445 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3446 !!(attr->qp_access_flags &
3447 IB_ACCESS_REMOTE_ATOMIC));
3448 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3449 0);
3450 } else {
3451 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3452 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3453 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3454 0);
3455
3456 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3457 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3458 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3459 0);
3460
3461 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3462 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3463 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3464 0);
3465 }
3466
3467 roce_set_field(context->byte_20_smac_sgid_idx,
3468 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
3469 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
3470 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3471 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
3472
3473 roce_set_field(context->byte_20_smac_sgid_idx,
3474 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
c7bcb134
LO		 3475 (hr_qp->ibqp.qp_type == IB_QPT_XRC_INI ||
3476 hr_qp->ibqp.qp_type == IB_QPT_XRC_TGT || ibqp->srq) ? 0 :
926a01dc
WHX		 3477 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
3478 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3479 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
3480
3481 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3482 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3483 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3484 V2_QPC_BYTE_16_PD_S, 0);
3485
3486 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3487 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3488 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3489 V2_QPC_BYTE_80_RX_CQN_S, 0);
3490
3491 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3492 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3493 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3494 V2_QPC_BYTE_252_TX_CQN_S, 0);
3495
3496 if (ibqp->srq) {
3497 roce_set_bit(context->byte_76_srqn_op_en,
3498 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3499 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3500 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3501 roce_set_field(context->byte_76_srqn_op_en,
3502 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3503 to_hr_srq(ibqp->srq)->srqn);
3504 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3505 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3506 }
3507
0fa95a9a 3508 if (attr_mask & IB_QP_QKEY) {
3509 context->qkey_xrcd = attr->qkey;
3510 qpc_mask->qkey_xrcd = 0;
3511 }
926a01dc
WHX		 3512
3513 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3514 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3515 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3516 V2_QPC_BYTE_4_SQPN_S, 0);
3517
b6dd9b34 3518 if (attr_mask & IB_QP_DEST_QPN) {
3519 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3520 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3521 roce_set_field(qpc_mask->byte_56_dqpn_err,
3522 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3523 }
926a01dc
WHX		 3524}
3525
3526static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3527 const struct ib_qp_attr *attr, int attr_mask,
3528 struct hns_roce_v2_qp_context *context,
3529 struct hns_roce_v2_qp_context *qpc_mask)
3530{
3531 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3532 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3533 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3534 struct device *dev = hr_dev->dev;
e92f2c18 3535 dma_addr_t dma_handle_3;
926a01dc
WHX		 3536 dma_addr_t dma_handle_2;
3537 dma_addr_t dma_handle;
3538 u32 page_size;
3539 u8 port_num;
e92f2c18 3540 u64 *mtts_3;
926a01dc
WHX		 3541 u64 *mtts_2;
3542 u64 *mtts;
3543 u8 *dmac;
3544 u8 *smac;
3545 int port;
3546
3547 /* Search qp buf's mtts */
3548 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3549 hr_qp->mtt.first_seg, &dma_handle);
3550 if (!mtts) {
3551 dev_err(dev, "qp buf pa find failed\n");
3552 return -EINVAL;
3553 }
3554
3555 /* Search IRRL's mtts */
3556 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3557 hr_qp->qpn, &dma_handle_2);
3558 if (!mtts_2) {
3559 dev_err(dev, "qp irrl_table find failed\n");
3560 return -EINVAL;
3561 }
3562
e92f2c18 3563 /* Search TRRL's mtts */
3564 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
3565 hr_qp->qpn, &dma_handle_3);
3566 if (!mtts_3) {
3567 dev_err(dev, "qp trrl_table find failed\n");
3568 return -EINVAL;
3569 }
3570
734f3863 3571 if (attr_mask & IB_QP_ALT_PATH) {
926a01dc
WHX		 3572 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
3573 return -EINVAL;
3574 }
3575
3576 dmac = (u8 *)attr->ah_attr.roce.dmac;
3577 context->wqe_sge_ba = (u32)(dma_handle >> 3);
3578 qpc_mask->wqe_sge_ba = 0;
3579
3580 /*
3581 * In v2 engine, software pass context and context mask to hardware
3582 * when modifying qp. If software need modify some fields in context,
3583 * we should set all bits of the relevant fields in context mask to
3584 * 0 at the same time, else set them to 0x1.
3585 */
3586 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3587 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
3588 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3589 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3590
3591 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3592 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
3593 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3594 0 : hr_dev->caps.mtt_hop_num);
3595 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3596 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3597
3598 roce_set_field(context->byte_20_smac_sgid_idx,
3599 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3600 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
0fa95a9a 3601 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
3602 hr_dev->caps.mtt_hop_num : 0);
926a01dc
WHX		 3603 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3604 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3605 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3606
3607 roce_set_field(context->byte_20_smac_sgid_idx,
3608 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3609 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
3610 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
3611 0 : hr_dev->caps.mtt_hop_num);
3612 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3613 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3614 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3615
3616 roce_set_field(context->byte_16_buf_ba_pg_sz,
3617 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3618 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
5e6e78db 3619 hr_dev->caps.mtt_ba_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3620 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3621 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3622 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3623
3624 roce_set_field(context->byte_16_buf_ba_pg_sz,
3625 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3626 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
5e6e78db 3627 hr_dev->caps.mtt_buf_pg_sz + PG_SHIFT_OFFSET);
926a01dc
WHX		 3628 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3629 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3630 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3631
3632 roce_set_field(context->byte_80_rnr_rx_cqn,
3633 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3634 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
3635 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
3636 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3637 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
3638
3639 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
3640 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
3641 >> PAGE_ADDR_SHIFT);
3642 qpc_mask->rq_cur_blk_addr = 0;
3643
3644 roce_set_field(context->byte_92_srq_info,
3645 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3646 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
3647 mtts[hr_qp->rq.offset / page_size]
3648 >> (32 + PAGE_ADDR_SHIFT));
3649 roce_set_field(qpc_mask->byte_92_srq_info,
3650 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3651 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3652
3653 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
3654 >> PAGE_ADDR_SHIFT);
3655 qpc_mask->rq_nxt_blk_addr = 0;
3656
3657 roce_set_field(context->byte_104_rq_sge,
3658 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3659 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
3660 mtts[hr_qp->rq.offset / page_size + 1]
3661 >> (32 + PAGE_ADDR_SHIFT));
3662 roce_set_field(qpc_mask->byte_104_rq_sge,
3663 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3664 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3665
3666 roce_set_field(context->byte_108_rx_reqepsn,
3667 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3668 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
3669 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3670 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
3671 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
3672
e92f2c18 3673 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3674 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
3675 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
3676 V2_QPC_BYTE_132_TRRL_BA_S, 0);
3677 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
3678 qpc_mask->trrl_ba = 0;
3679 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3680 V2_QPC_BYTE_140_TRRL_BA_S,
3681 (u32)(dma_handle_3 >> (32 + 16 + 4)));
3682 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
3683 V2_QPC_BYTE_140_TRRL_BA_S, 0);
3684
d5514246 3685 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 3686 qpc_mask->irrl_ba = 0;
3687 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3688 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 3689 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 3690 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
3691 V2_QPC_BYTE_208_IRRL_BA_S, 0);
3692
3693 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
3694 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
3695
3696 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3697 hr_qp->sq_signal_bits);
3698 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
3699 0);
3700
3701 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
3702
3703 smac = (u8 *)hr_dev->dev_addr[port];
3704 /* when dmac equals smac or loop_idc is 1, it should loopback */
3705 if (ether_addr_equal_unaligned(dmac, smac) ||
3706 hr_dev->loop_idc == 0x1) {
3707 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
3708 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
3709 }
3710
4f3f7a70 3711 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
3712 attr->max_dest_rd_atomic) {
3713 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3714 V2_QPC_BYTE_140_RR_MAX_S,
3715 fls(attr->max_dest_rd_atomic - 1));
3716 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
3717 V2_QPC_BYTE_140_RR_MAX_S, 0);
3718 }
926a01dc 3719
b6dd9b34 3720 if (attr_mask & IB_QP_DEST_QPN) {
3721 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3722 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
3723 roce_set_field(qpc_mask->byte_56_dqpn_err,
3724 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3725 }
926a01dc
WHX		 3726
3727 /* Configure GID index */
3728 port_num = rdma_ah_get_port_num(&attr->ah_attr);
3729 roce_set_field(context->byte_20_smac_sgid_idx,
3730 V2_QPC_BYTE_20_SGID_IDX_M,
3731 V2_QPC_BYTE_20_SGID_IDX_S,
3732 hns_get_gid_index(hr_dev, port_num - 1,
3733 grh->sgid_index));
3734 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3735 V2_QPC_BYTE_20_SGID_IDX_M,
3736 V2_QPC_BYTE_20_SGID_IDX_S, 0);
3737 memcpy(&(context->dmac), dmac, 4);
3738 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3739 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
3740 qpc_mask->dmac = 0;
3741 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
3742 V2_QPC_BYTE_52_DMAC_S, 0);
3743
3744 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3745 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
3746 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
3747 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
3748
0fa95a9a 3749 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3750 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3751 V2_QPC_BYTE_24_MTU_S, IB_MTU_4096);
6852af86 3752 else if (attr_mask & IB_QP_PATH_MTU)
0fa95a9a 3753 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3754 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
3755
926a01dc
WHX		 3756 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
3757 V2_QPC_BYTE_24_MTU_S, 0);
3758
926a01dc
WHX		 3759 roce_set_field(context->byte_84_rq_ci_pi,
3760 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3761 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3762 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3763 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3764 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3765
3766 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3767 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3768 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3769 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
3770 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
3771 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
3772 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
3773 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
3774 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
3775 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
3776
3777 context->rq_rnr_timer = 0;
3778 qpc_mask->rq_rnr_timer = 0;
3779
3780 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3781 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
3782 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
3783 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
3784
3785 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
3786 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
3787 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
3788 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
3789
3790 roce_set_field(context->byte_168_irrl_idx,
3791 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3792 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
3793 roce_set_field(qpc_mask->byte_168_irrl_idx,
3794 V2_QPC_BYTE_168_LP_SGEN_INI_M,
3795 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
3796
926a01dc
WHX		 3797 return 0;
3798}
3799
3800static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
3801 const struct ib_qp_attr *attr, int attr_mask,
3802 struct hns_roce_v2_qp_context *context,
3803 struct hns_roce_v2_qp_context *qpc_mask)
3804{
3805 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3806 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3807 struct device *dev = hr_dev->dev;
3808 dma_addr_t dma_handle;
befb63b4 3809 u32 page_size;
926a01dc
WHX		 3810 u64 *mtts;
3811
3812 /* Search qp buf's mtts */
3813 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
3814 hr_qp->mtt.first_seg, &dma_handle);
3815 if (!mtts) {
3816 dev_err(dev, "qp buf pa find failed\n");
3817 return -EINVAL;
3818 }
3819
734f3863 3820 /* Not support alternate path and path migration */
3821 if ((attr_mask & IB_QP_ALT_PATH) ||
3822 (attr_mask & IB_QP_PATH_MIG_STATE)) {
926a01dc
WHX		 3823 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
3824 return -EINVAL;
3825 }
3826
3827 /*
3828 * In v2 engine, software pass context and context mask to hardware
3829 * when modifying qp. If software need modify some fields in context,
3830 * we should set all bits of the relevant fields in context mask to
3831 * 0 at the same time, else set them to 0x1.
3832 */
926a01dc
WHX		 3833 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3834 roce_set_field(context->byte_168_irrl_idx,
3835 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3836 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3837 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3838 qpc_mask->sq_cur_blk_addr = 0;
3839 roce_set_field(qpc_mask->byte_168_irrl_idx,
3840 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3841 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3842
befb63b4 3843 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
0fa95a9a 3844 context->sq_cur_sge_blk_addr =
3845 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3846 ((u32)(mtts[hr_qp->sge.offset / page_size]
3847 >> PAGE_ADDR_SHIFT)) : 0;
3848 roce_set_field(context->byte_184_irrl_idx,
3849 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3850 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
0fa95a9a 3851 ((ibqp->qp_type == IB_QPT_GSI) || hr_qp->sq.max_gs > 2) ?
befb63b4 3852 (mtts[hr_qp->sge.offset / page_size] >>
3853 (32 + PAGE_ADDR_SHIFT)) : 0);
3854 qpc_mask->sq_cur_sge_blk_addr = 0;
3855 roce_set_field(qpc_mask->byte_184_irrl_idx,
3856 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3857 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3858
926a01dc
WHX		 3859 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
3860 roce_set_field(context->byte_232_irrl_sge,
3861 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3862 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3863 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
3864 qpc_mask->rx_sq_cur_blk_addr = 0;
3865 roce_set_field(qpc_mask->byte_232_irrl_sge,
3866 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3867 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3868
3869 /*
3870 * Set some fields in context to zero, Because the default values
3871 * of all fields in context are zero, we need not set them to 0 again.
3872 * but we should set the relevant fields of context mask to 0.
3873 */
3874 roce_set_field(qpc_mask->byte_232_irrl_sge,
3875 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
3876 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
3877
3878 roce_set_field(qpc_mask->byte_240_irrl_tail,
3879 V2_QPC_BYTE_240_RX_ACK_MSN_M,
3880 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
3881
3882 roce_set_field(context->byte_244_rnr_rxack,
3883 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3884 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
3885 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3886 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
3887 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
3888
3889 roce_set_field(qpc_mask->byte_248_ack_psn,
3890 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
3891 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
3892 roce_set_bit(qpc_mask->byte_248_ack_psn,
3893 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
3894 roce_set_field(qpc_mask->byte_248_ack_psn,
3895 V2_QPC_BYTE_248_IRRL_PSN_M,
3896 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
3897
3898 roce_set_field(qpc_mask->byte_240_irrl_tail,
3899 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
3900 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
3901
3902 roce_set_field(context->byte_220_retry_psn_msn,
3903 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3904 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
3905 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3906 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
3907 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
3908
3909 roce_set_field(context->byte_224_retry_msg,
3910 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3911 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
3912 roce_set_field(qpc_mask->byte_224_retry_msg,
3913 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
3914 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
3915
3916 roce_set_field(context->byte_224_retry_msg,
3917 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3918 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
3919 roce_set_field(qpc_mask->byte_224_retry_msg,
3920 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
3921 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
3922
3923 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
3924 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
3925 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
3926
3927 roce_set_bit(qpc_mask->byte_248_ack_psn,
3928 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
3929
3930 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
3931 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
3932
3933 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3934 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
3935 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
3936 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
3937
3938 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3939 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
3940 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
3941 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
3942
3943 roce_set_field(context->byte_244_rnr_rxack,
3944 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3945 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
3946 roce_set_field(qpc_mask->byte_244_rnr_rxack,
3947 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
3948 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
3949
3950 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3951 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
3952 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
3953 V2_QPC_BYTE_244_RNR_CNT_S, 0);
3954
3955 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3956 V2_QPC_BYTE_212_LSN_S, 0x100);
3957 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
3958 V2_QPC_BYTE_212_LSN_S, 0);
3959
28726461 3960 if (attr_mask & IB_QP_TIMEOUT) {
44754b95
LO		 3961 if (attr->timeout < 31) {
3962 roce_set_field(context->byte_28_at_fl,
3963 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
3964 attr->timeout);
3965 roce_set_field(qpc_mask->byte_28_at_fl,
3966 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
3967 0);
3968 } else {
3969 dev_warn(dev, "Local ACK timeout shall be 0 to 30.\n");
3970 }
28726461 3971 }
926a01dc 3972
926a01dc
WHX		 3973 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3974 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
3975 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
3976 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
3977
3978 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
3979 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
3980 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3981 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
3982 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
3983 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
3984
4f3f7a70 3985 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
3986 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
3987 V2_QPC_BYTE_208_SR_MAX_S,
3988 fls(attr->max_rd_atomic - 1));
3989 roce_set_field(qpc_mask->byte_208_irrl,
3990 V2_QPC_BYTE_208_SR_MAX_M,
3991 V2_QPC_BYTE_208_SR_MAX_S, 0);
3992 }
926a01dc
WHX		 3993 return 0;
3994}
3995
233673e4
LO		 3996static inline bool hns_roce_v2_check_qp_stat(enum ib_qp_state cur_state,
3997 enum ib_qp_state new_state)
3998{
3999
4000 if ((cur_state != IB_QPS_RESET &&
4001 (new_state == IB_QPS_ERR || new_state == IB_QPS_RESET)) ||
4002 ((cur_state == IB_QPS_RTS || cur_state == IB_QPS_SQD) &&
4003 (new_state == IB_QPS_RTS || new_state == IB_QPS_SQD)) ||
4004 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS))
4005 return true;
4006
4007 return false;
4008
4009}
4010
926a01dc
WHX		 4011static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
4012 const struct ib_qp_attr *attr,
4013 int attr_mask, enum ib_qp_state cur_state,
4014 enum ib_qp_state new_state)
4015{
4016 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4017 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4018 struct hns_roce_v2_qp_context *context;
4019 struct hns_roce_v2_qp_context *qpc_mask;
4020 struct device *dev = hr_dev->dev;
4021 int ret = -EINVAL;
4022
6396bb22 4023 context = kcalloc(2, sizeof(*context), GFP_KERNEL);
926a01dc
WHX		 4024 if (!context)
4025 return -ENOMEM;
4026
4027 qpc_mask = context + 1;
4028 /*
4029 * In v2 engine, software pass context and context mask to hardware
4030 * when modifying qp. If software need modify some fields in context,
4031 * we should set all bits of the relevant fields in context mask to
4032 * 0 at the same time, else set them to 0x1.
4033 */
4034 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
4035 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
9f507101 4036 memset(qpc_mask, 0, sizeof(*qpc_mask));
0fa95a9a 4037 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
4038 qpc_mask);
926a01dc
WHX		 4039 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4040 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
4041 qpc_mask);
4042 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4043 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4044 qpc_mask);
4045 if (ret)
4046 goto out;
4047 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4048 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
4049 qpc_mask);
4050 if (ret)
4051 goto out;
233673e4 4052 } else if (hns_roce_v2_check_qp_stat(cur_state, new_state)) {
926a01dc
WHX		 4053 /* Nothing */
4054 ;
4055 } else {
4056 dev_err(dev, "Illegal state for QP!\n");
ac7cbf96 4057 ret = -EINVAL;
926a01dc
WHX		 4058 goto out;
4059 }
4060
0425e3e6
YL		 4061 /* When QP state is err, SQ and RQ WQE should be flushed */
4062 if (new_state == IB_QPS_ERR) {
4063 roce_set_field(context->byte_160_sq_ci_pi,
4064 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4065 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
4066 hr_qp->sq.head);
4067 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
4068 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4069 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
9c6ccc03
LO		 4070
4071 if (!ibqp->srq) {
4072 roce_set_field(context->byte_84_rq_ci_pi,
0425e3e6
YL		 4073 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4074 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
4075 hr_qp->rq.head);
9c6ccc03 4076 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
0425e3e6
YL		 4077 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4078 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
9c6ccc03 4079 }
0425e3e6
YL		 4080 }
4081
610b8967
LO		 4082 if (attr_mask & IB_QP_AV) {
4083 const struct ib_global_route *grh =
4084 rdma_ah_read_grh(&attr->ah_attr);
4085 const struct ib_gid_attr *gid_attr = NULL;
4086 u8 src_mac[ETH_ALEN];
4087 int is_roce_protocol;
4088 u16 vlan = 0xffff;
4089 u8 ib_port;
4090 u8 hr_port;
4091
4092 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num :
4093 hr_qp->port + 1;
4094 hr_port = ib_port - 1;
4095 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4096 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4097
4098 if (is_roce_protocol) {
4099 gid_attr = attr->ah_attr.grh.sgid_attr;
4100 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
4101 memcpy(src_mac, gid_attr->ndev->dev_addr, ETH_ALEN);
4102 }
4103
caf3e406
LO		 4104 if (is_vlan_dev(gid_attr->ndev)) {
4105 roce_set_bit(context->byte_76_srqn_op_en,
4106 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
4107 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
4108 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
4109 roce_set_bit(context->byte_168_irrl_idx,
4110 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
4111 roce_set_bit(qpc_mask->byte_168_irrl_idx,
4112 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
4113 }
4114
c8e46f8d
LO		 4115 roce_set_field(context->byte_24_mtu_tc,
4116 V2_QPC_BYTE_24_VLAN_ID_M,
4117 V2_QPC_BYTE_24_VLAN_ID_S, vlan);
4118 roce_set_field(qpc_mask->byte_24_mtu_tc,
4119 V2_QPC_BYTE_24_VLAN_ID_M,
4120 V2_QPC_BYTE_24_VLAN_ID_S, 0);
4121
610b8967
LO		 4122 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
4123 dev_err(hr_dev->dev,
4124 "sgid_index(%u) too large. max is %d\n",
4125 grh->sgid_index,
4126 hr_dev->caps.gid_table_len[hr_port]);
4127 ret = -EINVAL;
4128 goto out;
4129 }
4130
4131 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
4132 dev_err(hr_dev->dev, "ah attr is not RDMA roce type\n");
4133 ret = -EINVAL;
4134 goto out;
4135 }
4136
4137 roce_set_field(context->byte_52_udpspn_dmac,
4138 V2_QPC_BYTE_52_UDPSPN_M, V2_QPC_BYTE_52_UDPSPN_S,
4139 (gid_attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) ?
4140 0 : 0x12b7);
4141
4142 roce_set_field(qpc_mask->byte_52_udpspn_dmac,
4143 V2_QPC_BYTE_52_UDPSPN_M,
4144 V2_QPC_BYTE_52_UDPSPN_S, 0);
4145
4146 roce_set_field(context->byte_20_smac_sgid_idx,
4147 V2_QPC_BYTE_20_SGID_IDX_M,
4148 V2_QPC_BYTE_20_SGID_IDX_S, grh->sgid_index);
4149
4150 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4151 V2_QPC_BYTE_20_SGID_IDX_M,
4152 V2_QPC_BYTE_20_SGID_IDX_S, 0);
4153
4154 roce_set_field(context->byte_24_mtu_tc,
4155 V2_QPC_BYTE_24_HOP_LIMIT_M,
4156 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
4157 roce_set_field(qpc_mask->byte_24_mtu_tc,
4158 V2_QPC_BYTE_24_HOP_LIMIT_M,
4159 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
4160
157b52a0
LO		 4161 if (hr_dev->pci_dev->revision == 0x21 &&
4162 gid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
4163 roce_set_field(context->byte_24_mtu_tc,
4164 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
4165 grh->traffic_class >> 2);
4166 else
4167 roce_set_field(context->byte_24_mtu_tc,
4168 V2_QPC_BYTE_24_TC_M, V2_QPC_BYTE_24_TC_S,
4169 grh->traffic_class);
610b8967
LO		 4170 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4171 V2_QPC_BYTE_24_TC_S, 0);
4172 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4173 V2_QPC_BYTE_28_FL_S, grh->flow_label);
4174 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4175 V2_QPC_BYTE_28_FL_S, 0);
4176 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4177 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4178 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4179 V2_QPC_BYTE_28_SL_S,
4180 rdma_ah_get_sl(&attr->ah_attr));
4181 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4182 V2_QPC_BYTE_28_SL_S, 0);
4183 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4184 }
4185
ace1c541 4186 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4187 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4188
c7bcb134
LO		 4189 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S,
4190 ibqp->srq ? 1 : 0);
4191 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4192 V2_QPC_BYTE_108_INV_CREDIT_S, 0);
4193
926a01dc 4194 /* Every status migrate must change state */
2362ccee 4195 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 4196 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 4197 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 4198 V2_QPC_BYTE_60_QP_ST_S, 0);
4199
4200 /* SW pass context to HW */
4201 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
4202 context, hr_qp);
4203 if (ret) {
4204 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
4205 goto out;
4206 }
4207
4208 hr_qp->state = new_state;
4209
ace1c541 4210 if (attr_mask & IB_QP_ACCESS_FLAGS)
4211 hr_qp->atomic_rd_en = attr->qp_access_flags;
4212
926a01dc
WHX		 4213 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4214 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4215 if (attr_mask & IB_QP_PORT) {
4216 hr_qp->port = attr->port_num - 1;
4217 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4218 }
4219
4220 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
4221 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
4222 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
4223 if (ibqp->send_cq != ibqp->recv_cq)
4224 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4225 hr_qp->qpn, NULL);
4226
4227 hr_qp->rq.head = 0;
4228 hr_qp->rq.tail = 0;
4229 hr_qp->sq.head = 0;
4230 hr_qp->sq.tail = 0;
4231 hr_qp->sq_next_wqe = 0;
4232 hr_qp->next_sge = 0;
e088a685
YL		 4233 if (hr_qp->rq.wqe_cnt)
4234 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 4235 }
4236
4237out:
4238 kfree(context);
4239 return ret;
4240}
4241
4242static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
4243{
4244 switch (state) {
4245 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
4246 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
4247 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
4248 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
4249 case HNS_ROCE_QP_ST_SQ_DRAINING:
4250 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
4251 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
4252 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
4253 default: return -1;
4254 }
4255}
4256
4257static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
4258 struct hns_roce_qp *hr_qp,
4259 struct hns_roce_v2_qp_context *hr_context)
4260{
4261 struct hns_roce_cmd_mailbox *mailbox;
4262 int ret;
4263
4264 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4265 if (IS_ERR(mailbox))
4266 return PTR_ERR(mailbox);
4267
4268 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
4269 HNS_ROCE_CMD_QUERY_QPC,
4270 HNS_ROCE_CMD_TIMEOUT_MSECS);
4271 if (ret) {
4272 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
4273 goto out;
4274 }
4275
4276 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
4277
4278out:
4279 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4280 return ret;
4281}
4282
4283static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4284 int qp_attr_mask,
4285 struct ib_qp_init_attr *qp_init_attr)
4286{
4287 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4288 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4289 struct hns_roce_v2_qp_context *context;
4290 struct device *dev = hr_dev->dev;
4291 int tmp_qp_state;
4292 int state;
4293 int ret;
4294
4295 context = kzalloc(sizeof(*context), GFP_KERNEL);
4296 if (!context)
4297 return -ENOMEM;
4298
4299 memset(qp_attr, 0, sizeof(*qp_attr));
4300 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4301
4302 mutex_lock(&hr_qp->mutex);
4303
4304 if (hr_qp->state == IB_QPS_RESET) {
4305 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 4306 ret = 0;
926a01dc
WHX		 4307 goto done;
4308 }
4309
4310 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
4311 if (ret) {
4312 dev_err(dev, "query qpc error\n");
4313 ret = -EINVAL;
4314 goto out;
4315 }
4316
2362ccee 4317 state = roce_get_field(context->byte_60_qpst_tempid,
926a01dc
WHX		 4318 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
4319 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
4320 if (tmp_qp_state == -1) {
4321 dev_err(dev, "Illegal ib_qp_state\n");
4322 ret = -EINVAL;
4323 goto out;
4324 }
4325 hr_qp->state = (u8)tmp_qp_state;
4326 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
4327 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
4328 V2_QPC_BYTE_24_MTU_M,
4329 V2_QPC_BYTE_24_MTU_S);
4330 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 4331 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 4332 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
4333 qp_attr->qkey = V2_QKEY_VAL;
4334
4335 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
4336 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4337 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
4338 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
4339 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4340 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
4341 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
4342 V2_QPC_BYTE_56_DQPN_M,
4343 V2_QPC_BYTE_56_DQPN_S);
4344 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
4345 V2_QPC_BYTE_76_RRE_S)) << 2) |
4346 ((roce_get_bit(context->byte_76_srqn_op_en,
4347 V2_QPC_BYTE_76_RWE_S)) << 1) |
4348 ((roce_get_bit(context->byte_76_srqn_op_en,
4349 V2_QPC_BYTE_76_ATE_S)) << 3);
4350 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
4351 hr_qp->ibqp.qp_type == IB_QPT_UC) {
4352 struct ib_global_route *grh =
4353 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
4354
4355 rdma_ah_set_sl(&qp_attr->ah_attr,
4356 roce_get_field(context->byte_28_at_fl,
4357 V2_QPC_BYTE_28_SL_M,
4358 V2_QPC_BYTE_28_SL_S));
4359 grh->flow_label = roce_get_field(context->byte_28_at_fl,
4360 V2_QPC_BYTE_28_FL_M,
4361 V2_QPC_BYTE_28_FL_S);
4362 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
4363 V2_QPC_BYTE_20_SGID_IDX_M,
4364 V2_QPC_BYTE_20_SGID_IDX_S);
4365 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
4366 V2_QPC_BYTE_24_HOP_LIMIT_M,
4367 V2_QPC_BYTE_24_HOP_LIMIT_S);
4368 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
4369 V2_QPC_BYTE_24_TC_M,
4370 V2_QPC_BYTE_24_TC_S);
4371
4372 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
4373 }
4374
4375 qp_attr->port_num = hr_qp->port + 1;
4376 qp_attr->sq_draining = 0;
4377 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
4378 V2_QPC_BYTE_208_SR_MAX_M,
4379 V2_QPC_BYTE_208_SR_MAX_S);
4380 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
4381 V2_QPC_BYTE_140_RR_MAX_M,
4382 V2_QPC_BYTE_140_RR_MAX_S);
4383 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
4384 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4385 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4386 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
4387 V2_QPC_BYTE_28_AT_M,
4388 V2_QPC_BYTE_28_AT_S);
4389 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
4390 V2_QPC_BYTE_212_RETRY_CNT_M,
4391 V2_QPC_BYTE_212_RETRY_CNT_S);
4392 qp_attr->rnr_retry = context->rq_rnr_timer;
4393
4394done:
4395 qp_attr->cur_qp_state = qp_attr->qp_state;
4396 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4397 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4398
4399 if (!ibqp->uobject) {
4400 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4401 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4402 } else {
4403 qp_attr->cap.max_send_wr = 0;
4404 qp_attr->cap.max_send_sge = 0;
4405 }
4406
4407 qp_init_attr->cap = qp_attr->cap;
4408
4409out:
4410 mutex_unlock(&hr_qp->mutex);
4411 kfree(context);
4412 return ret;
4413}
4414
4415static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4416 struct hns_roce_qp *hr_qp,
e00b64f7 4417 bool is_user)
926a01dc
WHX		 4418{
4419 struct hns_roce_cq *send_cq, *recv_cq;
4420 struct device *dev = hr_dev->dev;
4421 int ret;
4422
4423 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4424 /* Modify qp to reset before destroying qp */
4425 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4426 hr_qp->state, IB_QPS_RESET);
4427 if (ret) {
4428 dev_err(dev, "modify QP %06lx to ERR failed.\n",
4429 hr_qp->qpn);
4430 return ret;
4431 }
4432 }
4433
4434 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
4435 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
4436
4437 hns_roce_lock_cqs(send_cq, recv_cq);
4438
4439 if (!is_user) {
4440 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
4441 to_hr_srq(hr_qp->ibqp.srq) : NULL);
4442 if (send_cq != recv_cq)
4443 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
4444 }
4445
4446 hns_roce_qp_remove(hr_dev, hr_qp);
4447
4448 hns_roce_unlock_cqs(send_cq, recv_cq);
4449
4450 hns_roce_qp_free(hr_dev, hr_qp);
4451
4452 /* Not special_QP, free their QPN */
4453 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
4454 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
4455 (hr_qp->ibqp.qp_type == IB_QPT_UD))
4456 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
4457
4458 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
4459
4460 if (is_user) {
0425e3e6
YL		 4461 if (hr_qp->sq.wqe_cnt && (hr_qp->sdb_en == 1))
4462 hns_roce_db_unmap_user(
4463 to_hr_ucontext(hr_qp->ibqp.uobject->context),
4464 &hr_qp->sdb);
4465
e088a685
YL		 4466 if (hr_qp->rq.wqe_cnt && (hr_qp->rdb_en == 1))
4467 hns_roce_db_unmap_user(
4468 to_hr_ucontext(hr_qp->ibqp.uobject->context),
4469 &hr_qp->rdb);
926a01dc
WHX		 4470 ib_umem_release(hr_qp->umem);
4471 } else {
4472 kfree(hr_qp->sq.wrid);
4473 kfree(hr_qp->rq.wrid);
4474 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
472bc0fb
YL		 4475 if (hr_qp->rq.wqe_cnt)
4476 hns_roce_free_db(hr_dev, &hr_qp->rdb);
926a01dc
WHX		 4477 }
4478
c7bcb134
LO		 4479 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) &&
4480 hr_qp->rq.wqe_cnt) {
0009c2db 4481 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
4482 kfree(hr_qp->rq_inl_buf.wqe_list);
4483 }
4484
926a01dc
WHX		 4485 return 0;
4486}
4487
4488static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
4489{
4490 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4491 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4492 int ret;
4493
e00b64f7 4494 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, ibqp->uobject);
926a01dc
WHX		 4495 if (ret) {
4496 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
4497 return ret;
4498 }
4499
4500 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
4501 kfree(hr_to_hr_sqp(hr_qp));
4502 else
4503 kfree(hr_qp);
4504
4505 return 0;
4506}
4507
aa84fa18
YL		 4508static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
4509 struct hns_roce_qp *hr_qp)
4510{
da91ddfd 4511 struct hns_roce_sccc_clr_done *resp;
aa84fa18
YL		 4512 struct hns_roce_sccc_clr *clr;
4513 struct hns_roce_cmq_desc desc;
4514 int ret, i;
4515
4516 mutex_lock(&hr_dev->qp_table.scc_mutex);
4517
4518 /* set scc ctx clear done flag */
4519 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
aa84fa18
YL		 4520 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4521 if (ret) {
4522 dev_err(hr_dev->dev, "Reset SCC ctx failed(%d)\n", ret);
4523 goto out;
4524 }
4525
4526 /* clear scc context */
4527 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
4528 clr = (struct hns_roce_sccc_clr *)desc.data;
4529 clr->qpn = cpu_to_le32(hr_qp->qpn);
4530 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4531 if (ret) {
4532 dev_err(hr_dev->dev, "Clear SCC ctx failed(%d)\n", ret);
4533 goto out;
4534 }
4535
4536 /* query scc context clear is done or not */
4537 resp = (struct hns_roce_sccc_clr_done *)desc.data;
4538 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
4539 hns_roce_cmq_setup_basic_desc(&desc,
4540 HNS_ROCE_OPC_QUERY_SCCC, true);
4541 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4542 if (ret) {
4543 dev_err(hr_dev->dev, "Query clr cmq failed(%d)\n", ret);
4544 goto out;
4545 }
4546
4547 if (resp->clr_done)
4548 goto out;
4549
4550 msleep(20);
4551 }
4552
4553 dev_err(hr_dev->dev, "Query SCC clr done flag overtime.\n");
4554 ret = -ETIMEDOUT;
4555
4556out:
4557 mutex_unlock(&hr_dev->qp_table.scc_mutex);
4558 return ret;
4559}
4560
b156269d 4561static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
4562{
4563 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
4564 struct hns_roce_v2_cq_context *cq_context;
4565 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
4566 struct hns_roce_v2_cq_context *cqc_mask;
4567 struct hns_roce_cmd_mailbox *mailbox;
4568 int ret;
4569
4570 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4571 if (IS_ERR(mailbox))
4572 return PTR_ERR(mailbox);
4573
4574 cq_context = mailbox->buf;
4575 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
4576
4577 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
4578
4579 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4580 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4581 cq_count);
4582 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4583 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
4584 0);
4585 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
4586 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4587 cq_period);
4588 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
4589 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
4590 0);
4591
4592 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
4593 HNS_ROCE_CMD_MODIFY_CQC,
4594 HNS_ROCE_CMD_TIMEOUT_MSECS);
4595 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4596 if (ret)
4597 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
4598
4599 return ret;
4600}
4601
0425e3e6
YL		 4602static void hns_roce_set_qps_to_err(struct hns_roce_dev *hr_dev, u32 qpn)
4603{
4604 struct hns_roce_qp *hr_qp;
4605 struct ib_qp_attr attr;
4606 int attr_mask;
4607 int ret;
4608
4609 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
4610 if (!hr_qp) {
4611 dev_warn(hr_dev->dev, "no hr_qp can be found!\n");
4612 return;
4613 }
4614
4615 if (hr_qp->ibqp.uobject) {
4616 if (hr_qp->sdb_en == 1) {
4617 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
9c6ccc03
LO		 4618 if (hr_qp->rdb_en == 1)
4619 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
0425e3e6
YL		 4620 } else {
4621 dev_warn(hr_dev->dev, "flush cqe is unsupported in userspace!\n");
4622 return;
4623 }
4624 }
4625
4626 attr_mask = IB_QP_STATE;
4627 attr.qp_state = IB_QPS_ERR;
4628 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, &attr, attr_mask,
4629 hr_qp->state, IB_QPS_ERR);
4630 if (ret)
4631 dev_err(hr_dev->dev, "failed to modify qp %d to err state.\n",
4632 qpn);
4633}
4634
4635static void hns_roce_irq_work_handle(struct work_struct *work)
4636{
4637 struct hns_roce_work *irq_work =
4638 container_of(work, struct hns_roce_work, work);
b00a92c8 4639 struct device *dev = irq_work->hr_dev->dev;
0425e3e6 4640 u32 qpn = irq_work->qpn;
b00a92c8 4641 u32 cqn = irq_work->cqn;
0425e3e6
YL		 4642
4643 switch (irq_work->event_type) {
b00a92c8 4644 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4645 dev_info(dev, "Path migrated succeeded.\n");
4646 break;
4647 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4648 dev_warn(dev, "Path migration failed.\n");
4649 break;
4650 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4651 dev_info(dev, "Communication established.\n");
4652 break;
4653 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4654 dev_warn(dev, "Send queue drained.\n");
4655 break;
0425e3e6 4656 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
b00a92c8 4657 dev_err(dev, "Local work queue catastrophic error.\n");
4658 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4659 switch (irq_work->sub_type) {
4660 case HNS_ROCE_LWQCE_QPC_ERROR:
4661 dev_err(dev, "QP %d, QPC error.\n", qpn);
4662 break;
4663 case HNS_ROCE_LWQCE_MTU_ERROR:
4664 dev_err(dev, "QP %d, MTU error.\n", qpn);
4665 break;
4666 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4667 dev_err(dev, "QP %d, WQE BA addr error.\n", qpn);
4668 break;
4669 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4670 dev_err(dev, "QP %d, WQE addr error.\n", qpn);
4671 break;
4672 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4673 dev_err(dev, "QP %d, WQE shift error.\n", qpn);
4674 break;
4675 default:
4676 dev_err(dev, "Unhandled sub_event type %d.\n",
4677 irq_work->sub_type);
4678 break;
4679 }
4680 break;
0425e3e6 4681 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
b00a92c8 4682 dev_err(dev, "Invalid request local work queue error.\n");
4683 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
4684 break;
0425e3e6 4685 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4686 dev_err(dev, "Local access violation work queue error.\n");
0425e3e6 4687 hns_roce_set_qps_to_err(irq_work->hr_dev, qpn);
b00a92c8 4688 switch (irq_work->sub_type) {
4689 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4690 dev_err(dev, "QP %d, R_key violation.\n", qpn);
4691 break;
4692 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4693 dev_err(dev, "QP %d, length error.\n", qpn);
4694 break;
4695 case HNS_ROCE_LAVWQE_VA_ERROR:
4696 dev_err(dev, "QP %d, VA error.\n", qpn);
4697 break;
4698 case HNS_ROCE_LAVWQE_PD_ERROR:
4699 dev_err(dev, "QP %d, PD error.\n", qpn);
4700 break;
4701 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4702 dev_err(dev, "QP %d, rw acc error.\n", qpn);
4703 break;
4704 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4705 dev_err(dev, "QP %d, key state error.\n", qpn);
4706 break;
4707 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4708 dev_err(dev, "QP %d, MR operation error.\n", qpn);
4709 break;
4710 default:
4711 dev_err(dev, "Unhandled sub_event type %d.\n",
4712 irq_work->sub_type);
4713 break;
4714 }
4715 break;
4716 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4717 dev_warn(dev, "SRQ limit reach.\n");
4718 break;
4719 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4720 dev_warn(dev, "SRQ last wqe reach.\n");
4721 break;
4722 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4723 dev_err(dev, "SRQ catas error.\n");
4724 break;
4725 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4726 dev_err(dev, "CQ 0x%x access err.\n", cqn);
4727 break;
4728 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4729 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4730 break;
4731 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4732 dev_warn(dev, "DB overflow.\n");
4733 break;
4734 case HNS_ROCE_EVENT_TYPE_FLR:
4735 dev_warn(dev, "Function level reset.\n");
0425e3e6
YL		 4736 break;
4737 default:
4738 break;
4739 }
4740
4741 kfree(irq_work);
4742}
4743
4744static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 4745 struct hns_roce_eq *eq,
4746 u32 qpn, u32 cqn)
0425e3e6
YL		 4747{
4748 struct hns_roce_work *irq_work;
4749
4750 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
4751 if (!irq_work)
4752 return;
4753
4754 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
4755 irq_work->hr_dev = hr_dev;
4756 irq_work->qpn = qpn;
b00a92c8 4757 irq_work->cqn = cqn;
0425e3e6
YL		 4758 irq_work->event_type = eq->event_type;
4759 irq_work->sub_type = eq->sub_type;
4760 queue_work(hr_dev->irq_workq, &(irq_work->work));
4761}
4762
a5073d60
YL		 4763static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
4764{
d3743fa9 4765 struct hns_roce_dev *hr_dev = eq->hr_dev;
a5073d60
YL		 4766 u32 doorbell[2];
4767
4768 doorbell[0] = 0;
4769 doorbell[1] = 0;
4770
4771 if (eq->type_flag == HNS_ROCE_AEQ) {
4772 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4773 HNS_ROCE_V2_EQ_DB_CMD_S,
4774 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4775 HNS_ROCE_EQ_DB_CMD_AEQ :
4776 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
4777 } else {
4778 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
4779 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
4780
4781 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
4782 HNS_ROCE_V2_EQ_DB_CMD_S,
4783 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
4784 HNS_ROCE_EQ_DB_CMD_CEQ :
4785 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
4786 }
4787
4788 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
4789 HNS_ROCE_V2_EQ_DB_PARA_S,
4790 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
4791
d3743fa9 4792 hns_roce_write64(hr_dev, doorbell, eq->doorbell);
a5073d60
YL		 4793}
4794
a5073d60
YL		 4795static struct hns_roce_aeqe *get_aeqe_v2(struct hns_roce_eq *eq, u32 entry)
4796{
4797 u32 buf_chk_sz;
4798 unsigned long off;
4799
4800 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4801 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4802
4803 return (struct hns_roce_aeqe *)((char *)(eq->buf_list->buf) +
4804 off % buf_chk_sz);
4805}
4806
4807static struct hns_roce_aeqe *mhop_get_aeqe(struct hns_roce_eq *eq, u32 entry)
4808{
4809 u32 buf_chk_sz;
4810 unsigned long off;
4811
4812 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4813
4814 off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQ_ENTRY_SIZE;
4815
4816 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4817 return (struct hns_roce_aeqe *)((u8 *)(eq->bt_l0) +
4818 off % buf_chk_sz);
4819 else
4820 return (struct hns_roce_aeqe *)((u8 *)
4821 (eq->buf[off / buf_chk_sz]) + off % buf_chk_sz);
4822}
4823
4824static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
4825{
4826 struct hns_roce_aeqe *aeqe;
4827
4828 if (!eq->hop_num)
4829 aeqe = get_aeqe_v2(eq, eq->cons_index);
4830 else
4831 aeqe = mhop_get_aeqe(eq, eq->cons_index);
4832
4833 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
4834 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4835}
4836
4837static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
4838 struct hns_roce_eq *eq)
4839{
4840 struct device *dev = hr_dev->dev;
4841 struct hns_roce_aeqe *aeqe;
4842 int aeqe_found = 0;
4843 int event_type;
0425e3e6 4844 int sub_type;
81fce629 4845 u32 srqn;
0425e3e6
YL		 4846 u32 qpn;
4847 u32 cqn;
a5073d60
YL		 4848
4849 while ((aeqe = next_aeqe_sw_v2(eq))) {
4044a3f4
YL		 4850
4851 /* Make sure we read AEQ entry after we have checked the
4852 * ownership bit
4853 */
4854 dma_rmb();
a5073d60
YL		 4855
4856 event_type = roce_get_field(aeqe->asyn,
4857 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
4858 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 4859 sub_type = roce_get_field(aeqe->asyn,
4860 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
4861 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
4862 qpn = roce_get_field(aeqe->event.qp_event.qp,
4863 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4864 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
4865 cqn = roce_get_field(aeqe->event.cq_event.cq,
4866 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4867 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
81fce629
LO		 4868 srqn = roce_get_field(aeqe->event.srq_event.srq,
4869 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
4870 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 4871
4872 switch (event_type) {
4873 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 4874 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 4875 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4876 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4877 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
81fce629 4878 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
a5073d60
YL		 4879 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4880 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 4881 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 4882 break;
4883 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
a5073d60 4884 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
81fce629 4885 hns_roce_srq_event(hr_dev, srqn, event_type);
a5073d60
YL		 4886 break;
4887 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4888 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 4889 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 4890 break;
4891 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 4892 break;
4893 case HNS_ROCE_EVENT_TYPE_MB:
4894 hns_roce_cmd_event(hr_dev,
4895 le16_to_cpu(aeqe->event.cmd.token),
4896 aeqe->event.cmd.status,
4897 le64_to_cpu(aeqe->event.cmd.out_param));
4898 break;
4899 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 4900 break;
4901 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 4902 break;
4903 default:
4904 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4905 event_type, eq->eqn, eq->cons_index);
4906 break;
790b57f6 4907 }
a5073d60 4908
0425e3e6
YL		 4909 eq->event_type = event_type;
4910 eq->sub_type = sub_type;
a5073d60
YL		 4911 ++eq->cons_index;
4912 aeqe_found = 1;
4913
4914 if (eq->cons_index > (2 * eq->entries - 1)) {
4915 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4916 eq->cons_index = 0;
4917 }
b00a92c8 4918 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
a5073d60
YL		 4919 }
4920
4921 set_eq_cons_index_v2(eq);
4922 return aeqe_found;
4923}
4924
4925static struct hns_roce_ceqe *get_ceqe_v2(struct hns_roce_eq *eq, u32 entry)
4926{
4927 u32 buf_chk_sz;
4928 unsigned long off;
4929
4930 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4931 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4932
4933 return (struct hns_roce_ceqe *)((char *)(eq->buf_list->buf) +
4934 off % buf_chk_sz);
4935}
4936
4937static struct hns_roce_ceqe *mhop_get_ceqe(struct hns_roce_eq *eq, u32 entry)
4938{
4939 u32 buf_chk_sz;
4940 unsigned long off;
4941
4942 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
4943
4944 off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQ_ENTRY_SIZE;
4945
4946 if (eq->hop_num == HNS_ROCE_HOP_NUM_0)
4947 return (struct hns_roce_ceqe *)((u8 *)(eq->bt_l0) +
4948 off % buf_chk_sz);
4949 else
4950 return (struct hns_roce_ceqe *)((u8 *)(eq->buf[off /
4951 buf_chk_sz]) + off % buf_chk_sz);
4952}
4953
4954static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
4955{
4956 struct hns_roce_ceqe *ceqe;
4957
4958 if (!eq->hop_num)
4959 ceqe = get_ceqe_v2(eq, eq->cons_index);
4960 else
4961 ceqe = mhop_get_ceqe(eq, eq->cons_index);
4962
4963 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
4964 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4965}
4966
4967static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
4968 struct hns_roce_eq *eq)
4969{
4970 struct device *dev = hr_dev->dev;
4971 struct hns_roce_ceqe *ceqe;
4972 int ceqe_found = 0;
4973 u32 cqn;
4974
4975 while ((ceqe = next_ceqe_sw_v2(eq))) {
4976
4044a3f4
YL		 4977 /* Make sure we read CEQ entry after we have checked the
4978 * ownership bit
4979 */
4980 dma_rmb();
4981
a5073d60
YL		 4982 cqn = roce_get_field(ceqe->comp,
4983 HNS_ROCE_V2_CEQE_COMP_CQN_M,
4984 HNS_ROCE_V2_CEQE_COMP_CQN_S);
4985
4986 hns_roce_cq_completion(hr_dev, cqn);
4987
4988 ++eq->cons_index;
4989 ceqe_found = 1;
4990
4991 if (eq->cons_index > (2 * eq->entries - 1)) {
4992 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4993 eq->cons_index = 0;
4994 }
4995 }
4996
4997 set_eq_cons_index_v2(eq);
4998
4999 return ceqe_found;
5000}
5001
5002static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
5003{
5004 struct hns_roce_eq *eq = eq_ptr;
5005 struct hns_roce_dev *hr_dev = eq->hr_dev;
5006 int int_work = 0;
5007
5008 if (eq->type_flag == HNS_ROCE_CEQ)
5009 /* Completion event interrupt */
5010 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
5011 else
5012 /* Asychronous event interrupt */
5013 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5014
5015 return IRQ_RETVAL(int_work);
5016}
5017
5018static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5019{
5020 struct hns_roce_dev *hr_dev = dev_id;
5021 struct device *dev = hr_dev->dev;
5022 int int_work = 0;
5023 u32 int_st;
5024 u32 int_en;
5025
5026 /* Abnormal interrupt */
5027 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5028 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5029
5030 if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
2b9acb9a
XT		 5031 struct pci_dev *pdev = hr_dev->pci_dev;
5032 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5033 const struct hnae3_ae_ops *ops = ae_dev->ops;
5034
a5073d60
YL		 5035 dev_err(dev, "AEQ overflow!\n");
5036
5037 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S, 1);
5038 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5039
2b9acb9a
XT		 5040 /* Set reset level for reset_event() */
5041 if (ops->set_default_reset_request)
5042 ops->set_default_reset_request(ae_dev,
5043 HNAE3_FUNC_RESET);
5044 if (ops->reset_event)
5045 ops->reset_event(pdev, NULL);
5046
a5073d60
YL		 5047 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
5048 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5049
5050 int_work = 1;
5051 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
5052 dev_err(dev, "BUS ERR!\n");
5053
5054 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S, 1);
5055 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5056
a5073d60
YL		 5057 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
5058 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5059
5060 int_work = 1;
5061 } else if (roce_get_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
5062 dev_err(dev, "OTHER ERR!\n");
5063
5064 roce_set_bit(int_st, HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S, 1);
5065 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5066
a5073d60
YL		 5067 roce_set_bit(int_en, HNS_ROCE_V2_VF_ABN_INT_EN_S, 1);
5068 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5069
5070 int_work = 1;
5071 } else
5072 dev_err(dev, "There is no abnormal irq found!\n");
5073
5074 return IRQ_RETVAL(int_work);
5075}
5076
5077static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5078 int eq_num, int enable_flag)
5079{
5080 int i;
5081
5082 if (enable_flag == EQ_ENABLE) {
5083 for (i = 0; i < eq_num; i++)
5084 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5085 i * EQ_REG_OFFSET,
5086 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
5087
5088 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5089 HNS_ROCE_V2_VF_ABN_INT_EN_M);
5090 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5091 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
5092 } else {
5093 for (i = 0; i < eq_num; i++)
5094 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5095 i * EQ_REG_OFFSET,
5096 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
5097
5098 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5099 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
5100 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5101 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
5102 }
5103}
5104
5105static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5106{
5107 struct device *dev = hr_dev->dev;
5108 int ret;
5109
5110 if (eqn < hr_dev->caps.num_comp_vectors)
5111 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5112 0, HNS_ROCE_CMD_DESTROY_CEQC,
5113 HNS_ROCE_CMD_TIMEOUT_MSECS);
5114 else
5115 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5116 0, HNS_ROCE_CMD_DESTROY_AEQC,
5117 HNS_ROCE_CMD_TIMEOUT_MSECS);
5118 if (ret)
5119 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5120}
5121
5122static void hns_roce_mhop_free_eq(struct hns_roce_dev *hr_dev,
5123 struct hns_roce_eq *eq)
5124{
5125 struct device *dev = hr_dev->dev;
5126 u64 idx;
5127 u64 size;
5128 u32 buf_chk_sz;
5129 u32 bt_chk_sz;
5130 u32 mhop_num;
5131 int eqe_alloc;
a5073d60
YL		 5132 int i = 0;
5133 int j = 0;
5134
5135 mhop_num = hr_dev->caps.eqe_hop_num;
5136 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5137 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
a5073d60
YL		 5138
5139 /* hop_num = 0 */
5140 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
5141 dma_free_coherent(dev, (unsigned int)(eq->entries *
5142 eq->eqe_size), eq->bt_l0, eq->l0_dma);
5143 return;
5144 }
5145
5146 /* hop_num = 1 or hop = 2 */
5147 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5148 if (mhop_num == 1) {
5149 for (i = 0; i < eq->l0_last_num; i++) {
5150 if (i == eq->l0_last_num - 1) {
5151 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
5152 size = (eq->entries - eqe_alloc) * eq->eqe_size;
5153 dma_free_coherent(dev, size, eq->buf[i],
5154 eq->buf_dma[i]);
5155 break;
5156 }
5157 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
5158 eq->buf_dma[i]);
5159 }
5160 } else if (mhop_num == 2) {
5161 for (i = 0; i < eq->l0_last_num; i++) {
5162 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5163 eq->l1_dma[i]);
5164
5165 for (j = 0; j < bt_chk_sz / 8; j++) {
5166 idx = i * (bt_chk_sz / 8) + j;
5167 if ((i == eq->l0_last_num - 1)
5168 && j == eq->l1_last_num - 1) {
5169 eqe_alloc = (buf_chk_sz / eq->eqe_size)
5170 * idx;
5171 size = (eq->entries - eqe_alloc)
5172 * eq->eqe_size;
5173 dma_free_coherent(dev, size,
5174 eq->buf[idx],
5175 eq->buf_dma[idx]);
5176 break;
5177 }
5178 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
5179 eq->buf_dma[idx]);
5180 }
5181 }
5182 }
5183 kfree(eq->buf_dma);
5184 kfree(eq->buf);
5185 kfree(eq->l1_dma);
5186 kfree(eq->bt_l1);
5187 eq->buf_dma = NULL;
5188 eq->buf = NULL;
5189 eq->l1_dma = NULL;
5190 eq->bt_l1 = NULL;
5191}
5192
5193static void hns_roce_v2_free_eq(struct hns_roce_dev *hr_dev,
5194 struct hns_roce_eq *eq)
5195{
5196 u32 buf_chk_sz;
5197
5198 buf_chk_sz = 1 << (eq->eqe_buf_pg_sz + PAGE_SHIFT);
5199
5200 if (hr_dev->caps.eqe_hop_num) {
5201 hns_roce_mhop_free_eq(hr_dev, eq);
5202 return;
5203 }
5204
5205 if (eq->buf_list)
5206 dma_free_coherent(hr_dev->dev, buf_chk_sz,
5207 eq->buf_list->buf, eq->buf_list->map);
5208}
5209
5210static void hns_roce_config_eqc(struct hns_roce_dev *hr_dev,
5211 struct hns_roce_eq *eq,
5212 void *mb_buf)
5213{
5214 struct hns_roce_eq_context *eqc;
5215
5216 eqc = mb_buf;
5217 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5218
5219 /* init eqc */
5220 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
5221 eq->hop_num = hr_dev->caps.eqe_hop_num;
5222 eq->cons_index = 0;
5223 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5224 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5225 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
5226 eq->eqe_ba_pg_sz = hr_dev->caps.eqe_ba_pg_sz;
5227 eq->eqe_buf_pg_sz = hr_dev->caps.eqe_buf_pg_sz;
5228 eq->shift = ilog2((unsigned int)eq->entries);
5229
5230 if (!eq->hop_num)
5231 eq->eqe_ba = eq->buf_list->map;
5232 else
5233 eq->eqe_ba = eq->l0_dma;
5234
5235 /* set eqc state */
5236 roce_set_field(eqc->byte_4,
5237 HNS_ROCE_EQC_EQ_ST_M,
5238 HNS_ROCE_EQC_EQ_ST_S,
5239 HNS_ROCE_V2_EQ_STATE_VALID);
5240
5241 /* set eqe hop num */
5242 roce_set_field(eqc->byte_4,
5243 HNS_ROCE_EQC_HOP_NUM_M,
5244 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
5245
5246 /* set eqc over_ignore */
5247 roce_set_field(eqc->byte_4,
5248 HNS_ROCE_EQC_OVER_IGNORE_M,
5249 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
5250
5251 /* set eqc coalesce */
5252 roce_set_field(eqc->byte_4,
5253 HNS_ROCE_EQC_COALESCE_M,
5254 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
5255
5256 /* set eqc arm_state */
5257 roce_set_field(eqc->byte_4,
5258 HNS_ROCE_EQC_ARM_ST_M,
5259 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
5260
5261 /* set eqn */
5262 roce_set_field(eqc->byte_4,
5263 HNS_ROCE_EQC_EQN_M,
5264 HNS_ROCE_EQC_EQN_S, eq->eqn);
5265
5266 /* set eqe_cnt */
5267 roce_set_field(eqc->byte_4,
5268 HNS_ROCE_EQC_EQE_CNT_M,
5269 HNS_ROCE_EQC_EQE_CNT_S,
5270 HNS_ROCE_EQ_INIT_EQE_CNT);
5271
5272 /* set eqe_ba_pg_sz */
5273 roce_set_field(eqc->byte_8,
5274 HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db
YL		 5275 HNS_ROCE_EQC_BA_PG_SZ_S,
5276 eq->eqe_ba_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 5277
5278 /* set eqe_buf_pg_sz */
5279 roce_set_field(eqc->byte_8,
5280 HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db
YL		 5281 HNS_ROCE_EQC_BUF_PG_SZ_S,
5282 eq->eqe_buf_pg_sz + PG_SHIFT_OFFSET);
a5073d60
YL		 5283
5284 /* set eq_producer_idx */
5285 roce_set_field(eqc->byte_8,
5286 HNS_ROCE_EQC_PROD_INDX_M,
5287 HNS_ROCE_EQC_PROD_INDX_S,
5288 HNS_ROCE_EQ_INIT_PROD_IDX);
5289
5290 /* set eq_max_cnt */
5291 roce_set_field(eqc->byte_12,
5292 HNS_ROCE_EQC_MAX_CNT_M,
5293 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
5294
5295 /* set eq_period */
5296 roce_set_field(eqc->byte_12,
5297 HNS_ROCE_EQC_PERIOD_M,
5298 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
5299
5300 /* set eqe_report_timer */
5301 roce_set_field(eqc->eqe_report_timer,
5302 HNS_ROCE_EQC_REPORT_TIMER_M,
5303 HNS_ROCE_EQC_REPORT_TIMER_S,
5304 HNS_ROCE_EQ_INIT_REPORT_TIMER);
5305
5306 /* set eqe_ba [34:3] */
5307 roce_set_field(eqc->eqe_ba0,
5308 HNS_ROCE_EQC_EQE_BA_L_M,
5309 HNS_ROCE_EQC_EQE_BA_L_S, eq->eqe_ba >> 3);
5310
5311 /* set eqe_ba [64:35] */
5312 roce_set_field(eqc->eqe_ba1,
5313 HNS_ROCE_EQC_EQE_BA_H_M,
5314 HNS_ROCE_EQC_EQE_BA_H_S, eq->eqe_ba >> 35);
5315
5316 /* set eq shift */
5317 roce_set_field(eqc->byte_28,
5318 HNS_ROCE_EQC_SHIFT_M,
5319 HNS_ROCE_EQC_SHIFT_S, eq->shift);
5320
5321 /* set eq MSI_IDX */
5322 roce_set_field(eqc->byte_28,
5323 HNS_ROCE_EQC_MSI_INDX_M,
5324 HNS_ROCE_EQC_MSI_INDX_S,
5325 HNS_ROCE_EQ_INIT_MSI_IDX);
5326
5327 /* set cur_eqe_ba [27:12] */
5328 roce_set_field(eqc->byte_28,
5329 HNS_ROCE_EQC_CUR_EQE_BA_L_M,
5330 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eq->cur_eqe_ba >> 12);
5331
5332 /* set cur_eqe_ba [59:28] */
5333 roce_set_field(eqc->byte_32,
5334 HNS_ROCE_EQC_CUR_EQE_BA_M_M,
5335 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eq->cur_eqe_ba >> 28);
5336
5337 /* set cur_eqe_ba [63:60] */
5338 roce_set_field(eqc->byte_36,
5339 HNS_ROCE_EQC_CUR_EQE_BA_H_M,
5340 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eq->cur_eqe_ba >> 60);
5341
5342 /* set eq consumer idx */
5343 roce_set_field(eqc->byte_36,
5344 HNS_ROCE_EQC_CONS_INDX_M,
5345 HNS_ROCE_EQC_CONS_INDX_S,
5346 HNS_ROCE_EQ_INIT_CONS_IDX);
5347
5348 /* set nex_eqe_ba[43:12] */
5349 roce_set_field(eqc->nxt_eqe_ba0,
5350 HNS_ROCE_EQC_NXT_EQE_BA_L_M,
5351 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eq->nxt_eqe_ba >> 12);
5352
5353 /* set nex_eqe_ba[63:44] */
5354 roce_set_field(eqc->nxt_eqe_ba1,
5355 HNS_ROCE_EQC_NXT_EQE_BA_H_M,
5356 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eq->nxt_eqe_ba >> 44);
5357}
5358
5359static int hns_roce_mhop_alloc_eq(struct hns_roce_dev *hr_dev,
5360 struct hns_roce_eq *eq)
5361{
5362 struct device *dev = hr_dev->dev;
5363 int eq_alloc_done = 0;
5364 int eq_buf_cnt = 0;
5365 int eqe_alloc;
5366 u32 buf_chk_sz;
5367 u32 bt_chk_sz;
5368 u32 mhop_num;
5369 u64 size;
5370 u64 idx;
5371 int ba_num;
5372 int bt_num;
5373 int record_i;
5374 int record_j;
5375 int i = 0;
5376 int j = 0;
5377
5378 mhop_num = hr_dev->caps.eqe_hop_num;
5379 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5380 bt_chk_sz = 1 << (hr_dev->caps.eqe_ba_pg_sz + PAGE_SHIFT);
5381
5382 ba_num = (PAGE_ALIGN(eq->entries * eq->eqe_size) + buf_chk_sz - 1)
5383 / buf_chk_sz;
5384 bt_num = (ba_num + bt_chk_sz / 8 - 1) / (bt_chk_sz / 8);
5385
5386 /* hop_num = 0 */
5387 if (mhop_num == HNS_ROCE_HOP_NUM_0) {
5388 if (eq->entries > buf_chk_sz / eq->eqe_size) {
5389 dev_err(dev, "eq entries %d is larger than buf_pg_sz!",
5390 eq->entries);
5391 return -EINVAL;
5392 }
5393 eq->bt_l0 = dma_alloc_coherent(dev, eq->entries * eq->eqe_size,
5394 &(eq->l0_dma), GFP_KERNEL);
5395 if (!eq->bt_l0)
5396 return -ENOMEM;
5397
5398 eq->cur_eqe_ba = eq->l0_dma;
5399 eq->nxt_eqe_ba = 0;
5400
5401 memset(eq->bt_l0, 0, eq->entries * eq->eqe_size);
5402
5403 return 0;
5404 }
5405
5406 eq->buf_dma = kcalloc(ba_num, sizeof(*eq->buf_dma), GFP_KERNEL);
5407 if (!eq->buf_dma)
5408 return -ENOMEM;
5409 eq->buf = kcalloc(ba_num, sizeof(*eq->buf), GFP_KERNEL);
5410 if (!eq->buf)
5411 goto err_kcalloc_buf;
5412
5413 if (mhop_num == 2) {
5414 eq->l1_dma = kcalloc(bt_num, sizeof(*eq->l1_dma), GFP_KERNEL);
5415 if (!eq->l1_dma)
5416 goto err_kcalloc_l1_dma;
5417
5418 eq->bt_l1 = kcalloc(bt_num, sizeof(*eq->bt_l1), GFP_KERNEL);
5419 if (!eq->bt_l1)
5420 goto err_kcalloc_bt_l1;
5421 }
5422
5423 /* alloc L0 BT */
5424 eq->bt_l0 = dma_alloc_coherent(dev, bt_chk_sz, &eq->l0_dma, GFP_KERNEL);
5425 if (!eq->bt_l0)
5426 goto err_dma_alloc_l0;
5427
5428 if (mhop_num == 1) {
5429 if (ba_num > (bt_chk_sz / 8))
5430 dev_err(dev, "ba_num %d is too large for 1 hop\n",
5431 ba_num);
5432
5433 /* alloc buf */
5434 for (i = 0; i < bt_chk_sz / 8; i++) {
5435 if (eq_buf_cnt + 1 < ba_num) {
5436 size = buf_chk_sz;
5437 } else {
5438 eqe_alloc = i * (buf_chk_sz / eq->eqe_size);
5439 size = (eq->entries - eqe_alloc) * eq->eqe_size;
5440 }
750afb08 5441 eq->buf[i] = dma_alloc_coherent(dev, size,
a5073d60
YL		 5442 &(eq->buf_dma[i]),
5443 GFP_KERNEL);
5444 if (!eq->buf[i])
5445 goto err_dma_alloc_buf;
5446
a5073d60
YL		 5447 *(eq->bt_l0 + i) = eq->buf_dma[i];
5448
5449 eq_buf_cnt++;
5450 if (eq_buf_cnt >= ba_num)
5451 break;
5452 }
5453 eq->cur_eqe_ba = eq->buf_dma[0];
5454 eq->nxt_eqe_ba = eq->buf_dma[1];
5455
5456 } else if (mhop_num == 2) {
5457 /* alloc L1 BT and buf */
5458 for (i = 0; i < bt_chk_sz / 8; i++) {
5459 eq->bt_l1[i] = dma_alloc_coherent(dev, bt_chk_sz,
5460 &(eq->l1_dma[i]),
5461 GFP_KERNEL);
5462 if (!eq->bt_l1[i])
5463 goto err_dma_alloc_l1;
5464 *(eq->bt_l0 + i) = eq->l1_dma[i];
5465
5466 for (j = 0; j < bt_chk_sz / 8; j++) {
5467 idx = i * bt_chk_sz / 8 + j;
5468 if (eq_buf_cnt + 1 < ba_num) {
5469 size = buf_chk_sz;
5470 } else {
5471 eqe_alloc = (buf_chk_sz / eq->eqe_size)
5472 * idx;
5473 size = (eq->entries - eqe_alloc)
5474 * eq->eqe_size;
5475 }
750afb08
LC		 5476 eq->buf[idx] = dma_alloc_coherent(dev, size,
5477 &(eq->buf_dma[idx]),
5478 GFP_KERNEL);
a5073d60
YL		 5479 if (!eq->buf[idx])
5480 goto err_dma_alloc_buf;
5481
a5073d60
YL		 5482 *(eq->bt_l1[i] + j) = eq->buf_dma[idx];
5483
5484 eq_buf_cnt++;
5485 if (eq_buf_cnt >= ba_num) {
5486 eq_alloc_done = 1;
5487 break;
5488 }
5489 }
5490
5491 if (eq_alloc_done)
5492 break;
5493 }
5494 eq->cur_eqe_ba = eq->buf_dma[0];
5495 eq->nxt_eqe_ba = eq->buf_dma[1];
5496 }
5497
5498 eq->l0_last_num = i + 1;
5499 if (mhop_num == 2)
5500 eq->l1_last_num = j + 1;
5501
5502 return 0;
5503
5504err_dma_alloc_l1:
5505 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5506 eq->bt_l0 = NULL;
5507 eq->l0_dma = 0;
5508 for (i -= 1; i >= 0; i--) {
5509 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5510 eq->l1_dma[i]);
5511
5512 for (j = 0; j < bt_chk_sz / 8; j++) {
5513 idx = i * bt_chk_sz / 8 + j;
5514 dma_free_coherent(dev, buf_chk_sz, eq->buf[idx],
5515 eq->buf_dma[idx]);
5516 }
5517 }
5518 goto err_dma_alloc_l0;
5519
5520err_dma_alloc_buf:
5521 dma_free_coherent(dev, bt_chk_sz, eq->bt_l0, eq->l0_dma);
5522 eq->bt_l0 = NULL;
5523 eq->l0_dma = 0;
5524
5525 if (mhop_num == 1)
38759d61 5526 for (i -= 1; i >= 0; i--)
a5073d60
YL		 5527 dma_free_coherent(dev, buf_chk_sz, eq->buf[i],
5528 eq->buf_dma[i]);
5529 else if (mhop_num == 2) {
5530 record_i = i;
5531 record_j = j;
5532 for (; i >= 0; i--) {
5533 dma_free_coherent(dev, bt_chk_sz, eq->bt_l1[i],
5534 eq->l1_dma[i]);
5535
5536 for (j = 0; j < bt_chk_sz / 8; j++) {
5537 if (i == record_i && j >= record_j)
5538 break;
5539
5540 idx = i * bt_chk_sz / 8 + j;
5541 dma_free_coherent(dev, buf_chk_sz,
5542 eq->buf[idx],
5543 eq->buf_dma[idx]);
5544 }
5545 }
5546 }
5547
5548err_dma_alloc_l0:
5549 kfree(eq->bt_l1);
5550 eq->bt_l1 = NULL;
5551
5552err_kcalloc_bt_l1:
5553 kfree(eq->l1_dma);
5554 eq->l1_dma = NULL;
5555
5556err_kcalloc_l1_dma:
5557 kfree(eq->buf);
5558 eq->buf = NULL;
5559
5560err_kcalloc_buf:
5561 kfree(eq->buf_dma);
5562 eq->buf_dma = NULL;
5563
5564 return -ENOMEM;
5565}
5566
5567static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5568 struct hns_roce_eq *eq,
5569 unsigned int eq_cmd)
5570{
5571 struct device *dev = hr_dev->dev;
5572 struct hns_roce_cmd_mailbox *mailbox;
5573 u32 buf_chk_sz = 0;
5574 int ret;
5575
5576 /* Allocate mailbox memory */
5577 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5578 if (IS_ERR(mailbox))
5579 return PTR_ERR(mailbox);
5580
5581 if (!hr_dev->caps.eqe_hop_num) {
5582 buf_chk_sz = 1 << (hr_dev->caps.eqe_buf_pg_sz + PAGE_SHIFT);
5583
5584 eq->buf_list = kzalloc(sizeof(struct hns_roce_buf_list),
5585 GFP_KERNEL);
5586 if (!eq->buf_list) {
5587 ret = -ENOMEM;
5588 goto free_cmd_mbox;
5589 }
5590
750afb08 5591 eq->buf_list->buf = dma_alloc_coherent(dev, buf_chk_sz,
a5073d60
YL		 5592 &(eq->buf_list->map),
5593 GFP_KERNEL);
5594 if (!eq->buf_list->buf) {
5595 ret = -ENOMEM;
5596 goto err_alloc_buf;
5597 }
5598
a5073d60
YL		 5599 } else {
5600 ret = hns_roce_mhop_alloc_eq(hr_dev, eq);
5601 if (ret) {
5602 ret = -ENOMEM;
5603 goto free_cmd_mbox;
5604 }
5605 }
5606
5607 hns_roce_config_eqc(hr_dev, eq, mailbox->buf);
5608
5609 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5610 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5611 if (ret) {
ab178849 5612 dev_err(dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5613 goto err_cmd_mbox;
5614 }
5615
5616 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5617
5618 return 0;
5619
5620err_cmd_mbox:
5621 if (!hr_dev->caps.eqe_hop_num)
5622 dma_free_coherent(dev, buf_chk_sz, eq->buf_list->buf,
5623 eq->buf_list->map);
5624 else {
5625 hns_roce_mhop_free_eq(hr_dev, eq);
5626 goto free_cmd_mbox;
5627 }
5628
5629err_alloc_buf:
5630 kfree(eq->buf_list);
5631
5632free_cmd_mbox:
5633 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5634
5635 return ret;
5636}
5637
5638static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5639{
5640 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5641 struct device *dev = hr_dev->dev;
5642 struct hns_roce_eq *eq;
5643 unsigned int eq_cmd;
5644 int irq_num;
5645 int eq_num;
5646 int other_num;
5647 int comp_num;
5648 int aeq_num;
5649 int i, j, k;
5650 int ret;
5651
5652 other_num = hr_dev->caps.num_other_vectors;
5653 comp_num = hr_dev->caps.num_comp_vectors;
5654 aeq_num = hr_dev->caps.num_aeq_vectors;
5655
5656 eq_num = comp_num + aeq_num;
5657 irq_num = eq_num + other_num;
5658
5659 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5660 if (!eq_table->eq)
5661 return -ENOMEM;
5662
5663 for (i = 0; i < irq_num; i++) {
5664 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5665 GFP_KERNEL);
5666 if (!hr_dev->irq_names[i]) {
5667 ret = -ENOMEM;
5668 goto err_failed_kzalloc;
5669 }
5670 }
5671
5672 /* create eq */
5673 for (j = 0; j < eq_num; j++) {
5674 eq = &eq_table->eq[j];
5675 eq->hr_dev = hr_dev;
5676 eq->eqn = j;
5677 if (j < comp_num) {
5678 /* CEQ */
5679 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5680 eq->type_flag = HNS_ROCE_CEQ;
5681 eq->entries = hr_dev->caps.ceqe_depth;
5682 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
5683 eq->irq = hr_dev->irq[j + other_num + aeq_num];
5684 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5685 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5686 } else {
5687 /* AEQ */
5688 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5689 eq->type_flag = HNS_ROCE_AEQ;
5690 eq->entries = hr_dev->caps.aeqe_depth;
5691 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
5692 eq->irq = hr_dev->irq[j - comp_num + other_num];
5693 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5694 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5695 }
5696
5697 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5698 if (ret) {
5699 dev_err(dev, "eq create failed.\n");
5700 goto err_create_eq_fail;
5701 }
5702 }
5703
5704 /* enable irq */
5705 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5706
5707 /* irq contains: abnormal + AEQ + CEQ*/
5708 for (k = 0; k < irq_num; k++)
5709 if (k < other_num)
5710 snprintf((char *)hr_dev->irq_names[k],
5711 HNS_ROCE_INT_NAME_LEN, "hns-abn-%d", k);
5712 else if (k < (other_num + aeq_num))
5713 snprintf((char *)hr_dev->irq_names[k],
5714 HNS_ROCE_INT_NAME_LEN, "hns-aeq-%d",
5715 k - other_num);
5716 else
5717 snprintf((char *)hr_dev->irq_names[k],
5718 HNS_ROCE_INT_NAME_LEN, "hns-ceq-%d",
5719 k - other_num - aeq_num);
5720
5721 for (k = 0; k < irq_num; k++) {
5722 if (k < other_num)
5723 ret = request_irq(hr_dev->irq[k],
5724 hns_roce_v2_msix_interrupt_abn,
5725 0, hr_dev->irq_names[k], hr_dev);
5726
5727 else if (k < (other_num + comp_num))
5728 ret = request_irq(eq_table->eq[k - other_num].irq,
5729 hns_roce_v2_msix_interrupt_eq,
5730 0, hr_dev->irq_names[k + aeq_num],
5731 &eq_table->eq[k - other_num]);
5732 else
5733 ret = request_irq(eq_table->eq[k - other_num].irq,
5734 hns_roce_v2_msix_interrupt_eq,
5735 0, hr_dev->irq_names[k - comp_num],
5736 &eq_table->eq[k - other_num]);
5737 if (ret) {
5738 dev_err(dev, "Request irq error!\n");
5739 goto err_request_irq_fail;
5740 }
5741 }
5742
0425e3e6
YL		 5743 hr_dev->irq_workq =
5744 create_singlethread_workqueue("hns_roce_irq_workqueue");
5745 if (!hr_dev->irq_workq) {
5746 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5747 ret = -ENOMEM;
0425e3e6
YL		 5748 goto err_request_irq_fail;
5749 }
5750
a5073d60
YL		 5751 return 0;
5752
5753err_request_irq_fail:
5754 for (k -= 1; k >= 0; k--)
5755 if (k < other_num)
5756 free_irq(hr_dev->irq[k], hr_dev);
5757 else
5758 free_irq(eq_table->eq[k - other_num].irq,
5759 &eq_table->eq[k - other_num]);
5760
5761err_create_eq_fail:
5762 for (j -= 1; j >= 0; j--)
5763 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[j]);
5764
5765err_failed_kzalloc:
5766 for (i -= 1; i >= 0; i--)
5767 kfree(hr_dev->irq_names[i]);
5768 kfree(eq_table->eq);
5769
5770 return ret;
5771}
5772
5773static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5774{
5775 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5776 int irq_num;
5777 int eq_num;
5778 int i;
5779
5780 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5781 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5782
5783 /* Disable irq */
5784 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5785
5786 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5787 free_irq(hr_dev->irq[i], hr_dev);
5788
5789 for (i = 0; i < eq_num; i++) {
5790 hns_roce_v2_destroy_eqc(hr_dev, i);
5791
5792 free_irq(eq_table->eq[i].irq, &eq_table->eq[i]);
5793
5794 hns_roce_v2_free_eq(hr_dev, &eq_table->eq[i]);
5795 }
5796
5797 for (i = 0; i < irq_num; i++)
5798 kfree(hr_dev->irq_names[i]);
5799
5800 kfree(eq_table->eq);
0425e3e6
YL		 5801
5802 flush_workqueue(hr_dev->irq_workq);
5803 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5804}
5805
c7bcb134
LO		 5806static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
5807 struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
5808 u32 cqn, void *mb_buf, u64 *mtts_wqe,
5809 u64 *mtts_idx, dma_addr_t dma_handle_wqe,
5810 dma_addr_t dma_handle_idx)
5811{
5812 struct hns_roce_srq_context *srq_context;
5813
5814 srq_context = mb_buf;
5815 memset(srq_context, 0, sizeof(*srq_context));
5816
5817 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M,
5818 SRQC_BYTE_4_SRQ_ST_S, 1);
5819
5820 roce_set_field(srq_context->byte_4_srqn_srqst,
5821 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M,
5822 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S,
5823 (hr_dev->caps.srqwqe_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5824 hr_dev->caps.srqwqe_hop_num));
5825 roce_set_field(srq_context->byte_4_srqn_srqst,
5826 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S,
5827 ilog2(srq->max));
5828
5829 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M,
5830 SRQC_BYTE_4_SRQN_S, srq->srqn);
5831
5832 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5833 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5834
5835 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
5836 SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
5837
5838 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));
5839
5840 roce_set_field(srq_context->byte_24_wqe_bt_ba,
5841 SRQC_BYTE_24_SRQ_WQE_BT_BA_M,
5842 SRQC_BYTE_24_SRQ_WQE_BT_BA_S,
5843 cpu_to_le32(dma_handle_wqe >> 35));
5844
5845 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
5846 SRQC_BYTE_28_PD_S, pdn);
5847 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
5848 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
5849 fls(srq->max_gs - 1));
5850
5851 srq_context->idx_bt_ba = (u32)(dma_handle_idx >> 3);
5852 srq_context->idx_bt_ba = cpu_to_le32(srq_context->idx_bt_ba);
5853 roce_set_field(srq_context->rsv_idx_bt_ba,
5854 SRQC_BYTE_36_SRQ_IDX_BT_BA_M,
5855 SRQC_BYTE_36_SRQ_IDX_BT_BA_S,
5856 cpu_to_le32(dma_handle_idx >> 35));
5857
5858 srq_context->idx_cur_blk_addr = (u32)(mtts_idx[0] >> PAGE_ADDR_SHIFT);
5859 srq_context->idx_cur_blk_addr =
5860 cpu_to_le32(srq_context->idx_cur_blk_addr);
5861 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5862 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M,
5863 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S,
5864 cpu_to_le32((mtts_idx[0]) >> (32 + PAGE_ADDR_SHIFT)));
5865 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5866 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M,
5867 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S,
5868 hr_dev->caps.idx_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
5869 hr_dev->caps.idx_hop_num);
5870
5871 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5872 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
5873 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
5874 hr_dev->caps.idx_ba_pg_sz);
5875 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
5876 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
5877 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
5878 hr_dev->caps.idx_buf_pg_sz);
5879
5880 srq_context->idx_nxt_blk_addr = (u32)(mtts_idx[1] >> PAGE_ADDR_SHIFT);
5881 srq_context->idx_nxt_blk_addr =
5882 cpu_to_le32(srq_context->idx_nxt_blk_addr);
5883 roce_set_field(srq_context->rsv_idxnxtblkaddr,
5884 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M,
5885 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S,
5886 cpu_to_le32((mtts_idx[1]) >> (32 + PAGE_ADDR_SHIFT)));
5887 roce_set_field(srq_context->byte_56_xrc_cqn,
5888 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
5889 cqn);
5890 roce_set_field(srq_context->byte_56_xrc_cqn,
5891 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
5892 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
5893 hr_dev->caps.srqwqe_ba_pg_sz + PG_SHIFT_OFFSET);
5894 roce_set_field(srq_context->byte_56_xrc_cqn,
5895 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M,
5896 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S,
5897 hr_dev->caps.srqwqe_buf_pg_sz + PG_SHIFT_OFFSET);
5898
5899 roce_set_bit(srq_context->db_record_addr_record_en,
5900 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0);
5901}
5902
5903static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5904 struct ib_srq_attr *srq_attr,
5905 enum ib_srq_attr_mask srq_attr_mask,
5906 struct ib_udata *udata)
5907{
5908 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5909 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5910 struct hns_roce_srq_context *srq_context;
5911 struct hns_roce_srq_context *srqc_mask;
5912 struct hns_roce_cmd_mailbox *mailbox;
5913 int ret;
5914
5915 if (srq_attr_mask & IB_SRQ_LIMIT) {
5916 if (srq_attr->srq_limit >= srq->max)
5917 return -EINVAL;
5918
5919 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5920 if (IS_ERR(mailbox))
5921 return PTR_ERR(mailbox);
5922
5923 srq_context = mailbox->buf;
5924 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5925
5926 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5927
5928 roce_set_field(srq_context->byte_8_limit_wl,
5929 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5930 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit);
5931 roce_set_field(srqc_mask->byte_8_limit_wl,
5932 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5933 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5934
5935 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5936 HNS_ROCE_CMD_MODIFY_SRQC,
5937 HNS_ROCE_CMD_TIMEOUT_MSECS);
5938 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5939 if (ret) {
5940 dev_err(hr_dev->dev,
5941 "MODIFY SRQ Failed to cmd mailbox.\n");
5942 return ret;
5943 }
5944 }
5945
5946 return 0;
5947}
5948
c3c668e7 5949static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
c7bcb134
LO		 5950{
5951 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5952 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5953 struct hns_roce_srq_context *srq_context;
5954 struct hns_roce_cmd_mailbox *mailbox;
5955 int limit_wl;
5956 int ret;
5957
5958 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5959 if (IS_ERR(mailbox))
5960 return PTR_ERR(mailbox);
5961
5962 srq_context = mailbox->buf;
5963 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5964 HNS_ROCE_CMD_QUERY_SRQC,
5965 HNS_ROCE_CMD_TIMEOUT_MSECS);
5966 if (ret) {
5967 dev_err(hr_dev->dev, "QUERY SRQ cmd process error\n");
5968 goto out;
5969 }
5970
5971 limit_wl = roce_get_field(srq_context->byte_8_limit_wl,
5972 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5973 SRQC_BYTE_8_SRQ_LIMIT_WL_S);
5974
5975 attr->srq_limit = limit_wl;
5976 attr->max_wr = srq->max - 1;
5977 attr->max_sge = srq->max_gs;
5978
5979 memcpy(srq_context, mailbox->buf, sizeof(*srq_context));
5980
5981out:
5982 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5983 return ret;
5984}
5985
5986static int find_empty_entry(struct hns_roce_idx_que *idx_que)
5987{
5988 int bit_num;
5989 int i;
5990
5991 /* bitmap[i] is set zero if all bits are allocated */
5992 for (i = 0; idx_que->bitmap[i] == 0; ++i)
5993 ;
5994 bit_num = ffs(idx_que->bitmap[i]);
5995 idx_que->bitmap[i] &= ~(1ULL << (bit_num - 1));
5996
5997 return i * sizeof(u64) * 8 + (bit_num - 1);
5998}
5999
6000static void fill_idx_queue(struct hns_roce_idx_que *idx_que,
6001 int cur_idx, int wqe_idx)
6002{
6003 unsigned int *addr;
6004
6005 addr = (unsigned int *)hns_roce_buf_offset(&idx_que->idx_buf,
6006 cur_idx * idx_que->entry_sz);
6007 *addr = wqe_idx;
6008}
6009
6010static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
6011 const struct ib_recv_wr *wr,
6012 const struct ib_recv_wr **bad_wr)
6013{
d3743fa9 6014 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
c7bcb134
LO		 6015 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
6016 struct hns_roce_v2_wqe_data_seg *dseg;
6017 struct hns_roce_v2_db srq_db;
6018 unsigned long flags;
6019 int ret = 0;
6020 int wqe_idx;
6021 void *wqe;
6022 int nreq;
6023 int ind;
6024 int i;
6025
6026 spin_lock_irqsave(&srq->lock, flags);
6027
6028 ind = srq->head & (srq->max - 1);
6029
6030 for (nreq = 0; wr; ++nreq, wr = wr->next) {
6031 if (unlikely(wr->num_sge > srq->max_gs)) {
6032 ret = -EINVAL;
6033 *bad_wr = wr;
6034 break;
6035 }
6036
6037 if (unlikely(srq->head == srq->tail)) {
6038 ret = -ENOMEM;
6039 *bad_wr = wr;
6040 break;
6041 }
6042
6043 wqe_idx = find_empty_entry(&srq->idx_que);
6044 fill_idx_queue(&srq->idx_que, ind, wqe_idx);
6045 wqe = get_srq_wqe(srq, wqe_idx);
6046 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
6047
6048 for (i = 0; i < wr->num_sge; ++i) {
6049 dseg[i].len = cpu_to_le32(wr->sg_list[i].length);
6050 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey);
6051 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr);
6052 }
6053
6054 if (i < srq->max_gs) {
6055 dseg->len = 0;
6056 dseg->lkey = cpu_to_le32(0x100);
6057 dseg->addr = 0;
6058 }
6059
6060 srq->wrid[wqe_idx] = wr->wr_id;
6061 ind = (ind + 1) & (srq->max - 1);
6062 }
6063
6064 if (likely(nreq)) {
6065 srq->head += nreq;
6066
6067 /*
6068 * Make sure that descriptors are written before
6069 * doorbell record.
6070 */
6071 wmb();
6072
6073 srq_db.byte_4 = HNS_ROCE_V2_SRQ_DB << 24 | srq->srqn;
6074 srq_db.parameter = srq->head;
6075
d3743fa9 6076 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l);
c7bcb134
LO		 6077
6078 }
6079
6080 spin_unlock_irqrestore(&srq->lock, flags);
6081
6082 return ret;
6083}
6084
7f645a58
KH		 6085static const struct ib_device_ops hns_roce_v2_dev_ops = {
6086 .destroy_qp = hns_roce_v2_destroy_qp,
6087 .modify_cq = hns_roce_v2_modify_cq,
6088 .poll_cq = hns_roce_v2_poll_cq,
6089 .post_recv = hns_roce_v2_post_recv,
6090 .post_send = hns_roce_v2_post_send,
6091 .query_qp = hns_roce_v2_query_qp,
6092 .req_notify_cq = hns_roce_v2_req_notify_cq,
6093};
6094
6095static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
6096 .modify_srq = hns_roce_v2_modify_srq,
6097 .post_srq_recv = hns_roce_v2_post_srq_recv,
6098 .query_srq = hns_roce_v2_query_srq,
6099};
6100
a04ff739
WHX		 6101static const struct hns_roce_hw hns_roce_hw_v2 = {
6102 .cmq_init = hns_roce_v2_cmq_init,
6103 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 6104 .hw_profile = hns_roce_v2_profile,
6b63597d 6105 .hw_init = hns_roce_v2_init,
6106 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 6107 .post_mbox = hns_roce_v2_post_mbox,
6108 .chk_mbox = hns_roce_v2_chk_mbox,
6a04aed6 6109 .rst_prc_mbox = hns_roce_v2_rst_process_cmd,
7afddafa
WHX		 6110 .set_gid = hns_roce_v2_set_gid,
6111 .set_mac = hns_roce_v2_set_mac,
3958cc56 6112 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 6113 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 6114 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 6115 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 6116 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 6117 .set_hem = hns_roce_v2_set_hem,
6118 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 6119 .modify_qp = hns_roce_v2_modify_qp,
6120 .query_qp = hns_roce_v2_query_qp,
6121 .destroy_qp = hns_roce_v2_destroy_qp,
aa84fa18 6122 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
b156269d 6123 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 6124 .post_send = hns_roce_v2_post_send,
6125 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 6126 .req_notify_cq = hns_roce_v2_req_notify_cq,
6127 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 6128 .init_eq = hns_roce_v2_init_eq_table,
6129 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
c7bcb134
LO		 6130 .write_srqc = hns_roce_v2_write_srqc,
6131 .modify_srq = hns_roce_v2_modify_srq,
6132 .query_srq = hns_roce_v2_query_srq,
6133 .post_srq_recv = hns_roce_v2_post_srq_recv,
7f645a58
KH		 6134 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
6135 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
a04ff739 6136};
dd74282d
WHX		 6137
6138static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
6139 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
6140 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 6141 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
6142 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 6143 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
6144 /* required last entry */
6145 {0, }
6146};
6147
f97a62c3 6148MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
6149
dd74282d
WHX		 6150static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
6151 struct hnae3_handle *handle)
6152{
d061effc 6153 struct hns_roce_v2_priv *priv = hr_dev->priv;
dd74282d 6154 const struct pci_device_id *id;
a5073d60 6155 int i;
dd74282d
WHX		 6156
6157 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
6158 if (!id) {
6159 dev_err(hr_dev->dev, "device is not compatible!\n");
6160 return -ENXIO;
6161 }
6162
6163 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 6164 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
6165 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 6166
6167 /* Get info from NIC driver. */
6168 hr_dev->reg_base = handle->rinfo.roce_io_base;
6169 hr_dev->caps.num_ports = 1;
6170 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
6171 hr_dev->iboe.phy_port[0] = 0;
6172
d4994d2f 6173 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
6174 hr_dev->iboe.netdevs[0]->dev_addr);
6175
a5073d60
YL		 6176 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
6177 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6178 i + handle->rinfo.base_vector);
6179
dd74282d 6180 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 6181 hr_dev->cmd_mod = 1;
dd74282d
WHX		 6182 hr_dev->loop_idc = 0;
6183
d061effc
WHX		 6184 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6185 priv->handle = handle;
6186
dd74282d
WHX		 6187 return 0;
6188}
6189
d061effc 6190static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
dd74282d
WHX		 6191{
6192 struct hns_roce_dev *hr_dev;
6193 int ret;
6194
459cc69f 6195 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
dd74282d
WHX		 6196 if (!hr_dev)
6197 return -ENOMEM;
6198
a04ff739
WHX		 6199 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6200 if (!hr_dev->priv) {
6201 ret = -ENOMEM;
6202 goto error_failed_kzalloc;
6203 }
6204
dd74282d
WHX		 6205 hr_dev->pci_dev = handle->pdev;
6206 hr_dev->dev = &handle->pdev->dev;
dd74282d
WHX		 6207
6208 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
6209 if (ret) {
6210 dev_err(hr_dev->dev, "Get Configuration failed!\n");
6211 goto error_failed_get_cfg;
6212 }
6213
6214 ret = hns_roce_init(hr_dev);
6215 if (ret) {
6216 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6217 goto error_failed_get_cfg;
6218 }
6219
d061effc
WHX		 6220 handle->priv = hr_dev;
6221
dd74282d
WHX		 6222 return 0;
6223
6224error_failed_get_cfg:
a04ff739
WHX		 6225 kfree(hr_dev->priv);
6226
6227error_failed_kzalloc:
dd74282d
WHX		 6228 ib_dealloc_device(&hr_dev->ib_dev);
6229
6230 return ret;
6231}
6232
d061effc 6233static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
dd74282d
WHX		 6234 bool reset)
6235{
6236 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
6237
cb7a94c9
WHX		 6238 if (!hr_dev)
6239 return;
6240
d061effc 6241 handle->priv = NULL;
dd74282d 6242 hns_roce_exit(hr_dev);
a04ff739 6243 kfree(hr_dev->priv);
dd74282d
WHX		 6244 ib_dealloc_device(&hr_dev->ib_dev);
6245}
6246
d061effc
WHX		 6247static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6248{
6249 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
6250 struct device *dev = &handle->pdev->dev;
6251 int ret;
6252
6253 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6254
6255 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6256 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6257 goto reset_chk_err;
6258 }
6259
6260 ret = __hns_roce_hw_v2_init_instance(handle);
6261 if (ret) {
6262 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6263 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6264 if (ops->ae_dev_resetting(handle) ||
6265 ops->get_hw_reset_stat(handle))
6266 goto reset_chk_err;
6267 else
6268 return ret;
6269 }
6270
6271 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6272
6273
6274 return 0;
6275
6276reset_chk_err:
6277 dev_err(dev, "Device is busy in resetting state.\n"
6278 "please retry later.\n");
6279
6280 return -EBUSY;
6281}
6282
6283static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6284 bool reset)
6285{
6286 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6287 return;
6288
6289 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6290
6291 __hns_roce_hw_v2_uninit_instance(handle, reset);
6292
6293 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6294}
cb7a94c9
WHX		 6295static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6296{
d061effc 6297 struct hns_roce_dev *hr_dev;
cb7a94c9
WHX		 6298 struct ib_event event;
6299
d061effc
WHX		 6300 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6301 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6302 return 0;
cb7a94c9
WHX		 6303 }
6304
d061effc
WHX		 6305 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6306 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6307
6308 hr_dev = (struct hns_roce_dev *)handle->priv;
6309 if (!hr_dev)
6310 return 0;
6311
cb7a94c9 6312 hr_dev->active = false;
d3743fa9 6313 hr_dev->dis_db = true;
cb7a94c9
WHX		 6314
6315 event.event = IB_EVENT_DEVICE_FATAL;
6316 event.device = &hr_dev->ib_dev;
6317 event.element.port_num = 1;
6318 ib_dispatch_event(&event);
6319
6320 return 0;
6321}
6322
6323static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6324{
d061effc 6325 struct device *dev = &handle->pdev->dev;
cb7a94c9
WHX		 6326 int ret;
6327
d061effc
WHX		 6328 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6329 &handle->rinfo.state)) {
6330 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6331 return 0;
6332 }
6333
6334 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6335
6336 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6337 ret = __hns_roce_hw_v2_init_instance(handle);
cb7a94c9
WHX		 6338 if (ret) {
6339 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6340 * callback function, RoCE Engine reinitialize. If RoCE reinit
6341 * failed, we should inform NIC driver.
6342 */
6343 handle->priv = NULL;
d061effc
WHX		 6344 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6345 } else {
6346 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6347 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
cb7a94c9
WHX		 6348 }
6349
6350 return ret;
6351}
6352
6353static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6354{
d061effc
WHX		 6355 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6356 return 0;
6357
6358 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6359 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
cb7a94c9 6360 msleep(100);
d061effc
WHX		 6361 __hns_roce_hw_v2_uninit_instance(handle, false);
6362
cb7a94c9
WHX		 6363 return 0;
6364}
6365
6366static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6367 enum hnae3_reset_notify_type type)
6368{
6369 int ret = 0;
6370
6371 switch (type) {
6372 case HNAE3_DOWN_CLIENT:
6373 ret = hns_roce_hw_v2_reset_notify_down(handle);
6374 break;
6375 case HNAE3_INIT_CLIENT:
6376 ret = hns_roce_hw_v2_reset_notify_init(handle);
6377 break;
6378 case HNAE3_UNINIT_CLIENT:
6379 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6380 break;
6381 default:
6382 break;
6383 }
6384
6385 return ret;
6386}
6387
dd74282d
WHX		 6388static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6389 .init_instance = hns_roce_hw_v2_init_instance,
6390 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 6391 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 6392};
6393
6394static struct hnae3_client hns_roce_hw_v2_client = {
6395 .name = "hns_roce_hw_v2",
6396 .type = HNAE3_CLIENT_ROCE,
6397 .ops = &hns_roce_hw_v2_ops,
6398};
6399
6400static int __init hns_roce_hw_v2_init(void)
6401{
6402 return hnae3_register_client(&hns_roce_hw_v2_client);
6403}
6404
6405static void __exit hns_roce_hw_v2_exit(void)
6406{
6407 hnae3_unregister_client(&hns_roce_hw_v2_client);
6408}
6409
6410module_init(hns_roce_hw_v2_init);
6411module_exit(hns_roce_hw_v2_exit);
6412
6413MODULE_LICENSE("Dual BSD/GPL");
6414MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6415MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6416MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6417MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)