projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'usb-ci-v5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter...
[linux-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
0b25c9cc 37#include <linux/types.h>
d4994d2f 38#include <net/addrconf.h>
610b8967 39#include <rdma/ib_addr.h>
a70c0739 40#include <rdma/ib_cache.h>
dd74282d 41#include <rdma/ib_umem.h>
bdeacabd 42#include <rdma/uverbs_ioctl.h>
dd74282d
WHX		 43
44#include "hnae3.h"
45#include "hns_roce_common.h"
46#include "hns_roce_device.h"
47#include "hns_roce_cmd.h"
48#include "hns_roce_hem.h"
a04ff739 49#include "hns_roce_hw_v2.h"
dd74282d 50
2d407888
WHX		 51static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
52 struct ib_sge *sg)
53{
54 dseg->lkey = cpu_to_le32(sg->lkey);
55 dseg->addr = cpu_to_le64(sg->addr);
56 dseg->len = cpu_to_le32(sg->length);
57}
58
e363f7de
XW		 59/*
60 * mapped-value = 1 + real-value
61 * The hns wr opcode real value is start from 0, In order to distinguish between
62 * initialized and uninitialized map values, we plus 1 to the actual value when
63 * defining the mapping, so that the validity can be identified by checking the
64 * mapped value is greater than 0.
65 */
66#define HR_OPC_MAP(ib_key, hr_key) \
67 [IB_WR_ ## ib_key] = 1 + HNS_ROCE_V2_WQE_OP_ ## hr_key
68
69static const u32 hns_roce_op_code[] = {
70 HR_OPC_MAP(RDMA_WRITE, RDMA_WRITE),
71 HR_OPC_MAP(RDMA_WRITE_WITH_IMM, RDMA_WRITE_WITH_IMM),
72 HR_OPC_MAP(SEND, SEND),
73 HR_OPC_MAP(SEND_WITH_IMM, SEND_WITH_IMM),
74 HR_OPC_MAP(RDMA_READ, RDMA_READ),
75 HR_OPC_MAP(ATOMIC_CMP_AND_SWP, ATOM_CMP_AND_SWAP),
76 HR_OPC_MAP(ATOMIC_FETCH_AND_ADD, ATOM_FETCH_AND_ADD),
77 HR_OPC_MAP(SEND_WITH_INV, SEND_WITH_INV),
78 HR_OPC_MAP(LOCAL_INV, LOCAL_INV),
79 HR_OPC_MAP(MASKED_ATOMIC_CMP_AND_SWP, ATOM_MSK_CMP_AND_SWAP),
80 HR_OPC_MAP(MASKED_ATOMIC_FETCH_AND_ADD, ATOM_MSK_FETCH_AND_ADD),
81 HR_OPC_MAP(REG_MR, FAST_REG_PMR),
82};
83
84static u32 to_hr_opcode(u32 ib_opcode)
85{
86 if (ib_opcode >= ARRAY_SIZE(hns_roce_op_code))
87 return HNS_ROCE_V2_WQE_OP_MASK;
88
89 return hns_roce_op_code[ib_opcode] ? hns_roce_op_code[ib_opcode] - 1 :
90 HNS_ROCE_V2_WQE_OP_MASK;
91}
92
68a997c5 93static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
00a59d30 94 void *wqe, const struct ib_reg_wr *wr)
68a997c5
YL		 95{
96 struct hns_roce_mr *mr = to_hr_mr(wr->mr);
00a59d30 97 struct hns_roce_wqe_frmr_seg *fseg = wqe;
9b2cf76c 98 u64 pbl_ba;
68a997c5
YL		 99
100 /* use ib_access_flags */
60262b10 101 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S,
68a997c5 102 wr->access & IB_ACCESS_MW_BIND ? 1 : 0);
60262b10 103 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S,
68a997c5 104 wr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
60262b10 105 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RR_S,
68a997c5 106 wr->access & IB_ACCESS_REMOTE_READ ? 1 : 0);
60262b10 107 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_RW_S,
68a997c5 108 wr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
60262b10 109 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_FRMR_WQE_BYTE_4_LW_S,
68a997c5
YL		 110 wr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
111
112 /* Data structure reuse may lead to confusion */
9b2cf76c
XW		 113 pbl_ba = mr->pbl_mtr.hem_cfg.root_ba;
114 rc_sq_wqe->msg_len = cpu_to_le32(lower_32_bits(pbl_ba));
115 rc_sq_wqe->inv_key = cpu_to_le32(upper_32_bits(pbl_ba));
68a997c5
YL		 116
117 rc_sq_wqe->byte_16 = cpu_to_le32(wr->mr->length & 0xffffffff);
118 rc_sq_wqe->byte_20 = cpu_to_le32(wr->mr->length >> 32);
119 rc_sq_wqe->rkey = cpu_to_le32(wr->key);
120 rc_sq_wqe->va = cpu_to_le64(wr->mr->iova);
121
9b2cf76c 122 fseg->pbl_size = cpu_to_le32(mr->npages);
68a997c5
YL		 123 roce_set_field(fseg->mode_buf_pg_sz,
124 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M,
125 V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S,
9b2cf76c 126 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
68a997c5
YL		 127 roce_set_bit(fseg->mode_buf_pg_sz,
128 V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S, 0);
129}
130
00a59d30
XW		 131static void set_atomic_seg(const struct ib_send_wr *wr, void *wqe,
132 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
13aa13dd 133 unsigned int valid_num_sge)
384f8818 134{
00a59d30
XW		 135 struct hns_roce_wqe_atomic_seg *aseg;
136
137 set_data_seg_v2(wqe, wr->sg_list);
138 aseg = wqe + sizeof(struct hns_roce_v2_wqe_data_seg);
139
140 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
141 aseg->fetchadd_swap_data = cpu_to_le64(atomic_wr(wr)->swap);
142 aseg->cmp_data = cpu_to_le64(atomic_wr(wr)->compare_add);
384f8818 143 } else {
00a59d30
XW		 144 aseg->fetchadd_swap_data =
145 cpu_to_le64(atomic_wr(wr)->compare_add);
384f8818
LO		 146 aseg->cmp_data = 0;
147 }
00a59d30
XW		 148
149 roce_set_field(rc_sq_wqe->byte_16, V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
150 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
384f8818
LO		 151}
152
f696bf6d 153static void set_extend_sge(struct hns_roce_qp *qp, const struct ib_send_wr *wr,
13aa13dd 154 unsigned int *sge_ind, unsigned int valid_num_sge)
0b25c9cc
WHX		 155{
156 struct hns_roce_v2_wqe_data_seg *dseg;
13aa13dd 157 unsigned int cnt = valid_num_sge;
54d66387
XW		 158 struct ib_sge *sge = wr->sg_list;
159 unsigned int idx = *sge_ind;
0b25c9cc 160
54d66387
XW		 161 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
162 cnt -= HNS_ROCE_SGE_IN_WQE;
163 sge += HNS_ROCE_SGE_IN_WQE;
164 }
0b25c9cc 165
54d66387
XW		 166 while (cnt > 0) {
167 dseg = hns_roce_get_extend_sge(qp, idx & (qp->sge.sge_cnt - 1));
168 set_data_seg_v2(dseg, sge);
169 idx++;
170 sge++;
171 cnt--;
0b25c9cc 172 }
54d66387
XW		 173
174 *sge_ind = idx;
0b25c9cc
WHX		 175}
176
f696bf6d 177static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr,
7bdee415 178 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe,
179 void *wqe, unsigned int *sge_ind,
13aa13dd 180 unsigned int valid_num_sge)
7bdee415 181{
182 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
183 struct hns_roce_v2_wqe_data_seg *dseg = wqe;
00a59d30 184 struct ib_device *ibdev = &hr_dev->ib_dev;
7bdee415 185 struct hns_roce_qp *qp = to_hr_qp(ibqp);
468d020e 186 int j = 0;
7bdee415 187 int i;
188
468d020e 189 if (wr->send_flags & IB_SEND_INLINE && valid_num_sge) {
0db65709
LC		 190 if (unlikely(le32_to_cpu(rc_sq_wqe->msg_len) >
191 hr_dev->caps.max_sq_inline)) {
00a59d30
XW		 192 ibdev_err(ibdev, "inline len(1-%d)=%d, illegal",
193 rc_sq_wqe->msg_len,
194 hr_dev->caps.max_sq_inline);
7bdee415 195 return -EINVAL;
196 }
197
0db65709 198 if (unlikely(wr->opcode == IB_WR_RDMA_READ)) {
00a59d30 199 ibdev_err(ibdev, "Not support inline data!\n");
328d405b 200 return -EINVAL;
201 }
202
7bdee415 203 for (i = 0; i < wr->num_sge; i++) {
204 memcpy(wqe, ((void *)wr->sg_list[i].addr),
205 wr->sg_list[i].length);
206 wqe += wr->sg_list[i].length;
207 }
208
209 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_INLINE_S,
210 1);
211 } else {
54d66387 212 if (valid_num_sge <= HNS_ROCE_SGE_IN_WQE) {
7bdee415 213 for (i = 0; i < wr->num_sge; i++) {
214 if (likely(wr->sg_list[i].length)) {
215 set_data_seg_v2(dseg, wr->sg_list + i);
216 dseg++;
217 }
218 }
219 } else {
220 roce_set_field(rc_sq_wqe->byte_20,
221 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
222 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
223 (*sge_ind) & (qp->sge.sge_cnt - 1));
224
54d66387
XW		 225 for (i = 0; i < wr->num_sge && j < HNS_ROCE_SGE_IN_WQE;
226 i++) {
7bdee415 227 if (likely(wr->sg_list[i].length)) {
228 set_data_seg_v2(dseg, wr->sg_list + i);
229 dseg++;
468d020e 230 j++;
7bdee415 231 }
232 }
233
468d020e 234 set_extend_sge(qp, wr, sge_ind, valid_num_sge);
7bdee415 235 }
236
237 roce_set_field(rc_sq_wqe->byte_16,
238 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
468d020e 239 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
7bdee415 240 }
241
242 return 0;
243}
244
626903e9
XW		 245static int check_send_valid(struct hns_roce_dev *hr_dev,
246 struct hns_roce_qp *hr_qp)
247{
ae1c6148 248 struct ib_device *ibdev = &hr_dev->ib_dev;
626903e9 249 struct ib_qp *ibqp = &hr_qp->ibqp;
626903e9
XW		 250
251 if (unlikely(ibqp->qp_type != IB_QPT_RC &&
252 ibqp->qp_type != IB_QPT_GSI &&
253 ibqp->qp_type != IB_QPT_UD)) {
ae1c6148
LO		 254 ibdev_err(ibdev, "Not supported QP(0x%x)type!\n",
255 ibqp->qp_type);
626903e9
XW		 256 return -EOPNOTSUPP;
257 } else if (unlikely(hr_qp->state == IB_QPS_RESET ||
258 hr_qp->state == IB_QPS_INIT ||
259 hr_qp->state == IB_QPS_RTR)) {
ae1c6148
LO		 260 ibdev_err(ibdev, "failed to post WQE, QP state %d!\n",
261 hr_qp->state);
626903e9
XW		 262 return -EINVAL;
263 } else if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN)) {
ae1c6148
LO		 264 ibdev_err(ibdev, "failed to post WQE, dev state %d!\n",
265 hr_dev->state);
626903e9
XW		 266 return -EIO;
267 }
268
269 return 0;
270}
271
13aa13dd
WL		 272static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr,
273 unsigned int *sge_len)
d6a3627e 274{
13aa13dd
WL		 275 unsigned int valid_num = 0;
276 unsigned int len = 0;
d6a3627e
XW		 277 int i;
278
279 for (i = 0; i < wr->num_sge; i++) {
280 if (likely(wr->sg_list[i].length)) {
281 len += wr->sg_list[i].length;
282 valid_num++;
283 }
284 }
285
286 *sge_len = len;
287 return valid_num;
288}
289
290static inline int set_ud_wqe(struct hns_roce_qp *qp,
291 const struct ib_send_wr *wr,
292 void *wqe, unsigned int *sge_idx,
293 unsigned int owner_bit)
294{
295 struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
296 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
297 struct hns_roce_v2_ud_send_wqe *ud_sq_wqe = wqe;
298 unsigned int curr_idx = *sge_idx;
299 int valid_num_sge;
300 u32 msg_len = 0;
301 bool loopback;
302 u8 *smac;
303
304 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
305 memset(ud_sq_wqe, 0, sizeof(*ud_sq_wqe));
306
307 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_0_M,
308 V2_UD_SEND_WQE_DMAC_0_S, ah->av.mac[0]);
309 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_1_M,
310 V2_UD_SEND_WQE_DMAC_1_S, ah->av.mac[1]);
311 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_2_M,
312 V2_UD_SEND_WQE_DMAC_2_S, ah->av.mac[2]);
313 roce_set_field(ud_sq_wqe->dmac, V2_UD_SEND_WQE_DMAC_3_M,
314 V2_UD_SEND_WQE_DMAC_3_S, ah->av.mac[3]);
315 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_4_M,
316 V2_UD_SEND_WQE_BYTE_48_DMAC_4_S, ah->av.mac[4]);
317 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_DMAC_5_M,
318 V2_UD_SEND_WQE_BYTE_48_DMAC_5_S, ah->av.mac[5]);
319
320 /* MAC loopback */
321 smac = (u8 *)hr_dev->dev_addr[qp->port];
322 loopback = ether_addr_equal_unaligned(ah->av.mac, smac) ? 1 : 0;
323
324 roce_set_bit(ud_sq_wqe->byte_40,
325 V2_UD_SEND_WQE_BYTE_40_LBI_S, loopback);
326
327 roce_set_field(ud_sq_wqe->byte_4,
328 V2_UD_SEND_WQE_BYTE_4_OPCODE_M,
329 V2_UD_SEND_WQE_BYTE_4_OPCODE_S,
330 HNS_ROCE_V2_WQE_OP_SEND);
331
332 ud_sq_wqe->msg_len = cpu_to_le32(msg_len);
333
334 switch (wr->opcode) {
335 case IB_WR_SEND_WITH_IMM:
336 case IB_WR_RDMA_WRITE_WITH_IMM:
337 ud_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
338 break;
339 default:
340 ud_sq_wqe->immtdata = 0;
341 break;
342 }
343
344 /* Set sig attr */
345 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_CQE_S,
346 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
347
348 /* Set se attr */
349 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_SE_S,
350 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
351
352 roce_set_bit(ud_sq_wqe->byte_4, V2_UD_SEND_WQE_BYTE_4_OWNER_S,
353 owner_bit);
354
355 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_PD_M,
356 V2_UD_SEND_WQE_BYTE_16_PD_S, to_hr_pd(qp->ibqp.pd)->pdn);
357
358 roce_set_field(ud_sq_wqe->byte_16, V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M,
359 V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S, valid_num_sge);
360
361 roce_set_field(ud_sq_wqe->byte_20,
362 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
363 V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
364 curr_idx & (qp->sge.sge_cnt - 1));
365
366 roce_set_field(ud_sq_wqe->byte_24, V2_UD_SEND_WQE_BYTE_24_UDPSPN_M,
367 V2_UD_SEND_WQE_BYTE_24_UDPSPN_S, 0);
368 ud_sq_wqe->qkey = cpu_to_le32(ud_wr(wr)->remote_qkey & 0x80000000 ?
369 qp->qkey : ud_wr(wr)->remote_qkey);
370 roce_set_field(ud_sq_wqe->byte_32, V2_UD_SEND_WQE_BYTE_32_DQPN_M,
371 V2_UD_SEND_WQE_BYTE_32_DQPN_S, ud_wr(wr)->remote_qpn);
372
373 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_VLAN_M,
374 V2_UD_SEND_WQE_BYTE_36_VLAN_S, ah->av.vlan_id);
375 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
376 V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit);
377 roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
378 V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass);
379 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
380 V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel);
381 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M,
382 V2_UD_SEND_WQE_BYTE_40_SL_S, ah->av.sl);
383 roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_PORTN_M,
384 V2_UD_SEND_WQE_BYTE_40_PORTN_S, qp->port);
385
386 roce_set_bit(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S,
387 ah->av.vlan_en ? 1 : 0);
388 roce_set_field(ud_sq_wqe->byte_48, V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M,
389 V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S, ah->av.gid_index);
390
391 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN_V2);
392
393 set_extend_sge(qp, wr, &curr_idx, valid_num_sge);
394
395 *sge_idx = curr_idx;
396
397 return 0;
398}
399
400static inline int set_rc_wqe(struct hns_roce_qp *qp,
401 const struct ib_send_wr *wr,
402 void *wqe, unsigned int *sge_idx,
403 unsigned int owner_bit)
404{
405 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe;
406 unsigned int curr_idx = *sge_idx;
13aa13dd 407 unsigned int valid_num_sge;
d6a3627e
XW		 408 u32 msg_len = 0;
409 int ret = 0;
410
411 valid_num_sge = calc_wr_sge_num(wr, &msg_len);
412 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
413
414 rc_sq_wqe->msg_len = cpu_to_le32(msg_len);
415
416 switch (wr->opcode) {
417 case IB_WR_SEND_WITH_IMM:
418 case IB_WR_RDMA_WRITE_WITH_IMM:
419 rc_sq_wqe->immtdata = cpu_to_le32(be32_to_cpu(wr->ex.imm_data));
420 break;
421 case IB_WR_SEND_WITH_INV:
422 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
423 break;
424 default:
425 rc_sq_wqe->immtdata = 0;
426 break;
427 }
428
429 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
430 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
431
432 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
433 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
434
435 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
436 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
437
438 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
439 owner_bit);
440
441 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
442 switch (wr->opcode) {
443 case IB_WR_RDMA_READ:
444 case IB_WR_RDMA_WRITE:
445 case IB_WR_RDMA_WRITE_WITH_IMM:
446 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
447 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
448 break;
449 case IB_WR_LOCAL_INV:
450 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SO_S, 1);
451 rc_sq_wqe->inv_key = cpu_to_le32(wr->ex.invalidate_rkey);
452 break;
453 case IB_WR_REG_MR:
454 set_frmr_seg(rc_sq_wqe, wqe, reg_wr(wr));
455 break;
456 case IB_WR_ATOMIC_CMP_AND_SWP:
457 case IB_WR_ATOMIC_FETCH_AND_ADD:
458 rc_sq_wqe->rkey = cpu_to_le32(atomic_wr(wr)->rkey);
459 rc_sq_wqe->va = cpu_to_le64(atomic_wr(wr)->remote_addr);
460 break;
461 default:
462 break;
463 }
464
465 roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
466 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
467 to_hr_opcode(wr->opcode));
468
469 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
470 wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
471 set_atomic_seg(wr, wqe, rc_sq_wqe, valid_num_sge);
472 else if (wr->opcode != IB_WR_REG_MR)
473 ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,
474 wqe, &curr_idx, valid_num_sge);
475
476 *sge_idx = curr_idx;
477
478 return ret;
479}
480
75c994e6
YL		 481static inline void update_sq_db(struct hns_roce_dev *hr_dev,
482 struct hns_roce_qp *qp)
483{
484 /*
485 * Hip08 hardware cannot flush the WQEs in SQ if the QP state
486 * gets into errored mode. Hence, as a workaround to this
487 * hardware limitation, driver needs to assist in flushing. But
488 * the flushing operation uses mailbox to convey the QP state to
489 * the hardware and which can sleep due to the mutex protection
490 * around the mailbox calls. Hence, use the deferred flush for
491 * now.
492 */
493 if (qp->state == IB_QPS_ERR) {
494 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
495 init_flush_work(hr_dev, qp);
496 } else {
497 struct hns_roce_v2_db sq_db = {};
498
499 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
500 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
501 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
502 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
503 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M,
25966e89 504 V2_DB_PARAMETER_IDX_S, qp->sq.head);
75c994e6
YL		 505 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
506 V2_DB_PARAMETER_SL_S, qp->sl);
507
508 hns_roce_write64(hr_dev, (__le32 *)&sq_db, qp->sq.db_reg_l);
509 }
510}
511
d34ac5cd
BVA		 512static int hns_roce_v2_post_send(struct ib_qp *ibqp,
513 const struct ib_send_wr *wr,
514 const struct ib_send_wr **bad_wr)
2d407888
WHX		 515{
516 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
d6a3627e 517 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 518 struct hns_roce_qp *qp = to_hr_qp(ibqp);
d6a3627e 519 unsigned long flags = 0;
e8d18533 520 unsigned int owner_bit;
47688202
YL		 521 unsigned int sge_idx;
522 unsigned int wqe_idx;
2d407888 523 void *wqe = NULL;
2d407888 524 int nreq;
626903e9 525 int ret;
2d407888 526
626903e9 527 spin_lock_irqsave(&qp->sq.lock, flags);
2d407888 528
626903e9 529 ret = check_send_valid(hr_dev, qp);
0db65709 530 if (unlikely(ret)) {
2d407888 531 *bad_wr = wr;
626903e9
XW		 532 nreq = 0;
533 goto out;
2d407888
WHX		 534 }
535
47688202 536 sge_idx = qp->next_sge;
2d407888
WHX		 537
538 for (nreq = 0; wr; ++nreq, wr = wr->next) {
539 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
540 ret = -ENOMEM;
541 *bad_wr = wr;
542 goto out;
543 }
544
47688202
YL		 545 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
546
2d407888 547 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
d6a3627e
XW		 548 ibdev_err(ibdev, "num_sge=%d > qp->sq.max_gs=%d\n",
549 wr->num_sge, qp->sq.max_gs);
2d407888
WHX		 550 ret = -EINVAL;
551 *bad_wr = wr;
552 goto out;
553 }
554
6c6e3921 555 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
47688202 556 qp->sq.wrid[wqe_idx] = wr->wr_id;
634f6390 557 owner_bit =
558 ~(((qp->sq.head + nreq) >> ilog2(qp->sq.wqe_cnt)) & 0x1);
468d020e 559
7bdee415 560 /* Corresponding to the QP type, wqe process separately */
d6a3627e
XW		 561 if (ibqp->qp_type == IB_QPT_GSI)
562 ret = set_ud_wqe(qp, wr, wqe, &sge_idx, owner_bit);
563 else if (ibqp->qp_type == IB_QPT_RC)
564 ret = set_rc_wqe(qp, wr, wqe, &sge_idx, owner_bit);
d6a3627e 565
0db65709 566 if (unlikely(ret)) {
d6a3627e
XW		 567 *bad_wr = wr;
568 goto out;
569 }
2d407888
WHX		 570 }
571
572out:
573 if (likely(nreq)) {
574 qp->sq.head += nreq;
75c994e6 575 qp->next_sge = sge_idx;
2d407888
WHX		 576 /* Memory barrier */
577 wmb();
75c994e6 578 update_sq_db(hr_dev, qp);
2d407888
WHX		 579 }
580
581 spin_unlock_irqrestore(&qp->sq.lock, flags);
582
583 return ret;
584}
585
626903e9
XW		 586static int check_recv_valid(struct hns_roce_dev *hr_dev,
587 struct hns_roce_qp *hr_qp)
588{
589 if (unlikely(hr_dev->state >= HNS_ROCE_DEVICE_STATE_RST_DOWN))
590 return -EIO;
591 else if (hr_qp->state == IB_QPS_RESET)
592 return -EINVAL;
593
594 return 0;
595}
596
d34ac5cd
BVA		 597static int hns_roce_v2_post_recv(struct ib_qp *ibqp,
598 const struct ib_recv_wr *wr,
599 const struct ib_recv_wr **bad_wr)
2d407888
WHX		 600{
601 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
602 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 603 struct ib_device *ibdev = &hr_dev->ib_dev;
2d407888 604 struct hns_roce_v2_wqe_data_seg *dseg;
0009c2db 605 struct hns_roce_rinl_sge *sge_list;
2d407888
WHX		 606 unsigned long flags;
607 void *wqe = NULL;
47688202 608 u32 wqe_idx;
2d407888 609 int nreq;
626903e9 610 int ret;
2d407888
WHX		 611 int i;
612
613 spin_lock_irqsave(&hr_qp->rq.lock, flags);
2d407888 614
626903e9 615 ret = check_recv_valid(hr_dev, hr_qp);
0db65709 616 if (unlikely(ret)) {
2d407888 617 *bad_wr = wr;
626903e9
XW		 618 nreq = 0;
619 goto out;
2d407888
WHX		 620 }
621
622 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0db65709
LC		 623 if (unlikely(hns_roce_wq_overflow(&hr_qp->rq, nreq,
624 hr_qp->ibqp.recv_cq))) {
2d407888
WHX		 625 ret = -ENOMEM;
626 *bad_wr = wr;
627 goto out;
628 }
629
47688202
YL		 630 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
631
711195e5 632 if (unlikely(wr->num_sge >= hr_qp->rq.max_gs)) {
ae1c6148
LO		 633 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n",
634 wr->num_sge, hr_qp->rq.max_gs);
2d407888
WHX		 635 ret = -EINVAL;
636 *bad_wr = wr;
637 goto out;
638 }
639
6c6e3921 640 wqe = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
2d407888
WHX		 641 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
642 for (i = 0; i < wr->num_sge; i++) {
643 if (!wr->sg_list[i].length)
644 continue;
645 set_data_seg_v2(dseg, wr->sg_list + i);
646 dseg++;
647 }
648
e1b43f07 649 if (wr->num_sge < hr_qp->rq.max_gs) {
778cc5a8 650 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
651 dseg->addr = 0;
711195e5 652 dseg->len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
2d407888
WHX		 653 }
654
0009c2db 655 /* rq support inline data */
54d66387 656 if (hr_qp->rq_inl_buf.wqe_cnt) {
47688202
YL		 657 sge_list = hr_qp->rq_inl_buf.wqe_list[wqe_idx].sg_list;
658 hr_qp->rq_inl_buf.wqe_list[wqe_idx].sge_cnt =
ecaaf1e2 659 (u32)wr->num_sge;
660 for (i = 0; i < wr->num_sge; i++) {
661 sge_list[i].addr =
662 (void *)(u64)wr->sg_list[i].addr;
663 sge_list[i].len = wr->sg_list[i].length;
664 }
0009c2db 665 }
666
47688202 667 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
2d407888
WHX		 668 }
669
670out:
671 if (likely(nreq)) {
672 hr_qp->rq.head += nreq;
673 /* Memory barrier */
674 wmb();
675
b5374286
YL		 676 /*
677 * Hip08 hardware cannot flush the WQEs in RQ if the QP state
678 * gets into errored mode. Hence, as a workaround to this
679 * hardware limitation, driver needs to assist in flushing. But
680 * the flushing operation uses mailbox to convey the QP state to
681 * the hardware and which can sleep due to the mutex protection
682 * around the mailbox calls. Hence, use the deferred flush for
683 * now.
684 */
75c994e6 685 if (hr_qp->state == IB_QPS_ERR) {
b5374286
YL		 686 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG,
687 &hr_qp->flush_flag))
688 init_flush_work(hr_dev, hr_qp);
75c994e6
YL		 689 } else {
690 *hr_qp->rdb.db_record = hr_qp->rq.head & 0xffff;
691 }
2d407888
WHX		 692 }
693 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
694
695 return ret;
696}
697
ffb1308b
YL		 698static void *get_srq_wqe(struct hns_roce_srq *srq, int n)
699{
700 return hns_roce_buf_offset(srq->buf_mtr.kmem, n << srq->wqe_shift);
701}
702
67954a6e
XW		 703static void *get_idx_buf(struct hns_roce_idx_que *idx_que, int n)
704{
705 return hns_roce_buf_offset(idx_que->mtr.kmem,
706 n << idx_que->entry_shift);
707}
708
ffb1308b
YL		 709static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, int wqe_index)
710{
711 /* always called with interrupts disabled. */
712 spin_lock(&srq->lock);
713
714 bitmap_clear(srq->idx_que.bitmap, wqe_index, 1);
715 srq->tail++;
716
717 spin_unlock(&srq->lock);
718}
719
720static int find_empty_entry(struct hns_roce_idx_que *idx_que,
721 unsigned long size)
722{
723 int wqe_idx;
724
725 if (unlikely(bitmap_full(idx_que->bitmap, size)))
726 return -ENOSPC;
727
728 wqe_idx = find_first_zero_bit(idx_que->bitmap, size);
729
730 bitmap_set(idx_que->bitmap, wqe_idx, 1);
731
732 return wqe_idx;
733}
734
ffb1308b
YL		 735static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq,
736 const struct ib_recv_wr *wr,
737 const struct ib_recv_wr **bad_wr)
738{
739 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
740 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
741 struct hns_roce_v2_wqe_data_seg *dseg;
742 struct hns_roce_v2_db srq_db;
743 unsigned long flags;
67954a6e 744 __le32 *srq_idx;
ffb1308b
YL		 745 int ret = 0;
746 int wqe_idx;
747 void *wqe;
748 int nreq;
749 int ind;
750 int i;
751
752 spin_lock_irqsave(&srq->lock, flags);
753
754 ind = srq->head & (srq->wqe_cnt - 1);
755
756 for (nreq = 0; wr; ++nreq, wr = wr->next) {
757 if (unlikely(wr->num_sge >= srq->max_gs)) {
758 ret = -EINVAL;
759 *bad_wr = wr;
760 break;
761 }
762
763 if (unlikely(srq->head == srq->tail)) {
764 ret = -ENOMEM;
765 *bad_wr = wr;
766 break;
767 }
768
769 wqe_idx = find_empty_entry(&srq->idx_que, srq->wqe_cnt);
0db65709 770 if (unlikely(wqe_idx < 0)) {
ffb1308b
YL		 771 ret = -ENOMEM;
772 *bad_wr = wr;
773 break;
774 }
775
ffb1308b
YL		 776 wqe = get_srq_wqe(srq, wqe_idx);
777 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
778
779 for (i = 0; i < wr->num_sge; ++i) {
780 dseg[i].len = cpu_to_le32(wr->sg_list[i].length);
781 dseg[i].lkey = cpu_to_le32(wr->sg_list[i].lkey);
782 dseg[i].addr = cpu_to_le64(wr->sg_list[i].addr);
783 }
784
e1b43f07 785 if (wr->num_sge < srq->max_gs) {
711195e5
LO		 786 dseg[i].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
787 dseg[i].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
ffb1308b
YL		 788 dseg[i].addr = 0;
789 }
790
67954a6e
XW		 791 srq_idx = get_idx_buf(&srq->idx_que, ind);
792 *srq_idx = cpu_to_le32(wqe_idx);
793
ffb1308b
YL		 794 srq->wrid[wqe_idx] = wr->wr_id;
795 ind = (ind + 1) & (srq->wqe_cnt - 1);
796 }
797
798 if (likely(nreq)) {
799 srq->head += nreq;
800
801 /*
802 * Make sure that descriptors are written before
803 * doorbell record.
804 */
805 wmb();
806
807 srq_db.byte_4 =
808 cpu_to_le32(HNS_ROCE_V2_SRQ_DB << V2_DB_BYTE_4_CMD_S |
809 (srq->srqn & V2_DB_BYTE_4_TAG_M));
25966e89
LC		 810 srq_db.parameter =
811 cpu_to_le32(srq->head & V2_DB_PARAMETER_IDX_M);
ffb1308b
YL		 812
813 hns_roce_write64(hr_dev, (__le32 *)&srq_db, srq->db_reg_l);
814 }
815
816 spin_unlock_irqrestore(&srq->lock, flags);
817
818 return ret;
819}
820
6a04aed6
WHX		 821static int hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev,
822 unsigned long instance_stage,
823 unsigned long reset_stage)
824{
825 /* When hardware reset has been completed once or more, we should stop
d3743fa9 826 * sending mailbox&cmq&doorbell to hardware. If now in .init_instance()
6a04aed6
WHX		 827 * function, we should exit with error. If now at HNAE3_INIT_CLIENT
828 * stage of soft reset process, we should exit with error, and then
829 * HNAE3_INIT_CLIENT related process can rollback the operation like
830 * notifing hardware to free resources, HNAE3_INIT_CLIENT related
831 * process will exit with error to notify NIC driver to reschedule soft
832 * reset process once again.
833 */
834 hr_dev->is_reset = true;
d3743fa9 835 hr_dev->dis_db = true;
6a04aed6
WHX		 836
837 if (reset_stage == HNS_ROCE_STATE_RST_INIT ||
838 instance_stage == HNS_ROCE_STATE_INIT)
839 return CMD_RST_PRC_EBUSY;
840
841 return CMD_RST_PRC_SUCCESS;
842}
843
844static int hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev,
845 unsigned long instance_stage,
846 unsigned long reset_stage)
847{
14ba8730 848 struct hns_roce_v2_priv *priv = hr_dev->priv;
6a04aed6
WHX		 849 struct hnae3_handle *handle = priv->handle;
850 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
851
d3743fa9
WHX		 852 /* When hardware reset is detected, we should stop sending mailbox&cmq&
853 * doorbell to hardware. If now in .init_instance() function, we should
6a04aed6
WHX		 854 * exit with error. If now at HNAE3_INIT_CLIENT stage of soft reset
855 * process, we should exit with error, and then HNAE3_INIT_CLIENT
856 * related process can rollback the operation like notifing hardware to
857 * free resources, HNAE3_INIT_CLIENT related process will exit with
858 * error to notify NIC driver to reschedule soft reset process once
859 * again.
860 */
d3743fa9 861 hr_dev->dis_db = true;
6a04aed6
WHX		 862 if (!ops->get_hw_reset_stat(handle))
863 hr_dev->is_reset = true;
864
865 if (!hr_dev->is_reset || reset_stage == HNS_ROCE_STATE_RST_INIT ||
866 instance_stage == HNS_ROCE_STATE_INIT)
867 return CMD_RST_PRC_EBUSY;
868
869 return CMD_RST_PRC_SUCCESS;
870}
871
872static int hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev)
873{
14ba8730 874 struct hns_roce_v2_priv *priv = hr_dev->priv;
6a04aed6
WHX		 875 struct hnae3_handle *handle = priv->handle;
876 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
877
878 /* When software reset is detected at .init_instance() function, we
d3743fa9
WHX		 879 * should stop sending mailbox&cmq&doorbell to hardware, and exit
880 * with error.
6a04aed6 881 */
d3743fa9 882 hr_dev->dis_db = true;
6a04aed6
WHX		 883 if (ops->ae_dev_reset_cnt(handle) != hr_dev->reset_cnt)
884 hr_dev->is_reset = true;
885
886 return CMD_RST_PRC_EBUSY;
887}
888
889static int hns_roce_v2_rst_process_cmd(struct hns_roce_dev *hr_dev)
890{
14ba8730 891 struct hns_roce_v2_priv *priv = hr_dev->priv;
6a04aed6
WHX		 892 struct hnae3_handle *handle = priv->handle;
893 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
894 unsigned long instance_stage; /* the current instance stage */
895 unsigned long reset_stage; /* the current reset stage */
896 unsigned long reset_cnt;
897 bool sw_resetting;
898 bool hw_resetting;
899
900 if (hr_dev->is_reset)
901 return CMD_RST_PRC_SUCCESS;
902
903 /* Get information about reset from NIC driver or RoCE driver itself,
904 * the meaning of the following variables from NIC driver are described
905 * as below:
906 * reset_cnt -- The count value of completed hardware reset.
907 * hw_resetting -- Whether hardware device is resetting now.
908 * sw_resetting -- Whether NIC's software reset process is running now.
909 */
910 instance_stage = handle->rinfo.instance_state;
911 reset_stage = handle->rinfo.reset_state;
912 reset_cnt = ops->ae_dev_reset_cnt(handle);
3ec5f54f 913 hw_resetting = ops->get_cmdq_stat(handle);
6a04aed6
WHX		 914 sw_resetting = ops->ae_dev_resetting(handle);
915
916 if (reset_cnt != hr_dev->reset_cnt)
917 return hns_roce_v2_cmd_hw_reseted(hr_dev, instance_stage,
918 reset_stage);
919 else if (hw_resetting)
920 return hns_roce_v2_cmd_hw_resetting(hr_dev, instance_stage,
921 reset_stage);
922 else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT)
923 return hns_roce_v2_cmd_sw_resetting(hr_dev);
924
925 return 0;
926}
927
a04ff739
WHX		 928static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
929{
930 int ntu = ring->next_to_use;
931 int ntc = ring->next_to_clean;
932 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
933
934 return ring->desc_num - used - 1;
935}
936
937static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
938 struct hns_roce_v2_cmq_ring *ring)
939{
940 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
941
942 ring->desc = kzalloc(size, GFP_KERNEL);
943 if (!ring->desc)
944 return -ENOMEM;
945
946 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
947 DMA_BIDIRECTIONAL);
948 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
949 ring->desc_dma_addr = 0;
950 kfree(ring->desc);
951 ring->desc = NULL;
952 return -ENOMEM;
953 }
954
955 return 0;
956}
957
958static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
959 struct hns_roce_v2_cmq_ring *ring)
960{
961 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
962 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
963 DMA_BIDIRECTIONAL);
90e7a4d5 964
965 ring->desc_dma_addr = 0;
a04ff739
WHX		 966 kfree(ring->desc);
967}
968
969static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
970{
14ba8730 971 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 972 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
973 &priv->cmq.csq : &priv->cmq.crq;
974
975 ring->flag = ring_type;
976 ring->next_to_clean = 0;
977 ring->next_to_use = 0;
978
979 return hns_roce_alloc_cmq_desc(hr_dev, ring);
980}
981
982static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
983{
14ba8730 984 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 985 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
986 &priv->cmq.csq : &priv->cmq.crq;
987 dma_addr_t dma = ring->desc_dma_addr;
988
989 if (ring_type == TYPE_CSQ) {
990 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
991 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
992 upper_32_bits(dma));
993 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
2288b3b3 994 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 995 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
996 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
997 } else {
998 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
999 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
1000 upper_32_bits(dma));
1001 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
2288b3b3 1002 ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
a04ff739
WHX		 1003 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
1004 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
1005 }
1006}
1007
1008static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
1009{
14ba8730 1010 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1011 int ret;
1012
1013 /* Setup the queue entries for command queue */
426c4146
LO		 1014 priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
1015 priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
a04ff739
WHX		 1016
1017 /* Setup the lock for command queue */
1018 spin_lock_init(&priv->cmq.csq.lock);
1019 spin_lock_init(&priv->cmq.crq.lock);
1020
1021 /* Setup Tx write back timeout */
1022 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1023
1024 /* Init CSQ */
1025 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
1026 if (ret) {
1027 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
1028 return ret;
1029 }
1030
1031 /* Init CRQ */
1032 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
1033 if (ret) {
1034 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
1035 goto err_crq;
1036 }
1037
1038 /* Init CSQ REG */
1039 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
1040
1041 /* Init CRQ REG */
1042 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
1043
1044 return 0;
1045
1046err_crq:
1047 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1048
1049 return ret;
1050}
1051
1052static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
1053{
14ba8730 1054 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1055
1056 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1057 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
1058}
1059
281d0ccf
CIK		 1060static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
1061 enum hns_roce_opcode_type opcode,
1062 bool is_read)
a04ff739
WHX		 1063{
1064 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
1065 desc->opcode = cpu_to_le16(opcode);
1066 desc->flag =
1067 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1068 if (is_read)
1069 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
1070 else
1071 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1072}
1073
1074static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
1075{
a04ff739 1076 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
14ba8730 1077 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1078
1079 return head == priv->cmq.csq.next_to_use;
1080}
1081
1082static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
1083{
14ba8730 1084 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1085 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1086 struct hns_roce_cmq_desc *desc;
1087 u16 ntc = csq->next_to_clean;
1088 u32 head;
1089 int clean = 0;
1090
1091 desc = &csq->desc[ntc];
1092 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
1093 while (head != ntc) {
1094 memset(desc, 0, sizeof(*desc));
1095 ntc++;
1096 if (ntc == csq->desc_num)
1097 ntc = 0;
1098 desc = &csq->desc[ntc];
1099 clean++;
1100 }
1101 csq->next_to_clean = ntc;
1102
1103 return clean;
1104}
1105
6a04aed6
WHX		 1106static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
1107 struct hns_roce_cmq_desc *desc, int num)
a04ff739 1108{
14ba8730 1109 struct hns_roce_v2_priv *priv = hr_dev->priv;
a04ff739
WHX		 1110 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
1111 struct hns_roce_cmq_desc *desc_to_use;
1112 bool complete = false;
1113 u32 timeout = 0;
1114 int handle = 0;
1115 u16 desc_ret;
1116 int ret = 0;
1117 int ntc;
1118
1119 spin_lock_bh(&csq->lock);
1120
1121 if (num > hns_roce_cmq_space(csq)) {
1122 spin_unlock_bh(&csq->lock);
1123 return -EBUSY;
1124 }
1125
1126 /*
1127 * Record the location of desc in the cmq for this time
1128 * which will be use for hardware to write back
1129 */
1130 ntc = csq->next_to_use;
1131
1132 while (handle < num) {
1133 desc_to_use = &csq->desc[csq->next_to_use];
1134 *desc_to_use = desc[handle];
1135 dev_dbg(hr_dev->dev, "set cmq desc:\n");
1136 csq->next_to_use++;
1137 if (csq->next_to_use == csq->desc_num)
1138 csq->next_to_use = 0;
1139 handle++;
1140 }
1141
1142 /* Write to hardware */
1143 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
1144
1145 /*
1146 * If the command is sync, wait for the firmware to write back,
1147 * if multi descriptors to be sent, use the first one to check
1148 */
bfe86035 1149 if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
a04ff739
WHX		 1150 do {
1151 if (hns_roce_cmq_csq_done(hr_dev))
1152 break;
988e175b 1153 udelay(1);
a04ff739
WHX		 1154 timeout++;
1155 } while (timeout < priv->cmq.tx_timeout);
1156 }
1157
1158 if (hns_roce_cmq_csq_done(hr_dev)) {
1159 complete = true;
1160 handle = 0;
1161 while (handle < num) {
1162 /* get the result of hardware write back */
1163 desc_to_use = &csq->desc[ntc];
1164 desc[handle] = *desc_to_use;
1165 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
bfe86035 1166 desc_ret = le16_to_cpu(desc[handle].retval);
a04ff739
WHX		 1167 if (desc_ret == CMD_EXEC_SUCCESS)
1168 ret = 0;
1169 else
1170 ret = -EIO;
1171 priv->cmq.last_status = desc_ret;
1172 ntc++;
1173 handle++;
1174 if (ntc == csq->desc_num)
1175 ntc = 0;
1176 }
1177 }
1178
1179 if (!complete)
1180 ret = -EAGAIN;
1181
1182 /* clean the command send queue */
1183 handle = hns_roce_cmq_csq_clean(hr_dev);
1184 if (handle != num)
1185 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
1186 handle, num);
1187
1188 spin_unlock_bh(&csq->lock);
1189
1190 return ret;
1191}
1192
e95e52a1 1193static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
6a04aed6
WHX		 1194 struct hns_roce_cmq_desc *desc, int num)
1195{
1196 int retval;
1197 int ret;
1198
1199 ret = hns_roce_v2_rst_process_cmd(hr_dev);
1200 if (ret == CMD_RST_PRC_SUCCESS)
1201 return 0;
1202 if (ret == CMD_RST_PRC_EBUSY)
b417c087 1203 return -EBUSY;
6a04aed6
WHX		 1204
1205 ret = __hns_roce_cmq_send(hr_dev, desc, num);
1206 if (ret) {
1207 retval = hns_roce_v2_rst_process_cmd(hr_dev);
1208 if (retval == CMD_RST_PRC_SUCCESS)
1209 return 0;
1210 else if (retval == CMD_RST_PRC_EBUSY)
b417c087 1211 return -EBUSY;
6a04aed6
WHX		 1212 }
1213
1214 return ret;
1215}
1216
281d0ccf 1217static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 1218{
1219 struct hns_roce_query_version *resp;
1220 struct hns_roce_cmq_desc desc;
1221 int ret;
1222
1223 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
1224 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1225 if (ret)
1226 return ret;
1227
1228 resp = (struct hns_roce_query_version *)desc.data;
bfe86035 1229 hr_dev->hw_rev = le16_to_cpu(resp->rocee_hw_version);
3a63c964
LO		 1230 hr_dev->vendor_id = hr_dev->pci_dev->vendor;
1231
1232 return 0;
1233}
1234
e075da5e
LC		 1235static bool hns_roce_func_clr_chk_rst(struct hns_roce_dev *hr_dev)
1236{
14ba8730 1237 struct hns_roce_v2_priv *priv = hr_dev->priv;
e075da5e
LC		 1238 struct hnae3_handle *handle = priv->handle;
1239 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1240 unsigned long reset_cnt;
1241 bool sw_resetting;
1242 bool hw_resetting;
1243
1244 reset_cnt = ops->ae_dev_reset_cnt(handle);
1245 hw_resetting = ops->get_hw_reset_stat(handle);
1246 sw_resetting = ops->ae_dev_resetting(handle);
1247
1248 if (reset_cnt != hr_dev->reset_cnt || hw_resetting || sw_resetting)
1249 return true;
1250
1251 return false;
1252}
1253
1254static void hns_roce_func_clr_rst_prc(struct hns_roce_dev *hr_dev, int retval,
1255 int flag)
1256{
14ba8730 1257 struct hns_roce_v2_priv *priv = hr_dev->priv;
e075da5e
LC		 1258 struct hnae3_handle *handle = priv->handle;
1259 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
1260 unsigned long instance_stage;
1261 unsigned long reset_cnt;
1262 unsigned long end;
1263 bool sw_resetting;
1264 bool hw_resetting;
1265
1266 instance_stage = handle->rinfo.instance_state;
1267 reset_cnt = ops->ae_dev_reset_cnt(handle);
1268 hw_resetting = ops->get_hw_reset_stat(handle);
1269 sw_resetting = ops->ae_dev_resetting(handle);
1270
1271 if (reset_cnt != hr_dev->reset_cnt) {
1272 hr_dev->dis_db = true;
1273 hr_dev->is_reset = true;
1274 dev_info(hr_dev->dev, "Func clear success after reset.\n");
1275 } else if (hw_resetting) {
1276 hr_dev->dis_db = true;
1277
1278 dev_warn(hr_dev->dev,
1279 "Func clear is pending, device in resetting state.\n");
1280 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1281 while (end) {
1282 if (!ops->get_hw_reset_stat(handle)) {
1283 hr_dev->is_reset = true;
1284 dev_info(hr_dev->dev,
1285 "Func clear success after reset.\n");
1286 return;
1287 }
1288 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1289 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1290 }
1291
1292 dev_warn(hr_dev->dev, "Func clear failed.\n");
1293 } else if (sw_resetting && instance_stage == HNS_ROCE_STATE_INIT) {
1294 hr_dev->dis_db = true;
1295
1296 dev_warn(hr_dev->dev,
1297 "Func clear is pending, device in resetting state.\n");
1298 end = HNS_ROCE_V2_HW_RST_TIMEOUT;
1299 while (end) {
1300 if (ops->ae_dev_reset_cnt(handle) !=
1301 hr_dev->reset_cnt) {
1302 hr_dev->is_reset = true;
1303 dev_info(hr_dev->dev,
1304 "Func clear success after sw reset\n");
1305 return;
1306 }
1307 msleep(HNS_ROCE_V2_HW_RST_COMPLETION_WAIT);
1308 end -= HNS_ROCE_V2_HW_RST_COMPLETION_WAIT;
1309 }
1310
1311 dev_warn(hr_dev->dev, "Func clear failed because of unfinished sw reset\n");
1312 } else {
1313 if (retval && !flag)
1314 dev_warn(hr_dev->dev,
1315 "Func clear read failed, ret = %d.\n", retval);
1316
1317 dev_warn(hr_dev->dev, "Func clear failed.\n");
1318 }
1319}
89a6da3c
LC		 1320static void hns_roce_function_clear(struct hns_roce_dev *hr_dev)
1321{
e075da5e 1322 bool fclr_write_fail_flag = false;
89a6da3c
LC		 1323 struct hns_roce_func_clear *resp;
1324 struct hns_roce_cmq_desc desc;
1325 unsigned long end;
e075da5e
LC		 1326 int ret = 0;
1327
1328 if (hns_roce_func_clr_chk_rst(hr_dev))
1329 goto out;
89a6da3c
LC		 1330
1331 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR, false);
1332 resp = (struct hns_roce_func_clear *)desc.data;
1333
1334 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1335 if (ret) {
e075da5e 1336 fclr_write_fail_flag = true;
89a6da3c
LC		 1337 dev_err(hr_dev->dev, "Func clear write failed, ret = %d.\n",
1338 ret);
e075da5e 1339 goto out;
89a6da3c
LC		 1340 }
1341
1342 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL);
1343 end = HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS;
1344 while (end) {
e075da5e
LC		 1345 if (hns_roce_func_clr_chk_rst(hr_dev))
1346 goto out;
89a6da3c
LC		 1347 msleep(HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT);
1348 end -= HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT;
1349
1350 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_FUNC_CLEAR,
1351 true);
1352
1353 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1354 if (ret)
1355 continue;
1356
1357 if (roce_get_bit(resp->func_done, FUNC_CLEAR_RST_FUN_DONE_S)) {
1358 hr_dev->is_reset = true;
1359 return;
1360 }
1361 }
1362
e075da5e 1363out:
e075da5e 1364 hns_roce_func_clr_rst_prc(hr_dev, ret, fclr_write_fail_flag);
89a6da3c
LC		 1365}
1366
3a63c964
LO		 1367static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev)
1368{
1369 struct hns_roce_query_fw_info *resp;
1370 struct hns_roce_cmq_desc desc;
1371 int ret;
1372
1373 hns_roce_cmq_setup_basic_desc(&desc, HNS_QUERY_FW_VER, true);
1374 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1375 if (ret)
1376 return ret;
1377
1378 resp = (struct hns_roce_query_fw_info *)desc.data;
1379 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver));
cfc85f3e
WHX		 1380
1381 return 0;
1382}
1383
1384static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
1385{
1386 struct hns_roce_cfg_global_param *req;
1387 struct hns_roce_cmq_desc desc;
1388
1389 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
1390 false);
1391
1392 req = (struct hns_roce_cfg_global_param *)desc.data;
1393 memset(req, 0, sizeof(*req));
1394 roce_set_field(req->time_cfg_udp_port,
1395 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
1396 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
1397 roce_set_field(req->time_cfg_udp_port,
1398 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
1399 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
1400
1401 return hns_roce_cmq_send(hr_dev, &desc, 1);
1402}
1403
1404static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
1405{
1406 struct hns_roce_cmq_desc desc[2];
6b63597d 1407 struct hns_roce_pf_res_a *req_a;
1408 struct hns_roce_pf_res_b *req_b;
cfc85f3e
WHX		 1409 int ret;
1410 int i;
1411
1412 for (i = 0; i < 2; i++) {
1413 hns_roce_cmq_setup_basic_desc(&desc[i],
1414 HNS_ROCE_OPC_QUERY_PF_RES, true);
1415
1416 if (i == 0)
1417 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1418 else
1419 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1420 }
1421
1422 ret = hns_roce_cmq_send(hr_dev, desc, 2);
1423 if (ret)
1424 return ret;
1425
6b63597d 1426 req_a = (struct hns_roce_pf_res_a *)desc[0].data;
1427 req_b = (struct hns_roce_pf_res_b *)desc[1].data;
cfc85f3e 1428
6b63597d 1429 hr_dev->caps.qpc_bt_num = roce_get_field(req_a->qpc_bt_idx_num,
cfc85f3e
WHX		 1430 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
1431 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
6b63597d 1432 hr_dev->caps.srqc_bt_num = roce_get_field(req_a->srqc_bt_idx_num,
cfc85f3e
WHX		 1433 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
1434 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
6b63597d 1435 hr_dev->caps.cqc_bt_num = roce_get_field(req_a->cqc_bt_idx_num,
cfc85f3e
WHX		 1436 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
1437 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
6b63597d 1438 hr_dev->caps.mpt_bt_num = roce_get_field(req_a->mpt_bt_idx_num,
cfc85f3e
WHX		 1439 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
1440 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
1441
6b63597d 1442 hr_dev->caps.sl_num = roce_get_field(req_b->qid_idx_sl_num,
1443 PF_RES_DATA_3_PF_SL_NUM_M,
1444 PF_RES_DATA_3_PF_SL_NUM_S);
6a157f7d
YL		 1445 hr_dev->caps.sccc_bt_num = roce_get_field(req_b->sccc_bt_idx_num,
1446 PF_RES_DATA_4_PF_SCCC_BT_NUM_M,
1447 PF_RES_DATA_4_PF_SCCC_BT_NUM_S);
6b63597d 1448
cfc85f3e
WHX		 1449 return 0;
1450}
1451
0e40dc2f
YL		 1452static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
1453{
1454 struct hns_roce_pf_timer_res_a *req_a;
441c88d5
LC		 1455 struct hns_roce_cmq_desc desc;
1456 int ret;
0e40dc2f 1457
441c88d5
LC		 1458 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
1459 true);
0e40dc2f 1460
441c88d5 1461 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
0e40dc2f
YL		 1462 if (ret)
1463 return ret;
1464
441c88d5 1465 req_a = (struct hns_roce_pf_timer_res_a *)desc.data;
0e40dc2f
YL		 1466
1467 hr_dev->caps.qpc_timer_bt_num =
441c88d5
LC		 1468 roce_get_field(req_a->qpc_timer_bt_idx_num,
1469 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
1470 PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
0e40dc2f 1471 hr_dev->caps.cqc_timer_bt_num =
441c88d5
LC		 1472 roce_get_field(req_a->cqc_timer_bt_idx_num,
1473 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
1474 PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
0e40dc2f
YL		 1475
1476 return 0;
1477}
1478
60262b10 1479static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id)
0c1c3880
LO		 1480{
1481 struct hns_roce_cmq_desc desc;
1482 struct hns_roce_vf_switch *swt;
1483 int ret;
1484
1485 swt = (struct hns_roce_vf_switch *)desc.data;
1486 hns_roce_cmq_setup_basic_desc(&desc, HNS_SWITCH_PARAMETER_CFG, true);
bfe86035 1487 swt->rocee_sel |= cpu_to_le32(HNS_ICL_SWITCH_CMD_ROCEE_SEL);
60262b10
LO		 1488 roce_set_field(swt->fun_id, VF_SWITCH_DATA_FUN_ID_VF_ID_M,
1489 VF_SWITCH_DATA_FUN_ID_VF_ID_S, vf_id);
0c1c3880
LO		 1490 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
1491 if (ret)
1492 return ret;
60262b10 1493
0c1c3880
LO		 1494 desc.flag =
1495 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
1496 desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
1497 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1);
d967e262 1498 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0);
0c1c3880
LO		 1499 roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S, 1);
1500
1501 return hns_roce_cmq_send(hr_dev, &desc, 1);
1502}
1503
cfc85f3e
WHX		 1504static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
1505{
1506 struct hns_roce_cmq_desc desc[2];
1507 struct hns_roce_vf_res_a *req_a;
1508 struct hns_roce_vf_res_b *req_b;
1509 int i;
1510
1511 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
1512 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
1513 memset(req_a, 0, sizeof(*req_a));
1514 memset(req_b, 0, sizeof(*req_b));
1515 for (i = 0; i < 2; i++) {
1516 hns_roce_cmq_setup_basic_desc(&desc[i],
1517 HNS_ROCE_OPC_ALLOC_VF_RES, false);
1518
1519 if (i == 0)
1520 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1521 else
1522 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
cfc85f3e
WHX		 1523 }
1524
99e713f8
LO		 1525 roce_set_field(req_a->vf_qpc_bt_idx_num,
1526 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
1527 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
1528 roce_set_field(req_a->vf_qpc_bt_idx_num,
1529 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
1530 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S, HNS_ROCE_VF_QPC_BT_NUM);
1531
1532 roce_set_field(req_a->vf_srqc_bt_idx_num,
1533 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
1534 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
1535 roce_set_field(req_a->vf_srqc_bt_idx_num,
1536 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
1537 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
1538 HNS_ROCE_VF_SRQC_BT_NUM);
1539
1540 roce_set_field(req_a->vf_cqc_bt_idx_num,
1541 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
1542 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
1543 roce_set_field(req_a->vf_cqc_bt_idx_num,
1544 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
1545 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S, HNS_ROCE_VF_CQC_BT_NUM);
1546
1547 roce_set_field(req_a->vf_mpt_bt_idx_num,
1548 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
1549 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
1550 roce_set_field(req_a->vf_mpt_bt_idx_num,
1551 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
1552 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S, HNS_ROCE_VF_MPT_BT_NUM);
1553
1554 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_IDX_M,
1555 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
1556 roce_set_field(req_a->vf_eqc_bt_idx_num, VF_RES_A_DATA_5_VF_EQC_NUM_M,
1557 VF_RES_A_DATA_5_VF_EQC_NUM_S, HNS_ROCE_VF_EQC_NUM);
1558
1559 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_IDX_M,
1560 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
1561 roce_set_field(req_b->vf_smac_idx_num, VF_RES_B_DATA_1_VF_SMAC_NUM_M,
1562 VF_RES_B_DATA_1_VF_SMAC_NUM_S, HNS_ROCE_VF_SMAC_NUM);
1563
1564 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_IDX_M,
1565 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
1566 roce_set_field(req_b->vf_sgid_idx_num, VF_RES_B_DATA_2_VF_SGID_NUM_M,
1567 VF_RES_B_DATA_2_VF_SGID_NUM_S, HNS_ROCE_VF_SGID_NUM);
1568
1569 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_QID_IDX_M,
1570 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
1571 roce_set_field(req_b->vf_qid_idx_sl_num, VF_RES_B_DATA_3_VF_SL_NUM_M,
1572 VF_RES_B_DATA_3_VF_SL_NUM_S, HNS_ROCE_VF_SL_NUM);
1573
1574 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M,
1575 VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S, 0);
1576 roce_set_field(req_b->vf_sccc_idx_num, VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M,
1577 VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S,
1578 HNS_ROCE_VF_SCCC_BT_NUM);
1579
cfc85f3e
WHX		 1580 return hns_roce_cmq_send(hr_dev, desc, 2);
1581}
1582
a81fba28
WHX		 1583static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
1584{
1585 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
1586 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
1587 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
1588 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
6a157f7d 1589 u8 sccc_hop_num = hr_dev->caps.sccc_hop_num;
a81fba28
WHX		 1590 struct hns_roce_cfg_bt_attr *req;
1591 struct hns_roce_cmq_desc desc;
1592
1593 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
1594 req = (struct hns_roce_cfg_bt_attr *)desc.data;
1595 memset(req, 0, sizeof(*req));
1596
1597 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
1598 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
5e6e78db 1599 hr_dev->caps.qpc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1600 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
1601 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
5e6e78db 1602 hr_dev->caps.qpc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1603 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
1604 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
1605 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
1606
1607 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
1608 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
5e6e78db 1609 hr_dev->caps.srqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1610 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
1611 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
5e6e78db 1612 hr_dev->caps.srqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1613 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
1614 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
1615 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
1616
1617 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
1618 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
5e6e78db 1619 hr_dev->caps.cqc_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1620 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
1621 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
5e6e78db 1622 hr_dev->caps.cqc_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1623 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
1624 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
1625 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
1626
1627 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
1628 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
5e6e78db 1629 hr_dev->caps.mpt_ba_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1630 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
1631 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
5e6e78db 1632 hr_dev->caps.mpt_buf_pg_sz + PG_SHIFT_OFFSET);
a81fba28
WHX		 1633 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
1634 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
1635 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
1636
6a157f7d
YL		 1637 roce_set_field(req->vf_sccc_cfg,
1638 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_M,
1639 CFG_BT_ATTR_DATA_4_VF_SCCC_BA_PGSZ_S,
1640 hr_dev->caps.sccc_ba_pg_sz + PG_SHIFT_OFFSET);
1641 roce_set_field(req->vf_sccc_cfg,
1642 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_M,
1643 CFG_BT_ATTR_DATA_4_VF_SCCC_BUF_PGSZ_S,
1644 hr_dev->caps.sccc_buf_pg_sz + PG_SHIFT_OFFSET);
1645 roce_set_field(req->vf_sccc_cfg,
1646 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_M,
1647 CFG_BT_ATTR_DATA_4_VF_SCCC_HOPNUM_S,
1648 sccc_hop_num ==
1649 HNS_ROCE_HOP_NUM_0 ? 0 : sccc_hop_num);
1650
a81fba28
WHX		 1651 return hns_roce_cmq_send(hr_dev, &desc, 1);
1652}
1653
ba6bb7e9
LO		 1654static void set_default_caps(struct hns_roce_dev *hr_dev)
1655{
1656 struct hns_roce_caps *caps = &hr_dev->caps;
1657
1658 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
1659 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
1660 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
1661 caps->num_srqs = HNS_ROCE_V2_MAX_SRQ_NUM;
1662 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1663 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
1664 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
1665 caps->max_extend_sg = HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;
1666 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
1667 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
1668 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
1669 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
1670 caps->num_aeq_vectors = HNS_ROCE_V2_AEQE_VEC_NUM;
1671 caps->num_comp_vectors = HNS_ROCE_V2_COMP_VEC_NUM;
1672 caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;
1673 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
1674 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1675 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1676 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1677 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1678 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
1679 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
1680 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
1681 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
1682 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
1683 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
1684 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
1685 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
7db82697 1686 caps->trrl_entry_sz = HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;
ba6bb7e9
LO		 1687 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
1688 caps->srqc_entry_sz = HNS_ROCE_V2_SRQC_ENTRY_SZ;
1689 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
1690 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1691 caps->idx_entry_sz = HNS_ROCE_V2_IDX_ENTRY_SZ;
1692 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
1693 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
1694 caps->reserved_lkey = 0;
1695 caps->reserved_pds = 0;
1696 caps->reserved_mrws = 1;
1697 caps->reserved_uars = 0;
1698 caps->reserved_cqs = 0;
1699 caps->reserved_srqs = 0;
1700 caps->reserved_qps = HNS_ROCE_V2_RSV_QPS;
1701
1702 caps->qpc_ba_pg_sz = 0;
1703 caps->qpc_buf_pg_sz = 0;
1704 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1705 caps->srqc_ba_pg_sz = 0;
1706 caps->srqc_buf_pg_sz = 0;
1707 caps->srqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1708 caps->cqc_ba_pg_sz = 0;
1709 caps->cqc_buf_pg_sz = 0;
1710 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1711 caps->mpt_ba_pg_sz = 0;
1712 caps->mpt_buf_pg_sz = 0;
1713 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
1714 caps->mtt_ba_pg_sz = 0;
1715 caps->mtt_buf_pg_sz = 0;
1716 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
1717 caps->wqe_sq_hop_num = HNS_ROCE_SQWQE_HOP_NUM;
1718 caps->wqe_sge_hop_num = HNS_ROCE_EXT_SGE_HOP_NUM;
1719 caps->wqe_rq_hop_num = HNS_ROCE_RQWQE_HOP_NUM;
1720 caps->cqe_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
1721 caps->cqe_buf_pg_sz = 0;
1722 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
1723 caps->srqwqe_ba_pg_sz = 0;
1724 caps->srqwqe_buf_pg_sz = 0;
1725 caps->srqwqe_hop_num = HNS_ROCE_SRQWQE_HOP_NUM;
1726 caps->idx_ba_pg_sz = 0;
1727 caps->idx_buf_pg_sz = 0;
1728 caps->idx_hop_num = HNS_ROCE_IDX_HOP_NUM;
1729 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
1730
1731 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
1732 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |
1733 HNS_ROCE_CAP_FLAG_RQ_INLINE |
1734 HNS_ROCE_CAP_FLAG_RECORD_DB |
1735 HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
1736
1737 caps->pkey_table_len[0] = 1;
1738 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
1739 caps->ceqe_depth = HNS_ROCE_V2_COMP_EQE_NUM;
1740 caps->aeqe_depth = HNS_ROCE_V2_ASYNC_EQE_NUM;
1741 caps->local_ca_ack_delay = 0;
1742 caps->max_mtu = IB_MTU_4096;
1743
1744 caps->max_srq_wrs = HNS_ROCE_V2_MAX_SRQ_WR;
1745 caps->max_srq_sges = HNS_ROCE_V2_MAX_SRQ_SGE;
1746
dfaf2854 1747 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
ba6bb7e9
LO		 1748 caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |
1749 HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |
1750 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL;
1751
1752 caps->num_qpc_timer = HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
1753 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1754 caps->qpc_timer_ba_pg_sz = 0;
1755 caps->qpc_timer_buf_pg_sz = 0;
1756 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1757 caps->num_cqc_timer = HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
1758 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1759 caps->cqc_timer_ba_pg_sz = 0;
1760 caps->cqc_timer_buf_pg_sz = 0;
1761 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
1762
1763 caps->sccc_entry_sz = HNS_ROCE_V2_SCCC_ENTRY_SZ;
1764 caps->sccc_ba_pg_sz = 0;
1765 caps->sccc_buf_pg_sz = 0;
1766 caps->sccc_hop_num = HNS_ROCE_SCCC_HOP_NUM;
1767 }
1768}
1769
1770static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
1771 int *buf_page_size, int *bt_page_size, u32 hem_type)
1772{
1773 u64 obj_per_chunk;
1774 int bt_chunk_size = 1 << PAGE_SHIFT;
1775 int buf_chunk_size = 1 << PAGE_SHIFT;
1776 int obj_per_chunk_default = buf_chunk_size / obj_size;
1777
1778 *buf_page_size = 0;
1779 *bt_page_size = 0;
1780
1781 switch (hop_num) {
1782 case 3:
1783 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1784 (bt_chunk_size / BA_BYTE_LEN) *
1785 (bt_chunk_size / BA_BYTE_LEN) *
1786 obj_per_chunk_default;
1787 break;
1788 case 2:
1789 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1790 (bt_chunk_size / BA_BYTE_LEN) *
1791 obj_per_chunk_default;
1792 break;
1793 case 1:
1794 obj_per_chunk = ctx_bt_num * (bt_chunk_size / BA_BYTE_LEN) *
1795 obj_per_chunk_default;
1796 break;
1797 case HNS_ROCE_HOP_NUM_0:
1798 obj_per_chunk = ctx_bt_num * obj_per_chunk_default;
1799 break;
1800 default:
1801 pr_err("Table %d not support hop_num = %d!\n", hem_type,
1802 hop_num);
1803 return;
1804 }
1805
1806 if (hem_type >= HEM_TYPE_MTT)
1807 *bt_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1808 else
1809 *buf_page_size = ilog2(DIV_ROUND_UP(obj_num, obj_per_chunk));
1810}
1811
1812static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
1813{
1814 struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
1815 struct hns_roce_caps *caps = &hr_dev->caps;
1816 struct hns_roce_query_pf_caps_a *resp_a;
1817 struct hns_roce_query_pf_caps_b *resp_b;
1818 struct hns_roce_query_pf_caps_c *resp_c;
1819 struct hns_roce_query_pf_caps_d *resp_d;
1820 struct hns_roce_query_pf_caps_e *resp_e;
1821 int ctx_hop_num;
1822 int pbl_hop_num;
1823 int ret;
1824 int i;
1825
1826 for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
1827 hns_roce_cmq_setup_basic_desc(&desc[i],
1828 HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,
1829 true);
1830 if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))
1831 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1832 else
1833 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
1834 }
1835
1836 ret = hns_roce_cmq_send(hr_dev, desc, HNS_ROCE_QUERY_PF_CAPS_CMD_NUM);
1837 if (ret)
1838 return ret;
1839
1840 resp_a = (struct hns_roce_query_pf_caps_a *)desc[0].data;
1841 resp_b = (struct hns_roce_query_pf_caps_b *)desc[1].data;
1842 resp_c = (struct hns_roce_query_pf_caps_c *)desc[2].data;
1843 resp_d = (struct hns_roce_query_pf_caps_d *)desc[3].data;
1844 resp_e = (struct hns_roce_query_pf_caps_e *)desc[4].data;
1845
1846 caps->local_ca_ack_delay = resp_a->local_ca_ack_delay;
1847 caps->max_sq_sg = le16_to_cpu(resp_a->max_sq_sg);
1848 caps->max_sq_inline = le16_to_cpu(resp_a->max_sq_inline);
1849 caps->max_rq_sg = le16_to_cpu(resp_a->max_rq_sg);
1850 caps->max_extend_sg = le32_to_cpu(resp_a->max_extend_sg);
1851 caps->num_qpc_timer = le16_to_cpu(resp_a->num_qpc_timer);
1852 caps->num_cqc_timer = le16_to_cpu(resp_a->num_cqc_timer);
1853 caps->max_srq_sges = le16_to_cpu(resp_a->max_srq_sges);
1854 caps->num_aeq_vectors = resp_a->num_aeq_vectors;
1855 caps->num_other_vectors = resp_a->num_other_vectors;
1856 caps->max_sq_desc_sz = resp_a->max_sq_desc_sz;
1857 caps->max_rq_desc_sz = resp_a->max_rq_desc_sz;
1858 caps->max_srq_desc_sz = resp_a->max_srq_desc_sz;
1859 caps->cq_entry_sz = resp_a->cq_entry_sz;
1860
1861 caps->mtpt_entry_sz = resp_b->mtpt_entry_sz;
1862 caps->irrl_entry_sz = resp_b->irrl_entry_sz;
1863 caps->trrl_entry_sz = resp_b->trrl_entry_sz;
1864 caps->cqc_entry_sz = resp_b->cqc_entry_sz;
1865 caps->srqc_entry_sz = resp_b->srqc_entry_sz;
1866 caps->idx_entry_sz = resp_b->idx_entry_sz;
1867 caps->sccc_entry_sz = resp_b->scc_ctx_entry_sz;
1868 caps->max_mtu = resp_b->max_mtu;
1869 caps->qpc_entry_sz = le16_to_cpu(resp_b->qpc_entry_sz);
1870 caps->min_cqes = resp_b->min_cqes;
1871 caps->min_wqes = resp_b->min_wqes;
1872 caps->page_size_cap = le32_to_cpu(resp_b->page_size_cap);
1873 caps->pkey_table_len[0] = resp_b->pkey_table_len;
1874 caps->phy_num_uars = resp_b->phy_num_uars;
1875 ctx_hop_num = resp_b->ctx_hop_num;
1876 pbl_hop_num = resp_b->pbl_hop_num;
1877
1878 caps->num_pds = 1 << roce_get_field(resp_c->cap_flags_num_pds,
1879 V2_QUERY_PF_CAPS_C_NUM_PDS_M,
1880 V2_QUERY_PF_CAPS_C_NUM_PDS_S);
1881 caps->flags = roce_get_field(resp_c->cap_flags_num_pds,
1882 V2_QUERY_PF_CAPS_C_CAP_FLAGS_M,
1883 V2_QUERY_PF_CAPS_C_CAP_FLAGS_S);
30661322
WL		 1884 caps->flags |= le16_to_cpu(resp_d->cap_flags_ex) <<
1885 HNS_ROCE_CAP_FLAGS_EX_SHIFT;
1886
ba6bb7e9
LO		 1887 caps->num_cqs = 1 << roce_get_field(resp_c->max_gid_num_cqs,
1888 V2_QUERY_PF_CAPS_C_NUM_CQS_M,
1889 V2_QUERY_PF_CAPS_C_NUM_CQS_S);
1890 caps->gid_table_len[0] = roce_get_field(resp_c->max_gid_num_cqs,
1891 V2_QUERY_PF_CAPS_C_MAX_GID_M,
1892 V2_QUERY_PF_CAPS_C_MAX_GID_S);
1893 caps->max_cqes = 1 << roce_get_field(resp_c->cq_depth,
1894 V2_QUERY_PF_CAPS_C_CQ_DEPTH_M,
1895 V2_QUERY_PF_CAPS_C_CQ_DEPTH_S);
1896 caps->num_mtpts = 1 << roce_get_field(resp_c->num_mrws,
1897 V2_QUERY_PF_CAPS_C_NUM_MRWS_M,
1898 V2_QUERY_PF_CAPS_C_NUM_MRWS_S);
1899 caps->num_qps = 1 << roce_get_field(resp_c->ord_num_qps,
1900 V2_QUERY_PF_CAPS_C_NUM_QPS_M,
1901 V2_QUERY_PF_CAPS_C_NUM_QPS_S);
1902 caps->max_qp_init_rdma = roce_get_field(resp_c->ord_num_qps,
1903 V2_QUERY_PF_CAPS_C_MAX_ORD_M,
1904 V2_QUERY_PF_CAPS_C_MAX_ORD_S);
1905 caps->max_qp_dest_rdma = caps->max_qp_init_rdma;
1906 caps->max_wqes = 1 << le16_to_cpu(resp_c->sq_depth);
1907 caps->num_srqs = 1 << roce_get_field(resp_d->wq_hop_num_max_srqs,
1908 V2_QUERY_PF_CAPS_D_NUM_SRQS_M,
1909 V2_QUERY_PF_CAPS_D_NUM_SRQS_S);
1910 caps->max_srq_wrs = 1 << le16_to_cpu(resp_d->srq_depth);
1911 caps->ceqe_depth = 1 << roce_get_field(resp_d->num_ceqs_ceq_depth,
1912 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_M,
1913 V2_QUERY_PF_CAPS_D_CEQ_DEPTH_S);
1914 caps->num_comp_vectors = roce_get_field(resp_d->num_ceqs_ceq_depth,
1915 V2_QUERY_PF_CAPS_D_NUM_CEQS_M,
1916 V2_QUERY_PF_CAPS_D_NUM_CEQS_S);
1917 caps->aeqe_depth = 1 << roce_get_field(resp_d->arm_st_aeq_depth,
1918 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_M,
1919 V2_QUERY_PF_CAPS_D_AEQ_DEPTH_S);
1920 caps->default_aeq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1921 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_M,
1922 V2_QUERY_PF_CAPS_D_AEQ_ARM_ST_S);
1923 caps->default_ceq_arm_st = roce_get_field(resp_d->arm_st_aeq_depth,
1924 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_M,
1925 V2_QUERY_PF_CAPS_D_CEQ_ARM_ST_S);
1926 caps->reserved_pds = roce_get_field(resp_d->num_uars_rsv_pds,
1927 V2_QUERY_PF_CAPS_D_RSV_PDS_M,
1928 V2_QUERY_PF_CAPS_D_RSV_PDS_S);
1929 caps->num_uars = 1 << roce_get_field(resp_d->num_uars_rsv_pds,
1930 V2_QUERY_PF_CAPS_D_NUM_UARS_M,
1931 V2_QUERY_PF_CAPS_D_NUM_UARS_S);
1932 caps->reserved_qps = roce_get_field(resp_d->rsv_uars_rsv_qps,
1933 V2_QUERY_PF_CAPS_D_RSV_QPS_M,
1934 V2_QUERY_PF_CAPS_D_RSV_QPS_S);
1935 caps->reserved_uars = roce_get_field(resp_d->rsv_uars_rsv_qps,
1936 V2_QUERY_PF_CAPS_D_RSV_UARS_M,
1937 V2_QUERY_PF_CAPS_D_RSV_UARS_S);
1938 caps->reserved_mrws = roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1939 V2_QUERY_PF_CAPS_E_RSV_MRWS_M,
1940 V2_QUERY_PF_CAPS_E_RSV_MRWS_S);
1941 caps->chunk_sz = 1 << roce_get_field(resp_e->chunk_size_shift_rsv_mrws,
1942 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_M,
1943 V2_QUERY_PF_CAPS_E_CHUNK_SIZE_SHIFT_S);
1944 caps->reserved_cqs = roce_get_field(resp_e->rsv_cqs,
1945 V2_QUERY_PF_CAPS_E_RSV_CQS_M,
1946 V2_QUERY_PF_CAPS_E_RSV_CQS_S);
1947 caps->reserved_srqs = roce_get_field(resp_e->rsv_srqs,
1948 V2_QUERY_PF_CAPS_E_RSV_SRQS_M,
1949 V2_QUERY_PF_CAPS_E_RSV_SRQS_S);
1950 caps->reserved_lkey = roce_get_field(resp_e->rsv_lkey,
1951 V2_QUERY_PF_CAPS_E_RSV_LKEYS_M,
1952 V2_QUERY_PF_CAPS_E_RSV_LKEYS_S);
1953 caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);
1954 caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);
1955 caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);
1956 caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);
1957
1958 caps->qpc_timer_entry_sz = HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ;
1959 caps->cqc_timer_entry_sz = HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ;
1960 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
1961 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
1962 caps->mtt_ba_pg_sz = 0;
1963 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
1964 caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
1965 caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
1966
1967 caps->qpc_hop_num = ctx_hop_num;
1968 caps->srqc_hop_num = ctx_hop_num;
1969 caps->cqc_hop_num = ctx_hop_num;
1970 caps->mpt_hop_num = ctx_hop_num;
1971 caps->mtt_hop_num = pbl_hop_num;
1972 caps->cqe_hop_num = pbl_hop_num;
1973 caps->srqwqe_hop_num = pbl_hop_num;
1974 caps->idx_hop_num = pbl_hop_num;
1975 caps->wqe_sq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1976 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_M,
1977 V2_QUERY_PF_CAPS_D_SQWQE_HOP_NUM_S);
1978 caps->wqe_sge_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1979 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_M,
1980 V2_QUERY_PF_CAPS_D_EX_SGE_HOP_NUM_S);
1981 caps->wqe_rq_hop_num = roce_get_field(resp_d->wq_hop_num_max_srqs,
1982 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_M,
1983 V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
1984
1985 calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
1986 caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
1987 HEM_TYPE_QPC);
1988 calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
1989 caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
1990 HEM_TYPE_MTPT);
1991 calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
1992 caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
1993 HEM_TYPE_CQC);
1994 calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num,
1995 caps->srqc_bt_num, &caps->srqc_buf_pg_sz,
1996 &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC);
1997
dfaf2854 1998 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
ba6bb7e9
LO		 1999 caps->sccc_hop_num = ctx_hop_num;
2000 caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2001 caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
2002
2003 calc_pg_sz(caps->num_qps, caps->sccc_entry_sz,
2004 caps->sccc_hop_num, caps->sccc_bt_num,
2005 &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,
2006 HEM_TYPE_SCCC);
2007 calc_pg_sz(caps->num_cqc_timer, caps->cqc_timer_entry_sz,
2008 caps->cqc_timer_hop_num, caps->cqc_timer_bt_num,
2009 &caps->cqc_timer_buf_pg_sz,
2010 &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
2011 }
2012
2013 calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num,
2014 1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
2015 calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
2016 caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
2017 &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
2018 calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num,
2019 1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
2020
2021 return 0;
2022}
2023
cfc85f3e
WHX		 2024static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
2025{
2026 struct hns_roce_caps *caps = &hr_dev->caps;
2027 int ret;
2028
2029 ret = hns_roce_cmq_query_hw_info(hr_dev);
3a63c964
LO		 2030 if (ret) {
2031 dev_err(hr_dev->dev, "Query hardware version fail, ret = %d.\n",
2032 ret);
2033 return ret;
2034 }
2035
2036 ret = hns_roce_query_fw_ver(hr_dev);
cfc85f3e
WHX		 2037 if (ret) {
2038 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
2039 ret);
2040 return ret;
2041 }
2042
2043 ret = hns_roce_config_global_param(hr_dev);
2044 if (ret) {
2045 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
2046 ret);
2349fdd4 2047 return ret;
cfc85f3e
WHX		 2048 }
2049
2050 /* Get pf resource owned by every pf */
2051 ret = hns_roce_query_pf_resource(hr_dev);
2052 if (ret) {
2053 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
2054 ret);
2055 return ret;
2056 }
2057
dfaf2854 2058 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B) {
0e40dc2f
YL		 2059 ret = hns_roce_query_pf_timer_resource(hr_dev);
2060 if (ret) {
2061 dev_err(hr_dev->dev,
2062 "Query pf timer resource fail, ret = %d.\n",
2063 ret);
2064 return ret;
2065 }
cfc85f3e 2066
0c1c3880
LO		 2067 ret = hns_roce_set_vf_switch_param(hr_dev, 0);
2068 if (ret) {
2069 dev_err(hr_dev->dev,
2070 "Set function switch param fail, ret = %d.\n",
2071 ret);
2072 return ret;
2073 }
2074 }
3a63c964
LO		 2075
2076 hr_dev->vendor_part_id = hr_dev->pci_dev->device;
2077 hr_dev->sys_image_guid = be64_to_cpu(hr_dev->ib_dev.node_guid);
cfc85f3e 2078
80a78570 2079 caps->pbl_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_16K;
ff795f71
WHX		 2080 caps->pbl_buf_pg_sz = 0;
2081 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
a5073d60
YL		 2082 caps->eqe_ba_pg_sz = 0;
2083 caps->eqe_buf_pg_sz = 0;
2084 caps->eqe_hop_num = HNS_ROCE_EQE_HOP_NUM;
6b63597d 2085 caps->tsq_buf_pg_sz = 0;
aa84fa18 2086
80a78570
LO		 2087 ret = hns_roce_query_pf_caps(hr_dev);
2088 if (ret)
2089 set_default_caps(hr_dev);
384f8818 2090
99e713f8
LO		 2091 ret = hns_roce_alloc_vf_resource(hr_dev);
2092 if (ret) {
2093 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
2094 ret);
2095 return ret;
2096 }
2097
a81fba28
WHX		 2098 ret = hns_roce_v2_set_bt(hr_dev);
2099 if (ret)
2100 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
2101 ret);
2102
2103 return ret;
cfc85f3e
WHX		 2104}
2105
6b63597d 2106static int hns_roce_config_link_table(struct hns_roce_dev *hr_dev,
2107 enum hns_roce_link_table_type type)
2108{
2109 struct hns_roce_cmq_desc desc[2];
2110 struct hns_roce_cfg_llm_a *req_a =
2111 (struct hns_roce_cfg_llm_a *)desc[0].data;
2112 struct hns_roce_cfg_llm_b *req_b =
2113 (struct hns_roce_cfg_llm_b *)desc[1].data;
2114 struct hns_roce_v2_priv *priv = hr_dev->priv;
2115 struct hns_roce_link_table *link_tbl;
2116 struct hns_roce_link_table_entry *entry;
2117 enum hns_roce_opcode_type opcode;
2118 u32 page_num;
2119 int i;
2120
2121 switch (type) {
2122 case TSQ_LINK_TABLE:
2123 link_tbl = &priv->tsq;
2124 opcode = HNS_ROCE_OPC_CFG_EXT_LLM;
2125 break;
ded58ff9 2126 case TPQ_LINK_TABLE:
2127 link_tbl = &priv->tpq;
2128 opcode = HNS_ROCE_OPC_CFG_TMOUT_LLM;
2129 break;
6b63597d 2130 default:
2131 return -EINVAL;
2132 }
2133
2134 page_num = link_tbl->npages;
2135 entry = link_tbl->table.buf;
6b63597d 2136
2137 for (i = 0; i < 2; i++) {
2138 hns_roce_cmq_setup_basic_desc(&desc[i], opcode, false);
2139
2140 if (i == 0)
2141 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
2142 else
2143 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
6b63597d 2144 }
9976ea27
LO		 2145
2146 req_a->base_addr_l = cpu_to_le32(link_tbl->table.map & 0xffffffff);
2147 req_a->base_addr_h = cpu_to_le32(link_tbl->table.map >> 32);
2148 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_DEPTH_M,
2149 CFG_LLM_QUE_DEPTH_S, link_tbl->npages);
2150 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_QUE_PGSZ_M,
2151 CFG_LLM_QUE_PGSZ_S, link_tbl->pg_sz);
60262b10
LO		 2152 roce_set_field(req_a->depth_pgsz_init_en, CFG_LLM_INIT_EN_M,
2153 CFG_LLM_INIT_EN_S, 1);
9976ea27
LO		 2154 req_a->head_ba_l = cpu_to_le32(entry[0].blk_ba0);
2155 req_a->head_ba_h_nxtptr = cpu_to_le32(entry[0].blk_ba1_nxt_ptr);
2156 roce_set_field(req_a->head_ptr, CFG_LLM_HEAD_PTR_M, CFG_LLM_HEAD_PTR_S,
2157 0);
2158
2159 req_b->tail_ba_l = cpu_to_le32(entry[page_num - 1].blk_ba0);
2160 roce_set_field(req_b->tail_ba_h, CFG_LLM_TAIL_BA_H_M,
2161 CFG_LLM_TAIL_BA_H_S,
2162 entry[page_num - 1].blk_ba1_nxt_ptr &
2163 HNS_ROCE_LINK_TABLE_BA1_M);
2164 roce_set_field(req_b->tail_ptr, CFG_LLM_TAIL_PTR_M, CFG_LLM_TAIL_PTR_S,
2165 (entry[page_num - 2].blk_ba1_nxt_ptr &
2166 HNS_ROCE_LINK_TABLE_NXT_PTR_M) >>
2167 HNS_ROCE_LINK_TABLE_NXT_PTR_S);
6b63597d 2168
2169 return hns_roce_cmq_send(hr_dev, desc, 2);
2170}
2171
2172static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev,
2173 enum hns_roce_link_table_type type)
2174{
2175 struct hns_roce_v2_priv *priv = hr_dev->priv;
2176 struct hns_roce_link_table *link_tbl;
2177 struct hns_roce_link_table_entry *entry;
2178 struct device *dev = hr_dev->dev;
2179 u32 buf_chk_sz;
2180 dma_addr_t t;
ded58ff9 2181 int func_num = 1;
6b63597d 2182 int pg_num_a;
2183 int pg_num_b;
2184 int pg_num;
2185 int size;
2186 int i;
2187
2188 switch (type) {
2189 case TSQ_LINK_TABLE:
2190 link_tbl = &priv->tsq;
2191 buf_chk_sz = 1 << (hr_dev->caps.tsq_buf_pg_sz + PAGE_SHIFT);
2192 pg_num_a = hr_dev->caps.num_qps * 8 / buf_chk_sz;
2193 pg_num_b = hr_dev->caps.sl_num * 4 + 2;
2194 break;
ded58ff9 2195 case TPQ_LINK_TABLE:
2196 link_tbl = &priv->tpq;
2197 buf_chk_sz = 1 << (hr_dev->caps.tpq_buf_pg_sz + PAGE_SHIFT);
2198 pg_num_a = hr_dev->caps.num_cqs * 4 / buf_chk_sz;
2199 pg_num_b = 2 * 4 * func_num + 2;
2200 break;
6b63597d 2201 default:
2202 return -EINVAL;
2203 }
2204
2205 pg_num = max(pg_num_a, pg_num_b);
2206 size = pg_num * sizeof(struct hns_roce_link_table_entry);
2207
2208 link_tbl->table.buf = dma_alloc_coherent(dev, size,
2209 &link_tbl->table.map,
2210 GFP_KERNEL);
2211 if (!link_tbl->table.buf)
2212 goto out;
2213
2214 link_tbl->pg_list = kcalloc(pg_num, sizeof(*link_tbl->pg_list),
2215 GFP_KERNEL);
2216 if (!link_tbl->pg_list)
2217 goto err_kcalloc_failed;
2218
2219 entry = link_tbl->table.buf;
2220 for (i = 0; i < pg_num; ++i) {
2221 link_tbl->pg_list[i].buf = dma_alloc_coherent(dev, buf_chk_sz,
2222 &t, GFP_KERNEL);
2223 if (!link_tbl->pg_list[i].buf)
2224 goto err_alloc_buf_failed;
2225
2226 link_tbl->pg_list[i].map = t;
6b63597d 2227
bfe86035
LC		 2228 entry[i].blk_ba0 = (u32)(t >> 12);
2229 entry[i].blk_ba1_nxt_ptr = (u32)(t >> 44);
6b63597d 2230
2231 if (i < (pg_num - 1))
bfe86035
LC		 2232 entry[i].blk_ba1_nxt_ptr |=
2233 (i + 1) << HNS_ROCE_LINK_TABLE_NXT_PTR_S;
2234
6b63597d 2235 }
2236 link_tbl->npages = pg_num;
2237 link_tbl->pg_sz = buf_chk_sz;
2238
2239 return hns_roce_config_link_table(hr_dev, type);
2240
2241err_alloc_buf_failed:
2242 for (i -= 1; i >= 0; i--)
2243 dma_free_coherent(dev, buf_chk_sz,
2244 link_tbl->pg_list[i].buf,
2245 link_tbl->pg_list[i].map);
2246 kfree(link_tbl->pg_list);
2247
2248err_kcalloc_failed:
2249 dma_free_coherent(dev, size, link_tbl->table.buf,
2250 link_tbl->table.map);
2251
2252out:
2253 return -ENOMEM;
2254}
2255
2256static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev,
2257 struct hns_roce_link_table *link_tbl)
2258{
2259 struct device *dev = hr_dev->dev;
2260 int size;
2261 int i;
2262
2263 size = link_tbl->npages * sizeof(struct hns_roce_link_table_entry);
2264
2265 for (i = 0; i < link_tbl->npages; ++i)
2266 if (link_tbl->pg_list[i].buf)
2267 dma_free_coherent(dev, link_tbl->pg_sz,
2268 link_tbl->pg_list[i].buf,
2269 link_tbl->pg_list[i].map);
2270 kfree(link_tbl->pg_list);
2271
2272 dma_free_coherent(dev, size, link_tbl->table.buf,
2273 link_tbl->table.map);
2274}
2275
2276static int hns_roce_v2_init(struct hns_roce_dev *hr_dev)
2277{
ded58ff9 2278 struct hns_roce_v2_priv *priv = hr_dev->priv;
0e40dc2f
YL		 2279 int qpc_count, cqc_count;
2280 int ret, i;
6b63597d 2281
2282 /* TSQ includes SQ doorbell and ack doorbell */
2283 ret = hns_roce_init_link_table(hr_dev, TSQ_LINK_TABLE);
ded58ff9 2284 if (ret) {
6b63597d 2285 dev_err(hr_dev->dev, "TSQ init failed, ret = %d.\n", ret);
ded58ff9 2286 return ret;
2287 }
2288
2289 ret = hns_roce_init_link_table(hr_dev, TPQ_LINK_TABLE);
2290 if (ret) {
2291 dev_err(hr_dev->dev, "TPQ init failed, ret = %d.\n", ret);
2292 goto err_tpq_init_failed;
2293 }
2294
6def7de6 2295 /* Alloc memory for QPC Timer buffer space chunk */
0e40dc2f
YL		 2296 for (qpc_count = 0; qpc_count < hr_dev->caps.qpc_timer_bt_num;
2297 qpc_count++) {
2298 ret = hns_roce_table_get(hr_dev, &hr_dev->qpc_timer_table,
2299 qpc_count);
2300 if (ret) {
2301 dev_err(hr_dev->dev, "QPC Timer get failed\n");
2302 goto err_qpc_timer_failed;
2303 }
2304 }
2305
6def7de6 2306 /* Alloc memory for CQC Timer buffer space chunk */
0e40dc2f
YL		 2307 for (cqc_count = 0; cqc_count < hr_dev->caps.cqc_timer_bt_num;
2308 cqc_count++) {
2309 ret = hns_roce_table_get(hr_dev, &hr_dev->cqc_timer_table,
2310 cqc_count);
2311 if (ret) {
2312 dev_err(hr_dev->dev, "CQC Timer get failed\n");
2313 goto err_cqc_timer_failed;
2314 }
2315 }
2316
ded58ff9 2317 return 0;
2318
0e40dc2f
YL		 2319err_cqc_timer_failed:
2320 for (i = 0; i < cqc_count; i++)
2321 hns_roce_table_put(hr_dev, &hr_dev->cqc_timer_table, i);
2322
2323err_qpc_timer_failed:
2324 for (i = 0; i < qpc_count; i++)
2325 hns_roce_table_put(hr_dev, &hr_dev->qpc_timer_table, i);
2326
2327 hns_roce_free_link_table(hr_dev, &priv->tpq);
2328
ded58ff9 2329err_tpq_init_failed:
2330 hns_roce_free_link_table(hr_dev, &priv->tsq);
6b63597d 2331
2332 return ret;
2333}
2334
2335static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
2336{
2337 struct hns_roce_v2_priv *priv = hr_dev->priv;
2338
dfaf2854 2339 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B)
89a6da3c
LC		 2340 hns_roce_function_clear(hr_dev);
2341
ded58ff9 2342 hns_roce_free_link_table(hr_dev, &priv->tpq);
6b63597d 2343 hns_roce_free_link_table(hr_dev, &priv->tsq);
2344}
2345
f747b689
LO		 2346static int hns_roce_query_mbox_status(struct hns_roce_dev *hr_dev)
2347{
2348 struct hns_roce_cmq_desc desc;
2349 struct hns_roce_mbox_status *mb_st =
2350 (struct hns_roce_mbox_status *)desc.data;
2351 enum hns_roce_cmd_return_status status;
2352
2353 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_MB_ST, true);
2354
2355 status = hns_roce_cmq_send(hr_dev, &desc, 1);
2356 if (status)
2357 return status;
2358
bfe86035 2359 return le32_to_cpu(mb_st->mb_status_hw_run);
f747b689
LO		 2360}
2361
a680f2f3
WHX		 2362static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
2363{
f747b689 2364 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2365
2366 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
2367}
2368
2369static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
2370{
f747b689 2371 u32 status = hns_roce_query_mbox_status(hr_dev);
a680f2f3
WHX		 2372
2373 return status & HNS_ROCE_HW_MB_STATUS_MASK;
2374}
2375
f747b689
LO		 2376static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, u64 in_param,
2377 u64 out_param, u32 in_modifier, u8 op_modifier,
2378 u16 op, u16 token, int event)
2379{
2380 struct hns_roce_cmq_desc desc;
2381 struct hns_roce_post_mbox *mb = (struct hns_roce_post_mbox *)desc.data;
2382
2383 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_POST_MB, false);
2384
bfe86035
LC		 2385 mb->in_param_l = cpu_to_le32(in_param);
2386 mb->in_param_h = cpu_to_le32(in_param >> 32);
2387 mb->out_param_l = cpu_to_le32(out_param);
2388 mb->out_param_h = cpu_to_le32(out_param >> 32);
f747b689
LO		 2389 mb->cmd_tag = cpu_to_le32(in_modifier << 8 | op);
2390 mb->token_event_en = cpu_to_le32(event << 16 | token);
2391
2392 return hns_roce_cmq_send(hr_dev, &desc, 1);
2393}
2394
a680f2f3
WHX		 2395static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
2396 u64 out_param, u32 in_modifier, u8 op_modifier,
2397 u16 op, u16 token, int event)
2398{
2399 struct device *dev = hr_dev->dev;
a680f2f3 2400 unsigned long end;
f747b689 2401 int ret;
a680f2f3
WHX		 2402
2403 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
2404 while (hns_roce_v2_cmd_pending(hr_dev)) {
2405 if (time_after(jiffies, end)) {
2406 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
2407 (int)end);
2408 return -EAGAIN;
2409 }
2410 cond_resched();
2411 }
2412
f747b689
LO		 2413 ret = hns_roce_mbox_post(hr_dev, in_param, out_param, in_modifier,
2414 op_modifier, op, token, event);
2415 if (ret)
2416 dev_err(dev, "Post mailbox fail(%d)\n", ret);
a680f2f3 2417
f747b689 2418 return ret;
a680f2f3
WHX		 2419}
2420
2421static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
2422 unsigned long timeout)
2423{
2424 struct device *dev = hr_dev->dev;
617cf24f 2425 unsigned long end;
a680f2f3
WHX		 2426 u32 status;
2427
2428 end = msecs_to_jiffies(timeout) + jiffies;
2429 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
2430 cond_resched();
2431
2432 if (hns_roce_v2_cmd_pending(hr_dev)) {
2433 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
2434 return -ETIMEDOUT;
2435 }
2436
2437 status = hns_roce_v2_cmd_complete(hr_dev);
2438 if (status != 0x1) {
6a04aed6
WHX		 2439 if (status == CMD_RST_PRC_EBUSY)
2440 return status;
2441
a680f2f3
WHX		 2442 dev_err(dev, "mailbox status 0x%x!\n", status);
2443 return -EBUSY;
2444 }
2445
2446 return 0;
2447}
2448
4db134a3 2449static int hns_roce_config_sgid_table(struct hns_roce_dev *hr_dev,
2450 int gid_index, const union ib_gid *gid,
2451 enum hns_roce_sgid_type sgid_type)
2452{
2453 struct hns_roce_cmq_desc desc;
2454 struct hns_roce_cfg_sgid_tb *sgid_tb =
2455 (struct hns_roce_cfg_sgid_tb *)desc.data;
2456 u32 *p;
2457
2458 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SGID_TB, false);
2459
60262b10 2460 roce_set_field(sgid_tb->table_idx_rsv, CFG_SGID_TB_TABLE_IDX_M,
4db134a3 2461 CFG_SGID_TB_TABLE_IDX_S, gid_index);
60262b10 2462 roce_set_field(sgid_tb->vf_sgid_type_rsv, CFG_SGID_TB_VF_SGID_TYPE_M,
4db134a3 2463 CFG_SGID_TB_VF_SGID_TYPE_S, sgid_type);
2464
2465 p = (u32 *)&gid->raw[0];
2466 sgid_tb->vf_sgid_l = cpu_to_le32(*p);
2467
2468 p = (u32 *)&gid->raw[4];
2469 sgid_tb->vf_sgid_ml = cpu_to_le32(*p);
2470
2471 p = (u32 *)&gid->raw[8];
2472 sgid_tb->vf_sgid_mh = cpu_to_le32(*p);
2473
2474 p = (u32 *)&gid->raw[0xc];
2475 sgid_tb->vf_sgid_h = cpu_to_le32(*p);
2476
2477 return hns_roce_cmq_send(hr_dev, &desc, 1);
2478}
2479
b5ff0f61 2480static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 2481 int gid_index, const union ib_gid *gid,
b5ff0f61 2482 const struct ib_gid_attr *attr)
7afddafa 2483{
b5ff0f61 2484 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
4db134a3 2485 int ret;
7afddafa 2486
b5ff0f61
WHX		 2487 if (!gid || !attr)
2488 return -EINVAL;
2489
2490 if (attr->gid_type == IB_GID_TYPE_ROCE)
2491 sgid_type = GID_TYPE_FLAG_ROCE_V1;
2492
2493 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
2494 if (ipv6_addr_v4mapped((void *)gid))
2495 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
2496 else
2497 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
2498 }
2499
4db134a3 2500 ret = hns_roce_config_sgid_table(hr_dev, gid_index, gid, sgid_type);
2501 if (ret)
ae1c6148
LO		 2502 ibdev_err(&hr_dev->ib_dev,
2503 "failed to configure sgid table, ret = %d!\n",
2504 ret);
b5ff0f61 2505
4db134a3 2506 return ret;
7afddafa
WHX		 2507}
2508
a74dc41d
WHX		 2509static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
2510 u8 *addr)
7afddafa 2511{
e8e8b652 2512 struct hns_roce_cmq_desc desc;
2513 struct hns_roce_cfg_smac_tb *smac_tb =
2514 (struct hns_roce_cfg_smac_tb *)desc.data;
7afddafa
WHX		 2515 u16 reg_smac_h;
2516 u32 reg_smac_l;
e8e8b652 2517
2518 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_SMAC_TB, false);
7afddafa
WHX		 2519
2520 reg_smac_l = *(u32 *)(&addr[0]);
e8e8b652 2521 reg_smac_h = *(u16 *)(&addr[4]);
7afddafa 2522
375898e8 2523 roce_set_field(smac_tb->tb_idx_rsv, CFG_SMAC_TB_IDX_M,
e8e8b652 2524 CFG_SMAC_TB_IDX_S, phy_port);
375898e8 2525 roce_set_field(smac_tb->vf_smac_h_rsv, CFG_SMAC_TB_VF_SMAC_H_M,
e8e8b652 2526 CFG_SMAC_TB_VF_SMAC_H_S, reg_smac_h);
bfe86035 2527 smac_tb->vf_smac_l = cpu_to_le32(reg_smac_l);
a74dc41d 2528
e8e8b652 2529 return hns_roce_cmq_send(hr_dev, &desc, 1);
7afddafa
WHX		 2530}
2531
98a61519
YL		 2532static int set_mtpt_pbl(struct hns_roce_dev *hr_dev,
2533 struct hns_roce_v2_mpt_entry *mpt_entry,
ca088320 2534 struct hns_roce_mr *mr)
3958cc56 2535{
9b2cf76c
XW		 2536 u64 pages[HNS_ROCE_V2_MAX_INNER_MTPT_NUM] = { 0 };
2537 struct ib_device *ibdev = &hr_dev->ib_dev;
2538 dma_addr_t pbl_ba;
2539 int i, count;
2540
2541 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
2542 ARRAY_SIZE(pages), &pbl_ba);
2543 if (count < 1) {
2544 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.\n",
2545 count);
2546 return -ENOBUFS;
2547 }
3958cc56 2548
9b2cf76c
XW		 2549 /* Aligned to the hardware address access unit */
2550 for (i = 0; i < count; i++)
2551 pages[i] >>= 6;
2552
2553 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
2554 mpt_entry->pbl_ba_l = cpu_to_le32(pbl_ba >> 3);
ca088320
YL		 2555 roce_set_field(mpt_entry->byte_48_mode_ba,
2556 V2_MPT_BYTE_48_PBL_BA_H_M, V2_MPT_BYTE_48_PBL_BA_H_S,
9b2cf76c 2557 upper_32_bits(pbl_ba >> 3));
ca088320 2558
ca088320
YL		 2559 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
2560 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
2561 V2_MPT_BYTE_56_PA0_H_S, upper_32_bits(pages[0]));
2562
2563 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
2564 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
2565 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
2566 roce_set_field(mpt_entry->byte_64_buf_pa1,
2567 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2568 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
9b2cf76c 2569 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
ca088320
YL		 2570
2571 return 0;
2572}
2573
98a61519
YL		 2574static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev,
2575 void *mb_buf, struct hns_roce_mr *mr,
ca088320
YL		 2576 unsigned long mtpt_idx)
2577{
2578 struct hns_roce_v2_mpt_entry *mpt_entry;
2579 int ret;
2580
3958cc56
WHX		 2581 mpt_entry = mb_buf;
2582 memset(mpt_entry, 0, sizeof(*mpt_entry));
2583
2584 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2585 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2586 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2587 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
2588 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
2589 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2590 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
5e6e78db 2591 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
9b2cf76c 2592 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
3958cc56
WHX		 2593 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2594 V2_MPT_BYTE_4_PD_S, mr->pd);
3958cc56
WHX		 2595
2596 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
82342e49 2597 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 0);
e93df010 2598 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
3958cc56
WHX		 2599 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
2600 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
384f8818
LO		 2601 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S,
2602 mr->access & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
3958cc56
WHX		 2603 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
2604 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
2605 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
2606 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
2607 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
2608 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
3958cc56
WHX		 2609
2610 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
2611 mr->type == MR_TYPE_MR ? 0 : 1);
85e0274d 2612 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_INNER_PA_VLD_S,
2613 1);
3958cc56
WHX		 2614
2615 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
2616 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
2617 mpt_entry->lkey = cpu_to_le32(mr->key);
2618 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
2619 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
2620
2621 if (mr->type == MR_TYPE_DMA)
2622 return 0;
2623
98a61519 2624 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
3958cc56 2625
ca088320 2626 return ret;
3958cc56
WHX		 2627}
2628
a2c80b7b
WHX		 2629static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
2630 struct hns_roce_mr *mr, int flags,
2631 u32 pdn, int mr_access_flags, u64 iova,
2632 u64 size, void *mb_buf)
2633{
2634 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
ca088320 2635 int ret = 0;
a2c80b7b 2636
ab22bf05
YL		 2637 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2638 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
2639
a2c80b7b
WHX		 2640 if (flags & IB_MR_REREG_PD) {
2641 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2642 V2_MPT_BYTE_4_PD_S, pdn);
2643 mr->pd = pdn;
2644 }
2645
2646 if (flags & IB_MR_REREG_ACCESS) {
2647 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
2648 V2_MPT_BYTE_8_BIND_EN_S,
2649 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
2650 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
ca088320
YL		 2651 V2_MPT_BYTE_8_ATOMIC_EN_S,
2652 mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0);
a2c80b7b 2653 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
ca088320 2654 mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0);
a2c80b7b 2655 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
ca088320 2656 mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0);
a2c80b7b 2657 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
ca088320 2658 mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0);
a2c80b7b
WHX		 2659 }
2660
2661 if (flags & IB_MR_REREG_TRANS) {
2662 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
2663 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
2664 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
2665 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
2666
a2c80b7b
WHX		 2667 mr->iova = iova;
2668 mr->size = size;
ca088320 2669
98a61519 2670 ret = set_mtpt_pbl(hr_dev, mpt_entry, mr);
a2c80b7b
WHX		 2671 }
2672
ca088320 2673 return ret;
a2c80b7b
WHX		 2674}
2675
98a61519
YL		 2676static int hns_roce_v2_frmr_write_mtpt(struct hns_roce_dev *hr_dev,
2677 void *mb_buf, struct hns_roce_mr *mr)
68a997c5 2678{
9b2cf76c 2679 struct ib_device *ibdev = &hr_dev->ib_dev;
68a997c5 2680 struct hns_roce_v2_mpt_entry *mpt_entry;
9b2cf76c 2681 dma_addr_t pbl_ba = 0;
68a997c5
YL		 2682
2683 mpt_entry = mb_buf;
2684 memset(mpt_entry, 0, sizeof(*mpt_entry));
2685
9b2cf76c
XW		 2686 if (hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, NULL, 0, &pbl_ba) < 0) {
2687 ibdev_err(ibdev, "failed to find frmr mtr.\n");
2688 return -ENOBUFS;
2689 }
2690
68a997c5
YL		 2691 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2692 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2693 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
2694 V2_MPT_BYTE_4_PBL_HOP_NUM_S, 1);
2695 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2696 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2697 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
9b2cf76c 2698 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.ba_pg_shift));
68a997c5
YL		 2699 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2700 V2_MPT_BYTE_4_PD_S, mr->pd);
2701
2702 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 1);
2703 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2704 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2705
2706 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_FRE_S, 1);
2707 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2708 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 0);
2709 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2710
9b2cf76c 2711 mpt_entry->pbl_size = cpu_to_le32(mr->npages);
68a997c5 2712
9b2cf76c 2713 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(pbl_ba >> 3));
68a997c5
YL		 2714 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
2715 V2_MPT_BYTE_48_PBL_BA_H_S,
9b2cf76c 2716 upper_32_bits(pbl_ba >> 3));
68a997c5
YL		 2717
2718 roce_set_field(mpt_entry->byte_64_buf_pa1,
2719 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2720 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
9b2cf76c 2721 to_hr_hw_page_shift(mr->pbl_mtr.hem_cfg.buf_pg_shift));
68a997c5
YL		 2722
2723 return 0;
2724}
2725
c7c28191
YL		 2726static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw)
2727{
2728 struct hns_roce_v2_mpt_entry *mpt_entry;
2729
2730 mpt_entry = mb_buf;
2731 memset(mpt_entry, 0, sizeof(*mpt_entry));
2732
2733 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
2734 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_FREE);
2735 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
2736 V2_MPT_BYTE_4_PD_S, mw->pdn);
60262b10 2737 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
c7c28191 2738 V2_MPT_BYTE_4_PBL_HOP_NUM_S,
60262b10
LO		 2739 mw->pbl_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 :
2740 mw->pbl_hop_num);
c7c28191
YL		 2741 roce_set_field(mpt_entry->byte_4_pd_hop_st,
2742 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
2743 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S,
2744 mw->pbl_ba_pg_sz + PG_SHIFT_OFFSET);
2745
2746 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
2747 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 1);
2748
2749 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S, 0);
2750 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_MR_MW_S, 1);
2751 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BPD_S, 1);
2752 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_BQP_S,
2753 mw->ibmw.type == IB_MW_TYPE_1 ? 0 : 1);
2754
2755 roce_set_field(mpt_entry->byte_64_buf_pa1,
2756 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
2757 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S,
2758 mw->pbl_buf_pg_sz + PG_SHIFT_OFFSET);
2759
2760 mpt_entry->lkey = cpu_to_le32(mw->rkey);
2761
2762 return 0;
2763}
2764
93aa2187
WHX		 2765static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2766{
744b7bdf
XW		 2767 return hns_roce_buf_offset(hr_cq->mtr.kmem,
2768 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
93aa2187
WHX		 2769}
2770
2771static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
2772{
2773 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
2774
2775 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2776 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
e2b2744a 2777 !!(n & hr_cq->cq_depth)) ? cqe : NULL;
93aa2187
WHX		 2778}
2779
e4aaf4ba 2780static inline void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 ci)
93aa2187 2781{
e4aaf4ba 2782 *hr_cq->set_ci_db = ci & V2_CQ_DB_PARAMETER_CONS_IDX_M;
93aa2187
WHX		 2783}
2784
926a01dc
WHX		 2785static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2786 struct hns_roce_srq *srq)
2787{
2788 struct hns_roce_v2_cqe *cqe, *dest;
2789 u32 prod_index;
2790 int nfreed = 0;
c7bcb134 2791 int wqe_index;
926a01dc
WHX		 2792 u8 owner_bit;
2793
2794 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
2795 ++prod_index) {
d7e5ca88 2796 if (prod_index > hr_cq->cons_index + hr_cq->ib_cq.cqe)
926a01dc
WHX		 2797 break;
2798 }
2799
2800 /*
2801 * Now backwards through the CQ, removing CQ entries
2802 * that match our QP by overwriting them with next entries.
2803 */
2804 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2805 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2806 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
2807 V2_CQE_BYTE_16_LCL_QPN_S) &
2808 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
c7bcb134
LO		 2809 if (srq &&
2810 roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S)) {
2811 wqe_index = roce_get_field(cqe->byte_4,
2812 V2_CQE_BYTE_4_WQE_INDX_M,
2813 V2_CQE_BYTE_4_WQE_INDX_S);
2814 hns_roce_free_srq_wqe(srq, wqe_index);
2815 }
926a01dc
WHX		 2816 ++nfreed;
2817 } else if (nfreed) {
2818 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
2819 hr_cq->ib_cq.cqe);
2820 owner_bit = roce_get_bit(dest->byte_4,
2821 V2_CQE_BYTE_4_OWNER_S);
2822 memcpy(dest, cqe, sizeof(*cqe));
2823 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
2824 owner_bit);
2825 }
2826 }
2827
2828 if (nfreed) {
2829 hr_cq->cons_index += nfreed;
2830 /*
2831 * Make sure update of buffer contents is done before
2832 * updating consumer index.
2833 */
2834 wmb();
2835 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
2836 }
2837}
2838
2839static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2840 struct hns_roce_srq *srq)
2841{
2842 spin_lock_irq(&hr_cq->lock);
2843 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
2844 spin_unlock_irq(&hr_cq->lock);
2845}
2846
93aa2187
WHX		 2847static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
2848 struct hns_roce_cq *hr_cq, void *mb_buf,
e2b2744a 2849 u64 *mtts, dma_addr_t dma_handle)
93aa2187
WHX		 2850{
2851 struct hns_roce_v2_cq_context *cq_context;
2852
2853 cq_context = mb_buf;
2854 memset(cq_context, 0, sizeof(*cq_context));
2855
2856 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
2857 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
a5073d60
YL		 2858 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_ARM_ST_M,
2859 V2_CQC_BYTE_4_ARM_ST_S, REG_NXT_CEQE);
93aa2187 2860 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
60262b10 2861 V2_CQC_BYTE_4_SHIFT_S, ilog2(hr_cq->cq_depth));
93aa2187 2862 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
e2b2744a 2863 V2_CQC_BYTE_4_CEQN_S, hr_cq->vector);
93aa2187
WHX		 2864
2865 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
2866 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
2867
744b7bdf 2868 cq_context->cqe_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
93aa2187
WHX		 2869
2870 roce_set_field(cq_context->byte_16_hop_addr,
2871 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
2872 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
744b7bdf 2873 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
93aa2187
WHX		 2874 roce_set_field(cq_context->byte_16_hop_addr,
2875 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
2876 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
2877 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
2878
744b7bdf 2879 cq_context->cqe_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
93aa2187
WHX		 2880 roce_set_field(cq_context->byte_24_pgsz_addr,
2881 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
2882 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
744b7bdf 2883 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
93aa2187
WHX		 2884 roce_set_field(cq_context->byte_24_pgsz_addr,
2885 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
2886 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
744b7bdf 2887 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.ba_pg_shift));
93aa2187
WHX		 2888 roce_set_field(cq_context->byte_24_pgsz_addr,
2889 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
2890 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
744b7bdf 2891 to_hr_hw_page_shift(hr_cq->mtr.hem_cfg.buf_pg_shift));
93aa2187 2892
bfe86035 2893 cq_context->cqe_ba = cpu_to_le32(dma_handle >> 3);
93aa2187
WHX		 2894
2895 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
2896 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
a5073d60 2897
05e6a5a6
LC		 2898 roce_set_bit(cq_context->byte_44_db_record,
2899 V2_CQC_BYTE_44_DB_RECORD_EN_S,
2900 (hr_cq->flags & HNS_ROCE_CQ_FLAG_RECORD_DB) ? 1 : 0);
9b44703d
YL		 2901
2902 roce_set_field(cq_context->byte_44_db_record,
2903 V2_CQC_BYTE_44_DB_RECORD_ADDR_M,
2904 V2_CQC_BYTE_44_DB_RECORD_ADDR_S,
2905 ((u32)hr_cq->db.dma) >> 1);
bfe86035 2906 cq_context->db_record_addr = cpu_to_le32(hr_cq->db.dma >> 32);
9b44703d 2907
a5073d60
YL		 2908 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2909 V2_CQC_BYTE_56_CQ_MAX_CNT_M,
2910 V2_CQC_BYTE_56_CQ_MAX_CNT_S,
2911 HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM);
2912 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
2913 V2_CQC_BYTE_56_CQ_PERIOD_M,
2914 V2_CQC_BYTE_56_CQ_PERIOD_S,
2915 HNS_ROCE_V2_CQ_DEFAULT_INTERVAL);
93aa2187
WHX		 2916}
2917
2918static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
2919 enum ib_cq_notify_flags flags)
2920{
d3743fa9 2921 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 2922 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2923 u32 notification_flag;
bfe86035 2924 __le32 doorbell[2];
93aa2187
WHX		 2925
2926 doorbell[0] = 0;
2927 doorbell[1] = 0;
2928
2929 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
2930 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
2931 /*
2932 * flags = 0; Notification Flag = 1, next
2933 * flags = 1; Notification Flag = 0, solocited
2934 */
2935 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
2936 hr_cq->cqn);
2937 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
2938 HNS_ROCE_V2_CQ_DB_NTR);
2939 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
25966e89 2940 V2_CQ_DB_PARAMETER_CONS_IDX_S, hr_cq->cons_index);
93aa2187 2941 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 2942 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 2943 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
2944 notification_flag);
2945
d3743fa9 2946 hns_roce_write64(hr_dev, doorbell, hr_cq->cq_db_l);
93aa2187
WHX		 2947
2948 return 0;
2949}
2950
0009c2db 2951static int hns_roce_handle_recv_inl_wqe(struct hns_roce_v2_cqe *cqe,
2952 struct hns_roce_qp **cur_qp,
2953 struct ib_wc *wc)
2954{
2955 struct hns_roce_rinl_sge *sge_list;
2956 u32 wr_num, wr_cnt, sge_num;
2957 u32 sge_cnt, data_len, size;
2958 void *wqe_buf;
2959
2960 wr_num = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_WQE_INDX_M,
2961 V2_CQE_BYTE_4_WQE_INDX_S) & 0xffff;
2962 wr_cnt = wr_num & ((*cur_qp)->rq.wqe_cnt - 1);
2963
2964 sge_list = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sg_list;
2965 sge_num = (*cur_qp)->rq_inl_buf.wqe_list[wr_cnt].sge_cnt;
6c6e3921 2966 wqe_buf = hns_roce_get_recv_wqe(*cur_qp, wr_cnt);
0009c2db 2967 data_len = wc->byte_len;
2968
2969 for (sge_cnt = 0; (sge_cnt < sge_num) && (data_len); sge_cnt++) {
2970 size = min(sge_list[sge_cnt].len, data_len);
2971 memcpy((void *)sge_list[sge_cnt].addr, wqe_buf, size);
2972
2973 data_len -= size;
2974 wqe_buf += size;
2975 }
2976
0db65709 2977 if (unlikely(data_len)) {
0009c2db 2978 wc->status = IB_WC_LOC_LEN_ERR;
2979 return -EAGAIN;
2980 }
2981
2982 return 0;
2983}
2984
626903e9
XW		 2985static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq,
2986 int num_entries, struct ib_wc *wc)
2987{
2988 unsigned int left;
2989 int npolled = 0;
2990
2991 left = wq->head - wq->tail;
2992 if (left == 0)
2993 return 0;
2994
2995 left = min_t(unsigned int, (unsigned int)num_entries, left);
2996 while (npolled < left) {
2997 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2998 wc->status = IB_WC_WR_FLUSH_ERR;
2999 wc->vendor_err = 0;
3000 wc->qp = &hr_qp->ibqp;
3001
3002 wq->tail++;
3003 wc++;
3004 npolled++;
3005 }
3006
3007 return npolled;
3008}
3009
3010static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries,
3011 struct ib_wc *wc)
3012{
3013 struct hns_roce_qp *hr_qp;
3014 int npolled = 0;
3015
3016 list_for_each_entry(hr_qp, &hr_cq->sq_list, sq_node) {
3017 npolled += sw_comp(hr_qp, &hr_qp->sq,
3018 num_entries - npolled, wc + npolled);
3019 if (npolled >= num_entries)
3020 goto out;
3021 }
3022
3023 list_for_each_entry(hr_qp, &hr_cq->rq_list, rq_node) {
3024 npolled += sw_comp(hr_qp, &hr_qp->rq,
3025 num_entries - npolled, wc + npolled);
3026 if (npolled >= num_entries)
3027 goto out;
3028 }
3029
3030out:
3031 return npolled;
3032}
3033
7c044adc
LC		 3034static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
3035 struct hns_roce_v2_cqe *cqe, struct ib_wc *wc)
3036{
3037 static const struct {
3038 u32 cqe_status;
3039 enum ib_wc_status wc_status;
3040 } map[] = {
3041 { HNS_ROCE_CQE_V2_SUCCESS, IB_WC_SUCCESS },
3042 { HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR, IB_WC_LOC_LEN_ERR },
3043 { HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR, IB_WC_LOC_QP_OP_ERR },
3044 { HNS_ROCE_CQE_V2_LOCAL_PROT_ERR, IB_WC_LOC_PROT_ERR },
3045 { HNS_ROCE_CQE_V2_WR_FLUSH_ERR, IB_WC_WR_FLUSH_ERR },
3046 { HNS_ROCE_CQE_V2_MW_BIND_ERR, IB_WC_MW_BIND_ERR },
3047 { HNS_ROCE_CQE_V2_BAD_RESP_ERR, IB_WC_BAD_RESP_ERR },
3048 { HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR, IB_WC_LOC_ACCESS_ERR },
3049 { HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR, IB_WC_REM_INV_REQ_ERR },
3050 { HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR, IB_WC_REM_ACCESS_ERR },
3051 { HNS_ROCE_CQE_V2_REMOTE_OP_ERR, IB_WC_REM_OP_ERR },
3052 { HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR,
3053 IB_WC_RETRY_EXC_ERR },
3054 { HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR, IB_WC_RNR_RETRY_EXC_ERR },
3055 { HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR, IB_WC_REM_ABORT_ERR },
3056 };
3057
3058 u32 cqe_status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
3059 V2_CQE_BYTE_4_STATUS_S);
3060 int i;
3061
3062 wc->status = IB_WC_GENERAL_ERR;
3063 for (i = 0; i < ARRAY_SIZE(map); i++)
3064 if (cqe_status == map[i].cqe_status) {
3065 wc->status = map[i].wc_status;
3066 break;
3067 }
3068
0db65709
LC		 3069 if (likely(wc->status == IB_WC_SUCCESS ||
3070 wc->status == IB_WC_WR_FLUSH_ERR))
7c044adc
LC		 3071 return;
3072
3073 ibdev_err(&hr_dev->ib_dev, "error cqe status 0x%x:\n", cqe_status);
3074 print_hex_dump(KERN_ERR, "", DUMP_PREFIX_NONE, 16, 4, cqe,
3075 sizeof(*cqe), false);
3076
3077 /*
3078 * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state gets
3079 * into errored mode. Hence, as a workaround to this hardware
3080 * limitation, driver needs to assist in flushing. But the flushing
3081 * operation uses mailbox to convey the QP state to the hardware and
3082 * which can sleep due to the mutex protection around the mailbox calls.
3083 * Hence, use the deferred flush for now. Once wc error detected, the
3084 * flushing operation is needed.
3085 */
3086 if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag))
3087 init_flush_work(hr_dev, qp);
3088}
3089
93aa2187
WHX		 3090static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
3091 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
3092{
b5374286 3093 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
c7bcb134 3094 struct hns_roce_srq *srq = NULL;
93aa2187
WHX		 3095 struct hns_roce_v2_cqe *cqe;
3096 struct hns_roce_qp *hr_qp;
3097 struct hns_roce_wq *wq;
3098 int is_send;
3099 u16 wqe_ctr;
3100 u32 opcode;
93aa2187 3101 int qpn;
0009c2db 3102 int ret;
93aa2187
WHX		 3103
3104 /* Find cqe according to consumer index */
e4aaf4ba 3105 cqe = get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
93aa2187
WHX		 3106 if (!cqe)
3107 return -EAGAIN;
3108
3109 ++hr_cq->cons_index;
3110 /* Memory barrier */
3111 rmb();
3112
3113 /* 0->SQ, 1->RQ */
3114 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
3115
3116 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
3117 V2_CQE_BYTE_16_LCL_QPN_S);
3118
3119 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
93aa2187
WHX		 3120 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
3121 if (unlikely(!hr_qp)) {
ae1c6148
LO		 3122 ibdev_err(&hr_dev->ib_dev,
3123 "CQ %06lx with entry for unknown QPN %06x\n",
3124 hr_cq->cqn, qpn & HNS_ROCE_V2_CQE_QPN_MASK);
93aa2187
WHX		 3125 return -EINVAL;
3126 }
3127 *cur_qp = hr_qp;
3128 }
3129
3130 wc->qp = &(*cur_qp)->ibqp;
3131 wc->vendor_err = 0;
3132
c7bcb134
LO		 3133 if (is_send) {
3134 wq = &(*cur_qp)->sq;
3135 if ((*cur_qp)->sq_signal_bits) {
3136 /*
3137 * If sg_signal_bit is 1,
3138 * firstly tail pointer updated to wqe
3139 * which current cqe correspond to
3140 */
3141 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3142 V2_CQE_BYTE_4_WQE_INDX_M,
3143 V2_CQE_BYTE_4_WQE_INDX_S);
3144 wq->tail += (wqe_ctr - (u16)wq->tail) &
3145 (wq->wqe_cnt - 1);
3146 }
3147
3148 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3149 ++wq->tail;
3150 } else if ((*cur_qp)->ibqp.srq) {
3151 srq = to_hr_srq((*cur_qp)->ibqp.srq);
bfe86035
LC		 3152 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
3153 V2_CQE_BYTE_4_WQE_INDX_M,
3154 V2_CQE_BYTE_4_WQE_INDX_S);
c7bcb134
LO		 3155 wc->wr_id = srq->wrid[wqe_ctr];
3156 hns_roce_free_srq_wqe(srq, wqe_ctr);
3157 } else {
3158 /* Update tail pointer, record wr_id */
3159 wq = &(*cur_qp)->rq;
3160 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
3161 ++wq->tail;
3162 }
3163
7c044adc 3164 get_cqe_status(hr_dev, *cur_qp, cqe, wc);
0db65709 3165 if (unlikely(wc->status != IB_WC_SUCCESS))
93aa2187
WHX		 3166 return 0;
3167
3168 if (is_send) {
3169 wc->wc_flags = 0;
3170 /* SQ corresponding to CQE */
3171 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3172 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
3173 case HNS_ROCE_SQ_OPCODE_SEND:
3174 wc->opcode = IB_WC_SEND;
3175 break;
3176 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
3177 wc->opcode = IB_WC_SEND;
3178 break;
3179 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
3180 wc->opcode = IB_WC_SEND;
3181 wc->wc_flags |= IB_WC_WITH_IMM;
3182 break;
3183 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
3184 wc->opcode = IB_WC_RDMA_READ;
3185 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3186 break;
3187 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
3188 wc->opcode = IB_WC_RDMA_WRITE;
3189 break;
3190 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
3191 wc->opcode = IB_WC_RDMA_WRITE;
3192 wc->wc_flags |= IB_WC_WITH_IMM;
3193 break;
3194 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
3195 wc->opcode = IB_WC_LOCAL_INV;
3196 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3197 break;
3198 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
3199 wc->opcode = IB_WC_COMP_SWAP;
3200 wc->byte_len = 8;
3201 break;
3202 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
3203 wc->opcode = IB_WC_FETCH_ADD;
3204 wc->byte_len = 8;
3205 break;
3206 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
3207 wc->opcode = IB_WC_MASKED_COMP_SWAP;
3208 wc->byte_len = 8;
3209 break;
3210 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
3211 wc->opcode = IB_WC_MASKED_FETCH_ADD;
3212 wc->byte_len = 8;
3213 break;
3214 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
3215 wc->opcode = IB_WC_REG_MR;
3216 break;
3217 case HNS_ROCE_SQ_OPCODE_BIND_MW:
3218 wc->opcode = IB_WC_REG_MR;
3219 break;
3220 default:
3221 wc->status = IB_WC_GENERAL_ERR;
3222 break;
3223 }
93aa2187
WHX		 3224 } else {
3225 /* RQ correspond to CQE */
3226 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
3227
3228 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
3229 V2_CQE_BYTE_4_OPCODE_S);
3230 switch (opcode & 0x1f) {
3231 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
3232 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3233 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3234 wc->ex.imm_data =
3235 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3236 break;
3237 case HNS_ROCE_V2_OPCODE_SEND:
3238 wc->opcode = IB_WC_RECV;
3239 wc->wc_flags = 0;
3240 break;
3241 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
3242 wc->opcode = IB_WC_RECV;
3243 wc->wc_flags = IB_WC_WITH_IMM;
0c4a0e29
LO		 3244 wc->ex.imm_data =
3245 cpu_to_be32(le32_to_cpu(cqe->immtdata));
93aa2187
WHX		 3246 break;
3247 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
3248 wc->opcode = IB_WC_RECV;
3249 wc->wc_flags = IB_WC_WITH_INVALIDATE;
ccb8a29e 3250 wc->ex.invalidate_rkey = le32_to_cpu(cqe->rkey);
93aa2187
WHX		 3251 break;
3252 default:
3253 wc->status = IB_WC_GENERAL_ERR;
3254 break;
3255 }
3256
0009c2db 3257 if ((wc->qp->qp_type == IB_QPT_RC ||
3258 wc->qp->qp_type == IB_QPT_UC) &&
3259 (opcode == HNS_ROCE_V2_OPCODE_SEND ||
3260 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_IMM ||
3261 opcode == HNS_ROCE_V2_OPCODE_SEND_WITH_INV) &&
3262 (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_RQ_INLINE_S))) {
3263 ret = hns_roce_handle_recv_inl_wqe(cqe, cur_qp, wc);
0db65709 3264 if (unlikely(ret))
0009c2db 3265 return -EAGAIN;
3266 }
3267
93aa2187
WHX		 3268 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
3269 V2_CQE_BYTE_32_SL_S);
3270 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
3271 V2_CQE_BYTE_32_RMT_QPN_M,
3272 V2_CQE_BYTE_32_RMT_QPN_S);
15fc056f 3273 wc->slid = 0;
93aa2187
WHX		 3274 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
3275 V2_CQE_BYTE_32_GRH_S) ?
3276 IB_WC_GRH : 0);
6c1f08b3 3277 wc->port_num = roce_get_field(cqe->byte_32,
3278 V2_CQE_BYTE_32_PORTN_M, V2_CQE_BYTE_32_PORTN_S);
3279 wc->pkey_index = 0;
cd4a70bb 3280
944e6409
LO		 3281 if (roce_get_bit(cqe->byte_28, V2_CQE_BYTE_28_VID_VLD_S)) {
3282 wc->vlan_id = (u16)roce_get_field(cqe->byte_28,
3283 V2_CQE_BYTE_28_VID_M,
3284 V2_CQE_BYTE_28_VID_S);
0e1aa6f0 3285 wc->wc_flags |= IB_WC_WITH_VLAN;
944e6409
LO		 3286 } else {
3287 wc->vlan_id = 0xffff;
3288 }
3289
2eade675 3290 wc->network_hdr_type = roce_get_field(cqe->byte_28,
3291 V2_CQE_BYTE_28_PORT_TYPE_M,
3292 V2_CQE_BYTE_28_PORT_TYPE_S);
93aa2187
WHX		 3293 }
3294
3295 return 0;
3296}
3297
3298static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
3299 struct ib_wc *wc)
3300{
626903e9 3301 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
93aa2187
WHX		 3302 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3303 struct hns_roce_qp *cur_qp = NULL;
3304 unsigned long flags;
3305 int npolled;
3306
3307 spin_lock_irqsave(&hr_cq->lock, flags);
3308
626903e9
XW		 3309 /*
3310 * When the device starts to reset, the state is RST_DOWN. At this time,
3311 * there may still be some valid CQEs in the hardware that are not
3312 * polled. Therefore, it is not allowed to switch to the software mode
3313 * immediately. When the state changes to UNINIT, CQE no longer exists
3314 * in the hardware, and then switch to software mode.
3315 */
3316 if (hr_dev->state == HNS_ROCE_DEVICE_STATE_UNINIT) {
3317 npolled = hns_roce_v2_sw_poll_cq(hr_cq, num_entries, wc);
3318 goto out;
3319 }
3320
93aa2187
WHX		 3321 for (npolled = 0; npolled < num_entries; ++npolled) {
3322 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
3323 break;
3324 }
3325
3326 if (npolled) {
3327 /* Memory barrier */
3328 wmb();
3329 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
3330 }
3331
626903e9 3332out:
93aa2187
WHX		 3333 spin_unlock_irqrestore(&hr_cq->lock, flags);
3334
3335 return npolled;
3336}
3337
260c3b34
YL		 3338static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type,
3339 int step_idx)
3340{
3341 int op;
3342
3343 if (type == HEM_TYPE_SCCC && step_idx)
3344 return -EINVAL;
3345
3346 switch (type) {
3347 case HEM_TYPE_QPC:
3348 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
3349 break;
3350 case HEM_TYPE_MTPT:
3351 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
3352 break;
3353 case HEM_TYPE_CQC:
3354 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
3355 break;
3356 case HEM_TYPE_SRQC:
3357 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
3358 break;
3359 case HEM_TYPE_SCCC:
3360 op = HNS_ROCE_CMD_WRITE_SCCC_BT0;
3361 break;
3362 case HEM_TYPE_QPC_TIMER:
3363 op = HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0;
3364 break;
3365 case HEM_TYPE_CQC_TIMER:
3366 op = HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0;
3367 break;
3368 default:
3369 dev_warn(hr_dev->dev,
3370 "Table %d not to be written by mailbox!\n", type);
3371 return -EINVAL;
3372 }
3373
3374 return op + step_idx;
3375}
3376
a81fba28
WHX		 3377static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
3378 struct hns_roce_hem_table *table, int obj,
3379 int step_idx)
3380{
a81fba28
WHX		 3381 struct hns_roce_cmd_mailbox *mailbox;
3382 struct hns_roce_hem_iter iter;
3383 struct hns_roce_hem_mhop mhop;
3384 struct hns_roce_hem *hem;
3385 unsigned long mhop_obj = obj;
3386 int i, j, k;
3387 int ret = 0;
3388 u64 hem_idx = 0;
3389 u64 l1_idx = 0;
3390 u64 bt_ba = 0;
3391 u32 chunk_ba_num;
3392 u32 hop_num;
260c3b34 3393 int op;
a81fba28
WHX		 3394
3395 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3396 return 0;
3397
3398 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
3399 i = mhop.l0_idx;
3400 j = mhop.l1_idx;
3401 k = mhop.l2_idx;
3402 hop_num = mhop.hop_num;
3403 chunk_ba_num = mhop.bt_chunk_size / 8;
3404
3405 if (hop_num == 2) {
3406 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
3407 k;
3408 l1_idx = i * chunk_ba_num + j;
3409 } else if (hop_num == 1) {
3410 hem_idx = i * chunk_ba_num + j;
3411 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
3412 hem_idx = i;
3413 }
3414
260c3b34
YL		 3415 op = get_op_for_set_hem(hr_dev, table->type, step_idx);
3416 if (op == -EINVAL)
a81fba28 3417 return 0;
a81fba28
WHX		 3418
3419 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3420 if (IS_ERR(mailbox))
3421 return PTR_ERR(mailbox);
3422
6ac16e40
YL		 3423 if (table->type == HEM_TYPE_SCCC)
3424 obj = mhop.l0_idx;
3425
a81fba28
WHX		 3426 if (check_whether_last_step(hop_num, step_idx)) {
3427 hem = table->hem[hem_idx];
3428 for (hns_roce_hem_first(hem, &iter);
3429 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
3430 bt_ba = hns_roce_hem_addr(&iter);
3431
3432 /* configure the ba, tag, and op */
3433 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
3434 obj, 0, op,
3435 HNS_ROCE_CMD_TIMEOUT_MSECS);
3436 }
3437 } else {
3438 if (step_idx == 0)
3439 bt_ba = table->bt_l0_dma_addr[i];
3440 else if (step_idx == 1 && hop_num == 2)
3441 bt_ba = table->bt_l1_dma_addr[l1_idx];
3442
3443 /* configure the ba, tag, and op */
3444 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
3445 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
3446 }
3447
3448 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3449 return ret;
3450}
3451
3452static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
3453 struct hns_roce_hem_table *table, int obj,
3454 int step_idx)
3455{
3456 struct device *dev = hr_dev->dev;
3457 struct hns_roce_cmd_mailbox *mailbox;
617cf24f 3458 int ret;
a81fba28
WHX		 3459 u16 op = 0xff;
3460
3461 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
3462 return 0;
3463
3464 switch (table->type) {
3465 case HEM_TYPE_QPC:
3466 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
3467 break;
3468 case HEM_TYPE_MTPT:
3469 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
3470 break;
3471 case HEM_TYPE_CQC:
3472 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
3473 break;
6a157f7d 3474 case HEM_TYPE_SCCC:
0e40dc2f
YL		 3475 case HEM_TYPE_QPC_TIMER:
3476 case HEM_TYPE_CQC_TIMER:
6a157f7d 3477 break;
a81fba28
WHX		 3478 case HEM_TYPE_SRQC:
3479 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
3480 break;
3481 default:
3482 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
3483 table->type);
3484 return 0;
3485 }
6a157f7d 3486
0e40dc2f
YL		 3487 if (table->type == HEM_TYPE_SCCC ||
3488 table->type == HEM_TYPE_QPC_TIMER ||
3489 table->type == HEM_TYPE_CQC_TIMER)
6a157f7d
YL		 3490 return 0;
3491
a81fba28
WHX		 3492 op += step_idx;
3493
3494 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3495 if (IS_ERR(mailbox))
3496 return PTR_ERR(mailbox);
3497
3498 /* configure the tag and op */
3499 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
3500 HNS_ROCE_CMD_TIMEOUT_MSECS);
3501
3502 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3503 return ret;
3504}
3505
926a01dc 3506static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
926a01dc
WHX		 3507 struct hns_roce_v2_qp_context *context,
3508 struct hns_roce_qp *hr_qp)
3509{
3510 struct hns_roce_cmd_mailbox *mailbox;
3511 int ret;
3512
3513 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3514 if (IS_ERR(mailbox))
3515 return PTR_ERR(mailbox);
3516
3517 memcpy(mailbox->buf, context, sizeof(*context) * 2);
3518
3519 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
3520 HNS_ROCE_CMD_MODIFY_QPC,
3521 HNS_ROCE_CMD_TIMEOUT_MSECS);
3522
3523 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3524
3525 return ret;
3526}
3527
ace1c541 3528static void set_access_flags(struct hns_roce_qp *hr_qp,
3529 struct hns_roce_v2_qp_context *context,
3530 struct hns_roce_v2_qp_context *qpc_mask,
3531 const struct ib_qp_attr *attr, int attr_mask)
3532{
3533 u8 dest_rd_atomic;
3534 u32 access_flags;
3535
c2799119 3536 dest_rd_atomic = (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) ?
ace1c541 3537 attr->max_dest_rd_atomic : hr_qp->resp_depth;
3538
c2799119 3539 access_flags = (attr_mask & IB_QP_ACCESS_FLAGS) ?
ace1c541 3540 attr->qp_access_flags : hr_qp->atomic_rd_en;
3541
3542 if (!dest_rd_atomic)
3543 access_flags &= IB_ACCESS_REMOTE_WRITE;
3544
3545 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3546 !!(access_flags & IB_ACCESS_REMOTE_READ));
3547 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
3548
3549 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3550 !!(access_flags & IB_ACCESS_REMOTE_WRITE));
3551 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
3552
3553 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3554 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3555 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
7db82697
JZ		 3556 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S,
3557 !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
3558 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_EXT_ATE_S, 0);
ace1c541 3559}
3560
99441ab5
XW		 3561static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp,
3562 struct hns_roce_v2_qp_context *context,
3563 struct hns_roce_v2_qp_context *qpc_mask)
3564{
54d66387
XW		 3565 roce_set_field(context->byte_4_sqpn_tst,
3566 V2_QPC_BYTE_4_SGE_SHIFT_M, V2_QPC_BYTE_4_SGE_SHIFT_S,
3567 to_hr_hem_entries_shift(hr_qp->sge.sge_cnt,
3568 hr_qp->sge.sge_shift));
99441ab5 3569
99441ab5
XW		 3570 roce_set_field(context->byte_20_smac_sgid_idx,
3571 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
54d66387 3572 ilog2(hr_qp->sq.wqe_cnt));
99441ab5
XW		 3573
3574 roce_set_field(context->byte_20_smac_sgid_idx,
3575 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
54d66387 3576 ilog2(hr_qp->rq.wqe_cnt));
99441ab5
XW		 3577}
3578
926a01dc
WHX		 3579static void modify_qp_reset_to_init(struct ib_qp *ibqp,
3580 const struct ib_qp_attr *attr,
0fa95a9a 3581 int attr_mask,
926a01dc
WHX		 3582 struct hns_roce_v2_qp_context *context,
3583 struct hns_roce_v2_qp_context *qpc_mask)
3584{
ecaaf1e2 3585 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
926a01dc
WHX		 3586 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3587
3588 /*
3589 * In v2 engine, software pass context and context mask to hardware
3590 * when modifying qp. If software need modify some fields in context,
3591 * we should set all bits of the relevant fields in context mask to
3592 * 0 at the same time, else set them to 0x1.
3593 */
3594 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3595 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
926a01dc 3596
926a01dc
WHX		 3597 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3598 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
926a01dc
WHX		 3599
3600 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3601 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
926a01dc
WHX		 3602
3603 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
3604 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
926a01dc 3605
99441ab5 3606 set_qpc_wqe_cnt(hr_qp, context, qpc_mask);
926a01dc
WHX		 3607
3608 /* No VLAN need to set 0xFFF */
c8e46f8d
LO		 3609 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
3610 V2_QPC_BYTE_24_VLAN_ID_S, 0xfff);
926a01dc 3611
90ae0b57 3612 if (hr_qp->en_flags & HNS_ROCE_QP_CAP_RQ_RECORD_DB)
e088a685
YL		 3613 roce_set_bit(context->byte_68_rq_db,
3614 V2_QPC_BYTE_68_RQ_RECORD_EN_S, 1);
e088a685
YL		 3615
3616 roce_set_field(context->byte_68_rq_db,
3617 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M,
3618 V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S,
3619 ((u32)hr_qp->rdb.dma) >> 1);
bfe86035 3620 context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32);
e088a685 3621
ecaaf1e2 3622 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
3623 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
926a01dc
WHX		 3624
3625 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3626 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
926a01dc
WHX		 3627 if (ibqp->srq) {
3628 roce_set_field(context->byte_76_srqn_op_en,
3629 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3630 to_hr_srq(ibqp->srq)->srqn);
926a01dc
WHX		 3631 roce_set_bit(context->byte_76_srqn_op_en,
3632 V2_QPC_BYTE_76_SRQ_EN_S, 1);
f4c5d869 3633 }
926a01dc
WHX		 3634
3635 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
3636 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
926a01dc 3637
68a997c5 3638 roce_set_bit(context->byte_172_sq_psn, V2_QPC_BYTE_172_FRE_S, 1);
926a01dc
WHX		 3639
3640 hr_qp->access_flags = attr->qp_access_flags;
926a01dc
WHX		 3641 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3642 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3643}
3644
3645static void modify_qp_init_to_init(struct ib_qp *ibqp,
3646 const struct ib_qp_attr *attr, int attr_mask,
3647 struct hns_roce_v2_qp_context *context,
3648 struct hns_roce_v2_qp_context *qpc_mask)
3649{
3650 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3651
3652 /*
3653 * In v2 engine, software pass context and context mask to hardware
3654 * when modifying qp. If software need modify some fields in context,
3655 * we should set all bits of the relevant fields in context mask to
3656 * 0 at the same time, else set them to 0x1.
3657 */
3658 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3659 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
3660 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
3661 V2_QPC_BYTE_4_TST_S, 0);
3662
926a01dc
WHX		 3663 if (attr_mask & IB_QP_ACCESS_FLAGS) {
3664 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3665 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
3666 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3667 0);
3668
3669 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3670 !!(attr->qp_access_flags &
3671 IB_ACCESS_REMOTE_WRITE));
3672 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3673 0);
3674
3675 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3676 !!(attr->qp_access_flags &
3677 IB_ACCESS_REMOTE_ATOMIC));
3678 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3679 0);
7db82697
JZ		 3680 roce_set_bit(context->byte_76_srqn_op_en,
3681 V2_QPC_BYTE_76_EXT_ATE_S,
3682 !!(attr->qp_access_flags &
3683 IB_ACCESS_REMOTE_ATOMIC));
3684 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3685 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3686 } else {
3687 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3688 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
3689 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
3690 0);
3691
3692 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3693 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
3694 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
3695 0);
3696
3697 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3698 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3699 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
3700 0);
7db82697
JZ		 3701 roce_set_bit(context->byte_76_srqn_op_en,
3702 V2_QPC_BYTE_76_EXT_ATE_S,
3703 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
3704 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3705 V2_QPC_BYTE_76_EXT_ATE_S, 0);
926a01dc
WHX		 3706 }
3707
926a01dc
WHX		 3708 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3709 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
3710 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
3711 V2_QPC_BYTE_16_PD_S, 0);
3712
3713 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3714 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
3715 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
3716 V2_QPC_BYTE_80_RX_CQN_S, 0);
3717
3718 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
6d13b869 3719 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
926a01dc
WHX		 3720 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
3721 V2_QPC_BYTE_252_TX_CQN_S, 0);
3722
3723 if (ibqp->srq) {
3724 roce_set_bit(context->byte_76_srqn_op_en,
3725 V2_QPC_BYTE_76_SRQ_EN_S, 1);
3726 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
3727 V2_QPC_BYTE_76_SRQ_EN_S, 0);
3728 roce_set_field(context->byte_76_srqn_op_en,
3729 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
3730 to_hr_srq(ibqp->srq)->srqn);
3731 roce_set_field(qpc_mask->byte_76_srqn_op_en,
3732 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
3733 }
3734
926a01dc
WHX		 3735 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3736 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
3737 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
3738 V2_QPC_BYTE_4_SQPN_S, 0);
3739
b6dd9b34 3740 if (attr_mask & IB_QP_DEST_QPN) {
3741 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
3742 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
3743 roce_set_field(qpc_mask->byte_56_dqpn_err,
3744 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
3745 }
926a01dc
WHX		 3746}
3747
8d18ad83
LO		 3748static bool check_wqe_rq_mtt_count(struct hns_roce_dev *hr_dev,
3749 struct hns_roce_qp *hr_qp, int mtt_cnt,
3750 u32 page_size)
3751{
ae1c6148 3752 struct ib_device *ibdev = &hr_dev->ib_dev;
8d18ad83
LO		 3753
3754 if (hr_qp->rq.wqe_cnt < 1)
3755 return true;
3756
3757 if (mtt_cnt < 1) {
ae1c6148
LO		 3758 ibdev_err(ibdev, "failed to find RQWQE buf ba of QP(0x%lx)\n",
3759 hr_qp->qpn);
8d18ad83
LO		 3760 return false;
3761 }
3762
3763 if (mtt_cnt < MTT_MIN_COUNT &&
3764 (hr_qp->rq.offset + page_size) < hr_qp->buff_size) {
ae1c6148
LO		 3765 ibdev_err(ibdev,
3766 "failed to find next RQWQE buf ba of QP(0x%lx)\n",
3767 hr_qp->qpn);
8d18ad83
LO		 3768 return false;
3769 }
3770
3771 return true;
3772}
3773
494c3b31
XW		 3774static int config_qp_rq_buf(struct hns_roce_dev *hr_dev,
3775 struct hns_roce_qp *hr_qp,
3776 struct hns_roce_v2_qp_context *context,
3777 struct hns_roce_v2_qp_context *qpc_mask)
926a01dc 3778{
494c3b31 3779 struct ib_qp *ibqp = &hr_qp->ibqp;
8d18ad83 3780 u64 mtts[MTT_MIN_COUNT] = { 0 };
8d18ad83 3781 u64 wqe_sge_ba;
926a01dc 3782 u32 page_size;
8d18ad83 3783 int count;
926a01dc
WHX		 3784
3785 /* Search qp buf's mtts */
d563099e 3786 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift;
8d18ad83
LO		 3787 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
3788 hr_qp->rq.offset / page_size, mtts,
3789 MTT_MIN_COUNT, &wqe_sge_ba);
3790 if (!ibqp->srq)
3791 if (!check_wqe_rq_mtt_count(hr_dev, hr_qp, count, page_size))
3792 return -EINVAL;
926a01dc 3793
bfe86035 3794 context->wqe_sge_ba = cpu_to_le32(wqe_sge_ba >> 3);
926a01dc
WHX		 3795 qpc_mask->wqe_sge_ba = 0;
3796
3797 /*
3798 * In v2 engine, software pass context and context mask to hardware
3799 * when modifying qp. If software need modify some fields in context,
3800 * we should set all bits of the relevant fields in context mask to
3801 * 0 at the same time, else set them to 0x1.
3802 */
3803 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
8d18ad83 3804 V2_QPC_BYTE_12_WQE_SGE_BA_S, wqe_sge_ba >> (32 + 3));
926a01dc
WHX		 3805 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
3806 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
3807
3808 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3809 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
54d66387
XW		 3810 to_hr_hem_hopnum(hr_dev->caps.wqe_sq_hop_num,
3811 hr_qp->sq.wqe_cnt));
926a01dc
WHX		 3812 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
3813 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
3814
3815 roce_set_field(context->byte_20_smac_sgid_idx,
3816 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3817 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
54d66387
XW		 3818 to_hr_hem_hopnum(hr_dev->caps.wqe_sge_hop_num,
3819 hr_qp->sge.sge_cnt));
926a01dc
WHX		 3820 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3821 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
3822 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
3823
3824 roce_set_field(context->byte_20_smac_sgid_idx,
3825 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3826 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
54d66387
XW		 3827 to_hr_hem_hopnum(hr_dev->caps.wqe_rq_hop_num,
3828 hr_qp->rq.wqe_cnt));
3829
926a01dc
WHX		 3830 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
3831 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
3832 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
3833
3834 roce_set_field(context->byte_16_buf_ba_pg_sz,
3835 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3836 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
d563099e 3837 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.ba_pg_shift));
926a01dc
WHX		 3838 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3839 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
3840 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
3841
3842 roce_set_field(context->byte_16_buf_ba_pg_sz,
3843 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3844 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
d563099e 3845 to_hr_hw_page_shift(hr_qp->mtr.hem_cfg.buf_pg_shift));
926a01dc
WHX		 3846 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
3847 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
3848 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
3849
d563099e 3850 context->rq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[0]));
926a01dc
WHX		 3851 qpc_mask->rq_cur_blk_addr = 0;
3852
3853 roce_set_field(context->byte_92_srq_info,
3854 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3855 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
d563099e 3856 upper_32_bits(to_hr_hw_page_addr(mtts[0])));
926a01dc
WHX		 3857 roce_set_field(qpc_mask->byte_92_srq_info,
3858 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
3859 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
3860
d563099e 3861 context->rq_nxt_blk_addr = cpu_to_le32(to_hr_hw_page_addr(mtts[1]));
926a01dc
WHX		 3862 qpc_mask->rq_nxt_blk_addr = 0;
3863
3864 roce_set_field(context->byte_104_rq_sge,
3865 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3866 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
d563099e 3867 upper_32_bits(to_hr_hw_page_addr(mtts[1])));
926a01dc
WHX		 3868 roce_set_field(qpc_mask->byte_104_rq_sge,
3869 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
3870 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
3871
494c3b31
XW		 3872 roce_set_field(context->byte_84_rq_ci_pi,
3873 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3874 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
3875 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3876 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
3877 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
3878
3879 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
3880 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
3881 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
3882
3883 return 0;
3884}
3885
3886static int config_qp_sq_buf(struct hns_roce_dev *hr_dev,
3887 struct hns_roce_qp *hr_qp,
3888 struct hns_roce_v2_qp_context *context,
3889 struct hns_roce_v2_qp_context *qpc_mask)
3890{
3891 struct ib_device *ibdev = &hr_dev->ib_dev;
3892 u64 sge_cur_blk = 0;
3893 u64 sq_cur_blk = 0;
3894 u32 page_size;
3895 int count;
3896
3897 /* search qp buf's mtts */
3898 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, &sq_cur_blk, 1, NULL);
3899 if (count < 1) {
3900 ibdev_err(ibdev, "failed to find QP(0x%lx) SQ buf.\n",
3901 hr_qp->qpn);
3902 return -EINVAL;
3903 }
3904 if (hr_qp->sge.sge_cnt > 0) {
3905 page_size = 1 << hr_qp->mtr.hem_cfg.buf_pg_shift;
3906 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr,
3907 hr_qp->sge.offset / page_size,
3908 &sge_cur_blk, 1, NULL);
3909 if (count < 1) {
3910 ibdev_err(ibdev, "failed to find QP(0x%lx) SGE buf.\n",
3911 hr_qp->qpn);
3912 return -EINVAL;
3913 }
3914 }
3915
3916 /*
3917 * In v2 engine, software pass context and context mask to hardware
3918 * when modifying qp. If software need modify some fields in context,
3919 * we should set all bits of the relevant fields in context mask to
3920 * 0 at the same time, else set them to 0x1.
3921 */
3922 context->sq_cur_blk_addr = cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
3923 roce_set_field(context->byte_168_irrl_idx,
3924 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3925 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
3926 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
3927 qpc_mask->sq_cur_blk_addr = 0;
3928 roce_set_field(qpc_mask->byte_168_irrl_idx,
3929 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
3930 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
3931
3932 context->sq_cur_sge_blk_addr =
3933 cpu_to_le32(to_hr_hw_page_addr(sge_cur_blk));
3934 roce_set_field(context->byte_184_irrl_idx,
3935 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3936 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
3937 upper_32_bits(to_hr_hw_page_addr(sge_cur_blk)));
3938 qpc_mask->sq_cur_sge_blk_addr = 0;
3939 roce_set_field(qpc_mask->byte_184_irrl_idx,
3940 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
3941 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
3942
3943 context->rx_sq_cur_blk_addr =
3944 cpu_to_le32(to_hr_hw_page_addr(sq_cur_blk));
3945 roce_set_field(context->byte_232_irrl_sge,
3946 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3947 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
3948 upper_32_bits(to_hr_hw_page_addr(sq_cur_blk)));
3949 qpc_mask->rx_sq_cur_blk_addr = 0;
3950 roce_set_field(qpc_mask->byte_232_irrl_sge,
3951 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
3952 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
3953
3954 return 0;
3955}
3956
7b9bd73e
WL		 3957static inline enum ib_mtu get_mtu(struct ib_qp *ibqp,
3958 const struct ib_qp_attr *attr)
3959{
3960 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_UD)
3961 return IB_MTU_4096;
3962
3963 return attr->path_mtu;
3964}
3965
494c3b31
XW		 3966static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
3967 const struct ib_qp_attr *attr, int attr_mask,
3968 struct hns_roce_v2_qp_context *context,
3969 struct hns_roce_v2_qp_context *qpc_mask)
3970{
3971 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
3972 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3973 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3974 struct ib_device *ibdev = &hr_dev->ib_dev;
3975 dma_addr_t trrl_ba;
3976 dma_addr_t irrl_ba;
7b9bd73e 3977 enum ib_mtu mtu;
494c3b31
XW		 3978 u8 port_num;
3979 u64 *mtts;
3980 u8 *dmac;
3981 u8 *smac;
3982 int port;
3983 int ret;
3984
3985 ret = config_qp_rq_buf(hr_dev, hr_qp, context, qpc_mask);
3986 if (ret) {
3987 ibdev_err(ibdev, "failed to config rq buf, ret = %d.\n", ret);
3988 return ret;
3989 }
3990
3991 /* Search IRRL's mtts */
3992 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
3993 hr_qp->qpn, &irrl_ba);
3994 if (!mtts) {
3995 ibdev_err(ibdev, "failed to find qp irrl_table.\n");
3996 return -EINVAL;
3997 }
3998
3999 /* Search TRRL's mtts */
4000 mtts = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
4001 hr_qp->qpn, &trrl_ba);
4002 if (!mtts) {
4003 ibdev_err(ibdev, "failed to find qp trrl_table.\n");
4004 return -EINVAL;
4005 }
4006
4007 if (attr_mask & IB_QP_ALT_PATH) {
4008 ibdev_err(ibdev, "INIT2RTR attr_mask (0x%x) error.\n",
4009 attr_mask);
4010 return -EINVAL;
4011 }
4012
e92f2c18 4013 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
494c3b31 4014 V2_QPC_BYTE_132_TRRL_BA_S, trrl_ba >> 4);
e92f2c18 4015 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
4016 V2_QPC_BYTE_132_TRRL_BA_S, 0);
494c3b31 4017 context->trrl_ba = cpu_to_le32(trrl_ba >> (16 + 4));
e92f2c18 4018 qpc_mask->trrl_ba = 0;
4019 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
4020 V2_QPC_BYTE_140_TRRL_BA_S,
494c3b31 4021 (u32)(trrl_ba >> (32 + 16 + 4)));
e92f2c18 4022 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
4023 V2_QPC_BYTE_140_TRRL_BA_S, 0);
4024
494c3b31 4025 context->irrl_ba = cpu_to_le32(irrl_ba >> 6);
926a01dc
WHX		 4026 qpc_mask->irrl_ba = 0;
4027 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
4028 V2_QPC_BYTE_208_IRRL_BA_S,
494c3b31 4029 irrl_ba >> (32 + 6));
926a01dc
WHX		 4030 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
4031 V2_QPC_BYTE_208_IRRL_BA_S, 0);
4032
4033 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
4034 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
4035
4036 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
4037 hr_qp->sq_signal_bits);
4038 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
4039 0);
4040
4041 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
4042
4043 smac = (u8 *)hr_dev->dev_addr[port];
87d9e568 4044 dmac = (u8 *)attr->ah_attr.roce.dmac;
926a01dc
WHX		 4045 /* when dmac equals smac or loop_idc is 1, it should loopback */
4046 if (ether_addr_equal_unaligned(dmac, smac) ||
4047 hr_dev->loop_idc == 0x1) {
4048 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
4049 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
4050 }
4051
b6dd9b34 4052 if (attr_mask & IB_QP_DEST_QPN) {
4053 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
4054 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
4055 roce_set_field(qpc_mask->byte_56_dqpn_err,
4056 V2_QPC_BYTE_56_DQPN_M, V2_QPC_BYTE_56_DQPN_S, 0);
4057 }
926a01dc
WHX		 4058
4059 /* Configure GID index */
4060 port_num = rdma_ah_get_port_num(&attr->ah_attr);
4061 roce_set_field(context->byte_20_smac_sgid_idx,
60262b10 4062 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
926a01dc
WHX		 4063 hns_get_gid_index(hr_dev, port_num - 1,
4064 grh->sgid_index));
4065 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
60262b10 4066 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
494c3b31 4067
2a3d923f 4068 memcpy(&(context->dmac), dmac, sizeof(u32));
926a01dc
WHX		 4069 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
4070 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
4071 qpc_mask->dmac = 0;
4072 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
4073 V2_QPC_BYTE_52_DMAC_S, 0);
4074
7b9bd73e
WL		 4075 mtu = get_mtu(ibqp, attr);
4076
4077 if (attr_mask & IB_QP_PATH_MTU) {
4078 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
4079 V2_QPC_BYTE_24_MTU_S, mtu);
4080 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
4081 V2_QPC_BYTE_24_MTU_S, 0);
4082 }
4083
4084#define MAX_LP_MSG_LEN 65536
4085 /* MTU*(2^LP_PKTN_INI) shouldn't be bigger than 64kb */
926a01dc 4086 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
b713128d 4087 V2_QPC_BYTE_56_LP_PKTN_INI_S,
7b9bd73e 4088 ilog2(MAX_LP_MSG_LEN / ib_mtu_enum_to_int(mtu)));
926a01dc
WHX		 4089 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
4090 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
4091
926a01dc
WHX		 4092 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4093 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
4094 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
4095 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
4096 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4097 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
4098 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
4099
4100 context->rq_rnr_timer = 0;
4101 qpc_mask->rq_rnr_timer = 0;
4102
926a01dc
WHX		 4103 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
4104 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
4105 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
4106 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
4107
2a3d923f 4108 /* rocee send 2^lp_sgen_ini segs every time */
926a01dc
WHX		 4109 roce_set_field(context->byte_168_irrl_idx,
4110 V2_QPC_BYTE_168_LP_SGEN_INI_M,
4111 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
4112 roce_set_field(qpc_mask->byte_168_irrl_idx,
4113 V2_QPC_BYTE_168_LP_SGEN_INI_M,
4114 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
4115
926a01dc
WHX		 4116 return 0;
4117}
4118
4119static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
4120 const struct ib_qp_attr *attr, int attr_mask,
4121 struct hns_roce_v2_qp_context *context,
4122 struct hns_roce_v2_qp_context *qpc_mask)
4123{
4124 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4125 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 4126 struct ib_device *ibdev = &hr_dev->ib_dev;
494c3b31 4127 int ret;
8d18ad83 4128
734f3863 4129 /* Not support alternate path and path migration */
d398d4ca 4130 if (attr_mask & (IB_QP_ALT_PATH | IB_QP_PATH_MIG_STATE)) {
ae1c6148 4131 ibdev_err(ibdev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
926a01dc
WHX		 4132 return -EINVAL;
4133 }
4134
494c3b31
XW		 4135 ret = config_qp_sq_buf(hr_dev, hr_qp, context, qpc_mask);
4136 if (ret) {
4137 ibdev_err(ibdev, "failed to config sq buf, ret %d\n", ret);
4138 return ret;
4139 }
926a01dc
WHX		 4140
4141 /*
4142 * Set some fields in context to zero, Because the default values
4143 * of all fields in context are zero, we need not set them to 0 again.
4144 * but we should set the relevant fields of context mask to 0.
4145 */
4146 roce_set_field(qpc_mask->byte_232_irrl_sge,
4147 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
4148 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
4149
4150 roce_set_field(qpc_mask->byte_240_irrl_tail,
4151 V2_QPC_BYTE_240_RX_ACK_MSN_M,
4152 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
4153
926a01dc
WHX		 4154 roce_set_field(qpc_mask->byte_248_ack_psn,
4155 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
4156 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
4157 roce_set_bit(qpc_mask->byte_248_ack_psn,
4158 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
4159 roce_set_field(qpc_mask->byte_248_ack_psn,
4160 V2_QPC_BYTE_248_IRRL_PSN_M,
4161 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
4162
4163 roce_set_field(qpc_mask->byte_240_irrl_tail,
4164 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
4165 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
4166
926a01dc
WHX		 4167 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4168 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
4169 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
4170
4171 roce_set_bit(qpc_mask->byte_248_ack_psn,
4172 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
4173
4174 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
4175 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
4176
926a01dc
WHX		 4177 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4178 V2_QPC_BYTE_212_LSN_S, 0x100);
4179 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
4180 V2_QPC_BYTE_212_LSN_S, 0);
4181
926a01dc
WHX		 4182 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
4183 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
926a01dc
WHX		 4184
4185 return 0;
4186}
4187
606bf89e
LO		 4188static int hns_roce_v2_set_path(struct ib_qp *ibqp,
4189 const struct ib_qp_attr *attr,
4190 int attr_mask,
4191 struct hns_roce_v2_qp_context *context,
4192 struct hns_roce_v2_qp_context *qpc_mask)
926a01dc 4193{
606bf89e 4194 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
926a01dc
WHX		 4195 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4196 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
ae1c6148 4197 struct ib_device *ibdev = &hr_dev->ib_dev;
606bf89e
LO		 4198 const struct ib_gid_attr *gid_attr = NULL;
4199 int is_roce_protocol;
32883228 4200 u16 vlan_id = 0xffff;
606bf89e 4201 bool is_udp = false;
606bf89e
LO		 4202 u8 ib_port;
4203 u8 hr_port;
4204 int ret;
926a01dc 4205
606bf89e
LO		 4206 ib_port = (attr_mask & IB_QP_PORT) ? attr->port_num : hr_qp->port + 1;
4207 hr_port = ib_port - 1;
4208 is_roce_protocol = rdma_cap_eth_ah(&hr_dev->ib_dev, ib_port) &&
4209 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
4210
4211 if (is_roce_protocol) {
4212 gid_attr = attr->ah_attr.grh.sgid_attr;
32883228 4213 ret = rdma_read_gid_l2_fields(gid_attr, &vlan_id, NULL);
606bf89e
LO		 4214 if (ret)
4215 return ret;
4216
4217 if (gid_attr)
4218 is_udp = (gid_attr->gid_type ==
4219 IB_GID_TYPE_ROCE_UDP_ENCAP);
4220 }
4221
32883228 4222 if (vlan_id < VLAN_N_VID) {
606bf89e
LO		 4223 roce_set_bit(context->byte_76_srqn_op_en,
4224 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 1);
4225 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
4226 V2_QPC_BYTE_76_RQ_VLAN_EN_S, 0);
4227 roce_set_bit(context->byte_168_irrl_idx,
4228 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 1);
4229 roce_set_bit(qpc_mask->byte_168_irrl_idx,
4230 V2_QPC_BYTE_168_SQ_VLAN_EN_S, 0);
4231 }
4232
4233 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
32883228 4234 V2_QPC_BYTE_24_VLAN_ID_S, vlan_id);
606bf89e
LO		 4235 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_ID_M,
4236 V2_QPC_BYTE_24_VLAN_ID_S, 0);
4237
4238 if (grh->sgid_index >= hr_dev->caps.gid_table_len[hr_port]) {
ae1c6148
LO		 4239 ibdev_err(ibdev, "sgid_index(%u) too large. max is %d\n",
4240 grh->sgid_index, hr_dev->caps.gid_table_len[hr_port]);
606bf89e
LO		 4241 return -EINVAL;
4242 }
4243
4244 if (attr->ah_attr.type != RDMA_AH_ATTR_TYPE_ROCE) {
ae1c6148 4245 ibdev_err(ibdev, "ah attr is not RDMA roce type\n");
606bf89e
LO		 4246 return -EINVAL;
4247 }
4248
4249 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4250 V2_QPC_BYTE_52_UDPSPN_S,
4251 is_udp ? 0x12b7 : 0);
4252
4253 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_UDPSPN_M,
4254 V2_QPC_BYTE_52_UDPSPN_S, 0);
4255
4256 roce_set_field(context->byte_20_smac_sgid_idx,
4257 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S,
4258 grh->sgid_index);
4259
4260 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
4261 V2_QPC_BYTE_20_SGID_IDX_M, V2_QPC_BYTE_20_SGID_IDX_S, 0);
4262
4263 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4264 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
4265 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
4266 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
4267
dfaf2854 4268 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP08_B && is_udp)
606bf89e
LO		 4269 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4270 V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2);
4271 else
4272 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4273 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
4274 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
4275 V2_QPC_BYTE_24_TC_S, 0);
4276 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4277 V2_QPC_BYTE_28_FL_S, grh->flow_label);
4278 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
4279 V2_QPC_BYTE_28_FL_S, 0);
4280 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
4281 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
4282 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4283 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr));
4284 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
4285 V2_QPC_BYTE_28_SL_S, 0);
4286 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
4287
4288 return 0;
4289}
4290
357f3429
LC		 4291static bool check_qp_state(enum ib_qp_state cur_state,
4292 enum ib_qp_state new_state)
4293{
4294 static const bool sm[][IB_QPS_ERR + 1] = {
4295 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
4296 [IB_QPS_INIT] = true },
4297 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
4298 [IB_QPS_INIT] = true,
4299 [IB_QPS_RTR] = true,
4300 [IB_QPS_ERR] = true },
4301 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
4302 [IB_QPS_RTS] = true,
4303 [IB_QPS_ERR] = true },
4304 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
4305 [IB_QPS_SQD] = {},
4306 [IB_QPS_SQE] = {},
4307 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
4308 };
4309
4310 return sm[cur_state][new_state];
4311}
4312
606bf89e
LO		 4313static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp,
4314 const struct ib_qp_attr *attr,
4315 int attr_mask,
4316 enum ib_qp_state cur_state,
4317 enum ib_qp_state new_state,
4318 struct hns_roce_v2_qp_context *context,
4319 struct hns_roce_v2_qp_context *qpc_mask)
4320{
4321 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4322 int ret = 0;
926a01dc 4323
357f3429
LC		 4324 if (!check_qp_state(cur_state, new_state)) {
4325 ibdev_err(&hr_dev->ib_dev, "Illegal state for QP!\n");
4326 return -EINVAL;
4327 }
4328
926a01dc 4329 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
9f507101 4330 memset(qpc_mask, 0, sizeof(*qpc_mask));
0fa95a9a 4331 modify_qp_reset_to_init(ibqp, attr, attr_mask, context,
4332 qpc_mask);
926a01dc
WHX		 4333 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
4334 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
4335 qpc_mask);
4336 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
4337 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
4338 qpc_mask);
926a01dc
WHX		 4339 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
4340 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
4341 qpc_mask);
926a01dc
WHX		 4342 }
4343
606bf89e
LO		 4344 return ret;
4345}
9c6ccc03 4346
606bf89e
LO		 4347static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp,
4348 const struct ib_qp_attr *attr,
4349 int attr_mask,
4350 struct hns_roce_v2_qp_context *context,
4351 struct hns_roce_v2_qp_context *qpc_mask)
4352{
4353 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4354 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4355 int ret = 0;
0425e3e6 4356
610b8967 4357 if (attr_mask & IB_QP_AV) {
606bf89e
LO		 4358 ret = hns_roce_v2_set_path(ibqp, attr, attr_mask, context,
4359 qpc_mask);
4360 if (ret)
4361 return ret;
610b8967
LO		 4362 }
4363
5b01b243
LO		 4364 if (attr_mask & IB_QP_TIMEOUT) {
4365 if (attr->timeout < 31) {
4366 roce_set_field(context->byte_28_at_fl,
4367 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4368 attr->timeout);
4369 roce_set_field(qpc_mask->byte_28_at_fl,
4370 V2_QPC_BYTE_28_AT_M, V2_QPC_BYTE_28_AT_S,
4371 0);
4372 } else {
ae1c6148
LO		 4373 ibdev_warn(&hr_dev->ib_dev,
4374 "Local ACK timeout shall be 0 to 30.\n");
5b01b243
LO		 4375 }
4376 }
4377
4378 if (attr_mask & IB_QP_RETRY_CNT) {
4379 roce_set_field(context->byte_212_lsn,
4380 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4381 V2_QPC_BYTE_212_RETRY_NUM_INIT_S,
4382 attr->retry_cnt);
4383 roce_set_field(qpc_mask->byte_212_lsn,
4384 V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
4385 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
4386
4387 roce_set_field(context->byte_212_lsn,
4388 V2_QPC_BYTE_212_RETRY_CNT_M,
60262b10 4389 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
5b01b243
LO		 4390 roce_set_field(qpc_mask->byte_212_lsn,
4391 V2_QPC_BYTE_212_RETRY_CNT_M,
4392 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
4393 }
4394
4395 if (attr_mask & IB_QP_RNR_RETRY) {
4396 roce_set_field(context->byte_244_rnr_rxack,
4397 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4398 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
4399 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4400 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
4401 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
4402
4403 roce_set_field(context->byte_244_rnr_rxack,
4404 V2_QPC_BYTE_244_RNR_CNT_M,
4405 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
4406 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4407 V2_QPC_BYTE_244_RNR_CNT_M,
4408 V2_QPC_BYTE_244_RNR_CNT_S, 0);
4409 }
4410
606bf89e 4411 /* RC&UC&UD required attr */
f04cc178
LO		 4412 if (attr_mask & IB_QP_SQ_PSN) {
4413 roce_set_field(context->byte_172_sq_psn,
4414 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4415 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
4416 roce_set_field(qpc_mask->byte_172_sq_psn,
4417 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4418 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
4419
4420 roce_set_field(context->byte_196_sq_psn,
4421 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4422 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
4423 roce_set_field(qpc_mask->byte_196_sq_psn,
4424 V2_QPC_BYTE_196_SQ_MAX_PSN_M,
4425 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
4426
4427 roce_set_field(context->byte_220_retry_psn_msn,
4428 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4429 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
4430 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
4431 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
4432 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
4433
4434 roce_set_field(context->byte_224_retry_msg,
4435 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4436 V2_QPC_BYTE_224_RETRY_MSG_PSN_S,
2a3d923f 4437 attr->sq_psn >> V2_QPC_BYTE_220_RETRY_MSG_PSN_S);
f04cc178
LO		 4438 roce_set_field(qpc_mask->byte_224_retry_msg,
4439 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
4440 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
4441
4442 roce_set_field(context->byte_224_retry_msg,
4443 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4444 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S,
4445 attr->sq_psn);
4446 roce_set_field(qpc_mask->byte_224_retry_msg,
4447 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
4448 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
4449
4450 roce_set_field(context->byte_244_rnr_rxack,
4451 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4452 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
4453 roce_set_field(qpc_mask->byte_244_rnr_rxack,
4454 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
4455 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
4456 }
4457
5b01b243
LO		 4458 if ((attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) &&
4459 attr->max_dest_rd_atomic) {
4460 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4461 V2_QPC_BYTE_140_RR_MAX_S,
4462 fls(attr->max_dest_rd_atomic - 1));
4463 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
4464 V2_QPC_BYTE_140_RR_MAX_S, 0);
4465 }
4466
4467 if ((attr_mask & IB_QP_MAX_QP_RD_ATOMIC) && attr->max_rd_atomic) {
4468 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
4469 V2_QPC_BYTE_208_SR_MAX_S,
4470 fls(attr->max_rd_atomic - 1));
4471 roce_set_field(qpc_mask->byte_208_irrl,
4472 V2_QPC_BYTE_208_SR_MAX_M,
4473 V2_QPC_BYTE_208_SR_MAX_S, 0);
4474 }
4475
ace1c541 4476 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
4477 set_access_flags(hr_qp, context, qpc_mask, attr, attr_mask);
4478
5b01b243
LO		 4479 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
4480 roce_set_field(context->byte_80_rnr_rx_cqn,
4481 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4482 V2_QPC_BYTE_80_MIN_RNR_TIME_S,
4483 attr->min_rnr_timer);
4484 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
4485 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4486 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
4487 }
4488
601f3e6d
LO		 4489 /* RC&UC required attr */
4490 if (attr_mask & IB_QP_RQ_PSN) {
4491 roce_set_field(context->byte_108_rx_reqepsn,
4492 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4493 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
4494 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
4495 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4496 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
4497
4498 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
4499 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
4500 roce_set_field(qpc_mask->byte_152_raq,
4501 V2_QPC_BYTE_152_RAQ_PSN_M,
4502 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
4503 }
4504
5b01b243 4505 if (attr_mask & IB_QP_QKEY) {
bfe86035 4506 context->qkey_xrcd = cpu_to_le32(attr->qkey);
5b01b243
LO		 4507 qpc_mask->qkey_xrcd = 0;
4508 hr_qp->qkey = attr->qkey;
4509 }
4510
606bf89e
LO		 4511 return ret;
4512}
4513
4514static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp,
4515 const struct ib_qp_attr *attr,
4516 int attr_mask)
4517{
4518 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4519 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4520
4521 if (attr_mask & IB_QP_ACCESS_FLAGS)
4522 hr_qp->atomic_rd_en = attr->qp_access_flags;
4523
4524 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
4525 hr_qp->resp_depth = attr->max_dest_rd_atomic;
4526 if (attr_mask & IB_QP_PORT) {
4527 hr_qp->port = attr->port_num - 1;
4528 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
4529 }
4530}
4531
4532static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
4533 const struct ib_qp_attr *attr,
4534 int attr_mask, enum ib_qp_state cur_state,
4535 enum ib_qp_state new_state)
4536{
4537 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4538 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d
LC		 4539 struct hns_roce_v2_qp_context ctx[2];
4540 struct hns_roce_v2_qp_context *context = ctx;
4541 struct hns_roce_v2_qp_context *qpc_mask = ctx + 1;
ae1c6148 4542 struct ib_device *ibdev = &hr_dev->ib_dev;
b5374286
YL		 4543 unsigned long sq_flag = 0;
4544 unsigned long rq_flag = 0;
b5c229dc 4545 int ret;
606bf89e 4546
606bf89e
LO		 4547 /*
4548 * In v2 engine, software pass context and context mask to hardware
4549 * when modifying qp. If software need modify some fields in context,
4550 * we should set all bits of the relevant fields in context mask to
4551 * 0 at the same time, else set them to 0x1.
4552 */
4b42d05d 4553 memset(context, 0, sizeof(*context));
606bf89e
LO		 4554 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
4555 ret = hns_roce_v2_set_abs_fields(ibqp, attr, attr_mask, cur_state,
4556 new_state, context, qpc_mask);
4557 if (ret)
4558 goto out;
4559
4560 /* When QP state is err, SQ and RQ WQE should be flushed */
4561 if (new_state == IB_QPS_ERR) {
b5374286 4562 spin_lock_irqsave(&hr_qp->sq.lock, sq_flag);
b5374286 4563 hr_qp->state = IB_QPS_ERR;
606bf89e
LO		 4564 roce_set_field(context->byte_160_sq_ci_pi,
4565 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4566 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S,
4567 hr_qp->sq.head);
4568 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
4569 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
4570 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
75c994e6 4571 spin_unlock_irqrestore(&hr_qp->sq.lock, sq_flag);
606bf89e
LO		 4572
4573 if (!ibqp->srq) {
75c994e6 4574 spin_lock_irqsave(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4575 roce_set_field(context->byte_84_rq_ci_pi,
4576 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4577 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S,
4578 hr_qp->rq.head);
4579 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
4580 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
4581 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
75c994e6 4582 spin_unlock_irqrestore(&hr_qp->rq.lock, rq_flag);
606bf89e
LO		 4583 }
4584 }
4585
4586 /* Configure the optional fields */
4587 ret = hns_roce_v2_set_opt_fields(ibqp, attr, attr_mask, context,
4588 qpc_mask);
4589 if (ret)
4590 goto out;
4591
c7bcb134
LO		 4592 roce_set_bit(context->byte_108_rx_reqepsn, V2_QPC_BYTE_108_INV_CREDIT_S,
4593 ibqp->srq ? 1 : 0);
4594 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
4595 V2_QPC_BYTE_108_INV_CREDIT_S, 0);
4596
926a01dc 4597 /* Every status migrate must change state */
2362ccee 4598 roce_set_field(context->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc 4599 V2_QPC_BYTE_60_QP_ST_S, new_state);
2362ccee 4600 roce_set_field(qpc_mask->byte_60_qpst_tempid, V2_QPC_BYTE_60_QP_ST_M,
926a01dc
WHX		 4601 V2_QPC_BYTE_60_QP_ST_S, 0);
4602
4603 /* SW pass context to HW */
032b0574 4604 ret = hns_roce_v2_qp_modify(hr_dev, ctx, hr_qp);
926a01dc 4605 if (ret) {
ae1c6148 4606 ibdev_err(ibdev, "failed to modify QP, ret = %d\n", ret);
926a01dc
WHX		 4607 goto out;
4608 }
4609
4610 hr_qp->state = new_state;
4611
606bf89e 4612 hns_roce_v2_record_opt_fields(ibqp, attr, attr_mask);
926a01dc
WHX		 4613
4614 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
4615 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
4616 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
4617 if (ibqp->send_cq != ibqp->recv_cq)
4618 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
4619 hr_qp->qpn, NULL);
4620
4621 hr_qp->rq.head = 0;
4622 hr_qp->rq.tail = 0;
4623 hr_qp->sq.head = 0;
4624 hr_qp->sq.tail = 0;
926a01dc 4625 hr_qp->next_sge = 0;
e088a685
YL		 4626 if (hr_qp->rq.wqe_cnt)
4627 *hr_qp->rdb.db_record = 0;
926a01dc
WHX		 4628 }
4629
4630out:
926a01dc
WHX		 4631 return ret;
4632}
4633
a3de9e83 4634static int to_ib_qp_st(enum hns_roce_v2_qp_state state)
926a01dc 4635{
a3de9e83
LC		 4636 static const enum ib_qp_state map[] = {
4637 [HNS_ROCE_QP_ST_RST] = IB_QPS_RESET,
4638 [HNS_ROCE_QP_ST_INIT] = IB_QPS_INIT,
4639 [HNS_ROCE_QP_ST_RTR] = IB_QPS_RTR,
4640 [HNS_ROCE_QP_ST_RTS] = IB_QPS_RTS,
4641 [HNS_ROCE_QP_ST_SQD] = IB_QPS_SQD,
4642 [HNS_ROCE_QP_ST_SQER] = IB_QPS_SQE,
4643 [HNS_ROCE_QP_ST_ERR] = IB_QPS_ERR,
4644 [HNS_ROCE_QP_ST_SQ_DRAINING] = IB_QPS_SQD
4645 };
4646
4647 return (state < ARRAY_SIZE(map)) ? map[state] : -1;
926a01dc
WHX		 4648}
4649
4650static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
4651 struct hns_roce_qp *hr_qp,
4652 struct hns_roce_v2_qp_context *hr_context)
4653{
4654 struct hns_roce_cmd_mailbox *mailbox;
4655 int ret;
4656
4657 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
4658 if (IS_ERR(mailbox))
4659 return PTR_ERR(mailbox);
4660
4661 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
4662 HNS_ROCE_CMD_QUERY_QPC,
4663 HNS_ROCE_CMD_TIMEOUT_MSECS);
ae1c6148 4664 if (ret)
926a01dc 4665 goto out;
926a01dc
WHX		 4666
4667 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
4668
4669out:
4670 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
4671 return ret;
4672}
4673
4674static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4675 int qp_attr_mask,
4676 struct ib_qp_init_attr *qp_init_attr)
4677{
4678 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4679 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4b42d05d 4680 struct hns_roce_v2_qp_context context = {};
ae1c6148 4681 struct ib_device *ibdev = &hr_dev->ib_dev;
926a01dc
WHX		 4682 int tmp_qp_state;
4683 int state;
4684 int ret;
4685
926a01dc
WHX		 4686 memset(qp_attr, 0, sizeof(*qp_attr));
4687 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4688
4689 mutex_lock(&hr_qp->mutex);
4690
4691 if (hr_qp->state == IB_QPS_RESET) {
4692 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 4693 ret = 0;
926a01dc
WHX		 4694 goto done;
4695 }
4696
4b42d05d 4697 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, &context);
926a01dc 4698 if (ret) {
ae1c6148 4699 ibdev_err(ibdev, "failed to query QPC, ret = %d\n", ret);
926a01dc
WHX		 4700 ret = -EINVAL;
4701 goto out;
4702 }
4703
4b42d05d 4704 state = roce_get_field(context.byte_60_qpst_tempid,
926a01dc
WHX		 4705 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
4706 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
4707 if (tmp_qp_state == -1) {
ae1c6148 4708 ibdev_err(ibdev, "Illegal ib_qp_state\n");
926a01dc
WHX		 4709 ret = -EINVAL;
4710 goto out;
4711 }
4712 hr_qp->state = (u8)tmp_qp_state;
4713 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
4b42d05d 4714 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4715 V2_QPC_BYTE_24_MTU_M,
4716 V2_QPC_BYTE_24_MTU_S);
4717 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 4718 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc 4719 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
349be276 4720 qp_attr->qkey = le32_to_cpu(context.qkey_xrcd);
926a01dc 4721
4b42d05d 4722 qp_attr->rq_psn = roce_get_field(context.byte_108_rx_reqepsn,
926a01dc
WHX		 4723 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
4724 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
4b42d05d 4725 qp_attr->sq_psn = (u32)roce_get_field(context.byte_172_sq_psn,
926a01dc
WHX		 4726 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
4727 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
4b42d05d 4728 qp_attr->dest_qp_num = (u8)roce_get_field(context.byte_56_dqpn_err,
926a01dc
WHX		 4729 V2_QPC_BYTE_56_DQPN_M,
4730 V2_QPC_BYTE_56_DQPN_S);
4b42d05d 4731 qp_attr->qp_access_flags = ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4732 V2_QPC_BYTE_76_RRE_S)) << V2_QP_RRE_S) |
4b42d05d 4733 ((roce_get_bit(context.byte_76_srqn_op_en,
98c09b8c 4734 V2_QPC_BYTE_76_RWE_S)) << V2_QP_RWE_S) |
4b42d05d 4735 ((roce_get_bit(context.byte_76_srqn_op_en,
2a3d923f
LO		 4736 V2_QPC_BYTE_76_ATE_S)) << V2_QP_ATE_S);
4737
926a01dc
WHX		 4738 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
4739 hr_qp->ibqp.qp_type == IB_QPT_UC) {
4740 struct ib_global_route *grh =
4741 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
4742
4743 rdma_ah_set_sl(&qp_attr->ah_attr,
4b42d05d 4744 roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4745 V2_QPC_BYTE_28_SL_M,
4746 V2_QPC_BYTE_28_SL_S));
4b42d05d 4747 grh->flow_label = roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4748 V2_QPC_BYTE_28_FL_M,
4749 V2_QPC_BYTE_28_FL_S);
4b42d05d 4750 grh->sgid_index = roce_get_field(context.byte_20_smac_sgid_idx,
926a01dc
WHX		 4751 V2_QPC_BYTE_20_SGID_IDX_M,
4752 V2_QPC_BYTE_20_SGID_IDX_S);
4b42d05d 4753 grh->hop_limit = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4754 V2_QPC_BYTE_24_HOP_LIMIT_M,
4755 V2_QPC_BYTE_24_HOP_LIMIT_S);
4b42d05d 4756 grh->traffic_class = roce_get_field(context.byte_24_mtu_tc,
926a01dc
WHX		 4757 V2_QPC_BYTE_24_TC_M,
4758 V2_QPC_BYTE_24_TC_S);
4759
4b42d05d 4760 memcpy(grh->dgid.raw, context.dgid, sizeof(grh->dgid.raw));
926a01dc
WHX		 4761 }
4762
4763 qp_attr->port_num = hr_qp->port + 1;
4764 qp_attr->sq_draining = 0;
4b42d05d 4765 qp_attr->max_rd_atomic = 1 << roce_get_field(context.byte_208_irrl,
926a01dc
WHX		 4766 V2_QPC_BYTE_208_SR_MAX_M,
4767 V2_QPC_BYTE_208_SR_MAX_S);
4b42d05d 4768 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context.byte_140_raq,
926a01dc
WHX		 4769 V2_QPC_BYTE_140_RR_MAX_M,
4770 V2_QPC_BYTE_140_RR_MAX_S);
4b42d05d 4771 qp_attr->min_rnr_timer = (u8)roce_get_field(context.byte_80_rnr_rx_cqn,
926a01dc
WHX		 4772 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
4773 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
4b42d05d 4774 qp_attr->timeout = (u8)roce_get_field(context.byte_28_at_fl,
926a01dc
WHX		 4775 V2_QPC_BYTE_28_AT_M,
4776 V2_QPC_BYTE_28_AT_S);
4b42d05d 4777 qp_attr->retry_cnt = roce_get_field(context.byte_212_lsn,
926a01dc
WHX		 4778 V2_QPC_BYTE_212_RETRY_CNT_M,
4779 V2_QPC_BYTE_212_RETRY_CNT_S);
bfe86035 4780 qp_attr->rnr_retry = le32_to_cpu(context.rq_rnr_timer);
926a01dc
WHX		 4781
4782done:
4783 qp_attr->cur_qp_state = qp_attr->qp_state;
4784 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
4785 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
4786
4787 if (!ibqp->uobject) {
4788 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
4789 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
4790 } else {
4791 qp_attr->cap.max_send_wr = 0;
4792 qp_attr->cap.max_send_sge = 0;
4793 }
4794
4795 qp_init_attr->cap = qp_attr->cap;
4796
4797out:
4798 mutex_unlock(&hr_qp->mutex);
926a01dc
WHX		 4799 return ret;
4800}
4801
4802static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
4803 struct hns_roce_qp *hr_qp,
bdeacabd 4804 struct ib_udata *udata)
926a01dc 4805{
db50077b 4806 struct ib_device *ibdev = &hr_dev->ib_dev;
ae1c6148 4807 struct hns_roce_cq *send_cq, *recv_cq;
626903e9 4808 unsigned long flags;
d302c6e3 4809 int ret = 0;
926a01dc
WHX		 4810
4811 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
4812 /* Modify qp to reset before destroying qp */
4813 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
4814 hr_qp->state, IB_QPS_RESET);
d302c6e3 4815 if (ret)
ae1c6148
LO		 4816 ibdev_err(ibdev,
4817 "failed to modify QP to RST, ret = %d\n",
4818 ret);
926a01dc
WHX		 4819 }
4820
626903e9
XW		 4821 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
4822 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
926a01dc 4823
626903e9 4824 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
926a01dc
WHX		 4825 hns_roce_lock_cqs(send_cq, recv_cq);
4826
bdeacabd 4827 if (!udata) {
626903e9
XW		 4828 if (recv_cq)
4829 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn,
4830 (hr_qp->ibqp.srq ?
4831 to_hr_srq(hr_qp->ibqp.srq) :
4832 NULL));
4833
4834 if (send_cq && send_cq != recv_cq)
926a01dc 4835 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
626903e9 4836
926a01dc
WHX		 4837 }
4838
4839 hns_roce_qp_remove(hr_dev, hr_qp);
4840
4841 hns_roce_unlock_cqs(send_cq, recv_cq);
626903e9 4842 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
926a01dc 4843
d302c6e3 4844 return ret;
926a01dc
WHX		 4845}
4846
c4367a26 4847static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
926a01dc
WHX		 4848{
4849 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
4850 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
4851 int ret;
4852
bdeacabd 4853 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
d302c6e3 4854 if (ret)
ae1c6148
LO		 4855 ibdev_err(&hr_dev->ib_dev,
4856 "failed to destroy QP 0x%06lx, ret = %d\n",
db50077b 4857 hr_qp->qpn, ret);
926a01dc 4858
e365b26c 4859 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
926a01dc
WHX		 4860
4861 return 0;
4862}
4863
aa84fa18 4864static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev,
ae1c6148 4865 struct hns_roce_qp *hr_qp)
aa84fa18 4866{
ae1c6148 4867 struct ib_device *ibdev = &hr_dev->ib_dev;
da91ddfd 4868 struct hns_roce_sccc_clr_done *resp;
aa84fa18
YL		 4869 struct hns_roce_sccc_clr *clr;
4870 struct hns_roce_cmq_desc desc;
4871 int ret, i;
4872
4873 mutex_lock(&hr_dev->qp_table.scc_mutex);
4874
4875 /* set scc ctx clear done flag */
4876 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_RESET_SCCC, false);
aa84fa18
YL		 4877 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4878 if (ret) {
ae1c6148 4879 ibdev_err(ibdev, "failed to reset SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4880 goto out;
4881 }
4882
4883 /* clear scc context */
4884 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CLR_SCCC, false);
4885 clr = (struct hns_roce_sccc_clr *)desc.data;
4886 clr->qpn = cpu_to_le32(hr_qp->qpn);
4887 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4888 if (ret) {
ae1c6148 4889 ibdev_err(ibdev, "failed to clear SCC ctx, ret = %d\n", ret);
aa84fa18
YL		 4890 goto out;
4891 }
4892
4893 /* query scc context clear is done or not */
4894 resp = (struct hns_roce_sccc_clr_done *)desc.data;
4895 for (i = 0; i <= HNS_ROCE_CMQ_SCC_CLR_DONE_CNT; i++) {
4896 hns_roce_cmq_setup_basic_desc(&desc,
4897 HNS_ROCE_OPC_QUERY_SCCC, true);
4898 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
4899 if (ret) {
ae1c6148
LO		 4900 ibdev_err(ibdev, "failed to query clr cmq, ret = %d\n",
4901 ret);
aa84fa18
YL		 4902 goto out;
4903 }
4904
4905 if (resp->clr_done)
4906 goto out;
4907
4908 msleep(20);
4909 }
4910
ae1c6148 4911 ibdev_err(ibdev, "Query SCC clr done flag overtime.\n");
aa84fa18
YL		 4912 ret = -ETIMEDOUT;
4913
4914out:
4915 mutex_unlock(&hr_dev->qp_table.scc_mutex);
4916 return ret;
4917}
4918
ffb1308b
YL		 4919static void hns_roce_v2_write_srqc(struct hns_roce_dev *hr_dev,
4920 struct hns_roce_srq *srq, u32 pdn, u16 xrcd,
4921 u32 cqn, void *mb_buf, u64 *mtts_wqe,
4922 u64 *mtts_idx, dma_addr_t dma_handle_wqe,
4923 dma_addr_t dma_handle_idx)
b156269d 4924{
ffb1308b 4925 struct hns_roce_srq_context *srq_context;
b156269d 4926
ffb1308b
YL		 4927 srq_context = mb_buf;
4928 memset(srq_context, 0, sizeof(*srq_context));
b156269d 4929
ffb1308b
YL		 4930 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQ_ST_M,
4931 SRQC_BYTE_4_SRQ_ST_S, 1);
b156269d 4932
ffb1308b
YL		 4933 roce_set_field(srq_context->byte_4_srqn_srqst,
4934 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_M,
4935 SRQC_BYTE_4_SRQ_WQE_HOP_NUM_S,
67954a6e
XW		 4936 to_hr_hem_hopnum(hr_dev->caps.srqwqe_hop_num,
4937 srq->wqe_cnt));
ffb1308b
YL		 4938 roce_set_field(srq_context->byte_4_srqn_srqst,
4939 SRQC_BYTE_4_SRQ_SHIFT_M, SRQC_BYTE_4_SRQ_SHIFT_S,
4940 ilog2(srq->wqe_cnt));
b156269d 4941
ffb1308b
YL		 4942 roce_set_field(srq_context->byte_4_srqn_srqst, SRQC_BYTE_4_SRQN_M,
4943 SRQC_BYTE_4_SRQN_S, srq->srqn);
b156269d 4944
ffb1308b
YL		 4945 roce_set_field(srq_context->byte_8_limit_wl, SRQC_BYTE_8_SRQ_LIMIT_WL_M,
4946 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
b156269d 4947
ffb1308b
YL		 4948 roce_set_field(srq_context->byte_12_xrcd, SRQC_BYTE_12_SRQ_XRCD_M,
4949 SRQC_BYTE_12_SRQ_XRCD_S, xrcd);
0425e3e6 4950
ffb1308b 4951 srq_context->wqe_bt_ba = cpu_to_le32((u32)(dma_handle_wqe >> 3));
0425e3e6 4952
ffb1308b
YL		 4953 roce_set_field(srq_context->byte_24_wqe_bt_ba,
4954 SRQC_BYTE_24_SRQ_WQE_BT_BA_M,
4955 SRQC_BYTE_24_SRQ_WQE_BT_BA_S,
4956 dma_handle_wqe >> 35);
4957
4958 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_PD_M,
4959 SRQC_BYTE_28_PD_S, pdn);
4960 roce_set_field(srq_context->byte_28_rqws_pd, SRQC_BYTE_28_RQWS_M,
4961 SRQC_BYTE_28_RQWS_S, srq->max_gs <= 0 ? 0 :
4962 fls(srq->max_gs - 1));
4963
4964 srq_context->idx_bt_ba = cpu_to_le32(dma_handle_idx >> 3);
4965 roce_set_field(srq_context->rsv_idx_bt_ba,
4966 SRQC_BYTE_36_SRQ_IDX_BT_BA_M,
4967 SRQC_BYTE_36_SRQ_IDX_BT_BA_S,
4968 dma_handle_idx >> 35);
4969
4970 srq_context->idx_cur_blk_addr =
4971 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[0]));
4972 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
4973 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_M,
4974 SRQC_BYTE_44_SRQ_IDX_CUR_BLK_ADDR_S,
4975 upper_32_bits(to_hr_hw_page_addr(mtts_idx[0])));
4976 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
4977 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_M,
4978 SRQC_BYTE_44_SRQ_IDX_HOP_NUM_S,
67954a6e
XW		 4979 to_hr_hem_hopnum(hr_dev->caps.idx_hop_num,
4980 srq->wqe_cnt));
ffb1308b
YL		 4981
4982 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
4983 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_M,
4984 SRQC_BYTE_44_SRQ_IDX_BA_PG_SZ_S,
4985 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.ba_pg_shift));
4986 roce_set_field(srq_context->byte_44_idxbufpgsz_addr,
4987 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_M,
4988 SRQC_BYTE_44_SRQ_IDX_BUF_PG_SZ_S,
4989 to_hr_hw_page_shift(srq->idx_que.mtr.hem_cfg.buf_pg_shift));
4990
4991 srq_context->idx_nxt_blk_addr =
4992 cpu_to_le32(to_hr_hw_page_addr(mtts_idx[1]));
4993 roce_set_field(srq_context->rsv_idxnxtblkaddr,
4994 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_M,
4995 SRQC_BYTE_52_SRQ_IDX_NXT_BLK_ADDR_S,
4996 upper_32_bits(to_hr_hw_page_addr(mtts_idx[1])));
4997 roce_set_field(srq_context->byte_56_xrc_cqn,
4998 SRQC_BYTE_56_SRQ_XRC_CQN_M, SRQC_BYTE_56_SRQ_XRC_CQN_S,
4999 cqn);
5000 roce_set_field(srq_context->byte_56_xrc_cqn,
5001 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_M,
5002 SRQC_BYTE_56_SRQ_WQE_BA_PG_SZ_S,
5003 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.ba_pg_shift));
5004 roce_set_field(srq_context->byte_56_xrc_cqn,
5005 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_M,
5006 SRQC_BYTE_56_SRQ_WQE_BUF_PG_SZ_S,
5007 to_hr_hw_page_shift(srq->buf_mtr.hem_cfg.buf_pg_shift));
5008
5009 roce_set_bit(srq_context->db_record_addr_record_en,
5010 SRQC_BYTE_60_SRQ_RECORD_EN_S, 0);
5011}
5012
5013static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq,
5014 struct ib_srq_attr *srq_attr,
5015 enum ib_srq_attr_mask srq_attr_mask,
5016 struct ib_udata *udata)
5017{
5018 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5019 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5020 struct hns_roce_srq_context *srq_context;
5021 struct hns_roce_srq_context *srqc_mask;
5022 struct hns_roce_cmd_mailbox *mailbox;
5023 int ret;
5024
5025 if (srq_attr_mask & IB_SRQ_LIMIT) {
5026 if (srq_attr->srq_limit >= srq->wqe_cnt)
5027 return -EINVAL;
5028
5029 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5030 if (IS_ERR(mailbox))
5031 return PTR_ERR(mailbox);
5032
5033 srq_context = mailbox->buf;
5034 srqc_mask = (struct hns_roce_srq_context *)mailbox->buf + 1;
5035
5036 memset(srqc_mask, 0xff, sizeof(*srqc_mask));
5037
5038 roce_set_field(srq_context->byte_8_limit_wl,
5039 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5040 SRQC_BYTE_8_SRQ_LIMIT_WL_S, srq_attr->srq_limit);
5041 roce_set_field(srqc_mask->byte_8_limit_wl,
5042 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5043 SRQC_BYTE_8_SRQ_LIMIT_WL_S, 0);
5044
5045 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, srq->srqn, 0,
5046 HNS_ROCE_CMD_MODIFY_SRQC,
5047 HNS_ROCE_CMD_TIMEOUT_MSECS);
5048 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5049 if (ret) {
5050 ibdev_err(&hr_dev->ib_dev,
5051 "failed to handle cmd of modifying SRQ, ret = %d.\n",
5052 ret);
5053 return ret;
5054 }
5055 }
5056
5057 return 0;
5058}
5059
5060static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
5061{
5062 struct hns_roce_dev *hr_dev = to_hr_dev(ibsrq->device);
5063 struct hns_roce_srq *srq = to_hr_srq(ibsrq);
5064 struct hns_roce_srq_context *srq_context;
5065 struct hns_roce_cmd_mailbox *mailbox;
5066 int limit_wl;
5067 int ret;
5068
5069 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5070 if (IS_ERR(mailbox))
5071 return PTR_ERR(mailbox);
5072
5073 srq_context = mailbox->buf;
5074 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, srq->srqn, 0,
5075 HNS_ROCE_CMD_QUERY_SRQC,
5076 HNS_ROCE_CMD_TIMEOUT_MSECS);
5077 if (ret) {
5078 ibdev_err(&hr_dev->ib_dev,
5079 "failed to process cmd of querying SRQ, ret = %d.\n",
5080 ret);
5081 goto out;
5082 }
5083
5084 limit_wl = roce_get_field(srq_context->byte_8_limit_wl,
5085 SRQC_BYTE_8_SRQ_LIMIT_WL_M,
5086 SRQC_BYTE_8_SRQ_LIMIT_WL_S);
5087
5088 attr->srq_limit = limit_wl;
6968aeb5 5089 attr->max_wr = srq->wqe_cnt - 1;
711195e5 5090 attr->max_sge = srq->max_gs - HNS_ROCE_RESERVED_SGE;
ffb1308b 5091
ffb1308b
YL		 5092out:
5093 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5094 return ret;
5095}
5096
5097static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
5098{
5099 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
5100 struct hns_roce_v2_cq_context *cq_context;
5101 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
5102 struct hns_roce_v2_cq_context *cqc_mask;
5103 struct hns_roce_cmd_mailbox *mailbox;
5104 int ret;
5105
5106 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
5107 if (IS_ERR(mailbox))
5108 return PTR_ERR(mailbox);
5109
5110 cq_context = mailbox->buf;
5111 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
5112
5113 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
5114
5115 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
5116 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
5117 cq_count);
5118 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
5119 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
5120 0);
5121 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
5122 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
5123 cq_period);
5124 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
5125 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
5126 0);
5127
5128 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
5129 HNS_ROCE_CMD_MODIFY_CQC,
5130 HNS_ROCE_CMD_TIMEOUT_MSECS);
5131 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5132 if (ret)
5133 ibdev_err(&hr_dev->ib_dev,
5134 "failed to process cmd when modifying CQ, ret = %d\n",
5135 ret);
5136
5137 return ret;
5138}
5139
5140static void hns_roce_irq_work_handle(struct work_struct *work)
5141{
5142 struct hns_roce_work *irq_work =
5143 container_of(work, struct hns_roce_work, work);
5144 struct ib_device *ibdev = &irq_work->hr_dev->ib_dev;
5145 u32 qpn = irq_work->qpn;
5146 u32 cqn = irq_work->cqn;
5147
5148 switch (irq_work->event_type) {
5149 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
5150 ibdev_info(ibdev, "Path migrated succeeded.\n");
5151 break;
5152 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
5153 ibdev_warn(ibdev, "Path migration failed.\n");
5154 break;
5155 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5156 break;
5157 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5158 ibdev_warn(ibdev, "Send queue drained.\n");
5159 break;
5160 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
5161 ibdev_err(ibdev, "Local work queue 0x%x catast error, sub_event type is: %d\n",
5162 qpn, irq_work->sub_type);
5163 break;
5164 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5165 ibdev_err(ibdev, "Invalid request local work queue 0x%x error.\n",
5166 qpn);
5167 break;
5168 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
5169 ibdev_err(ibdev, "Local access violation work queue 0x%x error, sub_event type is: %d\n",
5170 qpn, irq_work->sub_type);
5171 break;
5172 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
5173 ibdev_warn(ibdev, "SRQ limit reach.\n");
5174 break;
5175 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
5176 ibdev_warn(ibdev, "SRQ last wqe reach.\n");
5177 break;
5178 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
5179 ibdev_err(ibdev, "SRQ catas error.\n");
5180 break;
5181 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5182 ibdev_err(ibdev, "CQ 0x%x access err.\n", cqn);
5183 break;
5184 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
5185 ibdev_warn(ibdev, "CQ 0x%x overflow\n", cqn);
5186 break;
5187 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
5188 ibdev_warn(ibdev, "DB overflow.\n");
5189 break;
5190 case HNS_ROCE_EVENT_TYPE_FLR:
5191 ibdev_warn(ibdev, "Function level reset.\n");
5192 break;
5193 default:
5194 break;
5195 }
5196
5197 kfree(irq_work);
5198}
0425e3e6
YL		 5199
5200static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev,
b00a92c8 5201 struct hns_roce_eq *eq,
5202 u32 qpn, u32 cqn)
0425e3e6
YL		 5203{
5204 struct hns_roce_work *irq_work;
5205
5206 irq_work = kzalloc(sizeof(struct hns_roce_work), GFP_ATOMIC);
5207 if (!irq_work)
5208 return;
5209
5210 INIT_WORK(&(irq_work->work), hns_roce_irq_work_handle);
5211 irq_work->hr_dev = hr_dev;
5212 irq_work->qpn = qpn;
b00a92c8 5213 irq_work->cqn = cqn;
0425e3e6
YL		 5214 irq_work->event_type = eq->event_type;
5215 irq_work->sub_type = eq->sub_type;
5216 queue_work(hr_dev->irq_workq, &(irq_work->work));
5217}
5218
a5073d60
YL		 5219static void set_eq_cons_index_v2(struct hns_roce_eq *eq)
5220{
d3743fa9 5221 struct hns_roce_dev *hr_dev = eq->hr_dev;
880f133c 5222 __le32 doorbell[2] = {};
a5073d60
YL		 5223
5224 if (eq->type_flag == HNS_ROCE_AEQ) {
5225 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
5226 HNS_ROCE_V2_EQ_DB_CMD_S,
5227 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5228 HNS_ROCE_EQ_DB_CMD_AEQ :
5229 HNS_ROCE_EQ_DB_CMD_AEQ_ARMED);
5230 } else {
5231 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_TAG_M,
5232 HNS_ROCE_V2_EQ_DB_TAG_S, eq->eqn);
5233
5234 roce_set_field(doorbell[0], HNS_ROCE_V2_EQ_DB_CMD_M,
5235 HNS_ROCE_V2_EQ_DB_CMD_S,
5236 eq->arm_st == HNS_ROCE_V2_EQ_ALWAYS_ARMED ?
5237 HNS_ROCE_EQ_DB_CMD_CEQ :
5238 HNS_ROCE_EQ_DB_CMD_CEQ_ARMED);
5239 }
5240
5241 roce_set_field(doorbell[1], HNS_ROCE_V2_EQ_DB_PARA_M,
5242 HNS_ROCE_V2_EQ_DB_PARA_S,
5243 (eq->cons_index & HNS_ROCE_V2_CONS_IDX_M));
5244
d3743fa9 5245 hns_roce_write64(hr_dev, doorbell, eq->doorbell);
a5073d60
YL		 5246}
5247
a5073d60
YL		 5248static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq)
5249{
5250 struct hns_roce_aeqe *aeqe;
5251
477a0a38 5252 aeqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a
XW		 5253 (eq->cons_index & (eq->entries - 1)) *
5254 HNS_ROCE_AEQ_ENTRY_SIZE);
5255
a5073d60
YL		 5256 return (roce_get_bit(aeqe->asyn, HNS_ROCE_V2_AEQ_AEQE_OWNER_S) ^
5257 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
5258}
5259
5260static int hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev,
5261 struct hns_roce_eq *eq)
5262{
5263 struct device *dev = hr_dev->dev;
e7f40440 5264 struct hns_roce_aeqe *aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 5265 int aeqe_found = 0;
5266 int event_type;
0425e3e6 5267 int sub_type;
81fce629 5268 u32 srqn;
0425e3e6
YL		 5269 u32 qpn;
5270 u32 cqn;
a5073d60 5271
e7f40440 5272 while (aeqe) {
4044a3f4
YL		 5273 /* Make sure we read AEQ entry after we have checked the
5274 * ownership bit
5275 */
5276 dma_rmb();
a5073d60
YL		 5277
5278 event_type = roce_get_field(aeqe->asyn,
5279 HNS_ROCE_V2_AEQE_EVENT_TYPE_M,
5280 HNS_ROCE_V2_AEQE_EVENT_TYPE_S);
0425e3e6
YL		 5281 sub_type = roce_get_field(aeqe->asyn,
5282 HNS_ROCE_V2_AEQE_SUB_TYPE_M,
5283 HNS_ROCE_V2_AEQE_SUB_TYPE_S);
5284 qpn = roce_get_field(aeqe->event.qp_event.qp,
5285 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5286 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
5287 cqn = roce_get_field(aeqe->event.cq_event.cq,
5288 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5289 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
81fce629
LO		 5290 srqn = roce_get_field(aeqe->event.srq_event.srq,
5291 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M,
5292 HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S);
a5073d60
YL		 5293
5294 switch (event_type) {
5295 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
a5073d60 5296 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
a5073d60
YL		 5297 case HNS_ROCE_EVENT_TYPE_COMM_EST:
5298 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
5299 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
81fce629 5300 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
a5073d60
YL		 5301 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
5302 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
b00a92c8 5303 hns_roce_qp_event(hr_dev, qpn, event_type);
a5073d60
YL		 5304 break;
5305 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
a5073d60 5306 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
81fce629 5307 hns_roce_srq_event(hr_dev, srqn, event_type);
a5073d60
YL		 5308 break;
5309 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
5310 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
b00a92c8 5311 hns_roce_cq_event(hr_dev, cqn, event_type);
a5073d60
YL		 5312 break;
5313 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
a5073d60
YL		 5314 break;
5315 case HNS_ROCE_EVENT_TYPE_MB:
5316 hns_roce_cmd_event(hr_dev,
5317 le16_to_cpu(aeqe->event.cmd.token),
5318 aeqe->event.cmd.status,
5319 le64_to_cpu(aeqe->event.cmd.out_param));
5320 break;
5321 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
a5073d60
YL		 5322 break;
5323 case HNS_ROCE_EVENT_TYPE_FLR:
a5073d60
YL		 5324 break;
5325 default:
5326 dev_err(dev, "Unhandled event %d on EQ %d at idx %u.\n",
5327 event_type, eq->eqn, eq->cons_index);
5328 break;
790b57f6 5329 }
a5073d60 5330
0425e3e6
YL		 5331 eq->event_type = event_type;
5332 eq->sub_type = sub_type;
a5073d60
YL		 5333 ++eq->cons_index;
5334 aeqe_found = 1;
5335
249f2f92 5336 if (eq->cons_index > (2 * eq->entries - 1))
a5073d60 5337 eq->cons_index = 0;
249f2f92 5338
b00a92c8 5339 hns_roce_v2_init_irq_work(hr_dev, eq, qpn, cqn);
e7f40440
LC		 5340
5341 aeqe = next_aeqe_sw_v2(eq);
a5073d60
YL		 5342 }
5343
5344 set_eq_cons_index_v2(eq);
5345 return aeqe_found;
5346}
5347
a5073d60
YL		 5348static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq)
5349{
5350 struct hns_roce_ceqe *ceqe;
5351
477a0a38 5352 ceqe = hns_roce_buf_offset(eq->mtr.kmem,
cc23267a
XW		 5353 (eq->cons_index & (eq->entries - 1)) *
5354 HNS_ROCE_CEQ_ENTRY_SIZE);
a5073d60
YL		 5355 return (!!(roce_get_bit(ceqe->comp, HNS_ROCE_V2_CEQ_CEQE_OWNER_S))) ^
5356 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
5357}
5358
5359static int hns_roce_v2_ceq_int(struct hns_roce_dev *hr_dev,
5360 struct hns_roce_eq *eq)
5361{
e7f40440 5362 struct hns_roce_ceqe *ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5363 int ceqe_found = 0;
5364 u32 cqn;
5365
e7f40440 5366 while (ceqe) {
4044a3f4
YL		 5367 /* Make sure we read CEQ entry after we have checked the
5368 * ownership bit
5369 */
5370 dma_rmb();
5371
60262b10 5372 cqn = roce_get_field(ceqe->comp, HNS_ROCE_V2_CEQE_COMP_CQN_M,
a5073d60
YL		 5373 HNS_ROCE_V2_CEQE_COMP_CQN_S);
5374
5375 hns_roce_cq_completion(hr_dev, cqn);
5376
5377 ++eq->cons_index;
5378 ceqe_found = 1;
5379
bceda6e6 5380 if (eq->cons_index > (EQ_DEPTH_COEFF * eq->entries - 1))
a5073d60 5381 eq->cons_index = 0;
e7f40440
LC		 5382
5383 ceqe = next_ceqe_sw_v2(eq);
a5073d60
YL		 5384 }
5385
5386 set_eq_cons_index_v2(eq);
5387
5388 return ceqe_found;
5389}
5390
5391static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr)
5392{
5393 struct hns_roce_eq *eq = eq_ptr;
5394 struct hns_roce_dev *hr_dev = eq->hr_dev;
5395 int int_work = 0;
5396
5397 if (eq->type_flag == HNS_ROCE_CEQ)
5398 /* Completion event interrupt */
5399 int_work = hns_roce_v2_ceq_int(hr_dev, eq);
5400 else
5401 /* Asychronous event interrupt */
5402 int_work = hns_roce_v2_aeq_int(hr_dev, eq);
5403
5404 return IRQ_RETVAL(int_work);
5405}
5406
5407static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
5408{
5409 struct hns_roce_dev *hr_dev = dev_id;
5410 struct device *dev = hr_dev->dev;
5411 int int_work = 0;
5412 u32 int_st;
5413 u32 int_en;
5414
5415 /* Abnormal interrupt */
5416 int_st = roce_read(hr_dev, ROCEE_VF_ABN_INT_ST_REG);
5417 int_en = roce_read(hr_dev, ROCEE_VF_ABN_INT_EN_REG);
5418
bfe86035 5419 if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S)) {
2b9acb9a
XT		 5420 struct pci_dev *pdev = hr_dev->pci_dev;
5421 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5422 const struct hnae3_ae_ops *ops = ae_dev->ops;
5423
a5073d60
YL		 5424 dev_err(dev, "AEQ overflow!\n");
5425
bfe86035 5426 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S;
a5073d60
YL		 5427 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5428
2b9acb9a
XT		 5429 /* Set reset level for reset_event() */
5430 if (ops->set_default_reset_request)
5431 ops->set_default_reset_request(ae_dev,
5432 HNAE3_FUNC_RESET);
5433 if (ops->reset_event)
5434 ops->reset_event(pdev, NULL);
5435
bfe86035 5436 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5437 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5438
5439 int_work = 1;
bfe86035 5440 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S)) {
a5073d60
YL		 5441 dev_err(dev, "BUS ERR!\n");
5442
bfe86035 5443 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S;
a5073d60
YL		 5444 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5445
bfe86035 5446 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5447 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5448
5449 int_work = 1;
bfe86035 5450 } else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S)) {
a5073d60
YL		 5451 dev_err(dev, "OTHER ERR!\n");
5452
bfe86035 5453 int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S;
a5073d60
YL		 5454 roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);
5455
bfe86035 5456 int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
a5073d60
YL		 5457 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);
5458
5459 int_work = 1;
5460 } else
5461 dev_err(dev, "There is no abnormal irq found!\n");
5462
5463 return IRQ_RETVAL(int_work);
5464}
5465
5466static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev,
5467 int eq_num, int enable_flag)
5468{
5469 int i;
5470
5471 if (enable_flag == EQ_ENABLE) {
5472 for (i = 0; i < eq_num; i++)
5473 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5474 i * EQ_REG_OFFSET,
5475 HNS_ROCE_V2_VF_EVENT_INT_EN_M);
5476
5477 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5478 HNS_ROCE_V2_VF_ABN_INT_EN_M);
5479 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5480 HNS_ROCE_V2_VF_ABN_INT_CFG_M);
5481 } else {
5482 for (i = 0; i < eq_num; i++)
5483 roce_write(hr_dev, ROCEE_VF_EVENT_INT_EN_REG +
5484 i * EQ_REG_OFFSET,
5485 HNS_ROCE_V2_VF_EVENT_INT_EN_M & 0x0);
5486
5487 roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG,
5488 HNS_ROCE_V2_VF_ABN_INT_EN_M & 0x0);
5489 roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG,
5490 HNS_ROCE_V2_VF_ABN_INT_CFG_M & 0x0);
5491 }
5492}
5493
5494static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, int eqn)
5495{
5496 struct device *dev = hr_dev->dev;
5497 int ret;
5498
5499 if (eqn < hr_dev->caps.num_comp_vectors)
5500 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5501 0, HNS_ROCE_CMD_DESTROY_CEQC,
5502 HNS_ROCE_CMD_TIMEOUT_MSECS);
5503 else
5504 ret = hns_roce_cmd_mbox(hr_dev, 0, 0, eqn & HNS_ROCE_V2_EQN_M,
5505 0, HNS_ROCE_CMD_DESTROY_AEQC,
5506 HNS_ROCE_CMD_TIMEOUT_MSECS);
5507 if (ret)
5508 dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);
5509}
5510
d7e2d343 5511static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
a5073d60 5512{
477a0a38 5513 hns_roce_mtr_destroy(hr_dev, &eq->mtr);
a5073d60
YL		 5514}
5515
477a0a38
XW		 5516static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq,
5517 void *mb_buf)
a5073d60 5518{
477a0a38 5519 u64 eqe_ba[MTT_MIN_COUNT] = { 0 };
a5073d60 5520 struct hns_roce_eq_context *eqc;
477a0a38 5521 u64 bt_ba = 0;
d7e2d343 5522 int count;
a5073d60
YL		 5523
5524 eqc = mb_buf;
5525 memset(eqc, 0, sizeof(struct hns_roce_eq_context));
5526
5527 /* init eqc */
5528 eq->doorbell = hr_dev->reg_base + ROCEE_VF_EQ_DB_CFG0_REG;
a5073d60
YL		 5529 eq->cons_index = 0;
5530 eq->over_ignore = HNS_ROCE_V2_EQ_OVER_IGNORE_0;
5531 eq->coalesce = HNS_ROCE_V2_EQ_COALESCE_0;
5532 eq->arm_st = HNS_ROCE_V2_EQ_ALWAYS_ARMED;
a5073d60
YL		 5533 eq->shift = ilog2((unsigned int)eq->entries);
5534
cc23267a 5535 /* if not multi-hop, eqe buffer only use one trunk */
477a0a38
XW		 5536 count = hns_roce_mtr_find(hr_dev, &eq->mtr, 0, eqe_ba, MTT_MIN_COUNT,
5537 &bt_ba);
5538 if (count < 1) {
5539 dev_err(hr_dev->dev, "failed to find EQE mtr\n");
5540 return -ENOBUFS;
d7e2d343 5541 }
a5073d60
YL		 5542
5543 /* set eqc state */
60262b10 5544 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQ_ST_M, HNS_ROCE_EQC_EQ_ST_S,
a5073d60
YL		 5545 HNS_ROCE_V2_EQ_STATE_VALID);
5546
5547 /* set eqe hop num */
60262b10 5548 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_HOP_NUM_M,
a5073d60
YL		 5549 HNS_ROCE_EQC_HOP_NUM_S, eq->hop_num);
5550
5551 /* set eqc over_ignore */
60262b10 5552 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_OVER_IGNORE_M,
a5073d60
YL		 5553 HNS_ROCE_EQC_OVER_IGNORE_S, eq->over_ignore);
5554
5555 /* set eqc coalesce */
60262b10 5556 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_COALESCE_M,
a5073d60
YL		 5557 HNS_ROCE_EQC_COALESCE_S, eq->coalesce);
5558
5559 /* set eqc arm_state */
60262b10 5560 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_ARM_ST_M,
a5073d60
YL		 5561 HNS_ROCE_EQC_ARM_ST_S, eq->arm_st);
5562
5563 /* set eqn */
60262b10
LO		 5564 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQN_M, HNS_ROCE_EQC_EQN_S,
5565 eq->eqn);
a5073d60
YL		 5566
5567 /* set eqe_cnt */
60262b10
LO		 5568 roce_set_field(eqc->byte_4, HNS_ROCE_EQC_EQE_CNT_M,
5569 HNS_ROCE_EQC_EQE_CNT_S, HNS_ROCE_EQ_INIT_EQE_CNT);
a5073d60
YL		 5570
5571 /* set eqe_ba_pg_sz */
60262b10 5572 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BA_PG_SZ_M,
5e6e78db 5573 HNS_ROCE_EQC_BA_PG_SZ_S,
477a0a38 5574 to_hr_hw_page_shift(eq->mtr.hem_cfg.ba_pg_shift));
a5073d60
YL		 5575
5576 /* set eqe_buf_pg_sz */
60262b10 5577 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_BUF_PG_SZ_M,
5e6e78db 5578 HNS_ROCE_EQC_BUF_PG_SZ_S,
477a0a38 5579 to_hr_hw_page_shift(eq->mtr.hem_cfg.buf_pg_shift));
a5073d60
YL		 5580
5581 /* set eq_producer_idx */
60262b10
LO		 5582 roce_set_field(eqc->byte_8, HNS_ROCE_EQC_PROD_INDX_M,
5583 HNS_ROCE_EQC_PROD_INDX_S, HNS_ROCE_EQ_INIT_PROD_IDX);
a5073d60
YL		 5584
5585 /* set eq_max_cnt */
60262b10 5586 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_MAX_CNT_M,
a5073d60
YL		 5587 HNS_ROCE_EQC_MAX_CNT_S, eq->eq_max_cnt);
5588
5589 /* set eq_period */
60262b10 5590 roce_set_field(eqc->byte_12, HNS_ROCE_EQC_PERIOD_M,
a5073d60
YL		 5591 HNS_ROCE_EQC_PERIOD_S, eq->eq_period);
5592
5593 /* set eqe_report_timer */
60262b10 5594 roce_set_field(eqc->eqe_report_timer, HNS_ROCE_EQC_REPORT_TIMER_M,
a5073d60
YL		 5595 HNS_ROCE_EQC_REPORT_TIMER_S,
5596 HNS_ROCE_EQ_INIT_REPORT_TIMER);
5597
477a0a38 5598 /* set bt_ba [34:3] */
60262b10 5599 roce_set_field(eqc->eqe_ba0, HNS_ROCE_EQC_EQE_BA_L_M,
477a0a38 5600 HNS_ROCE_EQC_EQE_BA_L_S, bt_ba >> 3);
a5073d60 5601
477a0a38 5602 /* set bt_ba [64:35] */
60262b10 5603 roce_set_field(eqc->eqe_ba1, HNS_ROCE_EQC_EQE_BA_H_M,
477a0a38 5604 HNS_ROCE_EQC_EQE_BA_H_S, bt_ba >> 35);
a5073d60
YL		 5605
5606 /* set eq shift */
60262b10
LO		 5607 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_SHIFT_M, HNS_ROCE_EQC_SHIFT_S,
5608 eq->shift);
a5073d60
YL		 5609
5610 /* set eq MSI_IDX */
60262b10
LO		 5611 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_MSI_INDX_M,
5612 HNS_ROCE_EQC_MSI_INDX_S, HNS_ROCE_EQ_INIT_MSI_IDX);
a5073d60
YL		 5613
5614 /* set cur_eqe_ba [27:12] */
60262b10 5615 roce_set_field(eqc->byte_28, HNS_ROCE_EQC_CUR_EQE_BA_L_M,
477a0a38 5616 HNS_ROCE_EQC_CUR_EQE_BA_L_S, eqe_ba[0] >> 12);
a5073d60
YL		 5617
5618 /* set cur_eqe_ba [59:28] */
60262b10 5619 roce_set_field(eqc->byte_32, HNS_ROCE_EQC_CUR_EQE_BA_M_M,
477a0a38 5620 HNS_ROCE_EQC_CUR_EQE_BA_M_S, eqe_ba[0] >> 28);
a5073d60
YL		 5621
5622 /* set cur_eqe_ba [63:60] */
60262b10 5623 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CUR_EQE_BA_H_M,
477a0a38 5624 HNS_ROCE_EQC_CUR_EQE_BA_H_S, eqe_ba[0] >> 60);
a5073d60
YL		 5625
5626 /* set eq consumer idx */
60262b10
LO		 5627 roce_set_field(eqc->byte_36, HNS_ROCE_EQC_CONS_INDX_M,
5628 HNS_ROCE_EQC_CONS_INDX_S, HNS_ROCE_EQ_INIT_CONS_IDX);
a5073d60
YL		 5629
5630 /* set nex_eqe_ba[43:12] */
60262b10 5631 roce_set_field(eqc->nxt_eqe_ba0, HNS_ROCE_EQC_NXT_EQE_BA_L_M,
477a0a38 5632 HNS_ROCE_EQC_NXT_EQE_BA_L_S, eqe_ba[1] >> 12);
a5073d60
YL		 5633
5634 /* set nex_eqe_ba[63:44] */
60262b10 5635 roce_set_field(eqc->nxt_eqe_ba1, HNS_ROCE_EQC_NXT_EQE_BA_H_M,
477a0a38 5636 HNS_ROCE_EQC_NXT_EQE_BA_H_S, eqe_ba[1] >> 44);
a5073d60 5637
477a0a38 5638 return 0;
d7e2d343 5639}
a5073d60 5640
d7e2d343
XW		 5641static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
5642{
477a0a38
XW		 5643 struct hns_roce_buf_attr buf_attr = {};
5644 int err;
a5073d60 5645
477a0a38
XW		 5646 if (hr_dev->caps.eqe_hop_num == HNS_ROCE_HOP_NUM_0)
5647 eq->hop_num = 0;
5648 else
5649 eq->hop_num = hr_dev->caps.eqe_hop_num;
a5073d60 5650
9581a356 5651 buf_attr.page_shift = hr_dev->caps.eqe_buf_pg_sz + HNS_HW_PAGE_SHIFT;
477a0a38
XW		 5652 buf_attr.region[0].size = eq->entries * eq->eqe_size;
5653 buf_attr.region[0].hopnum = eq->hop_num;
5654 buf_attr.region_count = 1;
5655 buf_attr.fixed_page = true;
d7e2d343 5656
477a0a38 5657 err = hns_roce_mtr_create(hr_dev, &eq->mtr, &buf_attr,
053c0acf 5658 hr_dev->caps.eqe_ba_pg_sz +
9581a356 5659 HNS_HW_PAGE_SHIFT, NULL, 0);
477a0a38
XW		 5660 if (err)
5661 dev_err(hr_dev->dev, "Failed to alloc EQE mtr, err %d\n", err);
a5073d60 5662
477a0a38 5663 return err;
a5073d60
YL		 5664}
5665
5666static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev,
5667 struct hns_roce_eq *eq,
5668 unsigned int eq_cmd)
5669{
a5073d60 5670 struct hns_roce_cmd_mailbox *mailbox;
a5073d60
YL		 5671 int ret;
5672
5673 /* Allocate mailbox memory */
5674 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
477a0a38
XW		 5675 if (IS_ERR_OR_NULL(mailbox))
5676 return -ENOMEM;
a5073d60 5677
d7e2d343 5678 ret = alloc_eq_buf(hr_dev, eq);
477a0a38 5679 if (ret)
d7e2d343 5680 goto free_cmd_mbox;
477a0a38
XW		 5681
5682 ret = config_eqc(hr_dev, eq, mailbox->buf);
5683 if (ret)
5684 goto err_cmd_mbox;
a5073d60
YL		 5685
5686 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, eq->eqn, 0,
5687 eq_cmd, HNS_ROCE_CMD_TIMEOUT_MSECS);
5688 if (ret) {
d7e2d343 5689 dev_err(hr_dev->dev, "[mailbox cmd] create eqc failed.\n");
a5073d60
YL		 5690 goto err_cmd_mbox;
5691 }
5692
5693 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5694
5695 return 0;
5696
5697err_cmd_mbox:
d7e2d343 5698 free_eq_buf(hr_dev, eq);
a5073d60
YL		 5699
5700free_cmd_mbox:
5701 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
5702
5703 return ret;
5704}
5705
33db6f94
YL		 5706static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num,
5707 int comp_num, int aeq_num, int other_num)
5708{
5709 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5710 int i, j;
5711 int ret;
5712
5713 for (i = 0; i < irq_num; i++) {
5714 hr_dev->irq_names[i] = kzalloc(HNS_ROCE_INT_NAME_LEN,
5715 GFP_KERNEL);
5716 if (!hr_dev->irq_names[i]) {
5717 ret = -ENOMEM;
5718 goto err_kzalloc_failed;
5719 }
5720 }
5721
6def7de6 5722 /* irq contains: abnormal + AEQ + CEQ */
bebdb83f 5723 for (j = 0; j < other_num; j++)
60262b10
LO		 5724 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5725 "hns-abn-%d", j);
bebdb83f
LC		 5726
5727 for (j = other_num; j < (other_num + aeq_num); j++)
60262b10
LO		 5728 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5729 "hns-aeq-%d", j - other_num);
bebdb83f
LC		 5730
5731 for (j = (other_num + aeq_num); j < irq_num; j++)
60262b10
LO		 5732 snprintf((char *)hr_dev->irq_names[j], HNS_ROCE_INT_NAME_LEN,
5733 "hns-ceq-%d", j - other_num - aeq_num);
33db6f94
YL		 5734
5735 for (j = 0; j < irq_num; j++) {
5736 if (j < other_num)
5737 ret = request_irq(hr_dev->irq[j],
5738 hns_roce_v2_msix_interrupt_abn,
5739 0, hr_dev->irq_names[j], hr_dev);
5740
5741 else if (j < (other_num + comp_num))
5742 ret = request_irq(eq_table->eq[j - other_num].irq,
5743 hns_roce_v2_msix_interrupt_eq,
5744 0, hr_dev->irq_names[j + aeq_num],
5745 &eq_table->eq[j - other_num]);
5746 else
5747 ret = request_irq(eq_table->eq[j - other_num].irq,
5748 hns_roce_v2_msix_interrupt_eq,
5749 0, hr_dev->irq_names[j - comp_num],
5750 &eq_table->eq[j - other_num]);
5751 if (ret) {
5752 dev_err(hr_dev->dev, "Request irq error!\n");
5753 goto err_request_failed;
5754 }
5755 }
5756
5757 return 0;
5758
5759err_request_failed:
5760 for (j -= 1; j >= 0; j--)
5761 if (j < other_num)
5762 free_irq(hr_dev->irq[j], hr_dev);
5763 else
5764 free_irq(eq_table->eq[j - other_num].irq,
5765 &eq_table->eq[j - other_num]);
5766
5767err_kzalloc_failed:
5768 for (i -= 1; i >= 0; i--)
5769 kfree(hr_dev->irq_names[i]);
5770
5771 return ret;
5772}
5773
5774static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev)
5775{
5776 int irq_num;
5777 int eq_num;
5778 int i;
5779
5780 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
5781 irq_num = eq_num + hr_dev->caps.num_other_vectors;
5782
5783 for (i = 0; i < hr_dev->caps.num_other_vectors; i++)
5784 free_irq(hr_dev->irq[i], hr_dev);
5785
5786 for (i = 0; i < eq_num; i++)
5787 free_irq(hr_dev->eq_table.eq[i].irq, &hr_dev->eq_table.eq[i]);
5788
5789 for (i = 0; i < irq_num; i++)
5790 kfree(hr_dev->irq_names[i]);
5791}
5792
a5073d60
YL		 5793static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev)
5794{
5795 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
5796 struct device *dev = hr_dev->dev;
5797 struct hns_roce_eq *eq;
5798 unsigned int eq_cmd;
5799 int irq_num;
5800 int eq_num;
5801 int other_num;
5802 int comp_num;
5803 int aeq_num;
33db6f94 5804 int i;
a5073d60
YL		 5805 int ret;
5806
5807 other_num = hr_dev->caps.num_other_vectors;
5808 comp_num = hr_dev->caps.num_comp_vectors;
5809 aeq_num = hr_dev->caps.num_aeq_vectors;
5810
5811 eq_num = comp_num + aeq_num;
5812 irq_num = eq_num + other_num;
5813
5814 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
5815 if (!eq_table->eq)
5816 return -ENOMEM;
5817
a5073d60 5818 /* create eq */
33db6f94
YL		 5819 for (i = 0; i < eq_num; i++) {
5820 eq = &eq_table->eq[i];
a5073d60 5821 eq->hr_dev = hr_dev;
33db6f94
YL		 5822 eq->eqn = i;
5823 if (i < comp_num) {
a5073d60
YL		 5824 /* CEQ */
5825 eq_cmd = HNS_ROCE_CMD_CREATE_CEQC;
5826 eq->type_flag = HNS_ROCE_CEQ;
5827 eq->entries = hr_dev->caps.ceqe_depth;
5828 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
33db6f94 5829 eq->irq = hr_dev->irq[i + other_num + aeq_num];
a5073d60
YL		 5830 eq->eq_max_cnt = HNS_ROCE_CEQ_DEFAULT_BURST_NUM;
5831 eq->eq_period = HNS_ROCE_CEQ_DEFAULT_INTERVAL;
5832 } else {
5833 /* AEQ */
5834 eq_cmd = HNS_ROCE_CMD_CREATE_AEQC;
5835 eq->type_flag = HNS_ROCE_AEQ;
5836 eq->entries = hr_dev->caps.aeqe_depth;
5837 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
33db6f94 5838 eq->irq = hr_dev->irq[i - comp_num + other_num];
a5073d60
YL		 5839 eq->eq_max_cnt = HNS_ROCE_AEQ_DEFAULT_BURST_NUM;
5840 eq->eq_period = HNS_ROCE_AEQ_DEFAULT_INTERVAL;
5841 }
5842
5843 ret = hns_roce_v2_create_eq(hr_dev, eq, eq_cmd);
5844 if (ret) {
5845 dev_err(dev, "eq create failed.\n");
5846 goto err_create_eq_fail;
5847 }
5848 }
5849
5850 /* enable irq */
5851 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_ENABLE);
5852
33db6f94
YL		 5853 ret = __hns_roce_request_irq(hr_dev, irq_num, comp_num,
5854 aeq_num, other_num);
5855 if (ret) {
5856 dev_err(dev, "Request irq failed.\n");
5857 goto err_request_irq_fail;
a5073d60
YL		 5858 }
5859
ffd541d4 5860 hr_dev->irq_workq = alloc_ordered_workqueue("hns_roce_irq_workq", 0);
0425e3e6
YL		 5861 if (!hr_dev->irq_workq) {
5862 dev_err(dev, "Create irq workqueue failed!\n");
f1a31542 5863 ret = -ENOMEM;
33db6f94 5864 goto err_create_wq_fail;
0425e3e6
YL		 5865 }
5866
a5073d60
YL		 5867 return 0;
5868
33db6f94
YL		 5869err_create_wq_fail:
5870 __hns_roce_free_irq(hr_dev);
5871
a5073d60 5872err_request_irq_fail:
33db6f94 5873 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
a5073d60
YL		 5874
5875err_create_eq_fail:
a5073d60 5876 for (i -= 1; i >= 0; i--)
d7e2d343 5877 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5878 kfree(eq_table->eq);
5879
5880 return ret;
5881}
5882
5883static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev)
5884{
5885 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
a5073d60
YL		 5886 int eq_num;
5887 int i;
5888
5889 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
a5073d60
YL		 5890
5891 /* Disable irq */
5892 hns_roce_v2_int_mask_enable(hr_dev, eq_num, EQ_DISABLE);
5893
33db6f94 5894 __hns_roce_free_irq(hr_dev);
a5073d60
YL		 5895
5896 for (i = 0; i < eq_num; i++) {
5897 hns_roce_v2_destroy_eqc(hr_dev, i);
5898
d7e2d343 5899 free_eq_buf(hr_dev, &eq_table->eq[i]);
a5073d60
YL		 5900 }
5901
a5073d60 5902 kfree(eq_table->eq);
0425e3e6
YL		 5903
5904 flush_workqueue(hr_dev->irq_workq);
5905 destroy_workqueue(hr_dev->irq_workq);
a5073d60
YL		 5906}
5907
e1c9a0dc
LO		 5908static const struct hns_roce_dfx_hw hns_roce_dfx_hw_v2 = {
5909 .query_cqc_info = hns_roce_v2_query_cqc_info,
5910};
5911
7f645a58
KH		 5912static const struct ib_device_ops hns_roce_v2_dev_ops = {
5913 .destroy_qp = hns_roce_v2_destroy_qp,
5914 .modify_cq = hns_roce_v2_modify_cq,
5915 .poll_cq = hns_roce_v2_poll_cq,
5916 .post_recv = hns_roce_v2_post_recv,
5917 .post_send = hns_roce_v2_post_send,
5918 .query_qp = hns_roce_v2_query_qp,
5919 .req_notify_cq = hns_roce_v2_req_notify_cq,
5920};
5921
5922static const struct ib_device_ops hns_roce_v2_dev_srq_ops = {
5923 .modify_srq = hns_roce_v2_modify_srq,
5924 .post_srq_recv = hns_roce_v2_post_srq_recv,
5925 .query_srq = hns_roce_v2_query_srq,
5926};
5927
a04ff739
WHX		 5928static const struct hns_roce_hw hns_roce_hw_v2 = {
5929 .cmq_init = hns_roce_v2_cmq_init,
5930 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 5931 .hw_profile = hns_roce_v2_profile,
6b63597d 5932 .hw_init = hns_roce_v2_init,
5933 .hw_exit = hns_roce_v2_exit,
a680f2f3
WHX		 5934 .post_mbox = hns_roce_v2_post_mbox,
5935 .chk_mbox = hns_roce_v2_chk_mbox,
6a04aed6 5936 .rst_prc_mbox = hns_roce_v2_rst_process_cmd,
7afddafa
WHX		 5937 .set_gid = hns_roce_v2_set_gid,
5938 .set_mac = hns_roce_v2_set_mac,
3958cc56 5939 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 5940 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
68a997c5 5941 .frmr_write_mtpt = hns_roce_v2_frmr_write_mtpt,
c7c28191 5942 .mw_write_mtpt = hns_roce_v2_mw_write_mtpt,
93aa2187 5943 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 5944 .set_hem = hns_roce_v2_set_hem,
5945 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 5946 .modify_qp = hns_roce_v2_modify_qp,
5947 .query_qp = hns_roce_v2_query_qp,
5948 .destroy_qp = hns_roce_v2_destroy_qp,
aa84fa18 5949 .qp_flow_control_init = hns_roce_v2_qp_flow_control_init,
b156269d 5950 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 5951 .post_send = hns_roce_v2_post_send,
5952 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 5953 .req_notify_cq = hns_roce_v2_req_notify_cq,
5954 .poll_cq = hns_roce_v2_poll_cq,
a5073d60
YL		 5955 .init_eq = hns_roce_v2_init_eq_table,
5956 .cleanup_eq = hns_roce_v2_cleanup_eq_table,
c7bcb134
LO		 5957 .write_srqc = hns_roce_v2_write_srqc,
5958 .modify_srq = hns_roce_v2_modify_srq,
5959 .query_srq = hns_roce_v2_query_srq,
5960 .post_srq_recv = hns_roce_v2_post_srq_recv,
7f645a58
KH		 5961 .hns_roce_dev_ops = &hns_roce_v2_dev_ops,
5962 .hns_roce_dev_srq_ops = &hns_roce_v2_dev_srq_ops,
a04ff739 5963};
dd74282d
WHX		 5964
5965static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
5966 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
5967 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
aaa31567
LO		 5968 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
5969 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
dd74282d
WHX		 5970 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
5971 /* required last entry */
5972 {0, }
5973};
5974
f97a62c3 5975MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl);
5976
301cc7eb 5977static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
dd74282d
WHX		 5978 struct hnae3_handle *handle)
5979{
d061effc 5980 struct hns_roce_v2_priv *priv = hr_dev->priv;
a5073d60 5981 int i;
dd74282d 5982
301cc7eb
LC		 5983 hr_dev->pci_dev = handle->pdev;
5984 hr_dev->dev = &handle->pdev->dev;
dd74282d 5985 hr_dev->hw = &hns_roce_hw_v2;
e1c9a0dc 5986 hr_dev->dfx = &hns_roce_dfx_hw_v2;
2d407888
WHX		 5987 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
5988 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 5989
5990 /* Get info from NIC driver. */
5991 hr_dev->reg_base = handle->rinfo.roce_io_base;
5992 hr_dev->caps.num_ports = 1;
5993 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
5994 hr_dev->iboe.phy_port[0] = 0;
5995
d4994d2f 5996 addrconf_addr_eui48((u8 *)&hr_dev->ib_dev.node_guid,
5997 hr_dev->iboe.netdevs[0]->dev_addr);
5998
a5073d60
YL		 5999 for (i = 0; i < HNS_ROCE_V2_MAX_IRQ_NUM; i++)
6000 hr_dev->irq[i] = pci_irq_vector(handle->pdev,
6001 i + handle->rinfo.base_vector);
6002
dd74282d 6003 /* cmd issue mode: 0 is poll, 1 is event */
a5073d60 6004 hr_dev->cmd_mod = 1;
dd74282d
WHX		 6005 hr_dev->loop_idc = 0;
6006
d061effc
WHX		 6007 hr_dev->reset_cnt = handle->ae_algo->ops->ae_dev_reset_cnt(handle);
6008 priv->handle = handle;
dd74282d
WHX		 6009}
6010
d061effc 6011static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
dd74282d
WHX		 6012{
6013 struct hns_roce_dev *hr_dev;
6014 int ret;
6015
459cc69f 6016 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
dd74282d
WHX		 6017 if (!hr_dev)
6018 return -ENOMEM;
6019
a04ff739
WHX		 6020 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
6021 if (!hr_dev->priv) {
6022 ret = -ENOMEM;
6023 goto error_failed_kzalloc;
6024 }
6025
301cc7eb 6026 hns_roce_hw_v2_get_cfg(hr_dev, handle);
dd74282d
WHX		 6027
6028 ret = hns_roce_init(hr_dev);
6029 if (ret) {
6030 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
6031 goto error_failed_get_cfg;
6032 }
6033
d061effc
WHX		 6034 handle->priv = hr_dev;
6035
dd74282d
WHX		 6036 return 0;
6037
6038error_failed_get_cfg:
a04ff739
WHX		 6039 kfree(hr_dev->priv);
6040
6041error_failed_kzalloc:
dd74282d
WHX		 6042 ib_dealloc_device(&hr_dev->ib_dev);
6043
6044 return ret;
6045}
6046
d061effc 6047static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
dd74282d
WHX		 6048 bool reset)
6049{
14ba8730 6050 struct hns_roce_dev *hr_dev = handle->priv;
dd74282d 6051
cb7a94c9
WHX		 6052 if (!hr_dev)
6053 return;
6054
d061effc 6055 handle->priv = NULL;
626903e9
XW		 6056
6057 hr_dev->state = HNS_ROCE_DEVICE_STATE_UNINIT;
6058 hns_roce_handle_device_err(hr_dev);
6059
dd74282d 6060 hns_roce_exit(hr_dev);
a04ff739 6061 kfree(hr_dev->priv);
dd74282d
WHX		 6062 ib_dealloc_device(&hr_dev->ib_dev);
6063}
6064
d061effc
WHX		 6065static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
6066{
6067 const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
07c2339a 6068 const struct pci_device_id *id;
d061effc
WHX		 6069 struct device *dev = &handle->pdev->dev;
6070 int ret;
6071
6072 handle->rinfo.instance_state = HNS_ROCE_STATE_INIT;
6073
6074 if (ops->ae_dev_resetting(handle) || ops->get_hw_reset_stat(handle)) {
6075 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6076 goto reset_chk_err;
6077 }
6078
07c2339a
LO		 6079 id = pci_match_id(hns_roce_hw_v2_pci_tbl, handle->pdev);
6080 if (!id)
6081 return 0;
6082
d061effc
WHX		 6083 ret = __hns_roce_hw_v2_init_instance(handle);
6084 if (ret) {
6085 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6086 dev_err(dev, "RoCE instance init failed! ret = %d\n", ret);
6087 if (ops->ae_dev_resetting(handle) ||
6088 ops->get_hw_reset_stat(handle))
6089 goto reset_chk_err;
6090 else
6091 return ret;
6092 }
6093
6094 handle->rinfo.instance_state = HNS_ROCE_STATE_INITED;
6095
6096
6097 return 0;
6098
6099reset_chk_err:
6100 dev_err(dev, "Device is busy in resetting state.\n"
6101 "please retry later.\n");
6102
6103 return -EBUSY;
6104}
6105
6106static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
6107 bool reset)
6108{
6109 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED)
6110 return;
6111
6112 handle->rinfo.instance_state = HNS_ROCE_STATE_UNINIT;
6113
6114 __hns_roce_hw_v2_uninit_instance(handle, reset);
6115
6116 handle->rinfo.instance_state = HNS_ROCE_STATE_NON_INIT;
6117}
cb7a94c9
WHX		 6118static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle)
6119{
d061effc 6120 struct hns_roce_dev *hr_dev;
cb7a94c9 6121
d061effc
WHX		 6122 if (handle->rinfo.instance_state != HNS_ROCE_STATE_INITED) {
6123 set_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6124 return 0;
cb7a94c9
WHX		 6125 }
6126
d061effc
WHX		 6127 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_DOWN;
6128 clear_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state);
6129
14ba8730 6130 hr_dev = handle->priv;
d061effc
WHX		 6131 if (!hr_dev)
6132 return 0;
6133
726be12f 6134 hr_dev->is_reset = true;
cb7a94c9 6135 hr_dev->active = false;
d3743fa9 6136 hr_dev->dis_db = true;
cb7a94c9 6137
626903e9 6138 hr_dev->state = HNS_ROCE_DEVICE_STATE_RST_DOWN;
cb7a94c9
WHX		 6139
6140 return 0;
6141}
6142
6143static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle)
6144{
d061effc 6145 struct device *dev = &handle->pdev->dev;
cb7a94c9
WHX		 6146 int ret;
6147
d061effc
WHX		 6148 if (test_and_clear_bit(HNS_ROCE_RST_DIRECT_RETURN,
6149 &handle->rinfo.state)) {
6150 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6151 return 0;
6152 }
6153
6154 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INIT;
6155
6156 dev_info(&handle->pdev->dev, "In reset process RoCE client reinit.\n");
6157 ret = __hns_roce_hw_v2_init_instance(handle);
cb7a94c9
WHX		 6158 if (ret) {
6159 /* when reset notify type is HNAE3_INIT_CLIENT In reset notify
6160 * callback function, RoCE Engine reinitialize. If RoCE reinit
6161 * failed, we should inform NIC driver.
6162 */
6163 handle->priv = NULL;
d061effc
WHX		 6164 dev_err(dev, "In reset process RoCE reinit failed %d.\n", ret);
6165 } else {
6166 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_INITED;
6167 dev_info(dev, "Reset done, RoCE client reinit finished.\n");
cb7a94c9
WHX		 6168 }
6169
6170 return ret;
6171}
6172
6173static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle)
6174{
d061effc
WHX		 6175 if (test_bit(HNS_ROCE_RST_DIRECT_RETURN, &handle->rinfo.state))
6176 return 0;
6177
6178 handle->rinfo.reset_state = HNS_ROCE_STATE_RST_UNINIT;
6179 dev_info(&handle->pdev->dev, "In reset process RoCE client uninit.\n");
90c559b1 6180 msleep(HNS_ROCE_V2_HW_RST_UNINT_DELAY);
d061effc
WHX		 6181 __hns_roce_hw_v2_uninit_instance(handle, false);
6182
cb7a94c9
WHX		 6183 return 0;
6184}
6185
6186static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle,
6187 enum hnae3_reset_notify_type type)
6188{
6189 int ret = 0;
6190
6191 switch (type) {
6192 case HNAE3_DOWN_CLIENT:
6193 ret = hns_roce_hw_v2_reset_notify_down(handle);
6194 break;
6195 case HNAE3_INIT_CLIENT:
6196 ret = hns_roce_hw_v2_reset_notify_init(handle);
6197 break;
6198 case HNAE3_UNINIT_CLIENT:
6199 ret = hns_roce_hw_v2_reset_notify_uninit(handle);
6200 break;
6201 default:
6202 break;
6203 }
6204
6205 return ret;
6206}
6207
dd74282d
WHX		 6208static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
6209 .init_instance = hns_roce_hw_v2_init_instance,
6210 .uninit_instance = hns_roce_hw_v2_uninit_instance,
cb7a94c9 6211 .reset_notify = hns_roce_hw_v2_reset_notify,
dd74282d
WHX		 6212};
6213
6214static struct hnae3_client hns_roce_hw_v2_client = {
6215 .name = "hns_roce_hw_v2",
6216 .type = HNAE3_CLIENT_ROCE,
6217 .ops = &hns_roce_hw_v2_ops,
6218};
6219
6220static int __init hns_roce_hw_v2_init(void)
6221{
6222 return hnae3_register_client(&hns_roce_hw_v2_client);
6223}
6224
6225static void __exit hns_roce_hw_v2_exit(void)
6226{
6227 hnae3_unregister_client(&hns_roce_hw_v2_client);
6228}
6229
6230module_init(hns_roce_hw_v2_init);
6231module_exit(hns_roce_hw_v2_exit);
6232
6233MODULE_LICENSE("Dual BSD/GPL");
6234MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
6235MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
6236MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
6237MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)