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Merge remote-tracking branches 'asoc/topic/ts3a227e', 'asoc/topic/tsc42xx', 'asoc...
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v2.c
CommitLineData
dd74282d
WHX		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/acpi.h>
34#include <linux/etherdevice.h>
35#include <linux/interrupt.h>
36#include <linux/kernel.h>
37#include <rdma/ib_umem.h>
38
39#include "hnae3.h"
40#include "hns_roce_common.h"
41#include "hns_roce_device.h"
42#include "hns_roce_cmd.h"
43#include "hns_roce_hem.h"
a04ff739 44#include "hns_roce_hw_v2.h"
dd74282d 45
2d407888
WHX		 46static void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg,
47 struct ib_sge *sg)
48{
49 dseg->lkey = cpu_to_le32(sg->lkey);
50 dseg->addr = cpu_to_le64(sg->addr);
51 dseg->len = cpu_to_le32(sg->length);
52}
53
54static int hns_roce_v2_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
55 struct ib_send_wr **bad_wr)
56{
57 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
58 struct hns_roce_v2_rc_send_wqe *rc_sq_wqe;
59 struct hns_roce_qp *qp = to_hr_qp(ibqp);
60 struct hns_roce_v2_wqe_data_seg *dseg;
61 struct device *dev = hr_dev->dev;
62 struct hns_roce_v2_db sq_db;
63 unsigned int sge_ind = 0;
64 unsigned int wqe_sz = 0;
e8d18533 65 unsigned int owner_bit;
2d407888
WHX		 66 unsigned long flags;
67 unsigned int ind;
68 void *wqe = NULL;
69 int ret = 0;
70 int nreq;
71 int i;
72
73 if (unlikely(ibqp->qp_type != IB_QPT_RC)) {
74 dev_err(dev, "Not supported QP(0x%x)type!\n", ibqp->qp_type);
75 *bad_wr = NULL;
76 return -EOPNOTSUPP;
77 }
78
79 if (unlikely(qp->state != IB_QPS_RTS && qp->state != IB_QPS_SQD)) {
80 dev_err(dev, "Post WQE fail, QP state %d err!\n", qp->state);
81 *bad_wr = wr;
82 return -EINVAL;
83 }
84
85 spin_lock_irqsave(&qp->sq.lock, flags);
86 ind = qp->sq_next_wqe;
87 sge_ind = qp->next_sge;
88
89 for (nreq = 0; wr; ++nreq, wr = wr->next) {
90 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
91 ret = -ENOMEM;
92 *bad_wr = wr;
93 goto out;
94 }
95
96 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
97 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
98 wr->num_sge, qp->sq.max_gs);
99 ret = -EINVAL;
100 *bad_wr = wr;
101 goto out;
102 }
103
104 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
105 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
106 wr->wr_id;
107
e8d18533 108 owner_bit = ~(qp->sq.head >> ilog2(qp->sq.wqe_cnt)) & 0x1;
2d407888
WHX		 109 rc_sq_wqe = wqe;
110 memset(rc_sq_wqe, 0, sizeof(*rc_sq_wqe));
111 for (i = 0; i < wr->num_sge; i++)
112 rc_sq_wqe->msg_len += wr->sg_list[i].length;
113
114 rc_sq_wqe->inv_key_immtdata = send_ieth(wr);
115
651487c2 116 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FENCE_S,
117 (wr->send_flags & IB_SEND_FENCE) ? 1 : 0);
492b2bd0 118
119 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_SE_S,
120 (wr->send_flags & IB_SEND_SOLICITED) ? 1 : 0);
651487c2 121
a49d761f 122 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_CQE_S,
123 (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);
124
e8d18533 125 roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_OWNER_S,
126 owner_bit);
127
2d407888
WHX		 128 switch (wr->opcode) {
129 case IB_WR_RDMA_READ:
130 roce_set_field(rc_sq_wqe->byte_4,
131 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
132 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
133 HNS_ROCE_V2_WQE_OP_RDMA_READ);
134 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
135 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
136 break;
137 case IB_WR_RDMA_WRITE:
138 roce_set_field(rc_sq_wqe->byte_4,
139 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
140 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
141 HNS_ROCE_V2_WQE_OP_RDMA_WRITE);
142 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
143 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
144 break;
145 case IB_WR_RDMA_WRITE_WITH_IMM:
146 roce_set_field(rc_sq_wqe->byte_4,
147 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
148 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
149 HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM);
150 rc_sq_wqe->rkey = cpu_to_le32(rdma_wr(wr)->rkey);
151 rc_sq_wqe->va = cpu_to_le64(rdma_wr(wr)->remote_addr);
152 break;
153 case IB_WR_SEND:
154 roce_set_field(rc_sq_wqe->byte_4,
155 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
156 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
157 HNS_ROCE_V2_WQE_OP_SEND);
158 break;
159 case IB_WR_SEND_WITH_INV:
160 roce_set_field(rc_sq_wqe->byte_4,
161 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
162 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
163 HNS_ROCE_V2_WQE_OP_SEND_WITH_INV);
164 break;
165 case IB_WR_SEND_WITH_IMM:
166 roce_set_field(rc_sq_wqe->byte_4,
167 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
168 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
169 HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM);
170 break;
171 case IB_WR_LOCAL_INV:
172 roce_set_field(rc_sq_wqe->byte_4,
173 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
174 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
175 HNS_ROCE_V2_WQE_OP_LOCAL_INV);
176 break;
177 case IB_WR_ATOMIC_CMP_AND_SWP:
178 roce_set_field(rc_sq_wqe->byte_4,
179 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
180 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
181 HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP);
182 break;
183 case IB_WR_ATOMIC_FETCH_AND_ADD:
184 roce_set_field(rc_sq_wqe->byte_4,
185 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
186 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
187 HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD);
188 break;
189 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
190 roce_set_field(rc_sq_wqe->byte_4,
191 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
192 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
193 HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP);
194 break;
195 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
196 roce_set_field(rc_sq_wqe->byte_4,
197 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
198 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
199 HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD);
200 break;
201 default:
202 roce_set_field(rc_sq_wqe->byte_4,
203 V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
204 V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
205 HNS_ROCE_V2_WQE_OP_MASK);
206 break;
207 }
208
2d407888
WHX		 209 wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
210 dseg = wqe;
211 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
212 if (rc_sq_wqe->msg_len >
213 hr_dev->caps.max_sq_inline) {
214 ret = -EINVAL;
215 *bad_wr = wr;
216 dev_err(dev, "inline len(1-%d)=%d, illegal",
217 rc_sq_wqe->msg_len,
218 hr_dev->caps.max_sq_inline);
219 goto out;
220 }
221
222 for (i = 0; i < wr->num_sge; i++) {
223 memcpy(wqe, ((void *)wr->sg_list[i].addr),
224 wr->sg_list[i].length);
225 wqe += wr->sg_list[i].length;
226 wqe_sz += wr->sg_list[i].length;
227 }
228
229 roce_set_bit(rc_sq_wqe->byte_4,
230 V2_RC_SEND_WQE_BYTE_4_INLINE_S, 1);
231 } else {
232 if (wr->num_sge <= 2) {
233 for (i = 0; i < wr->num_sge; i++)
234 set_data_seg_v2(dseg + i,
235 wr->sg_list + i);
236 } else {
237 roce_set_field(rc_sq_wqe->byte_20,
238 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M,
239 V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S,
240 sge_ind & (qp->sge.sge_cnt - 1));
241
242 for (i = 0; i < 2; i++)
243 set_data_seg_v2(dseg + i,
244 wr->sg_list + i);
245
246 dseg = get_send_extend_sge(qp,
247 sge_ind & (qp->sge.sge_cnt - 1));
248
249 for (i = 0; i < wr->num_sge - 2; i++) {
250 set_data_seg_v2(dseg + i,
251 wr->sg_list + 2 + i);
252 sge_ind++;
253 }
254 }
255
256 roce_set_field(rc_sq_wqe->byte_16,
257 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M,
258 V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S,
259 wr->num_sge);
260 wqe_sz += wr->num_sge *
261 sizeof(struct hns_roce_v2_wqe_data_seg);
262 }
263 ind++;
264 }
265
266out:
267 if (likely(nreq)) {
268 qp->sq.head += nreq;
269 /* Memory barrier */
270 wmb();
271
272 sq_db.byte_4 = 0;
273 sq_db.parameter = 0;
274
275 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_TAG_M,
276 V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn);
277 roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M,
278 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB);
279 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M,
280 V2_DB_PARAMETER_CONS_IDX_S,
281 qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1));
282 roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M,
283 V2_DB_PARAMETER_SL_S, qp->sl);
284
285 hns_roce_write64_k((__be32 *)&sq_db, qp->sq.db_reg_l);
286
287 qp->sq_next_wqe = ind;
288 qp->next_sge = sge_ind;
289 }
290
291 spin_unlock_irqrestore(&qp->sq.lock, flags);
292
293 return ret;
294}
295
296static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
297 struct ib_recv_wr **bad_wr)
298{
299 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
300 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
301 struct hns_roce_v2_wqe_data_seg *dseg;
302 struct device *dev = hr_dev->dev;
303 struct hns_roce_v2_db rq_db;
304 unsigned long flags;
305 void *wqe = NULL;
306 int ret = 0;
307 int nreq;
308 int ind;
309 int i;
310
311 spin_lock_irqsave(&hr_qp->rq.lock, flags);
312 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
313
314 if (hr_qp->state == IB_QPS_RESET || hr_qp->state == IB_QPS_ERR) {
315 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
316 *bad_wr = wr;
317 return -EINVAL;
318 }
319
320 for (nreq = 0; wr; ++nreq, wr = wr->next) {
321 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
322 hr_qp->ibqp.recv_cq)) {
323 ret = -ENOMEM;
324 *bad_wr = wr;
325 goto out;
326 }
327
328 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
329 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
330 wr->num_sge, hr_qp->rq.max_gs);
331 ret = -EINVAL;
332 *bad_wr = wr;
333 goto out;
334 }
335
336 wqe = get_recv_wqe(hr_qp, ind);
337 dseg = (struct hns_roce_v2_wqe_data_seg *)wqe;
338 for (i = 0; i < wr->num_sge; i++) {
339 if (!wr->sg_list[i].length)
340 continue;
341 set_data_seg_v2(dseg, wr->sg_list + i);
342 dseg++;
343 }
344
345 if (i < hr_qp->rq.max_gs) {
346 dseg[i].lkey = cpu_to_be32(HNS_ROCE_INVALID_LKEY);
347 dseg[i].addr = 0;
348 }
349
350 hr_qp->rq.wrid[ind] = wr->wr_id;
351
352 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
353 }
354
355out:
356 if (likely(nreq)) {
357 hr_qp->rq.head += nreq;
358 /* Memory barrier */
359 wmb();
360
361 rq_db.byte_4 = 0;
362 rq_db.parameter = 0;
363
364 roce_set_field(rq_db.byte_4, V2_DB_BYTE_4_TAG_M,
365 V2_DB_BYTE_4_TAG_S, hr_qp->qpn);
366 roce_set_field(rq_db.byte_4, V2_DB_BYTE_4_CMD_M,
367 V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_RQ_DB);
368 roce_set_field(rq_db.parameter, V2_DB_PARAMETER_CONS_IDX_M,
369 V2_DB_PARAMETER_CONS_IDX_S, hr_qp->rq.head);
370
371 hns_roce_write64_k((__be32 *)&rq_db, hr_qp->rq.db_reg_l);
372 }
373 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
374
375 return ret;
376}
377
a04ff739
WHX		 378static int hns_roce_cmq_space(struct hns_roce_v2_cmq_ring *ring)
379{
380 int ntu = ring->next_to_use;
381 int ntc = ring->next_to_clean;
382 int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
383
384 return ring->desc_num - used - 1;
385}
386
387static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev,
388 struct hns_roce_v2_cmq_ring *ring)
389{
390 int size = ring->desc_num * sizeof(struct hns_roce_cmq_desc);
391
392 ring->desc = kzalloc(size, GFP_KERNEL);
393 if (!ring->desc)
394 return -ENOMEM;
395
396 ring->desc_dma_addr = dma_map_single(hr_dev->dev, ring->desc, size,
397 DMA_BIDIRECTIONAL);
398 if (dma_mapping_error(hr_dev->dev, ring->desc_dma_addr)) {
399 ring->desc_dma_addr = 0;
400 kfree(ring->desc);
401 ring->desc = NULL;
402 return -ENOMEM;
403 }
404
405 return 0;
406}
407
408static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev,
409 struct hns_roce_v2_cmq_ring *ring)
410{
411 dma_unmap_single(hr_dev->dev, ring->desc_dma_addr,
412 ring->desc_num * sizeof(struct hns_roce_cmq_desc),
413 DMA_BIDIRECTIONAL);
414 kfree(ring->desc);
415}
416
417static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
418{
419 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
420 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
421 &priv->cmq.csq : &priv->cmq.crq;
422
423 ring->flag = ring_type;
424 ring->next_to_clean = 0;
425 ring->next_to_use = 0;
426
427 return hns_roce_alloc_cmq_desc(hr_dev, ring);
428}
429
430static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
431{
432 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
433 struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
434 &priv->cmq.csq : &priv->cmq.crq;
435 dma_addr_t dma = ring->desc_dma_addr;
436
437 if (ring_type == TYPE_CSQ) {
438 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
439 roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
440 upper_32_bits(dma));
441 roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
442 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
443 HNS_ROCE_CMQ_ENABLE);
444 roce_write(hr_dev, ROCEE_TX_CMQ_HEAD_REG, 0);
445 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, 0);
446 } else {
447 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
448 roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
449 upper_32_bits(dma));
450 roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
451 (ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S) |
452 HNS_ROCE_CMQ_ENABLE);
453 roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
454 roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
455 }
456}
457
458static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
459{
460 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
461 int ret;
462
463 /* Setup the queue entries for command queue */
464 priv->cmq.csq.desc_num = 1024;
465 priv->cmq.crq.desc_num = 1024;
466
467 /* Setup the lock for command queue */
468 spin_lock_init(&priv->cmq.csq.lock);
469 spin_lock_init(&priv->cmq.crq.lock);
470
471 /* Setup Tx write back timeout */
472 priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
473
474 /* Init CSQ */
475 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
476 if (ret) {
477 dev_err(hr_dev->dev, "Init CSQ error, ret = %d.\n", ret);
478 return ret;
479 }
480
481 /* Init CRQ */
482 ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
483 if (ret) {
484 dev_err(hr_dev->dev, "Init CRQ error, ret = %d.\n", ret);
485 goto err_crq;
486 }
487
488 /* Init CSQ REG */
489 hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
490
491 /* Init CRQ REG */
492 hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
493
494 return 0;
495
496err_crq:
497 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
498
499 return ret;
500}
501
502static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev)
503{
504 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
505
506 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
507 hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
508}
509
281d0ccf
CIK		 510static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
511 enum hns_roce_opcode_type opcode,
512 bool is_read)
a04ff739
WHX		 513{
514 memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc));
515 desc->opcode = cpu_to_le16(opcode);
516 desc->flag =
517 cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN);
518 if (is_read)
519 desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR);
520 else
521 desc->flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR);
522}
523
524static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev)
525{
526 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
527 u32 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
528
529 return head == priv->cmq.csq.next_to_use;
530}
531
532static int hns_roce_cmq_csq_clean(struct hns_roce_dev *hr_dev)
533{
534 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
535 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
536 struct hns_roce_cmq_desc *desc;
537 u16 ntc = csq->next_to_clean;
538 u32 head;
539 int clean = 0;
540
541 desc = &csq->desc[ntc];
542 head = roce_read(hr_dev, ROCEE_TX_CMQ_HEAD_REG);
543 while (head != ntc) {
544 memset(desc, 0, sizeof(*desc));
545 ntc++;
546 if (ntc == csq->desc_num)
547 ntc = 0;
548 desc = &csq->desc[ntc];
549 clean++;
550 }
551 csq->next_to_clean = ntc;
552
553 return clean;
554}
555
281d0ccf
CIK		 556static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
557 struct hns_roce_cmq_desc *desc, int num)
a04ff739
WHX		 558{
559 struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv;
560 struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;
561 struct hns_roce_cmq_desc *desc_to_use;
562 bool complete = false;
563 u32 timeout = 0;
564 int handle = 0;
565 u16 desc_ret;
566 int ret = 0;
567 int ntc;
568
569 spin_lock_bh(&csq->lock);
570
571 if (num > hns_roce_cmq_space(csq)) {
572 spin_unlock_bh(&csq->lock);
573 return -EBUSY;
574 }
575
576 /*
577 * Record the location of desc in the cmq for this time
578 * which will be use for hardware to write back
579 */
580 ntc = csq->next_to_use;
581
582 while (handle < num) {
583 desc_to_use = &csq->desc[csq->next_to_use];
584 *desc_to_use = desc[handle];
585 dev_dbg(hr_dev->dev, "set cmq desc:\n");
586 csq->next_to_use++;
587 if (csq->next_to_use == csq->desc_num)
588 csq->next_to_use = 0;
589 handle++;
590 }
591
592 /* Write to hardware */
593 roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use);
594
595 /*
596 * If the command is sync, wait for the firmware to write back,
597 * if multi descriptors to be sent, use the first one to check
598 */
599 if ((desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) {
600 do {
601 if (hns_roce_cmq_csq_done(hr_dev))
602 break;
988e175b 603 udelay(1);
a04ff739
WHX		 604 timeout++;
605 } while (timeout < priv->cmq.tx_timeout);
606 }
607
608 if (hns_roce_cmq_csq_done(hr_dev)) {
609 complete = true;
610 handle = 0;
611 while (handle < num) {
612 /* get the result of hardware write back */
613 desc_to_use = &csq->desc[ntc];
614 desc[handle] = *desc_to_use;
615 dev_dbg(hr_dev->dev, "Get cmq desc:\n");
616 desc_ret = desc[handle].retval;
617 if (desc_ret == CMD_EXEC_SUCCESS)
618 ret = 0;
619 else
620 ret = -EIO;
621 priv->cmq.last_status = desc_ret;
622 ntc++;
623 handle++;
624 if (ntc == csq->desc_num)
625 ntc = 0;
626 }
627 }
628
629 if (!complete)
630 ret = -EAGAIN;
631
632 /* clean the command send queue */
633 handle = hns_roce_cmq_csq_clean(hr_dev);
634 if (handle != num)
635 dev_warn(hr_dev->dev, "Cleaned %d, need to clean %d\n",
636 handle, num);
637
638 spin_unlock_bh(&csq->lock);
639
640 return ret;
641}
642
281d0ccf 643static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev)
cfc85f3e
WHX		 644{
645 struct hns_roce_query_version *resp;
646 struct hns_roce_cmq_desc desc;
647 int ret;
648
649 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_HW_VER, true);
650 ret = hns_roce_cmq_send(hr_dev, &desc, 1);
651 if (ret)
652 return ret;
653
654 resp = (struct hns_roce_query_version *)desc.data;
655 hr_dev->hw_rev = le32_to_cpu(resp->rocee_hw_version);
656 hr_dev->vendor_id = le32_to_cpu(resp->rocee_vendor_id);
657
658 return 0;
659}
660
661static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev)
662{
663 struct hns_roce_cfg_global_param *req;
664 struct hns_roce_cmq_desc desc;
665
666 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_GLOBAL_PARAM,
667 false);
668
669 req = (struct hns_roce_cfg_global_param *)desc.data;
670 memset(req, 0, sizeof(*req));
671 roce_set_field(req->time_cfg_udp_port,
672 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_M,
673 CFG_GLOBAL_PARAM_DATA_0_ROCEE_TIME_1US_CFG_S, 0x3e8);
674 roce_set_field(req->time_cfg_udp_port,
675 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_M,
676 CFG_GLOBAL_PARAM_DATA_0_ROCEE_UDP_PORT_S, 0x12b7);
677
678 return hns_roce_cmq_send(hr_dev, &desc, 1);
679}
680
681static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
682{
683 struct hns_roce_cmq_desc desc[2];
684 struct hns_roce_pf_res *res;
685 int ret;
686 int i;
687
688 for (i = 0; i < 2; i++) {
689 hns_roce_cmq_setup_basic_desc(&desc[i],
690 HNS_ROCE_OPC_QUERY_PF_RES, true);
691
692 if (i == 0)
693 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
694 else
695 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
696 }
697
698 ret = hns_roce_cmq_send(hr_dev, desc, 2);
699 if (ret)
700 return ret;
701
702 res = (struct hns_roce_pf_res *)desc[0].data;
703
704 hr_dev->caps.qpc_bt_num = roce_get_field(res->qpc_bt_idx_num,
705 PF_RES_DATA_1_PF_QPC_BT_NUM_M,
706 PF_RES_DATA_1_PF_QPC_BT_NUM_S);
707 hr_dev->caps.srqc_bt_num = roce_get_field(res->srqc_bt_idx_num,
708 PF_RES_DATA_2_PF_SRQC_BT_NUM_M,
709 PF_RES_DATA_2_PF_SRQC_BT_NUM_S);
710 hr_dev->caps.cqc_bt_num = roce_get_field(res->cqc_bt_idx_num,
711 PF_RES_DATA_3_PF_CQC_BT_NUM_M,
712 PF_RES_DATA_3_PF_CQC_BT_NUM_S);
713 hr_dev->caps.mpt_bt_num = roce_get_field(res->mpt_bt_idx_num,
714 PF_RES_DATA_4_PF_MPT_BT_NUM_M,
715 PF_RES_DATA_4_PF_MPT_BT_NUM_S);
716
717 return 0;
718}
719
720static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)
721{
722 struct hns_roce_cmq_desc desc[2];
723 struct hns_roce_vf_res_a *req_a;
724 struct hns_roce_vf_res_b *req_b;
725 int i;
726
727 req_a = (struct hns_roce_vf_res_a *)desc[0].data;
728 req_b = (struct hns_roce_vf_res_b *)desc[1].data;
729 memset(req_a, 0, sizeof(*req_a));
730 memset(req_b, 0, sizeof(*req_b));
731 for (i = 0; i < 2; i++) {
732 hns_roce_cmq_setup_basic_desc(&desc[i],
733 HNS_ROCE_OPC_ALLOC_VF_RES, false);
734
735 if (i == 0)
736 desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
737 else
738 desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
739
740 if (i == 0) {
741 roce_set_field(req_a->vf_qpc_bt_idx_num,
742 VF_RES_A_DATA_1_VF_QPC_BT_IDX_M,
743 VF_RES_A_DATA_1_VF_QPC_BT_IDX_S, 0);
744 roce_set_field(req_a->vf_qpc_bt_idx_num,
745 VF_RES_A_DATA_1_VF_QPC_BT_NUM_M,
746 VF_RES_A_DATA_1_VF_QPC_BT_NUM_S,
747 HNS_ROCE_VF_QPC_BT_NUM);
748
749 roce_set_field(req_a->vf_srqc_bt_idx_num,
750 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M,
751 VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S, 0);
752 roce_set_field(req_a->vf_srqc_bt_idx_num,
753 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M,
754 VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S,
755 HNS_ROCE_VF_SRQC_BT_NUM);
756
757 roce_set_field(req_a->vf_cqc_bt_idx_num,
758 VF_RES_A_DATA_3_VF_CQC_BT_IDX_M,
759 VF_RES_A_DATA_3_VF_CQC_BT_IDX_S, 0);
760 roce_set_field(req_a->vf_cqc_bt_idx_num,
761 VF_RES_A_DATA_3_VF_CQC_BT_NUM_M,
762 VF_RES_A_DATA_3_VF_CQC_BT_NUM_S,
763 HNS_ROCE_VF_CQC_BT_NUM);
764
765 roce_set_field(req_a->vf_mpt_bt_idx_num,
766 VF_RES_A_DATA_4_VF_MPT_BT_IDX_M,
767 VF_RES_A_DATA_4_VF_MPT_BT_IDX_S, 0);
768 roce_set_field(req_a->vf_mpt_bt_idx_num,
769 VF_RES_A_DATA_4_VF_MPT_BT_NUM_M,
770 VF_RES_A_DATA_4_VF_MPT_BT_NUM_S,
771 HNS_ROCE_VF_MPT_BT_NUM);
772
773 roce_set_field(req_a->vf_eqc_bt_idx_num,
774 VF_RES_A_DATA_5_VF_EQC_IDX_M,
775 VF_RES_A_DATA_5_VF_EQC_IDX_S, 0);
776 roce_set_field(req_a->vf_eqc_bt_idx_num,
777 VF_RES_A_DATA_5_VF_EQC_NUM_M,
778 VF_RES_A_DATA_5_VF_EQC_NUM_S,
779 HNS_ROCE_VF_EQC_NUM);
780 } else {
781 roce_set_field(req_b->vf_smac_idx_num,
782 VF_RES_B_DATA_1_VF_SMAC_IDX_M,
783 VF_RES_B_DATA_1_VF_SMAC_IDX_S, 0);
784 roce_set_field(req_b->vf_smac_idx_num,
785 VF_RES_B_DATA_1_VF_SMAC_NUM_M,
786 VF_RES_B_DATA_1_VF_SMAC_NUM_S,
787 HNS_ROCE_VF_SMAC_NUM);
788
789 roce_set_field(req_b->vf_sgid_idx_num,
790 VF_RES_B_DATA_2_VF_SGID_IDX_M,
791 VF_RES_B_DATA_2_VF_SGID_IDX_S, 0);
792 roce_set_field(req_b->vf_sgid_idx_num,
793 VF_RES_B_DATA_2_VF_SGID_NUM_M,
794 VF_RES_B_DATA_2_VF_SGID_NUM_S,
795 HNS_ROCE_VF_SGID_NUM);
796
797 roce_set_field(req_b->vf_qid_idx_sl_num,
798 VF_RES_B_DATA_3_VF_QID_IDX_M,
799 VF_RES_B_DATA_3_VF_QID_IDX_S, 0);
800 roce_set_field(req_b->vf_qid_idx_sl_num,
801 VF_RES_B_DATA_3_VF_SL_NUM_M,
802 VF_RES_B_DATA_3_VF_SL_NUM_S,
803 HNS_ROCE_VF_SL_NUM);
804 }
805 }
806
807 return hns_roce_cmq_send(hr_dev, desc, 2);
808}
809
a81fba28
WHX		 810static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev)
811{
812 u8 srqc_hop_num = hr_dev->caps.srqc_hop_num;
813 u8 qpc_hop_num = hr_dev->caps.qpc_hop_num;
814 u8 cqc_hop_num = hr_dev->caps.cqc_hop_num;
815 u8 mpt_hop_num = hr_dev->caps.mpt_hop_num;
816 struct hns_roce_cfg_bt_attr *req;
817 struct hns_roce_cmq_desc desc;
818
819 hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_BT_ATTR, false);
820 req = (struct hns_roce_cfg_bt_attr *)desc.data;
821 memset(req, 0, sizeof(*req));
822
823 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_M,
824 CFG_BT_ATTR_DATA_0_VF_QPC_BA_PGSZ_S,
825 hr_dev->caps.qpc_ba_pg_sz);
826 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_M,
827 CFG_BT_ATTR_DATA_0_VF_QPC_BUF_PGSZ_S,
828 hr_dev->caps.qpc_buf_pg_sz);
829 roce_set_field(req->vf_qpc_cfg, CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_M,
830 CFG_BT_ATTR_DATA_0_VF_QPC_HOPNUM_S,
831 qpc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : qpc_hop_num);
832
833 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_M,
834 CFG_BT_ATTR_DATA_1_VF_SRQC_BA_PGSZ_S,
835 hr_dev->caps.srqc_ba_pg_sz);
836 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_M,
837 CFG_BT_ATTR_DATA_1_VF_SRQC_BUF_PGSZ_S,
838 hr_dev->caps.srqc_buf_pg_sz);
839 roce_set_field(req->vf_srqc_cfg, CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_M,
840 CFG_BT_ATTR_DATA_1_VF_SRQC_HOPNUM_S,
841 srqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : srqc_hop_num);
842
843 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_M,
844 CFG_BT_ATTR_DATA_2_VF_CQC_BA_PGSZ_S,
845 hr_dev->caps.cqc_ba_pg_sz);
846 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_M,
847 CFG_BT_ATTR_DATA_2_VF_CQC_BUF_PGSZ_S,
848 hr_dev->caps.cqc_buf_pg_sz);
849 roce_set_field(req->vf_cqc_cfg, CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_M,
850 CFG_BT_ATTR_DATA_2_VF_CQC_HOPNUM_S,
851 cqc_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : cqc_hop_num);
852
853 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_M,
854 CFG_BT_ATTR_DATA_3_VF_MPT_BA_PGSZ_S,
855 hr_dev->caps.mpt_ba_pg_sz);
856 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_M,
857 CFG_BT_ATTR_DATA_3_VF_MPT_BUF_PGSZ_S,
858 hr_dev->caps.mpt_buf_pg_sz);
859 roce_set_field(req->vf_mpt_cfg, CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_M,
860 CFG_BT_ATTR_DATA_3_VF_MPT_HOPNUM_S,
861 mpt_hop_num == HNS_ROCE_HOP_NUM_0 ? 0 : mpt_hop_num);
862
863 return hns_roce_cmq_send(hr_dev, &desc, 1);
864}
865
cfc85f3e
WHX		 866static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
867{
868 struct hns_roce_caps *caps = &hr_dev->caps;
869 int ret;
870
871 ret = hns_roce_cmq_query_hw_info(hr_dev);
872 if (ret) {
873 dev_err(hr_dev->dev, "Query firmware version fail, ret = %d.\n",
874 ret);
875 return ret;
876 }
877
878 ret = hns_roce_config_global_param(hr_dev);
879 if (ret) {
880 dev_err(hr_dev->dev, "Configure global param fail, ret = %d.\n",
881 ret);
882 }
883
884 /* Get pf resource owned by every pf */
885 ret = hns_roce_query_pf_resource(hr_dev);
886 if (ret) {
887 dev_err(hr_dev->dev, "Query pf resource fail, ret = %d.\n",
888 ret);
889 return ret;
890 }
891
892 ret = hns_roce_alloc_vf_resource(hr_dev);
893 if (ret) {
894 dev_err(hr_dev->dev, "Allocate vf resource fail, ret = %d.\n",
895 ret);
896 return ret;
897 }
898
899 hr_dev->vendor_part_id = 0;
900 hr_dev->sys_image_guid = 0;
901
902 caps->num_qps = HNS_ROCE_V2_MAX_QP_NUM;
903 caps->max_wqes = HNS_ROCE_V2_MAX_WQE_NUM;
904 caps->num_cqs = HNS_ROCE_V2_MAX_CQ_NUM;
905 caps->max_cqes = HNS_ROCE_V2_MAX_CQE_NUM;
906 caps->max_sq_sg = HNS_ROCE_V2_MAX_SQ_SGE_NUM;
907 caps->max_rq_sg = HNS_ROCE_V2_MAX_RQ_SGE_NUM;
908 caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;
909 caps->num_uars = HNS_ROCE_V2_UAR_NUM;
910 caps->phy_num_uars = HNS_ROCE_V2_PHY_UAR_NUM;
911 caps->num_aeq_vectors = 1;
912 caps->num_comp_vectors = 63;
913 caps->num_other_vectors = 0;
914 caps->num_mtpts = HNS_ROCE_V2_MAX_MTPT_NUM;
915 caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
916 caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
917 caps->num_pds = HNS_ROCE_V2_MAX_PD_NUM;
918 caps->max_qp_init_rdma = HNS_ROCE_V2_MAX_QP_INIT_RDMA;
919 caps->max_qp_dest_rdma = HNS_ROCE_V2_MAX_QP_DEST_RDMA;
920 caps->max_sq_desc_sz = HNS_ROCE_V2_MAX_SQ_DESC_SZ;
921 caps->max_rq_desc_sz = HNS_ROCE_V2_MAX_RQ_DESC_SZ;
922 caps->max_srq_desc_sz = HNS_ROCE_V2_MAX_SRQ_DESC_SZ;
923 caps->qpc_entry_sz = HNS_ROCE_V2_QPC_ENTRY_SZ;
924 caps->irrl_entry_sz = HNS_ROCE_V2_IRRL_ENTRY_SZ;
e92f2c18 925 caps->trrl_entry_sz = HNS_ROCE_V2_TRRL_ENTRY_SZ;
cfc85f3e
WHX		 926 caps->cqc_entry_sz = HNS_ROCE_V2_CQC_ENTRY_SZ;
927 caps->mtpt_entry_sz = HNS_ROCE_V2_MTPT_ENTRY_SZ;
928 caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
929 caps->cq_entry_sz = HNS_ROCE_V2_CQE_ENTRY_SIZE;
930 caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;
931 caps->reserved_lkey = 0;
932 caps->reserved_pds = 0;
933 caps->reserved_mrws = 1;
934 caps->reserved_uars = 0;
935 caps->reserved_cqs = 0;
936
a25d13cb
SX		 937 caps->qpc_ba_pg_sz = 0;
938 caps->qpc_buf_pg_sz = 0;
939 caps->qpc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
940 caps->srqc_ba_pg_sz = 0;
941 caps->srqc_buf_pg_sz = 0;
942 caps->srqc_hop_num = HNS_ROCE_HOP_NUM_0;
943 caps->cqc_ba_pg_sz = 0;
944 caps->cqc_buf_pg_sz = 0;
945 caps->cqc_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
946 caps->mpt_ba_pg_sz = 0;
947 caps->mpt_buf_pg_sz = 0;
948 caps->mpt_hop_num = HNS_ROCE_CONTEXT_HOP_NUM;
ff795f71
WHX		 949 caps->pbl_ba_pg_sz = 0;
950 caps->pbl_buf_pg_sz = 0;
951 caps->pbl_hop_num = HNS_ROCE_PBL_HOP_NUM;
6a93c77a
SX		 952 caps->mtt_ba_pg_sz = 0;
953 caps->mtt_buf_pg_sz = 0;
954 caps->mtt_hop_num = HNS_ROCE_MTT_HOP_NUM;
955 caps->cqe_ba_pg_sz = 0;
956 caps->cqe_buf_pg_sz = 0;
957 caps->cqe_hop_num = HNS_ROCE_CQE_HOP_NUM;
29a1fe5d 958 caps->chunk_sz = HNS_ROCE_V2_TABLE_CHUNK_SIZE;
a25d13cb 959
023c1477
WHX		 960 caps->flags = HNS_ROCE_CAP_FLAG_REREG_MR |
961 HNS_ROCE_CAP_FLAG_ROCE_V1_V2;
cfc85f3e 962 caps->pkey_table_len[0] = 1;
b5ff0f61 963 caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
cfc85f3e
WHX		 964 caps->local_ca_ack_delay = 0;
965 caps->max_mtu = IB_MTU_4096;
966
a81fba28
WHX		 967 ret = hns_roce_v2_set_bt(hr_dev);
968 if (ret)
969 dev_err(hr_dev->dev, "Configure bt attribute fail, ret = %d.\n",
970 ret);
971
972 return ret;
cfc85f3e
WHX		 973}
974
a680f2f3
WHX		 975static int hns_roce_v2_cmd_pending(struct hns_roce_dev *hr_dev)
976{
977 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
978
979 return status >> HNS_ROCE_HW_RUN_BIT_SHIFT;
980}
981
982static int hns_roce_v2_cmd_complete(struct hns_roce_dev *hr_dev)
983{
984 u32 status = readl(hr_dev->reg_base + ROCEE_VF_MB_STATUS_REG);
985
986 return status & HNS_ROCE_HW_MB_STATUS_MASK;
987}
988
989static int hns_roce_v2_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
990 u64 out_param, u32 in_modifier, u8 op_modifier,
991 u16 op, u16 token, int event)
992{
993 struct device *dev = hr_dev->dev;
cc4ed08b
BVA		 994 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base +
995 ROCEE_VF_MB_CFG0_REG);
a680f2f3
WHX		 996 unsigned long end;
997 u32 val0 = 0;
998 u32 val1 = 0;
999
1000 end = msecs_to_jiffies(HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS) + jiffies;
1001 while (hns_roce_v2_cmd_pending(hr_dev)) {
1002 if (time_after(jiffies, end)) {
1003 dev_dbg(dev, "jiffies=%d end=%d\n", (int)jiffies,
1004 (int)end);
1005 return -EAGAIN;
1006 }
1007 cond_resched();
1008 }
1009
1010 roce_set_field(val0, HNS_ROCE_VF_MB4_TAG_MASK,
1011 HNS_ROCE_VF_MB4_TAG_SHIFT, in_modifier);
1012 roce_set_field(val0, HNS_ROCE_VF_MB4_CMD_MASK,
1013 HNS_ROCE_VF_MB4_CMD_SHIFT, op);
1014 roce_set_field(val1, HNS_ROCE_VF_MB5_EVENT_MASK,
1015 HNS_ROCE_VF_MB5_EVENT_SHIFT, event);
1016 roce_set_field(val1, HNS_ROCE_VF_MB5_TOKEN_MASK,
1017 HNS_ROCE_VF_MB5_TOKEN_SHIFT, token);
1018
1019 __raw_writeq(cpu_to_le64(in_param), hcr + 0);
1020 __raw_writeq(cpu_to_le64(out_param), hcr + 2);
1021
1022 /* Memory barrier */
1023 wmb();
1024
1025 __raw_writel(cpu_to_le32(val0), hcr + 4);
1026 __raw_writel(cpu_to_le32(val1), hcr + 5);
1027
1028 mmiowb();
1029
1030 return 0;
1031}
1032
1033static int hns_roce_v2_chk_mbox(struct hns_roce_dev *hr_dev,
1034 unsigned long timeout)
1035{
1036 struct device *dev = hr_dev->dev;
1037 unsigned long end = 0;
1038 u32 status;
1039
1040 end = msecs_to_jiffies(timeout) + jiffies;
1041 while (hns_roce_v2_cmd_pending(hr_dev) && time_before(jiffies, end))
1042 cond_resched();
1043
1044 if (hns_roce_v2_cmd_pending(hr_dev)) {
1045 dev_err(dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1046 return -ETIMEDOUT;
1047 }
1048
1049 status = hns_roce_v2_cmd_complete(hr_dev);
1050 if (status != 0x1) {
1051 dev_err(dev, "mailbox status 0x%x!\n", status);
1052 return -EBUSY;
1053 }
1054
1055 return 0;
1056}
1057
b5ff0f61
WHX		 1058static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, u8 port,
1059 int gid_index, union ib_gid *gid,
1060 const struct ib_gid_attr *attr)
7afddafa 1061{
b5ff0f61 1062 enum hns_roce_sgid_type sgid_type = GID_TYPE_FLAG_ROCE_V1;
7afddafa
WHX		 1063 u32 *p;
1064 u32 val;
1065
b5ff0f61
WHX		 1066 if (!gid || !attr)
1067 return -EINVAL;
1068
1069 if (attr->gid_type == IB_GID_TYPE_ROCE)
1070 sgid_type = GID_TYPE_FLAG_ROCE_V1;
1071
1072 if (attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
1073 if (ipv6_addr_v4mapped((void *)gid))
1074 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV4;
1075 else
1076 sgid_type = GID_TYPE_FLAG_ROCE_V2_IPV6;
1077 }
1078
7afddafa
WHX		 1079 p = (u32 *)&gid->raw[0];
1080 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG0_REG +
1081 0x20 * gid_index);
1082
1083 p = (u32 *)&gid->raw[4];
1084 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG1_REG +
1085 0x20 * gid_index);
1086
1087 p = (u32 *)&gid->raw[8];
1088 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG2_REG +
1089 0x20 * gid_index);
1090
1091 p = (u32 *)&gid->raw[0xc];
1092 roce_raw_write(*p, hr_dev->reg_base + ROCEE_VF_SGID_CFG3_REG +
1093 0x20 * gid_index);
1094
1095 val = roce_read(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index);
1096 roce_set_field(val, ROCEE_VF_SGID_CFG4_SGID_TYPE_M,
b5ff0f61 1097 ROCEE_VF_SGID_CFG4_SGID_TYPE_S, sgid_type);
7afddafa
WHX		 1098
1099 roce_write(hr_dev, ROCEE_VF_SGID_CFG4_REG + 0x20 * gid_index, val);
b5ff0f61
WHX		 1100
1101 return 0;
7afddafa
WHX		 1102}
1103
a74dc41d
WHX		 1104static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1105 u8 *addr)
7afddafa
WHX		 1106{
1107 u16 reg_smac_h;
1108 u32 reg_smac_l;
1109 u32 val;
1110
1111 reg_smac_l = *(u32 *)(&addr[0]);
1112 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_VF_SMAC_CFG0_REG +
1113 0x08 * phy_port);
1114 val = roce_read(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port);
1115
1116 reg_smac_h = *(u16 *)(&addr[4]);
1117 roce_set_field(val, ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M,
1118 ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S, reg_smac_h);
1119 roce_write(hr_dev, ROCEE_VF_SMAC_CFG1_REG + 0x08 * phy_port, val);
a74dc41d
WHX		 1120
1121 return 0;
7afddafa
WHX		 1122}
1123
3958cc56
WHX		 1124static int hns_roce_v2_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1125 unsigned long mtpt_idx)
1126{
1127 struct hns_roce_v2_mpt_entry *mpt_entry;
1128 struct scatterlist *sg;
db270c41 1129 u64 page_addr;
3958cc56 1130 u64 *pages;
db270c41
WHX		 1131 int i, j;
1132 int len;
3958cc56 1133 int entry;
3958cc56
WHX		 1134
1135 mpt_entry = mb_buf;
1136 memset(mpt_entry, 0, sizeof(*mpt_entry));
1137
1138 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_MPT_ST_M,
1139 V2_MPT_BYTE_4_MPT_ST_S, V2_MPT_ST_VALID);
1140 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PBL_HOP_NUM_M,
1141 V2_MPT_BYTE_4_PBL_HOP_NUM_S, mr->pbl_hop_num ==
1142 HNS_ROCE_HOP_NUM_0 ? 0 : mr->pbl_hop_num);
1143 roce_set_field(mpt_entry->byte_4_pd_hop_st,
1144 V2_MPT_BYTE_4_PBL_BA_PG_SZ_M,
1145 V2_MPT_BYTE_4_PBL_BA_PG_SZ_S, mr->pbl_ba_pg_sz);
1146 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1147 V2_MPT_BYTE_4_PD_S, mr->pd);
1148 mpt_entry->byte_4_pd_hop_st = cpu_to_le32(mpt_entry->byte_4_pd_hop_st);
1149
1150 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RA_EN_S, 0);
1151 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_R_INV_EN_S, 1);
1152 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_L_INV_EN_S, 0);
1153 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_BIND_EN_S,
1154 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1155 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_ATOMIC_EN_S, 0);
1156 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1157 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1158 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1159 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1160 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1161 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1162 mpt_entry->byte_8_mw_cnt_en = cpu_to_le32(mpt_entry->byte_8_mw_cnt_en);
1163
1164 roce_set_bit(mpt_entry->byte_12_mw_pa, V2_MPT_BYTE_12_PA_S,
1165 mr->type == MR_TYPE_MR ? 0 : 1);
1166 mpt_entry->byte_12_mw_pa = cpu_to_le32(mpt_entry->byte_12_mw_pa);
1167
1168 mpt_entry->len_l = cpu_to_le32(lower_32_bits(mr->size));
1169 mpt_entry->len_h = cpu_to_le32(upper_32_bits(mr->size));
1170 mpt_entry->lkey = cpu_to_le32(mr->key);
1171 mpt_entry->va_l = cpu_to_le32(lower_32_bits(mr->iova));
1172 mpt_entry->va_h = cpu_to_le32(upper_32_bits(mr->iova));
1173
1174 if (mr->type == MR_TYPE_DMA)
1175 return 0;
1176
1177 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1178
1179 mpt_entry->pbl_ba_l = cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1180 roce_set_field(mpt_entry->byte_48_mode_ba, V2_MPT_BYTE_48_PBL_BA_H_M,
1181 V2_MPT_BYTE_48_PBL_BA_H_S,
1182 upper_32_bits(mr->pbl_ba >> 3));
1183 mpt_entry->byte_48_mode_ba = cpu_to_le32(mpt_entry->byte_48_mode_ba);
1184
1185 pages = (u64 *)__get_free_page(GFP_KERNEL);
1186 if (!pages)
1187 return -ENOMEM;
1188
1189 i = 0;
1190 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
db270c41
WHX		 1191 len = sg_dma_len(sg) >> PAGE_SHIFT;
1192 for (j = 0; j < len; ++j) {
1193 page_addr = sg_dma_address(sg) +
1194 (j << mr->umem->page_shift);
1195 pages[i] = page_addr >> 6;
1196
1197 /* Record the first 2 entry directly to MTPT table */
1198 if (i >= HNS_ROCE_V2_MAX_INNER_MTPT_NUM - 1)
1199 goto found;
1200 i++;
1201 }
3958cc56
WHX		 1202 }
1203
db270c41 1204found:
3958cc56
WHX		 1205 mpt_entry->pa0_l = cpu_to_le32(lower_32_bits(pages[0]));
1206 roce_set_field(mpt_entry->byte_56_pa0_h, V2_MPT_BYTE_56_PA0_H_M,
1207 V2_MPT_BYTE_56_PA0_H_S,
1208 upper_32_bits(pages[0]));
1209 mpt_entry->byte_56_pa0_h = cpu_to_le32(mpt_entry->byte_56_pa0_h);
1210
1211 mpt_entry->pa1_l = cpu_to_le32(lower_32_bits(pages[1]));
1212 roce_set_field(mpt_entry->byte_64_buf_pa1, V2_MPT_BYTE_64_PA1_H_M,
1213 V2_MPT_BYTE_64_PA1_H_S, upper_32_bits(pages[1]));
1214
1215 free_page((unsigned long)pages);
1216
1217 roce_set_field(mpt_entry->byte_64_buf_pa1,
1218 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M,
1219 V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S, mr->pbl_buf_pg_sz);
1220 mpt_entry->byte_64_buf_pa1 = cpu_to_le32(mpt_entry->byte_64_buf_pa1);
1221
1222 return 0;
1223}
1224
a2c80b7b
WHX		 1225static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev,
1226 struct hns_roce_mr *mr, int flags,
1227 u32 pdn, int mr_access_flags, u64 iova,
1228 u64 size, void *mb_buf)
1229{
1230 struct hns_roce_v2_mpt_entry *mpt_entry = mb_buf;
1231
1232 if (flags & IB_MR_REREG_PD) {
1233 roce_set_field(mpt_entry->byte_4_pd_hop_st, V2_MPT_BYTE_4_PD_M,
1234 V2_MPT_BYTE_4_PD_S, pdn);
1235 mr->pd = pdn;
1236 }
1237
1238 if (flags & IB_MR_REREG_ACCESS) {
1239 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1240 V2_MPT_BYTE_8_BIND_EN_S,
1241 (mr_access_flags & IB_ACCESS_MW_BIND ? 1 : 0));
1242 roce_set_bit(mpt_entry->byte_8_mw_cnt_en,
1243 V2_MPT_BYTE_8_ATOMIC_EN_S,
1244 (mr_access_flags & IB_ACCESS_REMOTE_ATOMIC ? 1 : 0));
1245 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RR_EN_S,
1246 (mr_access_flags & IB_ACCESS_REMOTE_READ ? 1 : 0));
1247 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_RW_EN_S,
1248 (mr_access_flags & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1249 roce_set_bit(mpt_entry->byte_8_mw_cnt_en, V2_MPT_BYTE_8_LW_EN_S,
1250 (mr_access_flags & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1251 }
1252
1253 if (flags & IB_MR_REREG_TRANS) {
1254 mpt_entry->va_l = cpu_to_le32(lower_32_bits(iova));
1255 mpt_entry->va_h = cpu_to_le32(upper_32_bits(iova));
1256 mpt_entry->len_l = cpu_to_le32(lower_32_bits(size));
1257 mpt_entry->len_h = cpu_to_le32(upper_32_bits(size));
1258
1259 mpt_entry->pbl_size = cpu_to_le32(mr->pbl_size);
1260 mpt_entry->pbl_ba_l =
1261 cpu_to_le32(lower_32_bits(mr->pbl_ba >> 3));
1262 roce_set_field(mpt_entry->byte_48_mode_ba,
1263 V2_MPT_BYTE_48_PBL_BA_H_M,
1264 V2_MPT_BYTE_48_PBL_BA_H_S,
1265 upper_32_bits(mr->pbl_ba >> 3));
1266 mpt_entry->byte_48_mode_ba =
1267 cpu_to_le32(mpt_entry->byte_48_mode_ba);
1268
1269 mr->iova = iova;
1270 mr->size = size;
1271 }
1272
1273 return 0;
1274}
1275
93aa2187
WHX		 1276static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1277{
1278 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1279 n * HNS_ROCE_V2_CQE_ENTRY_SIZE);
1280}
1281
1282static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, int n)
1283{
1284 struct hns_roce_v2_cqe *cqe = get_cqe_v2(hr_cq, n & hr_cq->ib_cq.cqe);
1285
1286 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1287 return (roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_OWNER_S) ^
1288 !!(n & (hr_cq->ib_cq.cqe + 1))) ? cqe : NULL;
1289}
1290
1291static struct hns_roce_v2_cqe *next_cqe_sw_v2(struct hns_roce_cq *hr_cq)
1292{
1293 return get_sw_cqe_v2(hr_cq, hr_cq->cons_index);
1294}
1295
1296static void hns_roce_v2_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1297{
1298 struct hns_roce_v2_cq_db cq_db;
1299
1300 cq_db.byte_4 = 0;
1301 cq_db.parameter = 0;
1302
1303 roce_set_field(cq_db.byte_4, V2_CQ_DB_BYTE_4_TAG_M,
1304 V2_CQ_DB_BYTE_4_TAG_S, hr_cq->cqn);
1305 roce_set_field(cq_db.byte_4, V2_CQ_DB_BYTE_4_CMD_M,
1306 V2_CQ_DB_BYTE_4_CMD_S, HNS_ROCE_V2_CQ_DB_PTR);
1307
1308 roce_set_field(cq_db.parameter, V2_CQ_DB_PARAMETER_CONS_IDX_M,
1309 V2_CQ_DB_PARAMETER_CONS_IDX_S,
1310 cons_index & ((hr_cq->cq_depth << 1) - 1));
1311 roce_set_field(cq_db.parameter, V2_CQ_DB_PARAMETER_CMD_SN_M,
1312 V2_CQ_DB_PARAMETER_CMD_SN_S, 1);
1313
1314 hns_roce_write64_k((__be32 *)&cq_db, hr_cq->cq_db_l);
1315
1316}
1317
926a01dc
WHX		 1318static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1319 struct hns_roce_srq *srq)
1320{
1321 struct hns_roce_v2_cqe *cqe, *dest;
1322 u32 prod_index;
1323 int nfreed = 0;
1324 u8 owner_bit;
1325
1326 for (prod_index = hr_cq->cons_index; get_sw_cqe_v2(hr_cq, prod_index);
1327 ++prod_index) {
1328 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1329 break;
1330 }
1331
1332 /*
1333 * Now backwards through the CQ, removing CQ entries
1334 * that match our QP by overwriting them with next entries.
1335 */
1336 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1337 cqe = get_cqe_v2(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1338 if ((roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
1339 V2_CQE_BYTE_16_LCL_QPN_S) &
1340 HNS_ROCE_V2_CQE_QPN_MASK) == qpn) {
1341 /* In v1 engine, not support SRQ */
1342 ++nfreed;
1343 } else if (nfreed) {
1344 dest = get_cqe_v2(hr_cq, (prod_index + nfreed) &
1345 hr_cq->ib_cq.cqe);
1346 owner_bit = roce_get_bit(dest->byte_4,
1347 V2_CQE_BYTE_4_OWNER_S);
1348 memcpy(dest, cqe, sizeof(*cqe));
1349 roce_set_bit(dest->byte_4, V2_CQE_BYTE_4_OWNER_S,
1350 owner_bit);
1351 }
1352 }
1353
1354 if (nfreed) {
1355 hr_cq->cons_index += nfreed;
1356 /*
1357 * Make sure update of buffer contents is done before
1358 * updating consumer index.
1359 */
1360 wmb();
1361 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
1362 }
1363}
1364
1365static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1366 struct hns_roce_srq *srq)
1367{
1368 spin_lock_irq(&hr_cq->lock);
1369 __hns_roce_v2_cq_clean(hr_cq, qpn, srq);
1370 spin_unlock_irq(&hr_cq->lock);
1371}
1372
93aa2187
WHX		 1373static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
1374 struct hns_roce_cq *hr_cq, void *mb_buf,
1375 u64 *mtts, dma_addr_t dma_handle, int nent,
1376 u32 vector)
1377{
1378 struct hns_roce_v2_cq_context *cq_context;
1379
1380 cq_context = mb_buf;
1381 memset(cq_context, 0, sizeof(*cq_context));
1382
1383 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CQ_ST_M,
1384 V2_CQC_BYTE_4_CQ_ST_S, V2_CQ_STATE_VALID);
1385 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_SHIFT_M,
1386 V2_CQC_BYTE_4_SHIFT_S, ilog2((unsigned int)nent));
1387 roce_set_field(cq_context->byte_4_pg_ceqn, V2_CQC_BYTE_4_CEQN_M,
1388 V2_CQC_BYTE_4_CEQN_S, vector);
1389 cq_context->byte_4_pg_ceqn = cpu_to_le32(cq_context->byte_4_pg_ceqn);
1390
1391 roce_set_field(cq_context->byte_8_cqn, V2_CQC_BYTE_8_CQN_M,
1392 V2_CQC_BYTE_8_CQN_S, hr_cq->cqn);
1393
1394 cq_context->cqe_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
1395 cq_context->cqe_cur_blk_addr =
1396 cpu_to_le32(cq_context->cqe_cur_blk_addr);
1397
1398 roce_set_field(cq_context->byte_16_hop_addr,
1399 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M,
1400 V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S,
1401 cpu_to_le32((mtts[0]) >> (32 + PAGE_ADDR_SHIFT)));
1402 roce_set_field(cq_context->byte_16_hop_addr,
1403 V2_CQC_BYTE_16_CQE_HOP_NUM_M,
1404 V2_CQC_BYTE_16_CQE_HOP_NUM_S, hr_dev->caps.cqe_hop_num ==
1405 HNS_ROCE_HOP_NUM_0 ? 0 : hr_dev->caps.cqe_hop_num);
1406
1407 cq_context->cqe_nxt_blk_addr = (u32)(mtts[1] >> PAGE_ADDR_SHIFT);
1408 roce_set_field(cq_context->byte_24_pgsz_addr,
1409 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M,
1410 V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S,
1411 cpu_to_le32((mtts[1]) >> (32 + PAGE_ADDR_SHIFT)));
1412 roce_set_field(cq_context->byte_24_pgsz_addr,
1413 V2_CQC_BYTE_24_CQE_BA_PG_SZ_M,
1414 V2_CQC_BYTE_24_CQE_BA_PG_SZ_S,
1415 hr_dev->caps.cqe_ba_pg_sz);
1416 roce_set_field(cq_context->byte_24_pgsz_addr,
1417 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M,
1418 V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S,
1419 hr_dev->caps.cqe_buf_pg_sz);
1420
1421 cq_context->cqe_ba = (u32)(dma_handle >> 3);
1422
1423 roce_set_field(cq_context->byte_40_cqe_ba, V2_CQC_BYTE_40_CQE_BA_M,
1424 V2_CQC_BYTE_40_CQE_BA_S, (dma_handle >> (32 + 3)));
1425}
1426
1427static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq,
1428 enum ib_cq_notify_flags flags)
1429{
1430 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1431 u32 notification_flag;
1432 u32 doorbell[2];
1433
1434 doorbell[0] = 0;
1435 doorbell[1] = 0;
1436
1437 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
1438 V2_CQ_DB_REQ_NOT : V2_CQ_DB_REQ_NOT_SOL;
1439 /*
1440 * flags = 0; Notification Flag = 1, next
1441 * flags = 1; Notification Flag = 0, solocited
1442 */
1443 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_TAG_M, V2_DB_BYTE_4_TAG_S,
1444 hr_cq->cqn);
1445 roce_set_field(doorbell[0], V2_CQ_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S,
1446 HNS_ROCE_V2_CQ_DB_NTR);
1447 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CONS_IDX_M,
1448 V2_CQ_DB_PARAMETER_CONS_IDX_S,
1449 hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
1450 roce_set_field(doorbell[1], V2_CQ_DB_PARAMETER_CMD_SN_M,
26beb85f 1451 V2_CQ_DB_PARAMETER_CMD_SN_S, hr_cq->arm_sn & 0x3);
93aa2187
WHX		 1452 roce_set_bit(doorbell[1], V2_CQ_DB_PARAMETER_NOTIFY_S,
1453 notification_flag);
1454
1455 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1456
1457 return 0;
1458}
1459
1460static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq,
1461 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
1462{
1463 struct hns_roce_dev *hr_dev;
1464 struct hns_roce_v2_cqe *cqe;
1465 struct hns_roce_qp *hr_qp;
1466 struct hns_roce_wq *wq;
1467 int is_send;
1468 u16 wqe_ctr;
1469 u32 opcode;
1470 u32 status;
1471 int qpn;
1472
1473 /* Find cqe according to consumer index */
1474 cqe = next_cqe_sw_v2(hr_cq);
1475 if (!cqe)
1476 return -EAGAIN;
1477
1478 ++hr_cq->cons_index;
1479 /* Memory barrier */
1480 rmb();
1481
1482 /* 0->SQ, 1->RQ */
1483 is_send = !roce_get_bit(cqe->byte_4, V2_CQE_BYTE_4_S_R_S);
1484
1485 qpn = roce_get_field(cqe->byte_16, V2_CQE_BYTE_16_LCL_QPN_M,
1486 V2_CQE_BYTE_16_LCL_QPN_S);
1487
1488 if (!*cur_qp || (qpn & HNS_ROCE_V2_CQE_QPN_MASK) != (*cur_qp)->qpn) {
1489 hr_dev = to_hr_dev(hr_cq->ib_cq.device);
1490 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
1491 if (unlikely(!hr_qp)) {
1492 dev_err(hr_dev->dev, "CQ %06lx with entry for unknown QPN %06x\n",
1493 hr_cq->cqn, (qpn & HNS_ROCE_V2_CQE_QPN_MASK));
1494 return -EINVAL;
1495 }
1496 *cur_qp = hr_qp;
1497 }
1498
1499 wc->qp = &(*cur_qp)->ibqp;
1500 wc->vendor_err = 0;
1501
1502 status = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_STATUS_M,
1503 V2_CQE_BYTE_4_STATUS_S);
1504 switch (status & HNS_ROCE_V2_CQE_STATUS_MASK) {
1505 case HNS_ROCE_CQE_V2_SUCCESS:
1506 wc->status = IB_WC_SUCCESS;
1507 break;
1508 case HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR:
1509 wc->status = IB_WC_LOC_LEN_ERR;
1510 break;
1511 case HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR:
1512 wc->status = IB_WC_LOC_QP_OP_ERR;
1513 break;
1514 case HNS_ROCE_CQE_V2_LOCAL_PROT_ERR:
1515 wc->status = IB_WC_LOC_PROT_ERR;
1516 break;
1517 case HNS_ROCE_CQE_V2_WR_FLUSH_ERR:
1518 wc->status = IB_WC_WR_FLUSH_ERR;
1519 break;
1520 case HNS_ROCE_CQE_V2_MW_BIND_ERR:
1521 wc->status = IB_WC_MW_BIND_ERR;
1522 break;
1523 case HNS_ROCE_CQE_V2_BAD_RESP_ERR:
1524 wc->status = IB_WC_BAD_RESP_ERR;
1525 break;
1526 case HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR:
1527 wc->status = IB_WC_LOC_ACCESS_ERR;
1528 break;
1529 case HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR:
1530 wc->status = IB_WC_REM_INV_REQ_ERR;
1531 break;
1532 case HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR:
1533 wc->status = IB_WC_REM_ACCESS_ERR;
1534 break;
1535 case HNS_ROCE_CQE_V2_REMOTE_OP_ERR:
1536 wc->status = IB_WC_REM_OP_ERR;
1537 break;
1538 case HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR:
1539 wc->status = IB_WC_RETRY_EXC_ERR;
1540 break;
1541 case HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR:
1542 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
1543 break;
1544 case HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR:
1545 wc->status = IB_WC_REM_ABORT_ERR;
1546 break;
1547 default:
1548 wc->status = IB_WC_GENERAL_ERR;
1549 break;
1550 }
1551
1552 /* CQE status error, directly return */
1553 if (wc->status != IB_WC_SUCCESS)
1554 return 0;
1555
1556 if (is_send) {
1557 wc->wc_flags = 0;
1558 /* SQ corresponding to CQE */
1559 switch (roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
1560 V2_CQE_BYTE_4_OPCODE_S) & 0x1f) {
1561 case HNS_ROCE_SQ_OPCODE_SEND:
1562 wc->opcode = IB_WC_SEND;
1563 break;
1564 case HNS_ROCE_SQ_OPCODE_SEND_WITH_INV:
1565 wc->opcode = IB_WC_SEND;
1566 break;
1567 case HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM:
1568 wc->opcode = IB_WC_SEND;
1569 wc->wc_flags |= IB_WC_WITH_IMM;
1570 break;
1571 case HNS_ROCE_SQ_OPCODE_RDMA_READ:
1572 wc->opcode = IB_WC_RDMA_READ;
1573 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
1574 break;
1575 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE:
1576 wc->opcode = IB_WC_RDMA_WRITE;
1577 break;
1578 case HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM:
1579 wc->opcode = IB_WC_RDMA_WRITE;
1580 wc->wc_flags |= IB_WC_WITH_IMM;
1581 break;
1582 case HNS_ROCE_SQ_OPCODE_LOCAL_INV:
1583 wc->opcode = IB_WC_LOCAL_INV;
1584 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
1585 break;
1586 case HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP:
1587 wc->opcode = IB_WC_COMP_SWAP;
1588 wc->byte_len = 8;
1589 break;
1590 case HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD:
1591 wc->opcode = IB_WC_FETCH_ADD;
1592 wc->byte_len = 8;
1593 break;
1594 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP:
1595 wc->opcode = IB_WC_MASKED_COMP_SWAP;
1596 wc->byte_len = 8;
1597 break;
1598 case HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD:
1599 wc->opcode = IB_WC_MASKED_FETCH_ADD;
1600 wc->byte_len = 8;
1601 break;
1602 case HNS_ROCE_SQ_OPCODE_FAST_REG_WR:
1603 wc->opcode = IB_WC_REG_MR;
1604 break;
1605 case HNS_ROCE_SQ_OPCODE_BIND_MW:
1606 wc->opcode = IB_WC_REG_MR;
1607 break;
1608 default:
1609 wc->status = IB_WC_GENERAL_ERR;
1610 break;
1611 }
1612
1613 wq = &(*cur_qp)->sq;
1614 if ((*cur_qp)->sq_signal_bits) {
1615 /*
1616 * If sg_signal_bit is 1,
1617 * firstly tail pointer updated to wqe
1618 * which current cqe correspond to
1619 */
1620 wqe_ctr = (u16)roce_get_field(cqe->byte_4,
1621 V2_CQE_BYTE_4_WQE_INDX_M,
1622 V2_CQE_BYTE_4_WQE_INDX_S);
1623 wq->tail += (wqe_ctr - (u16)wq->tail) &
1624 (wq->wqe_cnt - 1);
1625 }
1626
1627 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
1628 ++wq->tail;
1629 } else {
1630 /* RQ correspond to CQE */
1631 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
1632
1633 opcode = roce_get_field(cqe->byte_4, V2_CQE_BYTE_4_OPCODE_M,
1634 V2_CQE_BYTE_4_OPCODE_S);
1635 switch (opcode & 0x1f) {
1636 case HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM:
1637 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
1638 wc->wc_flags = IB_WC_WITH_IMM;
1639 wc->ex.imm_data = le32_to_cpu(cqe->rkey_immtdata);
1640 break;
1641 case HNS_ROCE_V2_OPCODE_SEND:
1642 wc->opcode = IB_WC_RECV;
1643 wc->wc_flags = 0;
1644 break;
1645 case HNS_ROCE_V2_OPCODE_SEND_WITH_IMM:
1646 wc->opcode = IB_WC_RECV;
1647 wc->wc_flags = IB_WC_WITH_IMM;
1648 wc->ex.imm_data = le32_to_cpu(cqe->rkey_immtdata);
1649 break;
1650 case HNS_ROCE_V2_OPCODE_SEND_WITH_INV:
1651 wc->opcode = IB_WC_RECV;
1652 wc->wc_flags = IB_WC_WITH_INVALIDATE;
1653 wc->ex.invalidate_rkey = cqe->rkey_immtdata;
1654 break;
1655 default:
1656 wc->status = IB_WC_GENERAL_ERR;
1657 break;
1658 }
1659
1660 /* Update tail pointer, record wr_id */
1661 wq = &(*cur_qp)->rq;
1662 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
1663 ++wq->tail;
1664
1665 wc->sl = (u8)roce_get_field(cqe->byte_32, V2_CQE_BYTE_32_SL_M,
1666 V2_CQE_BYTE_32_SL_S);
1667 wc->src_qp = (u8)roce_get_field(cqe->byte_32,
1668 V2_CQE_BYTE_32_RMT_QPN_M,
1669 V2_CQE_BYTE_32_RMT_QPN_S);
1670 wc->wc_flags |= (roce_get_bit(cqe->byte_32,
1671 V2_CQE_BYTE_32_GRH_S) ?
1672 IB_WC_GRH : 0);
1673 }
1674
1675 return 0;
1676}
1677
1678static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries,
1679 struct ib_wc *wc)
1680{
1681 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1682 struct hns_roce_qp *cur_qp = NULL;
1683 unsigned long flags;
1684 int npolled;
1685
1686 spin_lock_irqsave(&hr_cq->lock, flags);
1687
1688 for (npolled = 0; npolled < num_entries; ++npolled) {
1689 if (hns_roce_v2_poll_one(hr_cq, &cur_qp, wc + npolled))
1690 break;
1691 }
1692
1693 if (npolled) {
1694 /* Memory barrier */
1695 wmb();
1696 hns_roce_v2_cq_set_ci(hr_cq, hr_cq->cons_index);
1697 }
1698
1699 spin_unlock_irqrestore(&hr_cq->lock, flags);
1700
1701 return npolled;
1702}
1703
a81fba28
WHX		 1704static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev,
1705 struct hns_roce_hem_table *table, int obj,
1706 int step_idx)
1707{
1708 struct device *dev = hr_dev->dev;
1709 struct hns_roce_cmd_mailbox *mailbox;
1710 struct hns_roce_hem_iter iter;
1711 struct hns_roce_hem_mhop mhop;
1712 struct hns_roce_hem *hem;
1713 unsigned long mhop_obj = obj;
1714 int i, j, k;
1715 int ret = 0;
1716 u64 hem_idx = 0;
1717 u64 l1_idx = 0;
1718 u64 bt_ba = 0;
1719 u32 chunk_ba_num;
1720 u32 hop_num;
1721 u16 op = 0xff;
1722
1723 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
1724 return 0;
1725
1726 hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
1727 i = mhop.l0_idx;
1728 j = mhop.l1_idx;
1729 k = mhop.l2_idx;
1730 hop_num = mhop.hop_num;
1731 chunk_ba_num = mhop.bt_chunk_size / 8;
1732
1733 if (hop_num == 2) {
1734 hem_idx = i * chunk_ba_num * chunk_ba_num + j * chunk_ba_num +
1735 k;
1736 l1_idx = i * chunk_ba_num + j;
1737 } else if (hop_num == 1) {
1738 hem_idx = i * chunk_ba_num + j;
1739 } else if (hop_num == HNS_ROCE_HOP_NUM_0) {
1740 hem_idx = i;
1741 }
1742
1743 switch (table->type) {
1744 case HEM_TYPE_QPC:
1745 op = HNS_ROCE_CMD_WRITE_QPC_BT0;
1746 break;
1747 case HEM_TYPE_MTPT:
1748 op = HNS_ROCE_CMD_WRITE_MPT_BT0;
1749 break;
1750 case HEM_TYPE_CQC:
1751 op = HNS_ROCE_CMD_WRITE_CQC_BT0;
1752 break;
1753 case HEM_TYPE_SRQC:
1754 op = HNS_ROCE_CMD_WRITE_SRQC_BT0;
1755 break;
1756 default:
1757 dev_warn(dev, "Table %d not to be written by mailbox!\n",
1758 table->type);
1759 return 0;
1760 }
1761 op += step_idx;
1762
1763 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1764 if (IS_ERR(mailbox))
1765 return PTR_ERR(mailbox);
1766
1767 if (check_whether_last_step(hop_num, step_idx)) {
1768 hem = table->hem[hem_idx];
1769 for (hns_roce_hem_first(hem, &iter);
1770 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
1771 bt_ba = hns_roce_hem_addr(&iter);
1772
1773 /* configure the ba, tag, and op */
1774 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma,
1775 obj, 0, op,
1776 HNS_ROCE_CMD_TIMEOUT_MSECS);
1777 }
1778 } else {
1779 if (step_idx == 0)
1780 bt_ba = table->bt_l0_dma_addr[i];
1781 else if (step_idx == 1 && hop_num == 2)
1782 bt_ba = table->bt_l1_dma_addr[l1_idx];
1783
1784 /* configure the ba, tag, and op */
1785 ret = hns_roce_cmd_mbox(hr_dev, bt_ba, mailbox->dma, obj,
1786 0, op, HNS_ROCE_CMD_TIMEOUT_MSECS);
1787 }
1788
1789 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1790 return ret;
1791}
1792
1793static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev,
1794 struct hns_roce_hem_table *table, int obj,
1795 int step_idx)
1796{
1797 struct device *dev = hr_dev->dev;
1798 struct hns_roce_cmd_mailbox *mailbox;
1799 int ret = 0;
1800 u16 op = 0xff;
1801
1802 if (!hns_roce_check_whether_mhop(hr_dev, table->type))
1803 return 0;
1804
1805 switch (table->type) {
1806 case HEM_TYPE_QPC:
1807 op = HNS_ROCE_CMD_DESTROY_QPC_BT0;
1808 break;
1809 case HEM_TYPE_MTPT:
1810 op = HNS_ROCE_CMD_DESTROY_MPT_BT0;
1811 break;
1812 case HEM_TYPE_CQC:
1813 op = HNS_ROCE_CMD_DESTROY_CQC_BT0;
1814 break;
1815 case HEM_TYPE_SRQC:
1816 op = HNS_ROCE_CMD_DESTROY_SRQC_BT0;
1817 break;
1818 default:
1819 dev_warn(dev, "Table %d not to be destroyed by mailbox!\n",
1820 table->type);
1821 return 0;
1822 }
1823 op += step_idx;
1824
1825 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1826 if (IS_ERR(mailbox))
1827 return PTR_ERR(mailbox);
1828
1829 /* configure the tag and op */
1830 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, obj, 0, op,
1831 HNS_ROCE_CMD_TIMEOUT_MSECS);
1832
1833 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1834 return ret;
1835}
1836
926a01dc
WHX		 1837static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev,
1838 struct hns_roce_mtt *mtt,
1839 enum ib_qp_state cur_state,
1840 enum ib_qp_state new_state,
1841 struct hns_roce_v2_qp_context *context,
1842 struct hns_roce_qp *hr_qp)
1843{
1844 struct hns_roce_cmd_mailbox *mailbox;
1845 int ret;
1846
1847 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1848 if (IS_ERR(mailbox))
1849 return PTR_ERR(mailbox);
1850
1851 memcpy(mailbox->buf, context, sizeof(*context) * 2);
1852
1853 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
1854 HNS_ROCE_CMD_MODIFY_QPC,
1855 HNS_ROCE_CMD_TIMEOUT_MSECS);
1856
1857 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1858
1859 return ret;
1860}
1861
1862static void modify_qp_reset_to_init(struct ib_qp *ibqp,
1863 const struct ib_qp_attr *attr,
1864 struct hns_roce_v2_qp_context *context,
1865 struct hns_roce_v2_qp_context *qpc_mask)
1866{
1867 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1868
1869 /*
1870 * In v2 engine, software pass context and context mask to hardware
1871 * when modifying qp. If software need modify some fields in context,
1872 * we should set all bits of the relevant fields in context mask to
1873 * 0 at the same time, else set them to 0x1.
1874 */
1875 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
1876 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
1877 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
1878 V2_QPC_BYTE_4_TST_S, 0);
1879
1880 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
1881 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
1882 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
1883 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
1884 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
1885
1886 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
1887 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
1888 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
1889 V2_QPC_BYTE_4_SQPN_S, 0);
1890
1891 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
1892 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
1893 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
1894 V2_QPC_BYTE_16_PD_S, 0);
1895
1896 roce_set_field(context->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
1897 V2_QPC_BYTE_20_RQWS_S, ilog2(hr_qp->rq.max_gs));
1898 roce_set_field(qpc_mask->byte_20_smac_sgid_idx, V2_QPC_BYTE_20_RQWS_M,
1899 V2_QPC_BYTE_20_RQWS_S, 0);
1900
1901 roce_set_field(context->byte_20_smac_sgid_idx,
1902 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
1903 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
1904 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
1905 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
1906
1907 roce_set_field(context->byte_20_smac_sgid_idx,
1908 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
1909 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
1910 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
1911 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
1912
1913 /* No VLAN need to set 0xFFF */
1914 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M,
1915 V2_QPC_BYTE_24_VLAN_IDX_S, 0xfff);
1916 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_VLAN_IDX_M,
1917 V2_QPC_BYTE_24_VLAN_IDX_S, 0);
1918
1919 /*
1920 * Set some fields in context to zero, Because the default values
1921 * of all fields in context are zero, we need not set them to 0 again.
1922 * but we should set the relevant fields of context mask to 0.
1923 */
1924 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_TX_ERR_S, 0);
1925 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_SQ_RX_ERR_S, 0);
1926 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_TX_ERR_S, 0);
1927 roce_set_bit(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_RQ_RX_ERR_S, 0);
1928
1929 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_MAPID_M,
1930 V2_QPC_BYTE_60_MAPID_S, 0);
1931
1932 roce_set_bit(qpc_mask->byte_60_qpst_mapid,
1933 V2_QPC_BYTE_60_INNER_MAP_IND_S, 0);
1934 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_MAP_IND_S,
1935 0);
1936 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_RQ_MAP_IND_S,
1937 0);
1938 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_EXT_MAP_IND_S,
1939 0);
1940 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_RLS_IND_S,
1941 0);
1942 roce_set_bit(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_SQ_EXT_IND_S,
1943 0);
1944 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CNP_TX_FLAG_S, 0);
1945 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_CE_FLAG_S, 0);
1946
1947 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
1948 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
1949 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S, 0);
1950
1951 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
1952 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE));
1953 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S, 0);
1954
1955 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
1956 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC));
1957 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S, 0);
1958
1959 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
1960
1961 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
1962 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
1963 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
1964 V2_QPC_BYTE_80_RX_CQN_S, 0);
1965 if (ibqp->srq) {
1966 roce_set_field(context->byte_76_srqn_op_en,
1967 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
1968 to_hr_srq(ibqp->srq)->srqn);
1969 roce_set_field(qpc_mask->byte_76_srqn_op_en,
1970 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
1971 roce_set_bit(context->byte_76_srqn_op_en,
1972 V2_QPC_BYTE_76_SRQ_EN_S, 1);
1973 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
1974 V2_QPC_BYTE_76_SRQ_EN_S, 0);
1975 }
1976
1977 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
1978 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
1979 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
1980 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
1981 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
1982 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
1983
1984 roce_set_field(qpc_mask->byte_92_srq_info, V2_QPC_BYTE_92_SRQ_INFO_M,
1985 V2_QPC_BYTE_92_SRQ_INFO_S, 0);
1986
1987 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
1988 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
1989
1990 roce_set_field(qpc_mask->byte_104_rq_sge,
1991 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M,
1992 V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S, 0);
1993
1994 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
1995 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
1996 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
1997 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
1998 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
1999 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2000 V2_QPC_BYTE_108_RX_REQ_RNR_S, 0);
2001
2002 qpc_mask->rq_rnr_timer = 0;
2003 qpc_mask->rx_msg_len = 0;
2004 qpc_mask->rx_rkey_pkt_info = 0;
2005 qpc_mask->rx_va = 0;
2006
2007 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2008 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2009 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2010 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2011
2012 roce_set_bit(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RSVD_RAQ_MAP_S, 0);
2013 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M,
2014 V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S, 0);
2015 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M,
2016 V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S, 0);
2017
2018 roce_set_field(qpc_mask->byte_144_raq,
2019 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M,
2020 V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S, 0);
2021 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_RTY_INI_IND_S,
2022 0);
2023 roce_set_field(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RAQ_CREDIT_M,
2024 V2_QPC_BYTE_144_RAQ_CREDIT_S, 0);
2025 roce_set_bit(qpc_mask->byte_144_raq, V2_QPC_BYTE_144_RESP_RTY_FLG_S, 0);
2026
2027 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RQ_MSN_M,
2028 V2_QPC_BYTE_148_RQ_MSN_S, 0);
2029 roce_set_field(qpc_mask->byte_148_raq, V2_QPC_BYTE_148_RAQ_SYNDROME_M,
2030 V2_QPC_BYTE_148_RAQ_SYNDROME_S, 0);
2031
2032 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2033 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2034 roce_set_field(qpc_mask->byte_152_raq,
2035 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M,
2036 V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S, 0);
2037
2038 roce_set_field(qpc_mask->byte_156_raq, V2_QPC_BYTE_156_RAQ_USE_PKTN_M,
2039 V2_QPC_BYTE_156_RAQ_USE_PKTN_S, 0);
2040
2041 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2042 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M,
2043 V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S, 0);
2044 roce_set_field(qpc_mask->byte_160_sq_ci_pi,
2045 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M,
2046 V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S, 0);
2047
2048 roce_set_field(context->byte_168_irrl_idx,
2049 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2050 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2051 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2052 roce_set_field(qpc_mask->byte_168_irrl_idx,
2053 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2054 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2055
2056 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2057 V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
b5fddb7c 2058 roce_set_bit(qpc_mask->byte_168_irrl_idx,
2059 V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
926a01dc
WHX		 2060 roce_set_field(qpc_mask->byte_168_irrl_idx,
2061 V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
2062 V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
2063
2064 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2065 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 4);
2066 roce_set_field(qpc_mask->byte_172_sq_psn,
2067 V2_QPC_BYTE_172_ACK_REQ_FREQ_M,
2068 V2_QPC_BYTE_172_ACK_REQ_FREQ_S, 0);
2069
2070 roce_set_bit(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_MSG_RNR_FLG_S,
2071 0);
2072
2073 roce_set_field(qpc_mask->byte_176_msg_pktn,
2074 V2_QPC_BYTE_176_MSG_USE_PKTN_M,
2075 V2_QPC_BYTE_176_MSG_USE_PKTN_S, 0);
2076 roce_set_field(qpc_mask->byte_176_msg_pktn,
2077 V2_QPC_BYTE_176_IRRL_HEAD_PRE_M,
2078 V2_QPC_BYTE_176_IRRL_HEAD_PRE_S, 0);
2079
2080 roce_set_field(qpc_mask->byte_184_irrl_idx,
2081 V2_QPC_BYTE_184_IRRL_IDX_MSB_M,
2082 V2_QPC_BYTE_184_IRRL_IDX_MSB_S, 0);
2083
2084 qpc_mask->cur_sge_offset = 0;
2085
2086 roce_set_field(qpc_mask->byte_192_ext_sge,
2087 V2_QPC_BYTE_192_CUR_SGE_IDX_M,
2088 V2_QPC_BYTE_192_CUR_SGE_IDX_S, 0);
2089 roce_set_field(qpc_mask->byte_192_ext_sge,
2090 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M,
2091 V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S, 0);
2092
2093 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2094 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2095
2096 roce_set_field(qpc_mask->byte_200_sq_max, V2_QPC_BYTE_200_SQ_MAX_IDX_M,
2097 V2_QPC_BYTE_200_SQ_MAX_IDX_S, 0);
2098 roce_set_field(qpc_mask->byte_200_sq_max,
2099 V2_QPC_BYTE_200_LCL_OPERATED_CNT_M,
2100 V2_QPC_BYTE_200_LCL_OPERATED_CNT_S, 0);
2101
2102 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RNR_FLG_S, 0);
2103 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_PKT_RTY_FLG_S, 0);
2104
2105 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2106 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2107
2108 qpc_mask->sq_timer = 0;
2109
2110 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2111 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2112 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2113 roce_set_field(qpc_mask->byte_232_irrl_sge,
2114 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2115 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2116
2117 qpc_mask->irrl_cur_sge_offset = 0;
2118
2119 roce_set_field(qpc_mask->byte_240_irrl_tail,
2120 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2121 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2122 roce_set_field(qpc_mask->byte_240_irrl_tail,
2123 V2_QPC_BYTE_240_IRRL_TAIL_RD_M,
2124 V2_QPC_BYTE_240_IRRL_TAIL_RD_S, 0);
2125 roce_set_field(qpc_mask->byte_240_irrl_tail,
2126 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2127 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2128
2129 roce_set_field(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_M,
2130 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2131 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_ACK_PSN_ERR_S,
2132 0);
2133 roce_set_field(qpc_mask->byte_248_ack_psn,
2134 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2135 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
2136 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_IRRL_PSN_VLD_S,
2137 0);
2138 roce_set_bit(qpc_mask->byte_248_ack_psn,
2139 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
2140 roce_set_bit(qpc_mask->byte_248_ack_psn, V2_QPC_BYTE_248_CQ_ERR_IND_S,
2141 0);
2142
2143 hr_qp->access_flags = attr->qp_access_flags;
2144 hr_qp->pkey_index = attr->pkey_index;
2145 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2146 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->send_cq)->cqn);
2147 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2148 V2_QPC_BYTE_252_TX_CQN_S, 0);
2149
2150 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_ERR_TYPE_M,
2151 V2_QPC_BYTE_252_ERR_TYPE_S, 0);
2152
2153 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2154 V2_QPC_BYTE_256_RQ_CQE_IDX_M,
2155 V2_QPC_BYTE_256_RQ_CQE_IDX_S, 0);
2156 roce_set_field(qpc_mask->byte_256_sqflush_rqcqe,
2157 V2_QPC_BYTE_256_SQ_FLUSH_IDX_M,
2158 V2_QPC_BYTE_256_SQ_FLUSH_IDX_S, 0);
2159}
2160
2161static void modify_qp_init_to_init(struct ib_qp *ibqp,
2162 const struct ib_qp_attr *attr, int attr_mask,
2163 struct hns_roce_v2_qp_context *context,
2164 struct hns_roce_v2_qp_context *qpc_mask)
2165{
2166 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2167
2168 /*
2169 * In v2 engine, software pass context and context mask to hardware
2170 * when modifying qp. If software need modify some fields in context,
2171 * we should set all bits of the relevant fields in context mask to
2172 * 0 at the same time, else set them to 0x1.
2173 */
2174 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2175 V2_QPC_BYTE_4_TST_S, to_hr_qp_type(hr_qp->ibqp.qp_type));
2176 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_TST_M,
2177 V2_QPC_BYTE_4_TST_S, 0);
2178
2179 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2180 V2_QPC_BYTE_4_SGE_SHIFT_S, hr_qp->sq.max_gs > 2 ?
2181 ilog2((unsigned int)hr_qp->sge.sge_cnt) : 0);
2182 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SGE_SHIFT_M,
2183 V2_QPC_BYTE_4_SGE_SHIFT_S, 0);
2184
2185 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2186 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2187 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2188 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2189 0);
2190
2191 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2192 !!(attr->qp_access_flags &
2193 IB_ACCESS_REMOTE_WRITE));
2194 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2195 0);
2196
2197 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2198 !!(attr->qp_access_flags &
2199 IB_ACCESS_REMOTE_ATOMIC));
2200 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2201 0);
2202 } else {
2203 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2204 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_READ));
2205 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RRE_S,
2206 0);
2207
2208 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2209 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_WRITE));
2210 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RWE_S,
2211 0);
2212
2213 roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2214 !!(hr_qp->access_flags & IB_ACCESS_REMOTE_ATOMIC));
2215 roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_ATE_S,
2216 0);
2217 }
2218
2219 roce_set_field(context->byte_20_smac_sgid_idx,
2220 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S,
2221 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2222 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2223 V2_QPC_BYTE_20_SQ_SHIFT_M, V2_QPC_BYTE_20_SQ_SHIFT_S, 0);
2224
2225 roce_set_field(context->byte_20_smac_sgid_idx,
2226 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S,
2227 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2228 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2229 V2_QPC_BYTE_20_RQ_SHIFT_M, V2_QPC_BYTE_20_RQ_SHIFT_S, 0);
2230
2231 roce_set_field(context->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2232 V2_QPC_BYTE_16_PD_S, to_hr_pd(ibqp->pd)->pdn);
2233 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz, V2_QPC_BYTE_16_PD_M,
2234 V2_QPC_BYTE_16_PD_S, 0);
2235
2236 roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2237 V2_QPC_BYTE_80_RX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2238 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
2239 V2_QPC_BYTE_80_RX_CQN_S, 0);
2240
2241 roce_set_field(context->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2242 V2_QPC_BYTE_252_TX_CQN_S, to_hr_cq(ibqp->recv_cq)->cqn);
2243 roce_set_field(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_TX_CQN_M,
2244 V2_QPC_BYTE_252_TX_CQN_S, 0);
2245
2246 if (ibqp->srq) {
2247 roce_set_bit(context->byte_76_srqn_op_en,
2248 V2_QPC_BYTE_76_SRQ_EN_S, 1);
2249 roce_set_bit(qpc_mask->byte_76_srqn_op_en,
2250 V2_QPC_BYTE_76_SRQ_EN_S, 0);
2251 roce_set_field(context->byte_76_srqn_op_en,
2252 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S,
2253 to_hr_srq(ibqp->srq)->srqn);
2254 roce_set_field(qpc_mask->byte_76_srqn_op_en,
2255 V2_QPC_BYTE_76_SRQN_M, V2_QPC_BYTE_76_SRQN_S, 0);
2256 }
2257
2258 if (attr_mask & IB_QP_PKEY_INDEX)
2259 context->qkey_xrcd = attr->pkey_index;
2260 else
2261 context->qkey_xrcd = hr_qp->pkey_index;
2262
2263 roce_set_field(context->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2264 V2_QPC_BYTE_4_SQPN_S, hr_qp->qpn);
2265 roce_set_field(qpc_mask->byte_4_sqpn_tst, V2_QPC_BYTE_4_SQPN_M,
2266 V2_QPC_BYTE_4_SQPN_S, 0);
2267
2268 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2269 V2_QPC_BYTE_56_DQPN_S, hr_qp->qpn);
2270 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2271 V2_QPC_BYTE_56_DQPN_S, 0);
2272 roce_set_field(context->byte_168_irrl_idx,
2273 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2274 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S,
2275 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2276 roce_set_field(qpc_mask->byte_168_irrl_idx,
2277 V2_QPC_BYTE_168_SQ_SHIFT_BAK_M,
2278 V2_QPC_BYTE_168_SQ_SHIFT_BAK_S, 0);
2279}
2280
2281static int modify_qp_init_to_rtr(struct ib_qp *ibqp,
2282 const struct ib_qp_attr *attr, int attr_mask,
2283 struct hns_roce_v2_qp_context *context,
2284 struct hns_roce_v2_qp_context *qpc_mask)
2285{
2286 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2287 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2288 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2289 struct device *dev = hr_dev->dev;
e92f2c18 2290 dma_addr_t dma_handle_3;
926a01dc
WHX		 2291 dma_addr_t dma_handle_2;
2292 dma_addr_t dma_handle;
2293 u32 page_size;
2294 u8 port_num;
e92f2c18 2295 u64 *mtts_3;
926a01dc
WHX		 2296 u64 *mtts_2;
2297 u64 *mtts;
2298 u8 *dmac;
2299 u8 *smac;
2300 int port;
2301
2302 /* Search qp buf's mtts */
2303 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2304 hr_qp->mtt.first_seg, &dma_handle);
2305 if (!mtts) {
2306 dev_err(dev, "qp buf pa find failed\n");
2307 return -EINVAL;
2308 }
2309
2310 /* Search IRRL's mtts */
2311 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2312 hr_qp->qpn, &dma_handle_2);
2313 if (!mtts_2) {
2314 dev_err(dev, "qp irrl_table find failed\n");
2315 return -EINVAL;
2316 }
2317
e92f2c18 2318 /* Search TRRL's mtts */
2319 mtts_3 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.trrl_table,
2320 hr_qp->qpn, &dma_handle_3);
2321 if (!mtts_3) {
2322 dev_err(dev, "qp trrl_table find failed\n");
2323 return -EINVAL;
2324 }
2325
926a01dc
WHX		 2326 if ((attr_mask & IB_QP_ALT_PATH) || (attr_mask & IB_QP_ACCESS_FLAGS) ||
2327 (attr_mask & IB_QP_PKEY_INDEX) || (attr_mask & IB_QP_QKEY)) {
2328 dev_err(dev, "INIT2RTR attr_mask (0x%x) error\n", attr_mask);
2329 return -EINVAL;
2330 }
2331
2332 dmac = (u8 *)attr->ah_attr.roce.dmac;
2333 context->wqe_sge_ba = (u32)(dma_handle >> 3);
2334 qpc_mask->wqe_sge_ba = 0;
2335
2336 /*
2337 * In v2 engine, software pass context and context mask to hardware
2338 * when modifying qp. If software need modify some fields in context,
2339 * we should set all bits of the relevant fields in context mask to
2340 * 0 at the same time, else set them to 0x1.
2341 */
2342 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
2343 V2_QPC_BYTE_12_WQE_SGE_BA_S, dma_handle >> (32 + 3));
2344 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_WQE_SGE_BA_M,
2345 V2_QPC_BYTE_12_WQE_SGE_BA_S, 0);
2346
2347 roce_set_field(context->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
2348 V2_QPC_BYTE_12_SQ_HOP_NUM_S,
2349 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
2350 0 : hr_dev->caps.mtt_hop_num);
2351 roce_set_field(qpc_mask->byte_12_sq_hop, V2_QPC_BYTE_12_SQ_HOP_NUM_M,
2352 V2_QPC_BYTE_12_SQ_HOP_NUM_S, 0);
2353
2354 roce_set_field(context->byte_20_smac_sgid_idx,
2355 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
2356 V2_QPC_BYTE_20_SGE_HOP_NUM_S,
2357 hr_qp->sq.max_gs > 2 ? hr_dev->caps.mtt_hop_num : 0);
2358 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2359 V2_QPC_BYTE_20_SGE_HOP_NUM_M,
2360 V2_QPC_BYTE_20_SGE_HOP_NUM_S, 0);
2361
2362 roce_set_field(context->byte_20_smac_sgid_idx,
2363 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
2364 V2_QPC_BYTE_20_RQ_HOP_NUM_S,
2365 hr_dev->caps.mtt_hop_num == HNS_ROCE_HOP_NUM_0 ?
2366 0 : hr_dev->caps.mtt_hop_num);
2367 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2368 V2_QPC_BYTE_20_RQ_HOP_NUM_M,
2369 V2_QPC_BYTE_20_RQ_HOP_NUM_S, 0);
2370
2371 roce_set_field(context->byte_16_buf_ba_pg_sz,
2372 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
2373 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S,
2374 hr_dev->caps.mtt_ba_pg_sz);
2375 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
2376 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M,
2377 V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S, 0);
2378
2379 roce_set_field(context->byte_16_buf_ba_pg_sz,
2380 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
2381 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S,
2382 hr_dev->caps.mtt_buf_pg_sz);
2383 roce_set_field(qpc_mask->byte_16_buf_ba_pg_sz,
2384 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M,
2385 V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S, 0);
2386
2387 roce_set_field(context->byte_80_rnr_rx_cqn,
2388 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
2389 V2_QPC_BYTE_80_MIN_RNR_TIME_S, attr->min_rnr_timer);
2390 roce_set_field(qpc_mask->byte_80_rnr_rx_cqn,
2391 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
2392 V2_QPC_BYTE_80_MIN_RNR_TIME_S, 0);
2393
2394 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
2395 context->rq_cur_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size]
2396 >> PAGE_ADDR_SHIFT);
2397 qpc_mask->rq_cur_blk_addr = 0;
2398
2399 roce_set_field(context->byte_92_srq_info,
2400 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
2401 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S,
2402 mtts[hr_qp->rq.offset / page_size]
2403 >> (32 + PAGE_ADDR_SHIFT));
2404 roce_set_field(qpc_mask->byte_92_srq_info,
2405 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M,
2406 V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S, 0);
2407
2408 context->rq_nxt_blk_addr = (u32)(mtts[hr_qp->rq.offset / page_size + 1]
2409 >> PAGE_ADDR_SHIFT);
2410 qpc_mask->rq_nxt_blk_addr = 0;
2411
2412 roce_set_field(context->byte_104_rq_sge,
2413 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
2414 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S,
2415 mtts[hr_qp->rq.offset / page_size + 1]
2416 >> (32 + PAGE_ADDR_SHIFT));
2417 roce_set_field(qpc_mask->byte_104_rq_sge,
2418 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M,
2419 V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S, 0);
2420
2421 roce_set_field(context->byte_108_rx_reqepsn,
2422 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
2423 V2_QPC_BYTE_108_RX_REQ_EPSN_S, attr->rq_psn);
2424 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2425 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
2426 V2_QPC_BYTE_108_RX_REQ_EPSN_S, 0);
2427
e92f2c18 2428 roce_set_field(context->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
2429 V2_QPC_BYTE_132_TRRL_BA_S, dma_handle_3 >> 4);
2430 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_BA_M,
2431 V2_QPC_BYTE_132_TRRL_BA_S, 0);
2432 context->trrl_ba = (u32)(dma_handle_3 >> (16 + 4));
2433 qpc_mask->trrl_ba = 0;
2434 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
2435 V2_QPC_BYTE_140_TRRL_BA_S,
2436 (u32)(dma_handle_3 >> (32 + 16 + 4)));
2437 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_TRRL_BA_M,
2438 V2_QPC_BYTE_140_TRRL_BA_S, 0);
2439
d5514246 2440 context->irrl_ba = (u32)(dma_handle_2 >> 6);
926a01dc
WHX		 2441 qpc_mask->irrl_ba = 0;
2442 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
2443 V2_QPC_BYTE_208_IRRL_BA_S,
d5514246 2444 dma_handle_2 >> (32 + 6));
926a01dc
WHX		 2445 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_IRRL_BA_M,
2446 V2_QPC_BYTE_208_IRRL_BA_S, 0);
2447
2448 roce_set_bit(context->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 1);
2449 roce_set_bit(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_RMT_E2E_S, 0);
2450
2451 roce_set_bit(context->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
2452 hr_qp->sq_signal_bits);
2453 roce_set_bit(qpc_mask->byte_252_err_txcqn, V2_QPC_BYTE_252_SIG_TYPE_S,
2454 0);
2455
2456 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) : hr_qp->port;
2457
2458 smac = (u8 *)hr_dev->dev_addr[port];
2459 /* when dmac equals smac or loop_idc is 1, it should loopback */
2460 if (ether_addr_equal_unaligned(dmac, smac) ||
2461 hr_dev->loop_idc == 0x1) {
2462 roce_set_bit(context->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 1);
2463 roce_set_bit(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_LBI_S, 0);
2464 }
2465
2466 roce_set_field(context->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
2467 V2_QPC_BYTE_140_RR_MAX_S,
2468 ilog2((unsigned int)attr->max_dest_rd_atomic));
2469 roce_set_field(qpc_mask->byte_140_raq, V2_QPC_BYTE_140_RR_MAX_M,
2470 V2_QPC_BYTE_140_RR_MAX_S, 0);
2471
2472 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2473 V2_QPC_BYTE_56_DQPN_S, attr->dest_qp_num);
2474 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_DQPN_M,
2475 V2_QPC_BYTE_56_DQPN_S, 0);
2476
2477 /* Configure GID index */
2478 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2479 roce_set_field(context->byte_20_smac_sgid_idx,
2480 V2_QPC_BYTE_20_SGID_IDX_M,
2481 V2_QPC_BYTE_20_SGID_IDX_S,
2482 hns_get_gid_index(hr_dev, port_num - 1,
2483 grh->sgid_index));
2484 roce_set_field(qpc_mask->byte_20_smac_sgid_idx,
2485 V2_QPC_BYTE_20_SGID_IDX_M,
2486 V2_QPC_BYTE_20_SGID_IDX_S, 0);
2487 memcpy(&(context->dmac), dmac, 4);
2488 roce_set_field(context->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
2489 V2_QPC_BYTE_52_DMAC_S, *((u16 *)(&dmac[4])));
2490 qpc_mask->dmac = 0;
2491 roce_set_field(qpc_mask->byte_52_udpspn_dmac, V2_QPC_BYTE_52_DMAC_M,
2492 V2_QPC_BYTE_52_DMAC_S, 0);
2493
2494 roce_set_field(context->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
2495 V2_QPC_BYTE_56_LP_PKTN_INI_S, 4);
2496 roce_set_field(qpc_mask->byte_56_dqpn_err, V2_QPC_BYTE_56_LP_PKTN_INI_M,
2497 V2_QPC_BYTE_56_LP_PKTN_INI_S, 0);
2498
2499 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
2500 V2_QPC_BYTE_24_HOP_LIMIT_S, grh->hop_limit);
2501 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
2502 V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
2503
2504 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
2505 V2_QPC_BYTE_28_FL_S, grh->flow_label);
2506 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
2507 V2_QPC_BYTE_28_FL_S, 0);
2508
2509 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
2510 V2_QPC_BYTE_24_TC_S, grh->traffic_class);
2511 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
2512 V2_QPC_BYTE_24_TC_S, 0);
2513
2514 roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
2515 V2_QPC_BYTE_24_MTU_S, attr->path_mtu);
2516 roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_MTU_M,
2517 V2_QPC_BYTE_24_MTU_S, 0);
2518
2519 memcpy(context->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
2520 memset(qpc_mask->dgid, 0, sizeof(grh->dgid.raw));
2521
2522 roce_set_field(context->byte_84_rq_ci_pi,
2523 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2524 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, hr_qp->rq.head);
2525 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2526 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M,
2527 V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S, 0);
2528
2529 roce_set_field(qpc_mask->byte_84_rq_ci_pi,
2530 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M,
2531 V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S, 0);
2532 roce_set_bit(qpc_mask->byte_108_rx_reqepsn,
2533 V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S, 0);
2534 roce_set_field(qpc_mask->byte_96_rx_reqmsn, V2_QPC_BYTE_96_RX_REQ_MSN_M,
2535 V2_QPC_BYTE_96_RX_REQ_MSN_S, 0);
2536 roce_set_field(qpc_mask->byte_108_rx_reqepsn,
2537 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M,
2538 V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S, 0);
2539
2540 context->rq_rnr_timer = 0;
2541 qpc_mask->rq_rnr_timer = 0;
2542
2543 roce_set_field(context->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2544 V2_QPC_BYTE_152_RAQ_PSN_S, attr->rq_psn - 1);
2545 roce_set_field(qpc_mask->byte_152_raq, V2_QPC_BYTE_152_RAQ_PSN_M,
2546 V2_QPC_BYTE_152_RAQ_PSN_S, 0);
2547
2548 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_HEAD_MAX_M,
2549 V2_QPC_BYTE_132_TRRL_HEAD_MAX_S, 0);
2550 roce_set_field(qpc_mask->byte_132_trrl, V2_QPC_BYTE_132_TRRL_TAIL_MAX_M,
2551 V2_QPC_BYTE_132_TRRL_TAIL_MAX_S, 0);
2552
2553 roce_set_field(context->byte_168_irrl_idx,
2554 V2_QPC_BYTE_168_LP_SGEN_INI_M,
2555 V2_QPC_BYTE_168_LP_SGEN_INI_S, 3);
2556 roce_set_field(qpc_mask->byte_168_irrl_idx,
2557 V2_QPC_BYTE_168_LP_SGEN_INI_M,
2558 V2_QPC_BYTE_168_LP_SGEN_INI_S, 0);
2559
2560 roce_set_field(context->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
2561 V2_QPC_BYTE_208_SR_MAX_S,
2562 ilog2((unsigned int)attr->max_rd_atomic));
2563 roce_set_field(qpc_mask->byte_208_irrl, V2_QPC_BYTE_208_SR_MAX_M,
2564 V2_QPC_BYTE_208_SR_MAX_S, 0);
2565
2566 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2567 V2_QPC_BYTE_28_SL_S, rdma_ah_get_sl(&attr->ah_attr));
2568 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2569 V2_QPC_BYTE_28_SL_S, 0);
2570 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
2571
2572 return 0;
2573}
2574
2575static int modify_qp_rtr_to_rts(struct ib_qp *ibqp,
2576 const struct ib_qp_attr *attr, int attr_mask,
2577 struct hns_roce_v2_qp_context *context,
2578 struct hns_roce_v2_qp_context *qpc_mask)
2579{
2580 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2581 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2582 struct device *dev = hr_dev->dev;
2583 dma_addr_t dma_handle;
befb63b4 2584 u32 page_size;
926a01dc
WHX		 2585 u64 *mtts;
2586
2587 /* Search qp buf's mtts */
2588 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
2589 hr_qp->mtt.first_seg, &dma_handle);
2590 if (!mtts) {
2591 dev_err(dev, "qp buf pa find failed\n");
2592 return -EINVAL;
2593 }
2594
2595 /* If exist optional param, return error */
2596 if ((attr_mask & IB_QP_ALT_PATH) || (attr_mask & IB_QP_ACCESS_FLAGS) ||
2597 (attr_mask & IB_QP_QKEY) || (attr_mask & IB_QP_PATH_MIG_STATE) ||
2598 (attr_mask & IB_QP_CUR_STATE) ||
2599 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
2600 dev_err(dev, "RTR2RTS attr_mask (0x%x)error\n", attr_mask);
2601 return -EINVAL;
2602 }
2603
2604 /*
2605 * In v2 engine, software pass context and context mask to hardware
2606 * when modifying qp. If software need modify some fields in context,
2607 * we should set all bits of the relevant fields in context mask to
2608 * 0 at the same time, else set them to 0x1.
2609 */
2610 roce_set_field(context->byte_60_qpst_mapid,
2611 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
2612 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, attr->retry_cnt);
2613 roce_set_field(qpc_mask->byte_60_qpst_mapid,
2614 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_M,
2615 V2_QPC_BYTE_60_RTY_NUM_INI_BAK_S, 0);
2616
2617 context->sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2618 roce_set_field(context->byte_168_irrl_idx,
2619 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
2620 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S,
2621 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
2622 qpc_mask->sq_cur_blk_addr = 0;
2623 roce_set_field(qpc_mask->byte_168_irrl_idx,
2624 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M,
2625 V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S, 0);
2626
befb63b4 2627 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
2628 context->sq_cur_sge_blk_addr = hr_qp->sq.max_gs > 2 ?
2629 ((u32)(mtts[hr_qp->sge.offset / page_size]
2630 >> PAGE_ADDR_SHIFT)) : 0;
2631 roce_set_field(context->byte_184_irrl_idx,
2632 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
2633 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S,
2634 hr_qp->sq.max_gs > 2 ?
2635 (mtts[hr_qp->sge.offset / page_size] >>
2636 (32 + PAGE_ADDR_SHIFT)) : 0);
2637 qpc_mask->sq_cur_sge_blk_addr = 0;
2638 roce_set_field(qpc_mask->byte_184_irrl_idx,
2639 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M,
2640 V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S, 0);
2641
926a01dc
WHX		 2642 context->rx_sq_cur_blk_addr = (u32)(mtts[0] >> PAGE_ADDR_SHIFT);
2643 roce_set_field(context->byte_232_irrl_sge,
2644 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
2645 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S,
2646 mtts[0] >> (32 + PAGE_ADDR_SHIFT));
2647 qpc_mask->rx_sq_cur_blk_addr = 0;
2648 roce_set_field(qpc_mask->byte_232_irrl_sge,
2649 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M,
2650 V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S, 0);
2651
2652 /*
2653 * Set some fields in context to zero, Because the default values
2654 * of all fields in context are zero, we need not set them to 0 again.
2655 * but we should set the relevant fields of context mask to 0.
2656 */
2657 roce_set_field(qpc_mask->byte_232_irrl_sge,
2658 V2_QPC_BYTE_232_IRRL_SGE_IDX_M,
2659 V2_QPC_BYTE_232_IRRL_SGE_IDX_S, 0);
2660
2661 roce_set_field(qpc_mask->byte_240_irrl_tail,
2662 V2_QPC_BYTE_240_RX_ACK_MSN_M,
2663 V2_QPC_BYTE_240_RX_ACK_MSN_S, 0);
2664
2665 roce_set_field(context->byte_244_rnr_rxack,
2666 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
2667 V2_QPC_BYTE_244_RX_ACK_EPSN_S, attr->sq_psn);
2668 roce_set_field(qpc_mask->byte_244_rnr_rxack,
2669 V2_QPC_BYTE_244_RX_ACK_EPSN_M,
2670 V2_QPC_BYTE_244_RX_ACK_EPSN_S, 0);
2671
2672 roce_set_field(qpc_mask->byte_248_ack_psn,
2673 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M,
2674 V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S, 0);
2675 roce_set_bit(qpc_mask->byte_248_ack_psn,
2676 V2_QPC_BYTE_248_IRRL_PSN_VLD_S, 0);
2677 roce_set_field(qpc_mask->byte_248_ack_psn,
2678 V2_QPC_BYTE_248_IRRL_PSN_M,
2679 V2_QPC_BYTE_248_IRRL_PSN_S, 0);
2680
2681 roce_set_field(qpc_mask->byte_240_irrl_tail,
2682 V2_QPC_BYTE_240_IRRL_TAIL_REAL_M,
2683 V2_QPC_BYTE_240_IRRL_TAIL_REAL_S, 0);
2684
2685 roce_set_field(context->byte_220_retry_psn_msn,
2686 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
2687 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, attr->sq_psn);
2688 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2689 V2_QPC_BYTE_220_RETRY_MSG_PSN_M,
2690 V2_QPC_BYTE_220_RETRY_MSG_PSN_S, 0);
2691
2692 roce_set_field(context->byte_224_retry_msg,
2693 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
2694 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, attr->sq_psn >> 16);
2695 roce_set_field(qpc_mask->byte_224_retry_msg,
2696 V2_QPC_BYTE_224_RETRY_MSG_PSN_M,
2697 V2_QPC_BYTE_224_RETRY_MSG_PSN_S, 0);
2698
2699 roce_set_field(context->byte_224_retry_msg,
2700 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
2701 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, attr->sq_psn);
2702 roce_set_field(qpc_mask->byte_224_retry_msg,
2703 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M,
2704 V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S, 0);
2705
2706 roce_set_field(qpc_mask->byte_220_retry_psn_msn,
2707 V2_QPC_BYTE_220_RETRY_MSG_MSN_M,
2708 V2_QPC_BYTE_220_RETRY_MSG_MSN_S, 0);
2709
2710 roce_set_bit(qpc_mask->byte_248_ack_psn,
2711 V2_QPC_BYTE_248_RNR_RETRY_FLAG_S, 0);
2712
2713 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_CHECK_FLG_M,
2714 V2_QPC_BYTE_212_CHECK_FLG_S, 0);
2715
2716 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
2717 V2_QPC_BYTE_212_RETRY_CNT_S, attr->retry_cnt);
2718 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_CNT_M,
2719 V2_QPC_BYTE_212_RETRY_CNT_S, 0);
2720
2721 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
2722 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, attr->retry_cnt);
2723 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_RETRY_NUM_INIT_M,
2724 V2_QPC_BYTE_212_RETRY_NUM_INIT_S, 0);
2725
2726 roce_set_field(context->byte_244_rnr_rxack,
2727 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
2728 V2_QPC_BYTE_244_RNR_NUM_INIT_S, attr->rnr_retry);
2729 roce_set_field(qpc_mask->byte_244_rnr_rxack,
2730 V2_QPC_BYTE_244_RNR_NUM_INIT_M,
2731 V2_QPC_BYTE_244_RNR_NUM_INIT_S, 0);
2732
2733 roce_set_field(context->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
2734 V2_QPC_BYTE_244_RNR_CNT_S, attr->rnr_retry);
2735 roce_set_field(qpc_mask->byte_244_rnr_rxack, V2_QPC_BYTE_244_RNR_CNT_M,
2736 V2_QPC_BYTE_244_RNR_CNT_S, 0);
2737
2738 roce_set_field(context->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
2739 V2_QPC_BYTE_212_LSN_S, 0x100);
2740 roce_set_field(qpc_mask->byte_212_lsn, V2_QPC_BYTE_212_LSN_M,
2741 V2_QPC_BYTE_212_LSN_S, 0);
2742
28726461 2743 if (attr_mask & IB_QP_TIMEOUT) {
926a01dc
WHX		 2744 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
2745 V2_QPC_BYTE_28_AT_S, attr->timeout);
28726461 2746 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_AT_M,
2747 V2_QPC_BYTE_28_AT_S, 0);
2748 }
926a01dc
WHX		 2749
2750 roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2751 V2_QPC_BYTE_28_SL_S,
2752 rdma_ah_get_sl(&attr->ah_attr));
2753 roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_SL_M,
2754 V2_QPC_BYTE_28_SL_S, 0);
2755 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
2756
2757 roce_set_field(context->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
2758 V2_QPC_BYTE_172_SQ_CUR_PSN_S, attr->sq_psn);
2759 roce_set_field(qpc_mask->byte_172_sq_psn, V2_QPC_BYTE_172_SQ_CUR_PSN_M,
2760 V2_QPC_BYTE_172_SQ_CUR_PSN_S, 0);
2761
2762 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_IRRL_HEAD_M,
2763 V2_QPC_BYTE_196_IRRL_HEAD_S, 0);
2764 roce_set_field(context->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
2765 V2_QPC_BYTE_196_SQ_MAX_PSN_S, attr->sq_psn);
2766 roce_set_field(qpc_mask->byte_196_sq_psn, V2_QPC_BYTE_196_SQ_MAX_PSN_M,
2767 V2_QPC_BYTE_196_SQ_MAX_PSN_S, 0);
2768
2769 return 0;
2770}
2771
2772static int hns_roce_v2_modify_qp(struct ib_qp *ibqp,
2773 const struct ib_qp_attr *attr,
2774 int attr_mask, enum ib_qp_state cur_state,
2775 enum ib_qp_state new_state)
2776{
2777 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2778 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2779 struct hns_roce_v2_qp_context *context;
2780 struct hns_roce_v2_qp_context *qpc_mask;
2781 struct device *dev = hr_dev->dev;
2782 int ret = -EINVAL;
2783
2784 context = kzalloc(2 * sizeof(*context), GFP_KERNEL);
2785 if (!context)
2786 return -ENOMEM;
2787
2788 qpc_mask = context + 1;
2789 /*
2790 * In v2 engine, software pass context and context mask to hardware
2791 * when modifying qp. If software need modify some fields in context,
2792 * we should set all bits of the relevant fields in context mask to
2793 * 0 at the same time, else set them to 0x1.
2794 */
2795 memset(qpc_mask, 0xff, sizeof(*qpc_mask));
2796 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2797 modify_qp_reset_to_init(ibqp, attr, context, qpc_mask);
2798 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2799 modify_qp_init_to_init(ibqp, attr, attr_mask, context,
2800 qpc_mask);
2801 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2802 ret = modify_qp_init_to_rtr(ibqp, attr, attr_mask, context,
2803 qpc_mask);
2804 if (ret)
2805 goto out;
2806 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
2807 ret = modify_qp_rtr_to_rts(ibqp, attr, attr_mask, context,
2808 qpc_mask);
2809 if (ret)
2810 goto out;
2811 } else if ((cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) ||
2812 (cur_state == IB_QPS_SQE && new_state == IB_QPS_RTS) ||
2813 (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD) ||
2814 (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD) ||
2815 (cur_state == IB_QPS_SQD && new_state == IB_QPS_RTS) ||
2816 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
2817 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
2818 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
2819 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
2820 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
2821 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
2822 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
2823 (cur_state == IB_QPS_SQD && new_state == IB_QPS_ERR) ||
2824 (cur_state == IB_QPS_SQE && new_state == IB_QPS_ERR)) {
2825 /* Nothing */
2826 ;
2827 } else {
2828 dev_err(dev, "Illegal state for QP!\n");
2829 goto out;
2830 }
2831
2832 /* Every status migrate must change state */
2833 roce_set_field(context->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
2834 V2_QPC_BYTE_60_QP_ST_S, new_state);
2835 roce_set_field(qpc_mask->byte_60_qpst_mapid, V2_QPC_BYTE_60_QP_ST_M,
2836 V2_QPC_BYTE_60_QP_ST_S, 0);
2837
2838 /* SW pass context to HW */
2839 ret = hns_roce_v2_qp_modify(hr_dev, &hr_qp->mtt, cur_state, new_state,
2840 context, hr_qp);
2841 if (ret) {
2842 dev_err(dev, "hns_roce_qp_modify failed(%d)\n", ret);
2843 goto out;
2844 }
2845
2846 hr_qp->state = new_state;
2847
2848 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2849 hr_qp->resp_depth = attr->max_dest_rd_atomic;
2850 if (attr_mask & IB_QP_PORT) {
2851 hr_qp->port = attr->port_num - 1;
2852 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
2853 }
2854
2855 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2856 hns_roce_v2_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2857 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2858 if (ibqp->send_cq != ibqp->recv_cq)
2859 hns_roce_v2_cq_clean(to_hr_cq(ibqp->send_cq),
2860 hr_qp->qpn, NULL);
2861
2862 hr_qp->rq.head = 0;
2863 hr_qp->rq.tail = 0;
2864 hr_qp->sq.head = 0;
2865 hr_qp->sq.tail = 0;
2866 hr_qp->sq_next_wqe = 0;
2867 hr_qp->next_sge = 0;
2868 }
2869
2870out:
2871 kfree(context);
2872 return ret;
2873}
2874
2875static inline enum ib_qp_state to_ib_qp_st(enum hns_roce_v2_qp_state state)
2876{
2877 switch (state) {
2878 case HNS_ROCE_QP_ST_RST: return IB_QPS_RESET;
2879 case HNS_ROCE_QP_ST_INIT: return IB_QPS_INIT;
2880 case HNS_ROCE_QP_ST_RTR: return IB_QPS_RTR;
2881 case HNS_ROCE_QP_ST_RTS: return IB_QPS_RTS;
2882 case HNS_ROCE_QP_ST_SQ_DRAINING:
2883 case HNS_ROCE_QP_ST_SQD: return IB_QPS_SQD;
2884 case HNS_ROCE_QP_ST_SQER: return IB_QPS_SQE;
2885 case HNS_ROCE_QP_ST_ERR: return IB_QPS_ERR;
2886 default: return -1;
2887 }
2888}
2889
2890static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev,
2891 struct hns_roce_qp *hr_qp,
2892 struct hns_roce_v2_qp_context *hr_context)
2893{
2894 struct hns_roce_cmd_mailbox *mailbox;
2895 int ret;
2896
2897 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2898 if (IS_ERR(mailbox))
2899 return PTR_ERR(mailbox);
2900
2901 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
2902 HNS_ROCE_CMD_QUERY_QPC,
2903 HNS_ROCE_CMD_TIMEOUT_MSECS);
2904 if (ret) {
2905 dev_err(hr_dev->dev, "QUERY QP cmd process error\n");
2906 goto out;
2907 }
2908
2909 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
2910
2911out:
2912 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2913 return ret;
2914}
2915
2916static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2917 int qp_attr_mask,
2918 struct ib_qp_init_attr *qp_init_attr)
2919{
2920 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2921 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2922 struct hns_roce_v2_qp_context *context;
2923 struct device *dev = hr_dev->dev;
2924 int tmp_qp_state;
2925 int state;
2926 int ret;
2927
2928 context = kzalloc(sizeof(*context), GFP_KERNEL);
2929 if (!context)
2930 return -ENOMEM;
2931
2932 memset(qp_attr, 0, sizeof(*qp_attr));
2933 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
2934
2935 mutex_lock(&hr_qp->mutex);
2936
2937 if (hr_qp->state == IB_QPS_RESET) {
2938 qp_attr->qp_state = IB_QPS_RESET;
63ea641f 2939 ret = 0;
926a01dc
WHX		 2940 goto done;
2941 }
2942
2943 ret = hns_roce_v2_query_qpc(hr_dev, hr_qp, context);
2944 if (ret) {
2945 dev_err(dev, "query qpc error\n");
2946 ret = -EINVAL;
2947 goto out;
2948 }
2949
2950 state = roce_get_field(context->byte_60_qpst_mapid,
2951 V2_QPC_BYTE_60_QP_ST_M, V2_QPC_BYTE_60_QP_ST_S);
2952 tmp_qp_state = to_ib_qp_st((enum hns_roce_v2_qp_state)state);
2953 if (tmp_qp_state == -1) {
2954 dev_err(dev, "Illegal ib_qp_state\n");
2955 ret = -EINVAL;
2956 goto out;
2957 }
2958 hr_qp->state = (u8)tmp_qp_state;
2959 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
2960 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->byte_24_mtu_tc,
2961 V2_QPC_BYTE_24_MTU_M,
2962 V2_QPC_BYTE_24_MTU_S);
2963 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 2964 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
926a01dc
WHX		 2965 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
2966 qp_attr->qkey = V2_QKEY_VAL;
2967
2968 qp_attr->rq_psn = roce_get_field(context->byte_108_rx_reqepsn,
2969 V2_QPC_BYTE_108_RX_REQ_EPSN_M,
2970 V2_QPC_BYTE_108_RX_REQ_EPSN_S);
2971 qp_attr->sq_psn = (u32)roce_get_field(context->byte_172_sq_psn,
2972 V2_QPC_BYTE_172_SQ_CUR_PSN_M,
2973 V2_QPC_BYTE_172_SQ_CUR_PSN_S);
2974 qp_attr->dest_qp_num = (u8)roce_get_field(context->byte_56_dqpn_err,
2975 V2_QPC_BYTE_56_DQPN_M,
2976 V2_QPC_BYTE_56_DQPN_S);
2977 qp_attr->qp_access_flags = ((roce_get_bit(context->byte_76_srqn_op_en,
2978 V2_QPC_BYTE_76_RRE_S)) << 2) |
2979 ((roce_get_bit(context->byte_76_srqn_op_en,
2980 V2_QPC_BYTE_76_RWE_S)) << 1) |
2981 ((roce_get_bit(context->byte_76_srqn_op_en,
2982 V2_QPC_BYTE_76_ATE_S)) << 3);
2983 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
2984 hr_qp->ibqp.qp_type == IB_QPT_UC) {
2985 struct ib_global_route *grh =
2986 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
2987
2988 rdma_ah_set_sl(&qp_attr->ah_attr,
2989 roce_get_field(context->byte_28_at_fl,
2990 V2_QPC_BYTE_28_SL_M,
2991 V2_QPC_BYTE_28_SL_S));
2992 grh->flow_label = roce_get_field(context->byte_28_at_fl,
2993 V2_QPC_BYTE_28_FL_M,
2994 V2_QPC_BYTE_28_FL_S);
2995 grh->sgid_index = roce_get_field(context->byte_20_smac_sgid_idx,
2996 V2_QPC_BYTE_20_SGID_IDX_M,
2997 V2_QPC_BYTE_20_SGID_IDX_S);
2998 grh->hop_limit = roce_get_field(context->byte_24_mtu_tc,
2999 V2_QPC_BYTE_24_HOP_LIMIT_M,
3000 V2_QPC_BYTE_24_HOP_LIMIT_S);
3001 grh->traffic_class = roce_get_field(context->byte_24_mtu_tc,
3002 V2_QPC_BYTE_24_TC_M,
3003 V2_QPC_BYTE_24_TC_S);
3004
3005 memcpy(grh->dgid.raw, context->dgid, sizeof(grh->dgid.raw));
3006 }
3007
3008 qp_attr->port_num = hr_qp->port + 1;
3009 qp_attr->sq_draining = 0;
3010 qp_attr->max_rd_atomic = 1 << roce_get_field(context->byte_208_irrl,
3011 V2_QPC_BYTE_208_SR_MAX_M,
3012 V2_QPC_BYTE_208_SR_MAX_S);
3013 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->byte_140_raq,
3014 V2_QPC_BYTE_140_RR_MAX_M,
3015 V2_QPC_BYTE_140_RR_MAX_S);
3016 qp_attr->min_rnr_timer = (u8)roce_get_field(context->byte_80_rnr_rx_cqn,
3017 V2_QPC_BYTE_80_MIN_RNR_TIME_M,
3018 V2_QPC_BYTE_80_MIN_RNR_TIME_S);
3019 qp_attr->timeout = (u8)roce_get_field(context->byte_28_at_fl,
3020 V2_QPC_BYTE_28_AT_M,
3021 V2_QPC_BYTE_28_AT_S);
3022 qp_attr->retry_cnt = roce_get_field(context->byte_212_lsn,
3023 V2_QPC_BYTE_212_RETRY_CNT_M,
3024 V2_QPC_BYTE_212_RETRY_CNT_S);
3025 qp_attr->rnr_retry = context->rq_rnr_timer;
3026
3027done:
3028 qp_attr->cur_qp_state = qp_attr->qp_state;
3029 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3030 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3031
3032 if (!ibqp->uobject) {
3033 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3034 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3035 } else {
3036 qp_attr->cap.max_send_wr = 0;
3037 qp_attr->cap.max_send_sge = 0;
3038 }
3039
3040 qp_init_attr->cap = qp_attr->cap;
3041
3042out:
3043 mutex_unlock(&hr_qp->mutex);
3044 kfree(context);
3045 return ret;
3046}
3047
3048static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
3049 struct hns_roce_qp *hr_qp,
3050 int is_user)
3051{
3052 struct hns_roce_cq *send_cq, *recv_cq;
3053 struct device *dev = hr_dev->dev;
3054 int ret;
3055
3056 if (hr_qp->ibqp.qp_type == IB_QPT_RC && hr_qp->state != IB_QPS_RESET) {
3057 /* Modify qp to reset before destroying qp */
3058 ret = hns_roce_v2_modify_qp(&hr_qp->ibqp, NULL, 0,
3059 hr_qp->state, IB_QPS_RESET);
3060 if (ret) {
3061 dev_err(dev, "modify QP %06lx to ERR failed.\n",
3062 hr_qp->qpn);
3063 return ret;
3064 }
3065 }
3066
3067 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3068 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3069
3070 hns_roce_lock_cqs(send_cq, recv_cq);
3071
3072 if (!is_user) {
3073 __hns_roce_v2_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3074 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3075 if (send_cq != recv_cq)
3076 __hns_roce_v2_cq_clean(send_cq, hr_qp->qpn, NULL);
3077 }
3078
3079 hns_roce_qp_remove(hr_dev, hr_qp);
3080
3081 hns_roce_unlock_cqs(send_cq, recv_cq);
3082
3083 hns_roce_qp_free(hr_dev, hr_qp);
3084
3085 /* Not special_QP, free their QPN */
3086 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
3087 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
3088 (hr_qp->ibqp.qp_type == IB_QPT_UD))
3089 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3090
3091 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3092
3093 if (is_user) {
3094 ib_umem_release(hr_qp->umem);
3095 } else {
3096 kfree(hr_qp->sq.wrid);
3097 kfree(hr_qp->rq.wrid);
3098 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3099 }
3100
3101 return 0;
3102}
3103
3104static int hns_roce_v2_destroy_qp(struct ib_qp *ibqp)
3105{
3106 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3107 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3108 int ret;
3109
3110 ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
3111 if (ret) {
3112 dev_err(hr_dev->dev, "Destroy qp failed(%d)\n", ret);
3113 return ret;
3114 }
3115
3116 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
3117 kfree(hr_to_hr_sqp(hr_qp));
3118 else
3119 kfree(hr_qp);
3120
3121 return 0;
3122}
3123
b156269d 3124static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
3125{
3126 struct hns_roce_dev *hr_dev = to_hr_dev(cq->device);
3127 struct hns_roce_v2_cq_context *cq_context;
3128 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
3129 struct hns_roce_v2_cq_context *cqc_mask;
3130 struct hns_roce_cmd_mailbox *mailbox;
3131 int ret;
3132
3133 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3134 if (IS_ERR(mailbox))
3135 return PTR_ERR(mailbox);
3136
3137 cq_context = mailbox->buf;
3138 cqc_mask = (struct hns_roce_v2_cq_context *)mailbox->buf + 1;
3139
3140 memset(cqc_mask, 0xff, sizeof(*cqc_mask));
3141
3142 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3143 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3144 cq_count);
3145 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3146 V2_CQC_BYTE_56_CQ_MAX_CNT_M, V2_CQC_BYTE_56_CQ_MAX_CNT_S,
3147 0);
3148 roce_set_field(cq_context->byte_56_cqe_period_maxcnt,
3149 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3150 cq_period);
3151 roce_set_field(cqc_mask->byte_56_cqe_period_maxcnt,
3152 V2_CQC_BYTE_56_CQ_PERIOD_M, V2_CQC_BYTE_56_CQ_PERIOD_S,
3153 0);
3154
3155 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_cq->cqn, 1,
3156 HNS_ROCE_CMD_MODIFY_CQC,
3157 HNS_ROCE_CMD_TIMEOUT_MSECS);
3158 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3159 if (ret)
3160 dev_err(hr_dev->dev, "MODIFY CQ Failed to cmd mailbox.\n");
3161
3162 return ret;
3163}
3164
a04ff739
WHX		 3165static const struct hns_roce_hw hns_roce_hw_v2 = {
3166 .cmq_init = hns_roce_v2_cmq_init,
3167 .cmq_exit = hns_roce_v2_cmq_exit,
cfc85f3e 3168 .hw_profile = hns_roce_v2_profile,
a680f2f3
WHX		 3169 .post_mbox = hns_roce_v2_post_mbox,
3170 .chk_mbox = hns_roce_v2_chk_mbox,
7afddafa
WHX		 3171 .set_gid = hns_roce_v2_set_gid,
3172 .set_mac = hns_roce_v2_set_mac,
3958cc56 3173 .write_mtpt = hns_roce_v2_write_mtpt,
a2c80b7b 3174 .rereg_write_mtpt = hns_roce_v2_rereg_write_mtpt,
93aa2187 3175 .write_cqc = hns_roce_v2_write_cqc,
a81fba28
WHX		 3176 .set_hem = hns_roce_v2_set_hem,
3177 .clear_hem = hns_roce_v2_clear_hem,
926a01dc
WHX		 3178 .modify_qp = hns_roce_v2_modify_qp,
3179 .query_qp = hns_roce_v2_query_qp,
3180 .destroy_qp = hns_roce_v2_destroy_qp,
b156269d 3181 .modify_cq = hns_roce_v2_modify_cq,
2d407888
WHX		 3182 .post_send = hns_roce_v2_post_send,
3183 .post_recv = hns_roce_v2_post_recv,
93aa2187
WHX		 3184 .req_notify_cq = hns_roce_v2_req_notify_cq,
3185 .poll_cq = hns_roce_v2_poll_cq,
a04ff739 3186};
dd74282d
WHX		 3187
3188static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = {
3189 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
3190 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
3191 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
3192 /* required last entry */
3193 {0, }
3194};
3195
3196static int hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev,
3197 struct hnae3_handle *handle)
3198{
3199 const struct pci_device_id *id;
3200
3201 id = pci_match_id(hns_roce_hw_v2_pci_tbl, hr_dev->pci_dev);
3202 if (!id) {
3203 dev_err(hr_dev->dev, "device is not compatible!\n");
3204 return -ENXIO;
3205 }
3206
3207 hr_dev->hw = &hns_roce_hw_v2;
2d407888
WHX		 3208 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
3209 hr_dev->odb_offset = hr_dev->sdb_offset;
dd74282d
WHX		 3210
3211 /* Get info from NIC driver. */
3212 hr_dev->reg_base = handle->rinfo.roce_io_base;
3213 hr_dev->caps.num_ports = 1;
3214 hr_dev->iboe.netdevs[0] = handle->rinfo.netdev;
3215 hr_dev->iboe.phy_port[0] = 0;
3216
3217 /* cmd issue mode: 0 is poll, 1 is event */
3218 hr_dev->cmd_mod = 0;
3219 hr_dev->loop_idc = 0;
3220
3221 return 0;
3222}
3223
3224static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle)
3225{
3226 struct hns_roce_dev *hr_dev;
3227 int ret;
3228
3229 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
3230 if (!hr_dev)
3231 return -ENOMEM;
3232
a04ff739
WHX		 3233 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v2_priv), GFP_KERNEL);
3234 if (!hr_dev->priv) {
3235 ret = -ENOMEM;
3236 goto error_failed_kzalloc;
3237 }
3238
dd74282d
WHX		 3239 hr_dev->pci_dev = handle->pdev;
3240 hr_dev->dev = &handle->pdev->dev;
3241 handle->priv = hr_dev;
3242
3243 ret = hns_roce_hw_v2_get_cfg(hr_dev, handle);
3244 if (ret) {
3245 dev_err(hr_dev->dev, "Get Configuration failed!\n");
3246 goto error_failed_get_cfg;
3247 }
3248
3249 ret = hns_roce_init(hr_dev);
3250 if (ret) {
3251 dev_err(hr_dev->dev, "RoCE Engine init failed!\n");
3252 goto error_failed_get_cfg;
3253 }
3254
3255 return 0;
3256
3257error_failed_get_cfg:
a04ff739
WHX		 3258 kfree(hr_dev->priv);
3259
3260error_failed_kzalloc:
dd74282d
WHX		 3261 ib_dealloc_device(&hr_dev->ib_dev);
3262
3263 return ret;
3264}
3265
3266static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle,
3267 bool reset)
3268{
3269 struct hns_roce_dev *hr_dev = (struct hns_roce_dev *)handle->priv;
3270
3271 hns_roce_exit(hr_dev);
a04ff739 3272 kfree(hr_dev->priv);
dd74282d
WHX		 3273 ib_dealloc_device(&hr_dev->ib_dev);
3274}
3275
3276static const struct hnae3_client_ops hns_roce_hw_v2_ops = {
3277 .init_instance = hns_roce_hw_v2_init_instance,
3278 .uninit_instance = hns_roce_hw_v2_uninit_instance,
3279};
3280
3281static struct hnae3_client hns_roce_hw_v2_client = {
3282 .name = "hns_roce_hw_v2",
3283 .type = HNAE3_CLIENT_ROCE,
3284 .ops = &hns_roce_hw_v2_ops,
3285};
3286
3287static int __init hns_roce_hw_v2_init(void)
3288{
3289 return hnae3_register_client(&hns_roce_hw_v2_client);
3290}
3291
3292static void __exit hns_roce_hw_v2_exit(void)
3293{
3294 hnae3_unregister_client(&hns_roce_hw_v2_client);
3295}
3296
3297module_init(hns_roce_hw_v2_init);
3298module_exit(hns_roce_hw_v2_exit);
3299
3300MODULE_LICENSE("Dual BSD/GPL");
3301MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
3302MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
3303MODULE_AUTHOR("Shaobo Xu <xushaobo2@huawei.com>");
3304MODULE_DESCRIPTION("Hisilicon Hip08 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)