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RDMA/hns: Add profile support for hip08 driver
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v1.c
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9a443537 1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/platform_device.h>
528f1deb 34#include <linux/acpi.h>
543bfe6c 35#include <linux/etherdevice.h>
cd6ce4a5 36#include <linux/of.h>
08805fdb 37#include <linux/of_platform.h>
9a443537 38#include <rdma/ib_umem.h>
39#include "hns_roce_common.h"
40#include "hns_roce_device.h"
41#include "hns_roce_cmd.h"
42#include "hns_roce_hem.h"
43#include "hns_roce_hw_v1.h"
44
45static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
46{
47 dseg->lkey = cpu_to_le32(sg->lkey);
48 dseg->addr = cpu_to_le64(sg->addr);
49 dseg->len = cpu_to_le32(sg->length);
50}
51
52static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
53 u32 rkey)
54{
55 rseg->raddr = cpu_to_le64(remote_addr);
56 rseg->rkey = cpu_to_le32(rkey);
57 rseg->len = 0;
58}
59
60int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
61 struct ib_send_wr **bad_wr)
62{
63 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
64 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
65 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
66 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
67 struct hns_roce_wqe_data_seg *dseg = NULL;
68 struct hns_roce_qp *qp = to_hr_qp(ibqp);
69 struct device *dev = &hr_dev->pdev->dev;
70 struct hns_roce_sq_db sq_db;
71 int ps_opcode = 0, i = 0;
72 unsigned long flags = 0;
73 void *wqe = NULL;
74 u32 doorbell[2];
75 int nreq = 0;
76 u32 ind = 0;
77 int ret = 0;
543bfe6c
LO		 78 u8 *smac;
79 int loopback;
9a443537 80
07182fa7
LO		 81 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
82 ibqp->qp_type != IB_QPT_RC)) {
83 dev_err(dev, "un-supported QP type\n");
84 *bad_wr = NULL;
85 return -EOPNOTSUPP;
86 }
9a443537 87
07182fa7 88 spin_lock_irqsave(&qp->sq.lock, flags);
9a443537 89 ind = qp->sq_next_wqe;
90 for (nreq = 0; wr; ++nreq, wr = wr->next) {
91 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
92 ret = -ENOMEM;
93 *bad_wr = wr;
94 goto out;
95 }
96
97 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
98 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
99 wr->num_sge, qp->sq.max_gs);
100 ret = -EINVAL;
101 *bad_wr = wr;
102 goto out;
103 }
104
105 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
106 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
107 wr->wr_id;
108
109 /* Corresponding to the RC and RD type wqe process separately */
110 if (ibqp->qp_type == IB_QPT_GSI) {
111 ud_sq_wqe = wqe;
112 roce_set_field(ud_sq_wqe->dmac_h,
113 UD_SEND_WQE_U32_4_DMAC_0_M,
114 UD_SEND_WQE_U32_4_DMAC_0_S,
115 ah->av.mac[0]);
116 roce_set_field(ud_sq_wqe->dmac_h,
117 UD_SEND_WQE_U32_4_DMAC_1_M,
118 UD_SEND_WQE_U32_4_DMAC_1_S,
119 ah->av.mac[1]);
120 roce_set_field(ud_sq_wqe->dmac_h,
121 UD_SEND_WQE_U32_4_DMAC_2_M,
122 UD_SEND_WQE_U32_4_DMAC_2_S,
123 ah->av.mac[2]);
124 roce_set_field(ud_sq_wqe->dmac_h,
125 UD_SEND_WQE_U32_4_DMAC_3_M,
126 UD_SEND_WQE_U32_4_DMAC_3_S,
127 ah->av.mac[3]);
128
129 roce_set_field(ud_sq_wqe->u32_8,
130 UD_SEND_WQE_U32_8_DMAC_4_M,
131 UD_SEND_WQE_U32_8_DMAC_4_S,
132 ah->av.mac[4]);
133 roce_set_field(ud_sq_wqe->u32_8,
134 UD_SEND_WQE_U32_8_DMAC_5_M,
135 UD_SEND_WQE_U32_8_DMAC_5_S,
136 ah->av.mac[5]);
543bfe6c
LO		 137
138 smac = (u8 *)hr_dev->dev_addr[qp->port];
139 loopback = ether_addr_equal_unaligned(ah->av.mac,
140 smac) ? 1 : 0;
141 roce_set_bit(ud_sq_wqe->u32_8,
142 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
143 loopback);
144
9a443537 145 roce_set_field(ud_sq_wqe->u32_8,
146 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
147 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
148 HNS_ROCE_WQE_OPCODE_SEND);
149 roce_set_field(ud_sq_wqe->u32_8,
150 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
151 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
152 2);
153 roce_set_bit(ud_sq_wqe->u32_8,
154 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
155 1);
156
157 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
158 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
159 (wr->send_flags & IB_SEND_SOLICITED ?
160 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
161 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
162 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
163
164 roce_set_field(ud_sq_wqe->u32_16,
165 UD_SEND_WQE_U32_16_DEST_QP_M,
166 UD_SEND_WQE_U32_16_DEST_QP_S,
167 ud_wr(wr)->remote_qpn);
168 roce_set_field(ud_sq_wqe->u32_16,
169 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
170 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
171 ah->av.stat_rate);
172
173 roce_set_field(ud_sq_wqe->u32_36,
174 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
175 UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0);
176 roce_set_field(ud_sq_wqe->u32_36,
177 UD_SEND_WQE_U32_36_PRIORITY_M,
178 UD_SEND_WQE_U32_36_PRIORITY_S,
179 ah->av.sl_tclass_flowlabel >>
180 HNS_ROCE_SL_SHIFT);
181 roce_set_field(ud_sq_wqe->u32_36,
182 UD_SEND_WQE_U32_36_SGID_INDEX_M,
183 UD_SEND_WQE_U32_36_SGID_INDEX_S,
7716809e 184 hns_get_gid_index(hr_dev, qp->phy_port,
9a443537 185 ah->av.gid_index));
186
187 roce_set_field(ud_sq_wqe->u32_40,
188 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
189 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
190 ah->av.hop_limit);
191 roce_set_field(ud_sq_wqe->u32_40,
192 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
193 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S, 0);
194
195 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
196
197 ud_sq_wqe->va0_l = (u32)wr->sg_list[0].addr;
198 ud_sq_wqe->va0_h = (wr->sg_list[0].addr) >> 32;
199 ud_sq_wqe->l_key0 = wr->sg_list[0].lkey;
200
201 ud_sq_wqe->va1_l = (u32)wr->sg_list[1].addr;
202 ud_sq_wqe->va1_h = (wr->sg_list[1].addr) >> 32;
203 ud_sq_wqe->l_key1 = wr->sg_list[1].lkey;
204 ind++;
205 } else if (ibqp->qp_type == IB_QPT_RC) {
206 ctrl = wqe;
207 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
208 for (i = 0; i < wr->num_sge; i++)
209 ctrl->msg_length += wr->sg_list[i].length;
210
211 ctrl->sgl_pa_h = 0;
212 ctrl->flag = 0;
213 ctrl->imm_data = send_ieth(wr);
214
215 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
216 /* SO wait for conforming application scenarios */
217 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
218 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
219 (wr->send_flags & IB_SEND_SOLICITED ?
220 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
221 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
222 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
223 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
224 (wr->send_flags & IB_SEND_FENCE ?
225 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
226
c24bf895 227 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
9a443537 228
229 switch (wr->opcode) {
230 case IB_WR_RDMA_READ:
231 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
9de61d3f 232 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
233 rdma_wr(wr)->rkey);
9a443537 234 break;
235 case IB_WR_RDMA_WRITE:
236 case IB_WR_RDMA_WRITE_WITH_IMM:
237 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
9de61d3f 238 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
239 rdma_wr(wr)->rkey);
9a443537 240 break;
241 case IB_WR_SEND:
242 case IB_WR_SEND_WITH_INV:
243 case IB_WR_SEND_WITH_IMM:
244 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
245 break;
246 case IB_WR_LOCAL_INV:
247 break;
248 case IB_WR_ATOMIC_CMP_AND_SWP:
249 case IB_WR_ATOMIC_FETCH_AND_ADD:
250 case IB_WR_LSO:
251 default:
252 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
253 break;
254 }
255 ctrl->flag |= cpu_to_le32(ps_opcode);
c24bf895 256 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
9a443537 257
258 dseg = wqe;
259 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
260 if (ctrl->msg_length >
261 hr_dev->caps.max_sq_inline) {
262 ret = -EINVAL;
263 *bad_wr = wr;
264 dev_err(dev, "inline len(1-%d)=%d, illegal",
265 ctrl->msg_length,
266 hr_dev->caps.max_sq_inline);
267 goto out;
268 }
269 for (i = 0; i < wr->num_sge; i++) {
270 memcpy(wqe, ((void *) (uintptr_t)
271 wr->sg_list[i].addr),
272 wr->sg_list[i].length);
c24bf895 273 wqe += wr->sg_list[i].length;
9a443537 274 }
275 ctrl->flag |= HNS_ROCE_WQE_INLINE;
276 } else {
277 /*sqe num is two */
278 for (i = 0; i < wr->num_sge; i++)
279 set_data_seg(dseg + i, wr->sg_list + i);
280
281 ctrl->flag |= cpu_to_le32(wr->num_sge <<
282 HNS_ROCE_WQE_SGE_NUM_BIT);
283 }
284 ind++;
9a443537 285 }
286 }
287
288out:
289 /* Set DB return */
290 if (likely(nreq)) {
291 qp->sq.head += nreq;
292 /* Memory barrier */
293 wmb();
294
295 sq_db.u32_4 = 0;
296 sq_db.u32_8 = 0;
297 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
298 SQ_DOORBELL_U32_4_SQ_HEAD_S,
299 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
bfcc681b
SX		 300 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
301 SQ_DOORBELL_U32_4_SL_S, qp->sl);
9a443537 302 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
7716809e 303 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
9a443537 304 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
305 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
306 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
307
308 doorbell[0] = sq_db.u32_4;
309 doorbell[1] = sq_db.u32_8;
310
311 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
312 qp->sq_next_wqe = ind;
313 }
314
315 spin_unlock_irqrestore(&qp->sq.lock, flags);
316
317 return ret;
318}
319
320int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
321 struct ib_recv_wr **bad_wr)
322{
323 int ret = 0;
324 int nreq = 0;
325 int ind = 0;
326 int i = 0;
327 u32 reg_val = 0;
328 unsigned long flags = 0;
329 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
330 struct hns_roce_wqe_data_seg *scat = NULL;
331 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
332 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
333 struct device *dev = &hr_dev->pdev->dev;
334 struct hns_roce_rq_db rq_db;
335 uint32_t doorbell[2] = {0};
336
337 spin_lock_irqsave(&hr_qp->rq.lock, flags);
338 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
339
340 for (nreq = 0; wr; ++nreq, wr = wr->next) {
341 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
342 hr_qp->ibqp.recv_cq)) {
343 ret = -ENOMEM;
344 *bad_wr = wr;
345 goto out;
346 }
347
348 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
349 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
350 wr->num_sge, hr_qp->rq.max_gs);
351 ret = -EINVAL;
352 *bad_wr = wr;
353 goto out;
354 }
355
356 ctrl = get_recv_wqe(hr_qp, ind);
357
358 roce_set_field(ctrl->rwqe_byte_12,
359 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
360 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
361 wr->num_sge);
362
363 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
364
365 for (i = 0; i < wr->num_sge; i++)
366 set_data_seg(scat + i, wr->sg_list + i);
367
368 hr_qp->rq.wrid[ind] = wr->wr_id;
369
370 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
371 }
372
373out:
374 if (likely(nreq)) {
375 hr_qp->rq.head += nreq;
376 /* Memory barrier */
377 wmb();
378
379 if (ibqp->qp_type == IB_QPT_GSI) {
380 /* SW update GSI rq header */
381 reg_val = roce_read(to_hr_dev(ibqp->device),
382 ROCEE_QP1C_CFG3_0_REG +
7716809e 383 QP1C_CFGN_OFFSET * hr_qp->phy_port);
9a443537 384 roce_set_field(reg_val,
385 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
386 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
387 hr_qp->rq.head);
388 roce_write(to_hr_dev(ibqp->device),
389 ROCEE_QP1C_CFG3_0_REG +
7716809e 390 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
9a443537 391 } else {
392 rq_db.u32_4 = 0;
393 rq_db.u32_8 = 0;
394
395 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
396 RQ_DOORBELL_U32_4_RQ_HEAD_S,
397 hr_qp->rq.head);
398 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
399 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
400 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
401 RQ_DOORBELL_U32_8_CMD_S, 1);
402 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
403 1);
404
405 doorbell[0] = rq_db.u32_4;
406 doorbell[1] = rq_db.u32_8;
407
408 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
409 }
410 }
411 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
412
413 return ret;
414}
415
416static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
417 int sdb_mode, int odb_mode)
418{
419 u32 val;
420
421 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
422 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
423 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
424 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
425}
426
427static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
428 u32 odb_mode)
429{
430 u32 val;
431
432 /* Configure SDB/ODB extend mode */
433 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
434 roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
435 roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
436 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
437}
438
439static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
440 u32 sdb_alful)
441{
442 u32 val;
443
444 /* Configure SDB */
445 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
446 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
447 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
448 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
449 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
450 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
451}
452
453static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
454 u32 odb_alful)
455{
456 u32 val;
457
458 /* Configure ODB */
459 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
460 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
461 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
462 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
463 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
464 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
465}
466
467static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
468 u32 ext_sdb_alful)
469{
470 struct device *dev = &hr_dev->pdev->dev;
471 struct hns_roce_v1_priv *priv;
472 struct hns_roce_db_table *db;
473 dma_addr_t sdb_dma_addr;
474 u32 val;
475
016a0059 476 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 477 db = &priv->db_table;
478
479 /* Configure extend SDB threshold */
480 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
481 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
482
483 /* Configure extend SDB base addr */
484 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
485 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
486
487 /* Configure extend SDB depth */
488 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
489 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
490 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
491 db->ext_db->esdb_dep);
492 /*
493 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
494 * using 4K page, and shift more 32 because of
495 * caculating the high 32 bit value evaluated to hardware.
496 */
497 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
498 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
499 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
500
501 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
502 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
503 ext_sdb_alept, ext_sdb_alful);
504}
505
506static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
507 u32 ext_odb_alful)
508{
509 struct device *dev = &hr_dev->pdev->dev;
510 struct hns_roce_v1_priv *priv;
511 struct hns_roce_db_table *db;
512 dma_addr_t odb_dma_addr;
513 u32 val;
514
016a0059 515 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 516 db = &priv->db_table;
517
518 /* Configure extend ODB threshold */
519 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
520 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
521
522 /* Configure extend ODB base addr */
523 odb_dma_addr = db->ext_db->odb_buf_list->map;
524 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
525
526 /* Configure extend ODB depth */
527 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
528 roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
529 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
530 db->ext_db->eodb_dep);
531 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
532 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
533 db->ext_db->eodb_dep);
534 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
535
536 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
537 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
538 ext_odb_alept, ext_odb_alful);
539}
540
541static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
542 u32 odb_ext_mod)
543{
544 struct device *dev = &hr_dev->pdev->dev;
545 struct hns_roce_v1_priv *priv;
546 struct hns_roce_db_table *db;
547 dma_addr_t sdb_dma_addr;
548 dma_addr_t odb_dma_addr;
549 int ret = 0;
550
016a0059 551 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 552 db = &priv->db_table;
553
554 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
555 if (!db->ext_db)
556 return -ENOMEM;
557
558 if (sdb_ext_mod) {
559 db->ext_db->sdb_buf_list = kmalloc(
560 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
561 if (!db->ext_db->sdb_buf_list) {
562 ret = -ENOMEM;
563 goto ext_sdb_buf_fail_out;
564 }
565
566 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
567 HNS_ROCE_V1_EXT_SDB_SIZE,
568 &sdb_dma_addr, GFP_KERNEL);
569 if (!db->ext_db->sdb_buf_list->buf) {
570 ret = -ENOMEM;
571 goto alloc_sq_db_buf_fail;
572 }
573 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
574
575 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
576 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
577 HNS_ROCE_V1_EXT_SDB_ALFUL);
578 } else
579 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
580 HNS_ROCE_V1_SDB_ALFUL);
581
582 if (odb_ext_mod) {
583 db->ext_db->odb_buf_list = kmalloc(
584 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
585 if (!db->ext_db->odb_buf_list) {
586 ret = -ENOMEM;
587 goto ext_odb_buf_fail_out;
588 }
589
590 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
591 HNS_ROCE_V1_EXT_ODB_SIZE,
592 &odb_dma_addr, GFP_KERNEL);
593 if (!db->ext_db->odb_buf_list->buf) {
594 ret = -ENOMEM;
595 goto alloc_otr_db_buf_fail;
596 }
597 db->ext_db->odb_buf_list->map = odb_dma_addr;
598
599 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
600 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
601 HNS_ROCE_V1_EXT_ODB_ALFUL);
602 } else
603 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
604 HNS_ROCE_V1_ODB_ALFUL);
605
606 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
607
608 return 0;
609
610alloc_otr_db_buf_fail:
611 kfree(db->ext_db->odb_buf_list);
612
613ext_odb_buf_fail_out:
614 if (sdb_ext_mod) {
615 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
616 db->ext_db->sdb_buf_list->buf,
617 db->ext_db->sdb_buf_list->map);
618 }
619
620alloc_sq_db_buf_fail:
621 if (sdb_ext_mod)
622 kfree(db->ext_db->sdb_buf_list);
623
624ext_sdb_buf_fail_out:
625 kfree(db->ext_db);
626 return ret;
627}
628
bfcc681b
SX		 629static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
630 struct ib_pd *pd)
631{
632 struct device *dev = &hr_dev->pdev->dev;
633 struct ib_qp_init_attr init_attr;
634 struct ib_qp *qp;
635
636 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
637 init_attr.qp_type = IB_QPT_RC;
638 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
639 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
640 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
641
642 qp = hns_roce_create_qp(pd, &init_attr, NULL);
643 if (IS_ERR(qp)) {
644 dev_err(dev, "Create loop qp for mr free failed!");
645 return NULL;
646 }
647
648 return to_hr_qp(qp);
649}
650
651static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
652{
653 struct hns_roce_caps *caps = &hr_dev->caps;
654 struct device *dev = &hr_dev->pdev->dev;
655 struct ib_cq_init_attr cq_init_attr;
656 struct hns_roce_free_mr *free_mr;
657 struct ib_qp_attr attr = { 0 };
658 struct hns_roce_v1_priv *priv;
659 struct hns_roce_qp *hr_qp;
660 struct ib_cq *cq;
661 struct ib_pd *pd;
d8966fcd 662 union ib_gid dgid;
bfcc681b
SX		 663 u64 subnet_prefix;
664 int attr_mask = 0;
5802883d 665 int i, j;
bfcc681b 666 int ret;
5802883d 667 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
bfcc681b 668 u8 phy_port;
5802883d 669 u8 port = 0;
bfcc681b
SX		 670 u8 sl;
671
016a0059 672 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 673 free_mr = &priv->free_mr;
674
675 /* Reserved cq for loop qp */
676 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
677 cq_init_attr.comp_vector = 0;
678 cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
679 if (IS_ERR(cq)) {
680 dev_err(dev, "Create cq for reseved loop qp failed!");
681 return -ENOMEM;
682 }
683 free_mr->mr_free_cq = to_hr_cq(cq);
684 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
685 free_mr->mr_free_cq->ib_cq.uobject = NULL;
686 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
687 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
688 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
689 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
690
691 pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
692 if (IS_ERR(pd)) {
693 dev_err(dev, "Create pd for reseved loop qp failed!");
694 ret = -ENOMEM;
695 goto alloc_pd_failed;
696 }
697 free_mr->mr_free_pd = to_hr_pd(pd);
698 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
699 free_mr->mr_free_pd->ibpd.uobject = NULL;
700 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
701
702 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
703 attr.pkey_index = 0;
704 attr.min_rnr_timer = 0;
705 /* Disable read ability */
706 attr.max_dest_rd_atomic = 0;
707 attr.max_rd_atomic = 0;
708 /* Use arbitrary values as rq_psn and sq_psn */
709 attr.rq_psn = 0x0808;
710 attr.sq_psn = 0x0808;
711 attr.retry_cnt = 7;
712 attr.rnr_retry = 7;
713 attr.timeout = 0x12;
714 attr.path_mtu = IB_MTU_256;
5802883d 715 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
d8966fcd
DC		 716 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
717 rdma_ah_set_static_rate(&attr.ah_attr, 3);
bfcc681b
SX		 718
719 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
720 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
5802883d 721 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
722 (i % HNS_ROCE_MAX_PORTS);
723 sl = i / HNS_ROCE_MAX_PORTS;
724
725 for (j = 0; j < caps->num_ports; j++) {
726 if (hr_dev->iboe.phy_port[j] == phy_port) {
727 queue_en[i] = 1;
728 port = j;
729 break;
730 }
731 }
732
733 if (!queue_en[i])
734 continue;
735
bfcc681b 736 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
5db465f2 737 if (!free_mr->mr_free_qp[i]) {
bfcc681b
SX		 738 dev_err(dev, "Create loop qp failed!\n");
739 goto create_lp_qp_failed;
740 }
741 hr_qp = free_mr->mr_free_qp[i];
742
5802883d 743 hr_qp->port = port;
bfcc681b
SX		 744 hr_qp->phy_port = phy_port;
745 hr_qp->ibqp.qp_type = IB_QPT_RC;
746 hr_qp->ibqp.device = &hr_dev->ib_dev;
747 hr_qp->ibqp.uobject = NULL;
748 atomic_set(&hr_qp->ibqp.usecnt, 0);
749 hr_qp->ibqp.pd = pd;
750 hr_qp->ibqp.recv_cq = cq;
751 hr_qp->ibqp.send_cq = cq;
752
5802883d 753 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
754 rdma_ah_set_sl(&attr.ah_attr, sl);
755 attr.port_num = port + 1;
bfcc681b
SX		 756
757 attr.dest_qp_num = hr_qp->qpn;
d8966fcd 758 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
5802883d 759 hr_dev->dev_addr[port],
bfcc681b
SX		 760 MAC_ADDR_OCTET_NUM);
761
d8966fcd 762 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
5802883d 763 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
764 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
d8966fcd
DC		 765 dgid.raw[11] = 0xff;
766 dgid.raw[12] = 0xfe;
767 dgid.raw[8] ^= 2;
768 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
bfcc681b
SX		 769
770 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
771 IB_QPS_RESET, IB_QPS_INIT);
772 if (ret) {
773 dev_err(dev, "modify qp failed(%d)!\n", ret);
774 goto create_lp_qp_failed;
775 }
776
777 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
778 IB_QPS_INIT, IB_QPS_RTR);
779 if (ret) {
780 dev_err(dev, "modify qp failed(%d)!\n", ret);
781 goto create_lp_qp_failed;
782 }
783
784 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
785 IB_QPS_RTR, IB_QPS_RTS);
786 if (ret) {
787 dev_err(dev, "modify qp failed(%d)!\n", ret);
788 goto create_lp_qp_failed;
789 }
790 }
791
792 return 0;
793
794create_lp_qp_failed:
795 for (i -= 1; i >= 0; i--) {
796 hr_qp = free_mr->mr_free_qp[i];
797 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
798 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
799 }
800
801 if (hns_roce_dealloc_pd(pd))
802 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
803
804alloc_pd_failed:
805 if (hns_roce_ib_destroy_cq(cq))
806 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
807
808 return -EINVAL;
809}
810
811static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
812{
813 struct device *dev = &hr_dev->pdev->dev;
814 struct hns_roce_free_mr *free_mr;
815 struct hns_roce_v1_priv *priv;
816 struct hns_roce_qp *hr_qp;
817 int ret;
818 int i;
819
016a0059 820 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 821 free_mr = &priv->free_mr;
822
823 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
824 hr_qp = free_mr->mr_free_qp[i];
5802883d 825 if (!hr_qp)
826 continue;
827
bfcc681b
SX		 828 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
829 if (ret)
830 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
831 i, ret);
832 }
833
834 ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
835 if (ret)
836 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
837
838 ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
839 if (ret)
840 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
841}
842
9a443537 843static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
844{
845 struct device *dev = &hr_dev->pdev->dev;
846 struct hns_roce_v1_priv *priv;
847 struct hns_roce_db_table *db;
848 u32 sdb_ext_mod;
849 u32 odb_ext_mod;
850 u32 sdb_evt_mod;
851 u32 odb_evt_mod;
852 int ret = 0;
853
016a0059 854 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 855 db = &priv->db_table;
856
857 memset(db, 0, sizeof(*db));
858
859 /* Default DB mode */
860 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
861 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
862 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
863 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
864
865 db->sdb_ext_mod = sdb_ext_mod;
866 db->odb_ext_mod = odb_ext_mod;
867
868 /* Init extend DB */
869 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
870 if (ret) {
871 dev_err(dev, "Failed in extend DB configuration.\n");
872 return ret;
873 }
874
875 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
876
877 return 0;
878}
879
bfcc681b
SX		 880void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
881{
882 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
883 struct hns_roce_dev *hr_dev;
884
885 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
886 work);
887 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
888
889 hns_roce_v1_release_lp_qp(hr_dev);
890
891 if (hns_roce_v1_rsv_lp_qp(hr_dev))
892 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
893
894 if (lp_qp_work->comp_flag)
895 complete(lp_qp_work->comp);
896
897 kfree(lp_qp_work);
898}
899
900static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
901{
902 struct device *dev = &hr_dev->pdev->dev;
903 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
904 struct hns_roce_free_mr *free_mr;
905 struct hns_roce_v1_priv *priv;
906 struct completion comp;
907 unsigned long end =
908 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
909
016a0059 910 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 911 free_mr = &priv->free_mr;
912
913 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
914 GFP_KERNEL);
915
916 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
917
918 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
919 lp_qp_work->comp = &comp;
920 lp_qp_work->comp_flag = 1;
921
922 init_completion(lp_qp_work->comp);
923
924 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
925
926 while (time_before_eq(jiffies, end)) {
927 if (try_wait_for_completion(&comp))
928 return 0;
929 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
930 }
931
932 lp_qp_work->comp_flag = 0;
933 if (try_wait_for_completion(&comp))
934 return 0;
935
936 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
937 return -ETIMEDOUT;
938}
939
940static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
941{
942 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
943 struct device *dev = &hr_dev->pdev->dev;
944 struct ib_send_wr send_wr, *bad_wr;
945 int ret;
946
947 memset(&send_wr, 0, sizeof(send_wr));
948 send_wr.next = NULL;
949 send_wr.num_sge = 0;
950 send_wr.send_flags = 0;
951 send_wr.sg_list = NULL;
952 send_wr.wr_id = (unsigned long long)&send_wr;
953 send_wr.opcode = IB_WR_RDMA_WRITE;
954
955 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
956 if (ret) {
957 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
958 return ret;
959 }
960
961 return 0;
962}
963
964static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
965{
966 struct hns_roce_mr_free_work *mr_work;
967 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
968 struct hns_roce_free_mr *free_mr;
969 struct hns_roce_cq *mr_free_cq;
970 struct hns_roce_v1_priv *priv;
971 struct hns_roce_dev *hr_dev;
972 struct hns_roce_mr *hr_mr;
973 struct hns_roce_qp *hr_qp;
974 struct device *dev;
975 unsigned long end =
976 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
977 int i;
978 int ret;
5802883d 979 int ne = 0;
bfcc681b
SX		 980
981 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
982 hr_mr = (struct hns_roce_mr *)mr_work->mr;
983 hr_dev = to_hr_dev(mr_work->ib_dev);
984 dev = &hr_dev->pdev->dev;
985
016a0059 986 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 987 free_mr = &priv->free_mr;
988 mr_free_cq = free_mr->mr_free_cq;
989
990 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
991 hr_qp = free_mr->mr_free_qp[i];
5802883d 992 if (!hr_qp)
993 continue;
994 ne++;
995
bfcc681b
SX		 996 ret = hns_roce_v1_send_lp_wqe(hr_qp);
997 if (ret) {
998 dev_err(dev,
999 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1000 hr_qp->qpn, ret);
1001 goto free_work;
1002 }
1003 }
1004
bfcc681b
SX		 1005 do {
1006 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1007 if (ret < 0) {
1008 dev_err(dev,
1009 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1010 hr_qp->qpn, ret, hr_mr->key, ne);
1011 goto free_work;
1012 }
1013 ne -= ret;
98e77d9f
LR		 1014 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1015 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
bfcc681b
SX		 1016 } while (ne && time_before_eq(jiffies, end));
1017
1018 if (ne != 0)
1019 dev_err(dev,
1020 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1021 hr_mr->key, ne);
1022
1023free_work:
1024 if (mr_work->comp_flag)
1025 complete(mr_work->comp);
1026 kfree(mr_work);
1027}
1028
1029int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
1030{
1031 struct device *dev = &hr_dev->pdev->dev;
1032 struct hns_roce_mr_free_work *mr_work;
1033 struct hns_roce_free_mr *free_mr;
1034 struct hns_roce_v1_priv *priv;
1035 struct completion comp;
1036 unsigned long end =
1037 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1038 unsigned long start = jiffies;
1039 int npages;
1040 int ret = 0;
1041
016a0059 1042 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1043 free_mr = &priv->free_mr;
1044
1045 if (mr->enabled) {
1046 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1047 & (hr_dev->caps.num_mtpts - 1)))
1048 dev_warn(dev, "HW2SW_MPT failed!\n");
1049 }
1050
1051 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1052 if (!mr_work) {
1053 ret = -ENOMEM;
1054 goto free_mr;
1055 }
1056
1057 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1058
1059 mr_work->ib_dev = &(hr_dev->ib_dev);
1060 mr_work->comp = &comp;
1061 mr_work->comp_flag = 1;
1062 mr_work->mr = (void *)mr;
1063 init_completion(mr_work->comp);
1064
1065 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1066
1067 while (time_before_eq(jiffies, end)) {
1068 if (try_wait_for_completion(&comp))
1069 goto free_mr;
1070 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1071 }
1072
1073 mr_work->comp_flag = 0;
1074 if (try_wait_for_completion(&comp))
1075 goto free_mr;
1076
1077 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1078 ret = -ETIMEDOUT;
1079
1080free_mr:
1081 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1082 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1083
1084 if (mr->size != ~0ULL) {
1085 npages = ib_umem_page_count(mr->umem);
1086 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1087 mr->pbl_dma_addr);
1088 }
1089
1090 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1091 key_to_hw_index(mr->key), 0);
1092
1093 if (mr->umem)
1094 ib_umem_release(mr->umem);
1095
1096 kfree(mr);
1097
1098 return ret;
1099}
1100
9a443537 1101static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1102{
1103 struct device *dev = &hr_dev->pdev->dev;
1104 struct hns_roce_v1_priv *priv;
1105 struct hns_roce_db_table *db;
1106
016a0059 1107 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1108 db = &priv->db_table;
1109
1110 if (db->sdb_ext_mod) {
1111 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1112 db->ext_db->sdb_buf_list->buf,
1113 db->ext_db->sdb_buf_list->map);
1114 kfree(db->ext_db->sdb_buf_list);
1115 }
1116
1117 if (db->odb_ext_mod) {
1118 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1119 db->ext_db->odb_buf_list->buf,
1120 db->ext_db->odb_buf_list->map);
1121 kfree(db->ext_db->odb_buf_list);
1122 }
1123
1124 kfree(db->ext_db);
1125}
1126
1127static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1128{
1129 int ret;
1130 int raq_shift = 0;
1131 dma_addr_t addr;
1132 u32 val;
1133 struct hns_roce_v1_priv *priv;
1134 struct hns_roce_raq_table *raq;
1135 struct device *dev = &hr_dev->pdev->dev;
1136
016a0059 1137 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1138 raq = &priv->raq_table;
1139
1140 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1141 if (!raq->e_raq_buf)
1142 return -ENOMEM;
1143
1144 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1145 &addr, GFP_KERNEL);
1146 if (!raq->e_raq_buf->buf) {
1147 ret = -ENOMEM;
1148 goto err_dma_alloc_raq;
1149 }
1150 raq->e_raq_buf->map = addr;
1151
1152 /* Configure raq extended address. 48bit 4K align*/
1153 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1154
1155 /* Configure raq_shift */
1156 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1157 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1158 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1159 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1160 /*
1161 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1162 * using 4K page, and shift more 32 because of
1163 * caculating the high 32 bit value evaluated to hardware.
1164 */
1165 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1166 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1167 raq->e_raq_buf->map >> 44);
1168 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1169 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1170
1171 /* Configure raq threshold */
1172 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1173 roce_set_field(val, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1174 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1175 HNS_ROCE_V1_EXT_RAQ_WF);
1176 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1177 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1178
1179 /* Enable extend raq */
1180 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1181 roce_set_field(val,
1182 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1183 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1184 POL_TIME_INTERVAL_VAL);
1185 roce_set_bit(val, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1186 roce_set_field(val,
1187 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1188 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1189 2);
1190 roce_set_bit(val,
1191 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1192 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1193 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1194
1195 /* Enable raq drop */
1196 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1197 roce_set_bit(val, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1198 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1199 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1200
1201 return 0;
1202
1203err_dma_alloc_raq:
1204 kfree(raq->e_raq_buf);
1205 return ret;
1206}
1207
1208static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1209{
1210 struct device *dev = &hr_dev->pdev->dev;
1211 struct hns_roce_v1_priv *priv;
1212 struct hns_roce_raq_table *raq;
1213
016a0059 1214 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1215 raq = &priv->raq_table;
1216
1217 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1218 raq->e_raq_buf->map);
1219 kfree(raq->e_raq_buf);
1220}
1221
1222static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1223{
1224 u32 val;
1225
1226 if (enable_flag) {
1227 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1228 /* Open all ports */
1229 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1230 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1231 ALL_PORT_VAL_OPEN);
1232 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1233 } else {
1234 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1235 /* Close all ports */
1236 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1237 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1238 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1239 }
1240}
1241
97f0e39f
WHX		 1242static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1243{
1244 struct device *dev = &hr_dev->pdev->dev;
1245 struct hns_roce_v1_priv *priv;
1246 int ret;
1247
016a0059 1248 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 1249
1250 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1251 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1252 GFP_KERNEL);
1253 if (!priv->bt_table.qpc_buf.buf)
1254 return -ENOMEM;
1255
1256 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1257 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1258 GFP_KERNEL);
1259 if (!priv->bt_table.mtpt_buf.buf) {
1260 ret = -ENOMEM;
1261 goto err_failed_alloc_mtpt_buf;
1262 }
1263
1264 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1265 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1266 GFP_KERNEL);
1267 if (!priv->bt_table.cqc_buf.buf) {
1268 ret = -ENOMEM;
1269 goto err_failed_alloc_cqc_buf;
1270 }
1271
1272 return 0;
1273
1274err_failed_alloc_cqc_buf:
1275 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1276 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1277
1278err_failed_alloc_mtpt_buf:
1279 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1280 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1281
1282 return ret;
1283}
1284
1285static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1286{
1287 struct device *dev = &hr_dev->pdev->dev;
1288 struct hns_roce_v1_priv *priv;
1289
016a0059 1290 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 1291
1292 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1293 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1294
1295 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1296 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1297
1298 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1299 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1300}
1301
8f3e9f3e
WHX		 1302static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1303{
1304 struct device *dev = &hr_dev->pdev->dev;
1305 struct hns_roce_buf_list *tptr_buf;
1306 struct hns_roce_v1_priv *priv;
1307
016a0059 1308 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e
WHX		 1309 tptr_buf = &priv->tptr_table.tptr_buf;
1310
1311 /*
1312 * This buffer will be used for CQ's tptr(tail pointer), also
1313 * named ci(customer index). Every CQ will use 2 bytes to save
1314 * cqe ci in hip06. Hardware will read this area to get new ci
1315 * when the queue is almost full.
1316 */
1317 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1318 &tptr_buf->map, GFP_KERNEL);
1319 if (!tptr_buf->buf)
1320 return -ENOMEM;
1321
1322 hr_dev->tptr_dma_addr = tptr_buf->map;
1323 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1324
1325 return 0;
1326}
1327
1328static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1329{
1330 struct device *dev = &hr_dev->pdev->dev;
1331 struct hns_roce_buf_list *tptr_buf;
1332 struct hns_roce_v1_priv *priv;
1333
016a0059 1334 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e
WHX		 1335 tptr_buf = &priv->tptr_table.tptr_buf;
1336
1337 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1338 tptr_buf->buf, tptr_buf->map);
1339}
1340
bfcc681b
SX		 1341static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1342{
1343 struct device *dev = &hr_dev->pdev->dev;
1344 struct hns_roce_free_mr *free_mr;
1345 struct hns_roce_v1_priv *priv;
1346 int ret = 0;
1347
016a0059 1348 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1349 free_mr = &priv->free_mr;
1350
1351 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1352 if (!free_mr->free_mr_wq) {
1353 dev_err(dev, "Create free mr workqueue failed!\n");
1354 return -ENOMEM;
1355 }
1356
1357 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1358 if (ret) {
1359 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1360 flush_workqueue(free_mr->free_mr_wq);
1361 destroy_workqueue(free_mr->free_mr_wq);
1362 }
1363
1364 return ret;
1365}
1366
1367static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1368{
1369 struct hns_roce_free_mr *free_mr;
1370 struct hns_roce_v1_priv *priv;
1371
016a0059 1372 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1373 free_mr = &priv->free_mr;
1374
1375 flush_workqueue(free_mr->free_mr_wq);
1376 destroy_workqueue(free_mr->free_mr_wq);
1377
1378 hns_roce_v1_release_lp_qp(hr_dev);
1379}
1380
9a443537 1381/**
1382 * hns_roce_v1_reset - reset RoCE
1383 * @hr_dev: RoCE device struct pointer
1384 * @enable: true -- drop reset, false -- reset
1385 * return 0 - success , negative --fail
1386 */
528f1deb 1387int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
9a443537 1388{
1389 struct device_node *dsaf_node;
1390 struct device *dev = &hr_dev->pdev->dev;
1391 struct device_node *np = dev->of_node;
528f1deb 1392 struct fwnode_handle *fwnode;
9a443537 1393 int ret;
1394
528f1deb
S		 1395 /* check if this is DT/ACPI case */
1396 if (dev_of_node(dev)) {
1397 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1398 if (!dsaf_node) {
1399 dev_err(dev, "could not find dsaf-handle\n");
1400 return -EINVAL;
1401 }
1402 fwnode = &dsaf_node->fwnode;
1403 } else if (is_acpi_device_node(dev->fwnode)) {
1404 struct acpi_reference_args args;
1405
1406 ret = acpi_node_get_property_reference(dev->fwnode,
1407 "dsaf-handle", 0, &args);
1408 if (ret) {
1409 dev_err(dev, "could not find dsaf-handle\n");
1410 return ret;
1411 }
1412 fwnode = acpi_fwnode_handle(args.adev);
1413 } else {
1414 dev_err(dev, "cannot read data from DT or ACPI\n");
1415 return -ENXIO;
9a443537 1416 }
1417
528f1deb 1418 ret = hns_dsaf_roce_reset(fwnode, false);
9a443537 1419 if (ret)
1420 return ret;
1421
528f1deb 1422 if (dereset) {
9a443537 1423 msleep(SLEEP_TIME_INTERVAL);
528f1deb 1424 ret = hns_dsaf_roce_reset(fwnode, true);
9a443537 1425 }
1426
528f1deb 1427 return ret;
9a443537 1428}
1429
d838c481
WHX		 1430static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1431{
1432 struct device *dev = &hr_dev->pdev->dev;
1433 struct hns_roce_v1_priv *priv;
1434 struct hns_roce_des_qp *des_qp;
1435
016a0059 1436 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 1437 des_qp = &priv->des_qp;
1438
1439 des_qp->requeue_flag = 1;
1440 des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1441 if (!des_qp->qp_wq) {
1442 dev_err(dev, "Create destroy qp workqueue failed!\n");
1443 return -ENOMEM;
1444 }
1445
1446 return 0;
1447}
1448
1449static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1450{
1451 struct hns_roce_v1_priv *priv;
1452 struct hns_roce_des_qp *des_qp;
1453
016a0059 1454 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 1455 des_qp = &priv->des_qp;
1456
1457 des_qp->requeue_flag = 0;
1458 flush_workqueue(des_qp->qp_wq);
1459 destroy_workqueue(des_qp->qp_wq);
1460}
1461
cfc85f3e 1462int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
9a443537 1463{
1464 int i = 0;
1465 struct hns_roce_caps *caps = &hr_dev->caps;
1466
1467 hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG));
1468 hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev,
1469 ROCEE_VENDOR_PART_ID_REG));
9a443537 1470 hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev,
1471 ROCEE_SYS_IMAGE_GUID_L_REG)) |
1472 ((u64)le32_to_cpu(roce_read(hr_dev,
1473 ROCEE_SYS_IMAGE_GUID_H_REG)) << 32);
8f3e9f3e 1474 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
9a443537 1475
1476 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1477 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1478 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1479 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1480 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1481 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1482 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1483 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1484 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1485 caps->num_aeq_vectors = HNS_ROCE_AEQE_VEC_NUM;
1486 caps->num_comp_vectors = HNS_ROCE_COMP_VEC_NUM;
1487 caps->num_other_vectors = HNS_ROCE_AEQE_OF_VEC_NUM;
1488 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1489 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1490 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1491 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1492 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1493 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1494 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1495 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1496 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1497 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1498 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1499 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1500 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1501 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
9a443537 1502 caps->reserved_lkey = 0;
1503 caps->reserved_pds = 0;
1504 caps->reserved_mrws = 1;
1505 caps->reserved_uars = 0;
1506 caps->reserved_cqs = 0;
1507
1508 for (i = 0; i < caps->num_ports; i++)
1509 caps->pkey_table_len[i] = 1;
1510
1511 for (i = 0; i < caps->num_ports; i++) {
1512 /* Six ports shared 16 GID in v1 engine */
1513 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1514 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1515 caps->num_ports;
1516 else
1517 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1518 caps->num_ports + 1;
1519 }
1520
1521 for (i = 0; i < caps->num_comp_vectors; i++)
1522 caps->ceqe_depth[i] = HNS_ROCE_V1_NUM_COMP_EQE;
1523
1524 caps->aeqe_depth = HNS_ROCE_V1_NUM_ASYNC_EQE;
1525 caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev,
1526 ROCEE_ACK_DELAY_REG));
1527 caps->max_mtu = IB_MTU_2048;
cfc85f3e
WHX		 1528
1529 return 0;
9a443537 1530}
1531
1532int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1533{
1534 int ret;
1535 u32 val;
1536 struct device *dev = &hr_dev->pdev->dev;
1537
1538 /* DMAE user config */
1539 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1540 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1541 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1542 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1543 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1544 1 << PAGES_SHIFT_16);
1545 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1546
1547 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1548 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1549 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1550 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1551 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1552 1 << PAGES_SHIFT_16);
1553
1554 ret = hns_roce_db_init(hr_dev);
1555 if (ret) {
1556 dev_err(dev, "doorbell init failed!\n");
1557 return ret;
1558 }
1559
1560 ret = hns_roce_raq_init(hr_dev);
1561 if (ret) {
1562 dev_err(dev, "raq init failed!\n");
1563 goto error_failed_raq_init;
1564 }
1565
97f0e39f
WHX		 1566 ret = hns_roce_bt_init(hr_dev);
1567 if (ret) {
1568 dev_err(dev, "bt init failed!\n");
1569 goto error_failed_bt_init;
1570 }
1571
8f3e9f3e
WHX		 1572 ret = hns_roce_tptr_init(hr_dev);
1573 if (ret) {
1574 dev_err(dev, "tptr init failed!\n");
1575 goto error_failed_tptr_init;
1576 }
1577
d838c481
WHX		 1578 ret = hns_roce_des_qp_init(hr_dev);
1579 if (ret) {
1580 dev_err(dev, "des qp init failed!\n");
1581 goto error_failed_des_qp_init;
1582 }
1583
bfcc681b
SX		 1584 ret = hns_roce_free_mr_init(hr_dev);
1585 if (ret) {
1586 dev_err(dev, "free mr init failed!\n");
1587 goto error_failed_free_mr_init;
1588 }
1589
d838c481
WHX		 1590 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1591
9a443537 1592 return 0;
1593
bfcc681b
SX		 1594error_failed_free_mr_init:
1595 hns_roce_des_qp_free(hr_dev);
1596
d838c481
WHX		 1597error_failed_des_qp_init:
1598 hns_roce_tptr_free(hr_dev);
1599
8f3e9f3e
WHX		 1600error_failed_tptr_init:
1601 hns_roce_bt_free(hr_dev);
1602
97f0e39f 1603error_failed_bt_init:
97f0e39f
WHX		 1604 hns_roce_raq_free(hr_dev);
1605
9a443537 1606error_failed_raq_init:
1607 hns_roce_db_free(hr_dev);
1608 return ret;
1609}
1610
1611void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1612{
d838c481 1613 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
bfcc681b 1614 hns_roce_free_mr_free(hr_dev);
d838c481 1615 hns_roce_des_qp_free(hr_dev);
8f3e9f3e 1616 hns_roce_tptr_free(hr_dev);
97f0e39f 1617 hns_roce_bt_free(hr_dev);
9a443537 1618 hns_roce_raq_free(hr_dev);
1619 hns_roce_db_free(hr_dev);
1620}
1621
1622void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
1623 union ib_gid *gid)
1624{
1625 u32 *p = NULL;
1626 u8 gid_idx = 0;
1627
1628 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1629
1630 p = (u32 *)&gid->raw[0];
1631 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1632 (HNS_ROCE_V1_GID_NUM * gid_idx));
1633
1634 p = (u32 *)&gid->raw[4];
1635 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1636 (HNS_ROCE_V1_GID_NUM * gid_idx));
1637
1638 p = (u32 *)&gid->raw[8];
1639 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1640 (HNS_ROCE_V1_GID_NUM * gid_idx));
1641
1642 p = (u32 *)&gid->raw[0xc];
1643 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1644 (HNS_ROCE_V1_GID_NUM * gid_idx));
1645}
1646
1647void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1648{
1649 u32 reg_smac_l;
1650 u16 reg_smac_h;
1651 u16 *p_h;
1652 u32 *p;
1653 u32 val;
1654
bfcc681b
SX		 1655 /*
1656 * When mac changed, loopback may fail
1657 * because of smac not equal to dmac.
1658 * We Need to release and create reserved qp again.
1659 */
1660 if (hr_dev->hw->dereg_mr && hns_roce_v1_recreate_lp_qp(hr_dev))
1661 dev_warn(&hr_dev->pdev->dev, "recreate lp qp timeout!\n");
1662
9a443537 1663 p = (u32 *)(&addr[0]);
1664 reg_smac_l = *p;
1665 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1666 PHY_PORT_OFFSET * phy_port);
1667
1668 val = roce_read(hr_dev,
1669 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1670 p_h = (u16 *)(&addr[4]);
1671 reg_smac_h = *p_h;
1672 roce_set_field(val, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1673 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1674 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1675 val);
1676}
1677
1678void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1679 enum ib_mtu mtu)
1680{
1681 u32 val;
1682
1683 val = roce_read(hr_dev,
1684 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1685 roce_set_field(val, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1686 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1687 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1688 val);
1689}
1690
1691int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1692 unsigned long mtpt_idx)
1693{
1694 struct hns_roce_v1_mpt_entry *mpt_entry;
1695 struct scatterlist *sg;
1696 u64 *pages;
1697 int entry;
1698 int i;
1699
1700 /* MPT filled into mailbox buf */
1701 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1702 memset(mpt_entry, 0, sizeof(*mpt_entry));
1703
1704 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1705 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1706 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1707 MPT_BYTE_4_KEY_S, mr->key);
1708 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1709 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1710 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1711 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1712 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1713 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1714 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1715 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1716 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1717 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1718 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1719 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1720 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1721 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1722 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1723 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1724 0);
1725 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1726
1727 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1728 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1729 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1730 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1731
1732 mpt_entry->virt_addr_l = (u32)mr->iova;
1733 mpt_entry->virt_addr_h = (u32)(mr->iova >> 32);
1734 mpt_entry->length = (u32)mr->size;
1735
1736 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1737 MPT_BYTE_28_PD_S, mr->pd);
1738 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1739 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1740 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1741 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1742
ad61dd30 1743 /* DMA memory register */
9a443537 1744 if (mr->type == MR_TYPE_DMA)
1745 return 0;
1746
1747 pages = (u64 *) __get_free_page(GFP_KERNEL);
1748 if (!pages)
1749 return -ENOMEM;
1750
1751 i = 0;
1752 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1753 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1754
1755 /* Directly record to MTPT table firstly 7 entry */
1756 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1757 break;
1758 i++;
1759 }
1760
1761 /* Register user mr */
1762 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1763 switch (i) {
1764 case 0:
1765 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1766 roce_set_field(mpt_entry->mpt_byte_36,
1767 MPT_BYTE_36_PA0_H_M,
1768 MPT_BYTE_36_PA0_H_S,
1769 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1770 break;
1771 case 1:
1772 roce_set_field(mpt_entry->mpt_byte_36,
1773 MPT_BYTE_36_PA1_L_M,
1774 MPT_BYTE_36_PA1_L_S,
1775 cpu_to_le32((u32)(pages[i])));
1776 roce_set_field(mpt_entry->mpt_byte_40,
1777 MPT_BYTE_40_PA1_H_M,
1778 MPT_BYTE_40_PA1_H_S,
1779 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1780 break;
1781 case 2:
1782 roce_set_field(mpt_entry->mpt_byte_40,
1783 MPT_BYTE_40_PA2_L_M,
1784 MPT_BYTE_40_PA2_L_S,
1785 cpu_to_le32((u32)(pages[i])));
1786 roce_set_field(mpt_entry->mpt_byte_44,
1787 MPT_BYTE_44_PA2_H_M,
1788 MPT_BYTE_44_PA2_H_S,
1789 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1790 break;
1791 case 3:
1792 roce_set_field(mpt_entry->mpt_byte_44,
1793 MPT_BYTE_44_PA3_L_M,
1794 MPT_BYTE_44_PA3_L_S,
1795 cpu_to_le32((u32)(pages[i])));
1796 roce_set_field(mpt_entry->mpt_byte_48,
1797 MPT_BYTE_48_PA3_H_M,
1798 MPT_BYTE_48_PA3_H_S,
1799 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_8)));
1800 break;
1801 case 4:
1802 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1803 roce_set_field(mpt_entry->mpt_byte_56,
1804 MPT_BYTE_56_PA4_H_M,
1805 MPT_BYTE_56_PA4_H_S,
1806 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1807 break;
1808 case 5:
1809 roce_set_field(mpt_entry->mpt_byte_56,
1810 MPT_BYTE_56_PA5_L_M,
1811 MPT_BYTE_56_PA5_L_S,
1812 cpu_to_le32((u32)(pages[i])));
1813 roce_set_field(mpt_entry->mpt_byte_60,
1814 MPT_BYTE_60_PA5_H_M,
1815 MPT_BYTE_60_PA5_H_S,
1816 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1817 break;
1818 case 6:
1819 roce_set_field(mpt_entry->mpt_byte_60,
1820 MPT_BYTE_60_PA6_L_M,
1821 MPT_BYTE_60_PA6_L_S,
1822 cpu_to_le32((u32)(pages[i])));
1823 roce_set_field(mpt_entry->mpt_byte_64,
1824 MPT_BYTE_64_PA6_H_M,
1825 MPT_BYTE_64_PA6_H_S,
1826 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1827 break;
1828 default:
1829 break;
1830 }
1831 }
1832
1833 free_page((unsigned long) pages);
1834
1835 mpt_entry->pbl_addr_l = (u32)(mr->pbl_dma_addr);
1836
1837 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1838 MPT_BYTE_12_PBL_ADDR_H_S,
1839 ((u32)(mr->pbl_dma_addr >> 32)));
1840
1841 return 0;
1842}
1843
1844static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1845{
1846 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1847 n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1848}
1849
1850static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1851{
1852 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1853
1854 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1855 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1856 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1857}
1858
1859static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1860{
1861 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1862}
1863
a4be892e 1864void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
9a443537 1865{
1866 u32 doorbell[2];
1867
1868 doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1);
5b0ff9a0 1869 doorbell[1] = 0;
9a443537 1870 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1871 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1872 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1873 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1874 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1875 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1876 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1877
1878 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1879}
1880
1881static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1882 struct hns_roce_srq *srq)
1883{
1884 struct hns_roce_cqe *cqe, *dest;
1885 u32 prod_index;
1886 int nfreed = 0;
1887 u8 owner_bit;
1888
1889 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1890 ++prod_index) {
1891 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1892 break;
1893 }
1894
1895 /*
e84e40be
S		 1896 * Now backwards through the CQ, removing CQ entries
1897 * that match our QP by overwriting them with next entries.
1898 */
9a443537 1899 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1900 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1901 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1902 CQE_BYTE_16_LOCAL_QPN_S) &
1903 HNS_ROCE_CQE_QPN_MASK) == qpn) {
1904 /* In v1 engine, not support SRQ */
1905 ++nfreed;
1906 } else if (nfreed) {
1907 dest = get_cqe(hr_cq, (prod_index + nfreed) &
1908 hr_cq->ib_cq.cqe);
1909 owner_bit = roce_get_bit(dest->cqe_byte_4,
1910 CQE_BYTE_4_OWNER_S);
1911 memcpy(dest, cqe, sizeof(*cqe));
1912 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1913 owner_bit);
1914 }
1915 }
1916
1917 if (nfreed) {
1918 hr_cq->cons_index += nfreed;
1919 /*
e84e40be
S		 1920 * Make sure update of buffer contents is done before
1921 * updating consumer index.
1922 */
9a443537 1923 wmb();
1924
a4be892e 1925 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
9a443537 1926 }
1927}
1928
1929static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1930 struct hns_roce_srq *srq)
1931{
1932 spin_lock_irq(&hr_cq->lock);
1933 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1934 spin_unlock_irq(&hr_cq->lock);
1935}
1936
1937void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1938 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
1939 dma_addr_t dma_handle, int nent, u32 vector)
1940{
1941 struct hns_roce_cq_context *cq_context = NULL;
8f3e9f3e
WHX		 1942 struct hns_roce_buf_list *tptr_buf;
1943 struct hns_roce_v1_priv *priv;
1944 dma_addr_t tptr_dma_addr;
1945 int offset;
1946
016a0059 1947 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e 1948 tptr_buf = &priv->tptr_table.tptr_buf;
9a443537 1949
1950 cq_context = mb_buf;
1951 memset(cq_context, 0, sizeof(*cq_context));
1952
8f3e9f3e
WHX		 1953 /* Get the tptr for this CQ. */
1954 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
1955 tptr_dma_addr = tptr_buf->map + offset;
1956 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
9a443537 1957
1958 /* Register cq_context members */
1959 roce_set_field(cq_context->cqc_byte_4,
1960 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
1961 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
1962 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
1963 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
1964 cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4);
1965
1966 cq_context->cq_bt_l = (u32)dma_handle;
1967 cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l);
1968
1969 roce_set_field(cq_context->cqc_byte_12,
1970 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
1971 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
1972 ((u64)dma_handle >> 32));
1973 roce_set_field(cq_context->cqc_byte_12,
1974 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
1975 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
1976 ilog2((unsigned int)nent));
1977 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
1978 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
1979 cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12);
1980
1981 cq_context->cur_cqe_ba0_l = (u32)(mtts[0]);
1982 cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l);
1983
1984 roce_set_field(cq_context->cqc_byte_20,
1985 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
1986 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S,
1987 cpu_to_le32((mtts[0]) >> 32));
1988 /* Dedicated hardware, directly set 0 */
1989 roce_set_field(cq_context->cqc_byte_20,
1990 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
1991 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
1992 /**
1993 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1994 * using 4K page, and shift more 32 because of
1995 * caculating the high 32 bit value evaluated to hardware.
1996 */
1997 roce_set_field(cq_context->cqc_byte_20,
1998 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
1999 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
8f3e9f3e 2000 tptr_dma_addr >> 44);
9a443537 2001 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
2002
8f3e9f3e 2003 cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
9a443537 2004
2005 roce_set_field(cq_context->cqc_byte_32,
2006 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2007 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2008 roce_set_bit(cq_context->cqc_byte_32,
2009 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2010 roce_set_bit(cq_context->cqc_byte_32,
2011 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2012 roce_set_bit(cq_context->cqc_byte_32,
2013 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2014 roce_set_bit(cq_context->cqc_byte_32,
2015 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2016 0);
e84e40be 2017 /* The initial value of cq's ci is 0 */
9a443537 2018 roce_set_field(cq_context->cqc_byte_32,
2019 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2020 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2021 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
2022}
2023
2024int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
2025{
2026 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2027 u32 notification_flag;
2028 u32 doorbell[2];
9a443537 2029
2030 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2031 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2032 /*
e84e40be
S		 2033 * flags = 0; Notification Flag = 1, next
2034 * flags = 1; Notification Flag = 0, solocited
2035 */
9a443537 2036 doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
2037 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2038 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2039 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2040 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2041 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2042 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2043 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2044 hr_cq->cqn | notification_flag);
2045
2046 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2047
87809f83 2048 return 0;
9a443537 2049}
2050
2051static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2052 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2053{
2054 int qpn;
2055 int is_send;
2056 u16 wqe_ctr;
2057 u32 status;
2058 u32 opcode;
2059 struct hns_roce_cqe *cqe;
2060 struct hns_roce_qp *hr_qp;
2061 struct hns_roce_wq *wq;
2062 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2063 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2064 struct device *dev = &hr_dev->pdev->dev;
2065
2066 /* Find cqe according consumer index */
2067 cqe = next_cqe_sw(hr_cq);
2068 if (!cqe)
2069 return -EAGAIN;
2070
2071 ++hr_cq->cons_index;
2072 /* Memory barrier */
2073 rmb();
2074 /* 0->SQ, 1->RQ */
2075 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2076
2077 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2078 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2079 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2080 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2081 CQE_BYTE_20_PORT_NUM_S) +
2082 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2083 CQE_BYTE_16_LOCAL_QPN_S) *
2084 HNS_ROCE_MAX_PORTS;
2085 } else {
2086 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2087 CQE_BYTE_16_LOCAL_QPN_S);
2088 }
2089
2090 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2091 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2092 if (unlikely(!hr_qp)) {
2093 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2094 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2095 return -EINVAL;
2096 }
2097
2098 *cur_qp = hr_qp;
2099 }
2100
2101 wc->qp = &(*cur_qp)->ibqp;
2102 wc->vendor_err = 0;
2103
2104 status = roce_get_field(cqe->cqe_byte_4,
2105 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2106 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2107 HNS_ROCE_CQE_STATUS_MASK;
2108 switch (status) {
2109 case HNS_ROCE_CQE_SUCCESS:
2110 wc->status = IB_WC_SUCCESS;
2111 break;
2112 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2113 wc->status = IB_WC_LOC_LEN_ERR;
2114 break;
2115 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2116 wc->status = IB_WC_LOC_QP_OP_ERR;
2117 break;
2118 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2119 wc->status = IB_WC_LOC_PROT_ERR;
2120 break;
2121 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2122 wc->status = IB_WC_WR_FLUSH_ERR;
2123 break;
2124 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2125 wc->status = IB_WC_MW_BIND_ERR;
2126 break;
2127 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2128 wc->status = IB_WC_BAD_RESP_ERR;
2129 break;
2130 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2131 wc->status = IB_WC_LOC_ACCESS_ERR;
2132 break;
2133 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2134 wc->status = IB_WC_REM_INV_REQ_ERR;
2135 break;
2136 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2137 wc->status = IB_WC_REM_ACCESS_ERR;
2138 break;
2139 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2140 wc->status = IB_WC_REM_OP_ERR;
2141 break;
2142 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2143 wc->status = IB_WC_RETRY_EXC_ERR;
2144 break;
2145 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2146 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2147 break;
2148 default:
2149 wc->status = IB_WC_GENERAL_ERR;
2150 break;
2151 }
2152
2153 /* CQE status error, directly return */
2154 if (wc->status != IB_WC_SUCCESS)
2155 return 0;
2156
2157 if (is_send) {
2158 /* SQ conrespond to CQE */
2159 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2160 CQE_BYTE_4_WQE_INDEX_M,
1bdab400
S		 2161 CQE_BYTE_4_WQE_INDEX_S)&
2162 ((*cur_qp)->sq.wqe_cnt-1));
9a443537 2163 switch (sq_wqe->flag & HNS_ROCE_WQE_OPCODE_MASK) {
2164 case HNS_ROCE_WQE_OPCODE_SEND:
2165 wc->opcode = IB_WC_SEND;
2166 break;
2167 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2168 wc->opcode = IB_WC_RDMA_READ;
2169 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2170 break;
2171 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2172 wc->opcode = IB_WC_RDMA_WRITE;
2173 break;
2174 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2175 wc->opcode = IB_WC_LOCAL_INV;
2176 break;
2177 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2178 wc->opcode = IB_WC_SEND;
2179 break;
2180 default:
2181 wc->status = IB_WC_GENERAL_ERR;
2182 break;
2183 }
2184 wc->wc_flags = (sq_wqe->flag & HNS_ROCE_WQE_IMM ?
2185 IB_WC_WITH_IMM : 0);
2186
2187 wq = &(*cur_qp)->sq;
2188 if ((*cur_qp)->sq_signal_bits) {
2189 /*
e84e40be
S		 2190 * If sg_signal_bit is 1,
2191 * firstly tail pointer updated to wqe
2192 * which current cqe correspond to
2193 */
9a443537 2194 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2195 CQE_BYTE_4_WQE_INDEX_M,
2196 CQE_BYTE_4_WQE_INDEX_S);
2197 wq->tail += (wqe_ctr - (u16)wq->tail) &
2198 (wq->wqe_cnt - 1);
2199 }
2200 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2201 ++wq->tail;
5f110ac4 2202 } else {
9a443537 2203 /* RQ conrespond to CQE */
2204 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2205 opcode = roce_get_field(cqe->cqe_byte_4,
2206 CQE_BYTE_4_OPERATION_TYPE_M,
2207 CQE_BYTE_4_OPERATION_TYPE_S) &
2208 HNS_ROCE_CQE_OPCODE_MASK;
2209 switch (opcode) {
2210 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2211 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2212 wc->wc_flags = IB_WC_WITH_IMM;
2213 wc->ex.imm_data = le32_to_cpu(cqe->immediate_data);
2214 break;
2215 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2216 if (roce_get_bit(cqe->cqe_byte_4,
2217 CQE_BYTE_4_IMM_INDICATOR_S)) {
2218 wc->opcode = IB_WC_RECV;
2219 wc->wc_flags = IB_WC_WITH_IMM;
2220 wc->ex.imm_data = le32_to_cpu(
2221 cqe->immediate_data);
2222 } else {
2223 wc->opcode = IB_WC_RECV;
2224 wc->wc_flags = 0;
2225 }
2226 break;
2227 default:
2228 wc->status = IB_WC_GENERAL_ERR;
2229 break;
2230 }
2231
2232 /* Update tail pointer, record wr_id */
2233 wq = &(*cur_qp)->rq;
2234 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2235 ++wq->tail;
2236 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2237 CQE_BYTE_20_SL_S);
2238 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2239 CQE_BYTE_20_REMOTE_QPN_M,
2240 CQE_BYTE_20_REMOTE_QPN_S);
2241 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2242 CQE_BYTE_20_GRH_PRESENT_S) ?
2243 IB_WC_GRH : 0);
2244 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2245 CQE_BYTE_28_P_KEY_IDX_M,
2246 CQE_BYTE_28_P_KEY_IDX_S);
2247 }
2248
2249 return 0;
2250}
2251
2252int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2253{
2254 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2255 struct hns_roce_qp *cur_qp = NULL;
2256 unsigned long flags;
2257 int npolled;
2258 int ret = 0;
2259
2260 spin_lock_irqsave(&hr_cq->lock, flags);
2261
2262 for (npolled = 0; npolled < num_entries; ++npolled) {
2263 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2264 if (ret)
2265 break;
2266 }
2267
8f3e9f3e
WHX		 2268 if (npolled) {
2269 *hr_cq->tptr_addr = hr_cq->cons_index &
2270 ((hr_cq->cq_depth << 1) - 1);
2271
2272 /* Memroy barrier */
2273 wmb();
a4be892e 2274 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
8f3e9f3e 2275 }
9a443537 2276
2277 spin_unlock_irqrestore(&hr_cq->lock, flags);
2278
2279 if (ret == 0 || ret == -EAGAIN)
2280 return npolled;
2281 else
2282 return ret;
2283}
2284
97f0e39f
WHX		 2285int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2286 struct hns_roce_hem_table *table, int obj)
2287{
2288 struct device *dev = &hr_dev->pdev->dev;
2289 struct hns_roce_v1_priv *priv;
2290 unsigned long end = 0, flags = 0;
2291 uint32_t bt_cmd_val[2] = {0};
2292 void __iomem *bt_cmd;
2293 u64 bt_ba = 0;
2294
016a0059 2295 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 2296
2297 switch (table->type) {
2298 case HEM_TYPE_QPC:
2299 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2300 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2301 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2302 break;
2303 case HEM_TYPE_MTPT:
2304 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2305 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2306 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2307 break;
2308 case HEM_TYPE_CQC:
2309 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2310 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2311 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2312 break;
2313 case HEM_TYPE_SRQC:
2314 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2315 return -EINVAL;
2316 default:
2317 return 0;
2318 }
2319 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2320 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2321 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2322 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2323
2324 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2325
2326 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2327
2328 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2329 while (1) {
2330 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2331 if (!(time_before(jiffies, end))) {
2332 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2333 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2334 flags);
2335 return -EBUSY;
2336 }
2337 } else {
2338 break;
2339 }
2340 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2341 }
2342
2343 bt_cmd_val[0] = (uint32_t)bt_ba;
2344 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2345 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2346 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2347
2348 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2349
2350 return 0;
2351}
2352
9a443537 2353static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2354 struct hns_roce_mtt *mtt,
2355 enum hns_roce_qp_state cur_state,
2356 enum hns_roce_qp_state new_state,
2357 struct hns_roce_qp_context *context,
2358 struct hns_roce_qp *hr_qp)
2359{
2360 static const u16
2361 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2362 [HNS_ROCE_QP_STATE_RST] = {
2363 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2364 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2365 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2366 },
2367 [HNS_ROCE_QP_STATE_INIT] = {
2368 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2369 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2370 /* Note: In v1 engine, HW doesn't support RST2INIT.
2371 * We use RST2INIT cmd instead of INIT2INIT.
2372 */
2373 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2374 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2375 },
2376 [HNS_ROCE_QP_STATE_RTR] = {
2377 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2378 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2379 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2380 },
2381 [HNS_ROCE_QP_STATE_RTS] = {
2382 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2383 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2384 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2385 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2386 },
2387 [HNS_ROCE_QP_STATE_SQD] = {
2388 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2389 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2390 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2391 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2392 },
2393 [HNS_ROCE_QP_STATE_ERR] = {
2394 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2395 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2396 }
2397 };
2398
2399 struct hns_roce_cmd_mailbox *mailbox;
2400 struct device *dev = &hr_dev->pdev->dev;
2401 int ret = 0;
2402
2403 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2404 new_state >= HNS_ROCE_QP_NUM_STATE ||
2405 !op[cur_state][new_state]) {
2406 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2407 cur_state, new_state);
2408 return -EINVAL;
2409 }
2410
2411 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2412 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2413 HNS_ROCE_CMD_2RST_QP,
6b877c32 2414 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2415
2416 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2417 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2418 HNS_ROCE_CMD_2ERR_QP,
6b877c32 2419 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2420
2421 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2422 if (IS_ERR(mailbox))
2423 return PTR_ERR(mailbox);
2424
2425 memcpy(mailbox->buf, context, sizeof(*context));
2426
2427 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2428 op[cur_state][new_state],
6b877c32 2429 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2430
2431 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2432 return ret;
2433}
2434
2435static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2436 int attr_mask, enum ib_qp_state cur_state,
2437 enum ib_qp_state new_state)
2438{
2439 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2440 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2441 struct hns_roce_sqp_context *context;
2442 struct device *dev = &hr_dev->pdev->dev;
2443 dma_addr_t dma_handle = 0;
2444 int rq_pa_start;
2445 u32 reg_val;
2446 u64 *mtts;
2447 u32 *addr;
2448
2449 context = kzalloc(sizeof(*context), GFP_KERNEL);
2450 if (!context)
2451 return -ENOMEM;
2452
2453 /* Search QP buf's MTTs */
2454 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2455 hr_qp->mtt.first_seg, &dma_handle);
2456 if (!mtts) {
2457 dev_err(dev, "qp buf pa find failed\n");
2458 goto out;
2459 }
2460
2461 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2462 roce_set_field(context->qp1c_bytes_4,
2463 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2464 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2465 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2466 roce_set_field(context->qp1c_bytes_4,
2467 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2468 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2469 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2470 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2471 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2472
2473 context->sq_rq_bt_l = (u32)(dma_handle);
2474 roce_set_field(context->qp1c_bytes_12,
2475 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2476 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2477 ((u32)(dma_handle >> 32)));
2478
2479 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2480 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2481 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
7716809e 2482 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
9a443537 2483 roce_set_bit(context->qp1c_bytes_16,
2484 QP1C_BYTES_16_SIGNALING_TYPE_S,
2485 hr_qp->sq_signal_bits);
9a443537 2486 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2487 1);
2488 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2489 1);
2490 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2491 0);
2492
2493 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2494 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2495 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2496 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2497
2498 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2499 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2500
2501 roce_set_field(context->qp1c_bytes_28,
2502 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2503 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2504 (mtts[rq_pa_start]) >> 32);
2505 roce_set_field(context->qp1c_bytes_28,
2506 QP1C_BYTES_28_RQ_CUR_IDX_M,
2507 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2508
2509 roce_set_field(context->qp1c_bytes_32,
2510 QP1C_BYTES_32_RX_CQ_NUM_M,
2511 QP1C_BYTES_32_RX_CQ_NUM_S,
2512 to_hr_cq(ibqp->recv_cq)->cqn);
2513 roce_set_field(context->qp1c_bytes_32,
2514 QP1C_BYTES_32_TX_CQ_NUM_M,
2515 QP1C_BYTES_32_TX_CQ_NUM_S,
2516 to_hr_cq(ibqp->send_cq)->cqn);
2517
2518 context->cur_sq_wqe_ba_l = (u32)mtts[0];
2519
2520 roce_set_field(context->qp1c_bytes_40,
2521 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2522 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2523 (mtts[0]) >> 32);
2524 roce_set_field(context->qp1c_bytes_40,
2525 QP1C_BYTES_40_SQ_CUR_IDX_M,
2526 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2527
2528 /* Copy context to QP1C register */
2529 addr = (u32 *)(hr_dev->reg_base + ROCEE_QP1C_CFG0_0_REG +
7716809e 2530 hr_qp->phy_port * sizeof(*context));
9a443537 2531
2532 writel(context->qp1c_bytes_4, addr);
2533 writel(context->sq_rq_bt_l, addr + 1);
2534 writel(context->qp1c_bytes_12, addr + 2);
2535 writel(context->qp1c_bytes_16, addr + 3);
2536 writel(context->qp1c_bytes_20, addr + 4);
2537 writel(context->cur_rq_wqe_ba_l, addr + 5);
2538 writel(context->qp1c_bytes_28, addr + 6);
2539 writel(context->qp1c_bytes_32, addr + 7);
2540 writel(context->cur_sq_wqe_ba_l, addr + 8);
c24bf895 2541 writel(context->qp1c_bytes_40, addr + 9);
9a443537 2542 }
2543
2544 /* Modify QP1C status */
2545 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 2546 hr_qp->phy_port * sizeof(*context));
9a443537 2547 roce_set_field(reg_val, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2548 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2549 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 2550 hr_qp->phy_port * sizeof(*context), reg_val);
9a443537 2551
2552 hr_qp->state = new_state;
2553 if (new_state == IB_QPS_RESET) {
2554 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2555 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2556 if (ibqp->send_cq != ibqp->recv_cq)
2557 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2558 hr_qp->qpn, NULL);
2559
2560 hr_qp->rq.head = 0;
2561 hr_qp->rq.tail = 0;
2562 hr_qp->sq.head = 0;
2563 hr_qp->sq.tail = 0;
2564 hr_qp->sq_next_wqe = 0;
2565 }
2566
2567 kfree(context);
2568 return 0;
2569
2570out:
2571 kfree(context);
2572 return -EINVAL;
2573}
2574
2575static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2576 int attr_mask, enum ib_qp_state cur_state,
2577 enum ib_qp_state new_state)
2578{
2579 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2580 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2581 struct device *dev = &hr_dev->pdev->dev;
2582 struct hns_roce_qp_context *context;
d8966fcd 2583 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
9a443537 2584 dma_addr_t dma_handle_2 = 0;
2585 dma_addr_t dma_handle = 0;
2586 uint32_t doorbell[2] = {0};
2587 int rq_pa_start = 0;
9a443537 2588 u64 *mtts_2 = NULL;
2589 int ret = -EINVAL;
2590 u64 *mtts = NULL;
2591 int port;
d8966fcd 2592 u8 port_num;
9a443537 2593 u8 *dmac;
2594 u8 *smac;
2595
2596 context = kzalloc(sizeof(*context), GFP_KERNEL);
2597 if (!context)
2598 return -ENOMEM;
2599
2600 /* Search qp buf's mtts */
2601 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2602 hr_qp->mtt.first_seg, &dma_handle);
2603 if (mtts == NULL) {
2604 dev_err(dev, "qp buf pa find failed\n");
2605 goto out;
2606 }
2607
2608 /* Search IRRL's mtts */
2609 mtts_2 = hns_roce_table_find(&hr_dev->qp_table.irrl_table, hr_qp->qpn,
2610 &dma_handle_2);
2611 if (mtts_2 == NULL) {
2612 dev_err(dev, "qp irrl_table find failed\n");
2613 goto out;
2614 }
2615
2616 /*
e84e40be
S		 2617 * Reset to init
2618 * Mandatory param:
2619 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2620 * Optional param: NA
2621 */
9a443537 2622 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2623 roce_set_field(context->qpc_bytes_4,
2624 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2625 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2626 to_hr_qp_type(hr_qp->ibqp.qp_type));
2627
2628 roce_set_bit(context->qpc_bytes_4,
2629 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2630 roce_set_bit(context->qpc_bytes_4,
2631 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2632 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2633 roce_set_bit(context->qpc_bytes_4,
2634 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2635 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2636 );
2637 roce_set_bit(context->qpc_bytes_4,
2638 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2639 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2640 );
2641 roce_set_bit(context->qpc_bytes_4,
2642 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2643 roce_set_field(context->qpc_bytes_4,
2644 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2645 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2646 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2647 roce_set_field(context->qpc_bytes_4,
2648 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2649 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2650 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2651 roce_set_field(context->qpc_bytes_4,
2652 QP_CONTEXT_QPC_BYTES_4_PD_M,
2653 QP_CONTEXT_QPC_BYTES_4_PD_S,
2654 to_hr_pd(ibqp->pd)->pdn);
2655 hr_qp->access_flags = attr->qp_access_flags;
2656 roce_set_field(context->qpc_bytes_8,
2657 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2658 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2659 to_hr_cq(ibqp->send_cq)->cqn);
2660 roce_set_field(context->qpc_bytes_8,
2661 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2662 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2663 to_hr_cq(ibqp->recv_cq)->cqn);
2664
2665 if (ibqp->srq)
2666 roce_set_field(context->qpc_bytes_12,
2667 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2668 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2669 to_hr_srq(ibqp->srq)->srqn);
2670
2671 roce_set_field(context->qpc_bytes_12,
2672 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2673 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2674 attr->pkey_index);
2675 hr_qp->pkey_index = attr->pkey_index;
2676 roce_set_field(context->qpc_bytes_16,
2677 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2678 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2679
2680 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2681 roce_set_field(context->qpc_bytes_4,
2682 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2683 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2684 to_hr_qp_type(hr_qp->ibqp.qp_type));
2685 roce_set_bit(context->qpc_bytes_4,
2686 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2687 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2688 roce_set_bit(context->qpc_bytes_4,
2689 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2690 !!(attr->qp_access_flags &
2691 IB_ACCESS_REMOTE_READ));
2692 roce_set_bit(context->qpc_bytes_4,
2693 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2694 !!(attr->qp_access_flags &
2695 IB_ACCESS_REMOTE_WRITE));
2696 } else {
2697 roce_set_bit(context->qpc_bytes_4,
2698 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2699 !!(hr_qp->access_flags &
2700 IB_ACCESS_REMOTE_READ));
2701 roce_set_bit(context->qpc_bytes_4,
2702 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2703 !!(hr_qp->access_flags &
2704 IB_ACCESS_REMOTE_WRITE));
2705 }
2706
2707 roce_set_bit(context->qpc_bytes_4,
2708 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2709 roce_set_field(context->qpc_bytes_4,
2710 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2711 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2712 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2713 roce_set_field(context->qpc_bytes_4,
2714 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2715 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2716 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2717 roce_set_field(context->qpc_bytes_4,
2718 QP_CONTEXT_QPC_BYTES_4_PD_M,
2719 QP_CONTEXT_QPC_BYTES_4_PD_S,
2720 to_hr_pd(ibqp->pd)->pdn);
2721
2722 roce_set_field(context->qpc_bytes_8,
2723 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2724 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2725 to_hr_cq(ibqp->send_cq)->cqn);
2726 roce_set_field(context->qpc_bytes_8,
2727 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2728 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2729 to_hr_cq(ibqp->recv_cq)->cqn);
2730
2731 if (ibqp->srq)
2732 roce_set_field(context->qpc_bytes_12,
2733 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2734 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2735 to_hr_srq(ibqp->srq)->srqn);
2736 if (attr_mask & IB_QP_PKEY_INDEX)
2737 roce_set_field(context->qpc_bytes_12,
2738 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2739 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2740 attr->pkey_index);
2741 else
2742 roce_set_field(context->qpc_bytes_12,
2743 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2744 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2745 hr_qp->pkey_index);
2746
2747 roce_set_field(context->qpc_bytes_16,
2748 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2749 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2750 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2751 if ((attr_mask & IB_QP_ALT_PATH) ||
2752 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2753 (attr_mask & IB_QP_PKEY_INDEX) ||
2754 (attr_mask & IB_QP_QKEY)) {
2755 dev_err(dev, "INIT2RTR attr_mask error\n");
2756 goto out;
2757 }
2758
44c58487 2759 dmac = (u8 *)attr->ah_attr.roce.dmac;
9a443537 2760
2761 context->sq_rq_bt_l = (u32)(dma_handle);
2762 roce_set_field(context->qpc_bytes_24,
2763 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2764 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2765 ((u32)(dma_handle >> 32)));
2766 roce_set_bit(context->qpc_bytes_24,
2767 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2768 1);
2769 roce_set_field(context->qpc_bytes_24,
2770 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2771 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2772 attr->min_rnr_timer);
2773 context->irrl_ba_l = (u32)(dma_handle_2);
2774 roce_set_field(context->qpc_bytes_32,
2775 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2776 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2777 ((u32)(dma_handle_2 >> 32)) &
2778 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2779 roce_set_field(context->qpc_bytes_32,
2780 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2781 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2782 roce_set_bit(context->qpc_bytes_32,
2783 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2784 1);
2785 roce_set_bit(context->qpc_bytes_32,
2786 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2787 hr_qp->sq_signal_bits);
2788
80596c67
LO		 2789 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2790 hr_qp->port;
2791 smac = (u8 *)hr_dev->dev_addr[port];
2792 /* when dmac equals smac or loop_idc is 1, it should loopback */
2793 if (ether_addr_equal_unaligned(dmac, smac) ||
2794 hr_dev->loop_idc == 0x1)
9a443537 2795 roce_set_bit(context->qpc_bytes_32,
80596c67 2796 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
9a443537 2797
2798 roce_set_bit(context->qpc_bytes_32,
2799 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
d8966fcd 2800 rdma_ah_get_ah_flags(&attr->ah_attr));
9a443537 2801 roce_set_field(context->qpc_bytes_32,
2802 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2803 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2804 ilog2((unsigned int)attr->max_dest_rd_atomic));
2805
2806 roce_set_field(context->qpc_bytes_36,
2807 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2808 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2809 attr->dest_qp_num);
2810
2811 /* Configure GID index */
d8966fcd 2812 port_num = rdma_ah_get_port_num(&attr->ah_attr);
9a443537 2813 roce_set_field(context->qpc_bytes_36,
2814 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2815 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
d8966fcd
DC		 2816 hns_get_gid_index(hr_dev,
2817 port_num - 1,
2818 grh->sgid_index));
9a443537 2819
2820 memcpy(&(context->dmac_l), dmac, 4);
2821
2822 roce_set_field(context->qpc_bytes_44,
2823 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2824 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2825 *((u16 *)(&dmac[4])));
2826 roce_set_field(context->qpc_bytes_44,
2827 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2828 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
d8966fcd 2829 rdma_ah_get_static_rate(&attr->ah_attr));
9a443537 2830 roce_set_field(context->qpc_bytes_44,
2831 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2832 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
d8966fcd 2833 grh->hop_limit);
9a443537 2834
2835 roce_set_field(context->qpc_bytes_48,
2836 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2837 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
d8966fcd 2838 grh->flow_label);
9a443537 2839 roce_set_field(context->qpc_bytes_48,
2840 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2841 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
d8966fcd 2842 grh->traffic_class);
9a443537 2843 roce_set_field(context->qpc_bytes_48,
2844 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2845 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2846
d8966fcd
DC		 2847 memcpy(context->dgid, grh->dgid.raw,
2848 sizeof(grh->dgid.raw));
9a443537 2849
2850 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2851 roce_get_field(context->qpc_bytes_44,
2852 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2853 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2854
2855 roce_set_field(context->qpc_bytes_68,
2856 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
1fad5fab
LO		 2857 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2858 hr_qp->rq.head);
9a443537 2859 roce_set_field(context->qpc_bytes_68,
2860 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2861 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2862
2863 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2864 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2865
2866 roce_set_field(context->qpc_bytes_76,
2867 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2868 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2869 mtts[rq_pa_start] >> 32);
2870 roce_set_field(context->qpc_bytes_76,
2871 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2872 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2873
2874 context->rx_rnr_time = 0;
2875
2876 roce_set_field(context->qpc_bytes_84,
2877 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2878 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2879 attr->rq_psn - 1);
2880 roce_set_field(context->qpc_bytes_84,
2881 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2882 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2883
2884 roce_set_field(context->qpc_bytes_88,
2885 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2886 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2887 attr->rq_psn);
2888 roce_set_bit(context->qpc_bytes_88,
2889 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2890 roce_set_bit(context->qpc_bytes_88,
2891 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2892 roce_set_field(context->qpc_bytes_88,
2893 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2894 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2895 0);
2896 roce_set_field(context->qpc_bytes_88,
2897 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2898 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2899 0);
2900
2901 context->dma_length = 0;
2902 context->r_key = 0;
2903 context->va_l = 0;
2904 context->va_h = 0;
2905
2906 roce_set_field(context->qpc_bytes_108,
2907 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2908 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2909 roce_set_bit(context->qpc_bytes_108,
2910 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2911 roce_set_bit(context->qpc_bytes_108,
2912 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
2913
2914 roce_set_field(context->qpc_bytes_112,
2915 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
2916 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
2917 roce_set_field(context->qpc_bytes_112,
2918 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
2919 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
2920
2921 /* For chip resp ack */
2922 roce_set_field(context->qpc_bytes_156,
2923 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2924 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 2925 hr_qp->phy_port);
9a443537 2926 roce_set_field(context->qpc_bytes_156,
2927 QP_CONTEXT_QPC_BYTES_156_SL_M,
d8966fcd
DC		 2928 QP_CONTEXT_QPC_BYTES_156_SL_S,
2929 rdma_ah_get_sl(&attr->ah_attr));
2930 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
9a443537 2931 } else if (cur_state == IB_QPS_RTR &&
2932 new_state == IB_QPS_RTS) {
2933 /* If exist optional param, return error */
2934 if ((attr_mask & IB_QP_ALT_PATH) ||
2935 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2936 (attr_mask & IB_QP_QKEY) ||
2937 (attr_mask & IB_QP_PATH_MIG_STATE) ||
2938 (attr_mask & IB_QP_CUR_STATE) ||
2939 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
2940 dev_err(dev, "RTR2RTS attr_mask error\n");
2941 goto out;
2942 }
2943
2944 context->rx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
2945
2946 roce_set_field(context->qpc_bytes_120,
2947 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
2948 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
2949 (mtts[0]) >> 32);
2950
2951 roce_set_field(context->qpc_bytes_124,
2952 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
2953 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
2954 roce_set_field(context->qpc_bytes_124,
2955 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
2956 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
2957
2958 roce_set_field(context->qpc_bytes_128,
2959 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
2960 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
2961 attr->sq_psn);
2962 roce_set_bit(context->qpc_bytes_128,
2963 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
2964 roce_set_field(context->qpc_bytes_128,
2965 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
2966 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
2967 0);
2968 roce_set_bit(context->qpc_bytes_128,
2969 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
2970
2971 roce_set_field(context->qpc_bytes_132,
2972 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
2973 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
2974 roce_set_field(context->qpc_bytes_132,
2975 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
2976 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
2977
2978 roce_set_field(context->qpc_bytes_136,
2979 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
2980 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
2981 attr->sq_psn);
2982 roce_set_field(context->qpc_bytes_136,
2983 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
2984 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
2985 attr->sq_psn);
2986
2987 roce_set_field(context->qpc_bytes_140,
2988 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
2989 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
2990 (attr->sq_psn >> SQ_PSN_SHIFT));
2991 roce_set_field(context->qpc_bytes_140,
2992 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
2993 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
2994 roce_set_bit(context->qpc_bytes_140,
2995 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
2996
9a443537 2997 roce_set_field(context->qpc_bytes_148,
2998 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
2999 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3000 roce_set_field(context->qpc_bytes_148,
3001 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
7c7a4ea1
LO		 3002 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3003 attr->retry_cnt);
9a443537 3004 roce_set_field(context->qpc_bytes_148,
3005 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
7c7a4ea1
LO		 3006 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3007 attr->rnr_retry);
9a443537 3008 roce_set_field(context->qpc_bytes_148,
3009 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3010 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3011
3012 context->rnr_retry = 0;
3013
3014 roce_set_field(context->qpc_bytes_156,
3015 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3016 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3017 attr->retry_cnt);
c6c3bfea
LO		 3018 if (attr->timeout < 0x12) {
3019 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3020 attr->timeout);
3021 roce_set_field(context->qpc_bytes_156,
3022 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3023 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3024 0x12);
3025 } else {
3026 roce_set_field(context->qpc_bytes_156,
3027 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3028 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3029 attr->timeout);
3030 }
9a443537 3031 roce_set_field(context->qpc_bytes_156,
3032 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3033 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3034 attr->rnr_retry);
3035 roce_set_field(context->qpc_bytes_156,
3036 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3037 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 3038 hr_qp->phy_port);
9a443537 3039 roce_set_field(context->qpc_bytes_156,
3040 QP_CONTEXT_QPC_BYTES_156_SL_M,
d8966fcd
DC		 3041 QP_CONTEXT_QPC_BYTES_156_SL_S,
3042 rdma_ah_get_sl(&attr->ah_attr));
3043 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
9a443537 3044 roce_set_field(context->qpc_bytes_156,
3045 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3046 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3047 ilog2((unsigned int)attr->max_rd_atomic));
3048 roce_set_field(context->qpc_bytes_156,
3049 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3050 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3051 context->pkt_use_len = 0;
3052
3053 roce_set_field(context->qpc_bytes_164,
3054 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3055 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3056 roce_set_field(context->qpc_bytes_164,
3057 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3058 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3059
3060 roce_set_field(context->qpc_bytes_168,
3061 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3062 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3063 attr->sq_psn);
3064 roce_set_field(context->qpc_bytes_168,
3065 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3066 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3067 roce_set_field(context->qpc_bytes_168,
3068 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3069 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3070 roce_set_bit(context->qpc_bytes_168,
3071 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3072 roce_set_bit(context->qpc_bytes_168,
3073 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3074 roce_set_bit(context->qpc_bytes_168,
3075 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3076 context->sge_use_len = 0;
3077
3078 roce_set_field(context->qpc_bytes_176,
3079 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3080 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3081 roce_set_field(context->qpc_bytes_176,
3082 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3083 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3084 0);
3085 roce_set_field(context->qpc_bytes_180,
3086 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3087 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3088 roce_set_field(context->qpc_bytes_180,
3089 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3090 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3091
3092 context->tx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
3093
3094 roce_set_field(context->qpc_bytes_188,
3095 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3096 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3097 (mtts[0]) >> 32);
3098 roce_set_bit(context->qpc_bytes_188,
3099 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3100 roce_set_field(context->qpc_bytes_188,
3101 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3102 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3103 0);
deb17f6f 3104 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
9a443537 3105 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3106 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3107 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3108 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3109 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3110 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
deb17f6f
LO		 3111 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3112 dev_err(dev, "not support this status migration\n");
9a443537 3113 goto out;
3114 }
3115
3116 /* Every status migrate must change state */
3117 roce_set_field(context->qpc_bytes_144,
3118 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
1dec243a 3119 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
9a443537 3120
3121 /* SW pass context to HW */
3122 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3123 to_hns_roce_state(cur_state),
3124 to_hns_roce_state(new_state), context,
3125 hr_qp);
3126 if (ret) {
3127 dev_err(dev, "hns_roce_qp_modify failed\n");
3128 goto out;
3129 }
3130
3131 /*
e84e40be
S		 3132 * Use rst2init to instead of init2init with drv,
3133 * need to hw to flash RQ HEAD by DB again
3134 */
9a443537 3135 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3136 /* Memory barrier */
3137 wmb();
9a443537 3138
509bf0c2
LO		 3139 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3140 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3141 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3142 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3143 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3144 RQ_DOORBELL_U32_8_CMD_S, 1);
3145 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3146
3147 if (ibqp->uobject) {
3148 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3149 ROCEE_DB_OTHERS_L_0_REG +
3150 DB_REG_OFFSET * hr_dev->priv_uar.index;
9a443537 3151 }
509bf0c2
LO		 3152
3153 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
9a443537 3154 }
3155
3156 hr_qp->state = new_state;
3157
3158 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3159 hr_qp->resp_depth = attr->max_dest_rd_atomic;
7716809e
LO		 3160 if (attr_mask & IB_QP_PORT) {
3161 hr_qp->port = attr->port_num - 1;
3162 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3163 }
9a443537 3164
3165 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3166 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3167 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3168 if (ibqp->send_cq != ibqp->recv_cq)
3169 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3170 hr_qp->qpn, NULL);
3171
3172 hr_qp->rq.head = 0;
3173 hr_qp->rq.tail = 0;
3174 hr_qp->sq.head = 0;
3175 hr_qp->sq.tail = 0;
3176 hr_qp->sq_next_wqe = 0;
3177 }
3178out:
3179 kfree(context);
3180 return ret;
3181}
3182
3183int hns_roce_v1_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
3184 int attr_mask, enum ib_qp_state cur_state,
3185 enum ib_qp_state new_state)
3186{
3187
3188 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3189 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3190 new_state);
3191 else
3192 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3193 new_state);
3194}
3195
3196static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3197{
3198 switch (state) {
3199 case HNS_ROCE_QP_STATE_RST:
3200 return IB_QPS_RESET;
3201 case HNS_ROCE_QP_STATE_INIT:
3202 return IB_QPS_INIT;
3203 case HNS_ROCE_QP_STATE_RTR:
3204 return IB_QPS_RTR;
3205 case HNS_ROCE_QP_STATE_RTS:
3206 return IB_QPS_RTS;
3207 case HNS_ROCE_QP_STATE_SQD:
3208 return IB_QPS_SQD;
3209 case HNS_ROCE_QP_STATE_ERR:
3210 return IB_QPS_ERR;
3211 default:
3212 return IB_QPS_ERR;
3213 }
3214}
3215
3216static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3217 struct hns_roce_qp *hr_qp,
3218 struct hns_roce_qp_context *hr_context)
3219{
3220 struct hns_roce_cmd_mailbox *mailbox;
3221 int ret;
3222
3223 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3224 if (IS_ERR(mailbox))
3225 return PTR_ERR(mailbox);
3226
3227 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3228 HNS_ROCE_CMD_QUERY_QP,
6b877c32 3229 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 3230 if (!ret)
3231 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3232 else
3233 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3234
3235 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3236
3237 return ret;
3238}
3239
9eefa953
LO		 3240static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3241 int qp_attr_mask,
3242 struct ib_qp_init_attr *qp_init_attr)
3243{
3244 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3245 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3246 struct hns_roce_sqp_context context;
3247 u32 addr;
3248
3249 mutex_lock(&hr_qp->mutex);
3250
3251 if (hr_qp->state == IB_QPS_RESET) {
3252 qp_attr->qp_state = IB_QPS_RESET;
3253 goto done;
3254 }
3255
3256 addr = ROCEE_QP1C_CFG0_0_REG +
3257 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3258 context.qp1c_bytes_4 = roce_read(hr_dev, addr);
3259 context.sq_rq_bt_l = roce_read(hr_dev, addr + 1);
3260 context.qp1c_bytes_12 = roce_read(hr_dev, addr + 2);
3261 context.qp1c_bytes_16 = roce_read(hr_dev, addr + 3);
3262 context.qp1c_bytes_20 = roce_read(hr_dev, addr + 4);
3263 context.cur_rq_wqe_ba_l = roce_read(hr_dev, addr + 5);
3264 context.qp1c_bytes_28 = roce_read(hr_dev, addr + 6);
3265 context.qp1c_bytes_32 = roce_read(hr_dev, addr + 7);
3266 context.cur_sq_wqe_ba_l = roce_read(hr_dev, addr + 8);
3267 context.qp1c_bytes_40 = roce_read(hr_dev, addr + 9);
3268
3269 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3270 QP1C_BYTES_4_QP_STATE_M,
3271 QP1C_BYTES_4_QP_STATE_S);
3272 qp_attr->qp_state = hr_qp->state;
3273 qp_attr->path_mtu = IB_MTU_256;
3274 qp_attr->path_mig_state = IB_MIG_ARMED;
3275 qp_attr->qkey = QKEY_VAL;
3276 qp_attr->rq_psn = 0;
3277 qp_attr->sq_psn = 0;
3278 qp_attr->dest_qp_num = 1;
3279 qp_attr->qp_access_flags = 6;
3280
3281 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3282 QP1C_BYTES_20_PKEY_IDX_M,
3283 QP1C_BYTES_20_PKEY_IDX_S);
3284 qp_attr->port_num = hr_qp->port + 1;
3285 qp_attr->sq_draining = 0;
3286 qp_attr->max_rd_atomic = 0;
3287 qp_attr->max_dest_rd_atomic = 0;
3288 qp_attr->min_rnr_timer = 0;
3289 qp_attr->timeout = 0;
3290 qp_attr->retry_cnt = 0;
3291 qp_attr->rnr_retry = 0;
3292 qp_attr->alt_timeout = 0;
3293
3294done:
3295 qp_attr->cur_qp_state = qp_attr->qp_state;
3296 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3297 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3298 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3299 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3300 qp_attr->cap.max_inline_data = 0;
3301 qp_init_attr->cap = qp_attr->cap;
3302 qp_init_attr->create_flags = 0;
3303
3304 mutex_unlock(&hr_qp->mutex);
3305
3306 return 0;
3307}
3308
3309static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3310 int qp_attr_mask,
3311 struct ib_qp_init_attr *qp_init_attr)
9a443537 3312{
3313 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3314 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3315 struct device *dev = &hr_dev->pdev->dev;
3316 struct hns_roce_qp_context *context;
3317 int tmp_qp_state = 0;
3318 int ret = 0;
3319 int state;
3320
3321 context = kzalloc(sizeof(*context), GFP_KERNEL);
3322 if (!context)
3323 return -ENOMEM;
3324
3325 memset(qp_attr, 0, sizeof(*qp_attr));
3326 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3327
3328 mutex_lock(&hr_qp->mutex);
3329
3330 if (hr_qp->state == IB_QPS_RESET) {
3331 qp_attr->qp_state = IB_QPS_RESET;
3332 goto done;
3333 }
3334
3335 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3336 if (ret) {
3337 dev_err(dev, "query qpc error\n");
3338 ret = -EINVAL;
3339 goto out;
3340 }
3341
3342 state = roce_get_field(context->qpc_bytes_144,
3343 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3344 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3345 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3346 if (tmp_qp_state == -1) {
3347 dev_err(dev, "to_ib_qp_state error\n");
3348 ret = -EINVAL;
3349 goto out;
3350 }
3351 hr_qp->state = (u8)tmp_qp_state;
3352 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3353 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3354 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3355 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3356 qp_attr->path_mig_state = IB_MIG_ARMED;
3357 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3358 qp_attr->qkey = QKEY_VAL;
3359
3360 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3361 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3362 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3363 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3364 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3365 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3366 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3367 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3368 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3369 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3370 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3371 ((roce_get_bit(context->qpc_bytes_4,
3372 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3373 ((roce_get_bit(context->qpc_bytes_4,
3374 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3375
3376 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3377 hr_qp->ibqp.qp_type == IB_QPT_UC) {
d8966fcd
DC		 3378 struct ib_global_route *grh =
3379 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3380
3381 rdma_ah_set_sl(&qp_attr->ah_attr,
3382 roce_get_field(context->qpc_bytes_156,
3383 QP_CONTEXT_QPC_BYTES_156_SL_M,
3384 QP_CONTEXT_QPC_BYTES_156_SL_S));
3385 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3386 grh->flow_label =
3387 roce_get_field(context->qpc_bytes_48,
3388 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3389 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3390 grh->sgid_index =
3391 roce_get_field(context->qpc_bytes_36,
3392 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3393 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3394 grh->hop_limit =
3395 roce_get_field(context->qpc_bytes_44,
3396 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3397 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3398 grh->traffic_class =
3399 roce_get_field(context->qpc_bytes_48,
3400 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3401 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3402
3403 memcpy(grh->dgid.raw, context->dgid,
3404 sizeof(grh->dgid.raw));
9a443537 3405 }
3406
3407 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3408 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3409 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
dd783a21 3410 qp_attr->port_num = hr_qp->port + 1;
9a443537 3411 qp_attr->sq_draining = 0;
3412 qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156,
3413 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3414 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3415 qp_attr->max_dest_rd_atomic = roce_get_field(context->qpc_bytes_32,
3416 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3417 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3418 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3419 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3420 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3421 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3422 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3423 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3424 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3425 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3426 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3427 qp_attr->rnr_retry = context->rnr_retry;
3428
3429done:
3430 qp_attr->cur_qp_state = qp_attr->qp_state;
3431 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3432 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3433
3434 if (!ibqp->uobject) {
3435 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3436 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3437 } else {
3438 qp_attr->cap.max_send_wr = 0;
3439 qp_attr->cap.max_send_sge = 0;
3440 }
3441
3442 qp_init_attr->cap = qp_attr->cap;
3443
3444out:
3445 mutex_unlock(&hr_qp->mutex);
3446 kfree(context);
3447 return ret;
3448}
3449
9eefa953
LO		 3450int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3451 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3452{
3453 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3454
3455 return hr_qp->doorbell_qpn <= 1 ?
3456 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3457 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3458}
d838c481
WHX		 3459
3460static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3461 struct hns_roce_qp *hr_qp,
3462 u32 sdb_issue_ptr,
3463 u32 *sdb_inv_cnt,
3464 u32 *wait_stage)
9a443537 3465{
9a443537 3466 struct device *dev = &hr_dev->pdev->dev;
d838c481
WHX		 3467 u32 sdb_retry_cnt, old_retry;
3468 u32 sdb_send_ptr, old_send;
3469 u32 success_flags = 0;
3470 u32 cur_cnt, old_cnt;
3471 unsigned long end;
3472 u32 send_ptr;
3473 u32 inv_cnt;
3474 u32 tsp_st;
3475
3476 if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3477 *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3478 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3479 hr_qp->qpn, *wait_stage);
3480 return -EINVAL;
3481 }
9a443537 3482
d838c481
WHX		 3483 /* Calculate the total timeout for the entire verification process */
3484 end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3485
3486 if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3487 /* Query db process status, until hw process completely */
3488 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3489 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3490 ROCEE_SDB_PTR_CMP_BITS)) {
3491 if (!time_before(jiffies, end)) {
3492 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3493 hr_qp->qpn, sdb_issue_ptr,
3494 sdb_send_ptr);
3495 return 0;
3496 }
3497
3498 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3499 sdb_send_ptr = roce_read(hr_dev,
9a443537 3500 ROCEE_SDB_SEND_PTR_REG);
d838c481 3501 }
9a443537 3502
d838c481
WHX		 3503 if (roce_get_field(sdb_issue_ptr,
3504 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3505 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3506 roce_get_field(sdb_send_ptr,
3507 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3508 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3509 old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3510 old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
9a443537 3511
9a443537 3512 do {
d838c481
WHX		 3513 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3514 if (roce_get_bit(tsp_st,
3515 ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3516 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3517 return 0;
3518 }
3519
9a443537 3520 if (!time_before(jiffies, end)) {
d838c481
WHX		 3521 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3522 "issue 0x%x send 0x%x.\n",
3523 hr_qp->qpn, sdb_issue_ptr,
3524 sdb_send_ptr);
3525 return 0;
9a443537 3526 }
d838c481
WHX		 3527
3528 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3529
3530 sdb_send_ptr = roce_read(hr_dev,
3531 ROCEE_SDB_SEND_PTR_REG);
3532 sdb_retry_cnt = roce_read(hr_dev,
3533 ROCEE_SDB_RETRY_CNT_REG);
3534 cur_cnt = roce_get_field(sdb_send_ptr,
3535 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3536 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3537 roce_get_field(sdb_retry_cnt,
3538 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3539 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3540 if (!roce_get_bit(tsp_st,
3541 ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3542 old_cnt = roce_get_field(old_send,
3543 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3544 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3545 roce_get_field(old_retry,
3546 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3547 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3548 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3549 success_flags = 1;
3550 } else {
3551 old_cnt = roce_get_field(old_send,
3552 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3553 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
5f110ac4 3554 if (cur_cnt - old_cnt >
3555 SDB_ST_CMP_VAL) {
d838c481 3556 success_flags = 1;
5f110ac4 3557 } else {
3558 send_ptr =
3559 roce_get_field(old_send,
d838c481
WHX		 3560 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3561 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3562 roce_get_field(sdb_retry_cnt,
3563 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3564 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3565 roce_set_field(old_send,
3566 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3567 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3568 send_ptr);
3569 }
3570 }
3571 } while (!success_flags);
3572 }
3573
3574 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3575
3576 /* Get list pointer */
3577 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3578 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3579 hr_qp->qpn, *sdb_inv_cnt);
3580 }
3581
3582 if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3583 /* Query db's list status, until hw reversal */
3584 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3585 while (roce_hw_index_cmp_lt(inv_cnt,
3586 *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3587 ROCEE_SDB_CNT_CMP_BITS)) {
3588 if (!time_before(jiffies, end)) {
3589 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3590 hr_qp->qpn, inv_cnt);
3591 return 0;
3592 }
3593
3594 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3595 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
9a443537 3596 }
d838c481
WHX		 3597
3598 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3599 }
3600
3601 return 0;
3602}
3603
3604static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3605 struct hns_roce_qp *hr_qp,
3606 struct hns_roce_qp_work *qp_work_entry,
3607 int *is_timeout)
3608{
3609 struct device *dev = &hr_dev->pdev->dev;
3610 u32 sdb_issue_ptr;
3611 int ret;
3612
3613 if (hr_qp->state != IB_QPS_RESET) {
3614 /* Set qp to ERR, waiting for hw complete processing all dbs */
3615 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3616 IB_QPS_ERR);
3617 if (ret) {
3618 dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3619 hr_qp->qpn);
3620 return ret;
3621 }
3622
3623 /* Record issued doorbell */
3624 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3625 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3626 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3627
3628 /* Query db process status, until hw process completely */
3629 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3630 &qp_work_entry->sdb_inv_cnt,
3631 &qp_work_entry->db_wait_stage);
3632 if (ret) {
3633 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3634 hr_qp->qpn);
3635 return ret;
3636 }
3637
3638 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3639 qp_work_entry->sche_cnt = 0;
3640 *is_timeout = 1;
3641 return 0;
3642 }
3643
3644 /* Modify qp to reset before destroying qp */
3645 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3646 IB_QPS_RESET);
3647 if (ret) {
3648 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3649 hr_qp->qpn);
3650 return ret;
3651 }
3652 }
3653
3654 return 0;
3655}
3656
3657static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3658{
3659 struct hns_roce_qp_work *qp_work_entry;
3660 struct hns_roce_v1_priv *priv;
3661 struct hns_roce_dev *hr_dev;
3662 struct hns_roce_qp *hr_qp;
3663 struct device *dev;
58c4f0d8 3664 unsigned long qpn;
d838c481
WHX		 3665 int ret;
3666
3667 qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3668 hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3669 dev = &hr_dev->pdev->dev;
016a0059 3670 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481 3671 hr_qp = qp_work_entry->qp;
58c4f0d8 3672 qpn = hr_qp->qpn;
d838c481 3673
58c4f0d8 3674 dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
d838c481
WHX		 3675
3676 qp_work_entry->sche_cnt++;
3677
3678 /* Query db process status, until hw process completely */
3679 ret = check_qp_db_process_status(hr_dev, hr_qp,
3680 qp_work_entry->sdb_issue_ptr,
3681 &qp_work_entry->sdb_inv_cnt,
3682 &qp_work_entry->db_wait_stage);
3683 if (ret) {
3684 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
58c4f0d8 3685 qpn);
d838c481
WHX		 3686 return;
3687 }
3688
3689 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3690 priv->des_qp.requeue_flag) {
3691 queue_work(priv->des_qp.qp_wq, work);
3692 return;
3693 }
3694
3695 /* Modify qp to reset before destroying qp */
3696 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3697 IB_QPS_RESET);
3698 if (ret) {
58c4f0d8 3699 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
d838c481
WHX		 3700 return;
3701 }
3702
3703 hns_roce_qp_remove(hr_dev, hr_qp);
3704 hns_roce_qp_free(hr_dev, hr_qp);
3705
3706 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3707 /* RC QP, release QPN */
58c4f0d8 3708 hns_roce_release_range_qp(hr_dev, qpn, 1);
d838c481
WHX		 3709 kfree(hr_qp);
3710 } else
3711 kfree(hr_to_hr_sqp(hr_qp));
3712
3713 kfree(qp_work_entry);
3714
58c4f0d8 3715 dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
d838c481
WHX		 3716}
3717
3718int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3719{
3720 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3721 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3722 struct device *dev = &hr_dev->pdev->dev;
3723 struct hns_roce_qp_work qp_work_entry;
3724 struct hns_roce_qp_work *qp_work;
3725 struct hns_roce_v1_priv *priv;
3726 struct hns_roce_cq *send_cq, *recv_cq;
3727 int is_user = !!ibqp->pd->uobject;
3728 int is_timeout = 0;
3729 int ret;
3730
3731 ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3732 if (ret) {
3733 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3734 return ret;
9a443537 3735 }
3736
3737 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3738 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3739
3740 hns_roce_lock_cqs(send_cq, recv_cq);
9a443537 3741 if (!is_user) {
3742 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3743 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3744 if (send_cq != recv_cq)
3745 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3746 }
9a443537 3747 hns_roce_unlock_cqs(send_cq, recv_cq);
3748
d838c481
WHX		 3749 if (!is_timeout) {
3750 hns_roce_qp_remove(hr_dev, hr_qp);
3751 hns_roce_qp_free(hr_dev, hr_qp);
9a443537 3752
d838c481
WHX		 3753 /* RC QP, release QPN */
3754 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3755 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3756 }
9a443537 3757
3758 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3759
d838c481 3760 if (is_user)
9a443537 3761 ib_umem_release(hr_qp->umem);
d838c481 3762 else {
9a443537 3763 kfree(hr_qp->sq.wrid);
3764 kfree(hr_qp->rq.wrid);
d838c481 3765
9a443537 3766 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3767 }
9a443537 3768
d838c481
WHX		 3769 if (!is_timeout) {
3770 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3771 kfree(hr_qp);
3772 else
3773 kfree(hr_to_hr_sqp(hr_qp));
3774 } else {
3775 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3776 if (!qp_work)
3777 return -ENOMEM;
3778
3779 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3780 qp_work->ib_dev = &hr_dev->ib_dev;
3781 qp_work->qp = hr_qp;
3782 qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3783 qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3784 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3785 qp_work->sche_cnt = qp_work_entry.sche_cnt;
3786
016a0059 3787 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 3788 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3789 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3790 }
9a443537 3791
3792 return 0;
3793}
3794
afb6b092
SX		 3795int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3796{
3797 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3798 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3799 struct device *dev = &hr_dev->pdev->dev;
3800 u32 cqe_cnt_ori;
3801 u32 cqe_cnt_cur;
3802 u32 cq_buf_size;
3803 int wait_time = 0;
3804 int ret = 0;
3805
3806 hns_roce_free_cq(hr_dev, hr_cq);
3807
3808 /*
3809 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3810 * have been written by checking the CQE counter.
3811 */
3812 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3813 while (1) {
3814 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3815 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3816 break;
3817
3818 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3819 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3820 break;
3821
3822 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3823 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3824 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3825 hr_cq->cqn);
3826 ret = -ETIMEDOUT;
3827 break;
3828 }
3829 wait_time++;
3830 }
3831
3832 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3833
3834 if (ibcq->uobject)
3835 ib_umem_release(hr_cq->umem);
3836 else {
3837 /* Free the buff of stored cq */
3838 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3839 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3840 }
3841
3842 kfree(hr_cq);
3843
3844 return ret;
3845}
3846
08805fdb 3847static const struct hns_roce_hw hns_roce_hw_v1 = {
9a443537 3848 .reset = hns_roce_v1_reset,
3849 .hw_profile = hns_roce_v1_profile,
3850 .hw_init = hns_roce_v1_init,
3851 .hw_exit = hns_roce_v1_exit,
3852 .set_gid = hns_roce_v1_set_gid,
3853 .set_mac = hns_roce_v1_set_mac,
3854 .set_mtu = hns_roce_v1_set_mtu,
3855 .write_mtpt = hns_roce_v1_write_mtpt,
3856 .write_cqc = hns_roce_v1_write_cqc,
97f0e39f 3857 .clear_hem = hns_roce_v1_clear_hem,
9a443537 3858 .modify_qp = hns_roce_v1_modify_qp,
3859 .query_qp = hns_roce_v1_query_qp,
3860 .destroy_qp = hns_roce_v1_destroy_qp,
3861 .post_send = hns_roce_v1_post_send,
3862 .post_recv = hns_roce_v1_post_recv,
3863 .req_notify_cq = hns_roce_v1_req_notify_cq,
3864 .poll_cq = hns_roce_v1_poll_cq,
bfcc681b 3865 .dereg_mr = hns_roce_v1_dereg_mr,
afb6b092 3866 .destroy_cq = hns_roce_v1_destroy_cq,
9a443537 3867};
08805fdb
WHX		 3868
3869static const struct of_device_id hns_roce_of_match[] = {
3870 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
3871 {},
3872};
3873MODULE_DEVICE_TABLE(of, hns_roce_of_match);
3874
3875static const struct acpi_device_id hns_roce_acpi_match[] = {
3876 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
3877 {},
3878};
3879MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
3880
3881static int hns_roce_node_match(struct device *dev, void *fwnode)
3882{
3883 return dev->fwnode == fwnode;
3884}
3885
3886static struct
3887platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
3888{
3889 struct device *dev;
3890
3891 /* get the 'device' corresponding to the matching 'fwnode' */
3892 dev = bus_find_device(&platform_bus_type, NULL,
3893 fwnode, hns_roce_node_match);
3894 /* get the platform device */
3895 return dev ? to_platform_device(dev) : NULL;
3896}
3897
3898static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
3899{
3900 struct device *dev = &hr_dev->pdev->dev;
3901 struct platform_device *pdev = NULL;
3902 struct net_device *netdev = NULL;
3903 struct device_node *net_node;
3904 struct resource *res;
3905 int port_cnt = 0;
3906 u8 phy_port;
3907 int ret;
3908 int i;
3909
3910 /* check if we are compatible with the underlying SoC */
3911 if (dev_of_node(dev)) {
3912 const struct of_device_id *of_id;
3913
3914 of_id = of_match_node(hns_roce_of_match, dev->of_node);
3915 if (!of_id) {
3916 dev_err(dev, "device is not compatible!\n");
3917 return -ENXIO;
3918 }
3919 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
3920 if (!hr_dev->hw) {
3921 dev_err(dev, "couldn't get H/W specific DT data!\n");
3922 return -ENXIO;
3923 }
3924 } else if (is_acpi_device_node(dev->fwnode)) {
3925 const struct acpi_device_id *acpi_id;
3926
3927 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
3928 if (!acpi_id) {
3929 dev_err(dev, "device is not compatible!\n");
3930 return -ENXIO;
3931 }
3932 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
3933 if (!hr_dev->hw) {
3934 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
3935 return -ENXIO;
3936 }
3937 } else {
3938 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
3939 return -ENXIO;
3940 }
3941
3942 /* get the mapped register base address */
3943 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
3944 if (!res) {
3945 dev_err(dev, "memory resource not found!\n");
3946 return -EINVAL;
3947 }
3948 hr_dev->reg_base = devm_ioremap_resource(dev, res);
3949 if (IS_ERR(hr_dev->reg_base))
3950 return PTR_ERR(hr_dev->reg_base);
3951
3952 /* read the node_guid of IB device from the DT or ACPI */
3953 ret = device_property_read_u8_array(dev, "node-guid",
3954 (u8 *)&hr_dev->ib_dev.node_guid,
3955 GUID_LEN);
3956 if (ret) {
3957 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
3958 return ret;
3959 }
3960
3961 /* get the RoCE associated ethernet ports or netdevices */
3962 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
3963 if (dev_of_node(dev)) {
3964 net_node = of_parse_phandle(dev->of_node, "eth-handle",
3965 i);
3966 if (!net_node)
3967 continue;
3968 pdev = of_find_device_by_node(net_node);
3969 } else if (is_acpi_device_node(dev->fwnode)) {
3970 struct acpi_reference_args args;
3971 struct fwnode_handle *fwnode;
3972
3973 ret = acpi_node_get_property_reference(dev->fwnode,
3974 "eth-handle",
3975 i, &args);
3976 if (ret)
3977 continue;
3978 fwnode = acpi_fwnode_handle(args.adev);
3979 pdev = hns_roce_find_pdev(fwnode);
3980 } else {
3981 dev_err(dev, "cannot read data from DT or ACPI\n");
3982 return -ENXIO;
3983 }
3984
3985 if (pdev) {
3986 netdev = platform_get_drvdata(pdev);
3987 phy_port = (u8)i;
3988 if (netdev) {
3989 hr_dev->iboe.netdevs[port_cnt] = netdev;
3990 hr_dev->iboe.phy_port[port_cnt] = phy_port;
3991 } else {
3992 dev_err(dev, "no netdev found with pdev %s\n",
3993 pdev->name);
3994 return -ENODEV;
3995 }
3996 port_cnt++;
3997 }
3998 }
3999
4000 if (port_cnt == 0) {
4001 dev_err(dev, "unable to get eth-handle for available ports!\n");
4002 return -EINVAL;
4003 }
4004
4005 hr_dev->caps.num_ports = port_cnt;
4006
4007 /* cmd issue mode: 0 is poll, 1 is event */
4008 hr_dev->cmd_mod = 1;
4009 hr_dev->loop_idc = 0;
4010
4011 /* read the interrupt names from the DT or ACPI */
4012 ret = device_property_read_string_array(dev, "interrupt-names",
4013 hr_dev->irq_names,
4014 HNS_ROCE_MAX_IRQ_NUM);
4015 if (ret < 0) {
4016 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4017 return ret;
4018 }
4019
4020 /* fetch the interrupt numbers */
4021 for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
4022 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4023 if (hr_dev->irq[i] <= 0) {
4024 dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4025 return -EINVAL;
4026 }
4027 }
4028
4029 return 0;
4030}
4031
4032/**
4033 * hns_roce_probe - RoCE driver entrance
4034 * @pdev: pointer to platform device
4035 * Return : int
4036 *
4037 */
4038static int hns_roce_probe(struct platform_device *pdev)
4039{
4040 int ret;
4041 struct hns_roce_dev *hr_dev;
4042 struct device *dev = &pdev->dev;
4043
4044 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
4045 if (!hr_dev)
4046 return -ENOMEM;
4047
016a0059
WHX		 4048 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4049 if (!hr_dev->priv) {
4050 ret = -ENOMEM;
4051 goto error_failed_kzalloc;
4052 }
4053
08805fdb 4054 hr_dev->pdev = pdev;
13ca970e 4055 hr_dev->dev = dev;
08805fdb
WHX		 4056 platform_set_drvdata(pdev, hr_dev);
4057
4058 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4059 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4060 dev_err(dev, "Not usable DMA addressing mode\n");
4061 ret = -EIO;
4062 goto error_failed_get_cfg;
4063 }
4064
4065 ret = hns_roce_get_cfg(hr_dev);
4066 if (ret) {
4067 dev_err(dev, "Get Configuration failed!\n");
4068 goto error_failed_get_cfg;
4069 }
4070
4071 ret = hns_roce_init(hr_dev);
4072 if (ret) {
4073 dev_err(dev, "RoCE engine init failed!\n");
4074 goto error_failed_get_cfg;
4075 }
4076
4077 return 0;
4078
4079error_failed_get_cfg:
016a0059
WHX		 4080 kfree(hr_dev->priv);
4081
4082error_failed_kzalloc:
08805fdb
WHX		 4083 ib_dealloc_device(&hr_dev->ib_dev);
4084
4085 return ret;
4086}
4087
4088/**
4089 * hns_roce_remove - remove RoCE device
4090 * @pdev: pointer to platform device
4091 */
4092static int hns_roce_remove(struct platform_device *pdev)
4093{
4094 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4095
4096 hns_roce_exit(hr_dev);
016a0059 4097 kfree(hr_dev->priv);
08805fdb
WHX		 4098 ib_dealloc_device(&hr_dev->ib_dev);
4099
4100 return 0;
4101}
4102
4103static struct platform_driver hns_roce_driver = {
4104 .probe = hns_roce_probe,
4105 .remove = hns_roce_remove,
4106 .driver = {
4107 .name = DRV_NAME,
4108 .of_match_table = hns_roce_of_match,
4109 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4110 },
4111};
4112
4113module_platform_driver(hns_roce_driver);
4114
4115MODULE_LICENSE("Dual BSD/GPL");
4116MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4117MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4118MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4119MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)