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RDMA/hns: Configure BT BA and BT attribute for the contexts in hip08
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v1.c
CommitLineData
9a443537 1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/platform_device.h>
528f1deb 34#include <linux/acpi.h>
543bfe6c 35#include <linux/etherdevice.h>
cd6ce4a5 36#include <linux/of.h>
08805fdb 37#include <linux/of_platform.h>
9a443537 38#include <rdma/ib_umem.h>
39#include "hns_roce_common.h"
40#include "hns_roce_device.h"
41#include "hns_roce_cmd.h"
42#include "hns_roce_hem.h"
43#include "hns_roce_hw_v1.h"
44
45static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
46{
47 dseg->lkey = cpu_to_le32(sg->lkey);
48 dseg->addr = cpu_to_le64(sg->addr);
49 dseg->len = cpu_to_le32(sg->length);
50}
51
52static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
53 u32 rkey)
54{
55 rseg->raddr = cpu_to_le64(remote_addr);
56 rseg->rkey = cpu_to_le32(rkey);
57 rseg->len = 0;
58}
59
60int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
61 struct ib_send_wr **bad_wr)
62{
63 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
64 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
65 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
66 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
67 struct hns_roce_wqe_data_seg *dseg = NULL;
68 struct hns_roce_qp *qp = to_hr_qp(ibqp);
69 struct device *dev = &hr_dev->pdev->dev;
70 struct hns_roce_sq_db sq_db;
71 int ps_opcode = 0, i = 0;
72 unsigned long flags = 0;
73 void *wqe = NULL;
74 u32 doorbell[2];
75 int nreq = 0;
76 u32 ind = 0;
77 int ret = 0;
543bfe6c
LO		 78 u8 *smac;
79 int loopback;
9a443537 80
07182fa7
LO		 81 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
82 ibqp->qp_type != IB_QPT_RC)) {
83 dev_err(dev, "un-supported QP type\n");
84 *bad_wr = NULL;
85 return -EOPNOTSUPP;
86 }
9a443537 87
07182fa7 88 spin_lock_irqsave(&qp->sq.lock, flags);
9a443537 89 ind = qp->sq_next_wqe;
90 for (nreq = 0; wr; ++nreq, wr = wr->next) {
91 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
92 ret = -ENOMEM;
93 *bad_wr = wr;
94 goto out;
95 }
96
97 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
98 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
99 wr->num_sge, qp->sq.max_gs);
100 ret = -EINVAL;
101 *bad_wr = wr;
102 goto out;
103 }
104
105 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
106 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
107 wr->wr_id;
108
109 /* Corresponding to the RC and RD type wqe process separately */
110 if (ibqp->qp_type == IB_QPT_GSI) {
111 ud_sq_wqe = wqe;
112 roce_set_field(ud_sq_wqe->dmac_h,
113 UD_SEND_WQE_U32_4_DMAC_0_M,
114 UD_SEND_WQE_U32_4_DMAC_0_S,
115 ah->av.mac[0]);
116 roce_set_field(ud_sq_wqe->dmac_h,
117 UD_SEND_WQE_U32_4_DMAC_1_M,
118 UD_SEND_WQE_U32_4_DMAC_1_S,
119 ah->av.mac[1]);
120 roce_set_field(ud_sq_wqe->dmac_h,
121 UD_SEND_WQE_U32_4_DMAC_2_M,
122 UD_SEND_WQE_U32_4_DMAC_2_S,
123 ah->av.mac[2]);
124 roce_set_field(ud_sq_wqe->dmac_h,
125 UD_SEND_WQE_U32_4_DMAC_3_M,
126 UD_SEND_WQE_U32_4_DMAC_3_S,
127 ah->av.mac[3]);
128
129 roce_set_field(ud_sq_wqe->u32_8,
130 UD_SEND_WQE_U32_8_DMAC_4_M,
131 UD_SEND_WQE_U32_8_DMAC_4_S,
132 ah->av.mac[4]);
133 roce_set_field(ud_sq_wqe->u32_8,
134 UD_SEND_WQE_U32_8_DMAC_5_M,
135 UD_SEND_WQE_U32_8_DMAC_5_S,
136 ah->av.mac[5]);
543bfe6c
LO		 137
138 smac = (u8 *)hr_dev->dev_addr[qp->port];
139 loopback = ether_addr_equal_unaligned(ah->av.mac,
140 smac) ? 1 : 0;
141 roce_set_bit(ud_sq_wqe->u32_8,
142 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
143 loopback);
144
9a443537 145 roce_set_field(ud_sq_wqe->u32_8,
146 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
147 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
148 HNS_ROCE_WQE_OPCODE_SEND);
149 roce_set_field(ud_sq_wqe->u32_8,
150 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
151 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
152 2);
153 roce_set_bit(ud_sq_wqe->u32_8,
154 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
155 1);
156
157 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
158 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
159 (wr->send_flags & IB_SEND_SOLICITED ?
160 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
161 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
162 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
163
164 roce_set_field(ud_sq_wqe->u32_16,
165 UD_SEND_WQE_U32_16_DEST_QP_M,
166 UD_SEND_WQE_U32_16_DEST_QP_S,
167 ud_wr(wr)->remote_qpn);
168 roce_set_field(ud_sq_wqe->u32_16,
169 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
170 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
171 ah->av.stat_rate);
172
173 roce_set_field(ud_sq_wqe->u32_36,
174 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
175 UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0);
176 roce_set_field(ud_sq_wqe->u32_36,
177 UD_SEND_WQE_U32_36_PRIORITY_M,
178 UD_SEND_WQE_U32_36_PRIORITY_S,
179 ah->av.sl_tclass_flowlabel >>
180 HNS_ROCE_SL_SHIFT);
181 roce_set_field(ud_sq_wqe->u32_36,
182 UD_SEND_WQE_U32_36_SGID_INDEX_M,
183 UD_SEND_WQE_U32_36_SGID_INDEX_S,
7716809e 184 hns_get_gid_index(hr_dev, qp->phy_port,
9a443537 185 ah->av.gid_index));
186
187 roce_set_field(ud_sq_wqe->u32_40,
188 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
189 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
190 ah->av.hop_limit);
191 roce_set_field(ud_sq_wqe->u32_40,
192 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
193 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S, 0);
194
195 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
196
197 ud_sq_wqe->va0_l = (u32)wr->sg_list[0].addr;
198 ud_sq_wqe->va0_h = (wr->sg_list[0].addr) >> 32;
199 ud_sq_wqe->l_key0 = wr->sg_list[0].lkey;
200
201 ud_sq_wqe->va1_l = (u32)wr->sg_list[1].addr;
202 ud_sq_wqe->va1_h = (wr->sg_list[1].addr) >> 32;
203 ud_sq_wqe->l_key1 = wr->sg_list[1].lkey;
204 ind++;
205 } else if (ibqp->qp_type == IB_QPT_RC) {
206 ctrl = wqe;
207 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
208 for (i = 0; i < wr->num_sge; i++)
209 ctrl->msg_length += wr->sg_list[i].length;
210
211 ctrl->sgl_pa_h = 0;
212 ctrl->flag = 0;
213 ctrl->imm_data = send_ieth(wr);
214
215 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
216 /* SO wait for conforming application scenarios */
217 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
218 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
219 (wr->send_flags & IB_SEND_SOLICITED ?
220 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
221 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
222 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
223 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
224 (wr->send_flags & IB_SEND_FENCE ?
225 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
226
c24bf895 227 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
9a443537 228
229 switch (wr->opcode) {
230 case IB_WR_RDMA_READ:
231 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
9de61d3f 232 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
233 rdma_wr(wr)->rkey);
9a443537 234 break;
235 case IB_WR_RDMA_WRITE:
236 case IB_WR_RDMA_WRITE_WITH_IMM:
237 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
9de61d3f 238 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
239 rdma_wr(wr)->rkey);
9a443537 240 break;
241 case IB_WR_SEND:
242 case IB_WR_SEND_WITH_INV:
243 case IB_WR_SEND_WITH_IMM:
244 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
245 break;
246 case IB_WR_LOCAL_INV:
247 break;
248 case IB_WR_ATOMIC_CMP_AND_SWP:
249 case IB_WR_ATOMIC_FETCH_AND_ADD:
250 case IB_WR_LSO:
251 default:
252 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
253 break;
254 }
255 ctrl->flag |= cpu_to_le32(ps_opcode);
c24bf895 256 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
9a443537 257
258 dseg = wqe;
259 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
260 if (ctrl->msg_length >
261 hr_dev->caps.max_sq_inline) {
262 ret = -EINVAL;
263 *bad_wr = wr;
264 dev_err(dev, "inline len(1-%d)=%d, illegal",
265 ctrl->msg_length,
266 hr_dev->caps.max_sq_inline);
267 goto out;
268 }
269 for (i = 0; i < wr->num_sge; i++) {
270 memcpy(wqe, ((void *) (uintptr_t)
271 wr->sg_list[i].addr),
272 wr->sg_list[i].length);
c24bf895 273 wqe += wr->sg_list[i].length;
9a443537 274 }
275 ctrl->flag |= HNS_ROCE_WQE_INLINE;
276 } else {
277 /*sqe num is two */
278 for (i = 0; i < wr->num_sge; i++)
279 set_data_seg(dseg + i, wr->sg_list + i);
280
281 ctrl->flag |= cpu_to_le32(wr->num_sge <<
282 HNS_ROCE_WQE_SGE_NUM_BIT);
283 }
284 ind++;
9a443537 285 }
286 }
287
288out:
289 /* Set DB return */
290 if (likely(nreq)) {
291 qp->sq.head += nreq;
292 /* Memory barrier */
293 wmb();
294
295 sq_db.u32_4 = 0;
296 sq_db.u32_8 = 0;
297 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
298 SQ_DOORBELL_U32_4_SQ_HEAD_S,
299 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
bfcc681b
SX		 300 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
301 SQ_DOORBELL_U32_4_SL_S, qp->sl);
9a443537 302 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
7716809e 303 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
9a443537 304 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
305 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
306 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
307
308 doorbell[0] = sq_db.u32_4;
309 doorbell[1] = sq_db.u32_8;
310
311 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
312 qp->sq_next_wqe = ind;
313 }
314
315 spin_unlock_irqrestore(&qp->sq.lock, flags);
316
317 return ret;
318}
319
320int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
321 struct ib_recv_wr **bad_wr)
322{
323 int ret = 0;
324 int nreq = 0;
325 int ind = 0;
326 int i = 0;
327 u32 reg_val = 0;
328 unsigned long flags = 0;
329 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
330 struct hns_roce_wqe_data_seg *scat = NULL;
331 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
332 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
333 struct device *dev = &hr_dev->pdev->dev;
334 struct hns_roce_rq_db rq_db;
335 uint32_t doorbell[2] = {0};
336
337 spin_lock_irqsave(&hr_qp->rq.lock, flags);
338 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
339
340 for (nreq = 0; wr; ++nreq, wr = wr->next) {
341 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
342 hr_qp->ibqp.recv_cq)) {
343 ret = -ENOMEM;
344 *bad_wr = wr;
345 goto out;
346 }
347
348 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
349 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
350 wr->num_sge, hr_qp->rq.max_gs);
351 ret = -EINVAL;
352 *bad_wr = wr;
353 goto out;
354 }
355
356 ctrl = get_recv_wqe(hr_qp, ind);
357
358 roce_set_field(ctrl->rwqe_byte_12,
359 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
360 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
361 wr->num_sge);
362
363 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
364
365 for (i = 0; i < wr->num_sge; i++)
366 set_data_seg(scat + i, wr->sg_list + i);
367
368 hr_qp->rq.wrid[ind] = wr->wr_id;
369
370 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
371 }
372
373out:
374 if (likely(nreq)) {
375 hr_qp->rq.head += nreq;
376 /* Memory barrier */
377 wmb();
378
379 if (ibqp->qp_type == IB_QPT_GSI) {
380 /* SW update GSI rq header */
381 reg_val = roce_read(to_hr_dev(ibqp->device),
382 ROCEE_QP1C_CFG3_0_REG +
7716809e 383 QP1C_CFGN_OFFSET * hr_qp->phy_port);
9a443537 384 roce_set_field(reg_val,
385 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
386 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
387 hr_qp->rq.head);
388 roce_write(to_hr_dev(ibqp->device),
389 ROCEE_QP1C_CFG3_0_REG +
7716809e 390 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
9a443537 391 } else {
392 rq_db.u32_4 = 0;
393 rq_db.u32_8 = 0;
394
395 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
396 RQ_DOORBELL_U32_4_RQ_HEAD_S,
397 hr_qp->rq.head);
398 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
399 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
400 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
401 RQ_DOORBELL_U32_8_CMD_S, 1);
402 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
403 1);
404
405 doorbell[0] = rq_db.u32_4;
406 doorbell[1] = rq_db.u32_8;
407
408 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
409 }
410 }
411 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
412
413 return ret;
414}
415
416static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
417 int sdb_mode, int odb_mode)
418{
419 u32 val;
420
421 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
422 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
423 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
424 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
425}
426
427static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
428 u32 odb_mode)
429{
430 u32 val;
431
432 /* Configure SDB/ODB extend mode */
433 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
434 roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
435 roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
436 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
437}
438
439static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
440 u32 sdb_alful)
441{
442 u32 val;
443
444 /* Configure SDB */
445 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
446 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
447 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
448 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
449 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
450 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
451}
452
453static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
454 u32 odb_alful)
455{
456 u32 val;
457
458 /* Configure ODB */
459 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
460 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
461 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
462 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
463 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
464 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
465}
466
467static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
468 u32 ext_sdb_alful)
469{
470 struct device *dev = &hr_dev->pdev->dev;
471 struct hns_roce_v1_priv *priv;
472 struct hns_roce_db_table *db;
473 dma_addr_t sdb_dma_addr;
474 u32 val;
475
016a0059 476 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 477 db = &priv->db_table;
478
479 /* Configure extend SDB threshold */
480 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
481 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
482
483 /* Configure extend SDB base addr */
484 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
485 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
486
487 /* Configure extend SDB depth */
488 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
489 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
490 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
491 db->ext_db->esdb_dep);
492 /*
493 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
494 * using 4K page, and shift more 32 because of
495 * caculating the high 32 bit value evaluated to hardware.
496 */
497 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
498 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
499 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
500
501 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
502 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
503 ext_sdb_alept, ext_sdb_alful);
504}
505
506static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
507 u32 ext_odb_alful)
508{
509 struct device *dev = &hr_dev->pdev->dev;
510 struct hns_roce_v1_priv *priv;
511 struct hns_roce_db_table *db;
512 dma_addr_t odb_dma_addr;
513 u32 val;
514
016a0059 515 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 516 db = &priv->db_table;
517
518 /* Configure extend ODB threshold */
519 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
520 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
521
522 /* Configure extend ODB base addr */
523 odb_dma_addr = db->ext_db->odb_buf_list->map;
524 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
525
526 /* Configure extend ODB depth */
527 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
528 roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
529 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
530 db->ext_db->eodb_dep);
531 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
532 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
533 db->ext_db->eodb_dep);
534 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
535
536 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
537 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
538 ext_odb_alept, ext_odb_alful);
539}
540
541static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
542 u32 odb_ext_mod)
543{
544 struct device *dev = &hr_dev->pdev->dev;
545 struct hns_roce_v1_priv *priv;
546 struct hns_roce_db_table *db;
547 dma_addr_t sdb_dma_addr;
548 dma_addr_t odb_dma_addr;
549 int ret = 0;
550
016a0059 551 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 552 db = &priv->db_table;
553
554 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
555 if (!db->ext_db)
556 return -ENOMEM;
557
558 if (sdb_ext_mod) {
559 db->ext_db->sdb_buf_list = kmalloc(
560 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
561 if (!db->ext_db->sdb_buf_list) {
562 ret = -ENOMEM;
563 goto ext_sdb_buf_fail_out;
564 }
565
566 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
567 HNS_ROCE_V1_EXT_SDB_SIZE,
568 &sdb_dma_addr, GFP_KERNEL);
569 if (!db->ext_db->sdb_buf_list->buf) {
570 ret = -ENOMEM;
571 goto alloc_sq_db_buf_fail;
572 }
573 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
574
575 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
576 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
577 HNS_ROCE_V1_EXT_SDB_ALFUL);
578 } else
579 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
580 HNS_ROCE_V1_SDB_ALFUL);
581
582 if (odb_ext_mod) {
583 db->ext_db->odb_buf_list = kmalloc(
584 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
585 if (!db->ext_db->odb_buf_list) {
586 ret = -ENOMEM;
587 goto ext_odb_buf_fail_out;
588 }
589
590 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
591 HNS_ROCE_V1_EXT_ODB_SIZE,
592 &odb_dma_addr, GFP_KERNEL);
593 if (!db->ext_db->odb_buf_list->buf) {
594 ret = -ENOMEM;
595 goto alloc_otr_db_buf_fail;
596 }
597 db->ext_db->odb_buf_list->map = odb_dma_addr;
598
599 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
600 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
601 HNS_ROCE_V1_EXT_ODB_ALFUL);
602 } else
603 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
604 HNS_ROCE_V1_ODB_ALFUL);
605
606 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
607
608 return 0;
609
610alloc_otr_db_buf_fail:
611 kfree(db->ext_db->odb_buf_list);
612
613ext_odb_buf_fail_out:
614 if (sdb_ext_mod) {
615 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
616 db->ext_db->sdb_buf_list->buf,
617 db->ext_db->sdb_buf_list->map);
618 }
619
620alloc_sq_db_buf_fail:
621 if (sdb_ext_mod)
622 kfree(db->ext_db->sdb_buf_list);
623
624ext_sdb_buf_fail_out:
625 kfree(db->ext_db);
626 return ret;
627}
628
bfcc681b
SX		 629static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
630 struct ib_pd *pd)
631{
632 struct device *dev = &hr_dev->pdev->dev;
633 struct ib_qp_init_attr init_attr;
634 struct ib_qp *qp;
635
636 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
637 init_attr.qp_type = IB_QPT_RC;
638 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
639 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
640 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
641
642 qp = hns_roce_create_qp(pd, &init_attr, NULL);
643 if (IS_ERR(qp)) {
644 dev_err(dev, "Create loop qp for mr free failed!");
645 return NULL;
646 }
647
648 return to_hr_qp(qp);
649}
650
651static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
652{
653 struct hns_roce_caps *caps = &hr_dev->caps;
654 struct device *dev = &hr_dev->pdev->dev;
655 struct ib_cq_init_attr cq_init_attr;
656 struct hns_roce_free_mr *free_mr;
657 struct ib_qp_attr attr = { 0 };
658 struct hns_roce_v1_priv *priv;
659 struct hns_roce_qp *hr_qp;
660 struct ib_cq *cq;
661 struct ib_pd *pd;
d8966fcd 662 union ib_gid dgid;
bfcc681b
SX		 663 u64 subnet_prefix;
664 int attr_mask = 0;
5802883d 665 int i, j;
bfcc681b 666 int ret;
5802883d 667 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
bfcc681b 668 u8 phy_port;
5802883d 669 u8 port = 0;
bfcc681b
SX		 670 u8 sl;
671
016a0059 672 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 673 free_mr = &priv->free_mr;
674
675 /* Reserved cq for loop qp */
676 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
677 cq_init_attr.comp_vector = 0;
678 cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
679 if (IS_ERR(cq)) {
680 dev_err(dev, "Create cq for reseved loop qp failed!");
681 return -ENOMEM;
682 }
683 free_mr->mr_free_cq = to_hr_cq(cq);
684 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
685 free_mr->mr_free_cq->ib_cq.uobject = NULL;
686 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
687 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
688 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
689 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
690
691 pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
692 if (IS_ERR(pd)) {
693 dev_err(dev, "Create pd for reseved loop qp failed!");
694 ret = -ENOMEM;
695 goto alloc_pd_failed;
696 }
697 free_mr->mr_free_pd = to_hr_pd(pd);
698 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
699 free_mr->mr_free_pd->ibpd.uobject = NULL;
700 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
701
702 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
703 attr.pkey_index = 0;
704 attr.min_rnr_timer = 0;
705 /* Disable read ability */
706 attr.max_dest_rd_atomic = 0;
707 attr.max_rd_atomic = 0;
708 /* Use arbitrary values as rq_psn and sq_psn */
709 attr.rq_psn = 0x0808;
710 attr.sq_psn = 0x0808;
711 attr.retry_cnt = 7;
712 attr.rnr_retry = 7;
713 attr.timeout = 0x12;
714 attr.path_mtu = IB_MTU_256;
5802883d 715 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
d8966fcd
DC		 716 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
717 rdma_ah_set_static_rate(&attr.ah_attr, 3);
bfcc681b
SX		 718
719 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
720 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
5802883d 721 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
722 (i % HNS_ROCE_MAX_PORTS);
723 sl = i / HNS_ROCE_MAX_PORTS;
724
725 for (j = 0; j < caps->num_ports; j++) {
726 if (hr_dev->iboe.phy_port[j] == phy_port) {
727 queue_en[i] = 1;
728 port = j;
729 break;
730 }
731 }
732
733 if (!queue_en[i])
734 continue;
735
bfcc681b 736 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
5db465f2 737 if (!free_mr->mr_free_qp[i]) {
bfcc681b
SX		 738 dev_err(dev, "Create loop qp failed!\n");
739 goto create_lp_qp_failed;
740 }
741 hr_qp = free_mr->mr_free_qp[i];
742
5802883d 743 hr_qp->port = port;
bfcc681b
SX		 744 hr_qp->phy_port = phy_port;
745 hr_qp->ibqp.qp_type = IB_QPT_RC;
746 hr_qp->ibqp.device = &hr_dev->ib_dev;
747 hr_qp->ibqp.uobject = NULL;
748 atomic_set(&hr_qp->ibqp.usecnt, 0);
749 hr_qp->ibqp.pd = pd;
750 hr_qp->ibqp.recv_cq = cq;
751 hr_qp->ibqp.send_cq = cq;
752
5802883d 753 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
754 rdma_ah_set_sl(&attr.ah_attr, sl);
755 attr.port_num = port + 1;
bfcc681b
SX		 756
757 attr.dest_qp_num = hr_qp->qpn;
d8966fcd 758 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
5802883d 759 hr_dev->dev_addr[port],
bfcc681b
SX		 760 MAC_ADDR_OCTET_NUM);
761
d8966fcd 762 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
5802883d 763 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
764 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
d8966fcd
DC		 765 dgid.raw[11] = 0xff;
766 dgid.raw[12] = 0xfe;
767 dgid.raw[8] ^= 2;
768 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
bfcc681b
SX		 769
770 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
771 IB_QPS_RESET, IB_QPS_INIT);
772 if (ret) {
773 dev_err(dev, "modify qp failed(%d)!\n", ret);
774 goto create_lp_qp_failed;
775 }
776
777 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
778 IB_QPS_INIT, IB_QPS_RTR);
779 if (ret) {
780 dev_err(dev, "modify qp failed(%d)!\n", ret);
781 goto create_lp_qp_failed;
782 }
783
784 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
785 IB_QPS_RTR, IB_QPS_RTS);
786 if (ret) {
787 dev_err(dev, "modify qp failed(%d)!\n", ret);
788 goto create_lp_qp_failed;
789 }
790 }
791
792 return 0;
793
794create_lp_qp_failed:
795 for (i -= 1; i >= 0; i--) {
796 hr_qp = free_mr->mr_free_qp[i];
797 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
798 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
799 }
800
801 if (hns_roce_dealloc_pd(pd))
802 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
803
804alloc_pd_failed:
805 if (hns_roce_ib_destroy_cq(cq))
806 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
807
808 return -EINVAL;
809}
810
811static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
812{
813 struct device *dev = &hr_dev->pdev->dev;
814 struct hns_roce_free_mr *free_mr;
815 struct hns_roce_v1_priv *priv;
816 struct hns_roce_qp *hr_qp;
817 int ret;
818 int i;
819
016a0059 820 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 821 free_mr = &priv->free_mr;
822
823 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
824 hr_qp = free_mr->mr_free_qp[i];
5802883d 825 if (!hr_qp)
826 continue;
827
bfcc681b
SX		 828 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
829 if (ret)
830 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
831 i, ret);
832 }
833
834 ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
835 if (ret)
836 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
837
838 ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
839 if (ret)
840 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
841}
842
9a443537 843static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
844{
845 struct device *dev = &hr_dev->pdev->dev;
846 struct hns_roce_v1_priv *priv;
847 struct hns_roce_db_table *db;
848 u32 sdb_ext_mod;
849 u32 odb_ext_mod;
850 u32 sdb_evt_mod;
851 u32 odb_evt_mod;
852 int ret = 0;
853
016a0059 854 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 855 db = &priv->db_table;
856
857 memset(db, 0, sizeof(*db));
858
859 /* Default DB mode */
860 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
861 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
862 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
863 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
864
865 db->sdb_ext_mod = sdb_ext_mod;
866 db->odb_ext_mod = odb_ext_mod;
867
868 /* Init extend DB */
869 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
870 if (ret) {
871 dev_err(dev, "Failed in extend DB configuration.\n");
872 return ret;
873 }
874
875 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
876
877 return 0;
878}
879
bfcc681b
SX		 880void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
881{
882 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
883 struct hns_roce_dev *hr_dev;
884
885 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
886 work);
887 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
888
889 hns_roce_v1_release_lp_qp(hr_dev);
890
891 if (hns_roce_v1_rsv_lp_qp(hr_dev))
892 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
893
894 if (lp_qp_work->comp_flag)
895 complete(lp_qp_work->comp);
896
897 kfree(lp_qp_work);
898}
899
900static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
901{
902 struct device *dev = &hr_dev->pdev->dev;
903 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
904 struct hns_roce_free_mr *free_mr;
905 struct hns_roce_v1_priv *priv;
906 struct completion comp;
907 unsigned long end =
908 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
909
016a0059 910 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 911 free_mr = &priv->free_mr;
912
913 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
914 GFP_KERNEL);
915
916 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
917
918 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
919 lp_qp_work->comp = &comp;
920 lp_qp_work->comp_flag = 1;
921
922 init_completion(lp_qp_work->comp);
923
924 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
925
926 while (time_before_eq(jiffies, end)) {
927 if (try_wait_for_completion(&comp))
928 return 0;
929 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
930 }
931
932 lp_qp_work->comp_flag = 0;
933 if (try_wait_for_completion(&comp))
934 return 0;
935
936 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
937 return -ETIMEDOUT;
938}
939
940static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
941{
942 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
943 struct device *dev = &hr_dev->pdev->dev;
944 struct ib_send_wr send_wr, *bad_wr;
945 int ret;
946
947 memset(&send_wr, 0, sizeof(send_wr));
948 send_wr.next = NULL;
949 send_wr.num_sge = 0;
950 send_wr.send_flags = 0;
951 send_wr.sg_list = NULL;
952 send_wr.wr_id = (unsigned long long)&send_wr;
953 send_wr.opcode = IB_WR_RDMA_WRITE;
954
955 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
956 if (ret) {
957 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
958 return ret;
959 }
960
961 return 0;
962}
963
964static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
965{
966 struct hns_roce_mr_free_work *mr_work;
967 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
968 struct hns_roce_free_mr *free_mr;
969 struct hns_roce_cq *mr_free_cq;
970 struct hns_roce_v1_priv *priv;
971 struct hns_roce_dev *hr_dev;
972 struct hns_roce_mr *hr_mr;
973 struct hns_roce_qp *hr_qp;
974 struct device *dev;
975 unsigned long end =
976 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
977 int i;
978 int ret;
5802883d 979 int ne = 0;
bfcc681b
SX		 980
981 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
982 hr_mr = (struct hns_roce_mr *)mr_work->mr;
983 hr_dev = to_hr_dev(mr_work->ib_dev);
984 dev = &hr_dev->pdev->dev;
985
016a0059 986 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 987 free_mr = &priv->free_mr;
988 mr_free_cq = free_mr->mr_free_cq;
989
990 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
991 hr_qp = free_mr->mr_free_qp[i];
5802883d 992 if (!hr_qp)
993 continue;
994 ne++;
995
bfcc681b
SX		 996 ret = hns_roce_v1_send_lp_wqe(hr_qp);
997 if (ret) {
998 dev_err(dev,
999 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1000 hr_qp->qpn, ret);
1001 goto free_work;
1002 }
1003 }
1004
bfcc681b
SX		 1005 do {
1006 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1007 if (ret < 0) {
1008 dev_err(dev,
1009 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1010 hr_qp->qpn, ret, hr_mr->key, ne);
1011 goto free_work;
1012 }
1013 ne -= ret;
98e77d9f
LR		 1014 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1015 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
bfcc681b
SX		 1016 } while (ne && time_before_eq(jiffies, end));
1017
1018 if (ne != 0)
1019 dev_err(dev,
1020 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1021 hr_mr->key, ne);
1022
1023free_work:
1024 if (mr_work->comp_flag)
1025 complete(mr_work->comp);
1026 kfree(mr_work);
1027}
1028
1029int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
1030{
1031 struct device *dev = &hr_dev->pdev->dev;
1032 struct hns_roce_mr_free_work *mr_work;
1033 struct hns_roce_free_mr *free_mr;
1034 struct hns_roce_v1_priv *priv;
1035 struct completion comp;
1036 unsigned long end =
1037 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1038 unsigned long start = jiffies;
1039 int npages;
1040 int ret = 0;
1041
016a0059 1042 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1043 free_mr = &priv->free_mr;
1044
1045 if (mr->enabled) {
1046 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1047 & (hr_dev->caps.num_mtpts - 1)))
1048 dev_warn(dev, "HW2SW_MPT failed!\n");
1049 }
1050
1051 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1052 if (!mr_work) {
1053 ret = -ENOMEM;
1054 goto free_mr;
1055 }
1056
1057 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1058
1059 mr_work->ib_dev = &(hr_dev->ib_dev);
1060 mr_work->comp = &comp;
1061 mr_work->comp_flag = 1;
1062 mr_work->mr = (void *)mr;
1063 init_completion(mr_work->comp);
1064
1065 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1066
1067 while (time_before_eq(jiffies, end)) {
1068 if (try_wait_for_completion(&comp))
1069 goto free_mr;
1070 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1071 }
1072
1073 mr_work->comp_flag = 0;
1074 if (try_wait_for_completion(&comp))
1075 goto free_mr;
1076
1077 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1078 ret = -ETIMEDOUT;
1079
1080free_mr:
1081 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1082 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1083
1084 if (mr->size != ~0ULL) {
1085 npages = ib_umem_page_count(mr->umem);
1086 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1087 mr->pbl_dma_addr);
1088 }
1089
1090 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1091 key_to_hw_index(mr->key), 0);
1092
1093 if (mr->umem)
1094 ib_umem_release(mr->umem);
1095
1096 kfree(mr);
1097
1098 return ret;
1099}
1100
9a443537 1101static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1102{
1103 struct device *dev = &hr_dev->pdev->dev;
1104 struct hns_roce_v1_priv *priv;
1105 struct hns_roce_db_table *db;
1106
016a0059 1107 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1108 db = &priv->db_table;
1109
1110 if (db->sdb_ext_mod) {
1111 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1112 db->ext_db->sdb_buf_list->buf,
1113 db->ext_db->sdb_buf_list->map);
1114 kfree(db->ext_db->sdb_buf_list);
1115 }
1116
1117 if (db->odb_ext_mod) {
1118 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1119 db->ext_db->odb_buf_list->buf,
1120 db->ext_db->odb_buf_list->map);
1121 kfree(db->ext_db->odb_buf_list);
1122 }
1123
1124 kfree(db->ext_db);
1125}
1126
1127static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1128{
1129 int ret;
1130 int raq_shift = 0;
1131 dma_addr_t addr;
1132 u32 val;
1133 struct hns_roce_v1_priv *priv;
1134 struct hns_roce_raq_table *raq;
1135 struct device *dev = &hr_dev->pdev->dev;
1136
016a0059 1137 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1138 raq = &priv->raq_table;
1139
1140 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1141 if (!raq->e_raq_buf)
1142 return -ENOMEM;
1143
1144 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1145 &addr, GFP_KERNEL);
1146 if (!raq->e_raq_buf->buf) {
1147 ret = -ENOMEM;
1148 goto err_dma_alloc_raq;
1149 }
1150 raq->e_raq_buf->map = addr;
1151
1152 /* Configure raq extended address. 48bit 4K align*/
1153 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1154
1155 /* Configure raq_shift */
1156 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1157 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1158 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1159 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1160 /*
1161 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1162 * using 4K page, and shift more 32 because of
1163 * caculating the high 32 bit value evaluated to hardware.
1164 */
1165 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1166 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1167 raq->e_raq_buf->map >> 44);
1168 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1169 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1170
1171 /* Configure raq threshold */
1172 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1173 roce_set_field(val, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1174 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1175 HNS_ROCE_V1_EXT_RAQ_WF);
1176 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1177 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1178
1179 /* Enable extend raq */
1180 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1181 roce_set_field(val,
1182 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1183 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1184 POL_TIME_INTERVAL_VAL);
1185 roce_set_bit(val, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1186 roce_set_field(val,
1187 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1188 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1189 2);
1190 roce_set_bit(val,
1191 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1192 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1193 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1194
1195 /* Enable raq drop */
1196 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1197 roce_set_bit(val, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1198 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1199 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1200
1201 return 0;
1202
1203err_dma_alloc_raq:
1204 kfree(raq->e_raq_buf);
1205 return ret;
1206}
1207
1208static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1209{
1210 struct device *dev = &hr_dev->pdev->dev;
1211 struct hns_roce_v1_priv *priv;
1212 struct hns_roce_raq_table *raq;
1213
016a0059 1214 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1215 raq = &priv->raq_table;
1216
1217 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1218 raq->e_raq_buf->map);
1219 kfree(raq->e_raq_buf);
1220}
1221
1222static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1223{
1224 u32 val;
1225
1226 if (enable_flag) {
1227 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1228 /* Open all ports */
1229 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1230 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1231 ALL_PORT_VAL_OPEN);
1232 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1233 } else {
1234 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1235 /* Close all ports */
1236 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1237 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1238 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1239 }
1240}
1241
97f0e39f
WHX		 1242static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1243{
1244 struct device *dev = &hr_dev->pdev->dev;
1245 struct hns_roce_v1_priv *priv;
1246 int ret;
1247
016a0059 1248 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 1249
1250 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1251 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1252 GFP_KERNEL);
1253 if (!priv->bt_table.qpc_buf.buf)
1254 return -ENOMEM;
1255
1256 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1257 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1258 GFP_KERNEL);
1259 if (!priv->bt_table.mtpt_buf.buf) {
1260 ret = -ENOMEM;
1261 goto err_failed_alloc_mtpt_buf;
1262 }
1263
1264 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1265 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1266 GFP_KERNEL);
1267 if (!priv->bt_table.cqc_buf.buf) {
1268 ret = -ENOMEM;
1269 goto err_failed_alloc_cqc_buf;
1270 }
1271
1272 return 0;
1273
1274err_failed_alloc_cqc_buf:
1275 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1276 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1277
1278err_failed_alloc_mtpt_buf:
1279 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1280 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1281
1282 return ret;
1283}
1284
1285static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1286{
1287 struct device *dev = &hr_dev->pdev->dev;
1288 struct hns_roce_v1_priv *priv;
1289
016a0059 1290 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 1291
1292 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1293 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1294
1295 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1296 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1297
1298 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1299 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1300}
1301
8f3e9f3e
WHX		 1302static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1303{
1304 struct device *dev = &hr_dev->pdev->dev;
1305 struct hns_roce_buf_list *tptr_buf;
1306 struct hns_roce_v1_priv *priv;
1307
016a0059 1308 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e
WHX		 1309 tptr_buf = &priv->tptr_table.tptr_buf;
1310
1311 /*
1312 * This buffer will be used for CQ's tptr(tail pointer), also
1313 * named ci(customer index). Every CQ will use 2 bytes to save
1314 * cqe ci in hip06. Hardware will read this area to get new ci
1315 * when the queue is almost full.
1316 */
1317 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1318 &tptr_buf->map, GFP_KERNEL);
1319 if (!tptr_buf->buf)
1320 return -ENOMEM;
1321
1322 hr_dev->tptr_dma_addr = tptr_buf->map;
1323 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1324
1325 return 0;
1326}
1327
1328static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1329{
1330 struct device *dev = &hr_dev->pdev->dev;
1331 struct hns_roce_buf_list *tptr_buf;
1332 struct hns_roce_v1_priv *priv;
1333
016a0059 1334 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e
WHX		 1335 tptr_buf = &priv->tptr_table.tptr_buf;
1336
1337 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1338 tptr_buf->buf, tptr_buf->map);
1339}
1340
bfcc681b
SX		 1341static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1342{
1343 struct device *dev = &hr_dev->pdev->dev;
1344 struct hns_roce_free_mr *free_mr;
1345 struct hns_roce_v1_priv *priv;
1346 int ret = 0;
1347
016a0059 1348 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1349 free_mr = &priv->free_mr;
1350
1351 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1352 if (!free_mr->free_mr_wq) {
1353 dev_err(dev, "Create free mr workqueue failed!\n");
1354 return -ENOMEM;
1355 }
1356
1357 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1358 if (ret) {
1359 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1360 flush_workqueue(free_mr->free_mr_wq);
1361 destroy_workqueue(free_mr->free_mr_wq);
1362 }
1363
1364 return ret;
1365}
1366
1367static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1368{
1369 struct hns_roce_free_mr *free_mr;
1370 struct hns_roce_v1_priv *priv;
1371
016a0059 1372 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1373 free_mr = &priv->free_mr;
1374
1375 flush_workqueue(free_mr->free_mr_wq);
1376 destroy_workqueue(free_mr->free_mr_wq);
1377
1378 hns_roce_v1_release_lp_qp(hr_dev);
1379}
1380
9a443537 1381/**
1382 * hns_roce_v1_reset - reset RoCE
1383 * @hr_dev: RoCE device struct pointer
1384 * @enable: true -- drop reset, false -- reset
1385 * return 0 - success , negative --fail
1386 */
528f1deb 1387int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
9a443537 1388{
1389 struct device_node *dsaf_node;
1390 struct device *dev = &hr_dev->pdev->dev;
1391 struct device_node *np = dev->of_node;
528f1deb 1392 struct fwnode_handle *fwnode;
9a443537 1393 int ret;
1394
528f1deb
S		 1395 /* check if this is DT/ACPI case */
1396 if (dev_of_node(dev)) {
1397 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1398 if (!dsaf_node) {
1399 dev_err(dev, "could not find dsaf-handle\n");
1400 return -EINVAL;
1401 }
1402 fwnode = &dsaf_node->fwnode;
1403 } else if (is_acpi_device_node(dev->fwnode)) {
1404 struct acpi_reference_args args;
1405
1406 ret = acpi_node_get_property_reference(dev->fwnode,
1407 "dsaf-handle", 0, &args);
1408 if (ret) {
1409 dev_err(dev, "could not find dsaf-handle\n");
1410 return ret;
1411 }
1412 fwnode = acpi_fwnode_handle(args.adev);
1413 } else {
1414 dev_err(dev, "cannot read data from DT or ACPI\n");
1415 return -ENXIO;
9a443537 1416 }
1417
528f1deb 1418 ret = hns_dsaf_roce_reset(fwnode, false);
9a443537 1419 if (ret)
1420 return ret;
1421
528f1deb 1422 if (dereset) {
9a443537 1423 msleep(SLEEP_TIME_INTERVAL);
528f1deb 1424 ret = hns_dsaf_roce_reset(fwnode, true);
9a443537 1425 }
1426
528f1deb 1427 return ret;
9a443537 1428}
1429
d838c481
WHX		 1430static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1431{
1432 struct device *dev = &hr_dev->pdev->dev;
1433 struct hns_roce_v1_priv *priv;
1434 struct hns_roce_des_qp *des_qp;
1435
016a0059 1436 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 1437 des_qp = &priv->des_qp;
1438
1439 des_qp->requeue_flag = 1;
1440 des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1441 if (!des_qp->qp_wq) {
1442 dev_err(dev, "Create destroy qp workqueue failed!\n");
1443 return -ENOMEM;
1444 }
1445
1446 return 0;
1447}
1448
1449static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1450{
1451 struct hns_roce_v1_priv *priv;
1452 struct hns_roce_des_qp *des_qp;
1453
016a0059 1454 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 1455 des_qp = &priv->des_qp;
1456
1457 des_qp->requeue_flag = 0;
1458 flush_workqueue(des_qp->qp_wq);
1459 destroy_workqueue(des_qp->qp_wq);
1460}
1461
cfc85f3e 1462int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
9a443537 1463{
1464 int i = 0;
1465 struct hns_roce_caps *caps = &hr_dev->caps;
1466
1467 hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG));
1468 hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev,
1469 ROCEE_VENDOR_PART_ID_REG));
9a443537 1470 hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev,
1471 ROCEE_SYS_IMAGE_GUID_L_REG)) |
1472 ((u64)le32_to_cpu(roce_read(hr_dev,
1473 ROCEE_SYS_IMAGE_GUID_H_REG)) << 32);
8f3e9f3e 1474 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
9a443537 1475
1476 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1477 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1478 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1479 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1480 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1481 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1482 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1483 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1484 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1485 caps->num_aeq_vectors = HNS_ROCE_AEQE_VEC_NUM;
1486 caps->num_comp_vectors = HNS_ROCE_COMP_VEC_NUM;
1487 caps->num_other_vectors = HNS_ROCE_AEQE_OF_VEC_NUM;
1488 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1489 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1490 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1491 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1492 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1493 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1494 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1495 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1496 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1497 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1498 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1499 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1500 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1501 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
9a443537 1502 caps->reserved_lkey = 0;
1503 caps->reserved_pds = 0;
1504 caps->reserved_mrws = 1;
1505 caps->reserved_uars = 0;
1506 caps->reserved_cqs = 0;
1507
1508 for (i = 0; i < caps->num_ports; i++)
1509 caps->pkey_table_len[i] = 1;
1510
1511 for (i = 0; i < caps->num_ports; i++) {
1512 /* Six ports shared 16 GID in v1 engine */
1513 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1514 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1515 caps->num_ports;
1516 else
1517 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1518 caps->num_ports + 1;
1519 }
1520
1521 for (i = 0; i < caps->num_comp_vectors; i++)
1522 caps->ceqe_depth[i] = HNS_ROCE_V1_NUM_COMP_EQE;
1523
1524 caps->aeqe_depth = HNS_ROCE_V1_NUM_ASYNC_EQE;
1525 caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev,
1526 ROCEE_ACK_DELAY_REG));
1527 caps->max_mtu = IB_MTU_2048;
cfc85f3e
WHX		 1528
1529 return 0;
9a443537 1530}
1531
1532int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1533{
1534 int ret;
1535 u32 val;
1536 struct device *dev = &hr_dev->pdev->dev;
1537
1538 /* DMAE user config */
1539 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1540 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1541 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1542 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1543 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1544 1 << PAGES_SHIFT_16);
1545 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1546
1547 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1548 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1549 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1550 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1551 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1552 1 << PAGES_SHIFT_16);
1553
1554 ret = hns_roce_db_init(hr_dev);
1555 if (ret) {
1556 dev_err(dev, "doorbell init failed!\n");
1557 return ret;
1558 }
1559
1560 ret = hns_roce_raq_init(hr_dev);
1561 if (ret) {
1562 dev_err(dev, "raq init failed!\n");
1563 goto error_failed_raq_init;
1564 }
1565
97f0e39f
WHX		 1566 ret = hns_roce_bt_init(hr_dev);
1567 if (ret) {
1568 dev_err(dev, "bt init failed!\n");
1569 goto error_failed_bt_init;
1570 }
1571
8f3e9f3e
WHX		 1572 ret = hns_roce_tptr_init(hr_dev);
1573 if (ret) {
1574 dev_err(dev, "tptr init failed!\n");
1575 goto error_failed_tptr_init;
1576 }
1577
d838c481
WHX		 1578 ret = hns_roce_des_qp_init(hr_dev);
1579 if (ret) {
1580 dev_err(dev, "des qp init failed!\n");
1581 goto error_failed_des_qp_init;
1582 }
1583
bfcc681b
SX		 1584 ret = hns_roce_free_mr_init(hr_dev);
1585 if (ret) {
1586 dev_err(dev, "free mr init failed!\n");
1587 goto error_failed_free_mr_init;
1588 }
1589
d838c481
WHX		 1590 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1591
9a443537 1592 return 0;
1593
bfcc681b
SX		 1594error_failed_free_mr_init:
1595 hns_roce_des_qp_free(hr_dev);
1596
d838c481
WHX		 1597error_failed_des_qp_init:
1598 hns_roce_tptr_free(hr_dev);
1599
8f3e9f3e
WHX		 1600error_failed_tptr_init:
1601 hns_roce_bt_free(hr_dev);
1602
97f0e39f 1603error_failed_bt_init:
97f0e39f
WHX		 1604 hns_roce_raq_free(hr_dev);
1605
9a443537 1606error_failed_raq_init:
1607 hns_roce_db_free(hr_dev);
1608 return ret;
1609}
1610
1611void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1612{
d838c481 1613 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
bfcc681b 1614 hns_roce_free_mr_free(hr_dev);
d838c481 1615 hns_roce_des_qp_free(hr_dev);
8f3e9f3e 1616 hns_roce_tptr_free(hr_dev);
97f0e39f 1617 hns_roce_bt_free(hr_dev);
9a443537 1618 hns_roce_raq_free(hr_dev);
1619 hns_roce_db_free(hr_dev);
1620}
1621
a680f2f3
WHX		 1622static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1623{
1624 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1625
1626 return (!!(status & (1 << HCR_GO_BIT)));
1627}
1628
1629int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1630 u64 out_param, u32 in_modifier, u8 op_modifier,
1631 u16 op, u16 token, int event)
1632{
1633 u32 *hcr = (u32 *)(hr_dev->reg_base + ROCEE_MB1_REG);
1634 unsigned long end;
1635 u32 val = 0;
1636
1637 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1638 while (hns_roce_v1_cmd_pending(hr_dev)) {
1639 if (time_after(jiffies, end)) {
1640 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1641 (int)jiffies, (int)end);
1642 return -EAGAIN;
1643 }
1644 cond_resched();
1645 }
1646
1647 roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1648 op);
1649 roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1650 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1651 roce_set_bit(val, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1652 roce_set_bit(val, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1653 roce_set_field(val, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1654 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1655
1656 __raw_writeq(cpu_to_le64(in_param), hcr + 0);
1657 __raw_writeq(cpu_to_le64(out_param), hcr + 2);
1658 __raw_writel(cpu_to_le32(in_modifier), hcr + 4);
1659 /* Memory barrier */
1660 wmb();
1661
1662 __raw_writel(cpu_to_le32(val), hcr + 5);
1663
1664 mmiowb();
1665
1666 return 0;
1667}
1668
1669static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1670 unsigned long timeout)
1671{
1672 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1673 unsigned long end = 0;
1674 u32 status = 0;
1675
1676 end = msecs_to_jiffies(timeout) + jiffies;
1677 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1678 cond_resched();
1679
1680 if (hns_roce_v1_cmd_pending(hr_dev)) {
1681 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1682 return -ETIMEDOUT;
1683 }
1684
1685 status = le32_to_cpu((__force __be32)
1686 __raw_readl(hcr + HCR_STATUS_OFFSET));
1687 if ((status & STATUS_MASK) != 0x1) {
1688 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1689 return -EBUSY;
1690 }
1691
1692 return 0;
1693}
1694
9a443537 1695void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
1696 union ib_gid *gid)
1697{
1698 u32 *p = NULL;
1699 u8 gid_idx = 0;
1700
1701 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1702
1703 p = (u32 *)&gid->raw[0];
1704 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1705 (HNS_ROCE_V1_GID_NUM * gid_idx));
1706
1707 p = (u32 *)&gid->raw[4];
1708 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1709 (HNS_ROCE_V1_GID_NUM * gid_idx));
1710
1711 p = (u32 *)&gid->raw[8];
1712 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1713 (HNS_ROCE_V1_GID_NUM * gid_idx));
1714
1715 p = (u32 *)&gid->raw[0xc];
1716 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1717 (HNS_ROCE_V1_GID_NUM * gid_idx));
1718}
1719
1720void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1721{
1722 u32 reg_smac_l;
1723 u16 reg_smac_h;
1724 u16 *p_h;
1725 u32 *p;
1726 u32 val;
1727
bfcc681b
SX		 1728 /*
1729 * When mac changed, loopback may fail
1730 * because of smac not equal to dmac.
1731 * We Need to release and create reserved qp again.
1732 */
1733 if (hr_dev->hw->dereg_mr && hns_roce_v1_recreate_lp_qp(hr_dev))
1734 dev_warn(&hr_dev->pdev->dev, "recreate lp qp timeout!\n");
1735
9a443537 1736 p = (u32 *)(&addr[0]);
1737 reg_smac_l = *p;
1738 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1739 PHY_PORT_OFFSET * phy_port);
1740
1741 val = roce_read(hr_dev,
1742 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1743 p_h = (u16 *)(&addr[4]);
1744 reg_smac_h = *p_h;
1745 roce_set_field(val, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1746 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1747 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1748 val);
1749}
1750
1751void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1752 enum ib_mtu mtu)
1753{
1754 u32 val;
1755
1756 val = roce_read(hr_dev,
1757 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1758 roce_set_field(val, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1759 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1760 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1761 val);
1762}
1763
1764int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1765 unsigned long mtpt_idx)
1766{
1767 struct hns_roce_v1_mpt_entry *mpt_entry;
1768 struct scatterlist *sg;
1769 u64 *pages;
1770 int entry;
1771 int i;
1772
1773 /* MPT filled into mailbox buf */
1774 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1775 memset(mpt_entry, 0, sizeof(*mpt_entry));
1776
1777 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1778 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1779 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1780 MPT_BYTE_4_KEY_S, mr->key);
1781 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1782 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1783 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1784 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1785 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1786 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1787 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1788 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1789 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1790 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1791 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1792 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1793 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1794 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1795 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1796 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1797 0);
1798 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1799
1800 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1801 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1802 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1803 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1804
1805 mpt_entry->virt_addr_l = (u32)mr->iova;
1806 mpt_entry->virt_addr_h = (u32)(mr->iova >> 32);
1807 mpt_entry->length = (u32)mr->size;
1808
1809 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1810 MPT_BYTE_28_PD_S, mr->pd);
1811 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1812 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1813 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1814 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1815
ad61dd30 1816 /* DMA memory register */
9a443537 1817 if (mr->type == MR_TYPE_DMA)
1818 return 0;
1819
1820 pages = (u64 *) __get_free_page(GFP_KERNEL);
1821 if (!pages)
1822 return -ENOMEM;
1823
1824 i = 0;
1825 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1826 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1827
1828 /* Directly record to MTPT table firstly 7 entry */
1829 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1830 break;
1831 i++;
1832 }
1833
1834 /* Register user mr */
1835 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1836 switch (i) {
1837 case 0:
1838 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1839 roce_set_field(mpt_entry->mpt_byte_36,
1840 MPT_BYTE_36_PA0_H_M,
1841 MPT_BYTE_36_PA0_H_S,
1842 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1843 break;
1844 case 1:
1845 roce_set_field(mpt_entry->mpt_byte_36,
1846 MPT_BYTE_36_PA1_L_M,
1847 MPT_BYTE_36_PA1_L_S,
1848 cpu_to_le32((u32)(pages[i])));
1849 roce_set_field(mpt_entry->mpt_byte_40,
1850 MPT_BYTE_40_PA1_H_M,
1851 MPT_BYTE_40_PA1_H_S,
1852 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1853 break;
1854 case 2:
1855 roce_set_field(mpt_entry->mpt_byte_40,
1856 MPT_BYTE_40_PA2_L_M,
1857 MPT_BYTE_40_PA2_L_S,
1858 cpu_to_le32((u32)(pages[i])));
1859 roce_set_field(mpt_entry->mpt_byte_44,
1860 MPT_BYTE_44_PA2_H_M,
1861 MPT_BYTE_44_PA2_H_S,
1862 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1863 break;
1864 case 3:
1865 roce_set_field(mpt_entry->mpt_byte_44,
1866 MPT_BYTE_44_PA3_L_M,
1867 MPT_BYTE_44_PA3_L_S,
1868 cpu_to_le32((u32)(pages[i])));
1869 roce_set_field(mpt_entry->mpt_byte_48,
1870 MPT_BYTE_48_PA3_H_M,
1871 MPT_BYTE_48_PA3_H_S,
1872 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_8)));
1873 break;
1874 case 4:
1875 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1876 roce_set_field(mpt_entry->mpt_byte_56,
1877 MPT_BYTE_56_PA4_H_M,
1878 MPT_BYTE_56_PA4_H_S,
1879 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1880 break;
1881 case 5:
1882 roce_set_field(mpt_entry->mpt_byte_56,
1883 MPT_BYTE_56_PA5_L_M,
1884 MPT_BYTE_56_PA5_L_S,
1885 cpu_to_le32((u32)(pages[i])));
1886 roce_set_field(mpt_entry->mpt_byte_60,
1887 MPT_BYTE_60_PA5_H_M,
1888 MPT_BYTE_60_PA5_H_S,
1889 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1890 break;
1891 case 6:
1892 roce_set_field(mpt_entry->mpt_byte_60,
1893 MPT_BYTE_60_PA6_L_M,
1894 MPT_BYTE_60_PA6_L_S,
1895 cpu_to_le32((u32)(pages[i])));
1896 roce_set_field(mpt_entry->mpt_byte_64,
1897 MPT_BYTE_64_PA6_H_M,
1898 MPT_BYTE_64_PA6_H_S,
1899 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1900 break;
1901 default:
1902 break;
1903 }
1904 }
1905
1906 free_page((unsigned long) pages);
1907
1908 mpt_entry->pbl_addr_l = (u32)(mr->pbl_dma_addr);
1909
1910 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1911 MPT_BYTE_12_PBL_ADDR_H_S,
1912 ((u32)(mr->pbl_dma_addr >> 32)));
1913
1914 return 0;
1915}
1916
1917static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1918{
1919 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1920 n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1921}
1922
1923static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1924{
1925 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1926
1927 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1928 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1929 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1930}
1931
1932static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1933{
1934 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1935}
1936
a4be892e 1937void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
9a443537 1938{
1939 u32 doorbell[2];
1940
1941 doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1);
5b0ff9a0 1942 doorbell[1] = 0;
9a443537 1943 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1944 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1945 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1946 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1947 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1948 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1949 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1950
1951 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1952}
1953
1954static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1955 struct hns_roce_srq *srq)
1956{
1957 struct hns_roce_cqe *cqe, *dest;
1958 u32 prod_index;
1959 int nfreed = 0;
1960 u8 owner_bit;
1961
1962 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1963 ++prod_index) {
1964 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1965 break;
1966 }
1967
1968 /*
e84e40be
S		 1969 * Now backwards through the CQ, removing CQ entries
1970 * that match our QP by overwriting them with next entries.
1971 */
9a443537 1972 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1973 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1974 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1975 CQE_BYTE_16_LOCAL_QPN_S) &
1976 HNS_ROCE_CQE_QPN_MASK) == qpn) {
1977 /* In v1 engine, not support SRQ */
1978 ++nfreed;
1979 } else if (nfreed) {
1980 dest = get_cqe(hr_cq, (prod_index + nfreed) &
1981 hr_cq->ib_cq.cqe);
1982 owner_bit = roce_get_bit(dest->cqe_byte_4,
1983 CQE_BYTE_4_OWNER_S);
1984 memcpy(dest, cqe, sizeof(*cqe));
1985 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1986 owner_bit);
1987 }
1988 }
1989
1990 if (nfreed) {
1991 hr_cq->cons_index += nfreed;
1992 /*
e84e40be
S		 1993 * Make sure update of buffer contents is done before
1994 * updating consumer index.
1995 */
9a443537 1996 wmb();
1997
a4be892e 1998 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
9a443537 1999 }
2000}
2001
2002static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2003 struct hns_roce_srq *srq)
2004{
2005 spin_lock_irq(&hr_cq->lock);
2006 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2007 spin_unlock_irq(&hr_cq->lock);
2008}
2009
2010void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2011 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
2012 dma_addr_t dma_handle, int nent, u32 vector)
2013{
2014 struct hns_roce_cq_context *cq_context = NULL;
8f3e9f3e
WHX		 2015 struct hns_roce_buf_list *tptr_buf;
2016 struct hns_roce_v1_priv *priv;
2017 dma_addr_t tptr_dma_addr;
2018 int offset;
2019
016a0059 2020 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e 2021 tptr_buf = &priv->tptr_table.tptr_buf;
9a443537 2022
2023 cq_context = mb_buf;
2024 memset(cq_context, 0, sizeof(*cq_context));
2025
8f3e9f3e
WHX		 2026 /* Get the tptr for this CQ. */
2027 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2028 tptr_dma_addr = tptr_buf->map + offset;
2029 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
9a443537 2030
2031 /* Register cq_context members */
2032 roce_set_field(cq_context->cqc_byte_4,
2033 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2034 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2035 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2036 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2037 cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4);
2038
2039 cq_context->cq_bt_l = (u32)dma_handle;
2040 cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l);
2041
2042 roce_set_field(cq_context->cqc_byte_12,
2043 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2044 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2045 ((u64)dma_handle >> 32));
2046 roce_set_field(cq_context->cqc_byte_12,
2047 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2048 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2049 ilog2((unsigned int)nent));
2050 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2051 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
2052 cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12);
2053
2054 cq_context->cur_cqe_ba0_l = (u32)(mtts[0]);
2055 cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l);
2056
2057 roce_set_field(cq_context->cqc_byte_20,
2058 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2059 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S,
2060 cpu_to_le32((mtts[0]) >> 32));
2061 /* Dedicated hardware, directly set 0 */
2062 roce_set_field(cq_context->cqc_byte_20,
2063 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2064 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2065 /**
2066 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2067 * using 4K page, and shift more 32 because of
2068 * caculating the high 32 bit value evaluated to hardware.
2069 */
2070 roce_set_field(cq_context->cqc_byte_20,
2071 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2072 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
8f3e9f3e 2073 tptr_dma_addr >> 44);
9a443537 2074 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
2075
8f3e9f3e 2076 cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
9a443537 2077
2078 roce_set_field(cq_context->cqc_byte_32,
2079 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2080 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2081 roce_set_bit(cq_context->cqc_byte_32,
2082 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2083 roce_set_bit(cq_context->cqc_byte_32,
2084 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2085 roce_set_bit(cq_context->cqc_byte_32,
2086 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2087 roce_set_bit(cq_context->cqc_byte_32,
2088 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2089 0);
e84e40be 2090 /* The initial value of cq's ci is 0 */
9a443537 2091 roce_set_field(cq_context->cqc_byte_32,
2092 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2093 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2094 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
2095}
2096
2097int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
2098{
2099 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2100 u32 notification_flag;
2101 u32 doorbell[2];
9a443537 2102
2103 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2104 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2105 /*
e84e40be
S		 2106 * flags = 0; Notification Flag = 1, next
2107 * flags = 1; Notification Flag = 0, solocited
2108 */
9a443537 2109 doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
2110 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2111 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2112 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2113 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2114 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2115 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2116 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2117 hr_cq->cqn | notification_flag);
2118
2119 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2120
87809f83 2121 return 0;
9a443537 2122}
2123
2124static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2125 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2126{
2127 int qpn;
2128 int is_send;
2129 u16 wqe_ctr;
2130 u32 status;
2131 u32 opcode;
2132 struct hns_roce_cqe *cqe;
2133 struct hns_roce_qp *hr_qp;
2134 struct hns_roce_wq *wq;
2135 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2136 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2137 struct device *dev = &hr_dev->pdev->dev;
2138
2139 /* Find cqe according consumer index */
2140 cqe = next_cqe_sw(hr_cq);
2141 if (!cqe)
2142 return -EAGAIN;
2143
2144 ++hr_cq->cons_index;
2145 /* Memory barrier */
2146 rmb();
2147 /* 0->SQ, 1->RQ */
2148 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2149
2150 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2151 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2152 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2153 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2154 CQE_BYTE_20_PORT_NUM_S) +
2155 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2156 CQE_BYTE_16_LOCAL_QPN_S) *
2157 HNS_ROCE_MAX_PORTS;
2158 } else {
2159 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2160 CQE_BYTE_16_LOCAL_QPN_S);
2161 }
2162
2163 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2164 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2165 if (unlikely(!hr_qp)) {
2166 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2167 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2168 return -EINVAL;
2169 }
2170
2171 *cur_qp = hr_qp;
2172 }
2173
2174 wc->qp = &(*cur_qp)->ibqp;
2175 wc->vendor_err = 0;
2176
2177 status = roce_get_field(cqe->cqe_byte_4,
2178 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2179 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2180 HNS_ROCE_CQE_STATUS_MASK;
2181 switch (status) {
2182 case HNS_ROCE_CQE_SUCCESS:
2183 wc->status = IB_WC_SUCCESS;
2184 break;
2185 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2186 wc->status = IB_WC_LOC_LEN_ERR;
2187 break;
2188 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2189 wc->status = IB_WC_LOC_QP_OP_ERR;
2190 break;
2191 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2192 wc->status = IB_WC_LOC_PROT_ERR;
2193 break;
2194 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2195 wc->status = IB_WC_WR_FLUSH_ERR;
2196 break;
2197 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2198 wc->status = IB_WC_MW_BIND_ERR;
2199 break;
2200 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2201 wc->status = IB_WC_BAD_RESP_ERR;
2202 break;
2203 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2204 wc->status = IB_WC_LOC_ACCESS_ERR;
2205 break;
2206 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2207 wc->status = IB_WC_REM_INV_REQ_ERR;
2208 break;
2209 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2210 wc->status = IB_WC_REM_ACCESS_ERR;
2211 break;
2212 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2213 wc->status = IB_WC_REM_OP_ERR;
2214 break;
2215 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2216 wc->status = IB_WC_RETRY_EXC_ERR;
2217 break;
2218 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2219 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2220 break;
2221 default:
2222 wc->status = IB_WC_GENERAL_ERR;
2223 break;
2224 }
2225
2226 /* CQE status error, directly return */
2227 if (wc->status != IB_WC_SUCCESS)
2228 return 0;
2229
2230 if (is_send) {
2231 /* SQ conrespond to CQE */
2232 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2233 CQE_BYTE_4_WQE_INDEX_M,
1bdab400
S		 2234 CQE_BYTE_4_WQE_INDEX_S)&
2235 ((*cur_qp)->sq.wqe_cnt-1));
9a443537 2236 switch (sq_wqe->flag & HNS_ROCE_WQE_OPCODE_MASK) {
2237 case HNS_ROCE_WQE_OPCODE_SEND:
2238 wc->opcode = IB_WC_SEND;
2239 break;
2240 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2241 wc->opcode = IB_WC_RDMA_READ;
2242 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2243 break;
2244 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2245 wc->opcode = IB_WC_RDMA_WRITE;
2246 break;
2247 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2248 wc->opcode = IB_WC_LOCAL_INV;
2249 break;
2250 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2251 wc->opcode = IB_WC_SEND;
2252 break;
2253 default:
2254 wc->status = IB_WC_GENERAL_ERR;
2255 break;
2256 }
2257 wc->wc_flags = (sq_wqe->flag & HNS_ROCE_WQE_IMM ?
2258 IB_WC_WITH_IMM : 0);
2259
2260 wq = &(*cur_qp)->sq;
2261 if ((*cur_qp)->sq_signal_bits) {
2262 /*
e84e40be
S		 2263 * If sg_signal_bit is 1,
2264 * firstly tail pointer updated to wqe
2265 * which current cqe correspond to
2266 */
9a443537 2267 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2268 CQE_BYTE_4_WQE_INDEX_M,
2269 CQE_BYTE_4_WQE_INDEX_S);
2270 wq->tail += (wqe_ctr - (u16)wq->tail) &
2271 (wq->wqe_cnt - 1);
2272 }
2273 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2274 ++wq->tail;
5f110ac4 2275 } else {
9a443537 2276 /* RQ conrespond to CQE */
2277 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2278 opcode = roce_get_field(cqe->cqe_byte_4,
2279 CQE_BYTE_4_OPERATION_TYPE_M,
2280 CQE_BYTE_4_OPERATION_TYPE_S) &
2281 HNS_ROCE_CQE_OPCODE_MASK;
2282 switch (opcode) {
2283 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2284 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2285 wc->wc_flags = IB_WC_WITH_IMM;
2286 wc->ex.imm_data = le32_to_cpu(cqe->immediate_data);
2287 break;
2288 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2289 if (roce_get_bit(cqe->cqe_byte_4,
2290 CQE_BYTE_4_IMM_INDICATOR_S)) {
2291 wc->opcode = IB_WC_RECV;
2292 wc->wc_flags = IB_WC_WITH_IMM;
2293 wc->ex.imm_data = le32_to_cpu(
2294 cqe->immediate_data);
2295 } else {
2296 wc->opcode = IB_WC_RECV;
2297 wc->wc_flags = 0;
2298 }
2299 break;
2300 default:
2301 wc->status = IB_WC_GENERAL_ERR;
2302 break;
2303 }
2304
2305 /* Update tail pointer, record wr_id */
2306 wq = &(*cur_qp)->rq;
2307 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2308 ++wq->tail;
2309 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2310 CQE_BYTE_20_SL_S);
2311 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2312 CQE_BYTE_20_REMOTE_QPN_M,
2313 CQE_BYTE_20_REMOTE_QPN_S);
2314 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2315 CQE_BYTE_20_GRH_PRESENT_S) ?
2316 IB_WC_GRH : 0);
2317 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2318 CQE_BYTE_28_P_KEY_IDX_M,
2319 CQE_BYTE_28_P_KEY_IDX_S);
2320 }
2321
2322 return 0;
2323}
2324
2325int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2326{
2327 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2328 struct hns_roce_qp *cur_qp = NULL;
2329 unsigned long flags;
2330 int npolled;
2331 int ret = 0;
2332
2333 spin_lock_irqsave(&hr_cq->lock, flags);
2334
2335 for (npolled = 0; npolled < num_entries; ++npolled) {
2336 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2337 if (ret)
2338 break;
2339 }
2340
8f3e9f3e
WHX		 2341 if (npolled) {
2342 *hr_cq->tptr_addr = hr_cq->cons_index &
2343 ((hr_cq->cq_depth << 1) - 1);
2344
2345 /* Memroy barrier */
2346 wmb();
a4be892e 2347 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
8f3e9f3e 2348 }
9a443537 2349
2350 spin_unlock_irqrestore(&hr_cq->lock, flags);
2351
2352 if (ret == 0 || ret == -EAGAIN)
2353 return npolled;
2354 else
2355 return ret;
2356}
2357
97f0e39f 2358int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
a25d13cb 2359 struct hns_roce_hem_table *table, int obj, int step_idx)
97f0e39f
WHX		 2360{
2361 struct device *dev = &hr_dev->pdev->dev;
2362 struct hns_roce_v1_priv *priv;
2363 unsigned long end = 0, flags = 0;
2364 uint32_t bt_cmd_val[2] = {0};
2365 void __iomem *bt_cmd;
2366 u64 bt_ba = 0;
2367
016a0059 2368 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 2369
2370 switch (table->type) {
2371 case HEM_TYPE_QPC:
2372 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2373 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2374 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2375 break;
2376 case HEM_TYPE_MTPT:
2377 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2378 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2379 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2380 break;
2381 case HEM_TYPE_CQC:
2382 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2383 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2384 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2385 break;
2386 case HEM_TYPE_SRQC:
2387 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2388 return -EINVAL;
2389 default:
2390 return 0;
2391 }
2392 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2393 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2394 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2395 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2396
2397 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2398
2399 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2400
2401 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2402 while (1) {
2403 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2404 if (!(time_before(jiffies, end))) {
2405 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2406 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2407 flags);
2408 return -EBUSY;
2409 }
2410 } else {
2411 break;
2412 }
2413 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2414 }
2415
2416 bt_cmd_val[0] = (uint32_t)bt_ba;
2417 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2418 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2419 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2420
2421 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2422
2423 return 0;
2424}
2425
9a443537 2426static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2427 struct hns_roce_mtt *mtt,
2428 enum hns_roce_qp_state cur_state,
2429 enum hns_roce_qp_state new_state,
2430 struct hns_roce_qp_context *context,
2431 struct hns_roce_qp *hr_qp)
2432{
2433 static const u16
2434 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2435 [HNS_ROCE_QP_STATE_RST] = {
2436 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2437 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2438 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2439 },
2440 [HNS_ROCE_QP_STATE_INIT] = {
2441 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2442 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2443 /* Note: In v1 engine, HW doesn't support RST2INIT.
2444 * We use RST2INIT cmd instead of INIT2INIT.
2445 */
2446 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2447 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2448 },
2449 [HNS_ROCE_QP_STATE_RTR] = {
2450 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2451 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2452 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2453 },
2454 [HNS_ROCE_QP_STATE_RTS] = {
2455 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2456 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2457 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2458 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2459 },
2460 [HNS_ROCE_QP_STATE_SQD] = {
2461 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2462 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2463 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2464 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2465 },
2466 [HNS_ROCE_QP_STATE_ERR] = {
2467 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2468 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2469 }
2470 };
2471
2472 struct hns_roce_cmd_mailbox *mailbox;
2473 struct device *dev = &hr_dev->pdev->dev;
2474 int ret = 0;
2475
2476 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2477 new_state >= HNS_ROCE_QP_NUM_STATE ||
2478 !op[cur_state][new_state]) {
2479 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2480 cur_state, new_state);
2481 return -EINVAL;
2482 }
2483
2484 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2485 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2486 HNS_ROCE_CMD_2RST_QP,
6b877c32 2487 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2488
2489 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2490 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2491 HNS_ROCE_CMD_2ERR_QP,
6b877c32 2492 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2493
2494 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2495 if (IS_ERR(mailbox))
2496 return PTR_ERR(mailbox);
2497
2498 memcpy(mailbox->buf, context, sizeof(*context));
2499
2500 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2501 op[cur_state][new_state],
6b877c32 2502 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2503
2504 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2505 return ret;
2506}
2507
2508static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2509 int attr_mask, enum ib_qp_state cur_state,
2510 enum ib_qp_state new_state)
2511{
2512 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2513 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2514 struct hns_roce_sqp_context *context;
2515 struct device *dev = &hr_dev->pdev->dev;
2516 dma_addr_t dma_handle = 0;
2517 int rq_pa_start;
2518 u32 reg_val;
2519 u64 *mtts;
2520 u32 *addr;
2521
2522 context = kzalloc(sizeof(*context), GFP_KERNEL);
2523 if (!context)
2524 return -ENOMEM;
2525
2526 /* Search QP buf's MTTs */
2527 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2528 hr_qp->mtt.first_seg, &dma_handle);
2529 if (!mtts) {
2530 dev_err(dev, "qp buf pa find failed\n");
2531 goto out;
2532 }
2533
2534 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2535 roce_set_field(context->qp1c_bytes_4,
2536 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2537 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2538 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2539 roce_set_field(context->qp1c_bytes_4,
2540 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2541 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2542 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2543 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2544 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2545
2546 context->sq_rq_bt_l = (u32)(dma_handle);
2547 roce_set_field(context->qp1c_bytes_12,
2548 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2549 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2550 ((u32)(dma_handle >> 32)));
2551
2552 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2553 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2554 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
7716809e 2555 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
9a443537 2556 roce_set_bit(context->qp1c_bytes_16,
2557 QP1C_BYTES_16_SIGNALING_TYPE_S,
2558 hr_qp->sq_signal_bits);
9a443537 2559 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2560 1);
2561 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2562 1);
2563 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2564 0);
2565
2566 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2567 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2568 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2569 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2570
2571 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2572 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2573
2574 roce_set_field(context->qp1c_bytes_28,
2575 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2576 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2577 (mtts[rq_pa_start]) >> 32);
2578 roce_set_field(context->qp1c_bytes_28,
2579 QP1C_BYTES_28_RQ_CUR_IDX_M,
2580 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2581
2582 roce_set_field(context->qp1c_bytes_32,
2583 QP1C_BYTES_32_RX_CQ_NUM_M,
2584 QP1C_BYTES_32_RX_CQ_NUM_S,
2585 to_hr_cq(ibqp->recv_cq)->cqn);
2586 roce_set_field(context->qp1c_bytes_32,
2587 QP1C_BYTES_32_TX_CQ_NUM_M,
2588 QP1C_BYTES_32_TX_CQ_NUM_S,
2589 to_hr_cq(ibqp->send_cq)->cqn);
2590
2591 context->cur_sq_wqe_ba_l = (u32)mtts[0];
2592
2593 roce_set_field(context->qp1c_bytes_40,
2594 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2595 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2596 (mtts[0]) >> 32);
2597 roce_set_field(context->qp1c_bytes_40,
2598 QP1C_BYTES_40_SQ_CUR_IDX_M,
2599 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2600
2601 /* Copy context to QP1C register */
2602 addr = (u32 *)(hr_dev->reg_base + ROCEE_QP1C_CFG0_0_REG +
7716809e 2603 hr_qp->phy_port * sizeof(*context));
9a443537 2604
2605 writel(context->qp1c_bytes_4, addr);
2606 writel(context->sq_rq_bt_l, addr + 1);
2607 writel(context->qp1c_bytes_12, addr + 2);
2608 writel(context->qp1c_bytes_16, addr + 3);
2609 writel(context->qp1c_bytes_20, addr + 4);
2610 writel(context->cur_rq_wqe_ba_l, addr + 5);
2611 writel(context->qp1c_bytes_28, addr + 6);
2612 writel(context->qp1c_bytes_32, addr + 7);
2613 writel(context->cur_sq_wqe_ba_l, addr + 8);
c24bf895 2614 writel(context->qp1c_bytes_40, addr + 9);
9a443537 2615 }
2616
2617 /* Modify QP1C status */
2618 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 2619 hr_qp->phy_port * sizeof(*context));
9a443537 2620 roce_set_field(reg_val, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2621 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2622 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 2623 hr_qp->phy_port * sizeof(*context), reg_val);
9a443537 2624
2625 hr_qp->state = new_state;
2626 if (new_state == IB_QPS_RESET) {
2627 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2628 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2629 if (ibqp->send_cq != ibqp->recv_cq)
2630 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2631 hr_qp->qpn, NULL);
2632
2633 hr_qp->rq.head = 0;
2634 hr_qp->rq.tail = 0;
2635 hr_qp->sq.head = 0;
2636 hr_qp->sq.tail = 0;
2637 hr_qp->sq_next_wqe = 0;
2638 }
2639
2640 kfree(context);
2641 return 0;
2642
2643out:
2644 kfree(context);
2645 return -EINVAL;
2646}
2647
2648static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2649 int attr_mask, enum ib_qp_state cur_state,
2650 enum ib_qp_state new_state)
2651{
2652 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2653 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2654 struct device *dev = &hr_dev->pdev->dev;
2655 struct hns_roce_qp_context *context;
d8966fcd 2656 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
9a443537 2657 dma_addr_t dma_handle_2 = 0;
2658 dma_addr_t dma_handle = 0;
2659 uint32_t doorbell[2] = {0};
2660 int rq_pa_start = 0;
9a443537 2661 u64 *mtts_2 = NULL;
2662 int ret = -EINVAL;
2663 u64 *mtts = NULL;
2664 int port;
d8966fcd 2665 u8 port_num;
9a443537 2666 u8 *dmac;
2667 u8 *smac;
2668
2669 context = kzalloc(sizeof(*context), GFP_KERNEL);
2670 if (!context)
2671 return -ENOMEM;
2672
2673 /* Search qp buf's mtts */
2674 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2675 hr_qp->mtt.first_seg, &dma_handle);
2676 if (mtts == NULL) {
2677 dev_err(dev, "qp buf pa find failed\n");
2678 goto out;
2679 }
2680
2681 /* Search IRRL's mtts */
2682 mtts_2 = hns_roce_table_find(&hr_dev->qp_table.irrl_table, hr_qp->qpn,
2683 &dma_handle_2);
2684 if (mtts_2 == NULL) {
2685 dev_err(dev, "qp irrl_table find failed\n");
2686 goto out;
2687 }
2688
2689 /*
e84e40be
S		 2690 * Reset to init
2691 * Mandatory param:
2692 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2693 * Optional param: NA
2694 */
9a443537 2695 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2696 roce_set_field(context->qpc_bytes_4,
2697 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2698 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2699 to_hr_qp_type(hr_qp->ibqp.qp_type));
2700
2701 roce_set_bit(context->qpc_bytes_4,
2702 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2703 roce_set_bit(context->qpc_bytes_4,
2704 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2705 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2706 roce_set_bit(context->qpc_bytes_4,
2707 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2708 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2709 );
2710 roce_set_bit(context->qpc_bytes_4,
2711 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2712 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2713 );
2714 roce_set_bit(context->qpc_bytes_4,
2715 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2716 roce_set_field(context->qpc_bytes_4,
2717 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2718 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2719 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2720 roce_set_field(context->qpc_bytes_4,
2721 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2722 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2723 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2724 roce_set_field(context->qpc_bytes_4,
2725 QP_CONTEXT_QPC_BYTES_4_PD_M,
2726 QP_CONTEXT_QPC_BYTES_4_PD_S,
2727 to_hr_pd(ibqp->pd)->pdn);
2728 hr_qp->access_flags = attr->qp_access_flags;
2729 roce_set_field(context->qpc_bytes_8,
2730 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2731 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2732 to_hr_cq(ibqp->send_cq)->cqn);
2733 roce_set_field(context->qpc_bytes_8,
2734 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2735 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2736 to_hr_cq(ibqp->recv_cq)->cqn);
2737
2738 if (ibqp->srq)
2739 roce_set_field(context->qpc_bytes_12,
2740 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2741 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2742 to_hr_srq(ibqp->srq)->srqn);
2743
2744 roce_set_field(context->qpc_bytes_12,
2745 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2746 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2747 attr->pkey_index);
2748 hr_qp->pkey_index = attr->pkey_index;
2749 roce_set_field(context->qpc_bytes_16,
2750 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2751 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2752
2753 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2754 roce_set_field(context->qpc_bytes_4,
2755 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2756 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2757 to_hr_qp_type(hr_qp->ibqp.qp_type));
2758 roce_set_bit(context->qpc_bytes_4,
2759 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2760 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2761 roce_set_bit(context->qpc_bytes_4,
2762 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2763 !!(attr->qp_access_flags &
2764 IB_ACCESS_REMOTE_READ));
2765 roce_set_bit(context->qpc_bytes_4,
2766 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2767 !!(attr->qp_access_flags &
2768 IB_ACCESS_REMOTE_WRITE));
2769 } else {
2770 roce_set_bit(context->qpc_bytes_4,
2771 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2772 !!(hr_qp->access_flags &
2773 IB_ACCESS_REMOTE_READ));
2774 roce_set_bit(context->qpc_bytes_4,
2775 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2776 !!(hr_qp->access_flags &
2777 IB_ACCESS_REMOTE_WRITE));
2778 }
2779
2780 roce_set_bit(context->qpc_bytes_4,
2781 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2782 roce_set_field(context->qpc_bytes_4,
2783 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2784 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2785 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2786 roce_set_field(context->qpc_bytes_4,
2787 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2788 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2789 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2790 roce_set_field(context->qpc_bytes_4,
2791 QP_CONTEXT_QPC_BYTES_4_PD_M,
2792 QP_CONTEXT_QPC_BYTES_4_PD_S,
2793 to_hr_pd(ibqp->pd)->pdn);
2794
2795 roce_set_field(context->qpc_bytes_8,
2796 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2797 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2798 to_hr_cq(ibqp->send_cq)->cqn);
2799 roce_set_field(context->qpc_bytes_8,
2800 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2801 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2802 to_hr_cq(ibqp->recv_cq)->cqn);
2803
2804 if (ibqp->srq)
2805 roce_set_field(context->qpc_bytes_12,
2806 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2807 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2808 to_hr_srq(ibqp->srq)->srqn);
2809 if (attr_mask & IB_QP_PKEY_INDEX)
2810 roce_set_field(context->qpc_bytes_12,
2811 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2812 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2813 attr->pkey_index);
2814 else
2815 roce_set_field(context->qpc_bytes_12,
2816 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2817 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2818 hr_qp->pkey_index);
2819
2820 roce_set_field(context->qpc_bytes_16,
2821 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2822 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2823 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2824 if ((attr_mask & IB_QP_ALT_PATH) ||
2825 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2826 (attr_mask & IB_QP_PKEY_INDEX) ||
2827 (attr_mask & IB_QP_QKEY)) {
2828 dev_err(dev, "INIT2RTR attr_mask error\n");
2829 goto out;
2830 }
2831
44c58487 2832 dmac = (u8 *)attr->ah_attr.roce.dmac;
9a443537 2833
2834 context->sq_rq_bt_l = (u32)(dma_handle);
2835 roce_set_field(context->qpc_bytes_24,
2836 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2837 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2838 ((u32)(dma_handle >> 32)));
2839 roce_set_bit(context->qpc_bytes_24,
2840 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2841 1);
2842 roce_set_field(context->qpc_bytes_24,
2843 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2844 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2845 attr->min_rnr_timer);
2846 context->irrl_ba_l = (u32)(dma_handle_2);
2847 roce_set_field(context->qpc_bytes_32,
2848 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2849 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2850 ((u32)(dma_handle_2 >> 32)) &
2851 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2852 roce_set_field(context->qpc_bytes_32,
2853 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2854 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2855 roce_set_bit(context->qpc_bytes_32,
2856 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2857 1);
2858 roce_set_bit(context->qpc_bytes_32,
2859 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2860 hr_qp->sq_signal_bits);
2861
80596c67
LO		 2862 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2863 hr_qp->port;
2864 smac = (u8 *)hr_dev->dev_addr[port];
2865 /* when dmac equals smac or loop_idc is 1, it should loopback */
2866 if (ether_addr_equal_unaligned(dmac, smac) ||
2867 hr_dev->loop_idc == 0x1)
9a443537 2868 roce_set_bit(context->qpc_bytes_32,
80596c67 2869 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
9a443537 2870
2871 roce_set_bit(context->qpc_bytes_32,
2872 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
d8966fcd 2873 rdma_ah_get_ah_flags(&attr->ah_attr));
9a443537 2874 roce_set_field(context->qpc_bytes_32,
2875 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2876 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2877 ilog2((unsigned int)attr->max_dest_rd_atomic));
2878
2879 roce_set_field(context->qpc_bytes_36,
2880 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2881 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2882 attr->dest_qp_num);
2883
2884 /* Configure GID index */
d8966fcd 2885 port_num = rdma_ah_get_port_num(&attr->ah_attr);
9a443537 2886 roce_set_field(context->qpc_bytes_36,
2887 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2888 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
d8966fcd
DC		 2889 hns_get_gid_index(hr_dev,
2890 port_num - 1,
2891 grh->sgid_index));
9a443537 2892
2893 memcpy(&(context->dmac_l), dmac, 4);
2894
2895 roce_set_field(context->qpc_bytes_44,
2896 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2897 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2898 *((u16 *)(&dmac[4])));
2899 roce_set_field(context->qpc_bytes_44,
2900 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2901 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
d8966fcd 2902 rdma_ah_get_static_rate(&attr->ah_attr));
9a443537 2903 roce_set_field(context->qpc_bytes_44,
2904 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2905 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
d8966fcd 2906 grh->hop_limit);
9a443537 2907
2908 roce_set_field(context->qpc_bytes_48,
2909 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2910 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
d8966fcd 2911 grh->flow_label);
9a443537 2912 roce_set_field(context->qpc_bytes_48,
2913 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2914 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
d8966fcd 2915 grh->traffic_class);
9a443537 2916 roce_set_field(context->qpc_bytes_48,
2917 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2918 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2919
d8966fcd
DC		 2920 memcpy(context->dgid, grh->dgid.raw,
2921 sizeof(grh->dgid.raw));
9a443537 2922
2923 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2924 roce_get_field(context->qpc_bytes_44,
2925 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2926 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2927
2928 roce_set_field(context->qpc_bytes_68,
2929 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
1fad5fab
LO		 2930 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2931 hr_qp->rq.head);
9a443537 2932 roce_set_field(context->qpc_bytes_68,
2933 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2934 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2935
2936 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2937 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2938
2939 roce_set_field(context->qpc_bytes_76,
2940 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2941 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2942 mtts[rq_pa_start] >> 32);
2943 roce_set_field(context->qpc_bytes_76,
2944 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2945 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2946
2947 context->rx_rnr_time = 0;
2948
2949 roce_set_field(context->qpc_bytes_84,
2950 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2951 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2952 attr->rq_psn - 1);
2953 roce_set_field(context->qpc_bytes_84,
2954 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2955 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2956
2957 roce_set_field(context->qpc_bytes_88,
2958 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2959 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2960 attr->rq_psn);
2961 roce_set_bit(context->qpc_bytes_88,
2962 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2963 roce_set_bit(context->qpc_bytes_88,
2964 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2965 roce_set_field(context->qpc_bytes_88,
2966 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2967 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2968 0);
2969 roce_set_field(context->qpc_bytes_88,
2970 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2971 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2972 0);
2973
2974 context->dma_length = 0;
2975 context->r_key = 0;
2976 context->va_l = 0;
2977 context->va_h = 0;
2978
2979 roce_set_field(context->qpc_bytes_108,
2980 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2981 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2982 roce_set_bit(context->qpc_bytes_108,
2983 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2984 roce_set_bit(context->qpc_bytes_108,
2985 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
2986
2987 roce_set_field(context->qpc_bytes_112,
2988 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
2989 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
2990 roce_set_field(context->qpc_bytes_112,
2991 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
2992 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
2993
2994 /* For chip resp ack */
2995 roce_set_field(context->qpc_bytes_156,
2996 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2997 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 2998 hr_qp->phy_port);
9a443537 2999 roce_set_field(context->qpc_bytes_156,
3000 QP_CONTEXT_QPC_BYTES_156_SL_M,
d8966fcd
DC		 3001 QP_CONTEXT_QPC_BYTES_156_SL_S,
3002 rdma_ah_get_sl(&attr->ah_attr));
3003 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
9a443537 3004 } else if (cur_state == IB_QPS_RTR &&
3005 new_state == IB_QPS_RTS) {
3006 /* If exist optional param, return error */
3007 if ((attr_mask & IB_QP_ALT_PATH) ||
3008 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3009 (attr_mask & IB_QP_QKEY) ||
3010 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3011 (attr_mask & IB_QP_CUR_STATE) ||
3012 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3013 dev_err(dev, "RTR2RTS attr_mask error\n");
3014 goto out;
3015 }
3016
3017 context->rx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
3018
3019 roce_set_field(context->qpc_bytes_120,
3020 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3021 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3022 (mtts[0]) >> 32);
3023
3024 roce_set_field(context->qpc_bytes_124,
3025 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3026 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3027 roce_set_field(context->qpc_bytes_124,
3028 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3029 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3030
3031 roce_set_field(context->qpc_bytes_128,
3032 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3033 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3034 attr->sq_psn);
3035 roce_set_bit(context->qpc_bytes_128,
3036 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3037 roce_set_field(context->qpc_bytes_128,
3038 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3039 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3040 0);
3041 roce_set_bit(context->qpc_bytes_128,
3042 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3043
3044 roce_set_field(context->qpc_bytes_132,
3045 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3046 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3047 roce_set_field(context->qpc_bytes_132,
3048 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3049 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3050
3051 roce_set_field(context->qpc_bytes_136,
3052 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3053 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3054 attr->sq_psn);
3055 roce_set_field(context->qpc_bytes_136,
3056 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3057 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3058 attr->sq_psn);
3059
3060 roce_set_field(context->qpc_bytes_140,
3061 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3062 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3063 (attr->sq_psn >> SQ_PSN_SHIFT));
3064 roce_set_field(context->qpc_bytes_140,
3065 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3066 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3067 roce_set_bit(context->qpc_bytes_140,
3068 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3069
9a443537 3070 roce_set_field(context->qpc_bytes_148,
3071 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3072 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3073 roce_set_field(context->qpc_bytes_148,
3074 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
7c7a4ea1
LO		 3075 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3076 attr->retry_cnt);
9a443537 3077 roce_set_field(context->qpc_bytes_148,
3078 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
7c7a4ea1
LO		 3079 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3080 attr->rnr_retry);
9a443537 3081 roce_set_field(context->qpc_bytes_148,
3082 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3083 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3084
3085 context->rnr_retry = 0;
3086
3087 roce_set_field(context->qpc_bytes_156,
3088 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3089 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3090 attr->retry_cnt);
c6c3bfea
LO		 3091 if (attr->timeout < 0x12) {
3092 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3093 attr->timeout);
3094 roce_set_field(context->qpc_bytes_156,
3095 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3096 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3097 0x12);
3098 } else {
3099 roce_set_field(context->qpc_bytes_156,
3100 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3101 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3102 attr->timeout);
3103 }
9a443537 3104 roce_set_field(context->qpc_bytes_156,
3105 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3106 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3107 attr->rnr_retry);
3108 roce_set_field(context->qpc_bytes_156,
3109 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3110 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 3111 hr_qp->phy_port);
9a443537 3112 roce_set_field(context->qpc_bytes_156,
3113 QP_CONTEXT_QPC_BYTES_156_SL_M,
d8966fcd
DC		 3114 QP_CONTEXT_QPC_BYTES_156_SL_S,
3115 rdma_ah_get_sl(&attr->ah_attr));
3116 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
9a443537 3117 roce_set_field(context->qpc_bytes_156,
3118 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3119 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3120 ilog2((unsigned int)attr->max_rd_atomic));
3121 roce_set_field(context->qpc_bytes_156,
3122 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3123 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3124 context->pkt_use_len = 0;
3125
3126 roce_set_field(context->qpc_bytes_164,
3127 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3128 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3129 roce_set_field(context->qpc_bytes_164,
3130 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3131 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3132
3133 roce_set_field(context->qpc_bytes_168,
3134 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3135 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3136 attr->sq_psn);
3137 roce_set_field(context->qpc_bytes_168,
3138 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3139 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3140 roce_set_field(context->qpc_bytes_168,
3141 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3142 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3143 roce_set_bit(context->qpc_bytes_168,
3144 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3145 roce_set_bit(context->qpc_bytes_168,
3146 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3147 roce_set_bit(context->qpc_bytes_168,
3148 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3149 context->sge_use_len = 0;
3150
3151 roce_set_field(context->qpc_bytes_176,
3152 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3153 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3154 roce_set_field(context->qpc_bytes_176,
3155 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3156 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3157 0);
3158 roce_set_field(context->qpc_bytes_180,
3159 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3160 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3161 roce_set_field(context->qpc_bytes_180,
3162 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3163 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3164
3165 context->tx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
3166
3167 roce_set_field(context->qpc_bytes_188,
3168 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3169 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3170 (mtts[0]) >> 32);
3171 roce_set_bit(context->qpc_bytes_188,
3172 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3173 roce_set_field(context->qpc_bytes_188,
3174 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3175 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3176 0);
deb17f6f 3177 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
9a443537 3178 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3179 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3180 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3181 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3182 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3183 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
deb17f6f
LO		 3184 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3185 dev_err(dev, "not support this status migration\n");
9a443537 3186 goto out;
3187 }
3188
3189 /* Every status migrate must change state */
3190 roce_set_field(context->qpc_bytes_144,
3191 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
1dec243a 3192 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
9a443537 3193
3194 /* SW pass context to HW */
3195 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3196 to_hns_roce_state(cur_state),
3197 to_hns_roce_state(new_state), context,
3198 hr_qp);
3199 if (ret) {
3200 dev_err(dev, "hns_roce_qp_modify failed\n");
3201 goto out;
3202 }
3203
3204 /*
e84e40be
S		 3205 * Use rst2init to instead of init2init with drv,
3206 * need to hw to flash RQ HEAD by DB again
3207 */
9a443537 3208 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3209 /* Memory barrier */
3210 wmb();
9a443537 3211
509bf0c2
LO		 3212 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3213 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3214 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3215 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3216 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3217 RQ_DOORBELL_U32_8_CMD_S, 1);
3218 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3219
3220 if (ibqp->uobject) {
3221 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3222 ROCEE_DB_OTHERS_L_0_REG +
3223 DB_REG_OFFSET * hr_dev->priv_uar.index;
9a443537 3224 }
509bf0c2
LO		 3225
3226 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
9a443537 3227 }
3228
3229 hr_qp->state = new_state;
3230
3231 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3232 hr_qp->resp_depth = attr->max_dest_rd_atomic;
7716809e
LO		 3233 if (attr_mask & IB_QP_PORT) {
3234 hr_qp->port = attr->port_num - 1;
3235 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3236 }
9a443537 3237
3238 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3239 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3240 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3241 if (ibqp->send_cq != ibqp->recv_cq)
3242 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3243 hr_qp->qpn, NULL);
3244
3245 hr_qp->rq.head = 0;
3246 hr_qp->rq.tail = 0;
3247 hr_qp->sq.head = 0;
3248 hr_qp->sq.tail = 0;
3249 hr_qp->sq_next_wqe = 0;
3250 }
3251out:
3252 kfree(context);
3253 return ret;
3254}
3255
3256int hns_roce_v1_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
3257 int attr_mask, enum ib_qp_state cur_state,
3258 enum ib_qp_state new_state)
3259{
3260
3261 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3262 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3263 new_state);
3264 else
3265 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3266 new_state);
3267}
3268
3269static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3270{
3271 switch (state) {
3272 case HNS_ROCE_QP_STATE_RST:
3273 return IB_QPS_RESET;
3274 case HNS_ROCE_QP_STATE_INIT:
3275 return IB_QPS_INIT;
3276 case HNS_ROCE_QP_STATE_RTR:
3277 return IB_QPS_RTR;
3278 case HNS_ROCE_QP_STATE_RTS:
3279 return IB_QPS_RTS;
3280 case HNS_ROCE_QP_STATE_SQD:
3281 return IB_QPS_SQD;
3282 case HNS_ROCE_QP_STATE_ERR:
3283 return IB_QPS_ERR;
3284 default:
3285 return IB_QPS_ERR;
3286 }
3287}
3288
3289static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3290 struct hns_roce_qp *hr_qp,
3291 struct hns_roce_qp_context *hr_context)
3292{
3293 struct hns_roce_cmd_mailbox *mailbox;
3294 int ret;
3295
3296 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3297 if (IS_ERR(mailbox))
3298 return PTR_ERR(mailbox);
3299
3300 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3301 HNS_ROCE_CMD_QUERY_QP,
6b877c32 3302 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 3303 if (!ret)
3304 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3305 else
3306 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3307
3308 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3309
3310 return ret;
3311}
3312
9eefa953
LO		 3313static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3314 int qp_attr_mask,
3315 struct ib_qp_init_attr *qp_init_attr)
3316{
3317 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3318 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3319 struct hns_roce_sqp_context context;
3320 u32 addr;
3321
3322 mutex_lock(&hr_qp->mutex);
3323
3324 if (hr_qp->state == IB_QPS_RESET) {
3325 qp_attr->qp_state = IB_QPS_RESET;
3326 goto done;
3327 }
3328
3329 addr = ROCEE_QP1C_CFG0_0_REG +
3330 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3331 context.qp1c_bytes_4 = roce_read(hr_dev, addr);
3332 context.sq_rq_bt_l = roce_read(hr_dev, addr + 1);
3333 context.qp1c_bytes_12 = roce_read(hr_dev, addr + 2);
3334 context.qp1c_bytes_16 = roce_read(hr_dev, addr + 3);
3335 context.qp1c_bytes_20 = roce_read(hr_dev, addr + 4);
3336 context.cur_rq_wqe_ba_l = roce_read(hr_dev, addr + 5);
3337 context.qp1c_bytes_28 = roce_read(hr_dev, addr + 6);
3338 context.qp1c_bytes_32 = roce_read(hr_dev, addr + 7);
3339 context.cur_sq_wqe_ba_l = roce_read(hr_dev, addr + 8);
3340 context.qp1c_bytes_40 = roce_read(hr_dev, addr + 9);
3341
3342 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3343 QP1C_BYTES_4_QP_STATE_M,
3344 QP1C_BYTES_4_QP_STATE_S);
3345 qp_attr->qp_state = hr_qp->state;
3346 qp_attr->path_mtu = IB_MTU_256;
3347 qp_attr->path_mig_state = IB_MIG_ARMED;
3348 qp_attr->qkey = QKEY_VAL;
3349 qp_attr->rq_psn = 0;
3350 qp_attr->sq_psn = 0;
3351 qp_attr->dest_qp_num = 1;
3352 qp_attr->qp_access_flags = 6;
3353
3354 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3355 QP1C_BYTES_20_PKEY_IDX_M,
3356 QP1C_BYTES_20_PKEY_IDX_S);
3357 qp_attr->port_num = hr_qp->port + 1;
3358 qp_attr->sq_draining = 0;
3359 qp_attr->max_rd_atomic = 0;
3360 qp_attr->max_dest_rd_atomic = 0;
3361 qp_attr->min_rnr_timer = 0;
3362 qp_attr->timeout = 0;
3363 qp_attr->retry_cnt = 0;
3364 qp_attr->rnr_retry = 0;
3365 qp_attr->alt_timeout = 0;
3366
3367done:
3368 qp_attr->cur_qp_state = qp_attr->qp_state;
3369 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3370 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3371 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3372 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3373 qp_attr->cap.max_inline_data = 0;
3374 qp_init_attr->cap = qp_attr->cap;
3375 qp_init_attr->create_flags = 0;
3376
3377 mutex_unlock(&hr_qp->mutex);
3378
3379 return 0;
3380}
3381
3382static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3383 int qp_attr_mask,
3384 struct ib_qp_init_attr *qp_init_attr)
9a443537 3385{
3386 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3387 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3388 struct device *dev = &hr_dev->pdev->dev;
3389 struct hns_roce_qp_context *context;
3390 int tmp_qp_state = 0;
3391 int ret = 0;
3392 int state;
3393
3394 context = kzalloc(sizeof(*context), GFP_KERNEL);
3395 if (!context)
3396 return -ENOMEM;
3397
3398 memset(qp_attr, 0, sizeof(*qp_attr));
3399 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3400
3401 mutex_lock(&hr_qp->mutex);
3402
3403 if (hr_qp->state == IB_QPS_RESET) {
3404 qp_attr->qp_state = IB_QPS_RESET;
3405 goto done;
3406 }
3407
3408 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3409 if (ret) {
3410 dev_err(dev, "query qpc error\n");
3411 ret = -EINVAL;
3412 goto out;
3413 }
3414
3415 state = roce_get_field(context->qpc_bytes_144,
3416 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3417 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3418 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3419 if (tmp_qp_state == -1) {
3420 dev_err(dev, "to_ib_qp_state error\n");
3421 ret = -EINVAL;
3422 goto out;
3423 }
3424 hr_qp->state = (u8)tmp_qp_state;
3425 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3426 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3427 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3428 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3429 qp_attr->path_mig_state = IB_MIG_ARMED;
3430 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3431 qp_attr->qkey = QKEY_VAL;
3432
3433 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3434 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3435 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3436 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3437 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3438 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3439 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3440 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3441 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3442 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3443 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3444 ((roce_get_bit(context->qpc_bytes_4,
3445 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3446 ((roce_get_bit(context->qpc_bytes_4,
3447 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3448
3449 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3450 hr_qp->ibqp.qp_type == IB_QPT_UC) {
d8966fcd
DC		 3451 struct ib_global_route *grh =
3452 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3453
3454 rdma_ah_set_sl(&qp_attr->ah_attr,
3455 roce_get_field(context->qpc_bytes_156,
3456 QP_CONTEXT_QPC_BYTES_156_SL_M,
3457 QP_CONTEXT_QPC_BYTES_156_SL_S));
3458 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3459 grh->flow_label =
3460 roce_get_field(context->qpc_bytes_48,
3461 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3462 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3463 grh->sgid_index =
3464 roce_get_field(context->qpc_bytes_36,
3465 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3466 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3467 grh->hop_limit =
3468 roce_get_field(context->qpc_bytes_44,
3469 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3470 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3471 grh->traffic_class =
3472 roce_get_field(context->qpc_bytes_48,
3473 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3474 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3475
3476 memcpy(grh->dgid.raw, context->dgid,
3477 sizeof(grh->dgid.raw));
9a443537 3478 }
3479
3480 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3481 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3482 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
dd783a21 3483 qp_attr->port_num = hr_qp->port + 1;
9a443537 3484 qp_attr->sq_draining = 0;
3485 qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156,
3486 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3487 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3488 qp_attr->max_dest_rd_atomic = roce_get_field(context->qpc_bytes_32,
3489 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3490 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3491 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3492 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3493 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3494 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3495 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3496 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3497 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3498 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3499 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3500 qp_attr->rnr_retry = context->rnr_retry;
3501
3502done:
3503 qp_attr->cur_qp_state = qp_attr->qp_state;
3504 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3505 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3506
3507 if (!ibqp->uobject) {
3508 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3509 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3510 } else {
3511 qp_attr->cap.max_send_wr = 0;
3512 qp_attr->cap.max_send_sge = 0;
3513 }
3514
3515 qp_init_attr->cap = qp_attr->cap;
3516
3517out:
3518 mutex_unlock(&hr_qp->mutex);
3519 kfree(context);
3520 return ret;
3521}
3522
9eefa953
LO		 3523int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3524 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3525{
3526 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3527
3528 return hr_qp->doorbell_qpn <= 1 ?
3529 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3530 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3531}
d838c481
WHX		 3532
3533static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3534 struct hns_roce_qp *hr_qp,
3535 u32 sdb_issue_ptr,
3536 u32 *sdb_inv_cnt,
3537 u32 *wait_stage)
9a443537 3538{
9a443537 3539 struct device *dev = &hr_dev->pdev->dev;
d838c481
WHX		 3540 u32 sdb_retry_cnt, old_retry;
3541 u32 sdb_send_ptr, old_send;
3542 u32 success_flags = 0;
3543 u32 cur_cnt, old_cnt;
3544 unsigned long end;
3545 u32 send_ptr;
3546 u32 inv_cnt;
3547 u32 tsp_st;
3548
3549 if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3550 *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3551 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3552 hr_qp->qpn, *wait_stage);
3553 return -EINVAL;
3554 }
9a443537 3555
d838c481
WHX		 3556 /* Calculate the total timeout for the entire verification process */
3557 end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3558
3559 if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3560 /* Query db process status, until hw process completely */
3561 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3562 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3563 ROCEE_SDB_PTR_CMP_BITS)) {
3564 if (!time_before(jiffies, end)) {
3565 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3566 hr_qp->qpn, sdb_issue_ptr,
3567 sdb_send_ptr);
3568 return 0;
3569 }
3570
3571 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3572 sdb_send_ptr = roce_read(hr_dev,
9a443537 3573 ROCEE_SDB_SEND_PTR_REG);
d838c481 3574 }
9a443537 3575
d838c481
WHX		 3576 if (roce_get_field(sdb_issue_ptr,
3577 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3578 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3579 roce_get_field(sdb_send_ptr,
3580 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3581 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3582 old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3583 old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
9a443537 3584
9a443537 3585 do {
d838c481
WHX		 3586 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3587 if (roce_get_bit(tsp_st,
3588 ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3589 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3590 return 0;
3591 }
3592
9a443537 3593 if (!time_before(jiffies, end)) {
d838c481
WHX		 3594 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3595 "issue 0x%x send 0x%x.\n",
3596 hr_qp->qpn, sdb_issue_ptr,
3597 sdb_send_ptr);
3598 return 0;
9a443537 3599 }
d838c481
WHX		 3600
3601 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3602
3603 sdb_send_ptr = roce_read(hr_dev,
3604 ROCEE_SDB_SEND_PTR_REG);
3605 sdb_retry_cnt = roce_read(hr_dev,
3606 ROCEE_SDB_RETRY_CNT_REG);
3607 cur_cnt = roce_get_field(sdb_send_ptr,
3608 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3609 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3610 roce_get_field(sdb_retry_cnt,
3611 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3612 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3613 if (!roce_get_bit(tsp_st,
3614 ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3615 old_cnt = roce_get_field(old_send,
3616 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3617 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3618 roce_get_field(old_retry,
3619 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3620 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3621 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3622 success_flags = 1;
3623 } else {
3624 old_cnt = roce_get_field(old_send,
3625 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3626 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
5f110ac4 3627 if (cur_cnt - old_cnt >
3628 SDB_ST_CMP_VAL) {
d838c481 3629 success_flags = 1;
5f110ac4 3630 } else {
3631 send_ptr =
3632 roce_get_field(old_send,
d838c481
WHX		 3633 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3634 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3635 roce_get_field(sdb_retry_cnt,
3636 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3637 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3638 roce_set_field(old_send,
3639 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3640 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3641 send_ptr);
3642 }
3643 }
3644 } while (!success_flags);
3645 }
3646
3647 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3648
3649 /* Get list pointer */
3650 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3651 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3652 hr_qp->qpn, *sdb_inv_cnt);
3653 }
3654
3655 if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3656 /* Query db's list status, until hw reversal */
3657 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3658 while (roce_hw_index_cmp_lt(inv_cnt,
3659 *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3660 ROCEE_SDB_CNT_CMP_BITS)) {
3661 if (!time_before(jiffies, end)) {
3662 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3663 hr_qp->qpn, inv_cnt);
3664 return 0;
3665 }
3666
3667 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3668 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
9a443537 3669 }
d838c481
WHX		 3670
3671 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3672 }
3673
3674 return 0;
3675}
3676
3677static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3678 struct hns_roce_qp *hr_qp,
3679 struct hns_roce_qp_work *qp_work_entry,
3680 int *is_timeout)
3681{
3682 struct device *dev = &hr_dev->pdev->dev;
3683 u32 sdb_issue_ptr;
3684 int ret;
3685
3686 if (hr_qp->state != IB_QPS_RESET) {
3687 /* Set qp to ERR, waiting for hw complete processing all dbs */
3688 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3689 IB_QPS_ERR);
3690 if (ret) {
3691 dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3692 hr_qp->qpn);
3693 return ret;
3694 }
3695
3696 /* Record issued doorbell */
3697 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3698 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3699 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3700
3701 /* Query db process status, until hw process completely */
3702 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3703 &qp_work_entry->sdb_inv_cnt,
3704 &qp_work_entry->db_wait_stage);
3705 if (ret) {
3706 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3707 hr_qp->qpn);
3708 return ret;
3709 }
3710
3711 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3712 qp_work_entry->sche_cnt = 0;
3713 *is_timeout = 1;
3714 return 0;
3715 }
3716
3717 /* Modify qp to reset before destroying qp */
3718 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3719 IB_QPS_RESET);
3720 if (ret) {
3721 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3722 hr_qp->qpn);
3723 return ret;
3724 }
3725 }
3726
3727 return 0;
3728}
3729
3730static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3731{
3732 struct hns_roce_qp_work *qp_work_entry;
3733 struct hns_roce_v1_priv *priv;
3734 struct hns_roce_dev *hr_dev;
3735 struct hns_roce_qp *hr_qp;
3736 struct device *dev;
58c4f0d8 3737 unsigned long qpn;
d838c481
WHX		 3738 int ret;
3739
3740 qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3741 hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3742 dev = &hr_dev->pdev->dev;
016a0059 3743 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481 3744 hr_qp = qp_work_entry->qp;
58c4f0d8 3745 qpn = hr_qp->qpn;
d838c481 3746
58c4f0d8 3747 dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
d838c481
WHX		 3748
3749 qp_work_entry->sche_cnt++;
3750
3751 /* Query db process status, until hw process completely */
3752 ret = check_qp_db_process_status(hr_dev, hr_qp,
3753 qp_work_entry->sdb_issue_ptr,
3754 &qp_work_entry->sdb_inv_cnt,
3755 &qp_work_entry->db_wait_stage);
3756 if (ret) {
3757 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
58c4f0d8 3758 qpn);
d838c481
WHX		 3759 return;
3760 }
3761
3762 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3763 priv->des_qp.requeue_flag) {
3764 queue_work(priv->des_qp.qp_wq, work);
3765 return;
3766 }
3767
3768 /* Modify qp to reset before destroying qp */
3769 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3770 IB_QPS_RESET);
3771 if (ret) {
58c4f0d8 3772 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
d838c481
WHX		 3773 return;
3774 }
3775
3776 hns_roce_qp_remove(hr_dev, hr_qp);
3777 hns_roce_qp_free(hr_dev, hr_qp);
3778
3779 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3780 /* RC QP, release QPN */
58c4f0d8 3781 hns_roce_release_range_qp(hr_dev, qpn, 1);
d838c481
WHX		 3782 kfree(hr_qp);
3783 } else
3784 kfree(hr_to_hr_sqp(hr_qp));
3785
3786 kfree(qp_work_entry);
3787
58c4f0d8 3788 dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
d838c481
WHX		 3789}
3790
3791int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3792{
3793 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3794 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3795 struct device *dev = &hr_dev->pdev->dev;
3796 struct hns_roce_qp_work qp_work_entry;
3797 struct hns_roce_qp_work *qp_work;
3798 struct hns_roce_v1_priv *priv;
3799 struct hns_roce_cq *send_cq, *recv_cq;
3800 int is_user = !!ibqp->pd->uobject;
3801 int is_timeout = 0;
3802 int ret;
3803
3804 ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3805 if (ret) {
3806 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3807 return ret;
9a443537 3808 }
3809
3810 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3811 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3812
3813 hns_roce_lock_cqs(send_cq, recv_cq);
9a443537 3814 if (!is_user) {
3815 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3816 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3817 if (send_cq != recv_cq)
3818 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3819 }
9a443537 3820 hns_roce_unlock_cqs(send_cq, recv_cq);
3821
d838c481
WHX		 3822 if (!is_timeout) {
3823 hns_roce_qp_remove(hr_dev, hr_qp);
3824 hns_roce_qp_free(hr_dev, hr_qp);
9a443537 3825
d838c481
WHX		 3826 /* RC QP, release QPN */
3827 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3828 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3829 }
9a443537 3830
3831 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3832
d838c481 3833 if (is_user)
9a443537 3834 ib_umem_release(hr_qp->umem);
d838c481 3835 else {
9a443537 3836 kfree(hr_qp->sq.wrid);
3837 kfree(hr_qp->rq.wrid);
d838c481 3838
9a443537 3839 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3840 }
9a443537 3841
d838c481
WHX		 3842 if (!is_timeout) {
3843 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3844 kfree(hr_qp);
3845 else
3846 kfree(hr_to_hr_sqp(hr_qp));
3847 } else {
3848 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3849 if (!qp_work)
3850 return -ENOMEM;
3851
3852 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3853 qp_work->ib_dev = &hr_dev->ib_dev;
3854 qp_work->qp = hr_qp;
3855 qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3856 qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3857 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3858 qp_work->sche_cnt = qp_work_entry.sche_cnt;
3859
016a0059 3860 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 3861 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3862 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3863 }
9a443537 3864
3865 return 0;
3866}
3867
afb6b092
SX		 3868int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3869{
3870 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3871 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3872 struct device *dev = &hr_dev->pdev->dev;
3873 u32 cqe_cnt_ori;
3874 u32 cqe_cnt_cur;
3875 u32 cq_buf_size;
3876 int wait_time = 0;
3877 int ret = 0;
3878
3879 hns_roce_free_cq(hr_dev, hr_cq);
3880
3881 /*
3882 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3883 * have been written by checking the CQE counter.
3884 */
3885 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3886 while (1) {
3887 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3888 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3889 break;
3890
3891 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3892 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3893 break;
3894
3895 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3896 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3897 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3898 hr_cq->cqn);
3899 ret = -ETIMEDOUT;
3900 break;
3901 }
3902 wait_time++;
3903 }
3904
3905 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3906
3907 if (ibcq->uobject)
3908 ib_umem_release(hr_cq->umem);
3909 else {
3910 /* Free the buff of stored cq */
3911 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3912 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3913 }
3914
3915 kfree(hr_cq);
3916
3917 return ret;
3918}
3919
08805fdb 3920static const struct hns_roce_hw hns_roce_hw_v1 = {
9a443537 3921 .reset = hns_roce_v1_reset,
3922 .hw_profile = hns_roce_v1_profile,
3923 .hw_init = hns_roce_v1_init,
3924 .hw_exit = hns_roce_v1_exit,
a680f2f3
WHX		 3925 .post_mbox = hns_roce_v1_post_mbox,
3926 .chk_mbox = hns_roce_v1_chk_mbox,
9a443537 3927 .set_gid = hns_roce_v1_set_gid,
3928 .set_mac = hns_roce_v1_set_mac,
3929 .set_mtu = hns_roce_v1_set_mtu,
3930 .write_mtpt = hns_roce_v1_write_mtpt,
3931 .write_cqc = hns_roce_v1_write_cqc,
97f0e39f 3932 .clear_hem = hns_roce_v1_clear_hem,
9a443537 3933 .modify_qp = hns_roce_v1_modify_qp,
3934 .query_qp = hns_roce_v1_query_qp,
3935 .destroy_qp = hns_roce_v1_destroy_qp,
3936 .post_send = hns_roce_v1_post_send,
3937 .post_recv = hns_roce_v1_post_recv,
3938 .req_notify_cq = hns_roce_v1_req_notify_cq,
3939 .poll_cq = hns_roce_v1_poll_cq,
bfcc681b 3940 .dereg_mr = hns_roce_v1_dereg_mr,
afb6b092 3941 .destroy_cq = hns_roce_v1_destroy_cq,
9a443537 3942};
08805fdb
WHX		 3943
3944static const struct of_device_id hns_roce_of_match[] = {
3945 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
3946 {},
3947};
3948MODULE_DEVICE_TABLE(of, hns_roce_of_match);
3949
3950static const struct acpi_device_id hns_roce_acpi_match[] = {
3951 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
3952 {},
3953};
3954MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
3955
3956static int hns_roce_node_match(struct device *dev, void *fwnode)
3957{
3958 return dev->fwnode == fwnode;
3959}
3960
3961static struct
3962platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
3963{
3964 struct device *dev;
3965
3966 /* get the 'device' corresponding to the matching 'fwnode' */
3967 dev = bus_find_device(&platform_bus_type, NULL,
3968 fwnode, hns_roce_node_match);
3969 /* get the platform device */
3970 return dev ? to_platform_device(dev) : NULL;
3971}
3972
3973static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
3974{
3975 struct device *dev = &hr_dev->pdev->dev;
3976 struct platform_device *pdev = NULL;
3977 struct net_device *netdev = NULL;
3978 struct device_node *net_node;
3979 struct resource *res;
3980 int port_cnt = 0;
3981 u8 phy_port;
3982 int ret;
3983 int i;
3984
3985 /* check if we are compatible with the underlying SoC */
3986 if (dev_of_node(dev)) {
3987 const struct of_device_id *of_id;
3988
3989 of_id = of_match_node(hns_roce_of_match, dev->of_node);
3990 if (!of_id) {
3991 dev_err(dev, "device is not compatible!\n");
3992 return -ENXIO;
3993 }
3994 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
3995 if (!hr_dev->hw) {
3996 dev_err(dev, "couldn't get H/W specific DT data!\n");
3997 return -ENXIO;
3998 }
3999 } else if (is_acpi_device_node(dev->fwnode)) {
4000 const struct acpi_device_id *acpi_id;
4001
4002 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4003 if (!acpi_id) {
4004 dev_err(dev, "device is not compatible!\n");
4005 return -ENXIO;
4006 }
4007 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4008 if (!hr_dev->hw) {
4009 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4010 return -ENXIO;
4011 }
4012 } else {
4013 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4014 return -ENXIO;
4015 }
4016
4017 /* get the mapped register base address */
4018 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
4019 if (!res) {
4020 dev_err(dev, "memory resource not found!\n");
4021 return -EINVAL;
4022 }
4023 hr_dev->reg_base = devm_ioremap_resource(dev, res);
4024 if (IS_ERR(hr_dev->reg_base))
4025 return PTR_ERR(hr_dev->reg_base);
4026
4027 /* read the node_guid of IB device from the DT or ACPI */
4028 ret = device_property_read_u8_array(dev, "node-guid",
4029 (u8 *)&hr_dev->ib_dev.node_guid,
4030 GUID_LEN);
4031 if (ret) {
4032 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4033 return ret;
4034 }
4035
4036 /* get the RoCE associated ethernet ports or netdevices */
4037 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4038 if (dev_of_node(dev)) {
4039 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4040 i);
4041 if (!net_node)
4042 continue;
4043 pdev = of_find_device_by_node(net_node);
4044 } else if (is_acpi_device_node(dev->fwnode)) {
4045 struct acpi_reference_args args;
4046 struct fwnode_handle *fwnode;
4047
4048 ret = acpi_node_get_property_reference(dev->fwnode,
4049 "eth-handle",
4050 i, &args);
4051 if (ret)
4052 continue;
4053 fwnode = acpi_fwnode_handle(args.adev);
4054 pdev = hns_roce_find_pdev(fwnode);
4055 } else {
4056 dev_err(dev, "cannot read data from DT or ACPI\n");
4057 return -ENXIO;
4058 }
4059
4060 if (pdev) {
4061 netdev = platform_get_drvdata(pdev);
4062 phy_port = (u8)i;
4063 if (netdev) {
4064 hr_dev->iboe.netdevs[port_cnt] = netdev;
4065 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4066 } else {
4067 dev_err(dev, "no netdev found with pdev %s\n",
4068 pdev->name);
4069 return -ENODEV;
4070 }
4071 port_cnt++;
4072 }
4073 }
4074
4075 if (port_cnt == 0) {
4076 dev_err(dev, "unable to get eth-handle for available ports!\n");
4077 return -EINVAL;
4078 }
4079
4080 hr_dev->caps.num_ports = port_cnt;
4081
4082 /* cmd issue mode: 0 is poll, 1 is event */
4083 hr_dev->cmd_mod = 1;
4084 hr_dev->loop_idc = 0;
4085
4086 /* read the interrupt names from the DT or ACPI */
4087 ret = device_property_read_string_array(dev, "interrupt-names",
4088 hr_dev->irq_names,
4089 HNS_ROCE_MAX_IRQ_NUM);
4090 if (ret < 0) {
4091 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4092 return ret;
4093 }
4094
4095 /* fetch the interrupt numbers */
4096 for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
4097 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4098 if (hr_dev->irq[i] <= 0) {
4099 dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4100 return -EINVAL;
4101 }
4102 }
4103
4104 return 0;
4105}
4106
4107/**
4108 * hns_roce_probe - RoCE driver entrance
4109 * @pdev: pointer to platform device
4110 * Return : int
4111 *
4112 */
4113static int hns_roce_probe(struct platform_device *pdev)
4114{
4115 int ret;
4116 struct hns_roce_dev *hr_dev;
4117 struct device *dev = &pdev->dev;
4118
4119 hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
4120 if (!hr_dev)
4121 return -ENOMEM;
4122
016a0059
WHX		 4123 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4124 if (!hr_dev->priv) {
4125 ret = -ENOMEM;
4126 goto error_failed_kzalloc;
4127 }
4128
08805fdb 4129 hr_dev->pdev = pdev;
13ca970e 4130 hr_dev->dev = dev;
08805fdb
WHX		 4131 platform_set_drvdata(pdev, hr_dev);
4132
4133 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4134 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4135 dev_err(dev, "Not usable DMA addressing mode\n");
4136 ret = -EIO;
4137 goto error_failed_get_cfg;
4138 }
4139
4140 ret = hns_roce_get_cfg(hr_dev);
4141 if (ret) {
4142 dev_err(dev, "Get Configuration failed!\n");
4143 goto error_failed_get_cfg;
4144 }
4145
4146 ret = hns_roce_init(hr_dev);
4147 if (ret) {
4148 dev_err(dev, "RoCE engine init failed!\n");
4149 goto error_failed_get_cfg;
4150 }
4151
4152 return 0;
4153
4154error_failed_get_cfg:
016a0059
WHX		 4155 kfree(hr_dev->priv);
4156
4157error_failed_kzalloc:
08805fdb
WHX		 4158 ib_dealloc_device(&hr_dev->ib_dev);
4159
4160 return ret;
4161}
4162
4163/**
4164 * hns_roce_remove - remove RoCE device
4165 * @pdev: pointer to platform device
4166 */
4167static int hns_roce_remove(struct platform_device *pdev)
4168{
4169 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4170
4171 hns_roce_exit(hr_dev);
016a0059 4172 kfree(hr_dev->priv);
08805fdb
WHX		 4173 ib_dealloc_device(&hr_dev->ib_dev);
4174
4175 return 0;
4176}
4177
4178static struct platform_driver hns_roce_driver = {
4179 .probe = hns_roce_probe,
4180 .remove = hns_roce_remove,
4181 .driver = {
4182 .name = DRV_NAME,
4183 .of_match_table = hns_roce_of_match,
4184 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4185 },
4186};
4187
4188module_platform_driver(hns_roce_driver);
4189
4190MODULE_LICENSE("Dual BSD/GPL");
4191MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4192MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4193MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4194MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)