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IB/hns: Optimize the logic of allocating memory using APIs
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v1.c
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9a443537 1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/platform_device.h>
528f1deb 34#include <linux/acpi.h>
9a443537 35#include <rdma/ib_umem.h>
36#include "hns_roce_common.h"
37#include "hns_roce_device.h"
38#include "hns_roce_cmd.h"
39#include "hns_roce_hem.h"
40#include "hns_roce_hw_v1.h"
41
42static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
43{
44 dseg->lkey = cpu_to_le32(sg->lkey);
45 dseg->addr = cpu_to_le64(sg->addr);
46 dseg->len = cpu_to_le32(sg->length);
47}
48
49static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
50 u32 rkey)
51{
52 rseg->raddr = cpu_to_le64(remote_addr);
53 rseg->rkey = cpu_to_le32(rkey);
54 rseg->len = 0;
55}
56
57int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
58 struct ib_send_wr **bad_wr)
59{
60 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
61 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
62 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
63 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
64 struct hns_roce_wqe_data_seg *dseg = NULL;
65 struct hns_roce_qp *qp = to_hr_qp(ibqp);
66 struct device *dev = &hr_dev->pdev->dev;
67 struct hns_roce_sq_db sq_db;
68 int ps_opcode = 0, i = 0;
69 unsigned long flags = 0;
70 void *wqe = NULL;
71 u32 doorbell[2];
72 int nreq = 0;
73 u32 ind = 0;
74 int ret = 0;
75
07182fa7
LO		 76 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
77 ibqp->qp_type != IB_QPT_RC)) {
78 dev_err(dev, "un-supported QP type\n");
79 *bad_wr = NULL;
80 return -EOPNOTSUPP;
81 }
9a443537 82
07182fa7 83 spin_lock_irqsave(&qp->sq.lock, flags);
9a443537 84 ind = qp->sq_next_wqe;
85 for (nreq = 0; wr; ++nreq, wr = wr->next) {
86 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
87 ret = -ENOMEM;
88 *bad_wr = wr;
89 goto out;
90 }
91
92 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
93 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
94 wr->num_sge, qp->sq.max_gs);
95 ret = -EINVAL;
96 *bad_wr = wr;
97 goto out;
98 }
99
100 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
101 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
102 wr->wr_id;
103
104 /* Corresponding to the RC and RD type wqe process separately */
105 if (ibqp->qp_type == IB_QPT_GSI) {
106 ud_sq_wqe = wqe;
107 roce_set_field(ud_sq_wqe->dmac_h,
108 UD_SEND_WQE_U32_4_DMAC_0_M,
109 UD_SEND_WQE_U32_4_DMAC_0_S,
110 ah->av.mac[0]);
111 roce_set_field(ud_sq_wqe->dmac_h,
112 UD_SEND_WQE_U32_4_DMAC_1_M,
113 UD_SEND_WQE_U32_4_DMAC_1_S,
114 ah->av.mac[1]);
115 roce_set_field(ud_sq_wqe->dmac_h,
116 UD_SEND_WQE_U32_4_DMAC_2_M,
117 UD_SEND_WQE_U32_4_DMAC_2_S,
118 ah->av.mac[2]);
119 roce_set_field(ud_sq_wqe->dmac_h,
120 UD_SEND_WQE_U32_4_DMAC_3_M,
121 UD_SEND_WQE_U32_4_DMAC_3_S,
122 ah->av.mac[3]);
123
124 roce_set_field(ud_sq_wqe->u32_8,
125 UD_SEND_WQE_U32_8_DMAC_4_M,
126 UD_SEND_WQE_U32_8_DMAC_4_S,
127 ah->av.mac[4]);
128 roce_set_field(ud_sq_wqe->u32_8,
129 UD_SEND_WQE_U32_8_DMAC_5_M,
130 UD_SEND_WQE_U32_8_DMAC_5_S,
131 ah->av.mac[5]);
132 roce_set_field(ud_sq_wqe->u32_8,
133 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
134 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
135 HNS_ROCE_WQE_OPCODE_SEND);
136 roce_set_field(ud_sq_wqe->u32_8,
137 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
138 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
139 2);
140 roce_set_bit(ud_sq_wqe->u32_8,
141 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
142 1);
143
144 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
145 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
146 (wr->send_flags & IB_SEND_SOLICITED ?
147 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
148 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
149 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
150
151 roce_set_field(ud_sq_wqe->u32_16,
152 UD_SEND_WQE_U32_16_DEST_QP_M,
153 UD_SEND_WQE_U32_16_DEST_QP_S,
154 ud_wr(wr)->remote_qpn);
155 roce_set_field(ud_sq_wqe->u32_16,
156 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
157 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
158 ah->av.stat_rate);
159
160 roce_set_field(ud_sq_wqe->u32_36,
161 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
162 UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0);
163 roce_set_field(ud_sq_wqe->u32_36,
164 UD_SEND_WQE_U32_36_PRIORITY_M,
165 UD_SEND_WQE_U32_36_PRIORITY_S,
166 ah->av.sl_tclass_flowlabel >>
167 HNS_ROCE_SL_SHIFT);
168 roce_set_field(ud_sq_wqe->u32_36,
169 UD_SEND_WQE_U32_36_SGID_INDEX_M,
170 UD_SEND_WQE_U32_36_SGID_INDEX_S,
7716809e 171 hns_get_gid_index(hr_dev, qp->phy_port,
9a443537 172 ah->av.gid_index));
173
174 roce_set_field(ud_sq_wqe->u32_40,
175 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
176 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
177 ah->av.hop_limit);
178 roce_set_field(ud_sq_wqe->u32_40,
179 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
180 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S, 0);
181
182 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
183
184 ud_sq_wqe->va0_l = (u32)wr->sg_list[0].addr;
185 ud_sq_wqe->va0_h = (wr->sg_list[0].addr) >> 32;
186 ud_sq_wqe->l_key0 = wr->sg_list[0].lkey;
187
188 ud_sq_wqe->va1_l = (u32)wr->sg_list[1].addr;
189 ud_sq_wqe->va1_h = (wr->sg_list[1].addr) >> 32;
190 ud_sq_wqe->l_key1 = wr->sg_list[1].lkey;
191 ind++;
192 } else if (ibqp->qp_type == IB_QPT_RC) {
193 ctrl = wqe;
194 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
195 for (i = 0; i < wr->num_sge; i++)
196 ctrl->msg_length += wr->sg_list[i].length;
197
198 ctrl->sgl_pa_h = 0;
199 ctrl->flag = 0;
200 ctrl->imm_data = send_ieth(wr);
201
202 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
203 /* SO wait for conforming application scenarios */
204 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
205 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
206 (wr->send_flags & IB_SEND_SOLICITED ?
207 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
208 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
209 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
210 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
211 (wr->send_flags & IB_SEND_FENCE ?
212 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
213
c24bf895 214 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
9a443537 215
216 switch (wr->opcode) {
217 case IB_WR_RDMA_READ:
218 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
219 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
220 atomic_wr(wr)->rkey);
221 break;
222 case IB_WR_RDMA_WRITE:
223 case IB_WR_RDMA_WRITE_WITH_IMM:
224 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
225 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
226 atomic_wr(wr)->rkey);
227 break;
228 case IB_WR_SEND:
229 case IB_WR_SEND_WITH_INV:
230 case IB_WR_SEND_WITH_IMM:
231 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
232 break;
233 case IB_WR_LOCAL_INV:
234 break;
235 case IB_WR_ATOMIC_CMP_AND_SWP:
236 case IB_WR_ATOMIC_FETCH_AND_ADD:
237 case IB_WR_LSO:
238 default:
239 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
240 break;
241 }
242 ctrl->flag |= cpu_to_le32(ps_opcode);
c24bf895 243 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
9a443537 244
245 dseg = wqe;
246 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
247 if (ctrl->msg_length >
248 hr_dev->caps.max_sq_inline) {
249 ret = -EINVAL;
250 *bad_wr = wr;
251 dev_err(dev, "inline len(1-%d)=%d, illegal",
252 ctrl->msg_length,
253 hr_dev->caps.max_sq_inline);
254 goto out;
255 }
256 for (i = 0; i < wr->num_sge; i++) {
257 memcpy(wqe, ((void *) (uintptr_t)
258 wr->sg_list[i].addr),
259 wr->sg_list[i].length);
c24bf895 260 wqe += wr->sg_list[i].length;
9a443537 261 }
262 ctrl->flag |= HNS_ROCE_WQE_INLINE;
263 } else {
264 /*sqe num is two */
265 for (i = 0; i < wr->num_sge; i++)
266 set_data_seg(dseg + i, wr->sg_list + i);
267
268 ctrl->flag |= cpu_to_le32(wr->num_sge <<
269 HNS_ROCE_WQE_SGE_NUM_BIT);
270 }
271 ind++;
9a443537 272 }
273 }
274
275out:
276 /* Set DB return */
277 if (likely(nreq)) {
278 qp->sq.head += nreq;
279 /* Memory barrier */
280 wmb();
281
282 sq_db.u32_4 = 0;
283 sq_db.u32_8 = 0;
284 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
285 SQ_DOORBELL_U32_4_SQ_HEAD_S,
286 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
287 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
7716809e 288 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
9a443537 289 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
290 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
291 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
292
293 doorbell[0] = sq_db.u32_4;
294 doorbell[1] = sq_db.u32_8;
295
296 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
297 qp->sq_next_wqe = ind;
298 }
299
300 spin_unlock_irqrestore(&qp->sq.lock, flags);
301
302 return ret;
303}
304
305int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
306 struct ib_recv_wr **bad_wr)
307{
308 int ret = 0;
309 int nreq = 0;
310 int ind = 0;
311 int i = 0;
312 u32 reg_val = 0;
313 unsigned long flags = 0;
314 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
315 struct hns_roce_wqe_data_seg *scat = NULL;
316 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
317 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
318 struct device *dev = &hr_dev->pdev->dev;
319 struct hns_roce_rq_db rq_db;
320 uint32_t doorbell[2] = {0};
321
322 spin_lock_irqsave(&hr_qp->rq.lock, flags);
323 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
324
325 for (nreq = 0; wr; ++nreq, wr = wr->next) {
326 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
327 hr_qp->ibqp.recv_cq)) {
328 ret = -ENOMEM;
329 *bad_wr = wr;
330 goto out;
331 }
332
333 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
334 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
335 wr->num_sge, hr_qp->rq.max_gs);
336 ret = -EINVAL;
337 *bad_wr = wr;
338 goto out;
339 }
340
341 ctrl = get_recv_wqe(hr_qp, ind);
342
343 roce_set_field(ctrl->rwqe_byte_12,
344 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
345 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
346 wr->num_sge);
347
348 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
349
350 for (i = 0; i < wr->num_sge; i++)
351 set_data_seg(scat + i, wr->sg_list + i);
352
353 hr_qp->rq.wrid[ind] = wr->wr_id;
354
355 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
356 }
357
358out:
359 if (likely(nreq)) {
360 hr_qp->rq.head += nreq;
361 /* Memory barrier */
362 wmb();
363
364 if (ibqp->qp_type == IB_QPT_GSI) {
365 /* SW update GSI rq header */
366 reg_val = roce_read(to_hr_dev(ibqp->device),
367 ROCEE_QP1C_CFG3_0_REG +
7716809e 368 QP1C_CFGN_OFFSET * hr_qp->phy_port);
9a443537 369 roce_set_field(reg_val,
370 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
371 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
372 hr_qp->rq.head);
373 roce_write(to_hr_dev(ibqp->device),
374 ROCEE_QP1C_CFG3_0_REG +
7716809e 375 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
9a443537 376 } else {
377 rq_db.u32_4 = 0;
378 rq_db.u32_8 = 0;
379
380 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
381 RQ_DOORBELL_U32_4_RQ_HEAD_S,
382 hr_qp->rq.head);
383 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
384 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
385 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
386 RQ_DOORBELL_U32_8_CMD_S, 1);
387 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
388 1);
389
390 doorbell[0] = rq_db.u32_4;
391 doorbell[1] = rq_db.u32_8;
392
393 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
394 }
395 }
396 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
397
398 return ret;
399}
400
401static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
402 int sdb_mode, int odb_mode)
403{
404 u32 val;
405
406 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
407 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
408 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
409 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
410}
411
412static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
413 u32 odb_mode)
414{
415 u32 val;
416
417 /* Configure SDB/ODB extend mode */
418 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
419 roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
420 roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
421 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
422}
423
424static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
425 u32 sdb_alful)
426{
427 u32 val;
428
429 /* Configure SDB */
430 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
431 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
432 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
433 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
434 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
435 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
436}
437
438static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
439 u32 odb_alful)
440{
441 u32 val;
442
443 /* Configure ODB */
444 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
445 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
446 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
447 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
448 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
449 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
450}
451
452static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
453 u32 ext_sdb_alful)
454{
455 struct device *dev = &hr_dev->pdev->dev;
456 struct hns_roce_v1_priv *priv;
457 struct hns_roce_db_table *db;
458 dma_addr_t sdb_dma_addr;
459 u32 val;
460
461 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
462 db = &priv->db_table;
463
464 /* Configure extend SDB threshold */
465 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
466 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
467
468 /* Configure extend SDB base addr */
469 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
470 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
471
472 /* Configure extend SDB depth */
473 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
474 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
475 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
476 db->ext_db->esdb_dep);
477 /*
478 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
479 * using 4K page, and shift more 32 because of
480 * caculating the high 32 bit value evaluated to hardware.
481 */
482 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
483 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
484 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
485
486 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
487 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
488 ext_sdb_alept, ext_sdb_alful);
489}
490
491static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
492 u32 ext_odb_alful)
493{
494 struct device *dev = &hr_dev->pdev->dev;
495 struct hns_roce_v1_priv *priv;
496 struct hns_roce_db_table *db;
497 dma_addr_t odb_dma_addr;
498 u32 val;
499
500 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
501 db = &priv->db_table;
502
503 /* Configure extend ODB threshold */
504 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
505 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
506
507 /* Configure extend ODB base addr */
508 odb_dma_addr = db->ext_db->odb_buf_list->map;
509 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
510
511 /* Configure extend ODB depth */
512 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
513 roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
514 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
515 db->ext_db->eodb_dep);
516 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
517 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
518 db->ext_db->eodb_dep);
519 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
520
521 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
522 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
523 ext_odb_alept, ext_odb_alful);
524}
525
526static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
527 u32 odb_ext_mod)
528{
529 struct device *dev = &hr_dev->pdev->dev;
530 struct hns_roce_v1_priv *priv;
531 struct hns_roce_db_table *db;
532 dma_addr_t sdb_dma_addr;
533 dma_addr_t odb_dma_addr;
534 int ret = 0;
535
536 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
537 db = &priv->db_table;
538
539 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
540 if (!db->ext_db)
541 return -ENOMEM;
542
543 if (sdb_ext_mod) {
544 db->ext_db->sdb_buf_list = kmalloc(
545 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
546 if (!db->ext_db->sdb_buf_list) {
547 ret = -ENOMEM;
548 goto ext_sdb_buf_fail_out;
549 }
550
551 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
552 HNS_ROCE_V1_EXT_SDB_SIZE,
553 &sdb_dma_addr, GFP_KERNEL);
554 if (!db->ext_db->sdb_buf_list->buf) {
555 ret = -ENOMEM;
556 goto alloc_sq_db_buf_fail;
557 }
558 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
559
560 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
561 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
562 HNS_ROCE_V1_EXT_SDB_ALFUL);
563 } else
564 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
565 HNS_ROCE_V1_SDB_ALFUL);
566
567 if (odb_ext_mod) {
568 db->ext_db->odb_buf_list = kmalloc(
569 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
570 if (!db->ext_db->odb_buf_list) {
571 ret = -ENOMEM;
572 goto ext_odb_buf_fail_out;
573 }
574
575 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
576 HNS_ROCE_V1_EXT_ODB_SIZE,
577 &odb_dma_addr, GFP_KERNEL);
578 if (!db->ext_db->odb_buf_list->buf) {
579 ret = -ENOMEM;
580 goto alloc_otr_db_buf_fail;
581 }
582 db->ext_db->odb_buf_list->map = odb_dma_addr;
583
584 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
585 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
586 HNS_ROCE_V1_EXT_ODB_ALFUL);
587 } else
588 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
589 HNS_ROCE_V1_ODB_ALFUL);
590
591 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
592
593 return 0;
594
595alloc_otr_db_buf_fail:
596 kfree(db->ext_db->odb_buf_list);
597
598ext_odb_buf_fail_out:
599 if (sdb_ext_mod) {
600 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
601 db->ext_db->sdb_buf_list->buf,
602 db->ext_db->sdb_buf_list->map);
603 }
604
605alloc_sq_db_buf_fail:
606 if (sdb_ext_mod)
607 kfree(db->ext_db->sdb_buf_list);
608
609ext_sdb_buf_fail_out:
610 kfree(db->ext_db);
611 return ret;
612}
613
614static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
615{
616 struct device *dev = &hr_dev->pdev->dev;
617 struct hns_roce_v1_priv *priv;
618 struct hns_roce_db_table *db;
619 u32 sdb_ext_mod;
620 u32 odb_ext_mod;
621 u32 sdb_evt_mod;
622 u32 odb_evt_mod;
623 int ret = 0;
624
625 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
626 db = &priv->db_table;
627
628 memset(db, 0, sizeof(*db));
629
630 /* Default DB mode */
631 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
632 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
633 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
634 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
635
636 db->sdb_ext_mod = sdb_ext_mod;
637 db->odb_ext_mod = odb_ext_mod;
638
639 /* Init extend DB */
640 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
641 if (ret) {
642 dev_err(dev, "Failed in extend DB configuration.\n");
643 return ret;
644 }
645
646 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
647
648 return 0;
649}
650
651static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
652{
653 struct device *dev = &hr_dev->pdev->dev;
654 struct hns_roce_v1_priv *priv;
655 struct hns_roce_db_table *db;
656
657 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
658 db = &priv->db_table;
659
660 if (db->sdb_ext_mod) {
661 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
662 db->ext_db->sdb_buf_list->buf,
663 db->ext_db->sdb_buf_list->map);
664 kfree(db->ext_db->sdb_buf_list);
665 }
666
667 if (db->odb_ext_mod) {
668 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
669 db->ext_db->odb_buf_list->buf,
670 db->ext_db->odb_buf_list->map);
671 kfree(db->ext_db->odb_buf_list);
672 }
673
674 kfree(db->ext_db);
675}
676
677static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
678{
679 int ret;
680 int raq_shift = 0;
681 dma_addr_t addr;
682 u32 val;
683 struct hns_roce_v1_priv *priv;
684 struct hns_roce_raq_table *raq;
685 struct device *dev = &hr_dev->pdev->dev;
686
687 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
688 raq = &priv->raq_table;
689
690 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
691 if (!raq->e_raq_buf)
692 return -ENOMEM;
693
694 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
695 &addr, GFP_KERNEL);
696 if (!raq->e_raq_buf->buf) {
697 ret = -ENOMEM;
698 goto err_dma_alloc_raq;
699 }
700 raq->e_raq_buf->map = addr;
701
702 /* Configure raq extended address. 48bit 4K align*/
703 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
704
705 /* Configure raq_shift */
706 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
707 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
708 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
709 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
710 /*
711 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
712 * using 4K page, and shift more 32 because of
713 * caculating the high 32 bit value evaluated to hardware.
714 */
715 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
716 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
717 raq->e_raq_buf->map >> 44);
718 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
719 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
720
721 /* Configure raq threshold */
722 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
723 roce_set_field(val, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
724 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
725 HNS_ROCE_V1_EXT_RAQ_WF);
726 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
727 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
728
729 /* Enable extend raq */
730 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
731 roce_set_field(val,
732 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
733 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
734 POL_TIME_INTERVAL_VAL);
735 roce_set_bit(val, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
736 roce_set_field(val,
737 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
738 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
739 2);
740 roce_set_bit(val,
741 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
742 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
743 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
744
745 /* Enable raq drop */
746 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
747 roce_set_bit(val, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
748 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
749 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
750
751 return 0;
752
753err_dma_alloc_raq:
754 kfree(raq->e_raq_buf);
755 return ret;
756}
757
758static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
759{
760 struct device *dev = &hr_dev->pdev->dev;
761 struct hns_roce_v1_priv *priv;
762 struct hns_roce_raq_table *raq;
763
764 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
765 raq = &priv->raq_table;
766
767 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
768 raq->e_raq_buf->map);
769 kfree(raq->e_raq_buf);
770}
771
772static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
773{
774 u32 val;
775
776 if (enable_flag) {
777 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
778 /* Open all ports */
779 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
780 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
781 ALL_PORT_VAL_OPEN);
782 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
783 } else {
784 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
785 /* Close all ports */
786 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
787 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
788 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
789 }
790}
791
97f0e39f
WHX		 792static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
793{
794 struct device *dev = &hr_dev->pdev->dev;
795 struct hns_roce_v1_priv *priv;
796 int ret;
797
798 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
799
800 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
801 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
802 GFP_KERNEL);
803 if (!priv->bt_table.qpc_buf.buf)
804 return -ENOMEM;
805
806 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
807 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
808 GFP_KERNEL);
809 if (!priv->bt_table.mtpt_buf.buf) {
810 ret = -ENOMEM;
811 goto err_failed_alloc_mtpt_buf;
812 }
813
814 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
815 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
816 GFP_KERNEL);
817 if (!priv->bt_table.cqc_buf.buf) {
818 ret = -ENOMEM;
819 goto err_failed_alloc_cqc_buf;
820 }
821
822 return 0;
823
824err_failed_alloc_cqc_buf:
825 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
826 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
827
828err_failed_alloc_mtpt_buf:
829 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
830 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
831
832 return ret;
833}
834
835static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
836{
837 struct device *dev = &hr_dev->pdev->dev;
838 struct hns_roce_v1_priv *priv;
839
840 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
841
842 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
843 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
844
845 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
846 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
847
848 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
849 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
850}
851
8f3e9f3e
WHX		 852static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
853{
854 struct device *dev = &hr_dev->pdev->dev;
855 struct hns_roce_buf_list *tptr_buf;
856 struct hns_roce_v1_priv *priv;
857
858 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
859 tptr_buf = &priv->tptr_table.tptr_buf;
860
861 /*
862 * This buffer will be used for CQ's tptr(tail pointer), also
863 * named ci(customer index). Every CQ will use 2 bytes to save
864 * cqe ci in hip06. Hardware will read this area to get new ci
865 * when the queue is almost full.
866 */
867 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
868 &tptr_buf->map, GFP_KERNEL);
869 if (!tptr_buf->buf)
870 return -ENOMEM;
871
872 hr_dev->tptr_dma_addr = tptr_buf->map;
873 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
874
875 return 0;
876}
877
878static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
879{
880 struct device *dev = &hr_dev->pdev->dev;
881 struct hns_roce_buf_list *tptr_buf;
882 struct hns_roce_v1_priv *priv;
883
884 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
885 tptr_buf = &priv->tptr_table.tptr_buf;
886
887 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
888 tptr_buf->buf, tptr_buf->map);
889}
890
9a443537 891/**
892 * hns_roce_v1_reset - reset RoCE
893 * @hr_dev: RoCE device struct pointer
894 * @enable: true -- drop reset, false -- reset
895 * return 0 - success , negative --fail
896 */
528f1deb 897int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
9a443537 898{
899 struct device_node *dsaf_node;
900 struct device *dev = &hr_dev->pdev->dev;
901 struct device_node *np = dev->of_node;
528f1deb 902 struct fwnode_handle *fwnode;
9a443537 903 int ret;
904
528f1deb
S		 905 /* check if this is DT/ACPI case */
906 if (dev_of_node(dev)) {
907 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
908 if (!dsaf_node) {
909 dev_err(dev, "could not find dsaf-handle\n");
910 return -EINVAL;
911 }
912 fwnode = &dsaf_node->fwnode;
913 } else if (is_acpi_device_node(dev->fwnode)) {
914 struct acpi_reference_args args;
915
916 ret = acpi_node_get_property_reference(dev->fwnode,
917 "dsaf-handle", 0, &args);
918 if (ret) {
919 dev_err(dev, "could not find dsaf-handle\n");
920 return ret;
921 }
922 fwnode = acpi_fwnode_handle(args.adev);
923 } else {
924 dev_err(dev, "cannot read data from DT or ACPI\n");
925 return -ENXIO;
9a443537 926 }
927
528f1deb 928 ret = hns_dsaf_roce_reset(fwnode, false);
9a443537 929 if (ret)
930 return ret;
931
528f1deb 932 if (dereset) {
9a443537 933 msleep(SLEEP_TIME_INTERVAL);
528f1deb 934 ret = hns_dsaf_roce_reset(fwnode, true);
9a443537 935 }
936
528f1deb 937 return ret;
9a443537 938}
939
940void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
941{
942 int i = 0;
943 struct hns_roce_caps *caps = &hr_dev->caps;
944
945 hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG));
946 hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev,
947 ROCEE_VENDOR_PART_ID_REG));
9a443537 948 hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev,
949 ROCEE_SYS_IMAGE_GUID_L_REG)) |
950 ((u64)le32_to_cpu(roce_read(hr_dev,
951 ROCEE_SYS_IMAGE_GUID_H_REG)) << 32);
8f3e9f3e 952 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
9a443537 953
954 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
955 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
956 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
957 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
958 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
959 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
960 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
961 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
962 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
963 caps->num_aeq_vectors = HNS_ROCE_AEQE_VEC_NUM;
964 caps->num_comp_vectors = HNS_ROCE_COMP_VEC_NUM;
965 caps->num_other_vectors = HNS_ROCE_AEQE_OF_VEC_NUM;
966 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
967 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
968 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
969 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
970 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
971 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
972 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
973 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
974 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
975 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
976 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
977 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
978 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
979 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
9a443537 980 caps->reserved_lkey = 0;
981 caps->reserved_pds = 0;
982 caps->reserved_mrws = 1;
983 caps->reserved_uars = 0;
984 caps->reserved_cqs = 0;
985
986 for (i = 0; i < caps->num_ports; i++)
987 caps->pkey_table_len[i] = 1;
988
989 for (i = 0; i < caps->num_ports; i++) {
990 /* Six ports shared 16 GID in v1 engine */
991 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
992 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
993 caps->num_ports;
994 else
995 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
996 caps->num_ports + 1;
997 }
998
999 for (i = 0; i < caps->num_comp_vectors; i++)
1000 caps->ceqe_depth[i] = HNS_ROCE_V1_NUM_COMP_EQE;
1001
1002 caps->aeqe_depth = HNS_ROCE_V1_NUM_ASYNC_EQE;
1003 caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev,
1004 ROCEE_ACK_DELAY_REG));
1005 caps->max_mtu = IB_MTU_2048;
1006}
1007
1008int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1009{
1010 int ret;
1011 u32 val;
1012 struct device *dev = &hr_dev->pdev->dev;
1013
1014 /* DMAE user config */
1015 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1016 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1017 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1018 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1019 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1020 1 << PAGES_SHIFT_16);
1021 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1022
1023 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1024 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1025 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1026 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1027 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1028 1 << PAGES_SHIFT_16);
1029
1030 ret = hns_roce_db_init(hr_dev);
1031 if (ret) {
1032 dev_err(dev, "doorbell init failed!\n");
1033 return ret;
1034 }
1035
1036 ret = hns_roce_raq_init(hr_dev);
1037 if (ret) {
1038 dev_err(dev, "raq init failed!\n");
1039 goto error_failed_raq_init;
1040 }
1041
1042 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1043
97f0e39f
WHX		 1044 ret = hns_roce_bt_init(hr_dev);
1045 if (ret) {
1046 dev_err(dev, "bt init failed!\n");
1047 goto error_failed_bt_init;
1048 }
1049
8f3e9f3e
WHX		 1050 ret = hns_roce_tptr_init(hr_dev);
1051 if (ret) {
1052 dev_err(dev, "tptr init failed!\n");
1053 goto error_failed_tptr_init;
1054 }
1055
9a443537 1056 return 0;
1057
8f3e9f3e
WHX		 1058error_failed_tptr_init:
1059 hns_roce_bt_free(hr_dev);
1060
97f0e39f
WHX		 1061error_failed_bt_init:
1062 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1063 hns_roce_raq_free(hr_dev);
1064
9a443537 1065error_failed_raq_init:
1066 hns_roce_db_free(hr_dev);
1067 return ret;
1068}
1069
1070void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1071{
8f3e9f3e 1072 hns_roce_tptr_free(hr_dev);
97f0e39f 1073 hns_roce_bt_free(hr_dev);
9a443537 1074 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1075 hns_roce_raq_free(hr_dev);
1076 hns_roce_db_free(hr_dev);
1077}
1078
1079void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
1080 union ib_gid *gid)
1081{
1082 u32 *p = NULL;
1083 u8 gid_idx = 0;
1084
1085 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1086
1087 p = (u32 *)&gid->raw[0];
1088 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1089 (HNS_ROCE_V1_GID_NUM * gid_idx));
1090
1091 p = (u32 *)&gid->raw[4];
1092 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1093 (HNS_ROCE_V1_GID_NUM * gid_idx));
1094
1095 p = (u32 *)&gid->raw[8];
1096 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1097 (HNS_ROCE_V1_GID_NUM * gid_idx));
1098
1099 p = (u32 *)&gid->raw[0xc];
1100 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1101 (HNS_ROCE_V1_GID_NUM * gid_idx));
1102}
1103
1104void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1105{
1106 u32 reg_smac_l;
1107 u16 reg_smac_h;
1108 u16 *p_h;
1109 u32 *p;
1110 u32 val;
1111
1112 p = (u32 *)(&addr[0]);
1113 reg_smac_l = *p;
1114 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1115 PHY_PORT_OFFSET * phy_port);
1116
1117 val = roce_read(hr_dev,
1118 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1119 p_h = (u16 *)(&addr[4]);
1120 reg_smac_h = *p_h;
1121 roce_set_field(val, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1122 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1123 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1124 val);
1125}
1126
1127void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1128 enum ib_mtu mtu)
1129{
1130 u32 val;
1131
1132 val = roce_read(hr_dev,
1133 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1134 roce_set_field(val, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1135 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1136 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1137 val);
1138}
1139
1140int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1141 unsigned long mtpt_idx)
1142{
1143 struct hns_roce_v1_mpt_entry *mpt_entry;
1144 struct scatterlist *sg;
1145 u64 *pages;
1146 int entry;
1147 int i;
1148
1149 /* MPT filled into mailbox buf */
1150 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1151 memset(mpt_entry, 0, sizeof(*mpt_entry));
1152
1153 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1154 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1155 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1156 MPT_BYTE_4_KEY_S, mr->key);
1157 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1158 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1159 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1160 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1161 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1162 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1163 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1164 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1165 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1166 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1167 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1168 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1169 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1170 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1171 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1172 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1173 0);
1174 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1175
1176 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1177 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1178 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1179 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1180
1181 mpt_entry->virt_addr_l = (u32)mr->iova;
1182 mpt_entry->virt_addr_h = (u32)(mr->iova >> 32);
1183 mpt_entry->length = (u32)mr->size;
1184
1185 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1186 MPT_BYTE_28_PD_S, mr->pd);
1187 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1188 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1189 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1190 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1191
1192 /* DMA momery regsiter */
1193 if (mr->type == MR_TYPE_DMA)
1194 return 0;
1195
1196 pages = (u64 *) __get_free_page(GFP_KERNEL);
1197 if (!pages)
1198 return -ENOMEM;
1199
1200 i = 0;
1201 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1202 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1203
1204 /* Directly record to MTPT table firstly 7 entry */
1205 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1206 break;
1207 i++;
1208 }
1209
1210 /* Register user mr */
1211 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1212 switch (i) {
1213 case 0:
1214 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1215 roce_set_field(mpt_entry->mpt_byte_36,
1216 MPT_BYTE_36_PA0_H_M,
1217 MPT_BYTE_36_PA0_H_S,
1218 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1219 break;
1220 case 1:
1221 roce_set_field(mpt_entry->mpt_byte_36,
1222 MPT_BYTE_36_PA1_L_M,
1223 MPT_BYTE_36_PA1_L_S,
1224 cpu_to_le32((u32)(pages[i])));
1225 roce_set_field(mpt_entry->mpt_byte_40,
1226 MPT_BYTE_40_PA1_H_M,
1227 MPT_BYTE_40_PA1_H_S,
1228 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1229 break;
1230 case 2:
1231 roce_set_field(mpt_entry->mpt_byte_40,
1232 MPT_BYTE_40_PA2_L_M,
1233 MPT_BYTE_40_PA2_L_S,
1234 cpu_to_le32((u32)(pages[i])));
1235 roce_set_field(mpt_entry->mpt_byte_44,
1236 MPT_BYTE_44_PA2_H_M,
1237 MPT_BYTE_44_PA2_H_S,
1238 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1239 break;
1240 case 3:
1241 roce_set_field(mpt_entry->mpt_byte_44,
1242 MPT_BYTE_44_PA3_L_M,
1243 MPT_BYTE_44_PA3_L_S,
1244 cpu_to_le32((u32)(pages[i])));
1245 roce_set_field(mpt_entry->mpt_byte_48,
1246 MPT_BYTE_48_PA3_H_M,
1247 MPT_BYTE_48_PA3_H_S,
1248 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_8)));
1249 break;
1250 case 4:
1251 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1252 roce_set_field(mpt_entry->mpt_byte_56,
1253 MPT_BYTE_56_PA4_H_M,
1254 MPT_BYTE_56_PA4_H_S,
1255 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1256 break;
1257 case 5:
1258 roce_set_field(mpt_entry->mpt_byte_56,
1259 MPT_BYTE_56_PA5_L_M,
1260 MPT_BYTE_56_PA5_L_S,
1261 cpu_to_le32((u32)(pages[i])));
1262 roce_set_field(mpt_entry->mpt_byte_60,
1263 MPT_BYTE_60_PA5_H_M,
1264 MPT_BYTE_60_PA5_H_S,
1265 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1266 break;
1267 case 6:
1268 roce_set_field(mpt_entry->mpt_byte_60,
1269 MPT_BYTE_60_PA6_L_M,
1270 MPT_BYTE_60_PA6_L_S,
1271 cpu_to_le32((u32)(pages[i])));
1272 roce_set_field(mpt_entry->mpt_byte_64,
1273 MPT_BYTE_64_PA6_H_M,
1274 MPT_BYTE_64_PA6_H_S,
1275 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1276 break;
1277 default:
1278 break;
1279 }
1280 }
1281
1282 free_page((unsigned long) pages);
1283
1284 mpt_entry->pbl_addr_l = (u32)(mr->pbl_dma_addr);
1285
1286 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1287 MPT_BYTE_12_PBL_ADDR_H_S,
1288 ((u32)(mr->pbl_dma_addr >> 32)));
1289
1290 return 0;
1291}
1292
1293static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1294{
1295 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1296 n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1297}
1298
1299static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1300{
1301 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1302
1303 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1304 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1305 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1306}
1307
1308static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1309{
1310 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1311}
1312
a4be892e 1313void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
9a443537 1314{
1315 u32 doorbell[2];
1316
1317 doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1);
1318 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1319 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1320 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1321 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1322 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1323 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1324 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1325
1326 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1327}
1328
1329static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1330 struct hns_roce_srq *srq)
1331{
1332 struct hns_roce_cqe *cqe, *dest;
1333 u32 prod_index;
1334 int nfreed = 0;
1335 u8 owner_bit;
1336
1337 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1338 ++prod_index) {
1339 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1340 break;
1341 }
1342
1343 /*
1344 * Now backwards through the CQ, removing CQ entries
1345 * that match our QP by overwriting them with next entries.
1346 */
1347 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1348 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1349 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1350 CQE_BYTE_16_LOCAL_QPN_S) &
1351 HNS_ROCE_CQE_QPN_MASK) == qpn) {
1352 /* In v1 engine, not support SRQ */
1353 ++nfreed;
1354 } else if (nfreed) {
1355 dest = get_cqe(hr_cq, (prod_index + nfreed) &
1356 hr_cq->ib_cq.cqe);
1357 owner_bit = roce_get_bit(dest->cqe_byte_4,
1358 CQE_BYTE_4_OWNER_S);
1359 memcpy(dest, cqe, sizeof(*cqe));
1360 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1361 owner_bit);
1362 }
1363 }
1364
1365 if (nfreed) {
1366 hr_cq->cons_index += nfreed;
1367 /*
1368 * Make sure update of buffer contents is done before
1369 * updating consumer index.
1370 */
1371 wmb();
1372
a4be892e 1373 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
9a443537 1374 }
1375}
1376
1377static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1378 struct hns_roce_srq *srq)
1379{
1380 spin_lock_irq(&hr_cq->lock);
1381 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1382 spin_unlock_irq(&hr_cq->lock);
1383}
1384
1385void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1386 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
1387 dma_addr_t dma_handle, int nent, u32 vector)
1388{
1389 struct hns_roce_cq_context *cq_context = NULL;
8f3e9f3e
WHX		 1390 struct hns_roce_buf_list *tptr_buf;
1391 struct hns_roce_v1_priv *priv;
1392 dma_addr_t tptr_dma_addr;
1393 int offset;
1394
1395 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1396 tptr_buf = &priv->tptr_table.tptr_buf;
9a443537 1397
1398 cq_context = mb_buf;
1399 memset(cq_context, 0, sizeof(*cq_context));
1400
8f3e9f3e
WHX		 1401 /* Get the tptr for this CQ. */
1402 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
1403 tptr_dma_addr = tptr_buf->map + offset;
1404 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
9a443537 1405
1406 /* Register cq_context members */
1407 roce_set_field(cq_context->cqc_byte_4,
1408 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
1409 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
1410 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
1411 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
1412 cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4);
1413
1414 cq_context->cq_bt_l = (u32)dma_handle;
1415 cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l);
1416
1417 roce_set_field(cq_context->cqc_byte_12,
1418 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
1419 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
1420 ((u64)dma_handle >> 32));
1421 roce_set_field(cq_context->cqc_byte_12,
1422 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
1423 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
1424 ilog2((unsigned int)nent));
1425 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
1426 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
1427 cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12);
1428
1429 cq_context->cur_cqe_ba0_l = (u32)(mtts[0]);
1430 cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l);
1431
1432 roce_set_field(cq_context->cqc_byte_20,
1433 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
1434 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S,
1435 cpu_to_le32((mtts[0]) >> 32));
1436 /* Dedicated hardware, directly set 0 */
1437 roce_set_field(cq_context->cqc_byte_20,
1438 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
1439 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
1440 /**
1441 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1442 * using 4K page, and shift more 32 because of
1443 * caculating the high 32 bit value evaluated to hardware.
1444 */
1445 roce_set_field(cq_context->cqc_byte_20,
1446 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
1447 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
8f3e9f3e 1448 tptr_dma_addr >> 44);
9a443537 1449 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
1450
8f3e9f3e 1451 cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
9a443537 1452
1453 roce_set_field(cq_context->cqc_byte_32,
1454 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
1455 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
1456 roce_set_bit(cq_context->cqc_byte_32,
1457 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
1458 roce_set_bit(cq_context->cqc_byte_32,
1459 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
1460 roce_set_bit(cq_context->cqc_byte_32,
1461 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
1462 roce_set_bit(cq_context->cqc_byte_32,
1463 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
1464 0);
1465 /*The initial value of cq's ci is 0 */
1466 roce_set_field(cq_context->cqc_byte_32,
1467 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
1468 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
1469 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
1470}
1471
1472int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
1473{
1474 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1475 u32 notification_flag;
1476 u32 doorbell[2];
1477 int ret = 0;
1478
1479 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
1480 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
1481 /*
1482 * flags = 0; Notification Flag = 1, next
1483 * flags = 1; Notification Flag = 0, solocited
1484 */
1485 doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
1486 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1487 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1488 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1489 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1490 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
1491 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1492 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
1493 hr_cq->cqn | notification_flag);
1494
1495 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1496
1497 return ret;
1498}
1499
1500static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
1501 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
1502{
1503 int qpn;
1504 int is_send;
1505 u16 wqe_ctr;
1506 u32 status;
1507 u32 opcode;
1508 struct hns_roce_cqe *cqe;
1509 struct hns_roce_qp *hr_qp;
1510 struct hns_roce_wq *wq;
1511 struct hns_roce_wqe_ctrl_seg *sq_wqe;
1512 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
1513 struct device *dev = &hr_dev->pdev->dev;
1514
1515 /* Find cqe according consumer index */
1516 cqe = next_cqe_sw(hr_cq);
1517 if (!cqe)
1518 return -EAGAIN;
1519
1520 ++hr_cq->cons_index;
1521 /* Memory barrier */
1522 rmb();
1523 /* 0->SQ, 1->RQ */
1524 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
1525
1526 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
1527 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1528 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
1529 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
1530 CQE_BYTE_20_PORT_NUM_S) +
1531 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1532 CQE_BYTE_16_LOCAL_QPN_S) *
1533 HNS_ROCE_MAX_PORTS;
1534 } else {
1535 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1536 CQE_BYTE_16_LOCAL_QPN_S);
1537 }
1538
1539 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
1540 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
1541 if (unlikely(!hr_qp)) {
1542 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
1543 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
1544 return -EINVAL;
1545 }
1546
1547 *cur_qp = hr_qp;
1548 }
1549
1550 wc->qp = &(*cur_qp)->ibqp;
1551 wc->vendor_err = 0;
1552
1553 status = roce_get_field(cqe->cqe_byte_4,
1554 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
1555 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
1556 HNS_ROCE_CQE_STATUS_MASK;
1557 switch (status) {
1558 case HNS_ROCE_CQE_SUCCESS:
1559 wc->status = IB_WC_SUCCESS;
1560 break;
1561 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
1562 wc->status = IB_WC_LOC_LEN_ERR;
1563 break;
1564 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
1565 wc->status = IB_WC_LOC_QP_OP_ERR;
1566 break;
1567 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
1568 wc->status = IB_WC_LOC_PROT_ERR;
1569 break;
1570 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
1571 wc->status = IB_WC_WR_FLUSH_ERR;
1572 break;
1573 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
1574 wc->status = IB_WC_MW_BIND_ERR;
1575 break;
1576 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
1577 wc->status = IB_WC_BAD_RESP_ERR;
1578 break;
1579 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
1580 wc->status = IB_WC_LOC_ACCESS_ERR;
1581 break;
1582 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
1583 wc->status = IB_WC_REM_INV_REQ_ERR;
1584 break;
1585 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
1586 wc->status = IB_WC_REM_ACCESS_ERR;
1587 break;
1588 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
1589 wc->status = IB_WC_REM_OP_ERR;
1590 break;
1591 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
1592 wc->status = IB_WC_RETRY_EXC_ERR;
1593 break;
1594 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
1595 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
1596 break;
1597 default:
1598 wc->status = IB_WC_GENERAL_ERR;
1599 break;
1600 }
1601
1602 /* CQE status error, directly return */
1603 if (wc->status != IB_WC_SUCCESS)
1604 return 0;
1605
1606 if (is_send) {
1607 /* SQ conrespond to CQE */
1608 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
1609 CQE_BYTE_4_WQE_INDEX_M,
1bdab400
S		 1610 CQE_BYTE_4_WQE_INDEX_S)&
1611 ((*cur_qp)->sq.wqe_cnt-1));
9a443537 1612 switch (sq_wqe->flag & HNS_ROCE_WQE_OPCODE_MASK) {
1613 case HNS_ROCE_WQE_OPCODE_SEND:
1614 wc->opcode = IB_WC_SEND;
1615 break;
1616 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
1617 wc->opcode = IB_WC_RDMA_READ;
1618 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
1619 break;
1620 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
1621 wc->opcode = IB_WC_RDMA_WRITE;
1622 break;
1623 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
1624 wc->opcode = IB_WC_LOCAL_INV;
1625 break;
1626 case HNS_ROCE_WQE_OPCODE_UD_SEND:
1627 wc->opcode = IB_WC_SEND;
1628 break;
1629 default:
1630 wc->status = IB_WC_GENERAL_ERR;
1631 break;
1632 }
1633 wc->wc_flags = (sq_wqe->flag & HNS_ROCE_WQE_IMM ?
1634 IB_WC_WITH_IMM : 0);
1635
1636 wq = &(*cur_qp)->sq;
1637 if ((*cur_qp)->sq_signal_bits) {
1638 /*
1639 * If sg_signal_bit is 1,
1640 * firstly tail pointer updated to wqe
1641 * which current cqe correspond to
1642 */
1643 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
1644 CQE_BYTE_4_WQE_INDEX_M,
1645 CQE_BYTE_4_WQE_INDEX_S);
1646 wq->tail += (wqe_ctr - (u16)wq->tail) &
1647 (wq->wqe_cnt - 1);
1648 }
1649 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
1650 ++wq->tail;
1651 } else {
1652 /* RQ conrespond to CQE */
1653 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
1654 opcode = roce_get_field(cqe->cqe_byte_4,
1655 CQE_BYTE_4_OPERATION_TYPE_M,
1656 CQE_BYTE_4_OPERATION_TYPE_S) &
1657 HNS_ROCE_CQE_OPCODE_MASK;
1658 switch (opcode) {
1659 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
1660 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
1661 wc->wc_flags = IB_WC_WITH_IMM;
1662 wc->ex.imm_data = le32_to_cpu(cqe->immediate_data);
1663 break;
1664 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
1665 if (roce_get_bit(cqe->cqe_byte_4,
1666 CQE_BYTE_4_IMM_INDICATOR_S)) {
1667 wc->opcode = IB_WC_RECV;
1668 wc->wc_flags = IB_WC_WITH_IMM;
1669 wc->ex.imm_data = le32_to_cpu(
1670 cqe->immediate_data);
1671 } else {
1672 wc->opcode = IB_WC_RECV;
1673 wc->wc_flags = 0;
1674 }
1675 break;
1676 default:
1677 wc->status = IB_WC_GENERAL_ERR;
1678 break;
1679 }
1680
1681 /* Update tail pointer, record wr_id */
1682 wq = &(*cur_qp)->rq;
1683 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
1684 ++wq->tail;
1685 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
1686 CQE_BYTE_20_SL_S);
1687 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
1688 CQE_BYTE_20_REMOTE_QPN_M,
1689 CQE_BYTE_20_REMOTE_QPN_S);
1690 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
1691 CQE_BYTE_20_GRH_PRESENT_S) ?
1692 IB_WC_GRH : 0);
1693 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
1694 CQE_BYTE_28_P_KEY_IDX_M,
1695 CQE_BYTE_28_P_KEY_IDX_S);
1696 }
1697
1698 return 0;
1699}
1700
1701int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
1702{
1703 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
1704 struct hns_roce_qp *cur_qp = NULL;
1705 unsigned long flags;
1706 int npolled;
1707 int ret = 0;
1708
1709 spin_lock_irqsave(&hr_cq->lock, flags);
1710
1711 for (npolled = 0; npolled < num_entries; ++npolled) {
1712 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
1713 if (ret)
1714 break;
1715 }
1716
8f3e9f3e
WHX		 1717 if (npolled) {
1718 *hr_cq->tptr_addr = hr_cq->cons_index &
1719 ((hr_cq->cq_depth << 1) - 1);
1720
1721 /* Memroy barrier */
1722 wmb();
a4be892e 1723 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
8f3e9f3e 1724 }
9a443537 1725
1726 spin_unlock_irqrestore(&hr_cq->lock, flags);
1727
1728 if (ret == 0 || ret == -EAGAIN)
1729 return npolled;
1730 else
1731 return ret;
1732}
1733
97f0e39f
WHX		 1734int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
1735 struct hns_roce_hem_table *table, int obj)
1736{
1737 struct device *dev = &hr_dev->pdev->dev;
1738 struct hns_roce_v1_priv *priv;
1739 unsigned long end = 0, flags = 0;
1740 uint32_t bt_cmd_val[2] = {0};
1741 void __iomem *bt_cmd;
1742 u64 bt_ba = 0;
1743
1744 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1745
1746 switch (table->type) {
1747 case HEM_TYPE_QPC:
1748 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
1749 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
1750 bt_ba = priv->bt_table.qpc_buf.map >> 12;
1751 break;
1752 case HEM_TYPE_MTPT:
1753 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
1754 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
1755 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
1756 break;
1757 case HEM_TYPE_CQC:
1758 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
1759 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
1760 bt_ba = priv->bt_table.cqc_buf.map >> 12;
1761 break;
1762 case HEM_TYPE_SRQC:
1763 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
1764 return -EINVAL;
1765 default:
1766 return 0;
1767 }
1768 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
1769 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
1770 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
1771 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
1772
1773 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
1774
1775 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
1776
1777 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
1778 while (1) {
1779 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
1780 if (!(time_before(jiffies, end))) {
1781 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
1782 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
1783 flags);
1784 return -EBUSY;
1785 }
1786 } else {
1787 break;
1788 }
1789 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
1790 }
1791
1792 bt_cmd_val[0] = (uint32_t)bt_ba;
1793 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
1794 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
1795 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
1796
1797 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
1798
1799 return 0;
1800}
1801
9a443537 1802static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
1803 struct hns_roce_mtt *mtt,
1804 enum hns_roce_qp_state cur_state,
1805 enum hns_roce_qp_state new_state,
1806 struct hns_roce_qp_context *context,
1807 struct hns_roce_qp *hr_qp)
1808{
1809 static const u16
1810 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
1811 [HNS_ROCE_QP_STATE_RST] = {
1812 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
1813 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
1814 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
1815 },
1816 [HNS_ROCE_QP_STATE_INIT] = {
1817 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
1818 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
1819 /* Note: In v1 engine, HW doesn't support RST2INIT.
1820 * We use RST2INIT cmd instead of INIT2INIT.
1821 */
1822 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
1823 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
1824 },
1825 [HNS_ROCE_QP_STATE_RTR] = {
1826 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
1827 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
1828 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
1829 },
1830 [HNS_ROCE_QP_STATE_RTS] = {
1831 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
1832 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
1833 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
1834 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
1835 },
1836 [HNS_ROCE_QP_STATE_SQD] = {
1837 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
1838 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
1839 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
1840 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
1841 },
1842 [HNS_ROCE_QP_STATE_ERR] = {
1843 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
1844 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
1845 }
1846 };
1847
1848 struct hns_roce_cmd_mailbox *mailbox;
1849 struct device *dev = &hr_dev->pdev->dev;
1850 int ret = 0;
1851
1852 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
1853 new_state >= HNS_ROCE_QP_NUM_STATE ||
1854 !op[cur_state][new_state]) {
1855 dev_err(dev, "[modify_qp]not support state %d to %d\n",
1856 cur_state, new_state);
1857 return -EINVAL;
1858 }
1859
1860 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
1861 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
1862 HNS_ROCE_CMD_2RST_QP,
1863 HNS_ROCE_CMD_TIME_CLASS_A);
1864
1865 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
1866 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
1867 HNS_ROCE_CMD_2ERR_QP,
1868 HNS_ROCE_CMD_TIME_CLASS_A);
1869
1870 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1871 if (IS_ERR(mailbox))
1872 return PTR_ERR(mailbox);
1873
1874 memcpy(mailbox->buf, context, sizeof(*context));
1875
1876 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
1877 op[cur_state][new_state],
1878 HNS_ROCE_CMD_TIME_CLASS_C);
1879
1880 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1881 return ret;
1882}
1883
1884static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
1885 int attr_mask, enum ib_qp_state cur_state,
1886 enum ib_qp_state new_state)
1887{
1888 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
1889 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
1890 struct hns_roce_sqp_context *context;
1891 struct device *dev = &hr_dev->pdev->dev;
1892 dma_addr_t dma_handle = 0;
1893 int rq_pa_start;
1894 u32 reg_val;
1895 u64 *mtts;
1896 u32 *addr;
1897
1898 context = kzalloc(sizeof(*context), GFP_KERNEL);
1899 if (!context)
1900 return -ENOMEM;
1901
1902 /* Search QP buf's MTTs */
1903 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
1904 hr_qp->mtt.first_seg, &dma_handle);
1905 if (!mtts) {
1906 dev_err(dev, "qp buf pa find failed\n");
1907 goto out;
1908 }
1909
1910 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1911 roce_set_field(context->qp1c_bytes_4,
1912 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
1913 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
1914 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
1915 roce_set_field(context->qp1c_bytes_4,
1916 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
1917 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
1918 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
1919 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
1920 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
1921
1922 context->sq_rq_bt_l = (u32)(dma_handle);
1923 roce_set_field(context->qp1c_bytes_12,
1924 QP1C_BYTES_12_SQ_RQ_BT_H_M,
1925 QP1C_BYTES_12_SQ_RQ_BT_H_S,
1926 ((u32)(dma_handle >> 32)));
1927
1928 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
1929 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
1930 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
7716809e 1931 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
9a443537 1932 roce_set_bit(context->qp1c_bytes_16,
1933 QP1C_BYTES_16_SIGNALING_TYPE_S,
1934 hr_qp->sq_signal_bits);
9a443537 1935 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
1936 1);
1937 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
1938 1);
1939 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
1940 0);
1941
1942 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
1943 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
1944 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
1945 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
1946
1947 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
1948 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
1949
1950 roce_set_field(context->qp1c_bytes_28,
1951 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
1952 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
1953 (mtts[rq_pa_start]) >> 32);
1954 roce_set_field(context->qp1c_bytes_28,
1955 QP1C_BYTES_28_RQ_CUR_IDX_M,
1956 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
1957
1958 roce_set_field(context->qp1c_bytes_32,
1959 QP1C_BYTES_32_RX_CQ_NUM_M,
1960 QP1C_BYTES_32_RX_CQ_NUM_S,
1961 to_hr_cq(ibqp->recv_cq)->cqn);
1962 roce_set_field(context->qp1c_bytes_32,
1963 QP1C_BYTES_32_TX_CQ_NUM_M,
1964 QP1C_BYTES_32_TX_CQ_NUM_S,
1965 to_hr_cq(ibqp->send_cq)->cqn);
1966
1967 context->cur_sq_wqe_ba_l = (u32)mtts[0];
1968
1969 roce_set_field(context->qp1c_bytes_40,
1970 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
1971 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
1972 (mtts[0]) >> 32);
1973 roce_set_field(context->qp1c_bytes_40,
1974 QP1C_BYTES_40_SQ_CUR_IDX_M,
1975 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
1976
1977 /* Copy context to QP1C register */
1978 addr = (u32 *)(hr_dev->reg_base + ROCEE_QP1C_CFG0_0_REG +
7716809e 1979 hr_qp->phy_port * sizeof(*context));
9a443537 1980
1981 writel(context->qp1c_bytes_4, addr);
1982 writel(context->sq_rq_bt_l, addr + 1);
1983 writel(context->qp1c_bytes_12, addr + 2);
1984 writel(context->qp1c_bytes_16, addr + 3);
1985 writel(context->qp1c_bytes_20, addr + 4);
1986 writel(context->cur_rq_wqe_ba_l, addr + 5);
1987 writel(context->qp1c_bytes_28, addr + 6);
1988 writel(context->qp1c_bytes_32, addr + 7);
1989 writel(context->cur_sq_wqe_ba_l, addr + 8);
c24bf895 1990 writel(context->qp1c_bytes_40, addr + 9);
9a443537 1991 }
1992
1993 /* Modify QP1C status */
1994 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 1995 hr_qp->phy_port * sizeof(*context));
9a443537 1996 roce_set_field(reg_val, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
1997 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
1998 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 1999 hr_qp->phy_port * sizeof(*context), reg_val);
9a443537 2000
2001 hr_qp->state = new_state;
2002 if (new_state == IB_QPS_RESET) {
2003 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2004 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2005 if (ibqp->send_cq != ibqp->recv_cq)
2006 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2007 hr_qp->qpn, NULL);
2008
2009 hr_qp->rq.head = 0;
2010 hr_qp->rq.tail = 0;
2011 hr_qp->sq.head = 0;
2012 hr_qp->sq.tail = 0;
2013 hr_qp->sq_next_wqe = 0;
2014 }
2015
2016 kfree(context);
2017 return 0;
2018
2019out:
2020 kfree(context);
2021 return -EINVAL;
2022}
2023
2024static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2025 int attr_mask, enum ib_qp_state cur_state,
2026 enum ib_qp_state new_state)
2027{
2028 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2029 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2030 struct device *dev = &hr_dev->pdev->dev;
2031 struct hns_roce_qp_context *context;
9a443537 2032 dma_addr_t dma_handle_2 = 0;
2033 dma_addr_t dma_handle = 0;
2034 uint32_t doorbell[2] = {0};
2035 int rq_pa_start = 0;
9a443537 2036 u64 *mtts_2 = NULL;
2037 int ret = -EINVAL;
2038 u64 *mtts = NULL;
2039 int port;
2040 u8 *dmac;
2041 u8 *smac;
2042
2043 context = kzalloc(sizeof(*context), GFP_KERNEL);
2044 if (!context)
2045 return -ENOMEM;
2046
2047 /* Search qp buf's mtts */
2048 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2049 hr_qp->mtt.first_seg, &dma_handle);
2050 if (mtts == NULL) {
2051 dev_err(dev, "qp buf pa find failed\n");
2052 goto out;
2053 }
2054
2055 /* Search IRRL's mtts */
2056 mtts_2 = hns_roce_table_find(&hr_dev->qp_table.irrl_table, hr_qp->qpn,
2057 &dma_handle_2);
2058 if (mtts_2 == NULL) {
2059 dev_err(dev, "qp irrl_table find failed\n");
2060 goto out;
2061 }
2062
2063 /*
2064 *Reset to init
2065 * Mandatory param:
2066 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2067 * Optional param: NA
2068 */
2069 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2070 roce_set_field(context->qpc_bytes_4,
2071 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2072 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2073 to_hr_qp_type(hr_qp->ibqp.qp_type));
2074
2075 roce_set_bit(context->qpc_bytes_4,
2076 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2077 roce_set_bit(context->qpc_bytes_4,
2078 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2079 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2080 roce_set_bit(context->qpc_bytes_4,
2081 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2082 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2083 );
2084 roce_set_bit(context->qpc_bytes_4,
2085 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2086 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2087 );
2088 roce_set_bit(context->qpc_bytes_4,
2089 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2090 roce_set_field(context->qpc_bytes_4,
2091 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2092 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2093 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2094 roce_set_field(context->qpc_bytes_4,
2095 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2096 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2097 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2098 roce_set_field(context->qpc_bytes_4,
2099 QP_CONTEXT_QPC_BYTES_4_PD_M,
2100 QP_CONTEXT_QPC_BYTES_4_PD_S,
2101 to_hr_pd(ibqp->pd)->pdn);
2102 hr_qp->access_flags = attr->qp_access_flags;
2103 roce_set_field(context->qpc_bytes_8,
2104 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2105 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2106 to_hr_cq(ibqp->send_cq)->cqn);
2107 roce_set_field(context->qpc_bytes_8,
2108 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2109 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2110 to_hr_cq(ibqp->recv_cq)->cqn);
2111
2112 if (ibqp->srq)
2113 roce_set_field(context->qpc_bytes_12,
2114 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2115 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2116 to_hr_srq(ibqp->srq)->srqn);
2117
2118 roce_set_field(context->qpc_bytes_12,
2119 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2120 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2121 attr->pkey_index);
2122 hr_qp->pkey_index = attr->pkey_index;
2123 roce_set_field(context->qpc_bytes_16,
2124 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2125 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2126
2127 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2128 roce_set_field(context->qpc_bytes_4,
2129 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2130 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2131 to_hr_qp_type(hr_qp->ibqp.qp_type));
2132 roce_set_bit(context->qpc_bytes_4,
2133 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2134 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2135 roce_set_bit(context->qpc_bytes_4,
2136 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2137 !!(attr->qp_access_flags &
2138 IB_ACCESS_REMOTE_READ));
2139 roce_set_bit(context->qpc_bytes_4,
2140 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2141 !!(attr->qp_access_flags &
2142 IB_ACCESS_REMOTE_WRITE));
2143 } else {
2144 roce_set_bit(context->qpc_bytes_4,
2145 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2146 !!(hr_qp->access_flags &
2147 IB_ACCESS_REMOTE_READ));
2148 roce_set_bit(context->qpc_bytes_4,
2149 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2150 !!(hr_qp->access_flags &
2151 IB_ACCESS_REMOTE_WRITE));
2152 }
2153
2154 roce_set_bit(context->qpc_bytes_4,
2155 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2156 roce_set_field(context->qpc_bytes_4,
2157 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2158 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2159 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2160 roce_set_field(context->qpc_bytes_4,
2161 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2162 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2163 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2164 roce_set_field(context->qpc_bytes_4,
2165 QP_CONTEXT_QPC_BYTES_4_PD_M,
2166 QP_CONTEXT_QPC_BYTES_4_PD_S,
2167 to_hr_pd(ibqp->pd)->pdn);
2168
2169 roce_set_field(context->qpc_bytes_8,
2170 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2171 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2172 to_hr_cq(ibqp->send_cq)->cqn);
2173 roce_set_field(context->qpc_bytes_8,
2174 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2175 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2176 to_hr_cq(ibqp->recv_cq)->cqn);
2177
2178 if (ibqp->srq)
2179 roce_set_field(context->qpc_bytes_12,
2180 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2181 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2182 to_hr_srq(ibqp->srq)->srqn);
2183 if (attr_mask & IB_QP_PKEY_INDEX)
2184 roce_set_field(context->qpc_bytes_12,
2185 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2186 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2187 attr->pkey_index);
2188 else
2189 roce_set_field(context->qpc_bytes_12,
2190 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2191 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2192 hr_qp->pkey_index);
2193
2194 roce_set_field(context->qpc_bytes_16,
2195 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2196 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2197 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2198 if ((attr_mask & IB_QP_ALT_PATH) ||
2199 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2200 (attr_mask & IB_QP_PKEY_INDEX) ||
2201 (attr_mask & IB_QP_QKEY)) {
2202 dev_err(dev, "INIT2RTR attr_mask error\n");
2203 goto out;
2204 }
2205
2206 dmac = (u8 *)attr->ah_attr.dmac;
2207
2208 context->sq_rq_bt_l = (u32)(dma_handle);
2209 roce_set_field(context->qpc_bytes_24,
2210 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2211 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2212 ((u32)(dma_handle >> 32)));
2213 roce_set_bit(context->qpc_bytes_24,
2214 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2215 1);
2216 roce_set_field(context->qpc_bytes_24,
2217 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2218 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2219 attr->min_rnr_timer);
2220 context->irrl_ba_l = (u32)(dma_handle_2);
2221 roce_set_field(context->qpc_bytes_32,
2222 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2223 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2224 ((u32)(dma_handle_2 >> 32)) &
2225 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2226 roce_set_field(context->qpc_bytes_32,
2227 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2228 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2229 roce_set_bit(context->qpc_bytes_32,
2230 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2231 1);
2232 roce_set_bit(context->qpc_bytes_32,
2233 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2234 hr_qp->sq_signal_bits);
2235
2236 for (port = 0; port < hr_dev->caps.num_ports; port++) {
2237 smac = (u8 *)hr_dev->dev_addr[port];
2238 dev_dbg(dev, "smac: %2x: %2x: %2x: %2x: %2x: %2x\n",
2239 smac[0], smac[1], smac[2], smac[3], smac[4],
2240 smac[5]);
2241 if ((dmac[0] == smac[0]) && (dmac[1] == smac[1]) &&
2242 (dmac[2] == smac[2]) && (dmac[3] == smac[3]) &&
2243 (dmac[4] == smac[4]) && (dmac[5] == smac[5])) {
2244 roce_set_bit(context->qpc_bytes_32,
2245 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S,
2246 1);
2247 break;
2248 }
2249 }
2250
2251 if (hr_dev->loop_idc == 0x1)
2252 roce_set_bit(context->qpc_bytes_32,
2253 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2254
2255 roce_set_bit(context->qpc_bytes_32,
2256 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2257 attr->ah_attr.ah_flags);
2258 roce_set_field(context->qpc_bytes_32,
2259 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2260 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2261 ilog2((unsigned int)attr->max_dest_rd_atomic));
2262
2263 roce_set_field(context->qpc_bytes_36,
2264 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2265 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2266 attr->dest_qp_num);
2267
2268 /* Configure GID index */
2269 roce_set_field(context->qpc_bytes_36,
2270 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2271 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2272 hns_get_gid_index(hr_dev,
2273 attr->ah_attr.port_num - 1,
2274 attr->ah_attr.grh.sgid_index));
2275
2276 memcpy(&(context->dmac_l), dmac, 4);
2277
2278 roce_set_field(context->qpc_bytes_44,
2279 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2280 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2281 *((u16 *)(&dmac[4])));
2282 roce_set_field(context->qpc_bytes_44,
2283 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2284 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2285 attr->ah_attr.static_rate);
2286 roce_set_field(context->qpc_bytes_44,
2287 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2288 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2289 attr->ah_attr.grh.hop_limit);
2290
2291 roce_set_field(context->qpc_bytes_48,
2292 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2293 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2294 attr->ah_attr.grh.flow_label);
2295 roce_set_field(context->qpc_bytes_48,
2296 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2297 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2298 attr->ah_attr.grh.traffic_class);
2299 roce_set_field(context->qpc_bytes_48,
2300 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2301 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2302
2303 memcpy(context->dgid, attr->ah_attr.grh.dgid.raw,
2304 sizeof(attr->ah_attr.grh.dgid.raw));
2305
2306 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2307 roce_get_field(context->qpc_bytes_44,
2308 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2309 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2310
2311 roce_set_field(context->qpc_bytes_68,
2312 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
1fad5fab
LO		 2313 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2314 hr_qp->rq.head);
9a443537 2315 roce_set_field(context->qpc_bytes_68,
2316 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2317 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2318
2319 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2320 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2321
2322 roce_set_field(context->qpc_bytes_76,
2323 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2324 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2325 mtts[rq_pa_start] >> 32);
2326 roce_set_field(context->qpc_bytes_76,
2327 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2328 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2329
2330 context->rx_rnr_time = 0;
2331
2332 roce_set_field(context->qpc_bytes_84,
2333 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2334 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2335 attr->rq_psn - 1);
2336 roce_set_field(context->qpc_bytes_84,
2337 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2338 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2339
2340 roce_set_field(context->qpc_bytes_88,
2341 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2342 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2343 attr->rq_psn);
2344 roce_set_bit(context->qpc_bytes_88,
2345 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2346 roce_set_bit(context->qpc_bytes_88,
2347 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2348 roce_set_field(context->qpc_bytes_88,
2349 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2350 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2351 0);
2352 roce_set_field(context->qpc_bytes_88,
2353 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2354 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2355 0);
2356
2357 context->dma_length = 0;
2358 context->r_key = 0;
2359 context->va_l = 0;
2360 context->va_h = 0;
2361
2362 roce_set_field(context->qpc_bytes_108,
2363 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2364 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2365 roce_set_bit(context->qpc_bytes_108,
2366 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2367 roce_set_bit(context->qpc_bytes_108,
2368 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
2369
2370 roce_set_field(context->qpc_bytes_112,
2371 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
2372 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
2373 roce_set_field(context->qpc_bytes_112,
2374 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
2375 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
2376
2377 /* For chip resp ack */
2378 roce_set_field(context->qpc_bytes_156,
2379 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2380 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 2381 hr_qp->phy_port);
9a443537 2382 roce_set_field(context->qpc_bytes_156,
2383 QP_CONTEXT_QPC_BYTES_156_SL_M,
2384 QP_CONTEXT_QPC_BYTES_156_SL_S, attr->ah_attr.sl);
2385 hr_qp->sl = attr->ah_attr.sl;
2386 } else if (cur_state == IB_QPS_RTR &&
2387 new_state == IB_QPS_RTS) {
2388 /* If exist optional param, return error */
2389 if ((attr_mask & IB_QP_ALT_PATH) ||
2390 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2391 (attr_mask & IB_QP_QKEY) ||
2392 (attr_mask & IB_QP_PATH_MIG_STATE) ||
2393 (attr_mask & IB_QP_CUR_STATE) ||
2394 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
2395 dev_err(dev, "RTR2RTS attr_mask error\n");
2396 goto out;
2397 }
2398
2399 context->rx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
2400
2401 roce_set_field(context->qpc_bytes_120,
2402 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
2403 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
2404 (mtts[0]) >> 32);
2405
2406 roce_set_field(context->qpc_bytes_124,
2407 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
2408 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
2409 roce_set_field(context->qpc_bytes_124,
2410 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
2411 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
2412
2413 roce_set_field(context->qpc_bytes_128,
2414 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
2415 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
2416 attr->sq_psn);
2417 roce_set_bit(context->qpc_bytes_128,
2418 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
2419 roce_set_field(context->qpc_bytes_128,
2420 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
2421 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
2422 0);
2423 roce_set_bit(context->qpc_bytes_128,
2424 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
2425
2426 roce_set_field(context->qpc_bytes_132,
2427 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
2428 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
2429 roce_set_field(context->qpc_bytes_132,
2430 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
2431 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
2432
2433 roce_set_field(context->qpc_bytes_136,
2434 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
2435 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
2436 attr->sq_psn);
2437 roce_set_field(context->qpc_bytes_136,
2438 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
2439 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
2440 attr->sq_psn);
2441
2442 roce_set_field(context->qpc_bytes_140,
2443 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
2444 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
2445 (attr->sq_psn >> SQ_PSN_SHIFT));
2446 roce_set_field(context->qpc_bytes_140,
2447 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
2448 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
2449 roce_set_bit(context->qpc_bytes_140,
2450 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
2451
9a443537 2452 roce_set_field(context->qpc_bytes_148,
2453 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
2454 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
2455 roce_set_field(context->qpc_bytes_148,
2456 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
7c7a4ea1
LO		 2457 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
2458 attr->retry_cnt);
9a443537 2459 roce_set_field(context->qpc_bytes_148,
2460 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
7c7a4ea1
LO		 2461 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
2462 attr->rnr_retry);
9a443537 2463 roce_set_field(context->qpc_bytes_148,
2464 QP_CONTEXT_QPC_BYTES_148_LSN_M,
2465 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
2466
2467 context->rnr_retry = 0;
2468
2469 roce_set_field(context->qpc_bytes_156,
2470 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
2471 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
2472 attr->retry_cnt);
c6c3bfea
LO		 2473 if (attr->timeout < 0x12) {
2474 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
2475 attr->timeout);
2476 roce_set_field(context->qpc_bytes_156,
2477 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
2478 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
2479 0x12);
2480 } else {
2481 roce_set_field(context->qpc_bytes_156,
2482 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
2483 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
2484 attr->timeout);
2485 }
9a443537 2486 roce_set_field(context->qpc_bytes_156,
2487 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
2488 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
2489 attr->rnr_retry);
2490 roce_set_field(context->qpc_bytes_156,
2491 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2492 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 2493 hr_qp->phy_port);
9a443537 2494 roce_set_field(context->qpc_bytes_156,
2495 QP_CONTEXT_QPC_BYTES_156_SL_M,
2496 QP_CONTEXT_QPC_BYTES_156_SL_S, attr->ah_attr.sl);
2497 hr_qp->sl = attr->ah_attr.sl;
2498 roce_set_field(context->qpc_bytes_156,
2499 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
2500 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
2501 ilog2((unsigned int)attr->max_rd_atomic));
2502 roce_set_field(context->qpc_bytes_156,
2503 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
2504 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
2505 context->pkt_use_len = 0;
2506
2507 roce_set_field(context->qpc_bytes_164,
2508 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
2509 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
2510 roce_set_field(context->qpc_bytes_164,
2511 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
2512 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
2513
2514 roce_set_field(context->qpc_bytes_168,
2515 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
2516 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
2517 attr->sq_psn);
2518 roce_set_field(context->qpc_bytes_168,
2519 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
2520 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
2521 roce_set_field(context->qpc_bytes_168,
2522 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
2523 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
2524 roce_set_bit(context->qpc_bytes_168,
2525 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
2526 roce_set_bit(context->qpc_bytes_168,
2527 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
2528 roce_set_bit(context->qpc_bytes_168,
2529 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
2530 context->sge_use_len = 0;
2531
2532 roce_set_field(context->qpc_bytes_176,
2533 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
2534 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
2535 roce_set_field(context->qpc_bytes_176,
2536 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
2537 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
2538 0);
2539 roce_set_field(context->qpc_bytes_180,
2540 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
2541 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
2542 roce_set_field(context->qpc_bytes_180,
2543 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
2544 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
2545
2546 context->tx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
2547
2548 roce_set_field(context->qpc_bytes_188,
2549 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
2550 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
2551 (mtts[0]) >> 32);
2552 roce_set_bit(context->qpc_bytes_188,
2553 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
2554 roce_set_field(context->qpc_bytes_188,
2555 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
2556 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
2557 0);
deb17f6f 2558 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
9a443537 2559 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
2560 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
2561 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
2562 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
2563 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
2564 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
deb17f6f
LO		 2565 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
2566 dev_err(dev, "not support this status migration\n");
9a443537 2567 goto out;
2568 }
2569
2570 /* Every status migrate must change state */
2571 roce_set_field(context->qpc_bytes_144,
2572 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
2573 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, attr->qp_state);
2574
2575 /* SW pass context to HW */
2576 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
2577 to_hns_roce_state(cur_state),
2578 to_hns_roce_state(new_state), context,
2579 hr_qp);
2580 if (ret) {
2581 dev_err(dev, "hns_roce_qp_modify failed\n");
2582 goto out;
2583 }
2584
2585 /*
2586 * Use rst2init to instead of init2init with drv,
2587 * need to hw to flash RQ HEAD by DB again
2588 */
2589 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2590 /* Memory barrier */
2591 wmb();
9a443537 2592
509bf0c2
LO		 2593 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
2594 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
2595 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
2596 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
2597 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
2598 RQ_DOORBELL_U32_8_CMD_S, 1);
2599 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
2600
2601 if (ibqp->uobject) {
2602 hr_qp->rq.db_reg_l = hr_dev->reg_base +
2603 ROCEE_DB_OTHERS_L_0_REG +
2604 DB_REG_OFFSET * hr_dev->priv_uar.index;
9a443537 2605 }
509bf0c2
LO		 2606
2607 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
9a443537 2608 }
2609
2610 hr_qp->state = new_state;
2611
2612 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2613 hr_qp->resp_depth = attr->max_dest_rd_atomic;
7716809e
LO		 2614 if (attr_mask & IB_QP_PORT) {
2615 hr_qp->port = attr->port_num - 1;
2616 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
2617 }
9a443537 2618
2619 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2620 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2621 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2622 if (ibqp->send_cq != ibqp->recv_cq)
2623 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2624 hr_qp->qpn, NULL);
2625
2626 hr_qp->rq.head = 0;
2627 hr_qp->rq.tail = 0;
2628 hr_qp->sq.head = 0;
2629 hr_qp->sq.tail = 0;
2630 hr_qp->sq_next_wqe = 0;
2631 }
2632out:
2633 kfree(context);
2634 return ret;
2635}
2636
2637int hns_roce_v1_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2638 int attr_mask, enum ib_qp_state cur_state,
2639 enum ib_qp_state new_state)
2640{
2641
2642 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
2643 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
2644 new_state);
2645 else
2646 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
2647 new_state);
2648}
2649
2650static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
2651{
2652 switch (state) {
2653 case HNS_ROCE_QP_STATE_RST:
2654 return IB_QPS_RESET;
2655 case HNS_ROCE_QP_STATE_INIT:
2656 return IB_QPS_INIT;
2657 case HNS_ROCE_QP_STATE_RTR:
2658 return IB_QPS_RTR;
2659 case HNS_ROCE_QP_STATE_RTS:
2660 return IB_QPS_RTS;
2661 case HNS_ROCE_QP_STATE_SQD:
2662 return IB_QPS_SQD;
2663 case HNS_ROCE_QP_STATE_ERR:
2664 return IB_QPS_ERR;
2665 default:
2666 return IB_QPS_ERR;
2667 }
2668}
2669
2670static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
2671 struct hns_roce_qp *hr_qp,
2672 struct hns_roce_qp_context *hr_context)
2673{
2674 struct hns_roce_cmd_mailbox *mailbox;
2675 int ret;
2676
2677 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2678 if (IS_ERR(mailbox))
2679 return PTR_ERR(mailbox);
2680
2681 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
2682 HNS_ROCE_CMD_QUERY_QP,
2683 HNS_ROCE_CMD_TIME_CLASS_A);
2684 if (!ret)
2685 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
2686 else
2687 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
2688
2689 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2690
2691 return ret;
2692}
2693
9eefa953
LO		 2694static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2695 int qp_attr_mask,
2696 struct ib_qp_init_attr *qp_init_attr)
2697{
2698 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2699 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2700 struct hns_roce_sqp_context context;
2701 u32 addr;
2702
2703 mutex_lock(&hr_qp->mutex);
2704
2705 if (hr_qp->state == IB_QPS_RESET) {
2706 qp_attr->qp_state = IB_QPS_RESET;
2707 goto done;
2708 }
2709
2710 addr = ROCEE_QP1C_CFG0_0_REG +
2711 hr_qp->port * sizeof(struct hns_roce_sqp_context);
2712 context.qp1c_bytes_4 = roce_read(hr_dev, addr);
2713 context.sq_rq_bt_l = roce_read(hr_dev, addr + 1);
2714 context.qp1c_bytes_12 = roce_read(hr_dev, addr + 2);
2715 context.qp1c_bytes_16 = roce_read(hr_dev, addr + 3);
2716 context.qp1c_bytes_20 = roce_read(hr_dev, addr + 4);
2717 context.cur_rq_wqe_ba_l = roce_read(hr_dev, addr + 5);
2718 context.qp1c_bytes_28 = roce_read(hr_dev, addr + 6);
2719 context.qp1c_bytes_32 = roce_read(hr_dev, addr + 7);
2720 context.cur_sq_wqe_ba_l = roce_read(hr_dev, addr + 8);
2721 context.qp1c_bytes_40 = roce_read(hr_dev, addr + 9);
2722
2723 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
2724 QP1C_BYTES_4_QP_STATE_M,
2725 QP1C_BYTES_4_QP_STATE_S);
2726 qp_attr->qp_state = hr_qp->state;
2727 qp_attr->path_mtu = IB_MTU_256;
2728 qp_attr->path_mig_state = IB_MIG_ARMED;
2729 qp_attr->qkey = QKEY_VAL;
2730 qp_attr->rq_psn = 0;
2731 qp_attr->sq_psn = 0;
2732 qp_attr->dest_qp_num = 1;
2733 qp_attr->qp_access_flags = 6;
2734
2735 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
2736 QP1C_BYTES_20_PKEY_IDX_M,
2737 QP1C_BYTES_20_PKEY_IDX_S);
2738 qp_attr->port_num = hr_qp->port + 1;
2739 qp_attr->sq_draining = 0;
2740 qp_attr->max_rd_atomic = 0;
2741 qp_attr->max_dest_rd_atomic = 0;
2742 qp_attr->min_rnr_timer = 0;
2743 qp_attr->timeout = 0;
2744 qp_attr->retry_cnt = 0;
2745 qp_attr->rnr_retry = 0;
2746 qp_attr->alt_timeout = 0;
2747
2748done:
2749 qp_attr->cur_qp_state = qp_attr->qp_state;
2750 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
2751 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
2752 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
2753 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
2754 qp_attr->cap.max_inline_data = 0;
2755 qp_init_attr->cap = qp_attr->cap;
2756 qp_init_attr->create_flags = 0;
2757
2758 mutex_unlock(&hr_qp->mutex);
2759
2760 return 0;
2761}
2762
2763static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2764 int qp_attr_mask,
2765 struct ib_qp_init_attr *qp_init_attr)
9a443537 2766{
2767 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2768 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2769 struct device *dev = &hr_dev->pdev->dev;
2770 struct hns_roce_qp_context *context;
2771 int tmp_qp_state = 0;
2772 int ret = 0;
2773 int state;
2774
2775 context = kzalloc(sizeof(*context), GFP_KERNEL);
2776 if (!context)
2777 return -ENOMEM;
2778
2779 memset(qp_attr, 0, sizeof(*qp_attr));
2780 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
2781
2782 mutex_lock(&hr_qp->mutex);
2783
2784 if (hr_qp->state == IB_QPS_RESET) {
2785 qp_attr->qp_state = IB_QPS_RESET;
2786 goto done;
2787 }
2788
2789 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
2790 if (ret) {
2791 dev_err(dev, "query qpc error\n");
2792 ret = -EINVAL;
2793 goto out;
2794 }
2795
2796 state = roce_get_field(context->qpc_bytes_144,
2797 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
2798 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
2799 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
2800 if (tmp_qp_state == -1) {
2801 dev_err(dev, "to_ib_qp_state error\n");
2802 ret = -EINVAL;
2803 goto out;
2804 }
2805 hr_qp->state = (u8)tmp_qp_state;
2806 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
2807 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
2808 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2809 QP_CONTEXT_QPC_BYTES_48_MTU_S);
2810 qp_attr->path_mig_state = IB_MIG_ARMED;
2811 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
2812 qp_attr->qkey = QKEY_VAL;
2813
2814 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
2815 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2816 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
2817 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
2818 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
2819 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
2820 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
2821 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2822 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
2823 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
2824 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
2825 ((roce_get_bit(context->qpc_bytes_4,
2826 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
2827 ((roce_get_bit(context->qpc_bytes_4,
2828 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
2829
2830 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
2831 hr_qp->ibqp.qp_type == IB_QPT_UC) {
2832 qp_attr->ah_attr.sl = roce_get_field(context->qpc_bytes_156,
2833 QP_CONTEXT_QPC_BYTES_156_SL_M,
2834 QP_CONTEXT_QPC_BYTES_156_SL_S);
2835 qp_attr->ah_attr.grh.flow_label = roce_get_field(
2836 context->qpc_bytes_48,
2837 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2838 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
2839 qp_attr->ah_attr.grh.sgid_index = roce_get_field(
2840 context->qpc_bytes_36,
2841 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2842 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
2843 qp_attr->ah_attr.grh.hop_limit = roce_get_field(
2844 context->qpc_bytes_44,
2845 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2846 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
2847 qp_attr->ah_attr.grh.traffic_class = roce_get_field(
2848 context->qpc_bytes_48,
2849 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2850 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
2851
2852 memcpy(qp_attr->ah_attr.grh.dgid.raw, context->dgid,
2853 sizeof(qp_attr->ah_attr.grh.dgid.raw));
2854 }
2855
2856 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
2857 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2858 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
2859 qp_attr->port_num = (u8)roce_get_field(context->qpc_bytes_156,
2860 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2861 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S) + 1;
2862 qp_attr->sq_draining = 0;
2863 qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156,
2864 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
2865 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
2866 qp_attr->max_dest_rd_atomic = roce_get_field(context->qpc_bytes_32,
2867 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2868 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
2869 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
2870 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2871 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
2872 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
2873 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
2874 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
2875 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
2876 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
2877 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
2878 qp_attr->rnr_retry = context->rnr_retry;
2879
2880done:
2881 qp_attr->cur_qp_state = qp_attr->qp_state;
2882 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
2883 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
2884
2885 if (!ibqp->uobject) {
2886 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
2887 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
2888 } else {
2889 qp_attr->cap.max_send_wr = 0;
2890 qp_attr->cap.max_send_sge = 0;
2891 }
2892
2893 qp_init_attr->cap = qp_attr->cap;
2894
2895out:
2896 mutex_unlock(&hr_qp->mutex);
2897 kfree(context);
2898 return ret;
2899}
2900
9eefa953
LO		 2901int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2902 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2903{
2904 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2905
2906 return hr_qp->doorbell_qpn <= 1 ?
2907 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
2908 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
2909}
9a443537 2910static void hns_roce_v1_destroy_qp_common(struct hns_roce_dev *hr_dev,
2911 struct hns_roce_qp *hr_qp,
2912 int is_user)
2913{
2914 u32 sdbinvcnt;
2915 unsigned long end = 0;
2916 u32 sdbinvcnt_val;
2917 u32 sdbsendptr_val;
2918 u32 sdbisusepr_val;
2919 struct hns_roce_cq *send_cq, *recv_cq;
2920 struct device *dev = &hr_dev->pdev->dev;
2921
2922 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
2923 if (hr_qp->state != IB_QPS_RESET) {
2924 /*
2925 * Set qp to ERR,
2926 * waiting for hw complete processing all dbs
2927 */
2928 if (hns_roce_v1_qp_modify(hr_dev, NULL,
2929 to_hns_roce_state(
2930 (enum ib_qp_state)hr_qp->state),
2931 HNS_ROCE_QP_STATE_ERR, NULL,
2932 hr_qp))
2933 dev_err(dev, "modify QP %06lx to ERR failed.\n",
2934 hr_qp->qpn);
2935
2936 /* Record issued doorbell */
2937 sdbisusepr_val = roce_read(hr_dev,
2938 ROCEE_SDB_ISSUE_PTR_REG);
2939 /*
2940 * Query db process status,
2941 * until hw process completely
2942 */
2943 end = msecs_to_jiffies(
2944 HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS) + jiffies;
2945 do {
2946 sdbsendptr_val = roce_read(hr_dev,
2947 ROCEE_SDB_SEND_PTR_REG);
2948 if (!time_before(jiffies, end)) {
2949 dev_err(dev, "destroy qp(0x%lx) timeout!!!",
2950 hr_qp->qpn);
2951 break;
2952 }
2953 } while ((short)(roce_get_field(sdbsendptr_val,
2954 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
2955 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) -
2956 roce_get_field(sdbisusepr_val,
2957 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
2958 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S)
2959 ) < 0);
2960
2961 /* Get list pointer */
2962 sdbinvcnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
2963
2964 /* Query db's list status, until hw reversal */
2965 do {
2966 sdbinvcnt_val = roce_read(hr_dev,
2967 ROCEE_SDB_INV_CNT_REG);
2968 if (!time_before(jiffies, end)) {
2969 dev_err(dev, "destroy qp(0x%lx) timeout!!!",
2970 hr_qp->qpn);
2971 dev_err(dev, "SdbInvCnt = 0x%x\n",
2972 sdbinvcnt_val);
2973 break;
2974 }
2975 } while ((short)(roce_get_field(sdbinvcnt_val,
2976 ROCEE_SDB_INV_CNT_SDB_INV_CNT_M,
2977 ROCEE_SDB_INV_CNT_SDB_INV_CNT_S) -
2978 (sdbinvcnt + SDB_INV_CNT_OFFSET)) < 0);
2979
2980 /* Modify qp to reset before destroying qp */
2981 if (hns_roce_v1_qp_modify(hr_dev, NULL,
2982 to_hns_roce_state(
2983 (enum ib_qp_state)hr_qp->state),
2984 HNS_ROCE_QP_STATE_RST, NULL, hr_qp))
2985 dev_err(dev, "modify QP %06lx to RESET failed.\n",
2986 hr_qp->qpn);
2987 }
2988 }
2989
2990 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
2991 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
2992
2993 hns_roce_lock_cqs(send_cq, recv_cq);
2994
2995 if (!is_user) {
2996 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
2997 to_hr_srq(hr_qp->ibqp.srq) : NULL);
2998 if (send_cq != recv_cq)
2999 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3000 }
3001
3002 hns_roce_qp_remove(hr_dev, hr_qp);
3003
3004 hns_roce_unlock_cqs(send_cq, recv_cq);
3005
3006 hns_roce_qp_free(hr_dev, hr_qp);
3007
3008 /* Not special_QP, free their QPN */
3009 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) ||
3010 (hr_qp->ibqp.qp_type == IB_QPT_UC) ||
3011 (hr_qp->ibqp.qp_type == IB_QPT_UD))
3012 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3013
3014 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3015
3016 if (is_user) {
3017 ib_umem_release(hr_qp->umem);
3018 } else {
3019 kfree(hr_qp->sq.wrid);
3020 kfree(hr_qp->rq.wrid);
3021 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3022 }
3023}
3024
3025int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3026{
3027 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3028 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3029
3030 hns_roce_v1_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject);
3031
3032 if (hr_qp->ibqp.qp_type == IB_QPT_GSI)
3033 kfree(hr_to_hr_sqp(hr_qp));
3034 else
3035 kfree(hr_qp);
3036
3037 return 0;
3038}
3039
3040struct hns_roce_v1_priv hr_v1_priv;
3041
3042struct hns_roce_hw hns_roce_hw_v1 = {
3043 .reset = hns_roce_v1_reset,
3044 .hw_profile = hns_roce_v1_profile,
3045 .hw_init = hns_roce_v1_init,
3046 .hw_exit = hns_roce_v1_exit,
3047 .set_gid = hns_roce_v1_set_gid,
3048 .set_mac = hns_roce_v1_set_mac,
3049 .set_mtu = hns_roce_v1_set_mtu,
3050 .write_mtpt = hns_roce_v1_write_mtpt,
3051 .write_cqc = hns_roce_v1_write_cqc,
97f0e39f 3052 .clear_hem = hns_roce_v1_clear_hem,
9a443537 3053 .modify_qp = hns_roce_v1_modify_qp,
3054 .query_qp = hns_roce_v1_query_qp,
3055 .destroy_qp = hns_roce_v1_destroy_qp,
3056 .post_send = hns_roce_v1_post_send,
3057 .post_recv = hns_roce_v1_post_recv,
3058 .req_notify_cq = hns_roce_v1_req_notify_cq,
3059 .poll_cq = hns_roce_v1_poll_cq,
3060 .priv = &hr_v1_priv,
3061};
Linux 6.x block layer and io_uring tree(s)