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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hw_v1.c
CommitLineData
9a443537 1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/platform_device.h>
528f1deb 34#include <linux/acpi.h>
543bfe6c 35#include <linux/etherdevice.h>
b16f8188 36#include <linux/interrupt.h>
cd6ce4a5 37#include <linux/of.h>
08805fdb 38#include <linux/of_platform.h>
9a443537 39#include <rdma/ib_umem.h>
40#include "hns_roce_common.h"
41#include "hns_roce_device.h"
42#include "hns_roce_cmd.h"
43#include "hns_roce_hem.h"
44#include "hns_roce_hw_v1.h"
45
46static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
47{
48 dseg->lkey = cpu_to_le32(sg->lkey);
49 dseg->addr = cpu_to_le64(sg->addr);
50 dseg->len = cpu_to_le32(sg->length);
51}
52
53static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
54 u32 rkey)
55{
56 rseg->raddr = cpu_to_le64(remote_addr);
57 rseg->rkey = cpu_to_le32(rkey);
58 rseg->len = 0;
59}
60
d34ac5cd
BVA		 61static int hns_roce_v1_post_send(struct ib_qp *ibqp,
62 const struct ib_send_wr *wr,
63 const struct ib_send_wr **bad_wr)
9a443537 64{
65 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
66 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
67 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
68 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
69 struct hns_roce_wqe_data_seg *dseg = NULL;
70 struct hns_roce_qp *qp = to_hr_qp(ibqp);
71 struct device *dev = &hr_dev->pdev->dev;
72 struct hns_roce_sq_db sq_db;
73 int ps_opcode = 0, i = 0;
74 unsigned long flags = 0;
75 void *wqe = NULL;
76 u32 doorbell[2];
77 int nreq = 0;
78 u32 ind = 0;
79 int ret = 0;
543bfe6c
LO		 80 u8 *smac;
81 int loopback;
9a443537 82
07182fa7
LO		 83 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
84 ibqp->qp_type != IB_QPT_RC)) {
85 dev_err(dev, "un-supported QP type\n");
86 *bad_wr = NULL;
87 return -EOPNOTSUPP;
88 }
9a443537 89
07182fa7 90 spin_lock_irqsave(&qp->sq.lock, flags);
9a443537 91 ind = qp->sq_next_wqe;
92 for (nreq = 0; wr; ++nreq, wr = wr->next) {
93 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
94 ret = -ENOMEM;
95 *bad_wr = wr;
96 goto out;
97 }
98
99 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
100 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
101 wr->num_sge, qp->sq.max_gs);
102 ret = -EINVAL;
103 *bad_wr = wr;
104 goto out;
105 }
106
107 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
108 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
109 wr->wr_id;
110
111 /* Corresponding to the RC and RD type wqe process separately */
112 if (ibqp->qp_type == IB_QPT_GSI) {
113 ud_sq_wqe = wqe;
114 roce_set_field(ud_sq_wqe->dmac_h,
115 UD_SEND_WQE_U32_4_DMAC_0_M,
116 UD_SEND_WQE_U32_4_DMAC_0_S,
117 ah->av.mac[0]);
118 roce_set_field(ud_sq_wqe->dmac_h,
119 UD_SEND_WQE_U32_4_DMAC_1_M,
120 UD_SEND_WQE_U32_4_DMAC_1_S,
121 ah->av.mac[1]);
122 roce_set_field(ud_sq_wqe->dmac_h,
123 UD_SEND_WQE_U32_4_DMAC_2_M,
124 UD_SEND_WQE_U32_4_DMAC_2_S,
125 ah->av.mac[2]);
126 roce_set_field(ud_sq_wqe->dmac_h,
127 UD_SEND_WQE_U32_4_DMAC_3_M,
128 UD_SEND_WQE_U32_4_DMAC_3_S,
129 ah->av.mac[3]);
130
131 roce_set_field(ud_sq_wqe->u32_8,
132 UD_SEND_WQE_U32_8_DMAC_4_M,
133 UD_SEND_WQE_U32_8_DMAC_4_S,
134 ah->av.mac[4]);
135 roce_set_field(ud_sq_wqe->u32_8,
136 UD_SEND_WQE_U32_8_DMAC_5_M,
137 UD_SEND_WQE_U32_8_DMAC_5_S,
138 ah->av.mac[5]);
543bfe6c
LO		 139
140 smac = (u8 *)hr_dev->dev_addr[qp->port];
141 loopback = ether_addr_equal_unaligned(ah->av.mac,
142 smac) ? 1 : 0;
143 roce_set_bit(ud_sq_wqe->u32_8,
144 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
145 loopback);
146
9a443537 147 roce_set_field(ud_sq_wqe->u32_8,
148 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
149 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
150 HNS_ROCE_WQE_OPCODE_SEND);
151 roce_set_field(ud_sq_wqe->u32_8,
152 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
153 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
154 2);
155 roce_set_bit(ud_sq_wqe->u32_8,
156 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
157 1);
158
159 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
160 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
161 (wr->send_flags & IB_SEND_SOLICITED ?
162 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
163 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
164 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
165
166 roce_set_field(ud_sq_wqe->u32_16,
167 UD_SEND_WQE_U32_16_DEST_QP_M,
168 UD_SEND_WQE_U32_16_DEST_QP_S,
169 ud_wr(wr)->remote_qpn);
170 roce_set_field(ud_sq_wqe->u32_16,
171 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
172 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
173 ah->av.stat_rate);
174
175 roce_set_field(ud_sq_wqe->u32_36,
176 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
cdfa4ad5
LO		 177 UD_SEND_WQE_U32_36_FLOW_LABEL_S,
178 ah->av.sl_tclass_flowlabel &
179 HNS_ROCE_FLOW_LABEL_MASK);
9a443537 180 roce_set_field(ud_sq_wqe->u32_36,
0576cbde 181 UD_SEND_WQE_U32_36_PRIORITY_M,
182 UD_SEND_WQE_U32_36_PRIORITY_S,
183 le32_to_cpu(ah->av.sl_tclass_flowlabel) >>
184 HNS_ROCE_SL_SHIFT);
9a443537 185 roce_set_field(ud_sq_wqe->u32_36,
186 UD_SEND_WQE_U32_36_SGID_INDEX_M,
187 UD_SEND_WQE_U32_36_SGID_INDEX_S,
7716809e 188 hns_get_gid_index(hr_dev, qp->phy_port,
9a443537 189 ah->av.gid_index));
190
191 roce_set_field(ud_sq_wqe->u32_40,
192 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
193 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
194 ah->av.hop_limit);
195 roce_set_field(ud_sq_wqe->u32_40,
196 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
cdfa4ad5
LO		 197 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
198 ah->av.sl_tclass_flowlabel >>
199 HNS_ROCE_TCLASS_SHIFT);
9a443537 200
201 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
202
8b9b8d14 203 ud_sq_wqe->va0_l =
204 cpu_to_le32((u32)wr->sg_list[0].addr);
205 ud_sq_wqe->va0_h =
206 cpu_to_le32((wr->sg_list[0].addr) >> 32);
207 ud_sq_wqe->l_key0 =
208 cpu_to_le32(wr->sg_list[0].lkey);
209
210 ud_sq_wqe->va1_l =
211 cpu_to_le32((u32)wr->sg_list[1].addr);
212 ud_sq_wqe->va1_h =
213 cpu_to_le32((wr->sg_list[1].addr) >> 32);
214 ud_sq_wqe->l_key1 =
215 cpu_to_le32(wr->sg_list[1].lkey);
9a443537 216 ind++;
217 } else if (ibqp->qp_type == IB_QPT_RC) {
8b9b8d14 218 u32 tmp_len = 0;
219
9a443537 220 ctrl = wqe;
221 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
222 for (i = 0; i < wr->num_sge; i++)
8b9b8d14 223 tmp_len += wr->sg_list[i].length;
224
225 ctrl->msg_length =
226 cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
9a443537 227
228 ctrl->sgl_pa_h = 0;
229 ctrl->flag = 0;
8b9b8d14 230
231 switch (wr->opcode) {
232 case IB_WR_SEND_WITH_IMM:
233 case IB_WR_RDMA_WRITE_WITH_IMM:
234 ctrl->imm_data = wr->ex.imm_data;
235 break;
236 case IB_WR_SEND_WITH_INV:
237 ctrl->inv_key =
238 cpu_to_le32(wr->ex.invalidate_rkey);
239 break;
240 default:
241 ctrl->imm_data = 0;
242 break;
243 }
9a443537 244
245 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
246 /* SO wait for conforming application scenarios */
247 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
248 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
249 (wr->send_flags & IB_SEND_SOLICITED ?
250 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
251 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
252 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
253 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
254 (wr->send_flags & IB_SEND_FENCE ?
255 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
256
c24bf895 257 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
9a443537 258
259 switch (wr->opcode) {
260 case IB_WR_RDMA_READ:
261 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
9de61d3f 262 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
263 rdma_wr(wr)->rkey);
9a443537 264 break;
265 case IB_WR_RDMA_WRITE:
266 case IB_WR_RDMA_WRITE_WITH_IMM:
267 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
9de61d3f 268 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
269 rdma_wr(wr)->rkey);
9a443537 270 break;
271 case IB_WR_SEND:
272 case IB_WR_SEND_WITH_INV:
273 case IB_WR_SEND_WITH_IMM:
274 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
275 break;
276 case IB_WR_LOCAL_INV:
277 break;
278 case IB_WR_ATOMIC_CMP_AND_SWP:
279 case IB_WR_ATOMIC_FETCH_AND_ADD:
280 case IB_WR_LSO:
281 default:
282 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
283 break;
284 }
285 ctrl->flag |= cpu_to_le32(ps_opcode);
c24bf895 286 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
9a443537 287
288 dseg = wqe;
289 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
8b9b8d14 290 if (le32_to_cpu(ctrl->msg_length) >
291 hr_dev->caps.max_sq_inline) {
9a443537 292 ret = -EINVAL;
293 *bad_wr = wr;
294 dev_err(dev, "inline len(1-%d)=%d, illegal",
295 ctrl->msg_length,
296 hr_dev->caps.max_sq_inline);
297 goto out;
298 }
299 for (i = 0; i < wr->num_sge; i++) {
300 memcpy(wqe, ((void *) (uintptr_t)
301 wr->sg_list[i].addr),
302 wr->sg_list[i].length);
c24bf895 303 wqe += wr->sg_list[i].length;
9a443537 304 }
8b9b8d14 305 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
9a443537 306 } else {
307 /*sqe num is two */
308 for (i = 0; i < wr->num_sge; i++)
309 set_data_seg(dseg + i, wr->sg_list + i);
310
311 ctrl->flag |= cpu_to_le32(wr->num_sge <<
312 HNS_ROCE_WQE_SGE_NUM_BIT);
313 }
314 ind++;
9a443537 315 }
316 }
317
318out:
319 /* Set DB return */
320 if (likely(nreq)) {
321 qp->sq.head += nreq;
322 /* Memory barrier */
323 wmb();
324
325 sq_db.u32_4 = 0;
326 sq_db.u32_8 = 0;
327 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
328 SQ_DOORBELL_U32_4_SQ_HEAD_S,
329 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
bfcc681b
SX		 330 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
331 SQ_DOORBELL_U32_4_SL_S, qp->sl);
9a443537 332 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
7716809e 333 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
9a443537 334 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
335 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
336 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
337
8b9b8d14 338 doorbell[0] = le32_to_cpu(sq_db.u32_4);
339 doorbell[1] = le32_to_cpu(sq_db.u32_8);
9a443537 340
0576cbde 341 hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l);
9a443537 342 qp->sq_next_wqe = ind;
343 }
344
345 spin_unlock_irqrestore(&qp->sq.lock, flags);
346
347 return ret;
348}
349
d34ac5cd
BVA		 350static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
351 const struct ib_recv_wr *wr,
352 const struct ib_recv_wr **bad_wr)
9a443537 353{
354 int ret = 0;
355 int nreq = 0;
356 int ind = 0;
357 int i = 0;
0576cbde 358 u32 reg_val;
9a443537 359 unsigned long flags = 0;
360 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
361 struct hns_roce_wqe_data_seg *scat = NULL;
362 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
363 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
364 struct device *dev = &hr_dev->pdev->dev;
365 struct hns_roce_rq_db rq_db;
366 uint32_t doorbell[2] = {0};
367
368 spin_lock_irqsave(&hr_qp->rq.lock, flags);
369 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
370
371 for (nreq = 0; wr; ++nreq, wr = wr->next) {
372 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
373 hr_qp->ibqp.recv_cq)) {
374 ret = -ENOMEM;
375 *bad_wr = wr;
376 goto out;
377 }
378
379 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
380 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
381 wr->num_sge, hr_qp->rq.max_gs);
382 ret = -EINVAL;
383 *bad_wr = wr;
384 goto out;
385 }
386
387 ctrl = get_recv_wqe(hr_qp, ind);
388
389 roce_set_field(ctrl->rwqe_byte_12,
390 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
391 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
392 wr->num_sge);
393
394 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
395
396 for (i = 0; i < wr->num_sge; i++)
397 set_data_seg(scat + i, wr->sg_list + i);
398
399 hr_qp->rq.wrid[ind] = wr->wr_id;
400
401 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
402 }
403
404out:
405 if (likely(nreq)) {
406 hr_qp->rq.head += nreq;
407 /* Memory barrier */
408 wmb();
409
410 if (ibqp->qp_type == IB_QPT_GSI) {
0576cbde 411 __le32 tmp;
412
9a443537 413 /* SW update GSI rq header */
414 reg_val = roce_read(to_hr_dev(ibqp->device),
415 ROCEE_QP1C_CFG3_0_REG +
7716809e 416 QP1C_CFGN_OFFSET * hr_qp->phy_port);
0576cbde 417 tmp = cpu_to_le32(reg_val);
418 roce_set_field(tmp,
9a443537 419 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
420 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
421 hr_qp->rq.head);
0576cbde 422 reg_val = le32_to_cpu(tmp);
9a443537 423 roce_write(to_hr_dev(ibqp->device),
424 ROCEE_QP1C_CFG3_0_REG +
7716809e 425 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
9a443537 426 } else {
427 rq_db.u32_4 = 0;
428 rq_db.u32_8 = 0;
429
430 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
431 RQ_DOORBELL_U32_4_RQ_HEAD_S,
432 hr_qp->rq.head);
433 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
434 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
435 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
436 RQ_DOORBELL_U32_8_CMD_S, 1);
437 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
438 1);
439
8b9b8d14 440 doorbell[0] = le32_to_cpu(rq_db.u32_4);
441 doorbell[1] = le32_to_cpu(rq_db.u32_8);
9a443537 442
0576cbde 443 hns_roce_write64_k((__le32 *)doorbell,
444 hr_qp->rq.db_reg_l);
9a443537 445 }
446 }
447 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
448
449 return ret;
450}
451
452static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
453 int sdb_mode, int odb_mode)
454{
0576cbde 455 __le32 tmp;
9a443537 456 u32 val;
457
458 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
0576cbde 459 tmp = cpu_to_le32(val);
460 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
461 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
462 val = le32_to_cpu(tmp);
9a443537 463 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
464}
465
466static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
467 u32 odb_mode)
468{
0576cbde 469 __le32 tmp;
9a443537 470 u32 val;
471
472 /* Configure SDB/ODB extend mode */
473 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
0576cbde 474 tmp = cpu_to_le32(val);
475 roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
476 roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
477 val = le32_to_cpu(tmp);
9a443537 478 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
479}
480
481static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
482 u32 sdb_alful)
483{
0576cbde 484 __le32 tmp;
9a443537 485 u32 val;
486
487 /* Configure SDB */
488 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
0576cbde 489 tmp = cpu_to_le32(val);
490 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
9a443537 491 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
0576cbde 492 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
9a443537 493 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
0576cbde 494 val = le32_to_cpu(tmp);
9a443537 495 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
496}
497
498static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
499 u32 odb_alful)
500{
0576cbde 501 __le32 tmp;
9a443537 502 u32 val;
503
504 /* Configure ODB */
505 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
0576cbde 506 tmp = cpu_to_le32(val);
507 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
9a443537 508 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
0576cbde 509 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
9a443537 510 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
0576cbde 511 val = le32_to_cpu(tmp);
9a443537 512 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
513}
514
515static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
516 u32 ext_sdb_alful)
517{
518 struct device *dev = &hr_dev->pdev->dev;
519 struct hns_roce_v1_priv *priv;
520 struct hns_roce_db_table *db;
521 dma_addr_t sdb_dma_addr;
0576cbde 522 __le32 tmp;
9a443537 523 u32 val;
524
016a0059 525 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 526 db = &priv->db_table;
527
528 /* Configure extend SDB threshold */
529 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
530 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
531
532 /* Configure extend SDB base addr */
533 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
534 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
535
536 /* Configure extend SDB depth */
537 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
0576cbde 538 tmp = cpu_to_le32(val);
539 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
9a443537 540 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
541 db->ext_db->esdb_dep);
542 /*
543 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
544 * using 4K page, and shift more 32 because of
545 * caculating the high 32 bit value evaluated to hardware.
546 */
0576cbde 547 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
9a443537 548 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
0576cbde 549 val = le32_to_cpu(tmp);
9a443537 550 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
551
552 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
553 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
554 ext_sdb_alept, ext_sdb_alful);
555}
556
557static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
558 u32 ext_odb_alful)
559{
560 struct device *dev = &hr_dev->pdev->dev;
561 struct hns_roce_v1_priv *priv;
562 struct hns_roce_db_table *db;
563 dma_addr_t odb_dma_addr;
0576cbde 564 __le32 tmp;
9a443537 565 u32 val;
566
016a0059 567 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 568 db = &priv->db_table;
569
570 /* Configure extend ODB threshold */
571 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
572 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
573
574 /* Configure extend ODB base addr */
575 odb_dma_addr = db->ext_db->odb_buf_list->map;
576 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
577
578 /* Configure extend ODB depth */
579 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
0576cbde 580 tmp = cpu_to_le32(val);
581 roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
9a443537 582 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
583 db->ext_db->eodb_dep);
0576cbde 584 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
9a443537 585 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
586 db->ext_db->eodb_dep);
0576cbde 587 val = le32_to_cpu(tmp);
9a443537 588 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
589
590 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
591 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
592 ext_odb_alept, ext_odb_alful);
593}
594
595static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
596 u32 odb_ext_mod)
597{
598 struct device *dev = &hr_dev->pdev->dev;
599 struct hns_roce_v1_priv *priv;
600 struct hns_roce_db_table *db;
601 dma_addr_t sdb_dma_addr;
602 dma_addr_t odb_dma_addr;
603 int ret = 0;
604
016a0059 605 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 606 db = &priv->db_table;
607
608 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
609 if (!db->ext_db)
610 return -ENOMEM;
611
612 if (sdb_ext_mod) {
613 db->ext_db->sdb_buf_list = kmalloc(
614 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
615 if (!db->ext_db->sdb_buf_list) {
616 ret = -ENOMEM;
617 goto ext_sdb_buf_fail_out;
618 }
619
620 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
621 HNS_ROCE_V1_EXT_SDB_SIZE,
622 &sdb_dma_addr, GFP_KERNEL);
623 if (!db->ext_db->sdb_buf_list->buf) {
624 ret = -ENOMEM;
625 goto alloc_sq_db_buf_fail;
626 }
627 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
628
629 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
630 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
631 HNS_ROCE_V1_EXT_SDB_ALFUL);
632 } else
633 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
634 HNS_ROCE_V1_SDB_ALFUL);
635
636 if (odb_ext_mod) {
637 db->ext_db->odb_buf_list = kmalloc(
638 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
639 if (!db->ext_db->odb_buf_list) {
640 ret = -ENOMEM;
641 goto ext_odb_buf_fail_out;
642 }
643
644 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
645 HNS_ROCE_V1_EXT_ODB_SIZE,
646 &odb_dma_addr, GFP_KERNEL);
647 if (!db->ext_db->odb_buf_list->buf) {
648 ret = -ENOMEM;
649 goto alloc_otr_db_buf_fail;
650 }
651 db->ext_db->odb_buf_list->map = odb_dma_addr;
652
653 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
654 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
655 HNS_ROCE_V1_EXT_ODB_ALFUL);
656 } else
657 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
658 HNS_ROCE_V1_ODB_ALFUL);
659
660 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
661
662 return 0;
663
664alloc_otr_db_buf_fail:
665 kfree(db->ext_db->odb_buf_list);
666
667ext_odb_buf_fail_out:
668 if (sdb_ext_mod) {
669 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
670 db->ext_db->sdb_buf_list->buf,
671 db->ext_db->sdb_buf_list->map);
672 }
673
674alloc_sq_db_buf_fail:
675 if (sdb_ext_mod)
676 kfree(db->ext_db->sdb_buf_list);
677
678ext_sdb_buf_fail_out:
679 kfree(db->ext_db);
680 return ret;
681}
682
bfcc681b
SX		 683static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
684 struct ib_pd *pd)
685{
686 struct device *dev = &hr_dev->pdev->dev;
687 struct ib_qp_init_attr init_attr;
688 struct ib_qp *qp;
689
690 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
691 init_attr.qp_type = IB_QPT_RC;
692 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
693 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
694 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
695
696 qp = hns_roce_create_qp(pd, &init_attr, NULL);
697 if (IS_ERR(qp)) {
698 dev_err(dev, "Create loop qp for mr free failed!");
699 return NULL;
700 }
701
702 return to_hr_qp(qp);
703}
704
705static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
706{
707 struct hns_roce_caps *caps = &hr_dev->caps;
708 struct device *dev = &hr_dev->pdev->dev;
709 struct ib_cq_init_attr cq_init_attr;
710 struct hns_roce_free_mr *free_mr;
711 struct ib_qp_attr attr = { 0 };
712 struct hns_roce_v1_priv *priv;
713 struct hns_roce_qp *hr_qp;
21a428a0 714 struct ib_device *ibdev;
bfcc681b
SX		 715 struct ib_cq *cq;
716 struct ib_pd *pd;
d8966fcd 717 union ib_gid dgid;
bfcc681b
SX		 718 u64 subnet_prefix;
719 int attr_mask = 0;
21a428a0 720 int ret = -ENOMEM;
5802883d 721 int i, j;
5802883d 722 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
bfcc681b 723 u8 phy_port;
5802883d 724 u8 port = 0;
bfcc681b
SX		 725 u8 sl;
726
016a0059 727 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 728 free_mr = &priv->free_mr;
729
730 /* Reserved cq for loop qp */
731 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
732 cq_init_attr.comp_vector = 0;
733 cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
734 if (IS_ERR(cq)) {
b54900fc 735 dev_err(dev, "Create cq for reserved loop qp failed!");
bfcc681b
SX		 736 return -ENOMEM;
737 }
738 free_mr->mr_free_cq = to_hr_cq(cq);
739 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
740 free_mr->mr_free_cq->ib_cq.uobject = NULL;
741 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
742 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
743 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
744 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
745
21a428a0
LR		 746 ibdev = &hr_dev->ib_dev;
747 pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
e8ac9389 748 if (!pd)
21a428a0
LR		 749 goto alloc_mem_failed;
750
751 pd->device = ibdev;
752 ret = hns_roce_alloc_pd(pd, NULL, NULL);
753 if (ret)
bfcc681b 754 goto alloc_pd_failed;
21a428a0 755
bfcc681b
SX		 756 free_mr->mr_free_pd = to_hr_pd(pd);
757 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
758 free_mr->mr_free_pd->ibpd.uobject = NULL;
79d44207 759 free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
bfcc681b
SX		 760 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
761
762 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
763 attr.pkey_index = 0;
764 attr.min_rnr_timer = 0;
765 /* Disable read ability */
766 attr.max_dest_rd_atomic = 0;
767 attr.max_rd_atomic = 0;
768 /* Use arbitrary values as rq_psn and sq_psn */
769 attr.rq_psn = 0x0808;
770 attr.sq_psn = 0x0808;
771 attr.retry_cnt = 7;
772 attr.rnr_retry = 7;
773 attr.timeout = 0x12;
774 attr.path_mtu = IB_MTU_256;
5802883d 775 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
d8966fcd
DC		 776 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
777 rdma_ah_set_static_rate(&attr.ah_attr, 3);
bfcc681b
SX		 778
779 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
780 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
5802883d 781 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
782 (i % HNS_ROCE_MAX_PORTS);
783 sl = i / HNS_ROCE_MAX_PORTS;
784
785 for (j = 0; j < caps->num_ports; j++) {
786 if (hr_dev->iboe.phy_port[j] == phy_port) {
787 queue_en[i] = 1;
788 port = j;
789 break;
790 }
791 }
792
793 if (!queue_en[i])
794 continue;
795
bfcc681b 796 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
5db465f2 797 if (!free_mr->mr_free_qp[i]) {
bfcc681b 798 dev_err(dev, "Create loop qp failed!\n");
dedf6350 799 ret = -ENOMEM;
bfcc681b
SX		 800 goto create_lp_qp_failed;
801 }
802 hr_qp = free_mr->mr_free_qp[i];
803
5802883d 804 hr_qp->port = port;
bfcc681b
SX		 805 hr_qp->phy_port = phy_port;
806 hr_qp->ibqp.qp_type = IB_QPT_RC;
807 hr_qp->ibqp.device = &hr_dev->ib_dev;
808 hr_qp->ibqp.uobject = NULL;
809 atomic_set(&hr_qp->ibqp.usecnt, 0);
810 hr_qp->ibqp.pd = pd;
811 hr_qp->ibqp.recv_cq = cq;
812 hr_qp->ibqp.send_cq = cq;
813
5802883d 814 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
815 rdma_ah_set_sl(&attr.ah_attr, sl);
816 attr.port_num = port + 1;
bfcc681b
SX		 817
818 attr.dest_qp_num = hr_qp->qpn;
d8966fcd 819 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
5802883d 820 hr_dev->dev_addr[port],
bfcc681b
SX		 821 MAC_ADDR_OCTET_NUM);
822
d8966fcd 823 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
5802883d 824 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
825 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
d8966fcd
DC		 826 dgid.raw[11] = 0xff;
827 dgid.raw[12] = 0xfe;
828 dgid.raw[8] ^= 2;
829 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
bfcc681b
SX		 830
831 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
832 IB_QPS_RESET, IB_QPS_INIT);
833 if (ret) {
834 dev_err(dev, "modify qp failed(%d)!\n", ret);
835 goto create_lp_qp_failed;
836 }
837
107013ce 838 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
bfcc681b
SX		 839 IB_QPS_INIT, IB_QPS_RTR);
840 if (ret) {
841 dev_err(dev, "modify qp failed(%d)!\n", ret);
842 goto create_lp_qp_failed;
843 }
844
845 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
846 IB_QPS_RTR, IB_QPS_RTS);
847 if (ret) {
848 dev_err(dev, "modify qp failed(%d)!\n", ret);
849 goto create_lp_qp_failed;
850 }
851 }
852
853 return 0;
854
855create_lp_qp_failed:
856 for (i -= 1; i >= 0; i--) {
857 hr_qp = free_mr->mr_free_qp[i];
858 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
859 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
860 }
861
21a428a0 862 hns_roce_dealloc_pd(pd);
bfcc681b
SX		 863
864alloc_pd_failed:
21a428a0
LR		 865 kfree(pd);
866
867alloc_mem_failed:
bfcc681b
SX		 868 if (hns_roce_ib_destroy_cq(cq))
869 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
870
dedf6350 871 return ret;
bfcc681b
SX		 872}
873
874static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
875{
876 struct device *dev = &hr_dev->pdev->dev;
877 struct hns_roce_free_mr *free_mr;
878 struct hns_roce_v1_priv *priv;
879 struct hns_roce_qp *hr_qp;
880 int ret;
881 int i;
882
016a0059 883 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 884 free_mr = &priv->free_mr;
885
886 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
887 hr_qp = free_mr->mr_free_qp[i];
5802883d 888 if (!hr_qp)
889 continue;
890
bfcc681b
SX		 891 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
892 if (ret)
893 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
894 i, ret);
895 }
896
897 ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
898 if (ret)
899 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
900
21a428a0 901 hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
bfcc681b
SX		 902}
903
9a443537 904static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
905{
906 struct device *dev = &hr_dev->pdev->dev;
907 struct hns_roce_v1_priv *priv;
908 struct hns_roce_db_table *db;
909 u32 sdb_ext_mod;
910 u32 odb_ext_mod;
911 u32 sdb_evt_mod;
912 u32 odb_evt_mod;
913 int ret = 0;
914
016a0059 915 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 916 db = &priv->db_table;
917
918 memset(db, 0, sizeof(*db));
919
920 /* Default DB mode */
921 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
922 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
923 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
924 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
925
926 db->sdb_ext_mod = sdb_ext_mod;
927 db->odb_ext_mod = odb_ext_mod;
928
929 /* Init extend DB */
930 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
931 if (ret) {
932 dev_err(dev, "Failed in extend DB configuration.\n");
933 return ret;
934 }
935
936 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
937
938 return 0;
939}
940
d61d6de0 941static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
bfcc681b
SX		 942{
943 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
944 struct hns_roce_dev *hr_dev;
945
946 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
947 work);
948 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
949
950 hns_roce_v1_release_lp_qp(hr_dev);
951
952 if (hns_roce_v1_rsv_lp_qp(hr_dev))
953 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
954
955 if (lp_qp_work->comp_flag)
956 complete(lp_qp_work->comp);
957
958 kfree(lp_qp_work);
959}
960
961static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
962{
963 struct device *dev = &hr_dev->pdev->dev;
964 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
965 struct hns_roce_free_mr *free_mr;
966 struct hns_roce_v1_priv *priv;
967 struct completion comp;
968 unsigned long end =
969 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
970
016a0059 971 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 972 free_mr = &priv->free_mr;
973
974 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
975 GFP_KERNEL);
a74dc41d
WHX		 976 if (!lp_qp_work)
977 return -ENOMEM;
bfcc681b
SX		 978
979 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
980
981 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
982 lp_qp_work->comp = &comp;
983 lp_qp_work->comp_flag = 1;
984
985 init_completion(lp_qp_work->comp);
986
987 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
988
989 while (time_before_eq(jiffies, end)) {
990 if (try_wait_for_completion(&comp))
991 return 0;
992 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
993 }
994
995 lp_qp_work->comp_flag = 0;
996 if (try_wait_for_completion(&comp))
997 return 0;
998
999 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
1000 return -ETIMEDOUT;
1001}
1002
1003static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1004{
1005 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1006 struct device *dev = &hr_dev->pdev->dev;
d34ac5cd
BVA		 1007 struct ib_send_wr send_wr;
1008 const struct ib_send_wr *bad_wr;
bfcc681b
SX		 1009 int ret;
1010
1011 memset(&send_wr, 0, sizeof(send_wr));
1012 send_wr.next = NULL;
1013 send_wr.num_sge = 0;
1014 send_wr.send_flags = 0;
1015 send_wr.sg_list = NULL;
1016 send_wr.wr_id = (unsigned long long)&send_wr;
1017 send_wr.opcode = IB_WR_RDMA_WRITE;
1018
1019 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1020 if (ret) {
1021 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1022 return ret;
1023 }
1024
1025 return 0;
1026}
1027
1028static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1029{
1030 struct hns_roce_mr_free_work *mr_work;
1031 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1032 struct hns_roce_free_mr *free_mr;
1033 struct hns_roce_cq *mr_free_cq;
1034 struct hns_roce_v1_priv *priv;
1035 struct hns_roce_dev *hr_dev;
1036 struct hns_roce_mr *hr_mr;
1037 struct hns_roce_qp *hr_qp;
1038 struct device *dev;
1039 unsigned long end =
1040 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1041 int i;
1042 int ret;
5802883d 1043 int ne = 0;
bfcc681b
SX		 1044
1045 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
1046 hr_mr = (struct hns_roce_mr *)mr_work->mr;
1047 hr_dev = to_hr_dev(mr_work->ib_dev);
1048 dev = &hr_dev->pdev->dev;
1049
016a0059 1050 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1051 free_mr = &priv->free_mr;
1052 mr_free_cq = free_mr->mr_free_cq;
1053
1054 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1055 hr_qp = free_mr->mr_free_qp[i];
5802883d 1056 if (!hr_qp)
1057 continue;
1058 ne++;
1059
bfcc681b
SX		 1060 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1061 if (ret) {
1062 dev_err(dev,
1063 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1064 hr_qp->qpn, ret);
1065 goto free_work;
1066 }
1067 }
1068
5e437b1d 1069 if (!ne) {
978cb696 1070 dev_err(dev, "Reserved loop qp is absent!\n");
5e437b1d
WHX		 1071 goto free_work;
1072 }
1073
bfcc681b
SX		 1074 do {
1075 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
a0403be8 1076 if (ret < 0 && hr_qp) {
bfcc681b
SX		 1077 dev_err(dev,
1078 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1079 hr_qp->qpn, ret, hr_mr->key, ne);
1080 goto free_work;
1081 }
1082 ne -= ret;
98e77d9f
LR		 1083 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1084 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
bfcc681b
SX		 1085 } while (ne && time_before_eq(jiffies, end));
1086
1087 if (ne != 0)
1088 dev_err(dev,
1089 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1090 hr_mr->key, ne);
1091
1092free_work:
1093 if (mr_work->comp_flag)
1094 complete(mr_work->comp);
1095 kfree(mr_work);
1096}
1097
d61d6de0
BVA		 1098static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1099 struct hns_roce_mr *mr)
bfcc681b
SX		 1100{
1101 struct device *dev = &hr_dev->pdev->dev;
1102 struct hns_roce_mr_free_work *mr_work;
1103 struct hns_roce_free_mr *free_mr;
1104 struct hns_roce_v1_priv *priv;
1105 struct completion comp;
1106 unsigned long end =
1107 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1108 unsigned long start = jiffies;
1109 int npages;
1110 int ret = 0;
1111
016a0059 1112 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1113 free_mr = &priv->free_mr;
1114
1115 if (mr->enabled) {
1116 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1117 & (hr_dev->caps.num_mtpts - 1)))
1118 dev_warn(dev, "HW2SW_MPT failed!\n");
1119 }
1120
1121 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1122 if (!mr_work) {
1123 ret = -ENOMEM;
1124 goto free_mr;
1125 }
1126
1127 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1128
1129 mr_work->ib_dev = &(hr_dev->ib_dev);
1130 mr_work->comp = &comp;
1131 mr_work->comp_flag = 1;
1132 mr_work->mr = (void *)mr;
1133 init_completion(mr_work->comp);
1134
1135 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1136
1137 while (time_before_eq(jiffies, end)) {
1138 if (try_wait_for_completion(&comp))
1139 goto free_mr;
1140 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1141 }
1142
1143 mr_work->comp_flag = 0;
1144 if (try_wait_for_completion(&comp))
1145 goto free_mr;
1146
1147 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1148 ret = -ETIMEDOUT;
1149
1150free_mr:
1151 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1152 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1153
1154 if (mr->size != ~0ULL) {
1155 npages = ib_umem_page_count(mr->umem);
1156 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1157 mr->pbl_dma_addr);
1158 }
1159
1160 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1161 key_to_hw_index(mr->key), 0);
1162
1163 if (mr->umem)
1164 ib_umem_release(mr->umem);
1165
1166 kfree(mr);
1167
1168 return ret;
1169}
1170
9a443537 1171static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1172{
1173 struct device *dev = &hr_dev->pdev->dev;
1174 struct hns_roce_v1_priv *priv;
1175 struct hns_roce_db_table *db;
1176
016a0059 1177 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1178 db = &priv->db_table;
1179
1180 if (db->sdb_ext_mod) {
1181 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1182 db->ext_db->sdb_buf_list->buf,
1183 db->ext_db->sdb_buf_list->map);
1184 kfree(db->ext_db->sdb_buf_list);
1185 }
1186
1187 if (db->odb_ext_mod) {
1188 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1189 db->ext_db->odb_buf_list->buf,
1190 db->ext_db->odb_buf_list->map);
1191 kfree(db->ext_db->odb_buf_list);
1192 }
1193
1194 kfree(db->ext_db);
1195}
1196
1197static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1198{
1199 int ret;
0576cbde 1200 u32 val;
1201 __le32 tmp;
9a443537 1202 int raq_shift = 0;
1203 dma_addr_t addr;
9a443537 1204 struct hns_roce_v1_priv *priv;
1205 struct hns_roce_raq_table *raq;
1206 struct device *dev = &hr_dev->pdev->dev;
1207
016a0059 1208 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1209 raq = &priv->raq_table;
1210
1211 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1212 if (!raq->e_raq_buf)
1213 return -ENOMEM;
1214
1215 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1216 &addr, GFP_KERNEL);
1217 if (!raq->e_raq_buf->buf) {
1218 ret = -ENOMEM;
1219 goto err_dma_alloc_raq;
1220 }
1221 raq->e_raq_buf->map = addr;
1222
1223 /* Configure raq extended address. 48bit 4K align*/
1224 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1225
1226 /* Configure raq_shift */
1227 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1228 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
0576cbde 1229 tmp = cpu_to_le32(val);
1230 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
9a443537 1231 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1232 /*
1233 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1234 * using 4K page, and shift more 32 because of
1235 * caculating the high 32 bit value evaluated to hardware.
1236 */
0576cbde 1237 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
9a443537 1238 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1239 raq->e_raq_buf->map >> 44);
0576cbde 1240 val = le32_to_cpu(tmp);
9a443537 1241 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1242 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1243
1244 /* Configure raq threshold */
1245 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
0576cbde 1246 tmp = cpu_to_le32(val);
1247 roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
9a443537 1248 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1249 HNS_ROCE_V1_EXT_RAQ_WF);
0576cbde 1250 val = le32_to_cpu(tmp);
9a443537 1251 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1252 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1253
1254 /* Enable extend raq */
1255 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
0576cbde 1256 tmp = cpu_to_le32(val);
1257 roce_set_field(tmp,
9a443537 1258 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1259 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1260 POL_TIME_INTERVAL_VAL);
0576cbde 1261 roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1262 roce_set_field(tmp,
9a443537 1263 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1264 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1265 2);
0576cbde 1266 roce_set_bit(tmp,
9a443537 1267 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
0576cbde 1268 val = le32_to_cpu(tmp);
9a443537 1269 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1270 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1271
1272 /* Enable raq drop */
1273 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
0576cbde 1274 tmp = cpu_to_le32(val);
1275 roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1276 val = le32_to_cpu(tmp);
9a443537 1277 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1278 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1279
1280 return 0;
1281
1282err_dma_alloc_raq:
1283 kfree(raq->e_raq_buf);
1284 return ret;
1285}
1286
1287static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1288{
1289 struct device *dev = &hr_dev->pdev->dev;
1290 struct hns_roce_v1_priv *priv;
1291 struct hns_roce_raq_table *raq;
1292
016a0059 1293 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
9a443537 1294 raq = &priv->raq_table;
1295
1296 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1297 raq->e_raq_buf->map);
1298 kfree(raq->e_raq_buf);
1299}
1300
1301static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1302{
0576cbde 1303 __le32 tmp;
9a443537 1304 u32 val;
1305
1306 if (enable_flag) {
1307 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1308 /* Open all ports */
0576cbde 1309 tmp = cpu_to_le32(val);
1310 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
9a443537 1311 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1312 ALL_PORT_VAL_OPEN);
0576cbde 1313 val = le32_to_cpu(tmp);
9a443537 1314 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1315 } else {
1316 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1317 /* Close all ports */
0576cbde 1318 tmp = cpu_to_le32(val);
1319 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
9a443537 1320 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
0576cbde 1321 val = le32_to_cpu(tmp);
9a443537 1322 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1323 }
1324}
1325
97f0e39f
WHX		 1326static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1327{
1328 struct device *dev = &hr_dev->pdev->dev;
1329 struct hns_roce_v1_priv *priv;
1330 int ret;
1331
016a0059 1332 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 1333
1334 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1335 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1336 GFP_KERNEL);
1337 if (!priv->bt_table.qpc_buf.buf)
1338 return -ENOMEM;
1339
1340 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1341 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1342 GFP_KERNEL);
1343 if (!priv->bt_table.mtpt_buf.buf) {
1344 ret = -ENOMEM;
1345 goto err_failed_alloc_mtpt_buf;
1346 }
1347
1348 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1349 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1350 GFP_KERNEL);
1351 if (!priv->bt_table.cqc_buf.buf) {
1352 ret = -ENOMEM;
1353 goto err_failed_alloc_cqc_buf;
1354 }
1355
1356 return 0;
1357
1358err_failed_alloc_cqc_buf:
1359 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1360 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1361
1362err_failed_alloc_mtpt_buf:
1363 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1364 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1365
1366 return ret;
1367}
1368
1369static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1370{
1371 struct device *dev = &hr_dev->pdev->dev;
1372 struct hns_roce_v1_priv *priv;
1373
016a0059 1374 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 1375
1376 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1377 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1378
1379 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1380 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1381
1382 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1383 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1384}
1385
8f3e9f3e
WHX		 1386static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1387{
1388 struct device *dev = &hr_dev->pdev->dev;
1389 struct hns_roce_buf_list *tptr_buf;
1390 struct hns_roce_v1_priv *priv;
1391
016a0059 1392 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e
WHX		 1393 tptr_buf = &priv->tptr_table.tptr_buf;
1394
1395 /*
1396 * This buffer will be used for CQ's tptr(tail pointer), also
1397 * named ci(customer index). Every CQ will use 2 bytes to save
1398 * cqe ci in hip06. Hardware will read this area to get new ci
1399 * when the queue is almost full.
1400 */
1401 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1402 &tptr_buf->map, GFP_KERNEL);
1403 if (!tptr_buf->buf)
1404 return -ENOMEM;
1405
1406 hr_dev->tptr_dma_addr = tptr_buf->map;
1407 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1408
1409 return 0;
1410}
1411
1412static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1413{
1414 struct device *dev = &hr_dev->pdev->dev;
1415 struct hns_roce_buf_list *tptr_buf;
1416 struct hns_roce_v1_priv *priv;
1417
016a0059 1418 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e
WHX		 1419 tptr_buf = &priv->tptr_table.tptr_buf;
1420
1421 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1422 tptr_buf->buf, tptr_buf->map);
1423}
1424
bfcc681b
SX		 1425static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1426{
1427 struct device *dev = &hr_dev->pdev->dev;
1428 struct hns_roce_free_mr *free_mr;
1429 struct hns_roce_v1_priv *priv;
1430 int ret = 0;
1431
016a0059 1432 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1433 free_mr = &priv->free_mr;
1434
1435 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1436 if (!free_mr->free_mr_wq) {
1437 dev_err(dev, "Create free mr workqueue failed!\n");
1438 return -ENOMEM;
1439 }
1440
1441 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1442 if (ret) {
1443 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1444 flush_workqueue(free_mr->free_mr_wq);
1445 destroy_workqueue(free_mr->free_mr_wq);
1446 }
1447
1448 return ret;
1449}
1450
1451static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1452{
1453 struct hns_roce_free_mr *free_mr;
1454 struct hns_roce_v1_priv *priv;
1455
016a0059 1456 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
bfcc681b
SX		 1457 free_mr = &priv->free_mr;
1458
1459 flush_workqueue(free_mr->free_mr_wq);
1460 destroy_workqueue(free_mr->free_mr_wq);
1461
1462 hns_roce_v1_release_lp_qp(hr_dev);
1463}
1464
9a443537 1465/**
1466 * hns_roce_v1_reset - reset RoCE
1467 * @hr_dev: RoCE device struct pointer
1468 * @enable: true -- drop reset, false -- reset
1469 * return 0 - success , negative --fail
1470 */
d61d6de0 1471static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
9a443537 1472{
1473 struct device_node *dsaf_node;
1474 struct device *dev = &hr_dev->pdev->dev;
1475 struct device_node *np = dev->of_node;
528f1deb 1476 struct fwnode_handle *fwnode;
9a443537 1477 int ret;
1478
528f1deb
S		 1479 /* check if this is DT/ACPI case */
1480 if (dev_of_node(dev)) {
1481 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1482 if (!dsaf_node) {
1483 dev_err(dev, "could not find dsaf-handle\n");
1484 return -EINVAL;
1485 }
1486 fwnode = &dsaf_node->fwnode;
1487 } else if (is_acpi_device_node(dev->fwnode)) {
977d5ad3 1488 struct fwnode_reference_args args;
528f1deb
S		 1489
1490 ret = acpi_node_get_property_reference(dev->fwnode,
1491 "dsaf-handle", 0, &args);
1492 if (ret) {
1493 dev_err(dev, "could not find dsaf-handle\n");
1494 return ret;
1495 }
977d5ad3 1496 fwnode = args.fwnode;
528f1deb
S		 1497 } else {
1498 dev_err(dev, "cannot read data from DT or ACPI\n");
1499 return -ENXIO;
9a443537 1500 }
1501
528f1deb 1502 ret = hns_dsaf_roce_reset(fwnode, false);
9a443537 1503 if (ret)
1504 return ret;
1505
528f1deb 1506 if (dereset) {
9a443537 1507 msleep(SLEEP_TIME_INTERVAL);
528f1deb 1508 ret = hns_dsaf_roce_reset(fwnode, true);
9a443537 1509 }
1510
528f1deb 1511 return ret;
9a443537 1512}
1513
d838c481
WHX		 1514static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1515{
1516 struct device *dev = &hr_dev->pdev->dev;
1517 struct hns_roce_v1_priv *priv;
1518 struct hns_roce_des_qp *des_qp;
1519
016a0059 1520 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 1521 des_qp = &priv->des_qp;
1522
1523 des_qp->requeue_flag = 1;
1524 des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1525 if (!des_qp->qp_wq) {
1526 dev_err(dev, "Create destroy qp workqueue failed!\n");
1527 return -ENOMEM;
1528 }
1529
1530 return 0;
1531}
1532
1533static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1534{
1535 struct hns_roce_v1_priv *priv;
1536 struct hns_roce_des_qp *des_qp;
1537
016a0059 1538 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 1539 des_qp = &priv->des_qp;
1540
1541 des_qp->requeue_flag = 0;
1542 flush_workqueue(des_qp->qp_wq);
1543 destroy_workqueue(des_qp->qp_wq);
1544}
1545
d61d6de0 1546static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
9a443537 1547{
1548 int i = 0;
1549 struct hns_roce_caps *caps = &hr_dev->caps;
1550
0576cbde 1551 hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1552 hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1553 hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1554 ((u64)roce_read(hr_dev,
1555 ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
8f3e9f3e 1556 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
9a443537 1557
1558 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1559 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
926a01dc 1560 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
9a443537 1561 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
93aa2187 1562 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
9a443537 1563 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1564 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1565 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1566 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1567 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1568 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
b16f8188
YL		 1569 caps->num_aeq_vectors = HNS_ROCE_V1_AEQE_VEC_NUM;
1570 caps->num_comp_vectors = HNS_ROCE_V1_COMP_VEC_NUM;
1571 caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
9a443537 1572 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1573 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1574 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1575 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1576 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1577 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1578 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1579 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1580 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1581 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1582 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1583 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1584 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1585 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
9a443537 1586 caps->reserved_lkey = 0;
1587 caps->reserved_pds = 0;
1588 caps->reserved_mrws = 1;
1589 caps->reserved_uars = 0;
1590 caps->reserved_cqs = 0;
29a1fe5d 1591 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
9a443537 1592
1593 for (i = 0; i < caps->num_ports; i++)
1594 caps->pkey_table_len[i] = 1;
1595
1596 for (i = 0; i < caps->num_ports; i++) {
1597 /* Six ports shared 16 GID in v1 engine */
1598 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1599 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1600 caps->num_ports;
1601 else
1602 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1603 caps->num_ports + 1;
1604 }
1605
b16f8188
YL		 1606 caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1607 caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
0576cbde 1608 caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
9a443537 1609 caps->max_mtu = IB_MTU_2048;
cfc85f3e
WHX		 1610
1611 return 0;
9a443537 1612}
1613
d61d6de0 1614static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
9a443537 1615{
1616 int ret;
1617 u32 val;
0576cbde 1618 __le32 tmp;
9a443537 1619 struct device *dev = &hr_dev->pdev->dev;
1620
1621 /* DMAE user config */
1622 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
0576cbde 1623 tmp = cpu_to_le32(val);
1624 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
9a443537 1625 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
0576cbde 1626 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
9a443537 1627 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1628 1 << PAGES_SHIFT_16);
0576cbde 1629 val = le32_to_cpu(tmp);
9a443537 1630 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1631
1632 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
0576cbde 1633 tmp = cpu_to_le32(val);
1634 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
9a443537 1635 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
0576cbde 1636 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
9a443537 1637 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1638 1 << PAGES_SHIFT_16);
1639
1640 ret = hns_roce_db_init(hr_dev);
1641 if (ret) {
1642 dev_err(dev, "doorbell init failed!\n");
1643 return ret;
1644 }
1645
1646 ret = hns_roce_raq_init(hr_dev);
1647 if (ret) {
1648 dev_err(dev, "raq init failed!\n");
1649 goto error_failed_raq_init;
1650 }
1651
97f0e39f
WHX		 1652 ret = hns_roce_bt_init(hr_dev);
1653 if (ret) {
1654 dev_err(dev, "bt init failed!\n");
1655 goto error_failed_bt_init;
1656 }
1657
8f3e9f3e
WHX		 1658 ret = hns_roce_tptr_init(hr_dev);
1659 if (ret) {
1660 dev_err(dev, "tptr init failed!\n");
1661 goto error_failed_tptr_init;
1662 }
1663
d838c481
WHX		 1664 ret = hns_roce_des_qp_init(hr_dev);
1665 if (ret) {
1666 dev_err(dev, "des qp init failed!\n");
1667 goto error_failed_des_qp_init;
1668 }
1669
bfcc681b
SX		 1670 ret = hns_roce_free_mr_init(hr_dev);
1671 if (ret) {
1672 dev_err(dev, "free mr init failed!\n");
1673 goto error_failed_free_mr_init;
1674 }
1675
d838c481
WHX		 1676 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1677
9a443537 1678 return 0;
1679
bfcc681b
SX		 1680error_failed_free_mr_init:
1681 hns_roce_des_qp_free(hr_dev);
1682
d838c481
WHX		 1683error_failed_des_qp_init:
1684 hns_roce_tptr_free(hr_dev);
1685
8f3e9f3e
WHX		 1686error_failed_tptr_init:
1687 hns_roce_bt_free(hr_dev);
1688
97f0e39f 1689error_failed_bt_init:
97f0e39f
WHX		 1690 hns_roce_raq_free(hr_dev);
1691
9a443537 1692error_failed_raq_init:
1693 hns_roce_db_free(hr_dev);
1694 return ret;
1695}
1696
d61d6de0 1697static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
9a443537 1698{
d838c481 1699 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
bfcc681b 1700 hns_roce_free_mr_free(hr_dev);
d838c481 1701 hns_roce_des_qp_free(hr_dev);
8f3e9f3e 1702 hns_roce_tptr_free(hr_dev);
97f0e39f 1703 hns_roce_bt_free(hr_dev);
9a443537 1704 hns_roce_raq_free(hr_dev);
1705 hns_roce_db_free(hr_dev);
1706}
1707
a680f2f3
WHX		 1708static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1709{
1710 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1711
1712 return (!!(status & (1 << HCR_GO_BIT)));
1713}
1714
281d0ccf
CIK		 1715static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1716 u64 out_param, u32 in_modifier, u8 op_modifier,
1717 u16 op, u16 token, int event)
a680f2f3 1718{
cc4ed08b 1719 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
a680f2f3
WHX		 1720 unsigned long end;
1721 u32 val = 0;
0576cbde 1722 __le32 tmp;
a680f2f3
WHX		 1723
1724 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1725 while (hns_roce_v1_cmd_pending(hr_dev)) {
1726 if (time_after(jiffies, end)) {
1727 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1728 (int)jiffies, (int)end);
1729 return -EAGAIN;
1730 }
1731 cond_resched();
1732 }
1733
0576cbde 1734 tmp = cpu_to_le32(val);
1735 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
a680f2f3 1736 op);
0576cbde 1737 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
a680f2f3 1738 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
0576cbde 1739 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1740 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1741 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
a680f2f3
WHX		 1742 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1743
0576cbde 1744 val = le32_to_cpu(tmp);
71591d12
AS		 1745 writeq(in_param, hcr + 0);
1746 writeq(out_param, hcr + 2);
1747 writel(in_modifier, hcr + 4);
a680f2f3
WHX		 1748 /* Memory barrier */
1749 wmb();
1750
71591d12 1751 writel(val, hcr + 5);
a680f2f3
WHX		 1752
1753 mmiowb();
1754
1755 return 0;
1756}
1757
1758static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1759 unsigned long timeout)
1760{
1761 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1762 unsigned long end = 0;
1763 u32 status = 0;
1764
1765 end = msecs_to_jiffies(timeout) + jiffies;
1766 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1767 cond_resched();
1768
1769 if (hns_roce_v1_cmd_pending(hr_dev)) {
1770 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1771 return -ETIMEDOUT;
1772 }
1773
0576cbde 1774 status = le32_to_cpu((__force __le32)
a680f2f3
WHX		 1775 __raw_readl(hcr + HCR_STATUS_OFFSET));
1776 if ((status & STATUS_MASK) != 0x1) {
1777 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1778 return -EBUSY;
1779 }
1780
1781 return 0;
1782}
1783
b5ff0f61 1784static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port,
f4df9a7c 1785 int gid_index, const union ib_gid *gid,
b5ff0f61 1786 const struct ib_gid_attr *attr)
9a443537 1787{
1788 u32 *p = NULL;
1789 u8 gid_idx = 0;
1790
1791 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1792
1793 p = (u32 *)&gid->raw[0];
1794 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1795 (HNS_ROCE_V1_GID_NUM * gid_idx));
1796
1797 p = (u32 *)&gid->raw[4];
1798 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1799 (HNS_ROCE_V1_GID_NUM * gid_idx));
1800
1801 p = (u32 *)&gid->raw[8];
1802 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1803 (HNS_ROCE_V1_GID_NUM * gid_idx));
1804
1805 p = (u32 *)&gid->raw[0xc];
1806 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1807 (HNS_ROCE_V1_GID_NUM * gid_idx));
b5ff0f61
WHX		 1808
1809 return 0;
9a443537 1810}
1811
a74dc41d
WHX		 1812static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1813 u8 *addr)
9a443537 1814{
1815 u32 reg_smac_l;
1816 u16 reg_smac_h;
0576cbde 1817 __le32 tmp;
9a443537 1818 u16 *p_h;
1819 u32 *p;
1820 u32 val;
1821
bfcc681b
SX		 1822 /*
1823 * When mac changed, loopback may fail
1824 * because of smac not equal to dmac.
1825 * We Need to release and create reserved qp again.
1826 */
a74dc41d
WHX		 1827 if (hr_dev->hw->dereg_mr) {
1828 int ret;
1829
1830 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1831 if (ret && ret != -ETIMEDOUT)
1832 return ret;
1833 }
bfcc681b 1834
9a443537 1835 p = (u32 *)(&addr[0]);
1836 reg_smac_l = *p;
1837 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1838 PHY_PORT_OFFSET * phy_port);
1839
1840 val = roce_read(hr_dev,
1841 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
0576cbde 1842 tmp = cpu_to_le32(val);
9a443537 1843 p_h = (u16 *)(&addr[4]);
1844 reg_smac_h = *p_h;
0576cbde 1845 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
9a443537 1846 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
0576cbde 1847 val = le32_to_cpu(tmp);
9a443537 1848 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1849 val);
a74dc41d
WHX		 1850
1851 return 0;
9a443537 1852}
1853
d61d6de0
BVA		 1854static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1855 enum ib_mtu mtu)
9a443537 1856{
0576cbde 1857 __le32 tmp;
9a443537 1858 u32 val;
1859
1860 val = roce_read(hr_dev,
1861 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
0576cbde 1862 tmp = cpu_to_le32(val);
1863 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
9a443537 1864 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
0576cbde 1865 val = le32_to_cpu(tmp);
9a443537 1866 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1867 val);
1868}
1869
d61d6de0
BVA		 1870static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1871 unsigned long mtpt_idx)
9a443537 1872{
1873 struct hns_roce_v1_mpt_entry *mpt_entry;
3856ec55 1874 struct sg_dma_page_iter sg_iter;
9a443537 1875 u64 *pages;
9a443537 1876 int i;
1877
1878 /* MPT filled into mailbox buf */
1879 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1880 memset(mpt_entry, 0, sizeof(*mpt_entry));
1881
1882 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1883 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1884 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1885 MPT_BYTE_4_KEY_S, mr->key);
1886 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1887 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1888 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1889 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1890 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1891 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1892 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1893 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1894 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1895 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1896 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1897 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1898 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1899 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1900 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1901 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1902 0);
1903 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1904
1905 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1906 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1907 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1908 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1909
0576cbde 1910 mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1911 mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1912 mpt_entry->length = cpu_to_le32((u32)mr->size);
9a443537 1913
1914 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1915 MPT_BYTE_28_PD_S, mr->pd);
1916 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1917 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1918 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1919 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1920
ad61dd30 1921 /* DMA memory register */
9a443537 1922 if (mr->type == MR_TYPE_DMA)
1923 return 0;
1924
1925 pages = (u64 *) __get_free_page(GFP_KERNEL);
1926 if (!pages)
1927 return -ENOMEM;
1928
1929 i = 0;
3856ec55
SS		 1930 for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) {
1931 pages[i] = ((u64)sg_page_iter_dma_address(&sg_iter)) >> 12;
9a443537 1932
1933 /* Directly record to MTPT table firstly 7 entry */
1934 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1935 break;
1936 i++;
1937 }
1938
1939 /* Register user mr */
1940 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1941 switch (i) {
1942 case 0:
1943 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1944 roce_set_field(mpt_entry->mpt_byte_36,
1945 MPT_BYTE_36_PA0_H_M,
1946 MPT_BYTE_36_PA0_H_S,
0576cbde 1947 (u32)(pages[i] >> PAGES_SHIFT_32));
9a443537 1948 break;
1949 case 1:
1950 roce_set_field(mpt_entry->mpt_byte_36,
1951 MPT_BYTE_36_PA1_L_M,
0576cbde 1952 MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
9a443537 1953 roce_set_field(mpt_entry->mpt_byte_40,
1954 MPT_BYTE_40_PA1_H_M,
1955 MPT_BYTE_40_PA1_H_S,
0576cbde 1956 (u32)(pages[i] >> PAGES_SHIFT_24));
9a443537 1957 break;
1958 case 2:
1959 roce_set_field(mpt_entry->mpt_byte_40,
1960 MPT_BYTE_40_PA2_L_M,
0576cbde 1961 MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
9a443537 1962 roce_set_field(mpt_entry->mpt_byte_44,
1963 MPT_BYTE_44_PA2_H_M,
1964 MPT_BYTE_44_PA2_H_S,
0576cbde 1965 (u32)(pages[i] >> PAGES_SHIFT_16));
9a443537 1966 break;
1967 case 3:
1968 roce_set_field(mpt_entry->mpt_byte_44,
1969 MPT_BYTE_44_PA3_L_M,
0576cbde 1970 MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
9a443537 1971 roce_set_field(mpt_entry->mpt_byte_48,
1972 MPT_BYTE_48_PA3_H_M,
1973 MPT_BYTE_48_PA3_H_S,
0576cbde 1974 (u32)(pages[i] >> PAGES_SHIFT_8));
9a443537 1975 break;
1976 case 4:
1977 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1978 roce_set_field(mpt_entry->mpt_byte_56,
1979 MPT_BYTE_56_PA4_H_M,
1980 MPT_BYTE_56_PA4_H_S,
0576cbde 1981 (u32)(pages[i] >> PAGES_SHIFT_32));
9a443537 1982 break;
1983 case 5:
1984 roce_set_field(mpt_entry->mpt_byte_56,
1985 MPT_BYTE_56_PA5_L_M,
0576cbde 1986 MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
9a443537 1987 roce_set_field(mpt_entry->mpt_byte_60,
1988 MPT_BYTE_60_PA5_H_M,
1989 MPT_BYTE_60_PA5_H_S,
0576cbde 1990 (u32)(pages[i] >> PAGES_SHIFT_24));
9a443537 1991 break;
1992 case 6:
1993 roce_set_field(mpt_entry->mpt_byte_60,
1994 MPT_BYTE_60_PA6_L_M,
0576cbde 1995 MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
9a443537 1996 roce_set_field(mpt_entry->mpt_byte_64,
1997 MPT_BYTE_64_PA6_H_M,
1998 MPT_BYTE_64_PA6_H_S,
0576cbde 1999 (u32)(pages[i] >> PAGES_SHIFT_16));
9a443537 2000 break;
2001 default:
2002 break;
2003 }
2004 }
2005
2006 free_page((unsigned long) pages);
2007
0576cbde 2008 mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr));
9a443537 2009
2010 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
2011 MPT_BYTE_12_PBL_ADDR_H_S,
2012 ((u32)(mr->pbl_dma_addr >> 32)));
2013
2014 return 0;
2015}
2016
2017static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
2018{
2019 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
2020 n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
2021}
2022
2023static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
2024{
2025 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
2026
2027 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
2028 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
2029 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
2030}
2031
2032static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
2033{
2034 return get_sw_cqe(hr_cq, hr_cq->cons_index);
2035}
2036
d61d6de0 2037static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
9a443537 2038{
0576cbde 2039 __le32 doorbell[2];
9a443537 2040
0576cbde 2041 doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
5b0ff9a0 2042 doorbell[1] = 0;
9a443537 2043 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2044 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2045 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2046 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2047 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2048 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2049 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2050
2051 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2052}
2053
2054static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2055 struct hns_roce_srq *srq)
2056{
2057 struct hns_roce_cqe *cqe, *dest;
2058 u32 prod_index;
2059 int nfreed = 0;
2060 u8 owner_bit;
2061
2062 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2063 ++prod_index) {
2064 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2065 break;
2066 }
2067
2068 /*
e84e40be
S		 2069 * Now backwards through the CQ, removing CQ entries
2070 * that match our QP by overwriting them with next entries.
2071 */
9a443537 2072 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2073 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2074 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2075 CQE_BYTE_16_LOCAL_QPN_S) &
2076 HNS_ROCE_CQE_QPN_MASK) == qpn) {
2077 /* In v1 engine, not support SRQ */
2078 ++nfreed;
2079 } else if (nfreed) {
2080 dest = get_cqe(hr_cq, (prod_index + nfreed) &
2081 hr_cq->ib_cq.cqe);
2082 owner_bit = roce_get_bit(dest->cqe_byte_4,
2083 CQE_BYTE_4_OWNER_S);
2084 memcpy(dest, cqe, sizeof(*cqe));
2085 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2086 owner_bit);
2087 }
2088 }
2089
2090 if (nfreed) {
2091 hr_cq->cons_index += nfreed;
2092 /*
e84e40be
S		 2093 * Make sure update of buffer contents is done before
2094 * updating consumer index.
2095 */
9a443537 2096 wmb();
2097
a4be892e 2098 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
9a443537 2099 }
2100}
2101
2102static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2103 struct hns_roce_srq *srq)
2104{
2105 spin_lock_irq(&hr_cq->lock);
2106 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2107 spin_unlock_irq(&hr_cq->lock);
2108}
2109
d61d6de0
BVA		 2110static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2111 struct hns_roce_cq *hr_cq, void *mb_buf,
2112 u64 *mtts, dma_addr_t dma_handle, int nent,
2113 u32 vector)
9a443537 2114{
2115 struct hns_roce_cq_context *cq_context = NULL;
8f3e9f3e
WHX		 2116 struct hns_roce_buf_list *tptr_buf;
2117 struct hns_roce_v1_priv *priv;
2118 dma_addr_t tptr_dma_addr;
2119 int offset;
2120
016a0059 2121 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
8f3e9f3e 2122 tptr_buf = &priv->tptr_table.tptr_buf;
9a443537 2123
2124 cq_context = mb_buf;
2125 memset(cq_context, 0, sizeof(*cq_context));
2126
8f3e9f3e
WHX		 2127 /* Get the tptr for this CQ. */
2128 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2129 tptr_dma_addr = tptr_buf->map + offset;
2130 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
9a443537 2131
2132 /* Register cq_context members */
2133 roce_set_field(cq_context->cqc_byte_4,
2134 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2135 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2136 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2137 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
9a443537 2138
0576cbde 2139 cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
9a443537 2140
2141 roce_set_field(cq_context->cqc_byte_12,
2142 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2143 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2144 ((u64)dma_handle >> 32));
2145 roce_set_field(cq_context->cqc_byte_12,
2146 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2147 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2148 ilog2((unsigned int)nent));
2149 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2150 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
9a443537 2151
0576cbde 2152 cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
9a443537 2153
2154 roce_set_field(cq_context->cqc_byte_20,
2155 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
0576cbde 2156 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
9a443537 2157 /* Dedicated hardware, directly set 0 */
2158 roce_set_field(cq_context->cqc_byte_20,
2159 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2160 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2161 /**
2162 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2163 * using 4K page, and shift more 32 because of
2164 * caculating the high 32 bit value evaluated to hardware.
2165 */
2166 roce_set_field(cq_context->cqc_byte_20,
2167 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2168 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
8f3e9f3e 2169 tptr_dma_addr >> 44);
9a443537 2170
0576cbde 2171 cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
9a443537 2172
2173 roce_set_field(cq_context->cqc_byte_32,
2174 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2175 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2176 roce_set_bit(cq_context->cqc_byte_32,
2177 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2178 roce_set_bit(cq_context->cqc_byte_32,
2179 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2180 roce_set_bit(cq_context->cqc_byte_32,
2181 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2182 roce_set_bit(cq_context->cqc_byte_32,
2183 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2184 0);
e84e40be 2185 /* The initial value of cq's ci is 0 */
9a443537 2186 roce_set_field(cq_context->cqc_byte_32,
2187 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2188 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
9a443537 2189}
2190
b156269d 2191static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
2192{
2193 return -EOPNOTSUPP;
2194}
2195
d61d6de0
BVA		 2196static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2197 enum ib_cq_notify_flags flags)
9a443537 2198{
2199 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2200 u32 notification_flag;
0576cbde 2201 __le32 doorbell[2];
9a443537 2202
2203 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2204 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2205 /*
e84e40be
S		 2206 * flags = 0; Notification Flag = 1, next
2207 * flags = 1; Notification Flag = 0, solocited
2208 */
0576cbde 2209 doorbell[0] =
2210 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
9a443537 2211 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2212 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2213 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2214 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2215 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2216 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2217 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2218 hr_cq->cqn | notification_flag);
2219
2220 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2221
87809f83 2222 return 0;
9a443537 2223}
2224
2225static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2226 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2227{
2228 int qpn;
2229 int is_send;
2230 u16 wqe_ctr;
2231 u32 status;
2232 u32 opcode;
2233 struct hns_roce_cqe *cqe;
2234 struct hns_roce_qp *hr_qp;
2235 struct hns_roce_wq *wq;
2236 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2237 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2238 struct device *dev = &hr_dev->pdev->dev;
2239
2240 /* Find cqe according consumer index */
2241 cqe = next_cqe_sw(hr_cq);
2242 if (!cqe)
2243 return -EAGAIN;
2244
2245 ++hr_cq->cons_index;
2246 /* Memory barrier */
2247 rmb();
2248 /* 0->SQ, 1->RQ */
2249 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2250
2251 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2252 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2253 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2254 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2255 CQE_BYTE_20_PORT_NUM_S) +
2256 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2257 CQE_BYTE_16_LOCAL_QPN_S) *
2258 HNS_ROCE_MAX_PORTS;
2259 } else {
2260 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2261 CQE_BYTE_16_LOCAL_QPN_S);
2262 }
2263
2264 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2265 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2266 if (unlikely(!hr_qp)) {
2267 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2268 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2269 return -EINVAL;
2270 }
2271
2272 *cur_qp = hr_qp;
2273 }
2274
2275 wc->qp = &(*cur_qp)->ibqp;
2276 wc->vendor_err = 0;
2277
2278 status = roce_get_field(cqe->cqe_byte_4,
2279 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2280 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2281 HNS_ROCE_CQE_STATUS_MASK;
2282 switch (status) {
2283 case HNS_ROCE_CQE_SUCCESS:
2284 wc->status = IB_WC_SUCCESS;
2285 break;
2286 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2287 wc->status = IB_WC_LOC_LEN_ERR;
2288 break;
2289 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2290 wc->status = IB_WC_LOC_QP_OP_ERR;
2291 break;
2292 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2293 wc->status = IB_WC_LOC_PROT_ERR;
2294 break;
2295 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2296 wc->status = IB_WC_WR_FLUSH_ERR;
2297 break;
2298 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2299 wc->status = IB_WC_MW_BIND_ERR;
2300 break;
2301 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2302 wc->status = IB_WC_BAD_RESP_ERR;
2303 break;
2304 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2305 wc->status = IB_WC_LOC_ACCESS_ERR;
2306 break;
2307 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2308 wc->status = IB_WC_REM_INV_REQ_ERR;
2309 break;
2310 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2311 wc->status = IB_WC_REM_ACCESS_ERR;
2312 break;
2313 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2314 wc->status = IB_WC_REM_OP_ERR;
2315 break;
2316 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2317 wc->status = IB_WC_RETRY_EXC_ERR;
2318 break;
2319 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2320 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2321 break;
2322 default:
2323 wc->status = IB_WC_GENERAL_ERR;
2324 break;
2325 }
2326
2327 /* CQE status error, directly return */
2328 if (wc->status != IB_WC_SUCCESS)
2329 return 0;
2330
2331 if (is_send) {
2332 /* SQ conrespond to CQE */
2333 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2334 CQE_BYTE_4_WQE_INDEX_M,
1bdab400
S		 2335 CQE_BYTE_4_WQE_INDEX_S)&
2336 ((*cur_qp)->sq.wqe_cnt-1));
8b9b8d14 2337 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
9a443537 2338 case HNS_ROCE_WQE_OPCODE_SEND:
2339 wc->opcode = IB_WC_SEND;
2340 break;
2341 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2342 wc->opcode = IB_WC_RDMA_READ;
2343 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2344 break;
2345 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2346 wc->opcode = IB_WC_RDMA_WRITE;
2347 break;
2348 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2349 wc->opcode = IB_WC_LOCAL_INV;
2350 break;
2351 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2352 wc->opcode = IB_WC_SEND;
2353 break;
2354 default:
2355 wc->status = IB_WC_GENERAL_ERR;
2356 break;
2357 }
8b9b8d14 2358 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
9a443537 2359 IB_WC_WITH_IMM : 0);
2360
2361 wq = &(*cur_qp)->sq;
2362 if ((*cur_qp)->sq_signal_bits) {
2363 /*
e84e40be
S		 2364 * If sg_signal_bit is 1,
2365 * firstly tail pointer updated to wqe
2366 * which current cqe correspond to
2367 */
9a443537 2368 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2369 CQE_BYTE_4_WQE_INDEX_M,
2370 CQE_BYTE_4_WQE_INDEX_S);
2371 wq->tail += (wqe_ctr - (u16)wq->tail) &
2372 (wq->wqe_cnt - 1);
2373 }
2374 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2375 ++wq->tail;
5f110ac4 2376 } else {
9a443537 2377 /* RQ conrespond to CQE */
2378 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2379 opcode = roce_get_field(cqe->cqe_byte_4,
2380 CQE_BYTE_4_OPERATION_TYPE_M,
2381 CQE_BYTE_4_OPERATION_TYPE_S) &
2382 HNS_ROCE_CQE_OPCODE_MASK;
2383 switch (opcode) {
2384 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2385 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2386 wc->wc_flags = IB_WC_WITH_IMM;
ccb8a29e
JG		 2387 wc->ex.imm_data =
2388 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
9a443537 2389 break;
2390 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2391 if (roce_get_bit(cqe->cqe_byte_4,
2392 CQE_BYTE_4_IMM_INDICATOR_S)) {
2393 wc->opcode = IB_WC_RECV;
2394 wc->wc_flags = IB_WC_WITH_IMM;
ccb8a29e
JG		 2395 wc->ex.imm_data = cpu_to_be32(
2396 le32_to_cpu(cqe->immediate_data));
9a443537 2397 } else {
2398 wc->opcode = IB_WC_RECV;
2399 wc->wc_flags = 0;
2400 }
2401 break;
2402 default:
2403 wc->status = IB_WC_GENERAL_ERR;
2404 break;
2405 }
2406
2407 /* Update tail pointer, record wr_id */
2408 wq = &(*cur_qp)->rq;
2409 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2410 ++wq->tail;
2411 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2412 CQE_BYTE_20_SL_S);
2413 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2414 CQE_BYTE_20_REMOTE_QPN_M,
2415 CQE_BYTE_20_REMOTE_QPN_S);
2416 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2417 CQE_BYTE_20_GRH_PRESENT_S) ?
2418 IB_WC_GRH : 0);
2419 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2420 CQE_BYTE_28_P_KEY_IDX_M,
2421 CQE_BYTE_28_P_KEY_IDX_S);
2422 }
2423
2424 return 0;
2425}
2426
2427int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2428{
2429 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2430 struct hns_roce_qp *cur_qp = NULL;
2431 unsigned long flags;
2432 int npolled;
2433 int ret = 0;
2434
2435 spin_lock_irqsave(&hr_cq->lock, flags);
2436
2437 for (npolled = 0; npolled < num_entries; ++npolled) {
2438 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2439 if (ret)
2440 break;
2441 }
2442
8f3e9f3e
WHX		 2443 if (npolled) {
2444 *hr_cq->tptr_addr = hr_cq->cons_index &
2445 ((hr_cq->cq_depth << 1) - 1);
2446
2447 /* Memroy barrier */
2448 wmb();
a4be892e 2449 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
8f3e9f3e 2450 }
9a443537 2451
2452 spin_unlock_irqrestore(&hr_cq->lock, flags);
2453
2454 if (ret == 0 || ret == -EAGAIN)
2455 return npolled;
2456 else
2457 return ret;
2458}
2459
d61d6de0
BVA		 2460static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2461 struct hns_roce_hem_table *table, int obj,
2462 int step_idx)
97f0e39f
WHX		 2463{
2464 struct device *dev = &hr_dev->pdev->dev;
2465 struct hns_roce_v1_priv *priv;
2466 unsigned long end = 0, flags = 0;
0576cbde 2467 __le32 bt_cmd_val[2] = {0};
97f0e39f
WHX		 2468 void __iomem *bt_cmd;
2469 u64 bt_ba = 0;
2470
016a0059 2471 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
97f0e39f
WHX		 2472
2473 switch (table->type) {
2474 case HEM_TYPE_QPC:
2475 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2476 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2477 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2478 break;
2479 case HEM_TYPE_MTPT:
2480 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2481 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2482 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2483 break;
2484 case HEM_TYPE_CQC:
2485 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2486 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2487 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2488 break;
2489 case HEM_TYPE_SRQC:
2490 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2491 return -EINVAL;
2492 default:
2493 return 0;
2494 }
2495 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2496 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2497 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2498 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2499
2500 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2501
2502 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2503
2504 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2505 while (1) {
2506 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2507 if (!(time_before(jiffies, end))) {
2508 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2509 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2510 flags);
2511 return -EBUSY;
2512 }
2513 } else {
2514 break;
2515 }
2516 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2517 }
2518
0576cbde 2519 bt_cmd_val[0] = (__le32)bt_ba;
97f0e39f
WHX		 2520 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2521 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2522 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2523
2524 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2525
2526 return 0;
2527}
2528
9a443537 2529static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2530 struct hns_roce_mtt *mtt,
2531 enum hns_roce_qp_state cur_state,
2532 enum hns_roce_qp_state new_state,
2533 struct hns_roce_qp_context *context,
2534 struct hns_roce_qp *hr_qp)
2535{
2536 static const u16
2537 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2538 [HNS_ROCE_QP_STATE_RST] = {
2539 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2540 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2541 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2542 },
2543 [HNS_ROCE_QP_STATE_INIT] = {
2544 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2545 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2546 /* Note: In v1 engine, HW doesn't support RST2INIT.
2547 * We use RST2INIT cmd instead of INIT2INIT.
2548 */
2549 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2550 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2551 },
2552 [HNS_ROCE_QP_STATE_RTR] = {
2553 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2554 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2555 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2556 },
2557 [HNS_ROCE_QP_STATE_RTS] = {
2558 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2559 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2560 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2561 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2562 },
2563 [HNS_ROCE_QP_STATE_SQD] = {
2564 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2565 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2566 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2567 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2568 },
2569 [HNS_ROCE_QP_STATE_ERR] = {
2570 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2571 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2572 }
2573 };
2574
2575 struct hns_roce_cmd_mailbox *mailbox;
2576 struct device *dev = &hr_dev->pdev->dev;
2577 int ret = 0;
2578
2579 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2580 new_state >= HNS_ROCE_QP_NUM_STATE ||
2581 !op[cur_state][new_state]) {
2582 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2583 cur_state, new_state);
2584 return -EINVAL;
2585 }
2586
2587 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2588 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2589 HNS_ROCE_CMD_2RST_QP,
6b877c32 2590 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2591
2592 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2593 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2594 HNS_ROCE_CMD_2ERR_QP,
6b877c32 2595 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2596
2597 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2598 if (IS_ERR(mailbox))
2599 return PTR_ERR(mailbox);
2600
2601 memcpy(mailbox->buf, context, sizeof(*context));
2602
2603 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2604 op[cur_state][new_state],
6b877c32 2605 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 2606
2607 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2608 return ret;
2609}
2610
2611static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2612 int attr_mask, enum ib_qp_state cur_state,
2613 enum ib_qp_state new_state)
2614{
2615 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2616 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2617 struct hns_roce_sqp_context *context;
2618 struct device *dev = &hr_dev->pdev->dev;
2619 dma_addr_t dma_handle = 0;
0576cbde 2620 u32 __iomem *addr;
9a443537 2621 int rq_pa_start;
0576cbde 2622 __le32 tmp;
9a443537 2623 u32 reg_val;
2624 u64 *mtts;
9a443537 2625
2626 context = kzalloc(sizeof(*context), GFP_KERNEL);
2627 if (!context)
2628 return -ENOMEM;
2629
2630 /* Search QP buf's MTTs */
6a93c77a 2631 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
9a443537 2632 hr_qp->mtt.first_seg, &dma_handle);
2633 if (!mtts) {
2634 dev_err(dev, "qp buf pa find failed\n");
2635 goto out;
2636 }
2637
2638 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2639 roce_set_field(context->qp1c_bytes_4,
2640 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2641 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2642 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2643 roce_set_field(context->qp1c_bytes_4,
2644 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2645 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2646 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2647 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2648 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2649
0576cbde 2650 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
9a443537 2651 roce_set_field(context->qp1c_bytes_12,
2652 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2653 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2654 ((u32)(dma_handle >> 32)));
2655
2656 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2657 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2658 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
7716809e 2659 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
9a443537 2660 roce_set_bit(context->qp1c_bytes_16,
2661 QP1C_BYTES_16_SIGNALING_TYPE_S,
0576cbde 2662 le32_to_cpu(hr_qp->sq_signal_bits));
9a443537 2663 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2664 1);
2665 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2666 1);
2667 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2668 0);
2669
2670 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2671 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2672 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2673 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2674
2675 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
0576cbde 2676 context->cur_rq_wqe_ba_l =
2677 cpu_to_le32((u32)(mtts[rq_pa_start]));
9a443537 2678
2679 roce_set_field(context->qp1c_bytes_28,
2680 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2681 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2682 (mtts[rq_pa_start]) >> 32);
2683 roce_set_field(context->qp1c_bytes_28,
2684 QP1C_BYTES_28_RQ_CUR_IDX_M,
2685 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2686
2687 roce_set_field(context->qp1c_bytes_32,
2688 QP1C_BYTES_32_RX_CQ_NUM_M,
2689 QP1C_BYTES_32_RX_CQ_NUM_S,
2690 to_hr_cq(ibqp->recv_cq)->cqn);
2691 roce_set_field(context->qp1c_bytes_32,
2692 QP1C_BYTES_32_TX_CQ_NUM_M,
2693 QP1C_BYTES_32_TX_CQ_NUM_S,
2694 to_hr_cq(ibqp->send_cq)->cqn);
2695
0576cbde 2696 context->cur_sq_wqe_ba_l = cpu_to_le32((u32)mtts[0]);
9a443537 2697
2698 roce_set_field(context->qp1c_bytes_40,
2699 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2700 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2701 (mtts[0]) >> 32);
2702 roce_set_field(context->qp1c_bytes_40,
2703 QP1C_BYTES_40_SQ_CUR_IDX_M,
2704 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2705
2706 /* Copy context to QP1C register */
cc4ed08b
BVA		 2707 addr = (u32 __iomem *)(hr_dev->reg_base +
2708 ROCEE_QP1C_CFG0_0_REG +
2709 hr_qp->phy_port * sizeof(*context));
9a443537 2710
0576cbde 2711 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2712 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2713 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2714 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2715 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2716 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2717 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2718 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2719 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2720 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
9a443537 2721 }
2722
2723 /* Modify QP1C status */
2724 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 2725 hr_qp->phy_port * sizeof(*context));
0576cbde 2726 tmp = cpu_to_le32(reg_val);
2727 roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
9a443537 2728 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
0576cbde 2729 reg_val = le32_to_cpu(tmp);
9a443537 2730 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
7716809e 2731 hr_qp->phy_port * sizeof(*context), reg_val);
9a443537 2732
2733 hr_qp->state = new_state;
2734 if (new_state == IB_QPS_RESET) {
2735 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2736 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2737 if (ibqp->send_cq != ibqp->recv_cq)
2738 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2739 hr_qp->qpn, NULL);
2740
2741 hr_qp->rq.head = 0;
2742 hr_qp->rq.tail = 0;
2743 hr_qp->sq.head = 0;
2744 hr_qp->sq.tail = 0;
2745 hr_qp->sq_next_wqe = 0;
2746 }
2747
2748 kfree(context);
2749 return 0;
2750
2751out:
2752 kfree(context);
2753 return -EINVAL;
2754}
2755
2756static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2757 int attr_mask, enum ib_qp_state cur_state,
2758 enum ib_qp_state new_state)
2759{
2760 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2761 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2762 struct device *dev = &hr_dev->pdev->dev;
2763 struct hns_roce_qp_context *context;
d8966fcd 2764 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
9a443537 2765 dma_addr_t dma_handle_2 = 0;
2766 dma_addr_t dma_handle = 0;
0576cbde 2767 __le32 doorbell[2] = {0};
9a443537 2768 int rq_pa_start = 0;
9a443537 2769 u64 *mtts_2 = NULL;
2770 int ret = -EINVAL;
2771 u64 *mtts = NULL;
2772 int port;
d8966fcd 2773 u8 port_num;
9a443537 2774 u8 *dmac;
2775 u8 *smac;
2776
2777 context = kzalloc(sizeof(*context), GFP_KERNEL);
2778 if (!context)
2779 return -ENOMEM;
2780
2781 /* Search qp buf's mtts */
6a93c77a 2782 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table,
9a443537 2783 hr_qp->mtt.first_seg, &dma_handle);
2784 if (mtts == NULL) {
2785 dev_err(dev, "qp buf pa find failed\n");
2786 goto out;
2787 }
2788
2789 /* Search IRRL's mtts */
6a93c77a
SX		 2790 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2791 hr_qp->qpn, &dma_handle_2);
9a443537 2792 if (mtts_2 == NULL) {
2793 dev_err(dev, "qp irrl_table find failed\n");
2794 goto out;
2795 }
2796
2797 /*
e84e40be
S		 2798 * Reset to init
2799 * Mandatory param:
2800 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2801 * Optional param: NA
2802 */
9a443537 2803 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2804 roce_set_field(context->qpc_bytes_4,
2805 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2806 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2807 to_hr_qp_type(hr_qp->ibqp.qp_type));
2808
2809 roce_set_bit(context->qpc_bytes_4,
2810 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2811 roce_set_bit(context->qpc_bytes_4,
2812 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2813 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2814 roce_set_bit(context->qpc_bytes_4,
2815 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2816 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2817 );
2818 roce_set_bit(context->qpc_bytes_4,
2819 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2820 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2821 );
2822 roce_set_bit(context->qpc_bytes_4,
2823 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2824 roce_set_field(context->qpc_bytes_4,
2825 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2826 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2827 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2828 roce_set_field(context->qpc_bytes_4,
2829 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2830 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2831 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2832 roce_set_field(context->qpc_bytes_4,
2833 QP_CONTEXT_QPC_BYTES_4_PD_M,
2834 QP_CONTEXT_QPC_BYTES_4_PD_S,
2835 to_hr_pd(ibqp->pd)->pdn);
2836 hr_qp->access_flags = attr->qp_access_flags;
2837 roce_set_field(context->qpc_bytes_8,
2838 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2839 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2840 to_hr_cq(ibqp->send_cq)->cqn);
2841 roce_set_field(context->qpc_bytes_8,
2842 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2843 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2844 to_hr_cq(ibqp->recv_cq)->cqn);
2845
2846 if (ibqp->srq)
2847 roce_set_field(context->qpc_bytes_12,
2848 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2849 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2850 to_hr_srq(ibqp->srq)->srqn);
2851
2852 roce_set_field(context->qpc_bytes_12,
2853 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2854 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2855 attr->pkey_index);
2856 hr_qp->pkey_index = attr->pkey_index;
2857 roce_set_field(context->qpc_bytes_16,
2858 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2859 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2860
2861 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2862 roce_set_field(context->qpc_bytes_4,
2863 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2864 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2865 to_hr_qp_type(hr_qp->ibqp.qp_type));
2866 roce_set_bit(context->qpc_bytes_4,
2867 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2868 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2869 roce_set_bit(context->qpc_bytes_4,
2870 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2871 !!(attr->qp_access_flags &
2872 IB_ACCESS_REMOTE_READ));
2873 roce_set_bit(context->qpc_bytes_4,
2874 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2875 !!(attr->qp_access_flags &
2876 IB_ACCESS_REMOTE_WRITE));
2877 } else {
2878 roce_set_bit(context->qpc_bytes_4,
2879 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2880 !!(hr_qp->access_flags &
2881 IB_ACCESS_REMOTE_READ));
2882 roce_set_bit(context->qpc_bytes_4,
2883 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2884 !!(hr_qp->access_flags &
2885 IB_ACCESS_REMOTE_WRITE));
2886 }
2887
2888 roce_set_bit(context->qpc_bytes_4,
2889 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2890 roce_set_field(context->qpc_bytes_4,
2891 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2892 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2893 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2894 roce_set_field(context->qpc_bytes_4,
2895 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2896 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2897 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2898 roce_set_field(context->qpc_bytes_4,
2899 QP_CONTEXT_QPC_BYTES_4_PD_M,
2900 QP_CONTEXT_QPC_BYTES_4_PD_S,
2901 to_hr_pd(ibqp->pd)->pdn);
2902
2903 roce_set_field(context->qpc_bytes_8,
2904 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2905 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2906 to_hr_cq(ibqp->send_cq)->cqn);
2907 roce_set_field(context->qpc_bytes_8,
2908 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2909 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2910 to_hr_cq(ibqp->recv_cq)->cqn);
2911
2912 if (ibqp->srq)
2913 roce_set_field(context->qpc_bytes_12,
2914 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2915 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2916 to_hr_srq(ibqp->srq)->srqn);
2917 if (attr_mask & IB_QP_PKEY_INDEX)
2918 roce_set_field(context->qpc_bytes_12,
2919 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2920 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2921 attr->pkey_index);
2922 else
2923 roce_set_field(context->qpc_bytes_12,
2924 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2925 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2926 hr_qp->pkey_index);
2927
2928 roce_set_field(context->qpc_bytes_16,
2929 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2930 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2931 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2932 if ((attr_mask & IB_QP_ALT_PATH) ||
2933 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2934 (attr_mask & IB_QP_PKEY_INDEX) ||
2935 (attr_mask & IB_QP_QKEY)) {
2936 dev_err(dev, "INIT2RTR attr_mask error\n");
2937 goto out;
2938 }
2939
44c58487 2940 dmac = (u8 *)attr->ah_attr.roce.dmac;
9a443537 2941
0576cbde 2942 context->sq_rq_bt_l = cpu_to_le32((u32)(dma_handle));
9a443537 2943 roce_set_field(context->qpc_bytes_24,
2944 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2945 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2946 ((u32)(dma_handle >> 32)));
2947 roce_set_bit(context->qpc_bytes_24,
2948 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2949 1);
2950 roce_set_field(context->qpc_bytes_24,
2951 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2952 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2953 attr->min_rnr_timer);
0576cbde 2954 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
9a443537 2955 roce_set_field(context->qpc_bytes_32,
2956 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2957 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2958 ((u32)(dma_handle_2 >> 32)) &
2959 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2960 roce_set_field(context->qpc_bytes_32,
2961 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2962 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2963 roce_set_bit(context->qpc_bytes_32,
2964 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2965 1);
2966 roce_set_bit(context->qpc_bytes_32,
2967 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
0576cbde 2968 le32_to_cpu(hr_qp->sq_signal_bits));
9a443537 2969
80596c67
LO		 2970 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2971 hr_qp->port;
2972 smac = (u8 *)hr_dev->dev_addr[port];
2973 /* when dmac equals smac or loop_idc is 1, it should loopback */
2974 if (ether_addr_equal_unaligned(dmac, smac) ||
2975 hr_dev->loop_idc == 0x1)
9a443537 2976 roce_set_bit(context->qpc_bytes_32,
80596c67 2977 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
9a443537 2978
2979 roce_set_bit(context->qpc_bytes_32,
2980 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
d8966fcd 2981 rdma_ah_get_ah_flags(&attr->ah_attr));
9a443537 2982 roce_set_field(context->qpc_bytes_32,
2983 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2984 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2985 ilog2((unsigned int)attr->max_dest_rd_atomic));
2986
512f4f16
LO		 2987 if (attr_mask & IB_QP_DEST_QPN)
2988 roce_set_field(context->qpc_bytes_36,
2989 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2990 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2991 attr->dest_qp_num);
9a443537 2992
2993 /* Configure GID index */
d8966fcd 2994 port_num = rdma_ah_get_port_num(&attr->ah_attr);
9a443537 2995 roce_set_field(context->qpc_bytes_36,
2996 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2997 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
d8966fcd
DC		 2998 hns_get_gid_index(hr_dev,
2999 port_num - 1,
3000 grh->sgid_index));
9a443537 3001
3002 memcpy(&(context->dmac_l), dmac, 4);
3003
3004 roce_set_field(context->qpc_bytes_44,
3005 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3006 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
3007 *((u16 *)(&dmac[4])));
3008 roce_set_field(context->qpc_bytes_44,
3009 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
3010 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
d8966fcd 3011 rdma_ah_get_static_rate(&attr->ah_attr));
9a443537 3012 roce_set_field(context->qpc_bytes_44,
3013 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3014 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
d8966fcd 3015 grh->hop_limit);
9a443537 3016
3017 roce_set_field(context->qpc_bytes_48,
3018 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3019 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
d8966fcd 3020 grh->flow_label);
9a443537 3021 roce_set_field(context->qpc_bytes_48,
3022 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3023 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
d8966fcd 3024 grh->traffic_class);
9a443537 3025 roce_set_field(context->qpc_bytes_48,
3026 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3027 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
3028
d8966fcd
DC		 3029 memcpy(context->dgid, grh->dgid.raw,
3030 sizeof(grh->dgid.raw));
9a443537 3031
3032 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
3033 roce_get_field(context->qpc_bytes_44,
3034 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3035 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
3036
3037 roce_set_field(context->qpc_bytes_68,
3038 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
1fad5fab
LO		 3039 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
3040 hr_qp->rq.head);
9a443537 3041 roce_set_field(context->qpc_bytes_68,
3042 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3043 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3044
3045 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
0576cbde 3046 context->cur_rq_wqe_ba_l =
3047 cpu_to_le32((u32)(mtts[rq_pa_start]));
9a443537 3048
3049 roce_set_field(context->qpc_bytes_76,
3050 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3051 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3052 mtts[rq_pa_start] >> 32);
3053 roce_set_field(context->qpc_bytes_76,
3054 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3055 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3056
3057 context->rx_rnr_time = 0;
3058
3059 roce_set_field(context->qpc_bytes_84,
3060 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3061 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3062 attr->rq_psn - 1);
3063 roce_set_field(context->qpc_bytes_84,
3064 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3065 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3066
3067 roce_set_field(context->qpc_bytes_88,
3068 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3069 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3070 attr->rq_psn);
3071 roce_set_bit(context->qpc_bytes_88,
3072 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3073 roce_set_bit(context->qpc_bytes_88,
3074 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3075 roce_set_field(context->qpc_bytes_88,
3076 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3077 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3078 0);
3079 roce_set_field(context->qpc_bytes_88,
3080 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3081 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3082 0);
3083
3084 context->dma_length = 0;
3085 context->r_key = 0;
3086 context->va_l = 0;
3087 context->va_h = 0;
3088
3089 roce_set_field(context->qpc_bytes_108,
3090 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3091 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3092 roce_set_bit(context->qpc_bytes_108,
3093 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3094 roce_set_bit(context->qpc_bytes_108,
3095 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3096
3097 roce_set_field(context->qpc_bytes_112,
3098 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3099 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3100 roce_set_field(context->qpc_bytes_112,
3101 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3102 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3103
3104 /* For chip resp ack */
3105 roce_set_field(context->qpc_bytes_156,
3106 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3107 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 3108 hr_qp->phy_port);
9a443537 3109 roce_set_field(context->qpc_bytes_156,
3110 QP_CONTEXT_QPC_BYTES_156_SL_M,
d8966fcd
DC		 3111 QP_CONTEXT_QPC_BYTES_156_SL_S,
3112 rdma_ah_get_sl(&attr->ah_attr));
3113 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
9a443537 3114 } else if (cur_state == IB_QPS_RTR &&
3115 new_state == IB_QPS_RTS) {
3116 /* If exist optional param, return error */
3117 if ((attr_mask & IB_QP_ALT_PATH) ||
3118 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3119 (attr_mask & IB_QP_QKEY) ||
3120 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3121 (attr_mask & IB_QP_CUR_STATE) ||
3122 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3123 dev_err(dev, "RTR2RTS attr_mask error\n");
3124 goto out;
3125 }
3126
0576cbde 3127 context->rx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
9a443537 3128
3129 roce_set_field(context->qpc_bytes_120,
3130 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3131 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3132 (mtts[0]) >> 32);
3133
3134 roce_set_field(context->qpc_bytes_124,
3135 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3136 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3137 roce_set_field(context->qpc_bytes_124,
3138 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3139 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3140
3141 roce_set_field(context->qpc_bytes_128,
3142 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3143 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3144 attr->sq_psn);
3145 roce_set_bit(context->qpc_bytes_128,
3146 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3147 roce_set_field(context->qpc_bytes_128,
3148 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3149 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3150 0);
3151 roce_set_bit(context->qpc_bytes_128,
3152 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3153
3154 roce_set_field(context->qpc_bytes_132,
3155 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3156 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3157 roce_set_field(context->qpc_bytes_132,
3158 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3159 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3160
3161 roce_set_field(context->qpc_bytes_136,
3162 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3163 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3164 attr->sq_psn);
3165 roce_set_field(context->qpc_bytes_136,
3166 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3167 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3168 attr->sq_psn);
3169
3170 roce_set_field(context->qpc_bytes_140,
3171 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3172 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3173 (attr->sq_psn >> SQ_PSN_SHIFT));
3174 roce_set_field(context->qpc_bytes_140,
3175 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3176 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3177 roce_set_bit(context->qpc_bytes_140,
3178 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3179
9a443537 3180 roce_set_field(context->qpc_bytes_148,
3181 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3182 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3183 roce_set_field(context->qpc_bytes_148,
3184 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
7c7a4ea1
LO		 3185 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3186 attr->retry_cnt);
9a443537 3187 roce_set_field(context->qpc_bytes_148,
3188 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
7c7a4ea1
LO		 3189 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3190 attr->rnr_retry);
9a443537 3191 roce_set_field(context->qpc_bytes_148,
3192 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3193 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3194
3195 context->rnr_retry = 0;
3196
3197 roce_set_field(context->qpc_bytes_156,
3198 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3199 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3200 attr->retry_cnt);
c6c3bfea
LO		 3201 if (attr->timeout < 0x12) {
3202 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3203 attr->timeout);
3204 roce_set_field(context->qpc_bytes_156,
3205 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3206 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3207 0x12);
3208 } else {
3209 roce_set_field(context->qpc_bytes_156,
3210 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3211 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3212 attr->timeout);
3213 }
9a443537 3214 roce_set_field(context->qpc_bytes_156,
3215 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3216 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3217 attr->rnr_retry);
3218 roce_set_field(context->qpc_bytes_156,
3219 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3220 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
7716809e 3221 hr_qp->phy_port);
9a443537 3222 roce_set_field(context->qpc_bytes_156,
3223 QP_CONTEXT_QPC_BYTES_156_SL_M,
d8966fcd
DC		 3224 QP_CONTEXT_QPC_BYTES_156_SL_S,
3225 rdma_ah_get_sl(&attr->ah_attr));
3226 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
9a443537 3227 roce_set_field(context->qpc_bytes_156,
3228 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3229 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3230 ilog2((unsigned int)attr->max_rd_atomic));
3231 roce_set_field(context->qpc_bytes_156,
3232 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3233 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3234 context->pkt_use_len = 0;
3235
3236 roce_set_field(context->qpc_bytes_164,
3237 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3238 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3239 roce_set_field(context->qpc_bytes_164,
3240 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3241 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3242
3243 roce_set_field(context->qpc_bytes_168,
3244 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3245 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3246 attr->sq_psn);
3247 roce_set_field(context->qpc_bytes_168,
3248 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3249 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3250 roce_set_field(context->qpc_bytes_168,
3251 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3252 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3253 roce_set_bit(context->qpc_bytes_168,
3254 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3255 roce_set_bit(context->qpc_bytes_168,
3256 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3257 roce_set_bit(context->qpc_bytes_168,
3258 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3259 context->sge_use_len = 0;
3260
3261 roce_set_field(context->qpc_bytes_176,
3262 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3263 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3264 roce_set_field(context->qpc_bytes_176,
3265 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3266 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3267 0);
3268 roce_set_field(context->qpc_bytes_180,
3269 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3270 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3271 roce_set_field(context->qpc_bytes_180,
3272 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3273 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3274
0576cbde 3275 context->tx_cur_sq_wqe_ba_l = cpu_to_le32((u32)(mtts[0]));
9a443537 3276
3277 roce_set_field(context->qpc_bytes_188,
3278 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3279 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3280 (mtts[0]) >> 32);
3281 roce_set_bit(context->qpc_bytes_188,
3282 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3283 roce_set_field(context->qpc_bytes_188,
3284 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3285 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3286 0);
deb17f6f 3287 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
9a443537 3288 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3289 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3290 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3291 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3292 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3293 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
deb17f6f
LO		 3294 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3295 dev_err(dev, "not support this status migration\n");
9a443537 3296 goto out;
3297 }
3298
3299 /* Every status migrate must change state */
3300 roce_set_field(context->qpc_bytes_144,
3301 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
1dec243a 3302 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
9a443537 3303
3304 /* SW pass context to HW */
3305 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3306 to_hns_roce_state(cur_state),
3307 to_hns_roce_state(new_state), context,
3308 hr_qp);
3309 if (ret) {
3310 dev_err(dev, "hns_roce_qp_modify failed\n");
3311 goto out;
3312 }
3313
3314 /*
e84e40be
S		 3315 * Use rst2init to instead of init2init with drv,
3316 * need to hw to flash RQ HEAD by DB again
3317 */
9a443537 3318 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3319 /* Memory barrier */
3320 wmb();
9a443537 3321
509bf0c2
LO		 3322 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3323 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3324 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3325 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3326 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3327 RQ_DOORBELL_U32_8_CMD_S, 1);
3328 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3329
3330 if (ibqp->uobject) {
3331 hr_qp->rq.db_reg_l = hr_dev->reg_base +
2d407888 3332 hr_dev->odb_offset +
509bf0c2 3333 DB_REG_OFFSET * hr_dev->priv_uar.index;
9a443537 3334 }
509bf0c2
LO		 3335
3336 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
9a443537 3337 }
3338
3339 hr_qp->state = new_state;
3340
3341 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3342 hr_qp->resp_depth = attr->max_dest_rd_atomic;
7716809e
LO		 3343 if (attr_mask & IB_QP_PORT) {
3344 hr_qp->port = attr->port_num - 1;
3345 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3346 }
9a443537 3347
3348 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3349 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3350 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3351 if (ibqp->send_cq != ibqp->recv_cq)
3352 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3353 hr_qp->qpn, NULL);
3354
3355 hr_qp->rq.head = 0;
3356 hr_qp->rq.tail = 0;
3357 hr_qp->sq.head = 0;
3358 hr_qp->sq.tail = 0;
3359 hr_qp->sq_next_wqe = 0;
3360 }
3361out:
3362 kfree(context);
3363 return ret;
3364}
3365
d61d6de0
BVA		 3366static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3367 const struct ib_qp_attr *attr, int attr_mask,
3368 enum ib_qp_state cur_state,
3369 enum ib_qp_state new_state)
9a443537 3370{
3371
3372 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3373 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3374 new_state);
3375 else
3376 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3377 new_state);
3378}
3379
3380static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3381{
3382 switch (state) {
3383 case HNS_ROCE_QP_STATE_RST:
3384 return IB_QPS_RESET;
3385 case HNS_ROCE_QP_STATE_INIT:
3386 return IB_QPS_INIT;
3387 case HNS_ROCE_QP_STATE_RTR:
3388 return IB_QPS_RTR;
3389 case HNS_ROCE_QP_STATE_RTS:
3390 return IB_QPS_RTS;
3391 case HNS_ROCE_QP_STATE_SQD:
3392 return IB_QPS_SQD;
3393 case HNS_ROCE_QP_STATE_ERR:
3394 return IB_QPS_ERR;
3395 default:
3396 return IB_QPS_ERR;
3397 }
3398}
3399
3400static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3401 struct hns_roce_qp *hr_qp,
3402 struct hns_roce_qp_context *hr_context)
3403{
3404 struct hns_roce_cmd_mailbox *mailbox;
3405 int ret;
3406
3407 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3408 if (IS_ERR(mailbox))
3409 return PTR_ERR(mailbox);
3410
3411 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3412 HNS_ROCE_CMD_QUERY_QP,
6b877c32 3413 HNS_ROCE_CMD_TIMEOUT_MSECS);
9a443537 3414 if (!ret)
3415 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3416 else
3417 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3418
3419 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3420
3421 return ret;
3422}
3423
9eefa953
LO		 3424static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3425 int qp_attr_mask,
3426 struct ib_qp_init_attr *qp_init_attr)
3427{
3428 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3429 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3430 struct hns_roce_sqp_context context;
3431 u32 addr;
3432
3433 mutex_lock(&hr_qp->mutex);
3434
3435 if (hr_qp->state == IB_QPS_RESET) {
3436 qp_attr->qp_state = IB_QPS_RESET;
3437 goto done;
3438 }
3439
3440 addr = ROCEE_QP1C_CFG0_0_REG +
3441 hr_qp->port * sizeof(struct hns_roce_sqp_context);
0576cbde 3442 context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3443 context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3444 context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3445 context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3446 context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3447 context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3448 context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3449 context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3450 context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3451 context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
9eefa953
LO		 3452
3453 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3454 QP1C_BYTES_4_QP_STATE_M,
3455 QP1C_BYTES_4_QP_STATE_S);
3456 qp_attr->qp_state = hr_qp->state;
3457 qp_attr->path_mtu = IB_MTU_256;
3458 qp_attr->path_mig_state = IB_MIG_ARMED;
3459 qp_attr->qkey = QKEY_VAL;
2bf910d4 3460 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
9eefa953
LO		 3461 qp_attr->rq_psn = 0;
3462 qp_attr->sq_psn = 0;
3463 qp_attr->dest_qp_num = 1;
3464 qp_attr->qp_access_flags = 6;
3465
3466 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3467 QP1C_BYTES_20_PKEY_IDX_M,
3468 QP1C_BYTES_20_PKEY_IDX_S);
3469 qp_attr->port_num = hr_qp->port + 1;
3470 qp_attr->sq_draining = 0;
3471 qp_attr->max_rd_atomic = 0;
3472 qp_attr->max_dest_rd_atomic = 0;
3473 qp_attr->min_rnr_timer = 0;
3474 qp_attr->timeout = 0;
3475 qp_attr->retry_cnt = 0;
3476 qp_attr->rnr_retry = 0;
3477 qp_attr->alt_timeout = 0;
3478
3479done:
3480 qp_attr->cur_qp_state = qp_attr->qp_state;
3481 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3482 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3483 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3484 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3485 qp_attr->cap.max_inline_data = 0;
3486 qp_init_attr->cap = qp_attr->cap;
3487 qp_init_attr->create_flags = 0;
3488
3489 mutex_unlock(&hr_qp->mutex);
3490
3491 return 0;
3492}
3493
3494static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3495 int qp_attr_mask,
3496 struct ib_qp_init_attr *qp_init_attr)
9a443537 3497{
3498 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3499 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3500 struct device *dev = &hr_dev->pdev->dev;
3501 struct hns_roce_qp_context *context;
3502 int tmp_qp_state = 0;
3503 int ret = 0;
3504 int state;
3505
3506 context = kzalloc(sizeof(*context), GFP_KERNEL);
3507 if (!context)
3508 return -ENOMEM;
3509
3510 memset(qp_attr, 0, sizeof(*qp_attr));
3511 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3512
3513 mutex_lock(&hr_qp->mutex);
3514
3515 if (hr_qp->state == IB_QPS_RESET) {
3516 qp_attr->qp_state = IB_QPS_RESET;
3517 goto done;
3518 }
3519
3520 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3521 if (ret) {
3522 dev_err(dev, "query qpc error\n");
3523 ret = -EINVAL;
3524 goto out;
3525 }
3526
3527 state = roce_get_field(context->qpc_bytes_144,
3528 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3529 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3530 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3531 if (tmp_qp_state == -1) {
3532 dev_err(dev, "to_ib_qp_state error\n");
3533 ret = -EINVAL;
3534 goto out;
3535 }
3536 hr_qp->state = (u8)tmp_qp_state;
3537 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3538 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3539 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3540 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3541 qp_attr->path_mig_state = IB_MIG_ARMED;
2bf910d4 3542 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
9a443537 3543 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3544 qp_attr->qkey = QKEY_VAL;
3545
3546 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3547 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3548 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3549 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3550 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3551 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3552 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3553 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3554 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3555 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3556 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3557 ((roce_get_bit(context->qpc_bytes_4,
3558 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3559 ((roce_get_bit(context->qpc_bytes_4,
3560 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3561
3562 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3563 hr_qp->ibqp.qp_type == IB_QPT_UC) {
d8966fcd
DC		 3564 struct ib_global_route *grh =
3565 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3566
3567 rdma_ah_set_sl(&qp_attr->ah_attr,
3568 roce_get_field(context->qpc_bytes_156,
3569 QP_CONTEXT_QPC_BYTES_156_SL_M,
3570 QP_CONTEXT_QPC_BYTES_156_SL_S));
3571 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3572 grh->flow_label =
3573 roce_get_field(context->qpc_bytes_48,
3574 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3575 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3576 grh->sgid_index =
3577 roce_get_field(context->qpc_bytes_36,
3578 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3579 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3580 grh->hop_limit =
3581 roce_get_field(context->qpc_bytes_44,
3582 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3583 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3584 grh->traffic_class =
3585 roce_get_field(context->qpc_bytes_48,
3586 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3587 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3588
3589 memcpy(grh->dgid.raw, context->dgid,
3590 sizeof(grh->dgid.raw));
9a443537 3591 }
3592
3593 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3594 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3595 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
dd783a21 3596 qp_attr->port_num = hr_qp->port + 1;
9a443537 3597 qp_attr->sq_draining = 0;
be7acd9d 3598 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
9a443537 3599 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3600 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
be7acd9d 3601 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
9a443537 3602 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3603 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3604 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3605 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3606 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3607 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3608 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3609 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3610 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3611 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3612 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
0576cbde 3613 qp_attr->rnr_retry = (u8)context->rnr_retry;
9a443537 3614
3615done:
3616 qp_attr->cur_qp_state = qp_attr->qp_state;
3617 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3618 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3619
3620 if (!ibqp->uobject) {
3621 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3622 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3623 } else {
3624 qp_attr->cap.max_send_wr = 0;
3625 qp_attr->cap.max_send_sge = 0;
3626 }
3627
3628 qp_init_attr->cap = qp_attr->cap;
3629
3630out:
3631 mutex_unlock(&hr_qp->mutex);
3632 kfree(context);
3633 return ret;
3634}
3635
d61d6de0
BVA		 3636static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3637 int qp_attr_mask,
3638 struct ib_qp_init_attr *qp_init_attr)
9eefa953
LO		 3639{
3640 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3641
3642 return hr_qp->doorbell_qpn <= 1 ?
3643 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3644 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3645}
d838c481 3646
f44c863b
LO		 3647static void hns_roce_check_sdb_status(struct hns_roce_dev *hr_dev,
3648 u32 *old_send, u32 *old_retry,
3649 u32 *tsp_st, u32 *success_flags)
3650{
0576cbde 3651 __le32 *old_send_tmp, *old_retry_tmp;
f44c863b
LO		 3652 u32 sdb_retry_cnt;
3653 u32 sdb_send_ptr;
3654 u32 cur_cnt, old_cnt;
0576cbde 3655 __le32 tmp, tmp1;
f44c863b
LO		 3656 u32 send_ptr;
3657
3658 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3659 sdb_retry_cnt = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
0576cbde 3660 tmp = cpu_to_le32(sdb_send_ptr);
3661 tmp1 = cpu_to_le32(sdb_retry_cnt);
3662 cur_cnt = roce_get_field(tmp, ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
f44c863b 3663 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
0576cbde 3664 roce_get_field(tmp1, ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
f44c863b 3665 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
0576cbde 3666
3667 old_send_tmp = (__le32 *)old_send;
3668 old_retry_tmp = (__le32 *)old_retry;
f44c863b 3669 if (!roce_get_bit(*tsp_st, ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
0576cbde 3670 old_cnt = roce_get_field(*old_send_tmp,
f44c863b
LO		 3671 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3672 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
0576cbde 3673 roce_get_field(*old_retry_tmp,
f44c863b
LO		 3674 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3675 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3676 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3677 *success_flags = 1;
3678 } else {
0576cbde 3679 old_cnt = roce_get_field(*old_send_tmp,
f44c863b
LO		 3680 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3681 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3682 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL) {
3683 *success_flags = 1;
3684 } else {
0576cbde 3685 send_ptr = roce_get_field(*old_send_tmp,
f44c863b
LO		 3686 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3687 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
0576cbde 3688 roce_get_field(tmp1,
f44c863b
LO		 3689 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3690 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
0576cbde 3691 roce_set_field(*old_send_tmp,
f44c863b
LO		 3692 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3693 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3694 send_ptr);
3695 }
3696 }
3697}
3698
d838c481
WHX		 3699static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3700 struct hns_roce_qp *hr_qp,
3701 u32 sdb_issue_ptr,
3702 u32 *sdb_inv_cnt,
3703 u32 *wait_stage)
9a443537 3704{
9a443537 3705 struct device *dev = &hr_dev->pdev->dev;
d838c481 3706 u32 sdb_send_ptr, old_send;
0576cbde 3707 __le32 sdb_issue_ptr_tmp;
3708 __le32 sdb_send_ptr_tmp;
d838c481 3709 u32 success_flags = 0;
d838c481 3710 unsigned long end;
f44c863b 3711 u32 old_retry;
d838c481
WHX		 3712 u32 inv_cnt;
3713 u32 tsp_st;
0576cbde 3714 __le32 tmp;
d838c481
WHX		 3715
3716 if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3717 *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3718 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3719 hr_qp->qpn, *wait_stage);
3720 return -EINVAL;
3721 }
9a443537 3722
d838c481
WHX		 3723 /* Calculate the total timeout for the entire verification process */
3724 end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3725
3726 if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3727 /* Query db process status, until hw process completely */
3728 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3729 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3730 ROCEE_SDB_PTR_CMP_BITS)) {
3731 if (!time_before(jiffies, end)) {
3732 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3733 hr_qp->qpn, sdb_issue_ptr,
3734 sdb_send_ptr);
3735 return 0;
3736 }
3737
3738 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3739 sdb_send_ptr = roce_read(hr_dev,
9a443537 3740 ROCEE_SDB_SEND_PTR_REG);
d838c481 3741 }
9a443537 3742
0576cbde 3743 sdb_send_ptr_tmp = cpu_to_le32(sdb_send_ptr);
3744 sdb_issue_ptr_tmp = cpu_to_le32(sdb_issue_ptr);
3745 if (roce_get_field(sdb_issue_ptr_tmp,
d838c481
WHX		 3746 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3747 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
0576cbde 3748 roce_get_field(sdb_send_ptr_tmp,
d838c481
WHX		 3749 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3750 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3751 old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3752 old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
9a443537 3753
9a443537 3754 do {
d838c481 3755 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
0576cbde 3756 tmp = cpu_to_le32(tsp_st);
3757 if (roce_get_bit(tmp,
d838c481
WHX		 3758 ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3759 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3760 return 0;
3761 }
3762
9a443537 3763 if (!time_before(jiffies, end)) {
d838c481
WHX		 3764 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3765 "issue 0x%x send 0x%x.\n",
0576cbde 3766 hr_qp->qpn,
3767 le32_to_cpu(sdb_issue_ptr_tmp),
3768 le32_to_cpu(sdb_send_ptr_tmp));
d838c481 3769 return 0;
9a443537 3770 }
d838c481
WHX		 3771
3772 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3773
f44c863b
LO		 3774 hns_roce_check_sdb_status(hr_dev, &old_send,
3775 &old_retry, &tsp_st,
3776 &success_flags);
d838c481
WHX		 3777 } while (!success_flags);
3778 }
3779
3780 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3781
3782 /* Get list pointer */
3783 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3784 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3785 hr_qp->qpn, *sdb_inv_cnt);
3786 }
3787
3788 if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3789 /* Query db's list status, until hw reversal */
3790 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3791 while (roce_hw_index_cmp_lt(inv_cnt,
3792 *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3793 ROCEE_SDB_CNT_CMP_BITS)) {
3794 if (!time_before(jiffies, end)) {
3795 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3796 hr_qp->qpn, inv_cnt);
3797 return 0;
3798 }
3799
3800 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3801 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
9a443537 3802 }
d838c481
WHX		 3803
3804 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3805 }
3806
3807 return 0;
3808}
3809
3810static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3811 struct hns_roce_qp *hr_qp,
3812 struct hns_roce_qp_work *qp_work_entry,
3813 int *is_timeout)
3814{
3815 struct device *dev = &hr_dev->pdev->dev;
3816 u32 sdb_issue_ptr;
3817 int ret;
3818
3819 if (hr_qp->state != IB_QPS_RESET) {
3820 /* Set qp to ERR, waiting for hw complete processing all dbs */
3821 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3822 IB_QPS_ERR);
3823 if (ret) {
3824 dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3825 hr_qp->qpn);
3826 return ret;
3827 }
3828
3829 /* Record issued doorbell */
3830 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3831 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3832 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3833
3834 /* Query db process status, until hw process completely */
3835 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3836 &qp_work_entry->sdb_inv_cnt,
3837 &qp_work_entry->db_wait_stage);
3838 if (ret) {
3839 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3840 hr_qp->qpn);
3841 return ret;
3842 }
3843
3844 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3845 qp_work_entry->sche_cnt = 0;
3846 *is_timeout = 1;
3847 return 0;
3848 }
3849
3850 /* Modify qp to reset before destroying qp */
3851 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3852 IB_QPS_RESET);
3853 if (ret) {
3854 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3855 hr_qp->qpn);
3856 return ret;
3857 }
3858 }
3859
3860 return 0;
3861}
3862
3863static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3864{
3865 struct hns_roce_qp_work *qp_work_entry;
3866 struct hns_roce_v1_priv *priv;
3867 struct hns_roce_dev *hr_dev;
3868 struct hns_roce_qp *hr_qp;
3869 struct device *dev;
58c4f0d8 3870 unsigned long qpn;
d838c481
WHX		 3871 int ret;
3872
3873 qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3874 hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3875 dev = &hr_dev->pdev->dev;
016a0059 3876 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481 3877 hr_qp = qp_work_entry->qp;
58c4f0d8 3878 qpn = hr_qp->qpn;
d838c481 3879
58c4f0d8 3880 dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", qpn);
d838c481
WHX		 3881
3882 qp_work_entry->sche_cnt++;
3883
3884 /* Query db process status, until hw process completely */
3885 ret = check_qp_db_process_status(hr_dev, hr_qp,
3886 qp_work_entry->sdb_issue_ptr,
3887 &qp_work_entry->sdb_inv_cnt,
3888 &qp_work_entry->db_wait_stage);
3889 if (ret) {
3890 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
58c4f0d8 3891 qpn);
d838c481
WHX		 3892 return;
3893 }
3894
3895 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3896 priv->des_qp.requeue_flag) {
3897 queue_work(priv->des_qp.qp_wq, work);
3898 return;
3899 }
3900
3901 /* Modify qp to reset before destroying qp */
3902 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3903 IB_QPS_RESET);
3904 if (ret) {
58c4f0d8 3905 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", qpn);
d838c481
WHX		 3906 return;
3907 }
3908
3909 hns_roce_qp_remove(hr_dev, hr_qp);
3910 hns_roce_qp_free(hr_dev, hr_qp);
3911
3912 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3913 /* RC QP, release QPN */
58c4f0d8 3914 hns_roce_release_range_qp(hr_dev, qpn, 1);
d838c481
WHX		 3915 kfree(hr_qp);
3916 } else
3917 kfree(hr_to_hr_sqp(hr_qp));
3918
3919 kfree(qp_work_entry);
3920
58c4f0d8 3921 dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", qpn);
d838c481
WHX		 3922}
3923
3924int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3925{
3926 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3927 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3928 struct device *dev = &hr_dev->pdev->dev;
3929 struct hns_roce_qp_work qp_work_entry;
3930 struct hns_roce_qp_work *qp_work;
3931 struct hns_roce_v1_priv *priv;
3932 struct hns_roce_cq *send_cq, *recv_cq;
e00b64f7 3933 bool is_user = ibqp->uobject;
d838c481
WHX		 3934 int is_timeout = 0;
3935 int ret;
3936
3937 ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3938 if (ret) {
3939 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3940 return ret;
9a443537 3941 }
3942
3943 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3944 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3945
3946 hns_roce_lock_cqs(send_cq, recv_cq);
9a443537 3947 if (!is_user) {
3948 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3949 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3950 if (send_cq != recv_cq)
3951 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3952 }
9a443537 3953 hns_roce_unlock_cqs(send_cq, recv_cq);
3954
d838c481
WHX		 3955 if (!is_timeout) {
3956 hns_roce_qp_remove(hr_dev, hr_qp);
3957 hns_roce_qp_free(hr_dev, hr_qp);
9a443537 3958
d838c481
WHX		 3959 /* RC QP, release QPN */
3960 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3961 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3962 }
9a443537 3963
3964 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3965
d838c481 3966 if (is_user)
9a443537 3967 ib_umem_release(hr_qp->umem);
d838c481 3968 else {
9a443537 3969 kfree(hr_qp->sq.wrid);
3970 kfree(hr_qp->rq.wrid);
d838c481 3971
9a443537 3972 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3973 }
9a443537 3974
d838c481
WHX		 3975 if (!is_timeout) {
3976 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3977 kfree(hr_qp);
3978 else
3979 kfree(hr_to_hr_sqp(hr_qp));
3980 } else {
3981 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3982 if (!qp_work)
3983 return -ENOMEM;
3984
3985 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3986 qp_work->ib_dev = &hr_dev->ib_dev;
3987 qp_work->qp = hr_qp;
3988 qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3989 qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3990 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3991 qp_work->sche_cnt = qp_work_entry.sche_cnt;
3992
016a0059 3993 priv = (struct hns_roce_v1_priv *)hr_dev->priv;
d838c481
WHX		 3994 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3995 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3996 }
9a443537 3997
3998 return 0;
3999}
4000
d61d6de0 4001static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
afb6b092
SX		 4002{
4003 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
4004 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
4005 struct device *dev = &hr_dev->pdev->dev;
4006 u32 cqe_cnt_ori;
4007 u32 cqe_cnt_cur;
4008 u32 cq_buf_size;
4009 int wait_time = 0;
4010 int ret = 0;
4011
4012 hns_roce_free_cq(hr_dev, hr_cq);
4013
4014 /*
4015 * Before freeing cq buffer, we need to ensure that the outstanding CQE
4016 * have been written by checking the CQE counter.
4017 */
4018 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4019 while (1) {
4020 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
4021 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
4022 break;
4023
4024 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
4025 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
4026 break;
4027
4028 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
4029 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
4030 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
4031 hr_cq->cqn);
4032 ret = -ETIMEDOUT;
4033 break;
4034 }
4035 wait_time++;
4036 }
4037
4038 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
4039
4040 if (ibcq->uobject)
4041 ib_umem_release(hr_cq->umem);
4042 else {
4043 /* Free the buff of stored cq */
4044 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
4045 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
4046 }
4047
4048 kfree(hr_cq);
4049
4050 return ret;
4051}
4052
b16f8188
YL		 4053static void set_eq_cons_index_v1(struct hns_roce_eq *eq, int req_not)
4054{
4055 roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
4056 (req_not << eq->log_entries), eq->doorbell);
b16f8188
YL		 4057}
4058
4059static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
4060 struct hns_roce_aeqe *aeqe, int qpn)
4061{
4062 struct device *dev = &hr_dev->pdev->dev;
4063
4064 dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
4065 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4066 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4067 case HNS_ROCE_LWQCE_QPC_ERROR:
4068 dev_warn(dev, "QP %d, QPC error.\n", qpn);
4069 break;
4070 case HNS_ROCE_LWQCE_MTU_ERROR:
4071 dev_warn(dev, "QP %d, MTU error.\n", qpn);
4072 break;
4073 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
4074 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
4075 break;
4076 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
4077 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
4078 break;
4079 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
4080 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
4081 break;
4082 case HNS_ROCE_LWQCE_SL_ERROR:
4083 dev_warn(dev, "QP %d, SL error.\n", qpn);
4084 break;
4085 case HNS_ROCE_LWQCE_PORT_ERROR:
4086 dev_warn(dev, "QP %d, port error.\n", qpn);
4087 break;
4088 default:
4089 break;
4090 }
4091}
4092
4093static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
4094 struct hns_roce_aeqe *aeqe,
4095 int qpn)
4096{
4097 struct device *dev = &hr_dev->pdev->dev;
4098
4099 dev_warn(dev, "Local Access Violation Work Queue Error.\n");
4100 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4101 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4102 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
4103 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
4104 break;
4105 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
4106 dev_warn(dev, "QP %d, length error.\n", qpn);
4107 break;
4108 case HNS_ROCE_LAVWQE_VA_ERROR:
4109 dev_warn(dev, "QP %d, VA error.\n", qpn);
4110 break;
4111 case HNS_ROCE_LAVWQE_PD_ERROR:
4112 dev_err(dev, "QP %d, PD error.\n", qpn);
4113 break;
4114 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
4115 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
4116 break;
4117 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
4118 dev_warn(dev, "QP %d, key state error.\n", qpn);
4119 break;
4120 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
4121 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
4122 break;
4123 default:
4124 break;
4125 }
4126}
4127
4128static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
4129 struct hns_roce_aeqe *aeqe,
4130 int event_type)
4131{
4132 struct device *dev = &hr_dev->pdev->dev;
4133 int phy_port;
4134 int qpn;
4135
4136 qpn = roce_get_field(aeqe->event.qp_event.qp,
4137 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
4138 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
4139 phy_port = roce_get_field(aeqe->event.qp_event.qp,
4140 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
4141 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
4142 if (qpn <= 1)
4143 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
4144
4145 switch (event_type) {
4146 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4147 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
4148 "QP %d, phy_port %d.\n", qpn, phy_port);
4149 break;
4150 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4151 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
4152 break;
4153 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4154 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
4155 break;
4156 default:
4157 break;
4158 }
4159
4160 hns_roce_qp_event(hr_dev, qpn, event_type);
4161}
4162
4163static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
4164 struct hns_roce_aeqe *aeqe,
4165 int event_type)
4166{
4167 struct device *dev = &hr_dev->pdev->dev;
4168 u32 cqn;
4169
0576cbde 4170 cqn = roce_get_field(aeqe->event.cq_event.cq,
b16f8188 4171 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
0576cbde 4172 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
b16f8188
YL		 4173
4174 switch (event_type) {
4175 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4176 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
4177 break;
4178 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4179 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
4180 break;
4181 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4182 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
4183 break;
4184 default:
4185 break;
4186 }
4187
4188 hns_roce_cq_event(hr_dev, cqn, event_type);
4189}
4190
4191static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
4192 struct hns_roce_aeqe *aeqe)
4193{
4194 struct device *dev = &hr_dev->pdev->dev;
4195
4196 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
4197 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
4198 case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
4199 dev_warn(dev, "SDB overflow.\n");
4200 break;
4201 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
4202 dev_warn(dev, "SDB almost overflow.\n");
4203 break;
4204 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
4205 dev_warn(dev, "SDB almost empty.\n");
4206 break;
4207 case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
4208 dev_warn(dev, "ODB overflow.\n");
4209 break;
4210 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
4211 dev_warn(dev, "ODB almost overflow.\n");
4212 break;
4213 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
4214 dev_warn(dev, "SDB almost empty.\n");
4215 break;
4216 default:
4217 break;
4218 }
4219}
4220
4221static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
4222{
4223 unsigned long off = (entry & (eq->entries - 1)) *
4224 HNS_ROCE_AEQ_ENTRY_SIZE;
4225
4226 return (struct hns_roce_aeqe *)((u8 *)
4227 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4228 off % HNS_ROCE_BA_SIZE);
4229}
4230
4231static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
4232{
4233 struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
4234
4235 return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
4236 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
4237}
4238
4239static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
4240 struct hns_roce_eq *eq)
4241{
4242 struct device *dev = &hr_dev->pdev->dev;
4243 struct hns_roce_aeqe *aeqe;
4244 int aeqes_found = 0;
4245 int event_type;
4246
4247 while ((aeqe = next_aeqe_sw_v1(eq))) {
4044a3f4
YL		 4248
4249 /* Make sure we read the AEQ entry after we have checked the
4250 * ownership bit
4251 */
4252 dma_rmb();
4253
b16f8188
YL		 4254 dev_dbg(dev, "aeqe = %p, aeqe->asyn.event_type = 0x%lx\n", aeqe,
4255 roce_get_field(aeqe->asyn,
4256 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4257 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
b16f8188
YL		 4258 event_type = roce_get_field(aeqe->asyn,
4259 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
4260 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
4261 switch (event_type) {
4262 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
4263 dev_warn(dev, "PATH MIG not supported\n");
4264 break;
4265 case HNS_ROCE_EVENT_TYPE_COMM_EST:
4266 dev_warn(dev, "COMMUNICATION established\n");
4267 break;
4268 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
4269 dev_warn(dev, "SQ DRAINED not supported\n");
4270 break;
4271 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
4272 dev_warn(dev, "PATH MIG failed\n");
4273 break;
4274 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
4275 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
4276 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
4277 hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
4278 break;
4279 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
4280 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
4281 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
4282 dev_warn(dev, "SRQ not support!\n");
4283 break;
4284 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
4285 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
4286 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
4287 hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
4288 break;
4289 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
4290 dev_warn(dev, "port change.\n");
4291 break;
4292 case HNS_ROCE_EVENT_TYPE_MB:
4293 hns_roce_cmd_event(hr_dev,
4294 le16_to_cpu(aeqe->event.cmd.token),
4295 aeqe->event.cmd.status,
4296 le64_to_cpu(aeqe->event.cmd.out_param
4297 ));
4298 break;
4299 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
4300 hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
4301 break;
4302 case HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW:
4303 dev_warn(dev, "CEQ 0x%lx overflow.\n",
4304 roce_get_field(aeqe->event.ce_event.ceqe,
4305 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M,
4306 HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S));
4307 break;
4308 default:
4309 dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
4310 event_type, eq->eqn, eq->cons_index);
4311 break;
4312 }
4313
4314 eq->cons_index++;
4315 aeqes_found = 1;
4316
4317 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1) {
4318 dev_warn(dev, "cons_index overflow, set back to 0.\n");
4319 eq->cons_index = 0;
4320 }
4321 }
4322
4323 set_eq_cons_index_v1(eq, 0);
4324
4325 return aeqes_found;
4326}
4327
4328static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
4329{
4330 unsigned long off = (entry & (eq->entries - 1)) *
4331 HNS_ROCE_CEQ_ENTRY_SIZE;
4332
4333 return (struct hns_roce_ceqe *)((u8 *)
4334 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
4335 off % HNS_ROCE_BA_SIZE);
4336}
4337
4338static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
4339{
4340 struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
4341
4342 return (!!(roce_get_bit(ceqe->comp,
4343 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
4344 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
4345}
4346
4347static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
4348 struct hns_roce_eq *eq)
4349{
4350 struct hns_roce_ceqe *ceqe;
4351 int ceqes_found = 0;
4352 u32 cqn;
4353
4354 while ((ceqe = next_ceqe_sw_v1(eq))) {
4044a3f4
YL		 4355
4356 /* Make sure we read CEQ entry after we have checked the
4357 * ownership bit
4358 */
4359 dma_rmb();
4360
b16f8188
YL		 4361 cqn = roce_get_field(ceqe->comp,
4362 HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
4363 HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
4364 hns_roce_cq_completion(hr_dev, cqn);
4365
4366 ++eq->cons_index;
4367 ceqes_found = 1;
4368
4369 if (eq->cons_index > 2 * hr_dev->caps.ceqe_depth - 1) {
4370 dev_warn(&eq->hr_dev->pdev->dev,
4371 "cons_index overflow, set back to 0.\n");
4372 eq->cons_index = 0;
4373 }
4374 }
4375
4376 set_eq_cons_index_v1(eq, 0);
4377
4378 return ceqes_found;
4379}
4380
4381static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
4382{
4383 struct hns_roce_eq *eq = eq_ptr;
4384 struct hns_roce_dev *hr_dev = eq->hr_dev;
4385 int int_work = 0;
4386
4387 if (eq->type_flag == HNS_ROCE_CEQ)
4388 /* CEQ irq routine, CEQ is pulse irq, not clear */
4389 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
4390 else
4391 /* AEQ irq routine, AEQ is pulse irq, not clear */
4392 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4393
4394 return IRQ_RETVAL(int_work);
4395}
4396
4397static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4398{
4399 struct hns_roce_dev *hr_dev = dev_id;
4400 struct device *dev = &hr_dev->pdev->dev;
4401 int int_work = 0;
4402 u32 caepaemask_val;
4403 u32 cealmovf_val;
4404 u32 caepaest_val;
4405 u32 aeshift_val;
4406 u32 ceshift_val;
4407 u32 cemask_val;
0576cbde 4408 __le32 tmp;
b16f8188
YL		 4409 int i;
4410
4411 /*
4412 * Abnormal interrupt:
4413 * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4414 * interrupt, mask irq, clear irq, cancel mask operation
4415 */
4416 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
0576cbde 4417 tmp = cpu_to_le32(aeshift_val);
b16f8188
YL		 4418
4419 /* AEQE overflow */
0576cbde 4420 if (roce_get_bit(tmp,
b16f8188
YL		 4421 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4422 dev_warn(dev, "AEQ overflow!\n");
4423
4424 /* Set mask */
4425 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
0576cbde 4426 tmp = cpu_to_le32(caepaemask_val);
4427 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
b16f8188 4428 HNS_ROCE_INT_MASK_ENABLE);
0576cbde 4429 caepaemask_val = le32_to_cpu(tmp);
b16f8188
YL		 4430 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4431
4432 /* Clear int state(INT_WC : write 1 clear) */
4433 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
0576cbde 4434 tmp = cpu_to_le32(caepaest_val);
4435 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4436 caepaest_val = le32_to_cpu(tmp);
b16f8188
YL		 4437 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4438
4439 /* Clear mask */
4440 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
0576cbde 4441 tmp = cpu_to_le32(caepaemask_val);
4442 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
b16f8188 4443 HNS_ROCE_INT_MASK_DISABLE);
0576cbde 4444 caepaemask_val = le32_to_cpu(tmp);
b16f8188
YL		 4445 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4446 }
4447
4448 /* CEQ almost overflow */
4449 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4450 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4451 i * CEQ_REG_OFFSET);
0576cbde 4452 tmp = cpu_to_le32(ceshift_val);
b16f8188 4453
0576cbde 4454 if (roce_get_bit(tmp,
b16f8188
YL		 4455 ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4456 dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4457 int_work++;
4458
4459 /* Set mask */
4460 cemask_val = roce_read(hr_dev,
4461 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4462 i * CEQ_REG_OFFSET);
0576cbde 4463 tmp = cpu_to_le32(cemask_val);
4464 roce_set_bit(tmp,
b16f8188
YL		 4465 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4466 HNS_ROCE_INT_MASK_ENABLE);
0576cbde 4467 cemask_val = le32_to_cpu(tmp);
b16f8188
YL		 4468 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4469 i * CEQ_REG_OFFSET, cemask_val);
4470
4471 /* Clear int state(INT_WC : write 1 clear) */
4472 cealmovf_val = roce_read(hr_dev,
4473 ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4474 i * CEQ_REG_OFFSET);
0576cbde 4475 tmp = cpu_to_le32(cealmovf_val);
4476 roce_set_bit(tmp,
b16f8188
YL		 4477 ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4478 1);
0576cbde 4479 cealmovf_val = le32_to_cpu(tmp);
b16f8188
YL		 4480 roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4481 i * CEQ_REG_OFFSET, cealmovf_val);
4482
4483 /* Clear mask */
4484 cemask_val = roce_read(hr_dev,
4485 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4486 i * CEQ_REG_OFFSET);
0576cbde 4487 tmp = cpu_to_le32(cemask_val);
4488 roce_set_bit(tmp,
b16f8188
YL		 4489 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4490 HNS_ROCE_INT_MASK_DISABLE);
0576cbde 4491 cemask_val = le32_to_cpu(tmp);
b16f8188
YL		 4492 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4493 i * CEQ_REG_OFFSET, cemask_val);
4494 }
4495 }
4496
4497 /* ECC multi-bit error alarm */
4498 dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4499 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4500 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4501 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4502
4503 dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4504 roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4505 roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4506 roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4507
4508 return IRQ_RETVAL(int_work);
4509}
4510
4511static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4512{
4513 u32 aemask_val;
4514 int masken = 0;
0576cbde 4515 __le32 tmp;
b16f8188
YL		 4516 int i;
4517
4518 /* AEQ INT */
4519 aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
0576cbde 4520 tmp = cpu_to_le32(aemask_val);
4521 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
b16f8188 4522 masken);
0576cbde 4523 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4524 aemask_val = le32_to_cpu(tmp);
b16f8188
YL		 4525 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4526
4527 /* CEQ INT */
4528 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4529 /* IRQ mask */
4530 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4531 i * CEQ_REG_OFFSET, masken);
4532 }
4533}
4534
4535static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4536 struct hns_roce_eq *eq)
4537{
4538 int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4539 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4540 int i;
4541
4542 if (!eq->buf_list)
4543 return;
4544
4545 for (i = 0; i < npages; ++i)
4546 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4547 eq->buf_list[i].buf, eq->buf_list[i].map);
4548
4549 kfree(eq->buf_list);
4550}
4551
4552static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4553 int enable_flag)
4554{
4555 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
0576cbde 4556 __le32 tmp;
b16f8188
YL		 4557 u32 val;
4558
4559 val = readl(eqc);
0576cbde 4560 tmp = cpu_to_le32(val);
b16f8188
YL		 4561
4562 if (enable_flag)
0576cbde 4563 roce_set_field(tmp,
b16f8188
YL		 4564 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4565 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4566 HNS_ROCE_EQ_STAT_VALID);
4567 else
0576cbde 4568 roce_set_field(tmp,
b16f8188
YL		 4569 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4570 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4571 HNS_ROCE_EQ_STAT_INVALID);
0576cbde 4572
4573 val = le32_to_cpu(tmp);
b16f8188
YL		 4574 writel(val, eqc);
4575}
4576
4577static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4578 struct hns_roce_eq *eq)
4579{
4580 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4581 struct device *dev = &hr_dev->pdev->dev;
4582 dma_addr_t tmp_dma_addr;
4583 u32 eqconsindx_val = 0;
4584 u32 eqcuridx_val = 0;
4585 u32 eqshift_val = 0;
0576cbde 4586 __le32 tmp2 = 0;
4587 __le32 tmp1 = 0;
4588 __le32 tmp = 0;
b16f8188
YL		 4589 int num_bas;
4590 int ret;
4591 int i;
4592
4593 num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4594 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4595
4596 if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4597 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4598 (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4599 num_bas);
4600 return -EINVAL;
4601 }
4602
4603 eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4604 if (!eq->buf_list)
4605 return -ENOMEM;
4606
4607 for (i = 0; i < num_bas; ++i) {
4608 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4609 &tmp_dma_addr,
4610 GFP_KERNEL);
4611 if (!eq->buf_list[i].buf) {
4612 ret = -ENOMEM;
4613 goto err_out_free_pages;
4614 }
4615
4616 eq->buf_list[i].map = tmp_dma_addr;
4617 memset(eq->buf_list[i].buf, 0, HNS_ROCE_BA_SIZE);
4618 }
4619 eq->cons_index = 0;
0576cbde 4620 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
b16f8188
YL		 4621 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4622 HNS_ROCE_EQ_STAT_INVALID);
0576cbde 4623 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
b16f8188
YL		 4624 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4625 eq->log_entries);
0576cbde 4626 eqshift_val = le32_to_cpu(tmp);
b16f8188
YL		 4627 writel(eqshift_val, eqc);
4628
4629 /* Configure eq extended address 12~44bit */
4630 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4631
4632 /*
4633 * Configure eq extended address 45~49 bit.
4634 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4635 * using 4K page, and shift more 32 because of
4636 * caculating the high 32 bit value evaluated to hardware.
4637 */
0576cbde 4638 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
b16f8188
YL		 4639 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4640 eq->buf_list[0].map >> 44);
0576cbde 4641 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
b16f8188 4642 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
0576cbde 4643 eqcuridx_val = le32_to_cpu(tmp1);
b16f8188
YL		 4644 writel(eqcuridx_val, eqc + 8);
4645
4646 /* Configure eq consumer index */
0576cbde 4647 roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
b16f8188 4648 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
0576cbde 4649 eqconsindx_val = le32_to_cpu(tmp2);
b16f8188
YL		 4650 writel(eqconsindx_val, eqc + 0xc);
4651
4652 return 0;
4653
4654err_out_free_pages:
4655 for (i -= 1; i >= 0; i--)
4656 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4657 eq->buf_list[i].map);
4658
4659 kfree(eq->buf_list);
4660 return ret;
4661}
4662
4663static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4664{
4665 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4666 struct device *dev = &hr_dev->pdev->dev;
4667 struct hns_roce_eq *eq;
4668 int irq_num;
4669 int eq_num;
4670 int ret;
4671 int i, j;
4672
4673 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4674 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4675
4676 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4677 if (!eq_table->eq)
4678 return -ENOMEM;
4679
4680 eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4681 GFP_KERNEL);
4682 if (!eq_table->eqc_base) {
4683 ret = -ENOMEM;
4684 goto err_eqc_base_alloc_fail;
4685 }
4686
4687 for (i = 0; i < eq_num; i++) {
4688 eq = &eq_table->eq[i];
4689 eq->hr_dev = hr_dev;
4690 eq->eqn = i;
4691 eq->irq = hr_dev->irq[i];
4692 eq->log_page_size = PAGE_SHIFT;
4693
4694 if (i < hr_dev->caps.num_comp_vectors) {
4695 /* CEQ */
4696 eq_table->eqc_base[i] = hr_dev->reg_base +
4697 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4698 CEQ_REG_OFFSET * i;
4699 eq->type_flag = HNS_ROCE_CEQ;
4700 eq->doorbell = hr_dev->reg_base +
4701 ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4702 CEQ_REG_OFFSET * i;
4703 eq->entries = hr_dev->caps.ceqe_depth;
4704 eq->log_entries = ilog2(eq->entries);
4705 eq->eqe_size = HNS_ROCE_CEQ_ENTRY_SIZE;
4706 } else {
4707 /* AEQ */
4708 eq_table->eqc_base[i] = hr_dev->reg_base +
4709 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4710 eq->type_flag = HNS_ROCE_AEQ;
4711 eq->doorbell = hr_dev->reg_base +
4712 ROCEE_CAEP_AEQE_CONS_IDX_REG;
4713 eq->entries = hr_dev->caps.aeqe_depth;
4714 eq->log_entries = ilog2(eq->entries);
4715 eq->eqe_size = HNS_ROCE_AEQ_ENTRY_SIZE;
4716 }
4717 }
4718
4719 /* Disable irq */
4720 hns_roce_v1_int_mask_enable(hr_dev);
4721
4722 /* Configure ce int interval */
4723 roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4724 HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4725
4726 /* Configure ce int burst num */
4727 roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4728 HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4729
4730 for (i = 0; i < eq_num; i++) {
4731 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4732 if (ret) {
4733 dev_err(dev, "eq create failed\n");
4734 goto err_create_eq_fail;
4735 }
4736 }
4737
4738 for (j = 0; j < irq_num; j++) {
4739 if (j < eq_num)
4740 ret = request_irq(hr_dev->irq[j],
4741 hns_roce_v1_msix_interrupt_eq, 0,
4742 hr_dev->irq_names[j],
4743 &eq_table->eq[j]);
4744 else
4745 ret = request_irq(hr_dev->irq[j],
4746 hns_roce_v1_msix_interrupt_abn, 0,
4747 hr_dev->irq_names[j], hr_dev);
4748
4749 if (ret) {
4750 dev_err(dev, "request irq error!\n");
4751 goto err_request_irq_fail;
4752 }
4753 }
4754
4755 for (i = 0; i < eq_num; i++)
4756 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4757
4758 return 0;
4759
4760err_request_irq_fail:
4761 for (j -= 1; j >= 0; j--)
4762 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4763
4764err_create_eq_fail:
4765 for (i -= 1; i >= 0; i--)
4766 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4767
4768 kfree(eq_table->eqc_base);
4769
4770err_eqc_base_alloc_fail:
4771 kfree(eq_table->eq);
4772
4773 return ret;
4774}
4775
4776static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4777{
4778 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4779 int irq_num;
4780 int eq_num;
4781 int i;
4782
4783 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4784 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4785 for (i = 0; i < eq_num; i++) {
4786 /* Disable EQ */
4787 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4788
4789 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4790
4791 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4792 }
4793 for (i = eq_num; i < irq_num; i++)
4794 free_irq(hr_dev->irq[i], hr_dev);
4795
4796 kfree(eq_table->eqc_base);
4797 kfree(eq_table->eq);
4798}
4799
7f645a58
KH		 4800static const struct ib_device_ops hns_roce_v1_dev_ops = {
4801 .destroy_qp = hns_roce_v1_destroy_qp,
4802 .modify_cq = hns_roce_v1_modify_cq,
4803 .poll_cq = hns_roce_v1_poll_cq,
4804 .post_recv = hns_roce_v1_post_recv,
4805 .post_send = hns_roce_v1_post_send,
4806 .query_qp = hns_roce_v1_query_qp,
4807 .req_notify_cq = hns_roce_v1_req_notify_cq,
4808};
4809
08805fdb 4810static const struct hns_roce_hw hns_roce_hw_v1 = {
9a443537 4811 .reset = hns_roce_v1_reset,
4812 .hw_profile = hns_roce_v1_profile,
4813 .hw_init = hns_roce_v1_init,
4814 .hw_exit = hns_roce_v1_exit,
a680f2f3
WHX		 4815 .post_mbox = hns_roce_v1_post_mbox,
4816 .chk_mbox = hns_roce_v1_chk_mbox,
9a443537 4817 .set_gid = hns_roce_v1_set_gid,
4818 .set_mac = hns_roce_v1_set_mac,
4819 .set_mtu = hns_roce_v1_set_mtu,
4820 .write_mtpt = hns_roce_v1_write_mtpt,
4821 .write_cqc = hns_roce_v1_write_cqc,
b156269d 4822 .modify_cq = hns_roce_v1_modify_cq,
97f0e39f 4823 .clear_hem = hns_roce_v1_clear_hem,
9a443537 4824 .modify_qp = hns_roce_v1_modify_qp,
4825 .query_qp = hns_roce_v1_query_qp,
4826 .destroy_qp = hns_roce_v1_destroy_qp,
4827 .post_send = hns_roce_v1_post_send,
4828 .post_recv = hns_roce_v1_post_recv,
4829 .req_notify_cq = hns_roce_v1_req_notify_cq,
4830 .poll_cq = hns_roce_v1_poll_cq,
bfcc681b 4831 .dereg_mr = hns_roce_v1_dereg_mr,
afb6b092 4832 .destroy_cq = hns_roce_v1_destroy_cq,
b16f8188
YL		 4833 .init_eq = hns_roce_v1_init_eq_table,
4834 .cleanup_eq = hns_roce_v1_cleanup_eq_table,
7f645a58 4835 .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
9a443537 4836};
08805fdb
WHX		 4837
4838static const struct of_device_id hns_roce_of_match[] = {
4839 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4840 {},
4841};
4842MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4843
4844static const struct acpi_device_id hns_roce_acpi_match[] = {
4845 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4846 {},
4847};
4848MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4849
4850static int hns_roce_node_match(struct device *dev, void *fwnode)
4851{
4852 return dev->fwnode == fwnode;
4853}
4854
4855static struct
4856platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4857{
4858 struct device *dev;
4859
4860 /* get the 'device' corresponding to the matching 'fwnode' */
4861 dev = bus_find_device(&platform_bus_type, NULL,
4862 fwnode, hns_roce_node_match);
4863 /* get the platform device */
4864 return dev ? to_platform_device(dev) : NULL;
4865}
4866
4867static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4868{
4869 struct device *dev = &hr_dev->pdev->dev;
4870 struct platform_device *pdev = NULL;
4871 struct net_device *netdev = NULL;
4872 struct device_node *net_node;
4873 struct resource *res;
4874 int port_cnt = 0;
4875 u8 phy_port;
4876 int ret;
4877 int i;
4878
4879 /* check if we are compatible with the underlying SoC */
4880 if (dev_of_node(dev)) {
4881 const struct of_device_id *of_id;
4882
4883 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4884 if (!of_id) {
4885 dev_err(dev, "device is not compatible!\n");
4886 return -ENXIO;
4887 }
4888 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4889 if (!hr_dev->hw) {
4890 dev_err(dev, "couldn't get H/W specific DT data!\n");
4891 return -ENXIO;
4892 }
4893 } else if (is_acpi_device_node(dev->fwnode)) {
4894 const struct acpi_device_id *acpi_id;
4895
4896 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4897 if (!acpi_id) {
4898 dev_err(dev, "device is not compatible!\n");
4899 return -ENXIO;
4900 }
4901 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4902 if (!hr_dev->hw) {
4903 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4904 return -ENXIO;
4905 }
4906 } else {
4907 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4908 return -ENXIO;
4909 }
4910
4911 /* get the mapped register base address */
4912 res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
08805fdb
WHX		 4913 hr_dev->reg_base = devm_ioremap_resource(dev, res);
4914 if (IS_ERR(hr_dev->reg_base))
4915 return PTR_ERR(hr_dev->reg_base);
4916
4917 /* read the node_guid of IB device from the DT or ACPI */
4918 ret = device_property_read_u8_array(dev, "node-guid",
4919 (u8 *)&hr_dev->ib_dev.node_guid,
4920 GUID_LEN);
4921 if (ret) {
4922 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4923 return ret;
4924 }
4925
4926 /* get the RoCE associated ethernet ports or netdevices */
4927 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4928 if (dev_of_node(dev)) {
4929 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4930 i);
4931 if (!net_node)
4932 continue;
4933 pdev = of_find_device_by_node(net_node);
4934 } else if (is_acpi_device_node(dev->fwnode)) {
977d5ad3 4935 struct fwnode_reference_args args;
08805fdb
WHX		 4936
4937 ret = acpi_node_get_property_reference(dev->fwnode,
4938 "eth-handle",
4939 i, &args);
4940 if (ret)
4941 continue;
977d5ad3 4942 pdev = hns_roce_find_pdev(args.fwnode);
08805fdb
WHX		 4943 } else {
4944 dev_err(dev, "cannot read data from DT or ACPI\n");
4945 return -ENXIO;
4946 }
4947
4948 if (pdev) {
4949 netdev = platform_get_drvdata(pdev);
4950 phy_port = (u8)i;
4951 if (netdev) {
4952 hr_dev->iboe.netdevs[port_cnt] = netdev;
4953 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4954 } else {
4955 dev_err(dev, "no netdev found with pdev %s\n",
4956 pdev->name);
4957 return -ENODEV;
4958 }
4959 port_cnt++;
4960 }
4961 }
4962
4963 if (port_cnt == 0) {
4964 dev_err(dev, "unable to get eth-handle for available ports!\n");
4965 return -EINVAL;
4966 }
4967
4968 hr_dev->caps.num_ports = port_cnt;
4969
4970 /* cmd issue mode: 0 is poll, 1 is event */
4971 hr_dev->cmd_mod = 1;
4972 hr_dev->loop_idc = 0;
2d407888
WHX		 4973 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4974 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
08805fdb
WHX		 4975
4976 /* read the interrupt names from the DT or ACPI */
4977 ret = device_property_read_string_array(dev, "interrupt-names",
4978 hr_dev->irq_names,
b16f8188 4979 HNS_ROCE_V1_MAX_IRQ_NUM);
08805fdb
WHX		 4980 if (ret < 0) {
4981 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4982 return ret;
4983 }
4984
4985 /* fetch the interrupt numbers */
b16f8188 4986 for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
08805fdb
WHX		 4987 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4988 if (hr_dev->irq[i] <= 0) {
4989 dev_err(dev, "platform get of irq[=%d] failed!\n", i);
4990 return -EINVAL;
4991 }
4992 }
4993
4994 return 0;
4995}
4996
4997/**
4998 * hns_roce_probe - RoCE driver entrance
4999 * @pdev: pointer to platform device
5000 * Return : int
5001 *
5002 */
5003static int hns_roce_probe(struct platform_device *pdev)
5004{
5005 int ret;
5006 struct hns_roce_dev *hr_dev;
5007 struct device *dev = &pdev->dev;
5008
459cc69f 5009 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
08805fdb
WHX		 5010 if (!hr_dev)
5011 return -ENOMEM;
5012
016a0059
WHX		 5013 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
5014 if (!hr_dev->priv) {
5015 ret = -ENOMEM;
5016 goto error_failed_kzalloc;
5017 }
5018
08805fdb 5019 hr_dev->pdev = pdev;
13ca970e 5020 hr_dev->dev = dev;
08805fdb
WHX		 5021 platform_set_drvdata(pdev, hr_dev);
5022
5023 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
5024 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
5025 dev_err(dev, "Not usable DMA addressing mode\n");
5026 ret = -EIO;
5027 goto error_failed_get_cfg;
5028 }
5029
5030 ret = hns_roce_get_cfg(hr_dev);
5031 if (ret) {
5032 dev_err(dev, "Get Configuration failed!\n");
5033 goto error_failed_get_cfg;
5034 }
5035
5036 ret = hns_roce_init(hr_dev);
5037 if (ret) {
5038 dev_err(dev, "RoCE engine init failed!\n");
5039 goto error_failed_get_cfg;
5040 }
5041
5042 return 0;
5043
5044error_failed_get_cfg:
016a0059
WHX		 5045 kfree(hr_dev->priv);
5046
5047error_failed_kzalloc:
08805fdb
WHX		 5048 ib_dealloc_device(&hr_dev->ib_dev);
5049
5050 return ret;
5051}
5052
5053/**
5054 * hns_roce_remove - remove RoCE device
5055 * @pdev: pointer to platform device
5056 */
5057static int hns_roce_remove(struct platform_device *pdev)
5058{
5059 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
5060
5061 hns_roce_exit(hr_dev);
016a0059 5062 kfree(hr_dev->priv);
08805fdb
WHX		 5063 ib_dealloc_device(&hr_dev->ib_dev);
5064
5065 return 0;
5066}
5067
5068static struct platform_driver hns_roce_driver = {
5069 .probe = hns_roce_probe,
5070 .remove = hns_roce_remove,
5071 .driver = {
5072 .name = DRV_NAME,
5073 .of_match_table = hns_roce_of_match,
5074 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
5075 },
5076};
5077
5078module_platform_driver(hns_roce_driver);
5079
5080MODULE_LICENSE("Dual BSD/GPL");
5081MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
5082MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
5083MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
5084MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
Linux 6.x block layer and io_uring tree(s)